From: "Jeff Brasen" <jbrasen@nvidia.com>
To: <devel@edk2.groups.io>
Cc: <Pierre.Gondois@arm.com>, <Sami.Mujawar@arm.com>,
<Alexei.Fedorov@arm.com>, Jeff Brasen <jbrasen@nvidia.com>
Subject: [PATCH v2 1/4] DynamicTablesPkg: AcpiSsdtPcieLibArm: Correct translation value
Date: Fri, 1 Jul 2022 10:32:34 -0600 [thread overview]
Message-ID: <d0c279bb8706bdcd78deebab616b6329daa93f0f.1656693003.git.jbrasen@nvidia.com> (raw)
In-Reply-To: <cover.1656693003.git.jbrasen@nvidia.com>
The translation value in ACPI should be the difference between the CPU and PCIe address.
Signed-off-by: Jeff Brasen <jbrasen@nvidia.com>
---
.../Arm/AcpiSsdtPcieLibArm/SsdtPcieGenerator.c | 18 ++++++++++++------
1 file changed, 12 insertions(+), 6 deletions(-)
diff --git a/DynamicTablesPkg/Library/Acpi/Arm/AcpiSsdtPcieLibArm/SsdtPcieGenerator.c b/DynamicTablesPkg/Library/Acpi/Arm/AcpiSsdtPcieLibArm/SsdtPcieGenerator.c
index a34018151f..d4c5f47b07 100644
--- a/DynamicTablesPkg/Library/Acpi/Arm/AcpiSsdtPcieLibArm/SsdtPcieGenerator.c
+++ b/DynamicTablesPkg/Library/Acpi/Arm/AcpiSsdtPcieLibArm/SsdtPcieGenerator.c
@@ -540,6 +540,7 @@ GeneratePciCrs (
UINT32 RefCount;
CM_ARM_PCI_ADDRESS_MAP_INFO *AddrMapInfo;
AML_OBJECT_NODE_HANDLE CrsNode;
+ BOOLEAN IsPosDecode;
ASSERT (Generator != NULL);
ASSERT (CfgMgrProtocol != NULL);
@@ -609,6 +610,11 @@ GeneratePciCrs (
}
Translation = (AddrMapInfo->CpuAddress != AddrMapInfo->PciAddress);
+ if (AddrMapInfo->CpuAddress >= AddrMapInfo->PciAddress) {
+ IsPosDecode = TRUE;
+ } else {
+ IsPosDecode = FALSE;
+ }
switch (AddrMapInfo->SpaceCode) {
case PCI_SS_IO:
@@ -616,12 +622,12 @@ GeneratePciCrs (
FALSE,
TRUE,
TRUE,
- TRUE,
+ IsPosDecode,
3,
0,
AddrMapInfo->PciAddress,
AddrMapInfo->PciAddress + AddrMapInfo->AddressSize - 1,
- Translation ? AddrMapInfo->CpuAddress : 0,
+ Translation ? AddrMapInfo->CpuAddress - AddrMapInfo->PciAddress : 0,
AddrMapInfo->AddressSize,
0,
NULL,
@@ -635,7 +641,7 @@ GeneratePciCrs (
case PCI_SS_M32:
Status = AmlCodeGenRdDWordMemory (
FALSE,
- TRUE,
+ IsPosDecode,
TRUE,
TRUE,
TRUE,
@@ -643,7 +649,7 @@ GeneratePciCrs (
0,
AddrMapInfo->PciAddress,
AddrMapInfo->PciAddress + AddrMapInfo->AddressSize - 1,
- Translation ? AddrMapInfo->CpuAddress : 0,
+ Translation ? AddrMapInfo->CpuAddress - AddrMapInfo->PciAddress : 0,
AddrMapInfo->AddressSize,
0,
NULL,
@@ -657,7 +663,7 @@ GeneratePciCrs (
case PCI_SS_M64:
Status = AmlCodeGenRdQWordMemory (
FALSE,
- TRUE,
+ IsPosDecode,
TRUE,
TRUE,
TRUE,
@@ -665,7 +671,7 @@ GeneratePciCrs (
0,
AddrMapInfo->PciAddress,
AddrMapInfo->PciAddress + AddrMapInfo->AddressSize - 1,
- Translation ? AddrMapInfo->CpuAddress : 0,
+ Translation ? AddrMapInfo->CpuAddress - AddrMapInfo->PciAddress : 0,
AddrMapInfo->AddressSize,
0,
NULL,
--
2.25.1
next prev parent reply other threads:[~2022-07-01 16:32 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-07-01 16:32 [PATCH v2 0/4] DynamicTablesPkg: Pcie generation updates Jeff Brasen
2022-07-01 16:32 ` Jeff Brasen [this message]
2022-07-01 16:32 ` [PATCH v2 2/4] DynamicTablesPkg: AcpiSsdtPcieLibArm: Allow use of segment number as UID Jeff Brasen
2022-07-01 16:32 ` [PATCH v2 3/4] DynamicTablesPkg: AcpiSsdtPcieLibArm: Support UID > 0xF Jeff Brasen
2022-07-01 16:32 ` [PATCH v2 4/4] DynamicTablesPkg: AcpiSsdtPcieLibArm: Add support for override protocol Jeff Brasen
2022-07-07 16:59 ` [PATCH v2 0/4] DynamicTablesPkg: Pcie generation updates Jeff Brasen
2022-07-08 7:31 ` PierreGondois
2022-07-08 15:13 ` Jeff Brasen
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