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Thu, 23 Mar 2023 01:14:03 -0500 From: "Abdul Lateef Attar" To: CC: Abdul Lateef Attar , Ard Biesheuvel , Leif Lindholm , Abner Chang , Michael D Kinney Subject: [PATCH v3 2/3] Platform/AMD/MinBoardPkg: Adds SetCacheMtrrLib library Date: Thu, 23 Mar 2023 11:43:55 +0530 Message-ID: X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 Return-Path: AbdulLateef.Attar@amd.com X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT077:EE_|IA1PR12MB6529:EE_ X-MS-Office365-Filtering-Correlation-Id: b2d09bb0-232d-44a9-bc90-08db2b65ceb1 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: bWMgIwcnfoNTEO7hfcQ2xhxpZs0cFpLM18+EukVuiax7oySPp/TtC3yv4OfmOomTmc4vPOHaj2uApz0Sxcx/dHxODmRhcj6v80H7JRLD3t31Bwghbb7fTWvlOYvABpSYRVelUyQI/QVg8yb4xaKXtns39M+jn2nqI+EIrq+oWNcdspLyzdDuMDLwAkzmbx5ALsHTZ9t/R9+oA1ctoYEIuklr8WdsWMtXHBjUrxsxcIMWqZQfEGfiPRtMhgU5gjls6Qdm6sk1z2nDcbCYXTeafbjwqdkPYC9tfym5dhUEPhh6djND/wn97tEDHR4e6DRwV8f3ZY0nLGArGZARtOdtdh8Y1l9ytIx+rctLL70yvZDPDbG1ITRCZHJDgEykLVsaRNAiA0vF6qDB5mIDDR/BcN8XmNQ3E5tapCEBiQl+CndlewT89znp8DIQDon4zrzFFEnTQymU6si22sKHwrCrHsCdXUb/HcDomho5gxGtz0DGRXyH/OtLYBa/mRmEzoSUAD1Uua2V7MOWjQodWCUvcfZc8z70ggHYcaT42Am799NEf0IIC450eUeQ8qFYroswXdQPU2gp/BPTOn8PToZF6nb3SrSb74Mh6MfmcZaO96ZqfyOtRumdzshmDp1wCYYdjx9jBEkbotFlwSrpDosoYONLOuxHmANOzKlIF2ynhX8op/t+uacaq1B3p5sfOBf5W6epoAJ9lImoMJLYr7NbSYSBZdaAIpm/YbT9GAkERmI= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230025)(4636009)(39860400002)(346002)(136003)(396003)(376002)(451199018)(36840700001)(46966006)(40470700004)(8936002)(41300700001)(5660300002)(4326008)(36860700001)(82310400005)(36756003)(40480700001)(356005)(82740400003)(2906002)(81166007)(40460700003)(336012)(7696005)(83380400001)(2616005)(47076005)(6666004)(426003)(478600001)(26005)(186003)(54906003)(70586007)(70206006)(316002)(6916009)(8676002)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Mar 2023 06:14:06.0940 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b2d09bb0-232d-44a9-bc90-08db2b65ceb1 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT077.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB6529 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain Adds SetCacheMtrrLib library for MinBoardPkg, which sets MTRR values for PEI phase and also modifies the MTRR value at the end of PEI phase. Signed-off-by: Abdul Lateef Attar Cc: Ard Biesheuvel Cc: Leif Lindholm Cc: Abner Chang Cc: Michael D Kinney --- Platform/AMD/MinBoardPkg/MinBoardPkg.dsc | 9 ++ .../SetCacheMtrrLib/SetCacheMtrrLib.inf | 37 +++++ .../Library/SetCacheMtrrLib/SetCacheMtrrLib.c | 133 ++++++++++++++++++ 3 files changed, 179 insertions(+) create mode 100644 Platform/AMD/MinBoardPkg/Library/SetCacheMtrrLib/SetCac= heMtrrLib.inf create mode 100644 Platform/AMD/MinBoardPkg/Library/SetCacheMtrrLib/SetCac= heMtrrLib.c diff --git a/Platform/AMD/MinBoardPkg/MinBoardPkg.dsc b/Platform/AMD/MinBoa= rdPkg/MinBoardPkg.dsc index 8c120c0649e7..810fac7aa9de 100644 --- a/Platform/AMD/MinBoardPkg/MinBoardPkg.dsc +++ b/Platform/AMD/MinBoardPkg/MinBoardPkg.dsc @@ -17,5 +17,14 @@ [Defines] SUPPORTED_ARCHITECTURES =3D IA32 | X64 =20 [Packages] + MdePkg/MdePkg.dec MinBoardPkg/MinBoardPkg.dec + MinPlatformPkg/MinPlatformPkg.dec + UefiCpuPkg/UefiCpuPkg.dec + +[LibraryClasses.common.PEIM] + SetCacheMtrrLib|MinBoardPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib.inf + +[Components.IA32] + MinBoardPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib.inf =20 diff --git a/Platform/AMD/MinBoardPkg/Library/SetCacheMtrrLib/SetCacheMtrrL= ib.inf b/Platform/AMD/MinBoardPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib.i= nf new file mode 100644 index 000000000000..add2e71651f9 --- /dev/null +++ b/Platform/AMD/MinBoardPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib.inf @@ -0,0 +1,37 @@ +## @file +# Component information file for Platform SetCacheMtrr Library. +# This library implementation is for AMD processor based platforms. +# +# Copyright (C) 2023 Advanced Micro Devices, Inc. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 1.29 + BASE_NAME =3D PeiSetCacheMtrrLib + FILE_GUID =3D 1E8468E0-5EB4-4088-9B52-BFDC6E4DAE87 + MODULE_TYPE =3D PEIM + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D SetCacheMtrrLib + +[LibraryClasses] + BaseLib + DebugLib + MtrrLib + +[Packages] + MdePkg/MdePkg.dec + MinPlatformPkg/MinPlatformPkg.dec + UefiCpuPkg/UefiCpuPkg.dec + +[Sources] + SetCacheMtrrLib.c + +[Guids] + +[Pcd] + gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress + gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize + diff --git a/Platform/AMD/MinBoardPkg/Library/SetCacheMtrrLib/SetCacheMtrrL= ib.c b/Platform/AMD/MinBoardPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib.c new file mode 100644 index 000000000000..33b774fedbd3 --- /dev/null +++ b/Platform/AMD/MinBoardPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib.c @@ -0,0 +1,133 @@ +/** @file + +SetCacheMtrr library functions. +This library implementation is for AMD processor based platforms. + +Copyright (C) 2023 Advanced Micro Devices, Inc. All rights reserved.
+ +SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include + +/** + This function sets the cache MTRR values for PEI phase. +**/ +VOID +EFIAPI +SetCacheMtrr ( + VOID + ) +{ + EFI_STATUS Status; + + Status =3D MtrrSetMemoryAttribute ( + 0, + 0xA0000, + CacheWriteBack + ); + if (EFI_ERROR (Status)) { + DEBUG (( + DEBUG_ERROR, + "Error(%r) in setting CacheWriteBack for 0-0x9FFFF\n", + Status + )); + } + + Status =3D MtrrSetMemoryAttribute ( + 0xA0000, + 0x20000, + CacheUncacheable + ); + if (EFI_ERROR (Status)) { + DEBUG (( + DEBUG_ERROR, + "Error(%r) in setting CacheUncacheable for 0xA0000-0xBFFFF\n", + Status + )); + } + + Status =3D MtrrSetMemoryAttribute ( + 0xC0000, + 0x40000, + CacheWriteProtected + ); + if (EFI_ERROR (Status)) { + DEBUG (( + DEBUG_ERROR, + "Error(%r) in setting CacheWriteProtected for 0xC0000-0xFFFFF\n", + Status + )); + } + + Status =3D MtrrSetMemoryAttribute ( + 0x100000, + 0xAFF00000, + CacheWriteBack + ); + if (EFI_ERROR (Status)) { + DEBUG (( + DEBUG_ERROR, + "Error(%r) in setting CacheWriteBack for 0x100000-0xAFFFFFFF\n", + Status + )); + } + + Status =3D MtrrSetMemoryAttribute ( + PcdGet32 (PcdFlashAreaBaseAddress), + PcdGet32 (PcdFlashAreaSize), + CacheWriteProtected + ); + if (EFI_ERROR (Status)) { + DEBUG (( + DEBUG_ERROR, + "Error(%r) in setting CacheWriteProtected for 0x%X-0x%X\n", + Status, + PcdGet32 (PcdFlashAreaBaseAddress), + PcdGet32 (PcdFlashAreaBaseAddress) + PcdGet32 (PcdFlashAreaSize) + )); + } + + MtrrDebugPrintAllMtrrs (); + return; +} + +/** + Update MTRR setting in EndOfPei phase. + This function will set the MTRR value as CacheUncacheable + for Flash address. + + @retval EFI_SUCCESS The function completes successfully. + @retval Others Some error occurs. +**/ +EFI_STATUS +EFIAPI +SetCacheMtrrAfterEndOfPei ( + VOID + ) +{ + EFI_STATUS Status; + + Status =3D MtrrSetMemoryAttribute ( + PcdGet32 (PcdFlashAreaBaseAddress), + PcdGet32 (PcdFlashAreaSize), + CacheUncacheable + ); + if (EFI_ERROR (Status)) { + DEBUG (( + DEBUG_ERROR, + "Error(%r) in setting CacheUncacheable for 0x%X-0x%X\n", + Status, + PcdGet32 (PcdFlashAreaBaseAddress), + PcdGet32 (PcdFlashAreaBaseAddress) + PcdGet32 (PcdFlashAreaSize) + )); + } + + MtrrDebugPrintAllMtrrs (); + return EFI_SUCCESS; +} + --=20 2.25.1