From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mx.groups.io with SMTP id smtpd.web11.7885.1609939676823027794 for ; Wed, 06 Jan 2021 05:27:57 -0800 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: arm.com, ip: 217.140.110.172, mailfrom: ard.biesheuvel@arm.com) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 37814D6E; Wed, 6 Jan 2021 05:27:55 -0800 (PST) Received: from [192.168.1.81] (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 434ED3F70D; Wed, 6 Jan 2021 05:27:54 -0800 (PST) To: "Bin, Sung-Uk (Bin)" , "devel@edk2.groups.io" Cc: "gaoliming@byosoft.com.cn" , "Villatel, Maugan" , "Collison, Sean" References: From: "Ard Biesheuvel" Autocrypt: addr=ard.biesheuvel@arm.com; keydata= LS0tLS1CRUdJTiBQR1AgUFVCTElDIEtFWSBCTE9DSy0tLS0tCgptUUlOQkZFS2xnWUJFQURa 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Vjh5SE1abTlhWTNSNE9oR1BDNU5vZ0V1Q3JZeFN3UXZYZ0IKdHptQmxTZlc5UGtiWTZvY3dO UVRDdk5URjU4NUd1YlJvWFNwWDV1ODZZeUEySjRlSjBhUHhjSUJpcnBTWDQ0MQpUSzZtOEgx d0Zxaz0KPXpEZFAKLS0tLS1FTkQgUEdQIFBVQkxJQyBLRVkgQkxPQ0stLS0tLQo= Subject: Re: [RFC] Incorrect memory ordering in ReleaseSpinLock() Message-ID: Date: Wed, 6 Jan 2021 14:27:52 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: quoted-printable On 1/6/21 12:29 PM, Bin, Sung-Uk (Bin) wrote: > Dear, Ard and maintainers >=20 > =C2=A0 >=20 > We are concerning that ReleaseSpinLock() does not have a memory barrier= . > This is reported to https://bugzilla.tianocore.org/show_bug.cgi?id=3D30= 05. > =C2=A0We=E2=80=99d like to hear from you whether current implementation= needs > improvement or not. >=20 I think you are correct that the current implementation is insufficient. However, I would prefer for someone to do a comprehensive audit of all the locking primitives for concurrency problems. > =C2=A0 >=20 > The concern comes from *'weak memory ordering' and multi-core.* (we are > using AARCH64) And the scenario that we=E2=80=99re concerning is like b= elow: >=20 When does UEFI run multi-core on a AArch64 system? The UEFI spec does not permit SMP at boot time, and at runtime, the runtime services are not reentrant, in which case we should be able to rely on barriers in the OS's critical section code to ensure visibility when several cores compete for the UEFI runtime services from the OS. > =C2=A0 >=20 > AcquireSpinLock(); // contains =E2=80=98dmb sy=E2=80=99 and prevents "a= =3D *b" from > moving up (and unnecessarily prevents other things from moving down) >=20 > a =3D *b; >=20 > a =3D a + 1; >=20 > *b =3D a; >=20 > *ReleaseSpinLock(); // No write barrier here, so "*b =3D a" can move do= wn. > Another core acquires the spinlock and can read stale data* >=20 > =C2=A0 >=20 > =C2=A0 >=20 > Please let me know if it would be helpful to add MemoryFence like below= : >=20 For symmetry, I'd prefer it if we could simply implement the release side in terms of InterlockedCompareExchangePointer(), and ASSERT() on the output. *However*, looking at the current code, there seems to be something seriously wrong: ReleaseSpinLock() has ASSERT (SPIN_LOCK_ACQUIRED =3D=3D LockValue || SPIN_LOCK_RELEASED =3D=3D = LockValue); which means you can release a released spinlock even on a DEBUG build without a diagnostic being printed - that seems like a bug to me. > =C2=A0 >=20 > SPIN_LOCK * >=20 > EFIAPI >=20 > ReleaseSpinLock ( >=20 > =C2=A0 IN OUT=C2=A0 SPIN_LOCK=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 *SpinLock >=20 > =C2=A0 ) >=20 > { >=20 > =C2=A0 SPIN_LOCK=C2=A0=C2=A0=C2=A0 LockValue; >=20 > =C2=A0 >=20 > =C2=A0 ASSERT (SpinLock !=3D NULL); >=20 > =C2=A0 >=20 > *=C2=A0 MemoryFence(); * >=20 > =C2=A0 >=20 > =C2=A0 LockValue =3D *SpinLock; >=20 > =C2=A0 ASSERT (SPIN_LOCK_ACQUIRED =3D=3D LockValue || SPIN_LOCK_RELEASE= D =3D=3D > LockValue); >=20 > =C2=A0 >=20 > =C2=A0 *SpinLock =3D SPIN_LOCK_RELEASED; >=20 > =C2=A0 return SpinLock; >=20 > } >=20 > *=C2=A0* >=20 > *MemoryFence is implemented with 'dmb', but I just wonder if it is okay > to not implement it with 'dsb'.* >=20 DSB is for cache and TLB maintenance, not for memory ordering. DMB should be sufficient here. And actually, we don't need a system wide DMB here, an inner shareable DMB should be sufficient (given that we don't share spinlocks with DMA masters) > =C2=A0 >=20 > * Attaching linux documentation describing SMP barrier pairing >=20 > https://github.com/torvalds/linux/blob/master/Documentation/memory-barr= iers.txt >=20 > =C2=A0 >=20 > SMP BARRIER PAIRING >=20 > =09 >=20 > ------------------- >=20 > =09 >=20 > =C2=A0 >=20 > =09 >=20 > When dealing with CPU-CPU interactions, certain types of memory barrier > should >=20 > =09 >=20 > always be paired.=C2=A0 A lack of appropriate pairing is almost certain= ly an > error. >=20 > =09 >=20 > =C2=A0 >=20 > =09 >=20 > General barriers pair with each other, though they also pair with most >=20 > =09 >=20 > other types of barriers, albeit without multicopy atomicity.=C2=A0 An a= cquire >=20 > =09 >=20 > barrier pairs with a release barrier, but both may also pair with other >=20 > =09 >=20 > barriers, including of course general barriers.=C2=A0 A write barrier p= airs >=20 > =09 >=20 > with a data dependency barrier, a control dependency, an acquire barrie= r, >=20 > =09 >=20 > a release barrier, a read barrier, or a general barrier.=C2=A0 Similarl= y a >=20 > =09 >=20 > read barrier, control dependency, or a data dependency barrier pairs >=20 > =09 >=20 > with a write barrier, an acquire barrier, a release barrier, or a >=20 > =09 >=20 > general barrier: >=20 > =09 >=20 > =C2=A0 >=20 > =09 >=20 > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 CPU 1=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0 =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 CPU 2 >=20 > =09 >=20 > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 =3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D >=20 > =09 >=20 > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 WRITE_ONCE(a, 1); >=20 > =09 >=20 > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 >=20 > =09 >=20 > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 WRITE_ONCE(b, 2);=C2=A0=C2=A0=C2=A0= =C2=A0 x =3D READ_ONCE(b); >=20 > =09 >=20 > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 =C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0 >=20 > =09 >=20 > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 =C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0 y =3D READ_ONCE(a); >=20 > =09 >=20 > =C2=A0 >=20 > =09 >=20 > Or: >=20 > =09 >=20 > =C2=A0 >=20 > =09 >=20 > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 CPU 1=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0 =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 CPU 2 >=20 > =09 >=20 > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 =3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D >=20 > =09 >=20 > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 a =3D 1; >=20 > =09 >=20 > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 >=20 > =09 >=20 > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 WRITE_ONCE(b, &a);=C2=A0=C2=A0=C2=A0= x =3D READ_ONCE(b); >=20 > =09 >=20 > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 =C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0 >=20 > =09 >=20 > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 =C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0 y =3D *x; >=20 > =09 >=20 > =C2=A0 >=20 > =09 >=20 > Or even: >=20 > =09 >=20 > =C2=A0 >=20 > =09 >=20 > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 CPU 1=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0 =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 CPU 2 >=20 > =09 >=20 > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 =3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D >=20 > =09 >=20 > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 r1 =3D READ_ONCE(y); >=20 > =09 >=20 > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 >=20 > =09 >=20 > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 WRITE_ONCE(x, 1);=C2=A0=C2=A0=C2=A0= =C2=A0 if (r2 =3D READ_ONCE(x)) { >=20 > =09 >=20 > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 =C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0 >=20 > =09 >=20 > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 =C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0 WRITE_ONCE(y, 1); >=20 > =09 >=20 > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 =C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0 } >=20 > =09 >=20 > =C2=A0 >=20 > =09 >=20 > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 assert(r1 =3D=3D 0 || r2 =3D=3D 0)= ; >=20 > =09 >=20 > =C2=A0 >=20 > =09 >=20 > Basically, the read barrier always has to be there, even though it can = be of >=20 > =09 >=20 > the "weaker" type. >=20 > =09 >=20 > =C2=A0 >=20 > =09 >=20 > [!] Note that the stores before the write barrier would normally be > expected to >=20 > =09 >=20 > match the loads after the read barrier or the data dependency barrier, > and vice >=20 > =09 >=20 > versa: >=20 > =09 >=20 > =C2=A0 >=20 > =09 >=20 > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 CPU 1=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= CPU 2 >=20 > =09 >=20 > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D >=20 > =09 >=20 > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 WRITE_ONCE(a, 1);=C2=A0=C2=A0=C2=A0= }----=C2=A0=C2=A0 --->{=C2=A0 v =3D READ_ONCE(c); >=20 > =09 >=20 > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 WRITE_ONCE(b, 2);=C2=A0=C2=A0=C2=A0= }=C2=A0=C2=A0=C2=A0 \ /=C2=A0=C2=A0=C2=A0 {=C2=A0 w =3D READ_ONCE(d); >=20 > =09 >=20 > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 =C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 \=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0 >=20 > =09 >=20 > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 WRITE_ONCE(c, 3);=C2=A0=C2=A0=C2=A0= }=C2=A0=C2=A0=C2=A0 / \=C2=A0=C2=A0=C2=A0 {=C2=A0 x =3D READ_ONCE(a); >=20 > =09 >=20 > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 WRITE_ONCE(d, 4);=C2=A0=C2=A0=C2=A0= }----=C2=A0=C2=A0 --->{=C2=A0 y =3D READ_ONCE(b); >=20 > =09 >=20 > =C2=A0 >=20 > =C2=A0 >=20 > =C2=A0 >=20 > =C2=A0 >=20 > Thanks, >=20 > Bin >=20 > =C2=A0 >=20 > *From:* bugzilla-daemon@bugzilla.tianocore.org > > *Sent:* Wednesday, November 4, 2020 10:44 AM > *To:* Bin, Sung-Uk (Bin) > *Subject:* [Bug 3005] ReleaseSpinLock() requires a barrier at the begin= ning >=20 > =C2=A0 >=20 > https://bugzilla.tianocore.org/show_bug.cgi?id=3D3005 >=20 > gaoliming@byosoft.com.cn changed: >=20 > What |Removed |Added > -----------------------------------------------------------------------= ----- > Priority|Lowest |Normal > Status|UNCONFIRMED |CONFIRMED > CC| |leif@nuviainc.com > Assignee|unassigned@tianocore.org > |ard.biesheuvel@arm.com > > Ever confirmed|0 |1 >=20 > --- Comment #5 from gaoliming@byosoft.com.cn > --- > Ard: can you help check it? This issue in AARCH64. >=20 > --=20 > You are receiving this mail because: > You reported the bug. >=20