From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=209.85.221.66; helo=mail-wr1-f66.google.com; envelope-from=philmd@redhat.com; receiver=edk2-devel@lists.01.org Received: from mail-wr1-f66.google.com (mail-wr1-f66.google.com [209.85.221.66]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 1496B21A00AE6 for ; Wed, 28 Nov 2018 06:41:29 -0800 (PST) Received: by mail-wr1-f66.google.com with SMTP id p4so26562735wrt.7 for ; Wed, 28 Nov 2018 06:41:29 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:openpgp:message-id :date:user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=ndL+cewKy1Q+qNMfkAQITRmeC47mhCf/rywpBj6OSCg=; b=Yooloel7YQ4MY7qDwq6S5ECLS32+czQaECA+b3uPRhe9WFd4qsL305cmvk2BLf6JWd LLMV7+xWhDwwWkO5QStxjAYPSLLhO8KG4YRZBn2AI5UfnWkpaYf6418kEJy1m5Fap34D EMCJbS/rmiu+X6n0kf+ZpYrWik9kAaoxXJ2FlzZ8y3dPHGCJPcqBFpgYURu5x/y9KS43 gYo7RCkZGPW2+iIN9MPusNQscPcE7v5800oQe6mw28Ryo+s60X+sAmrbHjaJzmNej6p6 DQJmAS8nxHREFpYSnHgHDDnEsHri8E14Vwf1/BxroHkbUuVAj4CdH2+4qjSkoUEIZngb IO0g== X-Gm-Message-State: AA+aEWaM8IGtuF/yop6VJhiSYWOdwnX/vyVPRjeiIUyJw3XTczEr2kyV jtR9YF8vdAAXP9hILmJ4efByiA== X-Google-Smtp-Source: AFSGD/U6FKOz1pgPGmTTlhB778kcpVT9HLL3+VbsoUOUzXd49DibsZQOha/MmRkJcFv4RdR2VbGVWA== X-Received: by 2002:adf:be8d:: with SMTP id i13mr32449420wrh.235.1543416087674; Wed, 28 Nov 2018 06:41:27 -0800 (PST) Received: from ?IPv6:2a01:cb1d:8a0a:f500:48c1:8eab:256a:caf9? ([2a01:cb1d:8a0a:f500:48c1:8eab:256a:caf9]) by smtp.gmail.com with ESMTPSA id g188sm2139417wmf.32.2018.11.28.06.41.26 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 28 Nov 2018 06:41:26 -0800 (PST) To: Ard Biesheuvel , edk2-devel@lists.01.org Cc: Laszlo Ersek , Leif Lindholm , Eric Auger , Andrew Jones , Julien Grall References: <20181128143357.991-1-ard.biesheuvel@linaro.org> <20181128143357.991-7-ard.biesheuvel@linaro.org> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Openpgp: id=89C1E78F601EE86C867495CBA2A3FD6EDEADC0DE; url=http://pgp.mit.edu/pks/lookup?op=get&search=0xA2A3FD6EDEADC0DE Message-ID: Date: Wed, 28 Nov 2018 15:41:25 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.3.0 MIME-Version: 1.0 In-Reply-To: <20181128143357.991-7-ard.biesheuvel@linaro.org> Subject: Re: [PATCH v3 06/16] ArmPkg/ArmLib: add support for reading the max physical address space size X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 28 Nov 2018 14:41:30 -0000 Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit On 28/11/18 15:33, Ard Biesheuvel wrote: > Add a helper function that returns the maximum physical address space > size as supported by the current CPU. > > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Ard Biesheuvel Reviewed-by: Philippe Mathieu-Daudé > --- > ArmPkg/Include/Library/ArmLib.h | 6 ++++++ > ArmPkg/Library/ArmLib/AArch64/ArmLibSupport.S | 17 +++++++++++++++++ > ArmPkg/Library/ArmLib/Arm/ArmLibSupport.S | 8 ++++++++ > ArmPkg/Library/ArmLib/Arm/ArmLibSupport.asm | 8 ++++++++ > 4 files changed, 39 insertions(+) > > diff --git a/ArmPkg/Include/Library/ArmLib.h b/ArmPkg/Include/Library/ArmLib.h > index ffda50e9d767..9a804c15fdb6 100644 > --- a/ArmPkg/Include/Library/ArmLib.h > +++ b/ArmPkg/Include/Library/ArmLib.h > @@ -733,4 +733,10 @@ ArmWriteCntvOff ( > UINT64 Val > ); > > +UINTN > +EFIAPI > +ArmGetPhysicalAddressBits ( > + VOID > + ); > + > #endif // __ARM_LIB__ > diff --git a/ArmPkg/Library/ArmLib/AArch64/ArmLibSupport.S b/ArmPkg/Library/ArmLib/AArch64/ArmLibSupport.S > index 1ef2f61f5979..b7173e00b039 100644 > --- a/ArmPkg/Library/ArmLib/AArch64/ArmLibSupport.S > +++ b/ArmPkg/Library/ArmLib/AArch64/ArmLibSupport.S > @@ -196,4 +196,21 @@ ASM_FUNC(ArmWriteSctlr) > 3:msr sctlr_el3, x0 > 4:ret > > +ASM_FUNC(ArmGetPhysicalAddressBits) > + mrs x0, id_aa64mmfr0_el1 > + adr x1, .LPARanges > + and x0, x0, #0xf > + ldrb w0, [x1, x0] > + ret > + > +// > +// Bits 0..3 of the AA64MFR0_EL1 system register encode the size of the > +// physical address space support on this CPU: > +// 0 == 32 bits, 1 == 36 bits, etc etc > +// 7 and up are reserved > +// > +.LPARanges: > + .byte 32, 36, 40, 42, 44, 48, 52, 0 > + .byte 0, 0, 0, 0, 0, 0, 0, 0 > + > ASM_FUNCTION_REMOVE_IF_UNREFERENCED > diff --git a/ArmPkg/Library/ArmLib/Arm/ArmLibSupport.S b/ArmPkg/Library/ArmLib/Arm/ArmLibSupport.S > index f2a517671f0a..0e9f9d0453e4 100644 > --- a/ArmPkg/Library/ArmLib/Arm/ArmLibSupport.S > +++ b/ArmPkg/Library/ArmLib/Arm/ArmLibSupport.S > @@ -165,4 +165,12 @@ ASM_FUNC(ArmWriteCpuActlr) > isb > bx lr > > +ASM_FUNC (ArmGetPhysicalAddressBits) > + mrc p15, 0, r0, c0, c1, 4 // MMFR0 > + and r0, r0, #0xf // VMSA [3:0] > + cmp r0, #5 // >= 5 implies LPAE support > + movlt r0, #32 // 32 bits if no LPAE > + movge r0, #40 // 40 bits if LPAE > + bx lr > + > ASM_FUNCTION_REMOVE_IF_UNREFERENCED > diff --git a/ArmPkg/Library/ArmLib/Arm/ArmLibSupport.asm b/ArmPkg/Library/ArmLib/Arm/ArmLibSupport.asm > index 219140c22b13..3eb52875971d 100644 > --- a/ArmPkg/Library/ArmLib/Arm/ArmLibSupport.asm > +++ b/ArmPkg/Library/ArmLib/Arm/ArmLibSupport.asm > @@ -169,4 +169,12 @@ > isb > bx lr > > + RVCT_ASM_EXPORT ArmGetPhysicalAddressBits > + mrc p15, 0, r0, c0, c1, 4 ; MMFR0 > + and r0, r0, #0xf ; VMSA [3:0] > + cmp r0, #5 ; >= 5 implies LPAE support > + movlt r0, #32 ; 32 bits if no LPAE > + movge r0, #40 ; 40 bits if LPAE > + bx lr > + > END >