From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by mx.groups.io with SMTP id smtpd.web08.929.1652334335731142201 for ; Wed, 11 May 2022 22:45:36 -0700 Authentication-Results: mx.groups.io; dkim=fail reason="unable to parse pub key" header.i=@intel.com header.s=intel header.b=g6QWHbXX; spf=pass (domain: intel.com, ip: 192.55.52.136, mailfrom: chinni.b.duggapu@intel.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1652334335; x=1683870335; h=from:to:subject:date:message-id:mime-version: content-transfer-encoding; bh=EHngaSMv6zcl8qCjowKrXNl6KCn8oPHEkOvEVuHnvlw=; b=g6QWHbXXMwb6uBkRwfdEgwfMf+l4DudG1UzYoQnRscwKa6obnZ8iSkC/ BaRK9xutM/xvavhjph/l+HN3yrmxxaForn7gPvbXCOgxLTW0LaZUNOCSx SRup+ThuFdc0+GCG262WeE0m6NNsbVBtVLIigO1+KE2YsUDrBP56lwDRi ghyUpB4XQh+gZLWq3h6o0ZpCiBROBytufnPi5xkaPnhq36WN7NyDcriXn ZQCyPJ2eWhROx0LuG9l1+i75P1HCcVWxdQIZG2xCLLV0FIfOOWB41xDn3 yzLwjBFWO22IvnvnFQurm9w7F9oxf20LZaoG/hAD2Lkl6dBWz5NyCDfkN g==; X-IronPort-AV: E=McAfee;i="6400,9594,10344"; a="249793357" X-IronPort-AV: E=Sophos;i="5.91,218,1647327600"; d="scan'208";a="249793357" Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 May 2022 22:45:34 -0700 X-IronPort-AV: E=Sophos;i="5.91,218,1647327600"; d="scan'208";a="553627549" Received: from cbduggap-mobl1.gar.corp.intel.com ([10.215.202.133]) by orsmga002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 May 2022 22:45:33 -0700 From: "cbduggap" To: devel@edk2.groups.io Subject: [PATCH] FSP_TEMP_RAM_INIT API call must follow X64 Calling Convention Date: Thu, 12 May 2022 11:14:59 +0530 Message-Id: X-Mailer: git-send-email 2.36.0.windows.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable This API accept one parameter using RCX and this is consumed in mutiple sub functions. Signed-off-by: cbduggap --- IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm | 23 +++--- .../Include/SaveRestoreSseAvxNasm.inc | 82 +++++++++++++++++++ 2 files changed, 95 insertions(+), 10 deletions(-) diff --git a/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm b/IntelFsp2Pkg/F= spSecCore/X64/FspApiEntryT.nasm index a9f5f28ed7..4add0ef3fd 100644 --- a/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm +++ b/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm @@ -130,10 +130,9 @@ ASM_PFX(LoadMicrocodeDefault): =0D cmp rsp, 0=0D jz ParamError=0D - mov eax, dword [rsp + 8] ; Parameter pointer=0D - cmp eax, 0=0D + cmp ecx, 0=0D jz ParamError=0D - mov esp, eax=0D + mov esp, ecx=0D =0D ; skip loading Microcode if the MicrocodeCodeSize is zero=0D ; and report error if size is less than 2k=0D @@ -321,8 +320,7 @@ ASM_PFX(EstablishStackFsp): ;=0D ; Save parameter pointer in rdx=0D ;=0D - mov rdx, qword [rsp + 8]=0D -=0D + mov rdx, rcx=0D ;=0D ; Enable FSP STACK=0D ;=0D @@ -418,9 +416,12 @@ ASM_PFX(TempRamInitApi): ;=0D ; Ensure both SSE and AVX are enabled=0D ;=0D - ENABLE_SSE=0D + ENABLE_SSE_X64=0D ENABLE_AVX=0D -=0D + ;=0D + ; Save Input Parameter in YMM10=0D + ;=0D + SAVE_RCX=0D ;=0D ; Save RBP, RBX, RSI, RDI and RSP in YMM7, YMM8 and YMM6=0D ;=0D @@ -442,9 +443,8 @@ ASM_PFX(TempRamInitApi): ;=0D ; Check Parameter=0D ;=0D - mov rax, qword [rsp + 8]=0D - cmp rax, 0=0D - mov rax, 08000000000000002h=0D + cmp rcx, 0=0D + mov rcx, 08000000000000002h=0D jz TempRamInitExit=0D =0D ;=0D @@ -456,17 +456,20 @@ ASM_PFX(TempRamInitApi): =0D ; Load microcode=0D LOAD_RSP=0D + LOAD_RCX=0D CALL_YMM ASM_PFX(LoadMicrocodeDefault)=0D SAVE_UCODE_STATUS rax ; Save microcode return status in SLOT= 0 in YMM9 (upper 128bits).=0D ; @note If return value rax is not 0, microcode did not load, but contin= ue and attempt to boot.=0D =0D ; Call Sec CAR Init=0D LOAD_RSP=0D + LOAD_RCX=0D CALL_YMM ASM_PFX(SecCarInit)=0D cmp rax, 0=0D jnz TempRamInitExit=0D =0D LOAD_RSP=0D + LOAD_RCX=0D CALL_YMM ASM_PFX(EstablishStackFsp)=0D cmp rax, 0=0D jnz TempRamInitExit=0D diff --git a/IntelFsp2Pkg/Include/SaveRestoreSseAvxNasm.inc b/IntelFsp2Pkg/= Include/SaveRestoreSseAvxNasm.inc index e8bd91669d..fb6df2a18b 100644 --- a/IntelFsp2Pkg/Include/SaveRestoreSseAvxNasm.inc +++ b/IntelFsp2Pkg/Include/SaveRestoreSseAvxNasm.inc @@ -177,6 +177,30 @@ LXMMN xmm5, %1, 1=0D %endmacro=0D =0D +;=0D +; Upper half of YMM10 to save/restore RCX=0D +;=0D +;=0D +; Save RCX to YMM10[128:191]=0D +; Modified: XMM5 and YMM10=0D +;=0D +=0D +%macro SAVE_RCX 0=0D + LYMMN ymm10, xmm5, 1=0D + SXMMN xmm5, 0, rcx=0D + SYMMN ymm10, 1, xmm5=0D + %endmacro=0D +=0D +;=0D +; Restore RCX from YMM10[128:191]=0D +; Modified: XMM5 and RCX=0D +;=0D +=0D +%macro LOAD_RCX 0=0D + LYMMN ymm10, xmm5, 1=0D + movq rcx, xmm5=0D + %endmacro=0D +=0D ;=0D ; YMM7[128:191] for calling stack=0D ; arg 1:Entry=0D @@ -258,6 +282,7 @@ NextAddress: %endmacro=0D =0D %macro ENABLE_AVX 0=0D + mov r10, rcx=0D mov eax, 1=0D cpuid=0D and ecx, 10000000h=0D @@ -280,5 +305,62 @@ EnableAvx: xgetbv ; result in edx:eax=0D or eax, 00000006h ; Set XCR0 bit #1 and bit #2 to enable = SSE state and AVX state=0D xsetbv=0D + mov rcx, r10=0D %endmacro=0D =0D +%macro ENABLE_SSE_X64 0=0D + ;=0D + ; Initialize floating point units=0D + ;=0D + jmp NextAddress=0D +align 4=0D + ;=0D + ; Float control word initial value:=0D + ; all exceptions masked, double-precision, round-to-nearest=0D + ;=0D +FpuControlWord DW 027Fh=0D + ;=0D + ; Multimedia-extensions control word:=0D + ; all exceptions masked, round-to-nearest, flush to zero for m= asked underflow=0D + ;=0D +MmxControlWord DQ 01F80h=0D +SseError:=0D + ;=0D + ; Processor has to support SSE=0D + ;=0D + jmp SseError=0D +NextAddress:=0D + finit=0D + mov rax, FpuControlWord=0D + fldcw [rax]=0D +=0D + ;=0D + ; Use CpuId instruction (CPUID.01H:EDX.SSE[bit 25] =3D 1) to t= est=0D + ; whether the processor supports SSE instruction.=0D + ;=0D + mov r10, rcx=0D + mov rax, 1=0D + cpuid=0D + bt rdx, 25=0D + jnc SseError=0D +=0D + ;=0D + ; SSE 4.1 support=0D + ;=0D + bt ecx, 19=0D + jnc SseError=0D + mov rcx, r10=0D + ;=0D + ; Set OSFXSR bit (bit #9) & OSXMMEXCPT bit (bit #10)=0D + ;=0D + mov rax, cr4=0D + or rax, 00000600h=0D + mov cr4, rax=0D +=0D + ;=0D + ; The processor should support SSE instruction and we can use= =0D + ; ldmxcsr instruction=0D + ;=0D + mov rax, MmxControlWord=0D + ldmxcsr [rax]=0D + %endmacro \ No newline at end of file --=20 2.36.0.windows.1