From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 8DA2F81F28 for ; Sun, 19 Feb 2017 22:05:24 -0800 (PST) Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga105.jf.intel.com with ESMTP; 19 Feb 2017 22:05:24 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.35,184,1484035200"; d="scan'208";a="66743598" Received: from shzintpr01.sh.intel.com (HELO [10.7.209.41]) ([10.239.4.80]) by orsmga005.jf.intel.com with ESMTP; 19 Feb 2017 22:05:22 -0800 To: Leo Duran , edk2-devel@ml01.01.org References: <1487278926-14303-1-git-send-email-leo.duran@amd.com> <1487278926-14303-3-git-send-email-leo.duran@amd.com> Cc: Laszlo Ersek , Feng Tian , Brijesh Singh , star.zeng@intel.com From: "Zeng, Star" Message-ID: Date: Mon, 20 Feb 2017 14:04:52 +0800 User-Agent: Mozilla/5.0 (Windows NT 6.3; WOW64; rv:45.0) Gecko/20100101 Thunderbird/45.7.1 MIME-Version: 1.0 In-Reply-To: <1487278926-14303-3-git-send-email-leo.duran@amd.com> Subject: Re: [PATCH v3 2/4] MdeModulePkg/Universal/CapsulePei: Add support for PCD PcdPteMemoryEncryptionAddressOrMask X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 20 Feb 2017 06:05:24 -0000 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Leo, Comments added inline. On 2017/2/17 5:02, Leo Duran wrote: > This PCD holds the address mask for page table entries when memory > encryption is enabled on AMD processors supporting the Secure Encrypted > Virtualization (SEV) feature. > > The mask is applied when 4GB tables are created (UefiCapsule.c), and when > the tables are expanded on-demand by page-faults above 4GB's (X64Entry.c). > > Cc: Feng Tian > Cc: Star Zeng > Cc: Laszlo Ersek > Cc: Brijesh Singh > Contributed-under: TianoCore Contribution Agreement 1.0 > Signed-off-by: Leo Duran > Reviewed-by: Star Zeng > --- > MdeModulePkg/Universal/CapsulePei/CapsulePei.inf | 2 ++ > .../Universal/CapsulePei/Common/CommonHeader.h | 7 +++++++ > MdeModulePkg/Universal/CapsulePei/UefiCapsule.c | 13 ++++++++---- > MdeModulePkg/Universal/CapsulePei/X64/X64Entry.c | 23 +++++++++++++++------- > 4 files changed, 34 insertions(+), 11 deletions(-) > [snipped] > diff --git a/MdeModulePkg/Universal/CapsulePei/X64/X64Entry.c b/MdeModulePkg/Universal/CapsulePei/X64/X64Entry.c > index 5ad95d2..2197502 100644 > --- a/MdeModulePkg/Universal/CapsulePei/X64/X64Entry.c > +++ b/MdeModulePkg/Universal/CapsulePei/X64/X64Entry.c > @@ -2,6 +2,8 @@ > The X64 entrypoint is used to process capsule in long mode. > > Copyright (c) 2011 - 2016, Intel Corporation. All rights reserved.
> +Copyright (c) 2017, AMD Incorporated. All rights reserved.
> + > This program and the accompanying materials > are licensed and made available under the terms and conditions of the BSD License > which accompanies this distribution. The full text of the license may be found at > @@ -29,6 +31,7 @@ typedef struct _PAGE_FAULT_CONTEXT { > UINT64 PhyMask; > UINTN PageFaultBuffer; > UINTN PageFaultIndex; > + UINT64 PteMemoryEncryptionAddressOrMask; > // > // Store the uplink information for each page being used. > // > @@ -114,6 +117,7 @@ AcquirePage ( > ) > { > UINTN Address; > + UINT64 AddressSetMask; > > Address = PageFaultContext->PageFaultBuffer + EFI_PAGES_TO_SIZE (PageFaultContext->PageFaultIndex); > ZeroMem ((VOID *) Address, EFI_PAGES_TO_SIZE (1)); > @@ -121,14 +125,16 @@ AcquirePage ( > // > // Cut the previous uplink if it exists and wasn't overwritten. > // > - if ((PageFaultContext->PageFaultUplink[PageFaultContext->PageFaultIndex] != NULL) && ((*PageFaultContext->PageFaultUplink[PageFaultContext->PageFaultIndex] & PageFaultContext->PhyMask) == Address)) { > + if ((PageFaultContext->PageFaultUplink[PageFaultContext->PageFaultIndex] != NULL) && > + ((*PageFaultContext->PageFaultUplink[PageFaultContext->PageFaultIndex] & PageFaultContext->PhyMask) == Address)) { No real change at here except the line feed added. You were going to update code at here, but forgot to do the real change? Will you do similar change for [PATCH v3 4/4] Thanks, Star > *PageFaultContext->PageFaultUplink[PageFaultContext->PageFaultIndex] = 0; > } > > // > // Link & Record the current uplink. > // > - *Uplink = Address | IA32_PG_P | IA32_PG_RW; > + AddressSetMask = PageFaultContext->PteMemoryEncryptionAddressOrMask; > + *Uplink = Address | (AddressSetMask & PAGING_4K_ADDRESS_MASK_64) | IA32_PG_P | IA32_PG_RW; > PageFaultContext->PageFaultUplink[PageFaultContext->PageFaultIndex] = Uplink; > > PageFaultContext->PageFaultIndex = (PageFaultContext->PageFaultIndex + 1) % EXTRA_PAGE_TABLE_PAGES; > @@ -153,6 +159,7 @@ PageFaultHandler ( > UINT64 *PageTable; > UINT64 PFAddress; > UINTN PTIndex; > + UINT64 AddressSetMask; > > // > // Get the IDT Descriptor. > @@ -163,6 +170,7 @@ PageFaultHandler ( > // > PageFaultContext = (PAGE_FAULT_CONTEXT *) (UINTN) (Idtr.Base - sizeof (PAGE_FAULT_CONTEXT)); > PhyMask = PageFaultContext->PhyMask; > + AddressSetMask = PageFaultContext->PteMemoryEncryptionAddressOrMask; > > PFAddress = AsmReadCr2 (); > DEBUG ((EFI_D_ERROR, "CapsuleX64 - PageFaultHandler: Cr2 - %lx\n", PFAddress)); > @@ -179,19 +187,19 @@ PageFaultHandler ( > if ((PageTable[PTIndex] & IA32_PG_P) == 0) { > AcquirePage (PageFaultContext, &PageTable[PTIndex]); > } > - PageTable = (UINT64*)(UINTN)(PageTable[PTIndex] & PhyMask); > + PageTable = (UINT64*)(UINTN)((PageTable[PTIndex] & ~(AddressSetMask & PAGING_4K_ADDRESS_MASK_64)) & PhyMask); > PTIndex = BitFieldRead64 (PFAddress, 30, 38); > // PDPTE > if (PageFaultContext->Page1GSupport) { > - PageTable[PTIndex] = (PFAddress & ~((1ull << 30) - 1)) | IA32_PG_P | IA32_PG_RW | IA32_PG_PS; > + PageTable[PTIndex] = ((PFAddress | (AddressSetMask & PAGING_1G_ADDRESS_MASK_64)) & ~((1ull << 30) - 1)) | IA32_PG_P | IA32_PG_RW | IA32_PG_PS; > } else { > if ((PageTable[PTIndex] & IA32_PG_P) == 0) { > AcquirePage (PageFaultContext, &PageTable[PTIndex]); > } > - PageTable = (UINT64*)(UINTN)(PageTable[PTIndex] & PhyMask); > + PageTable = (UINT64*)(UINTN)((PageTable[PTIndex] & ~(AddressSetMask & PAGING_4K_ADDRESS_MASK_64)) & PhyMask); > PTIndex = BitFieldRead64 (PFAddress, 21, 29); > // PD > - PageTable[PTIndex] = (PFAddress & ~((1ull << 21) - 1)) | IA32_PG_P | IA32_PG_RW | IA32_PG_PS; > + PageTable[PTIndex] = ((PFAddress | (AddressSetMask & PAGING_2M_ADDRESS_MASK_64)) & ~((1ull << 21) - 1)) | IA32_PG_P | IA32_PG_RW | IA32_PG_PS; > } > > return NULL; > @@ -244,6 +252,7 @@ _ModuleEntryPoint ( > // Hook page fault handler to handle >4G request. > // > PageFaultIdtTable.PageFaultContext.Page1GSupport = EntrypointContext->Page1GSupport; > + PageFaultIdtTable.PageFaultContext.PteMemoryEncryptionAddressOrMask = EntrypointContext->PteMemoryEncryptionAddressOrMask; > IdtEntry = (IA32_IDT_GATE_DESCRIPTOR *) (X64Idtr.Base + (14 * sizeof (IA32_IDT_GATE_DESCRIPTOR))); > HookPageFaultHandler (IdtEntry, &(PageFaultIdtTable.PageFaultContext)); > > @@ -298,4 +307,4 @@ _ModuleEntryPoint ( > // > ASSERT (FALSE); > return EFI_SUCCESS; > -} > \ No newline at end of file > +} >