From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from us-smtp-1.mimecast.com (us-smtp-1.mimecast.com [207.211.31.120]) by mx.groups.io with SMTP id smtpd.web12.10383.1582300463962719140 for ; Fri, 21 Feb 2020 07:54:24 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=@redhat.com header.s=mimecast20190719 header.b=YDZu3P6t; spf=pass (domain: redhat.com, ip: 207.211.31.120, mailfrom: lersek@redhat.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1582300463; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=e2m/VXaAVY71/ivgogy1XgWwDx8ZoSv5ZkfPx1LFzeo=; b=YDZu3P6twBCLHBMCMB92qZ/e+NukecKbQoTAaty0mfvs+dCLf41bxy3h9odSsCHPMfOZ66 Pez9XZH62OXMnuWkELpKDj/CqPez/15IX6bF/iH341hvyaLbVMlx1WvzlRsh33djPUagEd 0ZO1t82T+tWNK9eNnzgsCMFJexlPz9M= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-65-YeybhYA4Mv-0y6SH7lV_Tg-1; Fri, 21 Feb 2020 10:54:21 -0500 X-MC-Unique: YeybhYA4Mv-0y6SH7lV_Tg-1 Received: from smtp.corp.redhat.com (int-mx04.intmail.prod.int.phx2.redhat.com [10.5.11.14]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 01B3B1005510; Fri, 21 Feb 2020 15:54:20 +0000 (UTC) Received: from lacos-laptop-7.usersys.redhat.com (unknown [10.36.118.95]) by smtp.corp.redhat.com (Postfix) with ESMTP id E4FB85D9E2; Fri, 21 Feb 2020 15:54:18 +0000 (UTC) Subject: Re: [PATCH 1/1] ArmPlatformPkg/PrePeiCore: replace set/way cache ops with by-VA ones To: Ard Biesheuvel , devel@edk2.groups.io Cc: leif@nuviainc.com References: <20200221110714.17966-1-ard.biesheuvel@arm.com> From: "Laszlo Ersek" Message-ID: Date: Fri, 21 Feb 2020 16:54:18 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.9.1 MIME-Version: 1.0 In-Reply-To: <20200221110714.17966-1-ard.biesheuvel@arm.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.14 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Language: en-US Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit On 02/21/20 12:07, Ard Biesheuvel wrote: > Cache maintenance operations by set/way are only intended to be used > in the context of on/offlining a core, while it has been taken out of > the coherency domain. Any use intended to ensure that the contents of > the cache have made it to main memory is unreliable, since cacheline > migration and non-architected system caches may cause these contents > to linger elsewhere, without being visible in main memory once the > MMU and caches are disabled. > > In KVM on Linux, there are horrid hacks in place to ensure that such > set/way operations are trapped, and replaced with a single by-VA > clean/invalidate of the entire guest VA space once the MMU state > changes, which can be costly, and is unnecessary if we manage the > caches a bit more carefully, and perform maintenance by virtual > address only. > > So let's get rid of the call to ArmInvalidateDataCache () in the > PrePeiCore startup code, and instead, invalidate the temporary RAM > region by virtual address, which is the only memory region we will > be touching with the caches and MMU both disabled and enabled. > (This will lead to data corruption if data written with the MMU off > is shadowed by clean, stale cachelines that stick around when the > MMU is enabled again.) > > Signed-off-by: Ard Biesheuvel > --- > Tested on bare metal (SynQuacer 32-bit) and KVM (mach-virt 64-bit) > > ArmPlatformPkg/PrePeiCore/PrePeiCore.c | 6 ++++-- > ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf | 1 + > ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf | 1 + > 3 files changed, 6 insertions(+), 2 deletions(-) > > diff --git a/ArmPlatformPkg/PrePeiCore/PrePeiCore.c b/ArmPlatformPkg/PrePeiCore/PrePeiCore.c > index 4911f67577a2..a7a61fe9ddb5 100644 > --- a/ArmPlatformPkg/PrePeiCore/PrePeiCore.c > +++ b/ArmPlatformPkg/PrePeiCore/PrePeiCore.c > @@ -8,6 +8,7 @@ > **/ > > #include > +#include > #include > #include > > @@ -59,13 +60,14 @@ CEntryPoint ( > { > // Data Cache enabled on Primary core when MMU is enabled. > ArmDisableDataCache (); > - // Invalidate Data cache > - ArmInvalidateDataCache (); > // Invalidate instruction cache > ArmInvalidateInstructionCache (); > // Enable Instruction Caches on all cores. > ArmEnableInstructionCache (); > > + InvalidateDataCacheRange ((VOID *)(UINTN)PcdGet64 (PcdCPUCoresStackBase), > + PcdGet32 (PcdCPUCorePrimaryStackSize)); > + > // > // Note: Doesn't have to Enable CPU interface in non-secure world, > // as Non-secure interface is already enabled in Secure world. > diff --git a/ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf b/ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf > index f2ac45d171bc..9d90d46dcfc5 100644 > --- a/ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf > +++ b/ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf > @@ -44,6 +44,7 @@ [Packages] > [LibraryClasses] > ArmLib > ArmPlatformLib > + CacheMaintenanceLib > BaseLib > DebugLib > DebugAgentLib > diff --git a/ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf b/ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf > index 84c319c3679b..0749a6d575cf 100644 > --- a/ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf > +++ b/ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf > @@ -44,6 +44,7 @@ [Packages] > [LibraryClasses] > ArmLib > ArmPlatformLib > + CacheMaintenanceLib > BaseLib > DebugLib > DebugAgentLib > Acked-by: Laszlo Ersek