From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by mx.groups.io with SMTP id smtpd.web11.15333.1664306641897795939 for ; Tue, 27 Sep 2022 12:24:02 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=IYYbbBW3; spf=permerror, err=parse error for token &{10 18 %{ir}.%{v}.%{d}.spf.has.pphosted.com}: invalid domain name (domain: quicinc.com, ip: 205.220.180.131, mailfrom: quic_llindhol@quicinc.com) Received: from pps.filterd (m0279870.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 28RJKC1f011361; Tue, 27 Sep 2022 19:23:50 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=message-id : date : mime-version : subject : to : cc : references : from : in-reply-to : content-type : content-transfer-encoding; s=qcppdkim1; bh=s2NI2WRFb8Py9/8l/4fLqCHh+K/A4/krpuskFpmcJ1o=; b=IYYbbBW3RgM1oHdVDYR0lap7pNk1gIWR0mcXZqhp/JXoQc2Tk9wsAHFtEOp3L+M6zINo G/wyjAXe5Agct4Emz3kGYwXnC1ffKy12NYtx72DNpQTGz7ilRVhi0pDJvzkG5dbHqQgD Q9J9ltcQzfxyIkpOT4w5+Iz9nKIUkDCdN8KD6+xEhrLuGtmC5G7J6YD9HTZMGq5NeTzi V7SjJLGgV/E4C9klHCGlBKt9CAAmTenqaZk97DWtZuMMgdI8bUiDZ3+GPdDxRm8Vq/pu 7+B3FJq90qDbDrgmd4NdQJymBkAprbuqJ9jrEs/1g1SvZPfhEJAlgjQCn+4F3+vWNwNy LQ== Received: from nasanppmta01.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3juvej9wk6-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 27 Sep 2022 19:23:50 +0000 Received: from nasanex01c.na.qualcomm.com (corens_vlan604_snip.qualcomm.com [10.53.140.1]) by NASANPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 28RJ4JmS002412 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 27 Sep 2022 19:04:19 GMT Received: from [10.110.17.52] (10.80.80.8) by nasanex01c.na.qualcomm.com (10.45.79.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.29; Tue, 27 Sep 2022 12:04:18 -0700 Message-ID: Date: Tue, 27 Sep 2022 12:04:17 -0700 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:91.0) Gecko/20100101 Thunderbird/91.13.0 Subject: Re: [PATCH v5 07/21] ArmPkg: Add FID definitions for Firmware TRNG To: , CC: Sami Mujawar , Ard Biesheuvel , Rebecca Cran , Michael D Kinney , Liming Gao , Jiewen Yao , Jian J Wang References: <20220919192207.637786-1-Pierre.Gondois@arm.com> <20220919192207.637786-8-Pierre.Gondois@arm.com> From: "Leif Lindholm" In-Reply-To: <20220919192207.637786-8-Pierre.Gondois@arm.com> X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01c.na.qualcomm.com (10.45.79.139) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: pOh8Lfd2pTemjyETXIcOXXpnZG5AjzJt X-Proofpoint-ORIG-GUID: pOh8Lfd2pTemjyETXIcOXXpnZG5AjzJt X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.528,FMLib:17.11.122.1 definitions=2022-09-27_09,2022-09-27_01,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 bulkscore=0 clxscore=1015 lowpriorityscore=0 adultscore=0 phishscore=0 mlxlogscore=999 priorityscore=1501 impostorscore=0 malwarescore=0 suspectscore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2209130000 definitions=main-2209270121 Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit On 2022-09-19 12:21, Pierre.Gondois@arm.com wrote: > From: Sami Mujawar > > Bugzilla: 3668 (https://bugzilla.tianocore.org/show_bug.cgi?id=3668) > > The Arm True Random Number Generator Firmware, Interface 1.0, > Platform Design Document > (https://developer.arm.com/documentation/den0098/latest/) > defines an interface between an Operating System (OS) executing > at EL1 and Firmware (FW) exposing a conditioned entropy source > that is provided by a TRNG back end. > > New function IDs have been defined by the specification for > accessing the TRNG services. Therefore, add these definitions > to the Arm standard SMC header. > > Signed-off-by: Sami Mujawar The patch needs to be signed off by the contributor (you), and no one else. You cannot make legal statements on their behalf, and you must make the statement on your own behalf. / Leif > --- > ArmPkg/Include/IndustryStandard/ArmStdSmc.h | 109 +++++++++++++++++++- > 1 file changed, 107 insertions(+), 2 deletions(-) > > diff --git a/ArmPkg/Include/IndustryStandard/ArmStdSmc.h b/ArmPkg/Include/IndustryStandard/ArmStdSmc.h > index 78ce77cd734d..fa977a03a7ab 100644 > --- a/ArmPkg/Include/IndustryStandard/ArmStdSmc.h > +++ b/ArmPkg/Include/IndustryStandard/ArmStdSmc.h > @@ -1,13 +1,20 @@ > /** @file > * > * Copyright (c) 2020, NUVIA Inc. All rights reserved.
> -* Copyright (c) 2012-2017, ARM Limited. All rights reserved. > +* Copyright (c) 2012 - 2022, Arm Limited. All rights reserved. > * > * SPDX-License-Identifier: BSD-2-Clause-Patent > * > * @par Revision Reference: > -* - SMC Calling Convention version 1.2 > +* - [1] SMC Calling Convention version 1.2 > * (https://developer.arm.com/documentation/den0028/c/?lang=en) > +* - [2] Arm True Random Number Generator Firmware, Interface 1.0, > +* Platform Design Document. > +* (https://developer.arm.com/documentation/den0098/latest/) > +* > +* @par Glossary: > +* - TRNG - True Random Number Generator > +* > **/ > > #ifndef ARM_STD_SMC_H_ > @@ -139,4 +146,102 @@ > /* 0xbf00ff02 is reserved */ > #define ARM_SMC_ID_TOS_REVISION 0xbf00ff03 > > +// Firmware TRNG interface Function IDs > + > +/* > + SMC/HVC call to get the version of the TRNG backend, > + Cf. [2], 2.1 TRNG_VERSION > + Input values: > + W0 0x8400_0050 > + W1-W7 Reserved (MBZ) > + Return values: > + Success (W0 > 0) W0[31] MBZ > + W0[30:16] Major revision > + W0[15:0] Minor revision > + W1 - W3 Reserved (MBZ) > + Error (W0 < 0) > + NOT_SUPPORTED Function not implemented > +*/ > +#define FID_TRNG_VERSION 0x84000050 > + > +/* > + SMC/HVC call to check if a TRNG function ID is implemented by the backend, > + Cf. [2], Section 2.2 TRNG_FEATURES > + Input Values > + W0 0x8400_0051 > + W1 trng_func_id > + W2-W7 Reserved (MBZ) > + Return values: > + Success (W0 >= 0): > + SUCCESS Function is implemented. > + > 0 Function is implemented and > + has specific capabilities, > + see function definition. > + Error (W0 < 0) > + NOT_SUPPORTED Function with FID=trng_func_id > + is not implemented > +*/ > +#define FID_TRNG_FEATURES 0x84000051 > + > +/* > + SMC/HVC call to get the UUID of the TRNG backend, > + Cf. [2], Section 2.3 TRNG_GET_UUID > + Input Values: > + W0 0x8400_0052 > + W1-W7 Reserved (MBZ) > + Return Values: > + Success (W0 != -1) > + W0 UUID[31:0] > + W1 UUID[63:32] > + W2 UUID[95:64] > + W3 UUID[127:96] > + Error (W0 = -1) > + W0 NOT_SUPPORTED > +*/ > +#define FID_TRNG_GET_UUID 0x84000052 > + > +/* > + AARCH32 SMC/HVC call to get entropy bits, Cf. [2], Section 2.4 TRNG_RND. > + Input values: > + W0 0x8400_0053 > + W2-W7 Reserved (MBZ) > + Return values: > + Success (W0 = 0): > + W0 MBZ > + W1 Entropy[95:64] > + W2 Entropy[63:32] > + W3 Entropy[31:0] > + Error (W0 < 0) > + W0 NOT_SUPPORTED > + NO_ENTROPY > + INVALID_PARAMETERS > + W1 - W3 Reserved (MBZ) > +*/ > +#define FID_TRNG_RND_AARCH32 0x84000053 > + > +/* > + AARCH64 SMC/HVC call to get entropy bits, Cf. [2], Section 2.4 TRNG_RND. > + Input values: > + X0 0xC400_0053 > + X2-X7 Reserved (MBZ) > + Return values: > + Success (X0 = 0): > + X0 MBZ > + X1 Entropy[191:128] > + X2 Entropy[127:64] > + X3 Entropy[63:0] > + Error (X0 < 0) > + X0 NOT_SUPPORTED > + NO_ENTROPY > + INVALID_PARAMETERS > + X1 - X3 Reserved (MBZ) > +*/ > +#define FID_TRNG_RND_AARCH64 0xC4000053 > + > +// Firmware TRNG status codes > +#define TRNG_STATUS_SUCCESS (INT32)(0) > +#define TRNG_STATUS_NOT_SUPPORTED (INT32)(-1) > +#define TRNG_STATUS_INVALID_PARAMETER (INT32)(-2) > +#define TRNG_STATUS_NO_ENTROPY (INT32)(-3) > + > #endif // ARM_STD_SMC_H_