* [PATCH 2/6] AlderlakeOpenBoardPkg: Add modules
[not found] <cover.1686770061.git.saloni.kasbekar@intel.com>
2023-06-14 19:17 ` [PATCH 1/6] AlderlakeOpenBoardPkg: Add package and headers Saloni Kasbekar
@ 2023-06-14 19:17 ` Saloni Kasbekar
2023-06-14 19:17 ` [PATCH 3/6] AlderlakeOpenBoardPkg/AlderlakePRvp: Add library instances Saloni Kasbekar
` (3 subsequent siblings)
5 siblings, 0 replies; 6+ messages in thread
From: Saloni Kasbekar @ 2023-06-14 19:17 UTC (permalink / raw)
To: devel
Cc: Saloni Kasbekar, Sai Chaganty, Nate DeSimone, Isaac Oram,
Rosen Chuang
Adds the following modules:
-BiosInfo
-OpenBoardPlatformInit
-SBCVpdStructurePcd
-SmmMultiBoardAcpiSupportLib
Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Isaac Oram <isaac.w.oram@intel.com>
Cc: Rosen Chuang <rosen.chuang@intel.com>
Signed-off-by: Saloni Kasbekar <saloni.kasbekar@intel.com>
---
.../AlderlakeOpenBoardPkg/BiosInfo/BiosInfo.c | 196 +++++++
.../BiosInfo/BiosInfo.inf | 91 ++++
.../OpenBoardPlatformInitPostMem.c | 499 ++++++++++++++++++
.../OpenBoardPlatformInitPostMem.inf | 84 +++
.../OpenBoardPlatformInitPreMem.c | 192 +++++++
.../OpenBoardPlatformInitPreMem.inf | 59 +++
.../OpenBoardPlatformInitSmm.c | 250 +++++++++
.../OpenBoardPlatformInitSmm.h | 50 ++
.../OpenBoardPlatformInitSmm.inf | 60 +++
.../SBCVpdStructurePcd/AllStructPCD.dsc | 19 +
.../GpioTableAdlPPostMem.dsc | 40 ++
.../GpioTableAdlPPreMem.dsc | 29 +
.../MrcDqDqsSPD/AdlPSpdMap.dsc | 138 +++++
.../PcieClocks/AdlPPcieClocks.dsc | 32 ++
.../SmmAcpiEnableLib.c | 51 ++
.../SmmMultiBoardAcpiSupportLib.c | 89 ++++
.../SmmMultiBoardAcpiSupportLib.inf | 40 ++
.../SmmSiliconAcpiEnableLib.c | 157 ++++++
18 files changed, 2076 insertions(+)
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/BiosInfo/BiosInfo.c
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/BiosInfo/BiosInfo.inf
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/OpenBoardPlatformInit/OpenBoardPlatformInitPei/OpenBoardPlatformInitPostMem.c
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/OpenBoardPlatformInit/OpenBoardPlatformInitPei/OpenBoardPlatformInitPostMem.inf
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/OpenBoardPlatformInit/OpenBoardPlatformInitPei/OpenBoardPlatformInitPreMem.c
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/OpenBoardPlatformInit/OpenBoardPlatformInitPei/OpenBoardPlatformInitPreMem.inf
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/OpenBoardPlatformInit/OpenBoardPlatformInitSmm/OpenBoardPlatformInitSmm.c
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/OpenBoardPlatformInit/OpenBoardPlatformInitSmm/OpenBoardPlatformInitSmm.h
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/OpenBoardPlatformInit/OpenBoardPlatformInitSmm/OpenBoardPlatformInitSmm.inf
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/SBCVpdStructurePcd/AllStructPCD.dsc
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/SBCVpdStructurePcd/GpioTableAdlPPostMem.dsc
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/SBCVpdStructurePcd/GpioTableAdlPPreMem.dsc
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/SBCVpdStructurePcd/MrcDqDqsSPD/AdlPSpdMap.dsc
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/SBCVpdStructurePcd/PcieClocks/AdlPPcieClocks.dsc
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/SmmMultiBoardAcpiSupportLib/SmmAcpiEnableLib.c
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/SmmMultiBoardAcpiSupportLib/SmmMultiBoardAcpiSupportLib.c
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/SmmMultiBoardAcpiSupportLib/SmmMultiBoardAcpiSupportLib.inf
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/SmmMultiBoardAcpiSupportLib/SmmSiliconAcpiEnableLib.c
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/BiosInfo/BiosInfo.c b/Platform/Intel/AlderlakeOpenBoardPkg/BiosInfo/BiosInfo.c
new file mode 100644
index 0000000000..64462900de
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/BiosInfo/BiosInfo.c
@@ -0,0 +1,196 @@
+/** @file
+ PEIM to provide BiosInfo structure listing up all firmware volume's base addresses, sizes,
+ attributes, and information associated to the firmware volume.
+ Primarily the structure is used on FIT table creation and Bpm.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <PiPei.h>
+#include <Guid/BiosInfo.h>
+#include <Library/PeiServicesLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/HobLib.h>
+#include <Library/PcdLib.h>
+#include <IndustryStandard/FirmwareInterfaceTable.h>
+#include <Ppi/FirmwareVolumeInfoMeasurementExcluded.h>
+#include <Library/MemoryAllocationLib.h>
+
+#define BASE_FV_SIZE 10
+
+#define FSP_WRAPPER_FV_SIZE 3
+
+#define TSN_MAC_ADDRESS_FV_SIZE 0
+
+#define BIOS_INFO_STRUCT_SIZE (BASE_FV_SIZE + FSP_WRAPPER_FV_SIZE + TSN_MAC_ADDRESS_FV_SIZE)
+
+
+/*
+ BIOS_INFO structure is the base of the firmware volume layout for Intel platform BIOS implementation
+ so security checker module can run based on the structure and throw warnings, error or deadloop
+ when any unexpected firmware volumes are detected.
+
+ BIOS_INFO is recommended to support full entries of firmware volumes present in a flash
+ with right type, attribute, version, flash map base address and size,
+ all associated information which is defined by BIOS_INFO_STRUCT structure.
+ - IBB firmware volumes, which are expected to be measured or/and verified
+ by hardware base security solution to meet SecureBoot chain of trust
+ (Intel BootGuard for example), have attribute 0x0.
+ - Post IBB firmware volumes, which are expected to be measured or/and verified
+ by BIOS (TCG code for measurement, RSA2048SHA256Sign algorithm for verification for example),
+ have attribute BIOS_INFO_STRUCT_ATTRIBUTE_BIOS_POST_IBB.
+ - Else, follows Firmware Interface Table specification.
+*/
+#pragma pack (1)
+typedef struct {
+ BIOS_INFO_HEADER Header;
+ BIOS_INFO_STRUCT Entry[BIOS_INFO_STRUCT_SIZE];
+} BIOS_INFO;
+#pragma pack ()
+
+GLOBAL_REMOVE_IF_UNREFERENCED BIOS_INFO mBiosInfo = {
+ {
+ BIOS_INFO_SIGNATURE,
+ BIOS_INFO_STRUCT_SIZE,
+ 0,
+ },
+ {
+ {
+ FIT_TYPE_07_BIOS_STARTUP_MODULE,
+ BIOS_INFO_STRUCT_ATTRIBUTE_GENERAL_EXCLUDE_FROM_FIT,
+ 0x0100,
+ FixedPcdGet32 (PcdFlashNvStorageVariableSize) + FixedPcdGet32 (PcdFlashNvStorageFtwWorkingSize) + FixedPcdGet32 (PcdFlashNvStorageFtwSpareSize),
+ FixedPcdGet32 (PcdFlashNvStorageVariableBase)
+ },
+ {
+ FIT_TYPE_07_BIOS_STARTUP_MODULE,
+ BIOS_INFO_STRUCT_ATTRIBUTE_BIOS_POST_IBB,
+ 0x0100,
+ FixedPcdGet32 (PcdFlashFvAdvancedSize),
+ FixedPcdGet32 (PcdFlashFvAdvancedBase)
+ },
+ {
+ FIT_TYPE_07_BIOS_STARTUP_MODULE,
+ BIOS_INFO_STRUCT_ATTRIBUTE_BIOS_POST_IBB,
+ 0x0100,
+ FixedPcdGet32 (PcdFlashFvOptionalSize),
+ FixedPcdGet32 (PcdFlashFvOptionalBase)
+ },
+ {
+ FIT_TYPE_07_BIOS_STARTUP_MODULE,
+ BIOS_INFO_STRUCT_ATTRIBUTE_BIOS_POST_IBB,
+ 0x0100,
+ FixedPcdGet32 (PcdFlashFvSecuritySize),
+ FixedPcdGet32 (PcdFlashFvSecurityBase)
+ },
+ {
+ FIT_TYPE_07_BIOS_STARTUP_MODULE,
+ BIOS_INFO_STRUCT_ATTRIBUTE_BIOS_POST_IBB,
+ 0x0100,
+ FixedPcdGet32 (PcdFlashFvOsBootSize),
+ FixedPcdGet32 (PcdFlashFvOsBootBase)
+ },
+ {
+ FIT_TYPE_07_BIOS_STARTUP_MODULE,
+ BIOS_INFO_STRUCT_ATTRIBUTE_BIOS_POST_IBB,
+ 0x0100,
+ FixedPcdGet32 (PcdFlashFvUefiBootSize),
+ FixedPcdGet32 (PcdFlashFvUefiBootBase)
+ },
+ {
+ FIT_TYPE_07_BIOS_STARTUP_MODULE,
+ BIOS_INFO_STRUCT_ATTRIBUTE_BIOS_POST_IBB,
+ 0x0100,
+ FixedPcdGet32 (PcdFlashFvPostMemorySize),
+ FixedPcdGet32 (PcdFlashFvPostMemoryBase)
+ },
+ {
+ FIT_TYPE_07_BIOS_STARTUP_MODULE,
+ BIOS_INFO_STRUCT_ATTRIBUTE_GENERAL_EXCLUDE_FROM_FIT,
+ 0x0100,
+ FixedPcdGet32 (PcdFlashFvFirmwareBinariesSize),
+ FixedPcdGet32 (PcdFlashFvFirmwareBinariesBase)
+ },
+ {
+ FIT_TYPE_07_BIOS_STARTUP_MODULE,
+ BIOS_INFO_STRUCT_ATTRIBUTE_BIOS_POST_IBB,
+ 0x0100,
+ FixedPcdGet32 (PcdFlashFvFspSSize),
+ FixedPcdGet32 (PcdFlashFvFspSBase)
+ },
+ {
+ FIT_TYPE_07_BIOS_STARTUP_MODULE,
+ 0x00, // IBB FV
+ 0x0100,
+ FixedPcdGet32 (PcdFlashFvFspMSize),
+ FixedPcdGet32 (PcdFlashFvFspMBase)
+ },
+ {
+ FIT_TYPE_07_BIOS_STARTUP_MODULE,
+ 0x00, // IBB FV
+ 0x0100,
+ FixedPcdGet32 (PcdFlashFvFspTSize),
+ FixedPcdGet32 (PcdFlashFvFspTBase)
+ },
+ {
+ FIT_TYPE_07_BIOS_STARTUP_MODULE,
+ 0x00, // IBB FV
+ 0x0100,
+ FixedPcdGet32 (PcdFlashFvPreMemorySize),
+ FixedPcdGet32 (PcdFlashFvPreMemoryBase)
+ },
+ {
+ FIT_TYPE_01_MICROCODE,
+ BIOS_INFO_STRUCT_ATTRIBUTE_MICROCODE_WHOLE_REGION,
+ 0x0100,
+ FixedPcdGet32 (PcdFlashMicrocodeFvSize),
+ FixedPcdGet32 (PcdFlashMicrocodeFvBase)
+ },
+ }
+};
+
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_PEI_PPI_DESCRIPTOR mBiosInfoPpiList = {
+ EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,
+ &gBiosInfoGuid,
+ &mBiosInfo
+};
+
+/**
+ Installs BiosInfo Ppi.
+
+ @param FileHandle Handle of the file being invoked.
+ @param PeiServices Describes the list of possible PEI Services.
+
+ @retval EFI_SUCCESS Install the BiosInfo Ppi successfully.
+
+**/
+EFI_STATUS
+EFIAPI
+BiosInfoEntryPoint (
+ IN EFI_PEI_FILE_HANDLE FileHandle,
+ IN CONST EFI_PEI_SERVICES **PeiServices
+ )
+{
+ EFI_STATUS Status;
+ VOID *HobData;
+
+ //
+ // Install PPI, so that other PEI module can add dependency.
+ //
+ Status = PeiServicesInstallPpi (&mBiosInfoPpiList);
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Build hob, so that DXE module can also get the data.
+ //
+ HobData = BuildGuidHob (&gBiosInfoGuid, sizeof (mBiosInfo));
+ ASSERT (HobData != NULL);
+ if (HobData == NULL) {
+ return EFI_OUT_OF_RESOURCES;
+ }
+ CopyMem (HobData, &mBiosInfo, sizeof (mBiosInfo));
+ return EFI_SUCCESS;
+}
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/BiosInfo/BiosInfo.inf b/Platform/Intel/AlderlakeOpenBoardPkg/BiosInfo/BiosInfo.inf
new file mode 100644
index 0000000000..f020cb6432
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/BiosInfo/BiosInfo.inf
@@ -0,0 +1,91 @@
+### @file
+# Module Information description file for BIOS Info PEIM.
+# The module provides BiosInfo structure listing up all firmware volume's base addresses,
+# sizes, attributes, those information associated to each firmware volume.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+###
+
+[Defines]
+ INF_VERSION = 0x00010017
+ BASE_NAME = BiosInfo
+ FILE_GUID = 4A4CA1C6-871C-45BB-8801-6910A7AA5807
+ VERSION_STRING = 1.0
+ MODULE_TYPE = PEIM
+ ENTRY_POINT = BiosInfoEntryPoint
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES IA32 X64
+#
+
+[LibraryClasses]
+ PeimEntryPoint
+ PeiServicesLib
+ PeiServicesTablePointerLib
+ HobLib
+ BaseMemoryLib
+ MemoryAllocationLib
+ DebugLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ AlderlakeSiliconPkg/SiPkg.dec
+ IntelSiliconPkg/IntelSiliconPkg.dec
+ MinPlatformPkg/MinPlatformPkg.dec
+ AlderlakeOpenBoardPkg/OpenBoardPkg.dec
+ SecurityPkg/SecurityPkg.dec
+ BoardModulePkg/BoardModulePkg.dec
+
+[Pcd]
+ gIntelSiliconPkgTokenSpaceGuid.PcdBiosAreaBaseAddress ## CONSUMES
+ gIntelSiliconPkgTokenSpaceGuid.PcdBiosSize ## CONSUMES
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase ## CONSUMES
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize ## CONSUMES
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase ## CONSUMES
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize ## CONSUMES
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase ## CONSUMES
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdFlashFvFirmwareBinariesBase ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdFlashFvFirmwareBinariesSize ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedBase ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdFlashFvOptionalBase ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdFlashFvOptionalSize ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityBase ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootBase ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootBase ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryBase ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize ## CONSUMES
+ gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase ## CONSUMES
+ gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSBase ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMBase ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTBase ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSize ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryBase ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemorySize ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdFlashFvExtendedPostMemorySize ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdFlashFvExtendedPostMemoryBase ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdFlashFvExtendedAdvancedSize ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdFlashFvExtendedAdvancedBase ## CONSUMES
+
+[Sources]
+ BiosInfo.c
+
+[Ppis]
+ gEfiPeiFirmwareVolumeInfoMeasurementExcludedPpiGuid ## PRODUCES
+
+[Guids]
+ gBiosInfoGuid ## PRODUCES
+
+[Depex]
+ gEfiPeiMasterBootModePpiGuid
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/OpenBoardPlatformInit/OpenBoardPlatformInitPei/OpenBoardPlatformInitPostMem.c b/Platform/Intel/AlderlakeOpenBoardPkg/OpenBoardPlatformInit/OpenBoardPlatformInitPei/OpenBoardPlatformInitPostMem.c
new file mode 100644
index 0000000000..a1bbb5c179
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/OpenBoardPlatformInit/OpenBoardPlatformInitPei/OpenBoardPlatformInitPostMem.c
@@ -0,0 +1,499 @@
+/** @file
+ Source code file for OpenBoard Platform Init PEI module
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Register/Msr.h>
+#include <CpuRegs.h>
+#include <Library/IoLib.h>
+#include <Library/HobLib.h>
+#include <Library/DebugLib.h>
+#include <Library/PchInfoLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/PeiServicesLib.h>
+#include <Ppi/EndOfPeiPhase.h>
+#include <Library/MtrrLib.h>
+#include <Ppi/ReadOnlyVariable2.h>
+#include <Guid/SmramMemoryReserve.h>
+#include <Library/ConfigBlockLib.h>
+#include <Ppi/SiPolicy.h>
+#include <PchPolicyCommon.h>
+#include <Library/SiPolicyLib.h>
+#include <Guid/FirmwareFileSystem2.h>
+#include <Protocol/FirmwareVolumeBlock.h>
+#include <Library/PostCodeLib.h>
+#include <PlatformPostCode.h>
+#include <Ppi/Spi.h>
+#include <Library/MtrrLib.h>
+#include <Library/PciSegmentLib.h>
+#include <Register/PchRegs.h>
+#include <PlatformBoardId.h>
+#include <Core/Pei/PeiMain.h>
+#include <Library/PchPciBdfLib.h>
+#include <Ppi/GraphicsPlatformPolicyPpi.h>
+#include <Library/PeiGetFvInfoLib.h>
+
+/**
+ Initializes the valid bits mask and valid address mask for MTRRs.
+
+ This function initializes the valid bits mask and valid address mask for MTRRs.
+
+ @param[out] MtrrValidBitsMask The mask for the valid bit of the MTRR
+ @param[out] MtrrValidAddressMask The valid address mask for the MTRR
+
+**/
+VOID
+MtrrLibInitializeMtrrMask (
+ OUT UINT64 *MtrrValidBitsMask,
+ OUT UINT64 *MtrrValidAddressMask
+ );
+
+/**
+ Convert variable MTRRs to a RAW MTRR_MEMORY_RANGE array.
+ One MTRR_MEMORY_RANGE element is created for each MTRR setting.
+ The routine doesn't remove the overlap or combine the near-by region.
+
+ @param[in] VariableSettings The variable MTRR values to shadow
+ @param[in] VariableMtrrCount The number of variable MTRRs
+ @param[in] MtrrValidBitsMask The mask for the valid bit of the MTRR
+ @param[in] MtrrValidAddressMask The valid address mask for MTRR
+ @param[out] VariableMtrr The array to shadow variable MTRRs content
+
+ @return Number of MTRRs which has been used.
+
+**/
+UINT32
+MtrrLibGetRawVariableRanges (
+ IN MTRR_VARIABLE_SETTINGS *VariableSettings,
+ IN UINTN VariableMtrrCount,
+ IN UINT64 MtrrValidBitsMask,
+ IN UINT64 MtrrValidAddressMask,
+ OUT MTRR_MEMORY_RANGE *VariableMtrr
+ );
+
+/**
+ Apply the variable MTRR settings to memory range array.
+
+ @param[in] VariableMtrr The variable MTRR array.
+ @param[in] VariableMtrrCount The count of variable MTRRs.
+ @param[in, out] Ranges Return the memory range array with new MTRR settings applied.
+ @param[in] RangeCapacity The capacity of memory range array.
+ @param[in, out] RangeCount Return the count of memory range.
+
+ @retval RETURN_SUCCESS The memory range array is returned successfully.
+ @retval RETURN_OUT_OF_RESOURCES The count of memory ranges exceeds capacity.
+**/
+RETURN_STATUS
+MtrrLibApplyVariableMtrrs (
+ IN CONST MTRR_MEMORY_RANGE *VariableMtrr,
+ IN UINT32 VariableMtrrCount,
+ IN OUT MTRR_MEMORY_RANGE *Ranges,
+ IN UINTN RangeCapacity,
+ IN OUT UINTN *RangeCount
+ );
+
+/**
+ This function attempts to set the attributes into MTRR setting buffer.
+
+ @param[in, out] MtrrSetting - A buffer holding all MTRRs content.
+ @param[in] Ranges - Array holding memory type settings.
+ @param[in] RangeCount - Memory range count in the array.
+
+ @retval Count of used variable Mtrrs
+**/
+EFI_STATUS
+EFIAPI
+EOPSetMemoryAttributesInMtrrSettings (
+ IN OUT MTRR_SETTINGS *MtrrSetting,
+ IN MTRR_MEMORY_RANGE *Ranges,
+ IN UINTN RangeCount
+ )
+{
+ EFI_STATUS Status;
+ UINTN Index;
+ UINTN HighIndex;
+ UINT64 TopHighMemory;
+
+ Status = EFI_NOT_FOUND;
+
+ for (Index = 0, HighIndex = 0xFF; Index < RangeCount; Index++) {
+ //
+ // Set Mtrr variables from 1M.
+ //
+ if (Ranges[Index].BaseAddress < 0x100000) {
+ Ranges[Index].Length -= 0x100000;
+ Ranges[Index].BaseAddress = 0x100000;
+ }
+ if ((Ranges[Index].BaseAddress >= SIZE_4GB) && (Ranges[Index].Type == CacheWriteBack)) {
+ HighIndex = Index; // Set above 4G attributes at the latest step.
+ } else {
+ Status = MtrrSetMemoryAttributeInMtrrSettings (
+ MtrrSetting,
+ Ranges[Index].BaseAddress,
+ Ranges[Index].Length,
+ Ranges[Index].Type
+ );
+ ASSERT_EFI_ERROR (Status);
+ }
+ }
+ if (HighIndex != 0xFF) {
+ TopHighMemory = Ranges[HighIndex].BaseAddress + Ranges[HighIndex].Length;
+ //
+ // Try to cover memory as mmuch as we can.
+ // In later phase boot loader code can re-configure MTRR to exclude flash region and get back above 4GB coverage.
+ //
+ do {
+ Status = MtrrSetMemoryAttributeInMtrrSettings (
+ MtrrSetting,
+ SIZE_4GB,
+ TopHighMemory - SIZE_4GB,
+ CacheWriteBack
+ );
+ if (TopHighMemory > SIZE_4GB) {
+ TopHighMemory = RShiftU64 (TopHighMemory, 1);
+ }
+ } while ((EFI_SUCCESS != Status) && (TopHighMemory > SIZE_4GB));
+ }
+
+ return Status;
+}
+
+
+EFI_STATUS
+EFIAPI
+OpenBoardPlatformInitEndOfPei (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
+ IN VOID *Ppi
+ );
+
+static EFI_PEI_NOTIFY_DESCRIPTOR mEndOfPeiNotifyList = {
+ (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
+ &gEfiEndOfPeiSignalPpiGuid,
+ (EFI_PEIM_NOTIFY_ENTRY_POINT) OpenBoardPlatformInitEndOfPei
+};
+
+EFI_STATUS
+EFIAPI
+GetPeiPlatformLidStatus (
+ OUT LID_STATUS *CurrentLidStatus
+ );
+
+EFI_STATUS
+EFIAPI
+GetVbtData (
+ OUT EFI_PHYSICAL_ADDRESS *VbtAddress,
+ OUT UINT32 *VbtSize
+ );
+
+PEI_GRAPHICS_PLATFORM_POLICY_PPI PeiGraphicsPlatform = {
+ PEI_GRAPHICS_PLATFORM_POLICY_REVISION,
+ GetPeiPlatformLidStatus,
+ GetVbtData
+};
+
+EFI_PEI_PPI_DESCRIPTOR mPeiGraphicsPlatformPpi = {
+ (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
+ &gPeiGraphicsPlatformPpiGuid,
+ &PeiGraphicsPlatform
+};
+
+EFI_STATUS
+EFIAPI
+GetVbtData (
+ OUT EFI_PHYSICAL_ADDRESS *VbtAddress,
+ OUT UINT32 *VbtSize
+ )
+{
+ EFI_GUID FileGuid;
+ EFI_GUID BmpImageGuid;
+ VOID *Buffer;
+ UINT32 Size;
+
+ Size = 0;
+ Buffer = NULL;
+
+
+ DEBUG((DEBUG_INFO, "GetVbtData Entry\n"));
+
+ CopyMem (&BmpImageGuid, PcdGetPtr(PcdIntelGraphicsVbtFileGuid), sizeof(BmpImageGuid));
+
+ CopyMem(&FileGuid, &BmpImageGuid, sizeof(FileGuid));
+ PeiGetSectionFromFv(FileGuid, &Buffer, &Size);
+ if (Buffer == NULL) {
+ DEBUG((DEBUG_ERROR, "Could not locate VBT\n"));
+ } else {
+ DEBUG ((DEBUG_INFO, "GetVbtData Buffer is 0x%x\n", Buffer));
+ DEBUG ((DEBUG_INFO, "GetVbtData Size is 0x%x\n", Size));
+ *VbtAddress = (EFI_PHYSICAL_ADDRESS)(UINTN)Buffer;
+ *VbtSize = Size;
+ }
+ DEBUG((DEBUG_INFO, "GetVbtData exit\n"));
+
+ return EFI_SUCCESS;
+}
+
+
+/**
+ This function will return Lid Status in PEI phase.
+
+ @param[out] CurrentLidStatus
+
+ @retval EFI_SUCCESS
+ @retval EFI_UNSUPPORTED
+**/
+
+EFI_STATUS
+EFIAPI
+GetPeiPlatformLidStatus (
+ OUT LID_STATUS *CurrentLidStatus
+ )
+{
+ DEBUG ((DEBUG_INFO, "LidStatus Entry\n"));
+ //
+ // If the platform does not support a lid, the function must return EFI_UNSUPPORTED
+ //
+ if (PcdGet8 (PcdPlatformType) == TypeTrad && PcdGet8 (PcdPlatformFlavor) == FlavorDesktop) {
+ DEBUG ((DEBUG_INFO, "Returning Lid status as unsupported to GOP for DT/AIO board\n"));
+ return EFI_UNSUPPORTED;
+ }
+
+ DEBUG ((DEBUG_INFO, "LidStatus UnSupported\n"));
+ return EFI_UNSUPPORTED;
+}
+
+/**
+ Update MTRR setting in EndOfPei phase.
+
+ @retval EFI_SUCCESS The function completes successfully.
+ @retval Others Some error occurs.
+**/
+EFI_STATUS
+EFIAPI
+SetCacheMtrrAfterEndOfPei (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+ EFI_PEI_HOB_POINTERS Hob;
+ UINTN Index;
+ UINT64 SmramSize;
+ UINT64 SmramBase;
+ EFI_SMRAM_HOB_DESCRIPTOR_BLOCK *SmramHobDescriptorBlock;
+ MTRR_SETTINGS MtrrSetting;
+ UINTN RangeCount;
+ UINT32 VariableMtrrCount;
+ UINT64 MtrrValidBitsMask;
+ UINT64 MtrrValidAddressMask;
+ MTRR_MEMORY_RANGE RawVariableRanges[MTRR_NUMBER_OF_VARIABLE_MTRR];
+ MTRR_MEMORY_RANGE Ranges[MTRR_NUMBER_OF_VARIABLE_MTRR];
+ MTRR_SETTINGS UCMtrrSetting;
+ //
+ // PI SMM IPL can't set SMRAM to WB because at that time CPU ARCH protocol is not available.
+ // Set cacheability of SMRAM to WB here to improve SMRAM initialization performance.
+ //
+ SmramSize = 0;
+ SmramBase = 0;
+ Status = PeiServicesGetHobList ((VOID **) &Hob.Raw);
+ while (!END_OF_HOB_LIST (Hob)) {
+ if (Hob.Header->HobType == EFI_HOB_TYPE_GUID_EXTENSION) {
+ if (CompareGuid (&Hob.Guid->Name, &gEfiSmmSmramMemoryGuid)) {
+ SmramHobDescriptorBlock = (EFI_SMRAM_HOB_DESCRIPTOR_BLOCK *) (Hob.Guid + 1);
+ for (Index = 0; Index < SmramHobDescriptorBlock->NumberOfSmmReservedRegions; Index++) {
+ if (SmramHobDescriptorBlock->Descriptor[Index].PhysicalStart > 0x100000) {
+ SmramSize += SmramHobDescriptorBlock->Descriptor[Index].PhysicalSize;
+ if (SmramBase == 0 || SmramBase > SmramHobDescriptorBlock->Descriptor[Index].CpuStart) {
+ SmramBase = SmramHobDescriptorBlock->Descriptor[Index].CpuStart;
+ }
+ }
+ }
+ break;
+ }
+ }
+ Hob.Raw = GET_NEXT_HOB (Hob);
+ }
+
+ MtrrGetAllMtrrs (&MtrrSetting);
+ VariableMtrrCount = GetVariableMtrrCount ();
+ MtrrLibInitializeMtrrMask (&MtrrValidBitsMask, &MtrrValidAddressMask);
+
+ Ranges[0].BaseAddress = 0;
+ Ranges[0].Length = MtrrValidBitsMask + 1;
+ Ranges[0].Type = (MTRR_MEMORY_CACHE_TYPE)(MtrrSetting.MtrrDefType & 0x07); //[Bits 2:0] Default Memory Type.
+ RangeCount = 1;
+
+ MtrrLibGetRawVariableRanges (
+ &MtrrSetting.Variables, VariableMtrrCount,
+ MtrrValidBitsMask, MtrrValidAddressMask, RawVariableRanges
+ );
+
+ MtrrLibApplyVariableMtrrs (
+ RawVariableRanges, VariableMtrrCount,
+ Ranges, ARRAY_SIZE (Ranges), &RangeCount
+ );
+
+ //
+ // Set SMRAM as CacheWriteBack for performance.
+ //
+ Ranges[RangeCount].BaseAddress = SmramBase;
+ Ranges[RangeCount].Length = SmramSize;
+ Ranges[RangeCount].Type = CacheWriteBack;
+ RangeCount++;
+
+ ZeroMem (&UCMtrrSetting, sizeof (MTRR_SETTINGS));
+ UCMtrrSetting.MtrrDefType = MtrrSetting.MtrrDefType;
+ Status = EOPSetMemoryAttributesInMtrrSettings (&UCMtrrSetting, Ranges, RangeCount);
+
+ CopyMem (&MtrrSetting.Variables, &UCMtrrSetting.Variables, sizeof (MTRR_VARIABLE_SETTINGS));
+ MtrrSetting.MtrrDefType = UCMtrrSetting.MtrrDefType;
+ return Status;
+}
+
+/**
+ Configure PciHostBridge related PCDs
+**/
+VOID
+ConfigurePciHostBridgePcds (
+ VOID
+ )
+{
+ EFI_PHYSICAL_ADDRESS PciBaseAddress;
+ UINT32 Tolud;
+ UINT64 Length;
+ UINT64 McD0BaseAddress;
+ UINTN ResMemLimit1;
+ //
+ // Allocate 56 KB of I/O space [0x2000..0xFFFF]
+ //
+ DEBUG ((DEBUG_INFO, " Assign IO resource for PCI_ROOT_BRIDGE from 0x%X to 0x%X\n", PcdGet16 (PcdPciReservedIobase) ,PcdGet16 (PcdPciReservedIoLimit)));
+
+ //
+ // Read memory map registers
+ //
+ McD0BaseAddress = PCI_SEGMENT_LIB_ADDRESS (SA_SEG_NUM, SA_MC_BUS, 0, 0, 0);
+ Tolud = PciSegmentRead32 (McD0BaseAddress + R_SA_TOLUD) & B_SA_TOLUD_TOLUD_MASK;
+ PciBaseAddress = Tolud;
+
+ ResMemLimit1 = PcdGet32 (PcdPciReservedMemLimit);
+ if (ResMemLimit1 == 0) {
+ ResMemLimit1 = (UINTN) PcdGet64 (PcdPciExpressBaseAddress);
+ }
+
+ Length = ResMemLimit1 - PciBaseAddress;
+
+ if (Length != 0) {
+ PcdSet32S (PcdPciReservedMemBase, (UINT32) PciBaseAddress);
+ PcdSet32S (PcdPciReservedMemLimit, (UINT32) (PciBaseAddress + Length - 1));
+ DEBUG ((DEBUG_INFO, " Assign Memory Resource for PCI_ROOT_BRIDGE from 0x%X", PcdGet32 (PcdPciReservedMemBase)));
+ DEBUG ((DEBUG_INFO, " to 0x%X\n", PcdGet32 (PcdPciReservedMemLimit)));
+ }
+
+ //
+ // Provide 256GB available above 4GB MMIO resource
+ // limited to use single variable MTRR to cover this above 4GB MMIO region.
+ //
+ PcdSet64S (PcdPciReservedMemAbove4GBBase, BASE_256GB);
+ PcdSet64S (PcdPciReservedMemAbove4GBLimit, BASE_256GB + SIZE_256GB - 1);
+ if (PcdGet64 (PcdPciReservedMemAbove4GBBase) < PcdGet64 (PcdPciReservedMemAbove4GBLimit)) {
+ DEBUG ((DEBUG_INFO, " PCI space that above 4GB MMIO is from 0x%lX", PcdGet64 (PcdPciReservedMemAbove4GBBase)));
+ DEBUG ((DEBUG_INFO, " to 0x%lX\n", PcdGet64 (PcdPciReservedMemAbove4GBLimit)));
+ }
+}
+
+/**
+ This function handles PlatformInit task at the end of PEI
+
+ @param[in] PeiServices Pointer to PEI Services Table.
+ @param[in] NotifyDesc Pointer to the descriptor for the Notification event that
+ caused this function to execute.
+ @param[in] Ppi Pointer to the PPI data associated with this function.
+
+ @retval EFI_SUCCESS The function completes successfully
+ @retval others
+**/
+EFI_STATUS
+EFIAPI
+OpenBoardPlatformInitEndOfPei (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
+ IN VOID *Ppi
+ )
+{
+ EFI_STATUS Status;
+
+ Status = SetCacheMtrrAfterEndOfPei ();
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Configure PciHostBridge related PCDs before DXE phase
+ //
+ ConfigurePciHostBridgePcds ();
+
+ return Status;
+}
+
+
+/**
+ Platform Init PEI module entry point
+
+ @param[in] FileHandle Not used.
+ @param[in] PeiServices General purpose services available to every PEIM.
+
+ @retval EFI_SUCCESS The function completes successfully
+ @retval EFI_OUT_OF_RESOURCES Insufficient resources to create database
+**/
+EFI_STATUS
+EFIAPI
+OpenBoardPlatformInitPostMemEntryPoint (
+ IN EFI_PEI_FILE_HANDLE FileHandle,
+ IN CONST EFI_PEI_SERVICES **PeiServices
+ )
+{
+ EFI_STATUS Status;
+ PEI_CORE_INSTANCE *PrivateData;
+ UINTN CurrentFv;
+ PEI_CORE_FV_HANDLE *CoreFvHandle;
+ VOID *HobData;
+
+ PostCode (PLATFORM_INIT_POSTMEM_ENTRY);
+
+
+ //
+ // Build a HOB to show current FV location for SA policy update code to consume.
+ //
+ PrivateData = PEI_CORE_INSTANCE_FROM_PS_THIS(PeiServices);
+ CurrentFv = PrivateData->CurrentPeimFvCount;
+ CoreFvHandle = &(PrivateData->Fv[CurrentFv]);
+
+ HobData = BuildGuidHob (
+ &gPlatformInitFvLocationGuid,
+ sizeof (VOID *)
+ );
+ ASSERT (HobData != NULL);
+ CopyMem (HobData, (VOID *) &CoreFvHandle, sizeof (VOID *));
+
+#if FixedPcdGetBool(PcdAdlLpSupport) == 1
+ //
+ // Install mPeiGraphicsPlatformPpi
+ //
+ DEBUG ((DEBUG_INFO, "Install mPeiGraphicsPlatformPpi \n"));
+ Status = PeiServicesInstallPpi (&mPeiGraphicsPlatformPpi);
+#else
+ //
+ // Notify mPeiGraphicsPlatformNotifyList
+ //
+ DEBUG ((DEBUG_INFO, "Notify mPeiGraphicsPlatformNotifyList \n"));
+ Status = PeiServicesNotifyPpi (&mPeiGraphicsPlatformNotifyList);
+#endif
+
+ //
+ // Performing PlatformInitEndOfPei after EndOfPei PPI produced
+ //
+ Status = PeiServicesNotifyPpi (&mEndOfPeiNotifyList);
+ PostCode (PLATFORM_INIT_POSTMEM_EXIT);
+
+ return Status;
+}
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/OpenBoardPlatformInit/OpenBoardPlatformInitPei/OpenBoardPlatformInitPostMem.inf b/Platform/Intel/AlderlakeOpenBoardPkg/OpenBoardPlatformInit/OpenBoardPlatformInitPei/OpenBoardPlatformInitPostMem.inf
new file mode 100644
index 0000000000..ff8e8fc60b
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/OpenBoardPlatformInit/OpenBoardPlatformInitPei/OpenBoardPlatformInitPostMem.inf
@@ -0,0 +1,84 @@
+### @file
+# Component information file for the OpenBoard Platform Init PEI module.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+###
+
+[Defines]
+ INF_VERSION = 0x00010017
+ BASE_NAME = OpenBoardPlatformInitPostMem
+ FILE_GUID = 314EE04C-1106-4DC6-ACBC-CF19C0DBC5CC
+ VERSION_STRING = 1.0
+ MODULE_TYPE = PEIM
+ ENTRY_POINT = OpenBoardPlatformInitPostMemEntryPoint
+
+[LibraryClasses]
+ PeimEntryPoint
+ DebugLib
+ IoLib
+ MemoryAllocationLib
+ BaseMemoryLib
+ HobLib
+ PeiServicesLib
+ PciSegmentLib
+ MtrrLib
+ PchInfoLib
+ PostCodeLib
+ SiPolicyLib
+ FspCommonLib
+ PcdLib
+ PchPciBdfLib
+ GpioLib
+ PeiGetFvInfoLib
+
+[Packages]
+ AlderlakeSiliconPkg/SiPkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ MdePkg/MdePkg.dec
+ UefiCpuPkg/UefiCpuPkg.dec
+ IntelFsp2Pkg/IntelFsp2Pkg.dec
+ IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec
+ AlderLakeFspBinPkg/Client/AlderLakeP/AlderLakeFspBinPkg.dec
+ SecurityPkg/SecurityPkg.dec
+ AlderlakeOpenBoardPkg/OpenBoardPkg.dec
+ MinPlatformPkg/MinPlatformPkg.dec
+ IntelSiliconPkg/IntelSiliconPkg.dec
+
+[Sources]
+ OpenBoardPlatformInitPostMem.c
+
+[Ppis]
+ gEfiEndOfPeiSignalPpiGuid ## CONSUMES
+ gEfiPeiReadOnlyVariable2PpiGuid ## CONSUMES
+ gPeiGraphicsPlatformPpiGuid ## PRODUCES
+ gFspSiliconInitDonePpiGuid ## CONSUMES
+
+[Protocols]
+
+[Guids]
+ gEfiSmmSmramMemoryGuid ## CONSUMES
+ gPlatformInitFvLocationGuid ## PRODUCES
+
+[Depex]
+ gEfiPeiMemoryDiscoveredPpiGuid
+
+[Pcd]
+ gEfiSecurityPkgTokenSpaceGuid.PcdFirmwareDebuggerInitialized ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdPlatformFlavor ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdPlatformType ## CONSUMES
+ gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdPciReservedIobase ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdPciReservedIoLimit ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdPciReservedMemBase ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdPciReservedMemLimit ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdPciReservedMemAbove4GBBase ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdPciReservedMemAbove4GBLimit ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdPciSegmentCount ## CONSUMES
+
+ gIntelSiliconPkgTokenSpaceGuid.PcdIntelGraphicsVbtFileGuid ## CONSUMES
+
+[FixedPcd]
+ gSiPkgTokenSpaceGuid.PcdAdlLpSupport ## CONSUMES
+ gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection ## CONSUMES
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/OpenBoardPlatformInit/OpenBoardPlatformInitPei/OpenBoardPlatformInitPreMem.c b/Platform/Intel/AlderlakeOpenBoardPkg/OpenBoardPlatformInit/OpenBoardPlatformInitPei/OpenBoardPlatformInitPreMem.c
new file mode 100644
index 0000000000..21c3e6a221
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/OpenBoardPlatformInit/OpenBoardPlatformInitPei/OpenBoardPlatformInitPreMem.c
@@ -0,0 +1,192 @@
+/** @file
+ Source code file for OpenBoard Platform Init Pre-Memory PEI module
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <PiPei.h>
+#include <Ppi/Reset.h>
+#include <Ppi/ReadOnlyVariable2.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/HobLib.h>
+#include <Library/IoLib.h>
+#include <Library/PcdLib.h>
+#include <Library/PciSegmentLib.h>
+#include <Library/PostCodeLib.h>
+#include <Register/PchRegs.h>
+#include <PlatformPostCode.h>
+#include <Library/PeiServicesLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <CpuRegs.h>
+
+
+///
+/// Reset Generator I/O Port
+///
+#define RESET_GENERATOR_PORT 0xCF9
+
+EFI_STATUS
+EFIAPI
+PlatformInitPreMem (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
+ IN VOID *Ppi
+ );
+
+EFI_STATUS
+EFIAPI
+MemoryDiscoveredPpiNotifyCallback (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
+ IN VOID *Ppi
+ );
+
+EFI_STATUS
+EFIAPI
+PchReset (
+ IN CONST EFI_PEI_SERVICES **PeiServices
+ );
+
+static EFI_PEI_NOTIFY_DESCRIPTOR mPreMemNotifyList = {
+ (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
+ &gEfiPeiReadOnlyVariable2PpiGuid,
+ (EFI_PEIM_NOTIFY_ENTRY_POINT) PlatformInitPreMem
+};
+
+static EFI_PEI_NOTIFY_DESCRIPTOR mMemDiscoveredNotifyList = {
+ (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
+ &gEfiPeiMemoryDiscoveredPpiGuid,
+ (EFI_PEIM_NOTIFY_ENTRY_POINT) MemoryDiscoveredPpiNotifyCallback
+};
+
+static EFI_PEI_RESET_PPI mResetPpi = {
+ PchReset
+};
+
+static EFI_PEI_PPI_DESCRIPTOR mPreMemPpiList[] = {
+ {
+ (EFI_PEI_PPI_DESCRIPTOR_PPI| EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
+ &gEfiPeiResetPpiGuid,
+ &mResetPpi
+ }
+};
+
+
+/**
+ Callback once there is main memory
+
+ @param[in] PeiServices General purpose services available to every PEIM.
+ @param[in] NotifyDescriptor Notify that this module published.
+ @param[in] Ppi PPI that was installed.
+
+ @retval EFI_SUCCESS The function completed successfully.
+**/
+EFI_STATUS
+EFIAPI
+MemoryDiscoveredPpiNotifyCallback (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
+ IN VOID *Ppi
+ )
+{
+ return EFI_SUCCESS;
+}
+
+//@todo it should be performed in Si Pkg.
+/**
+ Provide hard reset PPI service.
+ To generate full hard reset, write 0x0E to PCH RESET_GENERATOR_PORT (0xCF9).
+
+ @param[in] PeiServices General purpose services available to every PEIM.
+
+ @retval Not return System reset occured.
+ @retval EFI_DEVICE_ERROR Device error, could not reset the system.
+**/
+EFI_STATUS
+EFIAPI
+PchReset (
+ IN CONST EFI_PEI_SERVICES **PeiServices
+ )
+{
+ DEBUG ((DEBUG_INFO, "Perform Cold Reset\n"));
+ IoWrite8 (RESET_GENERATOR_PORT, 0x0E);
+
+ CpuDeadLoop ();
+
+ ///
+ /// System reset occured, should never reach at this line.
+ ///
+ ASSERT_EFI_ERROR (EFI_DEVICE_ERROR);
+
+ return EFI_DEVICE_ERROR;
+}
+
+/**
+ This function handles PlatformInit task after PeiReadOnlyVariable2 PPI produced
+
+ @param[in] PeiServices Pointer to PEI Services Table.
+ @param[in] NotifyDesc Pointer to the descriptor for the Notification event that
+ caused this function to execute.
+ @param[in] Ppi Pointer to the PPI data associated with this function.
+
+ @retval EFI_SUCCESS The function completes successfully
+ @retval others
+**/
+EFI_STATUS
+EFIAPI
+PlatformInitPreMem (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
+ IN VOID *Ppi
+ )
+{
+ EFI_STATUS Status;
+
+ PostCode(PLATFORM_INIT_PREMEM_ENTRY);
+
+ ///
+ /// Install Pre Memory PPIs
+ ///
+ Status = PeiServicesInstallPpi (&mPreMemPpiList[0]);
+ ASSERT_EFI_ERROR (Status);
+
+ PostCode(PLATFORM_INIT_PREMEM_EXIT);
+
+ return Status;
+}
+
+/**
+ Platform Init before memory PEI module entry point
+
+ @param[in] FileHandle Not used.
+ @param[in] PeiServices General purpose services available to every PEIM.
+
+ @retval EFI_SUCCESS The function completes successfully
+ @retval EFI_OUT_OF_RESOURCES Insufficient resources to create database
+**/
+EFI_STATUS
+EFIAPI
+OpenBoardPlatformInitPreMemEntryPoint (
+ IN EFI_PEI_FILE_HANDLE FileHandle,
+ IN CONST EFI_PEI_SERVICES **PeiServices
+ )
+{
+ EFI_STATUS Status;
+
+ ///
+ /// Performing PlatformInitPreMem after PeiReadOnlyVariable2 PPI produced
+ ///
+ Status = PeiServicesNotifyPpi (&mPreMemNotifyList);
+
+ ///
+ /// After code reorangized, memorycallback will run because the PPI is already
+ /// installed when code run to here, it is supposed that the InstallEfiMemory is
+ /// done before.
+ ///
+ Status = PeiServicesNotifyPpi (&mMemDiscoveredNotifyList);
+
+ return Status;
+}
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/OpenBoardPlatformInit/OpenBoardPlatformInitPei/OpenBoardPlatformInitPreMem.inf b/Platform/Intel/AlderlakeOpenBoardPkg/OpenBoardPlatformInit/OpenBoardPlatformInitPei/OpenBoardPlatformInitPreMem.inf
new file mode 100644
index 0000000000..e92ef0279a
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/OpenBoardPlatformInit/OpenBoardPlatformInitPei/OpenBoardPlatformInitPreMem.inf
@@ -0,0 +1,59 @@
+### @file
+# Component information file for the OpenBoard Platform Init Pre-Memory PEI module.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+###
+
+[Defines]
+ INF_VERSION = 0x00010017
+ BASE_NAME = OpenBoardPlatformInitPreMem
+ FILE_GUID = 56BBC314-B442-4D5A-BA5C-D842DAFDBB24
+ VERSION_STRING = 1.0
+ MODULE_TYPE = PEIM
+ ENTRY_POINT = OpenBoardPlatformInitPreMemEntryPoint
+
+[LibraryClasses]
+ PeimEntryPoint
+ BaseMemoryLib
+ DebugLib
+ HobLib
+ IoLib
+ PcdLib
+ PciSegmentLib
+ PostCodeLib
+ PostCodeMapLib
+ PeiServicesLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ UefiCpuPkg/UefiCpuPkg.dec
+ IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec
+ BoardModulePkg/BoardModulePkg.dec
+ PostCodeDebugFeaturePkg/PostCodeDebugFeaturePkg.dec
+ AlderlakeSiliconPkg/SiPkg.dec
+ AlderlakeOpenBoardPkg/OpenBoardPkg.dec
+ MinPlatformPkg/MinPlatformPkg.dec
+ SecurityPkg/SecurityPkg.dec
+
+[Pcd]
+ gPlatformModuleTokenSpaceGuid.PcdRamDebugEnable ## CONSUMES
+ gPlatformModuleTokenSpaceGuid.PcdSerialPortEnable ## CONSUMES
+ gSiPkgTokenSpaceGuid.PcdSerialIoUartEnable ## CONSUMES
+ gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial ## PRODUCES
+
+[Sources]
+ OpenBoardPlatformInitPreMem.c
+
+[Ppis]
+ gEfiPeiReadOnlyVariable2PpiGuid ## SOMETIMES_CONSUMES ## NOTIFY
+ gEfiPeiMemoryDiscoveredPpiGuid ## NOTIFY
+ gEfiPeiResetPpiGuid ## NOTIFY
+
+[Guids]
+ gDebugConfigVariableGuid ## CONSUMES ## Variable
+
+[Depex]
+ gEfiPeiReadOnlyVariable2PpiGuid
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/OpenBoardPlatformInit/OpenBoardPlatformInitSmm/OpenBoardPlatformInitSmm.c b/Platform/Intel/AlderlakeOpenBoardPkg/OpenBoardPlatformInit/OpenBoardPlatformInitSmm/OpenBoardPlatformInitSmm.c
new file mode 100644
index 0000000000..4ae8995bf1
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/OpenBoardPlatformInit/OpenBoardPlatformInitSmm/OpenBoardPlatformInitSmm.c
@@ -0,0 +1,250 @@
+/** @file
+ OpenBoard Platform SMM Driver.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "OpenBoardPlatformInitSmm.h"
+#include <CpuRegs.h>
+#include <PchPolicyCommon.h>
+#include "AcpiCommon.h"
+#include <Library/PmcLib.h>
+#include <Library/PciSegmentLib.h>
+#include <Library/PostCodeLib.h>
+#include <PlatformPostCode.h>
+#include <Register/PchRegs.h>
+#include <Register/PmcRegs.h>
+#include <Register/RtcRegs.h>
+
+//
+// Global variables
+//
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_SMM_SYSTEM_TABLE2 *mSmst;
+GLOBAL_REMOVE_IF_UNREFERENCED UINT16 mAcpiBaseAddr;
+GLOBAL_REMOVE_IF_UNREFERENCED PLATFORM_NVS_AREA *mPlatformNvsAreaPtr = 0;
+
+/**
+ Clear Port 80h
+
+ SMI handler to enable ACPI mode
+
+ Dispatched on reads from APM port with value EFI_ACPI_ENABLE_SW_SMI
+
+ Disables the SW SMI Timer.
+ ACPI events are disabled and ACPI event status is cleared.
+ SCI mode is then enabled.
+
+ Clear SLP SMI status
+ Enable SLP SMI
+
+ Disable SW SMI Timer
+
+ Clear all ACPI event status and disable all ACPI events
+
+ Disable PM sources except power button
+ Clear status bits
+
+ Disable GPE0 sources
+ Clear status bits
+
+ Disable GPE1 sources
+ Clear status bits
+
+ Guarantee day-of-month alarm is invalid (ACPI 1.0 section 4.7.2.4)
+
+ Enable SCI
+
+ Set 8254 timer clock gate enable if it's not set in early phase
+
+ @param[in] DispatchHandle - The handle of this callback, obtained when registering
+ @param[in] DispatchContext - Pointer to the EFI_SMM_SW_DISPATCH_CONTEXT
+ @param[in] CommBuffer - A pointer to a collection of data in memory that will
+ be conveyed from a non-SMM environment into an SMM environment.
+ @param[in] CommBufferSize - The size of the CommBuffer.
+**/
+EFI_STATUS
+EFIAPI
+EnableAcpiCallback (
+ IN EFI_HANDLE DispatchHandle,
+ IN CONST VOID *DispatchContext,
+ IN OUT VOID *CommBuffer OPTIONAL,
+ IN OUT UINTN *CommBufferSize OPTIONAL
+ )
+{
+ UINT32 OutputValue;
+ UINT32 Pm1Cnt;
+ EFI_STATUS Status;
+
+ Status = EFI_SUCCESS;
+ //
+ // BIOS must also ensure that CF9GR is cleared and locked before handing control to the
+ // OS in order to prevent the host from issuing global resets and resetting ME
+ //
+ // EDK2: To match PCCG current BIOS behavior, do not lock CF9 Global Reset
+ // MmioWrite32 (
+ // PmcBaseAddress + R_PCH_PMC_ETR3),
+ // PmInit);
+
+ //
+ // Clear Port 80h
+ //
+ OutputValue = 0;
+ mSmst->SmmIo.Io.Write (&mSmst->SmmIo, SMM_IO_UINT16, 0x80, 1, &OutputValue);
+
+ //
+ // Disable PM sources except power button
+ //
+ OutputValue = B_ACPI_IO_PM1_EN_PWRBTN;
+ mSmst->SmmIo.Io.Write (&mSmst->SmmIo, SMM_IO_UINT16, mAcpiBaseAddr + R_ACPI_IO_PM1_EN, 1, &OutputValue);
+ //
+ // Clear PM status except Power Button status for RapidStart Resume
+ //
+ // OutputValue = 0xFFFF;
+ OutputValue = 0xFEFF;
+ mSmst->SmmIo.Io.Write (&mSmst->SmmIo, SMM_IO_UINT16, mAcpiBaseAddr + R_ACPI_IO_PM1_STS, 1, &OutputValue);
+
+ //
+ // Guarantee day-of-month alarm is invalid (ACPI 1.0 section 4.7.2.4)
+ //
+ OutputValue = R_RTC_IO_REGD;
+ mSmst->SmmIo.Io.Write (&mSmst->SmmIo, SMM_IO_UINT8, R_RTC_IO_INDEX_ALT, 1, &OutputValue);
+ OutputValue = 0x0;
+ mSmst->SmmIo.Io.Write (&mSmst->SmmIo, SMM_IO_UINT8, R_RTC_IO_TARGET_ALT, 1, &OutputValue);
+
+ //
+ // Enable SCI
+ //
+ mSmst->SmmIo.Io.Read (&mSmst->SmmIo, SMM_IO_UINT32, mAcpiBaseAddr + R_ACPI_IO_PM1_CNT, 1, &Pm1Cnt);
+ Pm1Cnt |= B_ACPI_IO_PM1_CNT_SCI_EN;
+ mSmst->SmmIo.Io.Write (&mSmst->SmmIo, SMM_IO_UINT32, mAcpiBaseAddr + R_ACPI_IO_PM1_CNT, 1, &Pm1Cnt);
+ //
+ // Write ALT_GPI_SMI_EN to disable GPI1 (SMC_EXTSMI#)
+ //
+ OutputValue = 0;
+ mSmst->SmmIo.Io.Read (&mSmst->SmmIo, SMM_IO_UINT32, mAcpiBaseAddr + 0x38, 1, &OutputValue);
+ OutputValue = OutputValue & ~(1 << (UINTN) PcdGet8 (PcdSmcExtSmiBitPosition));
+ mSmst->SmmIo.Io.Write (&mSmst->SmmIo, SMM_IO_UINT32, mAcpiBaseAddr + 0x38, 1, &OutputValue);
+
+
+ return Status;
+}
+
+/**
+ Disable SCI
+
+ @param[in] DispatchHandle - The handle of this callback, obtained when registering
+ @param[in] DispatchContext - Pointer to the EFI_SMM_SW_DISPATCH_CONTEXT
+ @param[in] CommBuffer - A pointer to a collection of data in memory that will
+ be conveyed from a non-SMM environment into an SMM environment.
+ @param[in] CommBufferSize - The size of the CommBuffer.
+**/
+EFI_STATUS
+EFIAPI
+DisableAcpiCallback (
+ IN EFI_HANDLE DispatchHandle,
+ IN CONST VOID *DispatchContext,
+ IN OUT VOID *CommBuffer OPTIONAL,
+ IN UINTN *CommBufferSize OPTIONAL
+ )
+{
+ UINT32 Pm1Cnt;
+
+ //
+ // Disable SCI
+ //
+ mSmst->SmmIo.Io.Read (&mSmst->SmmIo, SMM_IO_UINT32, mAcpiBaseAddr + R_ACPI_IO_PM1_CNT, 1, &Pm1Cnt);
+ Pm1Cnt &= ~B_ACPI_IO_PM1_CNT_SCI_EN;
+ mSmst->SmmIo.Io.Write (&mSmst->SmmIo, SMM_IO_UINT32, mAcpiBaseAddr + R_ACPI_IO_PM1_CNT, 1, &Pm1Cnt);
+
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Initializes the SMM Platform Driver
+
+ @param[in] ImageHandle - Pointer to the loaded image protocol for this driver
+ @param[in] SystemTable - Pointer to the EFI System Table
+
+ @retval Status - EFI_SUCCESS
+ @retval Assert, otherwise.
+
+**/
+EFI_STATUS
+EFIAPI
+InitializePlatformSmm (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUS Status;
+ EFI_HANDLE Handle;
+ EFI_HANDLE SwHandle;
+ EFI_SMM_SW_DISPATCH2_PROTOCOL *SwDispatch;
+ EFI_SMM_SW_REGISTER_CONTEXT SwContext;
+ PLATFORM_NVS_AREA_PROTOCOL *PlatformNvsAreaProtocol;
+
+
+ Handle = NULL;
+ SwHandle = NULL;
+
+ PostCode (PLATFORM_SMM_INIT_ENTRY);
+
+ //
+ // Great! We're now in SMM!
+ //
+
+ //
+ // Initialize global variables
+ //
+ mSmst = gSmst;
+
+ //
+ // Get the ACPI Base Address
+ //
+ mAcpiBaseAddr = PmcGetAcpiBase ();
+
+ //
+ // Locate the ICH SMM SW dispatch protocol
+ //
+ Status = mSmst->SmmLocateProtocol (&gEfiSmmSwDispatch2ProtocolGuid, NULL, (VOID**)&SwDispatch);
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Locate our shared data area
+ //
+ Status = gBS->LocateProtocol (&gPlatformNvsAreaProtocolGuid, NULL, (VOID **) &PlatformNvsAreaProtocol);
+ ASSERT_EFI_ERROR (Status);
+ mPlatformNvsAreaPtr = PlatformNvsAreaProtocol->Area;
+
+ //
+ // Register ACPI enable handler
+ //
+ SwContext.SwSmiInputValue = (UINTN) PcdGet8 (PcdAcpiEnableSwSmi);
+ Status = SwDispatch->Register (
+ SwDispatch,
+ EnableAcpiCallback,
+ &SwContext,
+ &SwHandle
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Register ACPI disable handler
+ //
+ SwContext.SwSmiInputValue = (UINTN) PcdGet8 (PcdAcpiDisableSwSmi);
+ Status = SwDispatch->Register (
+ SwDispatch,
+ DisableAcpiCallback,
+ &SwContext,
+ &SwHandle
+ );
+ ASSERT_EFI_ERROR (Status);
+
+
+ PostCode(PLATFORM_SMM_INIT_EXIT);
+
+ return EFI_SUCCESS;
+}
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/OpenBoardPlatformInit/OpenBoardPlatformInitSmm/OpenBoardPlatformInitSmm.h b/Platform/Intel/AlderlakeOpenBoardPkg/OpenBoardPlatformInit/OpenBoardPlatformInitSmm/OpenBoardPlatformInitSmm.h
new file mode 100644
index 0000000000..f8949f613f
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/OpenBoardPlatformInit/OpenBoardPlatformInitSmm/OpenBoardPlatformInitSmm.h
@@ -0,0 +1,50 @@
+/** @file
+ Header file for the OpenBoard Platform SMM Driver.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _OPEN_BOARD_PLATFORM_INIT_SMM_H_
+#define _OPEN_BOARD_PLATFORM_INIT_SMM_H_
+
+#include "Platform.h"
+#include <Uefi/UefiBaseType.h>
+#include <Library/IoLib.h>
+#include <Library/PcdLib.h>
+#include <Library/DebugLib.h>
+#include <Library/SmmServicesTableLib.h>
+#include <Library/ReportStatusCodeLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/UefiRuntimeServicesTableLib.h>
+#include <PlatformBoardType.h>
+#include <Protocol/PciRootBridgeIo.h>
+#include <Protocol/SmmBase2.h>
+#include <Protocol/SmmSwDispatch2.h>
+#include <Protocol/PlatformNvsArea.h>
+#include <IndustryStandard/Pci30.h>
+
+//
+// Callback function prototypes
+//
+EFI_STATUS
+EFIAPI
+EnableAcpiCallback (
+ IN EFI_HANDLE DispatchHandle,
+ IN CONST VOID *DispatchContext,
+ IN OUT VOID *CommBuffer OPTIONAL,
+ IN UINTN *CommBufferSize OPTIONAL
+ );
+
+EFI_STATUS
+EFIAPI
+DisableAcpiCallback (
+ IN EFI_HANDLE DispatchHandle,
+ IN CONST VOID *DispatchContext,
+ IN OUT VOID *CommBuffer OPTIONAL,
+ IN UINTN *CommBufferSize OPTIONAL
+ );
+
+#endif
+
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/OpenBoardPlatformInit/OpenBoardPlatformInitSmm/OpenBoardPlatformInitSmm.inf b/Platform/Intel/AlderlakeOpenBoardPkg/OpenBoardPlatformInit/OpenBoardPlatformInitSmm/OpenBoardPlatformInitSmm.inf
new file mode 100644
index 0000000000..f426090a46
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/OpenBoardPlatformInit/OpenBoardPlatformInitSmm/OpenBoardPlatformInitSmm.inf
@@ -0,0 +1,60 @@
+### @file
+# Component information file for OpenBoard Platform SMM Driver
+#
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+###
+
+[Defines]
+ INF_VERSION = 0x00010017
+ BASE_NAME = OpenBoardPlatformInitSmm
+ FILE_GUID = CB73C3D9-2F01-4342-AE67-04DDE5264092
+ VERSION_STRING = 1.0
+ MODULE_TYPE = DXE_SMM_DRIVER
+ PI_SPECIFICATION_VERSION = 1.20
+ ENTRY_POINT = InitializePlatformSmm
+
+[LibraryClasses]
+ UefiDriverEntryPoint
+ BaseMemoryLib
+ BasePciLibPciExpress
+ DebugLib
+ ReportStatusCodeLib
+ SmmServicesTableLib
+ PmcLib
+ UefiRuntimeServicesTableLib
+ PciSegmentLib
+ PostCodeLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ AlderlakeSiliconPkg/SiPkg.dec
+ AlderlakeOpenBoardPkg/OpenBoardPkg.dec
+ UefiCpuPkg/UefiCpuPkg.dec
+
+[Pcd]
+ gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ## CONSUMES
+ gPlatformModuleTokenSpaceGuid.PcdAcpiEnableSwSmi ## CONSUMES
+ gPlatformModuleTokenSpaceGuid.PcdAcpiDisableSwSmi ## CONSUMES
+ gPlatformModuleTokenSpaceGuid.PcdSmcExtSmiBitPosition ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdPlatformFlavor
+
+[Sources]
+ OpenBoardPlatformInitSmm.h
+ OpenBoardPlatformInitSmm.c
+
+[Protocols]
+ gPlatformNvsAreaProtocolGuid ## CONSUMES
+ gEfiSmmBase2ProtocolGuid ## CONSUMES
+ gEfiSmmSwDispatch2ProtocolGuid ## CONSUMES
+
+[Depex]
+ gEfiSmmBase2ProtocolGuid AND
+ gEfiSmmSwDispatch2ProtocolGuid AND
+ gPlatformNvsAreaProtocolGuid
+
+
+
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/SBCVpdStructurePcd/AllStructPCD.dsc b/Platform/Intel/AlderlakeOpenBoardPkg/SBCVpdStructurePcd/AllStructPCD.dsc
new file mode 100644
index 0000000000..9215a026ae
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/SBCVpdStructurePcd/AllStructPCD.dsc
@@ -0,0 +1,19 @@
+## @file
+# Include All Board Gpio configuration file.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+!include $(PLATFORM_BOARD_PACKAGE)/SBCVpdStructurePcd/GpioTableAdlPPostMem.dsc
+!include $(PLATFORM_BOARD_PACKAGE)/SBCVpdStructurePcd/GpioTableAdlPPreMem.dsc
+
+
+# PCIe clock mapping
+!include $(PLATFORM_BOARD_PACKAGE)/SBCVpdStructurePcd/PcieClocks/AdlPPcieClocks.dsc
+
+# MRC DQS DQ and SPD mapping
+!include $(PLATFORM_BOARD_PACKAGE)/SBCVpdStructurePcd/MrcDqDqsSPD/AdlPSpdMap.dsc
+
+
+
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/SBCVpdStructurePcd/GpioTableAdlPPostMem.dsc b/Platform/Intel/AlderlakeOpenBoardPkg/SBCVpdStructurePcd/GpioTableAdlPPostMem.dsc
new file mode 100644
index 0000000000..3eb8c276b5
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/SBCVpdStructurePcd/GpioTableAdlPPostMem.dsc
@@ -0,0 +1,40 @@
+## @file
+# GPIO definition table for Alderlake P
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+###
+### !!! GPIOs designated to Native Functions shall not be configured by Platform Code.
+### Native Pins shall be configured by Silicon Code (based on BIOS policies setting) or soft straps(set by CSME in FITc).
+###
+###
+
+
+#mGpioTableAdlPDdr5Rvp
+[PcdsDynamicExVpd.common.SkuIdAdlPDdr5Rvp]
+gBoardModuleTokenSpaceGuid.VpdPcdBoardGpioTable|*|{CODE({
+ // CPU M.2 SSD1
+ {GPIO_VER2_LP_GPP_F20, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis,GpioPlatformReset, GpioTermNone}}, //CPU SSD1 RESET
+
+ // CPU M.2 SSD2
+ {GPIO_VER2_LP_GPP_C2, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis,GpioPlatformReset, GpioTermNone}}, //CPU SSD2 PWREN
+ {GPIO_VER2_LP_GPP_H1, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis,GpioPlatformReset, GpioTermNone}}, // CPU SSD2 RESET
+
+ // X4 Pcie Slot for Gen3 and Gen 4
+ {GPIO_VER2_LP_GPP_F10, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis,GpioPlatformReset, GpioTermNone}},//ONBOARD_X4_PCIE_SLOT1_RESET_N
+
+ // PCH M.2 SSD
+ {GPIO_VER2_LP_GPP_D16, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis,GpioPlatformReset, GpioTermNone}}, //M2_PCH_SSD_PWREN
+ {GPIO_VER2_LP_GPP_H0, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis,GpioPlatformReset, GpioTermNone}}, //M2_SSD_RST_N
+
+ // EC
+ {GPIO_VER2_LP_GPP_E7, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault,GpioIntLevel|GpioIntSmi,GpioPlatformReset, GpioTermNone, GpioPadConfigUnlock }}, //EC_SMI_N
+ {GPIO_VER2_LP_GPP_F9, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis,GpioPlatformReset, GpioTermNone}}, //EC_SLP_S0_CS_N
+
+ {0x0} // terminator
+})}
+
+
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/SBCVpdStructurePcd/GpioTableAdlPPreMem.dsc b/Platform/Intel/AlderlakeOpenBoardPkg/SBCVpdStructurePcd/GpioTableAdlPPreMem.dsc
new file mode 100644
index 0000000000..3e147894c7
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/SBCVpdStructurePcd/GpioTableAdlPPreMem.dsc
@@ -0,0 +1,29 @@
+## @file
+# Alderlake P RVP GPIO definition table for Pre-Memory Initialization
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+###
+### !!! GPIOs designated to Native Functions shall not be configured by Platform Code.
+### Native Pins shall be configured by Silicon Code (based on BIOS policies setting) or soft straps(set by CSME in FITc).
+###
+###
+
+# mGpioTablePreMemAdlPDdr5Rvp
+[PcdsDynamicExVpd.common.SkuIdAdlPDdr5Rvp]
+gBoardModuleTokenSpaceGuid.VpdPcdBoardGpioTablePreMem|*|{CODE({
+ // CPU M.2 SSD
+ { GPIO_VER2_LP_GPP_F20, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis, GpioPlatformReset, GpioTermNone } }, //CPU SSD RESET
+
+ // CPU M.2 SSD2
+ {GPIO_VER2_LP_GPP_C2, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis,GpioPlatformReset, GpioTermNone}}, //CPU SSD2 PWREN
+ {GPIO_VER2_LP_GPP_H1, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis,GpioPlatformReset, GpioTermNone}}, //CPU SSD2 RESET
+
+ // X4 Pcie Slot for Gen3 and Gen 4
+ {GPIO_VER2_LP_GPP_F10, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis,GpioPlatformReset, GpioTermNone}},//ONBOARD_X4_PCIE_SLOT1_RESET_N
+
+ {0x0} // terminator
+})}
\ No newline at end of file
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/SBCVpdStructurePcd/MrcDqDqsSPD/AdlPSpdMap.dsc b/Platform/Intel/AlderlakeOpenBoardPkg/SBCVpdStructurePcd/MrcDqDqsSPD/AdlPSpdMap.dsc
new file mode 100644
index 0000000000..096cc380cd
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/SBCVpdStructurePcd/MrcDqDqsSPD/AdlPSpdMap.dsc
@@ -0,0 +1,138 @@
+## @file
+# ADL P SPD DATA configuration file.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+
+[PcdsDynamicExVpd.common.SkuIdAdlPDdr5Rvp]
+gBoardModuleTokenSpaceGuid.VpdPcdMrcSpdData|*|{CODE(
+{
+// DDR5 1Rx16 - 4800 MHz
+ 1,
+ {0x30, ///< 0 1024 SPD bytes total
+ 0x08, ///< 1 SPD Revision 0.8
+ 0x12, ///< 2 DRAM Type: DDR5 SDRAM
+ 0x03, ///< 3 Module Type: Not Hybrid (DRAM only) / SO-DIMM Solution
+ 0x04, ///< 4 Monolithic SDRAM, 16 Gb SDRAM density
+ 0x00, ///< 5 16 Rows, 10 Columns
+ 0x40, ///< 6 x16 SDRAM I/O Width
+ 0x42, ///< 7 4 Bank Groups, 4 Banks per Bank Group
+ 0x00, ///< 8 Secondary SDRAM Density and Package
+ 0x00, ///< 9 Secondary SDRAM Addressing
+ 0x00, ///< 10 Secondary SDRAM I/O Width
+ 0x00, ///< 11 Secondary BankGroups and Banks per Bank Group
+ 0x60, ///< 12 PPR Supported, One row per bank group, Soft PPR Supported
+ 0x00, ///< 13 Commercial Temperature Grade, 0 to 85 C
+ 0x00, ///< 14 Reserved
+ 0x00, ///< 15 Reserved
+ 0x00, ///< 16 SDRAM Nominal Voltage VDD: 1.1V
+ 0x00, ///< 17 SDRAM Nominal Voltage VDDQ: 1.1V
+ 0x00, ///< 18 SDRAM Nominal Voltage VPP: 1.8V
+ 0x00, ///< 19 Reserved
+ 0xA1, ///< 20 tCKAVGmin LSB
+ 0x01, ///< 21 tCKAVGmin MSB
+ 0xE8, ///< 22 tCKAVGmax LSB
+ 0x03, ///< 23 tCKAVGmax MSB
+ 0x72, ///< 24 CAS Latencies supported (First Byte) : 32, 30, 28, 22
+ 0x15, ///< 25 CAS Latencies supported (Second Byte): 44, 40, 36
+ 0x00, ///< 26 CAS Latencies supported (Third Byte) :
+ 0x00, ///< 27 CAS Latencies supported (Fourth Byte):
+ 0x00, ///< 28 CAS Latencies supported (Fifth Byte) :
+ 0x00, ///< 29 Reserved
+ 0x1E, ///< 30 Minimum CAS Latency (tAAmin) LSB
+ 0x41, ///< 31 Minimum CAS Latency (tAAmin) MSB
+ 0x1E, ///< 32 Minimum RAS-to-CAS delay (tRCDmin) LSB
+ 0x41, ///< 33 Minimum RAS-to-CAS delay (tRCDmin) MSB
+ 0x1E, ///< 34 Minimum Row Precharge delay (tRPmin) LSB
+ 0x41, ///< 35 Minimum Row Precharge delay (tRPmin) MSB
+ 0x00, ///< 36 Minimum Active to Precharge delay (tRASmin) LSB
+ 0x7D, ///< 37 Minimum Active to Precharge delay (tRASmin) MSB
+ 0x1E, ///< 38 Minimum Active to Active/Refresh delay (tRCmin) LSB
+ 0xBE, ///< 39 Minimum Active to Active/Refresh delay (tRCmin) MSB
+ 0x30, ///< 40 Minimum Write Recovery time (tWRmin) LSB
+ 0x75, ///< 41 Minimum Write Recovery time (tWRmin) MSB
+ 0x27, ///< 42 Refresh Recovery Delay (tRFC1min) LSB
+ 0x01, ///< 43 Refresh Recovery Delay (tRFC1min) MSB
+ 0xA0, ///< 44 Refresh Recovery Delay (tRFC2min) MSB
+ 0x00, ///< 45 Refresh Recovery Delay (tRFC2min) MSB
+ 0x82, ///< 46 Refresh Recovery Delay (tRFCsbmin) MSB
+ 0x00, ///< 47 Refresh Recovery Delay (tRFCsbmin) MSB
+ 0, 0, ///< 48 - 49
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 50 - 59
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 60 - 69
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 70 - 79
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 80 - 89
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 90 - 99
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 100 - 109
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 110 - 119
+ 0, 0, 0, 0, 0, 0, ///< 120 - 125
+ 0x47, ///< 126 CRC Bytes 0 - 127 LSB
+ 0xAE, ///< 127 CRC Bytes 0 - 127 MSB
+ 0, 0, ///< 128 - 129
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 130 - 139
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 140 - 149
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 150 - 159
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 160 - 169
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 170 - 179
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 180 - 189
+ 0, 0, ///< 190 - 191
+ 0x08, ///< 192 SPD Revision for Module Information: 0.8
+ 0x00, ///< 193 Reserved
+ 0xC2, ///< 194 SPD Manufacturer ID First Byte
+ 0xC4, ///< 195 SPD Manufacturer ID Second Byte
+ 0x80, ///< 196 SPD Device Type
+ 0x00, ///< 197 SPD Device Revision
+ 0x80, ///< 198 PMIC0 Manufacturer ID First Byte
+ 0xB3, ///< 199 PMIC0 Manufacturer ID Second Byte
+ 0x80, ///< 200 PMIC0 Device Type
+ 0x11, ///< 201 PMIC0 Device Revision
+ 0, 0, 0, 0, ///< 202 - 205 PMIC1
+ 0, 0, 0, 0, ///< 206 - 209 PMIC2
+ 0x80, ///< 210 Thermal Sensors Manufacturer ID First Byte
+ 0xB3, ///< 211 Thermal Sensors Manufacturer ID First Byte
+ 0x80, ///< 212 Thermal Sensors Device Type
+ 0x11, ///< 213 Thermal Sensors Device Revision
+ 0, 0, 0, 0, 0, 0, ///< 214 - 219
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 220 - 229
+ 0x0F, ///< 230 Module Nominal Height
+ 0x10, ///< 231 Module Nominal Thickness
+ 0x00, ///< 232 Reference Raw Card Used
+ 0x01, ///< 233 1 Row of DRAM on Module
+ 0x01, ///< 234 1 Rank, 8 bits SDRAM data width per channel
+ 0x22, ///< 235 2 Channels per DIMM, 32 bits per Channel
+ 0, 0, 0, 0, ///< 236 - 239
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 240 - 249
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 250 - 259
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 260 - 269
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 270 - 279
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 280 - 289
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 290 - 299
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 300 - 309
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 310 - 319
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 320 - 329
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 330 - 339
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 340 - 349
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 350 - 359
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 360 - 369
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 370 - 379
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 380 - 389
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 390 - 399
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 400 - 409
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 410 - 419
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 420 - 429
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 430 - 439
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ///< 440 - 445
+ 0x9C, ///< 446 CRC for Bytes 128 - 253 LSB
+ 0xAD, ///< 447 CRC for Bytes 128 - 253 MSB
+ 0, 0, ///< 448 - 449
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 450 - 459
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 460 - 469
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 470 - 479
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 480 - 489
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 490 - 499
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 500 - 509
+ 0, 0 ///< 510 - 511
+ ///< Ignore bytes 512-1023, @todo_adl: support 1024 bytes SPD array
+}})}
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/SBCVpdStructurePcd/PcieClocks/AdlPPcieClocks.dsc b/Platform/Intel/AlderlakeOpenBoardPkg/SBCVpdStructurePcd/PcieClocks/AdlPPcieClocks.dsc
new file mode 100644
index 0000000000..9871bb0c87
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/SBCVpdStructurePcd/PcieClocks/AdlPPcieClocks.dsc
@@ -0,0 +1,32 @@
+## @file
+# Alderlake P Pcie Clock configuration file.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+
+[PcdsDynamicExVpd.common.SkuIdAdlPDdr5Rvp]
+gBoardModuleTokenSpaceGuid.VpdPcdPcieClkUsageMap|*|{CODE(
+{{
+ PCIE_PEG, // CPU M.2 SSD 1
+ PCIE_PCH + 8, // PCH M.2 SSD
+ PCIE_PCH + 4,
+ PCIE_PEG + 1, // X8 DG/DG2
+ PCIE_PEG + 2, // CPU M.2 SSD 2
+ PCIE_PCH + 5, // M.2 KEY B WWAN - PCIe P6
+ LAN_CLOCK,
+ // Default Case:
+ // - PCIe P7 mapped to GBELAN
+ // - PCIe P8 mapped to x4 PCIe DT Slot (Pair 1)
+ PCIE_PCH + 7, // x4 PCIe DT Slot (x1)
+ // Reworked Case: with rework and soft strap changes
+ // - PCIe P7 mapped to x4 PCIe DT Slot (Pair 2)
+ // - PCIe P8 mapped to x4 PCIe DT Slot (Pair 1)
+ // @todo: To support reworked case, enable the below code.
+ // PCIE_PCH + 6, // x4 PCIe DT Slot (x2)
+ NOT_USED,
+ NOT_USED
+}}
+)}
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/SmmMultiBoardAcpiSupportLib/SmmAcpiEnableLib.c b/Platform/Intel/AlderlakeOpenBoardPkg/SmmMultiBoardAcpiSupportLib/SmmAcpiEnableLib.c
new file mode 100644
index 0000000000..d5a51cbc14
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/SmmMultiBoardAcpiSupportLib/SmmAcpiEnableLib.c
@@ -0,0 +1,51 @@
+/** @file
+ SMM Board ACPI Enable Library
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Base.h>
+#include <Uefi.h>
+#include <PiDxe.h>
+#include <Library/BaseLib.h>
+#include <Library/IoLib.h>
+#include <Library/BoardAcpiTableLib.h>
+#include <Library/PcdLib.h>
+#include <Library/DebugLib.h>
+#include <PlatformBoardId.h>
+
+/**
+ Enable Board Acpi
+
+ @param[in] EnableSci Enable SCI if EnableSci parameters is True.
+
+ @retval EFI_SUCCESS The function always return successfully.
+**/
+EFI_STATUS
+EFIAPI
+BoardEnableAcpi (
+ IN BOOLEAN EnableSci
+ )
+{
+ // @todo:enable additional board register
+ return EFI_SUCCESS;
+}
+
+/**
+ Disable Board Acpi
+
+ @param[in] DisableSci Disable SCI if DisableSci parameters is True.
+
+ @retval EFI_SUCCESS The function always return successfully.
+**/
+EFI_STATUS
+EFIAPI
+BoardDisableAcpi (
+ IN BOOLEAN DisableSci
+ )
+{
+ // @todo: enable additional board register
+ return EFI_SUCCESS;
+}
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/SmmMultiBoardAcpiSupportLib/SmmMultiBoardAcpiSupportLib.c b/Platform/Intel/AlderlakeOpenBoardPkg/SmmMultiBoardAcpiSupportLib/SmmMultiBoardAcpiSupportLib.c
new file mode 100644
index 0000000000..c278409e7b
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/SmmMultiBoardAcpiSupportLib/SmmMultiBoardAcpiSupportLib.c
@@ -0,0 +1,89 @@
+/** @file
+ SMM Multi-Board ACPI Support Library
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Base.h>
+#include <Uefi.h>
+#include <PiDxe.h>
+#include <Library/BaseLib.h>
+#include <Library/IoLib.h>
+#include <Library/BoardAcpiEnableLib.h>
+#include <Library/MultiBoardAcpiSupportLib.h>
+#include <Library/PcdLib.h>
+#include <Library/DebugLib.h>
+
+#include <PlatformBoardId.h>
+
+EFI_STATUS
+EFIAPI
+BoardEnableAcpi (
+ IN BOOLEAN EnableSci
+ );
+
+EFI_STATUS
+EFIAPI
+BoardDisableAcpi (
+ IN BOOLEAN DisableSci
+ );
+
+EFI_STATUS
+EFIAPI
+SiliconEnableAcpi (
+ IN BOOLEAN EnableSci
+ );
+
+EFI_STATUS
+EFIAPI
+SiliconDisableAcpi (
+ IN BOOLEAN DisableSci
+ );
+
+EFI_STATUS
+EFIAPI
+MultiBoardEnableAcpi (
+ IN BOOLEAN EnableSci
+ )
+{
+ SiliconEnableAcpi (EnableSci);
+ return BoardEnableAcpi (EnableSci);
+}
+
+EFI_STATUS
+EFIAPI
+MultiBoardDisableAcpi (
+ IN BOOLEAN DisableSci
+ )
+{
+ SiliconDisableAcpi (DisableSci);
+ return BoardDisableAcpi (DisableSci);
+}
+
+BOARD_ACPI_ENABLE_FUNC mBoardAcpiEnableFunc = {
+ MultiBoardEnableAcpi,
+ MultiBoardDisableAcpi,
+};
+
+/**
+ The constructor function to register mBoardAcpiEnableFunc function.
+
+ @param[in] ImageHandle The firmware allocated handle for the EFI image.
+ @param[in] SystemTable A pointer to the EFI System Table.
+
+ @retval EFI_SUCCESS This constructor always return EFI_SUCCESS.
+ It will ASSERT on errors.
+**/
+EFI_STATUS
+EFIAPI
+SmmMultiBoardAcpiSupportLibConstructor (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ DEBUG ((DEBUG_INFO, "SKU_ID: 0x%x\n", LibPcdGetSku()));
+ return RegisterBoardAcpiEnableFunc (&mBoardAcpiEnableFunc);
+}
+
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/SmmMultiBoardAcpiSupportLib/SmmMultiBoardAcpiSupportLib.inf b/Platform/Intel/AlderlakeOpenBoardPkg/SmmMultiBoardAcpiSupportLib/SmmMultiBoardAcpiSupportLib.inf
new file mode 100644
index 0000000000..ecea111b41
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/SmmMultiBoardAcpiSupportLib/SmmMultiBoardAcpiSupportLib.inf
@@ -0,0 +1,40 @@
+### @file
+# SMM Multi-Board ACPI Support Library
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+###
+
+[Defines]
+ INF_VERSION = 0x00010017
+ BASE_NAME = SmmMultiBoardAcpiSupportLib
+ FILE_GUID = 8929A54E-7ED8-4AB3-BEBB-C0367BDBBFF5
+ VERSION_STRING = 1.0
+ MODULE_TYPE = DXE_SMM_DRIVER
+ LIBRARY_CLASS = NULL
+ CONSTRUCTOR = SmmMultiBoardAcpiSupportLibConstructor
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = IA32 X64 IPF EBC
+#
+
+[LibraryClasses]
+ BaseLib
+ IoLib
+ PciLib
+ PchCycleDecodingLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ MinPlatformPkg/MinPlatformPkg.dec
+ AlderlakeOpenBoardPkg/OpenBoardPkg.dec
+ AlderlakeSiliconPkg/SiPkg.dec
+
+[Sources]
+ SmmAcpiEnableLib.c
+ SmmSiliconAcpiEnableLib.c
+ SmmMultiBoardAcpiSupportLib.c
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/SmmMultiBoardAcpiSupportLib/SmmSiliconAcpiEnableLib.c b/Platform/Intel/AlderlakeOpenBoardPkg/SmmMultiBoardAcpiSupportLib/SmmSiliconAcpiEnableLib.c
new file mode 100644
index 0000000000..38390305c4
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/SmmMultiBoardAcpiSupportLib/SmmSiliconAcpiEnableLib.c
@@ -0,0 +1,157 @@
+/** @file
+ SMM Silicon ACPI Support Library
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Base.h>
+#include <Uefi.h>
+#include <PiDxe.h>
+#include <Library/BaseLib.h>
+#include <Library/SmmServicesTableLib.h>
+#include <Library/IoLib.h>
+#include <Library/BoardAcpiEnableLib.h>
+#include <Library/PcdLib.h>
+#include <Library/DebugLib.h>
+#include <Library/PciSegmentLib.h>
+#include <Library/PchCycleDecodingLib.h>
+#include <Library/PmcLib.h>
+#include <Register/PchRegs.h>
+#include <Register/PchRegsLpc.h>
+#include <Register/PmcRegs.h>
+#include <Register/RtcRegs.h>
+#include <Library/PchPciBdfLib.h>
+
+//
+// Global variables
+//
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_SMM_SYSTEM_TABLE2 *mSmst;
+
+GLOBAL_REMOVE_IF_UNREFERENCED UINT16 mAcpiBaseAddr;
+
+/**
+
+**/
+EFI_STATUS
+EFIAPI
+SiliconEnableAcpi (
+ IN BOOLEAN EnableSci
+ )
+{
+ UINT32 OutputValue;
+ UINT32 SmiEn;
+ UINT32 SmiSts;
+ UINT32 ULKMC;
+ UINT32 Pm1Cnt;
+ EFI_STATUS Status;
+ UINT64 LpcBaseAddress;
+
+ LpcBaseAddress = LpcPciCfgBase ();
+
+ //
+ // Initialize global variables
+ //
+ mSmst = gSmst;
+
+ //
+ // Get the ACPI Base Address
+ //
+ mAcpiBaseAddr = PmcGetAcpiBase ();
+
+ Status = EFI_SUCCESS;
+ //
+ // BIOS must also ensure that CF9GR is cleared and locked before handing control to the
+ // OS in order to prevent the host from issuing global resets and resetting ME
+ //
+ // EDK2: To match PCCG current BIOS behavior, do not lock CF9 Global Reset
+ // MmioWrite32 (
+ // PmcBaseAddress + R_PCH_PMC_ETR3),
+ // PmInit);
+
+ //
+ // Clear Port 80h
+ //
+ OutputValue = 0;
+ mSmst->SmmIo.Io.Write (&mSmst->SmmIo, SMM_IO_UINT16, 0x80, 1, &OutputValue);
+ //
+ // Disable SW SMI Timer and clean the status
+ //
+ mSmst->SmmIo.Io.Read (&mSmst->SmmIo, SMM_IO_UINT32, mAcpiBaseAddr + R_ACPI_IO_SMI_EN, 1, &SmiEn);
+ SmiEn &= ~(B_ACPI_IO_SMI_EN_LEGACY_USB2 | B_ACPI_IO_SMI_EN_SWSMI_TMR | B_ACPI_IO_SMI_EN_LEGACY_USB);
+ mSmst->SmmIo.Io.Write (&mSmst->SmmIo, SMM_IO_UINT32, mAcpiBaseAddr + R_ACPI_IO_SMI_EN, 1, &SmiEn);
+
+ mSmst->SmmIo.Io.Read (&mSmst->SmmIo, SMM_IO_UINT32, mAcpiBaseAddr + R_ACPI_IO_SMI_STS, 1, &SmiSts);
+ SmiSts |= B_ACPI_IO_SMI_EN_LEGACY_USB2 | B_ACPI_IO_SMI_EN_SWSMI_TMR | B_ACPI_IO_SMI_EN_LEGACY_USB;
+ mSmst->SmmIo.Io.Write (&mSmst->SmmIo, SMM_IO_UINT32, mAcpiBaseAddr + R_ACPI_IO_SMI_STS, 1, &SmiSts);
+
+ //
+ // Disable port 60/64 SMI trap if they are enabled
+ //
+ ULKMC = PciSegmentRead32 (LpcBaseAddress + R_LPC_CFG_ULKMC);
+ ULKMC &= ~(B_LPC_CFG_ULKMC_60REN | B_LPC_CFG_ULKMC_60WEN | B_LPC_CFG_ULKMC_64REN | B_LPC_CFG_ULKMC_64WEN | B_LPC_CFG_ULKMC_A20PASSEN);
+ PciSegmentWrite32 (LpcBaseAddress + R_LPC_CFG_ULKMC, ULKMC);
+
+ //
+ // Disable PM sources except power button
+ //
+ OutputValue = B_ACPI_IO_PM1_EN_PWRBTN;
+ mSmst->SmmIo.Io.Write (&mSmst->SmmIo, SMM_IO_UINT16, mAcpiBaseAddr + R_ACPI_IO_PM1_EN, 1, &OutputValue);
+ //
+ // Clear PM status except Power Button status for RapidStart Resume
+ //
+ // OutputValue = 0xFFFF;
+ OutputValue = 0xFEFF;
+ mSmst->SmmIo.Io.Write (&mSmst->SmmIo, SMM_IO_UINT16, mAcpiBaseAddr + R_ACPI_IO_PM1_STS, 1, &OutputValue);
+
+ //
+ // Guarantee day-of-month alarm is invalid (ACPI 1.0 section 4.7.2.4)
+ //
+ OutputValue = R_RTC_IO_REGD;
+ mSmst->SmmIo.Io.Write (&mSmst->SmmIo, SMM_IO_UINT8, R_RTC_IO_INDEX_ALT, 1, &OutputValue);
+ OutputValue = 0x0;
+ mSmst->SmmIo.Io.Write (&mSmst->SmmIo, SMM_IO_UINT8, R_RTC_IO_TARGET_ALT, 1, &OutputValue);
+
+ //
+ // Enable SCI
+ //
+ if (EnableSci) {
+ mSmst->SmmIo.Io.Read (&mSmst->SmmIo, SMM_IO_UINT32, mAcpiBaseAddr + R_ACPI_IO_PM1_CNT, 1, &Pm1Cnt);
+ Pm1Cnt |= B_ACPI_IO_PM1_CNT_SCI_EN;
+ mSmst->SmmIo.Io.Write (&mSmst->SmmIo, SMM_IO_UINT32, mAcpiBaseAddr + R_ACPI_IO_PM1_CNT, 1, &Pm1Cnt);
+ }
+
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+EFIAPI
+SiliconDisableAcpi (
+ IN BOOLEAN DisableSci
+ )
+{
+ UINT32 Pm1Cnt;
+
+ //
+ // Initialize global variables
+ //
+ mSmst = gSmst;
+
+ //
+ // Get the ACPI Base Address
+ //
+ mAcpiBaseAddr = PmcGetAcpiBase ();
+
+
+ //
+ // Disable SCI
+ //
+ if (DisableSci) {
+ mSmst->SmmIo.Io.Read (&mSmst->SmmIo, SMM_IO_UINT32, mAcpiBaseAddr + R_ACPI_IO_PM1_CNT, 1, &Pm1Cnt);
+ Pm1Cnt &= ~B_ACPI_IO_PM1_CNT_SCI_EN;
+ mSmst->SmmIo.Io.Write (&mSmst->SmmIo, SMM_IO_UINT32, mAcpiBaseAddr + R_ACPI_IO_PM1_CNT, 1, &Pm1Cnt);
+ }
+
+ return EFI_SUCCESS;
+}
--
2.36.1.windows.1
^ permalink raw reply related [flat|nested] 6+ messages in thread* [PATCH 4/6] AlderlakeOpenBoardPkg: Add ACPI module
[not found] <cover.1686770061.git.saloni.kasbekar@intel.com>
` (2 preceding siblings ...)
2023-06-14 19:17 ` [PATCH 3/6] AlderlakeOpenBoardPkg/AlderlakePRvp: Add library instances Saloni Kasbekar
@ 2023-06-14 19:17 ` Saloni Kasbekar
2023-06-14 19:17 ` [PATCH 5/6] AlderlakeOpenBoardPkg: Adds the Policy Module Saloni Kasbekar
2023-06-14 19:17 ` [PATCH 6/6] AlderlakeOpenBoardPkg: Add Library Instances Saloni Kasbekar
5 siblings, 0 replies; 6+ messages in thread
From: Saloni Kasbekar @ 2023-06-14 19:17 UTC (permalink / raw)
To: devel
Cc: Saloni Kasbekar, Sai Chaganty, Nate DeSimone, Isaac Oram,
Rosen Chuang
Adds AcpiTables and AdvancedAcpiDxe drivers
Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Isaac Oram <isaac.w.oram@intel.com>
Cc: Rosen Chuang <rosen.chuang@intel.com>
Signed-off-by: Saloni Kasbekar <saloni.kasbekar@intel.com>
---
.../Acpi/AcpiTables/AcpiTables.inf | 68 +
.../Acpi/AcpiTables/Dsdt/Dsdt.asl | 32 +
.../Acpi/AcpiTables/Dsdt/PciTree.asl | 17 +
.../Acpi/AcpiTables/Ecdt/Ecdt.act | 103 +
.../Acpi/AcpiTables/Ecdt/Ecdt.h | 26 +
.../Acpi/AcpiTables/Facs/Facs.act | 91 +
.../Acpi/AcpiTables/Facs/Facs.h | 34 +
.../Acpi/AcpiTables/Fadt/Fadt6.3.act | 236 +++
.../Acpi/AcpiTables/Fadt/Fadt6.3.h | 184 ++
.../Acpi/AcpiTables/Hpet/Hpet.act | 77 +
.../Acpi/AcpiTables/Hpet/Hpet.h | 43 +
.../Acpi/AcpiTables/Include/AcpiCommon.h | 16 +
.../Acpi/AcpiTables/Madt/Madt.act | 573 ++++++
.../Acpi/AcpiTables/Madt/Madt.h | 226 +++
.../Acpi/AcpiTables/Madt/MadtX2Apic.act | 522 +++++
.../Acpi/AcpiTables/Mcfg/Mcfg.act | 91 +
.../Acpi/AcpiTables/Mcfg/Mcfg.h | 53 +
.../Acpi/AdvancedAcpiDxe/AcpiByteStream.h | 137 ++
.../Acpi/AdvancedAcpiDxe/AcpiPlatform.c | 1716 +++++++++++++++++
.../Acpi/AdvancedAcpiDxe/AcpiPlatform.h | 142 ++
.../Acpi/AdvancedAcpiDxe/AdvancedAcpiDxe.inf | 154 ++
.../Acpi/AdvancedAcpiDxe/GenSsdtLib.c | 474 +++++
.../Acpi/AdvancedAcpiDxe/GenSsdtLib.h | 17 +
23 files changed, 5032 insertions(+)
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AcpiTables/AcpiTables.inf
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AcpiTables/Dsdt/Dsdt.asl
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AcpiTables/Dsdt/PciTree.asl
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AcpiTables/Ecdt/Ecdt.act
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AcpiTables/Ecdt/Ecdt.h
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AcpiTables/Facs/Facs.act
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AcpiTables/Facs/Facs.h
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AcpiTables/Fadt/Fadt6.3.act
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AcpiTables/Fadt/Fadt6.3.h
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AcpiTables/Hpet/Hpet.act
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AcpiTables/Hpet/Hpet.h
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AcpiTables/Include/AcpiCommon.h
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AcpiTables/Madt/Madt.act
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AcpiTables/Madt/Madt.h
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AcpiTables/Madt/MadtX2Apic.act
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AcpiTables/Mcfg/Mcfg.act
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AcpiTables/Mcfg/Mcfg.h
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AdvancedAcpiDxe/AcpiByteStream.h
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AdvancedAcpiDxe/AcpiPlatform.c
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AdvancedAcpiDxe/AcpiPlatform.h
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AdvancedAcpiDxe/AdvancedAcpiDxe.inf
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AdvancedAcpiDxe/GenSsdtLib.c
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AdvancedAcpiDxe/GenSsdtLib.h
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AcpiTables/AcpiTables.inf b/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AcpiTables/AcpiTables.inf
new file mode 100644
index 0000000000..ccf1f3f69b
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AcpiTables/AcpiTables.inf
@@ -0,0 +1,68 @@
+### @file
+# Component information file for the ACPI tables
+#
+# Copyright (c) 1999 - 2021, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+###
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = AcpiTables
+ FILE_GUID = 7E374E25-8E01-4FEE-87F2-390C23C606CD
+ MODULE_TYPE = USER_DEFINED
+ VERSION_STRING = 1.0
+
+[Sources]
+ Fadt/Fadt6.3.act
+ Facs/Facs.act
+ Hpet/Hpet.act
+ Madt/Madt.act
+ Madt/MadtX2Apic.act
+ Mcfg/Mcfg.act
+ Ecdt/Ecdt.act
+ Dsdt/Dsdt.asl
+
+################################################################################
+#
+# Package Dependency Section - list of Package files that are required for
+# this module.
+#
+################################################################################
+[Packages]
+ MdePkg/MdePkg.dec
+ AlderlakeSiliconPkg/SiPkg.dec
+ AlderlakeOpenBoardPkg/OpenBoardPkg.dec
+ PcAtChipsetPkg/PcAtChipsetPkg.dec
+
+################################################################################
+#
+# Library Class Section - list of Library Classes that are required for
+# this module.
+#
+################################################################################
+
+[LibraryClasses]
+
+[FixedPcd]
+ gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress ## CONSUMES
+ gSiPkgTokenSpaceGuid.PcdTcoBaseAddress ## CONSUMES
+ gPlatformModuleTokenSpaceGuid.PcdApicLocalAddress ## CONSUMES
+ gPlatformModuleTokenSpaceGuid.PcdApicIoAddress ## CONSUMES
+ gPlatformModuleTokenSpaceGuid.PcdAcpiEnableSwSmi ## CONSUMES
+ gPlatformModuleTokenSpaceGuid.PcdAcpiDisableSwSmi ## CONSUMES
+ gPlatformModuleTokenSpaceGuid.PcdApicIoIdPch ## CONSUMES
+
+################################################################################
+#
+# Protocol C Name Section - list of Protocol and Protocol Notify C Names
+# that this module uses or produces.
+#
+################################################################################
+[Protocols]
+
+[PPIs]
+
+[Guids]
+
+[Depex]
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AcpiTables/Dsdt/Dsdt.asl b/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AcpiTables/Dsdt/Dsdt.asl
new file mode 100644
index 0000000000..5a5a8698d6
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AcpiTables/Dsdt/Dsdt.asl
@@ -0,0 +1,32 @@
+/** @file
+ ACPI DSDT table
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "PlatformBoardId.h"
+#include <Include/AcpiDebug.h>
+
+
+DefinitionBlock (
+ "DSDT.aml",
+ "DSDT",
+ 0x02, // DSDT revision.
+ // A Revision field value greater than or equal to 2 signifies that integers
+ // declared within the Definition Block are to be evaluated as 64-bit values
+ "INTEL", // OEM ID (6 byte string)
+ "SKL ",// OEM table ID (8 byte string)
+ 0x0 // OEM version of DSDT table (4 byte Integer)
+)
+
+// BEGIN OF ASL SCOPE
+{
+ Name (SANB, 0xFFFF0000) // SA NVS Base address
+ Name (SANL, 0xAA55) // SA NVS Length
+
+ Include ("SaNvs.asl")
+ Include ("PciTree.asl")
+
+}// End of ASL File
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AcpiTables/Dsdt/PciTree.asl b/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AcpiTables/Dsdt/PciTree.asl
new file mode 100644
index 0000000000..bef0b6cccd
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AcpiTables/Dsdt/PciTree.asl
@@ -0,0 +1,17 @@
+/** @file
+ ACPI DSDT table
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+Scope(\_SB) {
+//---------------------------------------------------------------------------
+// Begin PCI tree object scope
+//---------------------------------------------------------------------------
+ Device(PC00) { // PCI Bridge "Host Bridge"
+ Name(_HID, EISAID("PNP0A08")) // Indicates PCI Express/PCI-X Mode2 host hierarchy
+ Include("HostBus.asl")
+ } // end PC00 Bridge "Host Bridge"
+} // end _SB scope
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AcpiTables/Ecdt/Ecdt.act b/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AcpiTables/Ecdt/Ecdt.act
new file mode 100644
index 0000000000..3e30b41d11
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AcpiTables/Ecdt/Ecdt.act
@@ -0,0 +1,103 @@
+/** @file
+ This file contains a structure definition for the ACPI Embedded Controller Boot
+ Resources Table (ECDT). The contents of this file should only be modified
+ for bug fixes, no porting is required.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+//
+// Statements that include other files
+//
+
+#include "Ecdt.h"
+
+//
+// Embedded Controller Boot Resources Table Structure
+//
+#pragma pack(1)
+typedef struct {
+ EFI_ACPI_5_0_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE ActionTable;
+ //
+ // ASCII, null terminated, string that contains a fully qualified
+ // reference to the namespace object that is this embedded controller device.
+ //
+ CHAR8 Ec_Id[40];
+} EFI_ACPI_EMBEDDED_CONTROLLER_BOOT_RESOURCES_ENTIRE_TABLE;
+#pragma pack()
+
+EFI_ACPI_EMBEDDED_CONTROLLER_BOOT_RESOURCES_ENTIRE_TABLE Ecdt = {
+ {
+ {
+ EFI_ACPI_5_0_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE_SIGNATURE,
+ sizeof (EFI_ACPI_5_0_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE) + 40,
+ EFI_ACPI_5_0_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE_REVISION,
+
+ //
+ // Checksum will be updated at runtime
+ //
+ 0x00,
+
+ //
+ // It is expected that these values will be updated at runtime
+ //
+ { ' ', ' ', ' ', ' ', ' ', ' ' },
+
+ 0,
+ EFI_ACPI_OEM_ECDT_REVISION,
+ 0,
+ 0
+ },
+
+ //
+ // EC_CONTROL Register Block
+ //
+ {
+ EFI_ACPI_5_0_SYSTEM_IO,
+ 8,
+ 0,
+ EFI_ACPI_RESERVED_BYTE,
+ 0x66
+ },
+
+ //
+ // EC_DATA Register Block
+ //
+ {
+ EFI_ACPI_5_0_SYSTEM_IO,
+ 8,
+ 0,
+ EFI_ACPI_RESERVED_BYTE,
+ 0x62
+ },
+
+ 1, // UID
+ 0 // GPE_BIT
+ },
+ "\\_SB.PC00.LPCB.H_EC" //EC_ID
+};
+
+#ifdef __GNUC__
+VOID*
+ReferenceAcpiTable (
+ VOID
+ )
+
+{
+ //
+ // Reference the table being generated to prevent the optimizer from removing the
+ // data structure from the exeutable
+ //
+ return (VOID*)&Ecdt;
+}
+#else
+VOID
+main (
+ VOID
+ )
+
+{
+}
+#endif
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AcpiTables/Ecdt/Ecdt.h b/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AcpiTables/Ecdt/Ecdt.h
new file mode 100644
index 0000000000..4afa4874d2
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AcpiTables/Ecdt/Ecdt.h
@@ -0,0 +1,26 @@
+/** @file
+ This file describes the contents of the ACPI Embedded Controller Boot
+ Resources Table (ECDT). All changes to the ECDT contents should be done
+ in this file.
+
+ Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+
+**/
+
+#ifndef _ECDT_H_
+#define _ECDT_H_
+
+//
+// Statements that include other files
+//
+
+#include <IndustryStandard/Acpi.h>
+
+//
+// ECDT Definitions
+//
+#define EFI_ACPI_OEM_ECDT_REVISION 0x00000001
+
+#endif
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AcpiTables/Facs/Facs.act b/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AcpiTables/Facs/Facs.act
new file mode 100644
index 0000000000..fde17b577c
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AcpiTables/Facs/Facs.act
@@ -0,0 +1,91 @@
+/** @file
+ This file contains a structure definition for the ACPI 5.0 Firmware ACPI
+ Control Structure (FACS). The contents of this file should only be modified
+ for bug fixes, no porting is required.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+//
+// Statements that include other files
+//
+
+#include "Facs.h"
+
+//
+// Firmware ACPI Control Structure
+// Please modify all values in Facs.h only.
+//
+
+EFI_ACPI_5_0_FIRMWARE_ACPI_CONTROL_STRUCTURE Facs = {
+ EFI_ACPI_5_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE,
+ sizeof (EFI_ACPI_5_0_FIRMWARE_ACPI_CONTROL_STRUCTURE),
+
+ //
+ // Hardware Signature will be updated at runtime
+ //
+ 0x00000000,
+
+ EFI_ACPI_FIRMWARE_WAKING_VECTOR,
+ EFI_ACPI_GLOBAL_LOCK,
+ EFI_ACPI_FIRMWARE_CONTROL_STRUCTURE_FLAGS,
+ EFI_ACPI_X_FIRMWARE_WAKING_VECTOR,
+ EFI_ACPI_5_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_VERSION,
+ {
+ EFI_ACPI_RESERVED_BYTE,
+ EFI_ACPI_RESERVED_BYTE,
+ EFI_ACPI_RESERVED_BYTE
+ },
+ EFI_ACPI_RESERVED_DWORD, //EFI_ACPI_5_0_OSPM_64BIT_WAKE_F
+ {
+ EFI_ACPI_RESERVED_BYTE,
+ EFI_ACPI_RESERVED_BYTE,
+ EFI_ACPI_RESERVED_BYTE,
+ EFI_ACPI_RESERVED_BYTE,
+ EFI_ACPI_RESERVED_BYTE,
+ EFI_ACPI_RESERVED_BYTE,
+ EFI_ACPI_RESERVED_BYTE,
+ EFI_ACPI_RESERVED_BYTE,
+ EFI_ACPI_RESERVED_BYTE,
+ EFI_ACPI_RESERVED_BYTE,
+ EFI_ACPI_RESERVED_BYTE,
+ EFI_ACPI_RESERVED_BYTE,
+ EFI_ACPI_RESERVED_BYTE,
+ EFI_ACPI_RESERVED_BYTE,
+ EFI_ACPI_RESERVED_BYTE,
+ EFI_ACPI_RESERVED_BYTE,
+ EFI_ACPI_RESERVED_BYTE,
+ EFI_ACPI_RESERVED_BYTE,
+ EFI_ACPI_RESERVED_BYTE,
+ EFI_ACPI_RESERVED_BYTE,
+ EFI_ACPI_RESERVED_BYTE,
+ EFI_ACPI_RESERVED_BYTE,
+ EFI_ACPI_RESERVED_BYTE,
+ EFI_ACPI_RESERVED_BYTE
+ }
+};
+
+#ifdef __GNUC__
+VOID*
+ReferenceAcpiTable (
+ VOID
+ )
+
+{
+ //
+ // Reference the table being generated to prevent the optimizer from removing the
+ // data structure from the exeutable
+ //
+ return (VOID*)&Facs;
+}
+#else
+VOID
+main (
+ VOID
+ )
+
+{
+}
+#endif
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AcpiTables/Facs/Facs.h b/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AcpiTables/Facs/Facs.h
new file mode 100644
index 0000000000..711d952583
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AcpiTables/Facs/Facs.h
@@ -0,0 +1,34 @@
+/** @file
+ This file describes the contents of the ACPI Firmware ACPI Control
+ Structure (FACS). All changes to the FACS contents should be done
+ in this file.
+
+ Copyright (c) 1999 - 2017, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _FACS_H_
+#define _FACS_H_
+
+//
+// Statements that include other files
+//
+
+#include <IndustryStandard/Acpi.h>
+
+//
+// FACS Definitions
+//
+
+#define EFI_ACPI_FIRMWARE_WAKING_VECTOR 0x00000000
+#define EFI_ACPI_GLOBAL_LOCK 0x00000000
+
+//
+// Firmware Control Structure Feature Flags are defined in AcpiX.0.h
+//
+#define EFI_ACPI_FIRMWARE_CONTROL_STRUCTURE_FLAGS 0x00000000
+
+#define EFI_ACPI_X_FIRMWARE_WAKING_VECTOR 0x0000000000000000
+
+#endif
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AcpiTables/Fadt/Fadt6.3.act b/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AcpiTables/Fadt/Fadt6.3.act
new file mode 100644
index 0000000000..5acc63d744
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AcpiTables/Fadt/Fadt6.3.act
@@ -0,0 +1,236 @@
+/** @file
+ This file contains a structure definition for the ACPI 6.1 Fixed ACPI
+ Description Table (FADT). The contents of this file should only be modified
+ for bug fixes, no porting is required.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+//
+// Statements that include other files
+//
+
+#include "Fadt6.3.h"
+
+//
+// Fixed ACPI Description Table
+// Please modify all values in Fadt.h only.
+//
+
+EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE Fadt = {
+ {
+ EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE,
+ sizeof (EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE),
+ EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE_REVISION,
+
+ //
+ // Checksum will be updated at runtime
+ //
+ 0x00,
+
+ //
+ // It is expected that these values will be updated at runtime
+ //
+ { ' ', ' ', ' ', ' ', ' ', ' ' },
+
+ 0,
+ EFI_ACPI_OEM_FADT_REVISION,
+ 0,
+ 0
+ },
+
+ //
+ // These addresses will be updated at runtime
+ //
+ 0x00000000,
+ 0x00000000,
+
+ EFI_ACPI_RESERVED_BYTE,
+ EFI_ACPI_PREFERRED_PM_PROFILE,
+ EFI_ACPI_SCI_INT,
+ EFI_ACPI_SMI_CMD,
+ FixedPcdGet8 (PcdAcpiEnableSwSmi),
+ FixedPcdGet8 (PcdAcpiDisableSwSmi),
+ EFI_ACPI_S4_BIOS_REQ,
+ EFI_ACPI_PSTATE_CNT,
+
+ EFI_ACPI_PM1A_EVT_BLK_ADDRESS,
+ EFI_ACPI_PM1B_EVT_BLK_ADDRESS,
+ EFI_ACPI_PM1A_CNT_BLK_ADDRESS,
+ EFI_ACPI_PM1B_CNT_BLK_ADDRESS,
+ EFI_ACPI_PM2_CNT_BLK_ADDRESS,
+ EFI_ACPI_PM_TMR_BLK_ADDRESS,
+ EFI_ACPI_GPE0_BLK_ADDRESS,
+ EFI_ACPI_GPE1_BLK_ADDRESS,
+ EFI_ACPI_PM1_EVT_LEN,
+ EFI_ACPI_PM1_CNT_LEN,
+ EFI_ACPI_PM2_CNT_LEN,
+ EFI_ACPI_PM_TMR_LEN,
+ EFI_ACPI_GPE0_BLK_LEN,
+ EFI_ACPI_GPE1_BLK_LEN,
+ EFI_ACPI_GPE1_BASE,
+
+ //
+ // Latest OS have C-State capability and CST_CNT SMI doesn't need to be defined.
+ // CST_CNT SMI is not handled in BIOS and it can be removed safely.
+ //
+ EFI_ACPI_CST_CNT,
+ EFI_ACPI_P_LVL2_LAT,
+ EFI_ACPI_P_LVL3_LAT,
+ EFI_ACPI_FLUSH_SIZE,
+ EFI_ACPI_FLUSH_STRIDE,
+ EFI_ACPI_DUTY_OFFSET,
+ EFI_ACPI_DUTY_WIDTH,
+ EFI_ACPI_DAY_ALRM,
+ EFI_ACPI_MON_ALRM,
+ EFI_ACPI_CENTURY,
+ EFI_ACPI_IAPC_BOOT_ARCH,
+ EFI_ACPI_RESERVED_BYTE,
+ EFI_ACPI_FIXED_FEATURE_FLAGS,
+
+ //
+ // Reset Register Block
+ //
+ {
+ EFI_ACPI_RESET_REG_ADDRESS_SPACE_ID,
+ EFI_ACPI_RESET_REG_BIT_WIDTH,
+ EFI_ACPI_RESET_REG_BIT_OFFSET,
+ EFI_ACPI_6_3_BYTE,
+ EFI_ACPI_RESET_REG_ADDRESS
+ },
+ EFI_ACPI_RESET_VALUE,
+ 0, // ArmBootArch
+ EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE_MINOR_REVISION,
+
+ //
+ // These addresses will be updated at runtime
+ //
+ 0x0000000000000000, // X_FIRMWARE_CTRL
+ 0x0000000000000000, // X_DSDT
+
+ {
+ //
+ // X_PM1a Event Register Block
+ //
+ EFI_ACPI_PM1A_EVT_BLK_ADDRESS_SPACE_ID,
+ EFI_ACPI_PM1A_EVT_BLK_BIT_WIDTH,
+ EFI_ACPI_PM1A_EVT_BLK_BIT_OFFSET,
+ EFI_ACPI_6_3_WORD,
+ EFI_ACPI_PM1A_EVT_BLK_ADDRESS
+ },
+ {
+ //
+ // X_PM1b Event Register Block
+ //
+ EFI_ACPI_PM1B_EVT_BLK_ADDRESS_SPACE_ID,
+ EFI_ACPI_PM1B_EVT_BLK_BIT_WIDTH,
+ EFI_ACPI_PM1B_EVT_BLK_BIT_OFFSET,
+ EFI_ACPI_6_3_WORD,
+ EFI_ACPI_PM1B_EVT_BLK_ADDRESS
+ },
+ {
+ //
+ // X_PM1a Control Register Block
+ //
+ EFI_ACPI_PM1A_CNT_BLK_ADDRESS_SPACE_ID,
+ EFI_ACPI_PM1A_CNT_BLK_BIT_WIDTH,
+ EFI_ACPI_PM1A_CNT_BLK_BIT_OFFSET,
+ EFI_ACPI_6_3_WORD,
+ EFI_ACPI_PM1A_CNT_BLK_ADDRESS
+ },
+ {
+ //
+ // X_PM1b Control Register Block
+ //
+ EFI_ACPI_PM1B_CNT_BLK_ADDRESS_SPACE_ID,
+ EFI_ACPI_PM1B_CNT_BLK_BIT_WIDTH,
+ EFI_ACPI_PM1B_CNT_BLK_BIT_OFFSET,
+ EFI_ACPI_6_3_WORD,
+ EFI_ACPI_PM1B_CNT_BLK_ADDRESS
+ },
+ {
+ //
+ // X_PM2 Control Register Block
+ //
+ EFI_ACPI_PM2_CNT_BLK_ADDRESS_SPACE_ID,
+ EFI_ACPI_PM2_CNT_BLK_BIT_WIDTH,
+ EFI_ACPI_PM2_CNT_BLK_BIT_OFFSET,
+ EFI_ACPI_6_3_BYTE,
+ EFI_ACPI_PM2_CNT_BLK_ADDRESS
+ },
+ {
+ //
+ // X_PM Timer Control Register Block
+ //
+ EFI_ACPI_PM_TMR_BLK_ADDRESS_SPACE_ID,
+ EFI_ACPI_PM_TMR_BLK_BIT_WIDTH,
+ EFI_ACPI_PM_TMR_BLK_BIT_OFFSET,
+ EFI_ACPI_6_3_DWORD,
+ EFI_ACPI_PM_TMR_BLK_ADDRESS
+ },
+ {
+ //
+ // X_General Purpose Event 0 Register Block
+ //
+ EFI_ACPI_GPE0_BLK_ADDRESS_SPACE_ID,
+ 0x0,
+ EFI_ACPI_GPE0_BLK_BIT_OFFSET,
+ EFI_ACPI_6_3_BYTE,
+ EFI_ACPI_GPE0_BLK_ADDRESS
+ },
+ {
+ //
+ // X_General Purpose Event 1 Register Block
+ //
+ EFI_ACPI_GPE1_BLK_ADDRESS_SPACE_ID,
+ EFI_ACPI_GPE1_BLK_BIT_WIDTH,
+ EFI_ACPI_GPE1_BLK_BIT_OFFSET,
+ EFI_ACPI_6_3_BYTE,
+ EFI_ACPI_GPE1_BLK_ADDRESS
+ },
+ {
+ //
+ // Sleep Control Reg - update in DXE driver
+ //
+ 0,
+ 0,
+ 0,
+ 0,
+ 0
+ },
+ {
+ //
+ // Sleep Status Reg - update in DXE driver
+ //
+ 0,
+ 0,
+ 0,
+ 0,
+ 0
+ },
+ 0 // HypervisorVendorIdentity
+};
+
+#ifdef __GNUC__
+VOID*
+ReferenceAcpiTable (
+ VOID
+ )
+
+{
+ //
+ // Reference the table being generated to prevent the optimizer from removing the
+ // data structure from the exeutable
+ //
+ return (VOID*)&Fadt;
+}
+#else
+VOID
+main (
+ VOID
+ )
+{
+}
+#endif
\ No newline at end of file
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AcpiTables/Fadt/Fadt6.3.h b/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AcpiTables/Fadt/Fadt6.3.h
new file mode 100644
index 0000000000..e2dffeb13c
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AcpiTables/Fadt/Fadt6.3.h
@@ -0,0 +1,184 @@
+/** @file
+ This file describes the contents of the ACPI Fixed ACPI Description Table
+ (FADT). All changes to the FADT contents should be done in this file.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _FADT_H_
+#define _FADT_H_
+
+//
+// Statements that include other files
+//
+
+#include <IndustryStandard/Acpi.h>
+
+#include "Register/PmcRegs.h"
+#include "Register/TcoRegs.h"
+
+//
+// FADT Definitions
+//
+#ifndef EFI_ACPI_OEM_FADT_REVISION
+#define EFI_ACPI_OEM_FADT_REVISION 0x00000000
+#endif
+
+//
+// For ACPI 1.0 support
+//
+/*
+1 Desktop
+2 Mobile
+3 Workstation
+4 Enterprise Server
+5 SOHO Server
+6 Appliance PC
+7 Performance Server
+*/
+#define EFI_ACPI_PREFERRED_PM_PROFILE 0x01
+#define EFI_ACPI_SCI_INT 0x0009
+#define EFI_ACPI_SMI_CMD 0x000000B2
+#define EFI_ACPI_S4_BIOS_REQ 0xF2
+#define EFI_ACPI_PSTATE_CNT 0x00
+#define EFI_ACPI_GPE1_BASE 0x10
+#define EFI_ACPI_CST_CNT 0x0
+#define EFI_ACPI_P_LVL2_LAT 101
+#define EFI_ACPI_P_LVL3_LAT 1001
+#define EFI_ACPI_FLUSH_SIZE 0x0000
+#define EFI_ACPI_FLUSH_STRIDE 0x0000
+#define EFI_ACPI_DUTY_OFFSET 0x01
+#define EFI_ACPI_DUTY_WIDTH 0x03
+#define EFI_ACPI_DAY_ALRM 0x0D
+#define EFI_ACPI_MON_ALRM 0x00
+#define EFI_ACPI_CENTURY 0x32
+
+//
+// IA-PC Boot Architecture Flags, see ACPI 6.3 table specification and Acpi61.h
+// We should not use EFI_ACPI_6_3_8042 for legacy free platform, or XP reset fail. No impact to mobile.
+//
+#define EFI_ACPI_IAPC_BOOT_ARCH (EFI_ACPI_6_3_LEGACY_DEVICES)
+
+//
+// Fixed Feature Flags, see ACPI 6.3 table specification and Acpi6_3.h
+//
+#define EFI_ACPI_FIXED_FEATURE_FLAGS (\
+ EFI_ACPI_6_3_USE_PLATFORM_CLOCK | \
+ EFI_ACPI_6_3_WBINVD | \
+ EFI_ACPI_6_3_DCK_CAP | \
+ EFI_ACPI_6_3_FIX_RTC | \
+ EFI_ACPI_6_3_RTC_S4 | \
+ EFI_ACPI_6_3_SLP_BUTTON | \
+ EFI_ACPI_6_3_PROC_C1 | \
+ EFI_ACPI_6_3_RESET_REG_SUP \
+ )
+
+//
+// PM1A Event Register Block Generic Address Information
+//
+#define EFI_ACPI_PM1A_EVT_BLK_ADDRESS_SPACE_ID EFI_ACPI_6_3_SYSTEM_IO
+#define EFI_ACPI_PM1A_EVT_BLK_BIT_WIDTH 0x20
+#define EFI_ACPI_PM1A_EVT_BLK_BIT_OFFSET 0x00
+#define EFI_ACPI_PM1A_EVT_BLK_ADDRESS FixedPcdGet16 (PcdAcpiBaseAddress)
+
+//
+// PM1B Event Register Block Generic Address Information
+//
+#define EFI_ACPI_PM1B_EVT_BLK_ADDRESS_SPACE_ID EFI_ACPI_6_3_SYSTEM_IO
+#define EFI_ACPI_PM1B_EVT_BLK_BIT_WIDTH 0x00
+#define EFI_ACPI_PM1B_EVT_BLK_BIT_OFFSET 0x00
+#define EFI_ACPI_PM1B_EVT_BLK_ADDRESS 0x0000000000000000
+
+//
+// PM1A Control Register Block Generic Address Information
+//
+#define EFI_ACPI_PM1A_CNT_BLK_ADDRESS_SPACE_ID EFI_ACPI_6_3_SYSTEM_IO
+#define EFI_ACPI_PM1A_CNT_BLK_BIT_WIDTH 0x10
+#define EFI_ACPI_PM1A_CNT_BLK_BIT_OFFSET 0x00
+#define EFI_ACPI_PM1A_CNT_BLK_ADDRESS (EFI_ACPI_PM1A_EVT_BLK_ADDRESS + 0x04)
+
+//
+// PM1B Control Register Block Generic Address Information
+//
+#define EFI_ACPI_PM1B_CNT_BLK_ADDRESS_SPACE_ID EFI_ACPI_6_3_SYSTEM_IO
+#define EFI_ACPI_PM1B_CNT_BLK_BIT_WIDTH 0x00
+#define EFI_ACPI_PM1B_CNT_BLK_BIT_OFFSET 0x00
+#define EFI_ACPI_PM1B_CNT_BLK_ADDRESS 0x0000000000000000
+
+//
+// PM2 Control Register Block Generic Address Information
+//
+#define EFI_ACPI_PM2_CNT_BLK_ADDRESS_SPACE_ID EFI_ACPI_6_3_SYSTEM_IO
+#define EFI_ACPI_PM2_CNT_BLK_BIT_WIDTH 0x08
+#define EFI_ACPI_PM2_CNT_BLK_BIT_OFFSET 0x00
+#define EFI_ACPI_PM2_CNT_BLK_ADDRESS (EFI_ACPI_PM1A_EVT_BLK_ADDRESS + 0x50)
+
+//
+// Power Management Timer Control Register Block Generic Address
+// Information
+//
+#define EFI_ACPI_PM_TMR_BLK_ADDRESS_SPACE_ID EFI_ACPI_6_3_SYSTEM_IO
+#define EFI_ACPI_PM_TMR_BLK_BIT_WIDTH 0x20
+#define EFI_ACPI_PM_TMR_BLK_BIT_OFFSET 0x00
+#define EFI_ACPI_PM_TMR_BLK_ADDRESS (EFI_ACPI_PM1A_EVT_BLK_ADDRESS + 0x08)
+
+//
+// General Purpose Event 0 Register Block Generic Address
+// Information
+//
+#define EFI_ACPI_GPE0_BLK_ADDRESS_SPACE_ID EFI_ACPI_6_3_SYSTEM_IO
+#define EFI_ACPI_GPE0_BLK_BIT_WIDTH 0x100
+#define EFI_ACPI_GPE0_BLK_BIT_OFFSET 0x00
+#define EFI_ACPI_GPE0_BLK_ADDRESS 0x00
+
+//
+// General Purpose Event 1 Register Block Generic Address
+// Information
+//
+#define EFI_ACPI_GPE1_BLK_ADDRESS_SPACE_ID EFI_ACPI_6_3_SYSTEM_IO
+#define EFI_ACPI_GPE1_BLK_BIT_WIDTH 0x00
+#define EFI_ACPI_GPE1_BLK_BIT_OFFSET 0x00
+#define EFI_ACPI_GPE1_BLK_ADDRESS 0x0000000000000000
+
+//
+// Reset Register Generic Address Information
+//
+#define EFI_ACPI_RESET_REG_ADDRESS_SPACE_ID EFI_ACPI_6_3_SYSTEM_IO
+#define EFI_ACPI_RESET_REG_BIT_WIDTH 0x08
+#define EFI_ACPI_RESET_REG_BIT_OFFSET 0x00
+#define EFI_ACPI_RESET_REG_ADDRESS 0x0000000000000CF9
+#define EFI_ACPI_RESET_VALUE 0x06
+
+//
+// Number of bytes decoded by PM1 event blocks (a and b)
+//
+#define EFI_ACPI_PM1_EVT_LEN ((EFI_ACPI_PM1A_EVT_BLK_BIT_WIDTH + EFI_ACPI_PM1B_EVT_BLK_BIT_WIDTH) / 8)
+
+//
+// Number of bytes decoded by PM1 control blocks (a and b)
+//
+#define EFI_ACPI_PM1_CNT_LEN ((EFI_ACPI_PM1A_CNT_BLK_BIT_WIDTH + EFI_ACPI_PM1B_CNT_BLK_BIT_WIDTH) / 8)
+
+//
+// Number of bytes decoded by PM2 control block
+//
+#define EFI_ACPI_PM2_CNT_LEN (EFI_ACPI_PM2_CNT_BLK_BIT_WIDTH / 8)
+
+//
+// Number of bytes decoded by PM timer block
+//
+#define EFI_ACPI_PM_TMR_LEN (EFI_ACPI_PM_TMR_BLK_BIT_WIDTH / 8)
+
+//
+// Number of bytes decoded by GPE0 block
+//
+#define EFI_ACPI_GPE0_BLK_LEN (EFI_ACPI_GPE0_BLK_BIT_WIDTH / 8)
+
+//
+// Number of bytes decoded by GPE1 block
+//
+#define EFI_ACPI_GPE1_BLK_LEN (EFI_ACPI_GPE1_BLK_BIT_WIDTH / 8)
+
+#endif
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AcpiTables/Hpet/Hpet.act b/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AcpiTables/Hpet/Hpet.act
new file mode 100644
index 0000000000..c4b87cecdd
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AcpiTables/Hpet/Hpet.act
@@ -0,0 +1,77 @@
+/** @file
+ This file contains a structure definition for the ACPI 1.0 High Precision Event Timer
+ Description Table (HPET). The contents of this file should only be modified
+ for bug fixes, no porting is required.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+//
+// Statements that include other files
+//
+
+#include "Hpet.h"
+
+//
+// High Precision Event Timer Table
+// Please modify all values in Hpet.h only.
+//
+
+EFI_ACPI_HIGH_PRECISION_EVENT_TIMER_TABLE_HEADER Fadt = {
+ {
+ EFI_ACPI_3_0_HIGH_PRECISION_EVENT_TIMER_TABLE_SIGNATURE,
+ sizeof (EFI_ACPI_HIGH_PRECISION_EVENT_TIMER_TABLE_HEADER),
+ EFI_ACPI_HIGH_PRECISION_EVENT_TIMER_TABLE_REVISION,
+
+ //
+ // Checksum will be updated at runtime
+ //
+ 0x00,
+
+ //
+ // It is expected that these values will be updated at runtime
+ //
+ { ' ', ' ', ' ', ' ', ' ', ' ' },
+
+ 0,
+ EFI_ACPI_OEM_HPET_REVISION,
+ 0,
+ 0
+ },
+
+ EFI_ACPI_EVENT_TIMER_BLOCK_ID,
+ {
+ EFI_ACPI_EVENT_TIMER_BLOCK_ADDRESS_SPACE_ID,
+ EFI_ACPI_EVENT_TIMER_BLOCK_BIT_WIDTH,
+ EFI_ACPI_EVENT_TIMER_BLOCK_BIT_OFFSET,
+ EFI_ACPI_EVENT_TIMER_ACCESS_SIZE,
+ EFI_ACPI_EVENT_TIMER_BLOCK_ADDRESS
+ },
+ EFI_ACPI_HPET_NUMBER,
+ EFI_ACPI_MIN_CLOCK_TICK,
+ EFI_ACPI_HPET_ATTRIBUTES
+};
+
+#ifdef __GNUC__
+VOID*
+ReferenceAcpiTable (
+ VOID
+ )
+
+{
+ //
+ // Reference the table being generated to prevent the optimizer from removing the
+ // data structure from the exeutable
+ //
+ return (VOID*)&Fadt;
+}
+#else
+VOID
+main (
+ VOID
+ )
+{
+}
+#endif
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AcpiTables/Hpet/Hpet.h b/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AcpiTables/Hpet/Hpet.h
new file mode 100644
index 0000000000..7a0b3b7a59
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AcpiTables/Hpet/Hpet.h
@@ -0,0 +1,43 @@
+/** @file
+ This file describes the contents of the ACPI High Precision Event Timer Description Table
+ (HPET). All changes to the HPET contents should be done in this file.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _HPET_H_
+#define _HPET_H_
+
+//
+// Statements that include other files
+//
+
+#include <IndustryStandard/Acpi30.h>
+#include <IndustryStandard/HighPrecisionEventTimerTable.h>
+
+//
+// HPET Definitions
+//
+
+#define EFI_ACPI_OEM_HPET_REVISION 0x00000001
+
+#define EFI_ACPI_EVENT_TIMER_BLOCK_ID 0x8086A201
+
+//
+// Event Timer Block Base Address Information
+//
+#define EFI_ACPI_EVENT_TIMER_BLOCK_ADDRESS_SPACE_ID EFI_ACPI_3_0_SYSTEM_MEMORY
+#define EFI_ACPI_EVENT_TIMER_BLOCK_BIT_WIDTH 0x40
+#define EFI_ACPI_EVENT_TIMER_BLOCK_BIT_OFFSET 0x00
+#define EFI_ACPI_EVENT_TIMER_ACCESS_SIZE 0x00
+#define EFI_ACPI_EVENT_TIMER_BLOCK_ADDRESS 0x00000000FED00000
+
+#define EFI_ACPI_HPET_NUMBER 0x00
+
+#define EFI_ACPI_MIN_CLOCK_TICK 0x0080
+
+#define EFI_ACPI_HPET_ATTRIBUTES 0x00
+
+#endif
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AcpiTables/Include/AcpiCommon.h b/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AcpiTables/Include/AcpiCommon.h
new file mode 100644
index 0000000000..f689c7e339
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AcpiTables/Include/AcpiCommon.h
@@ -0,0 +1,16 @@
+/** @file
+ Header file for ACPI common Initialization Driver.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _ACPI_COMMON_H_
+#define _ACPI_COMMON_H_
+
+
+
+
+
+#endif
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AcpiTables/Madt/Madt.act b/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AcpiTables/Madt/Madt.act
new file mode 100644
index 0000000000..9bb0884219
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AcpiTables/Madt/Madt.act
@@ -0,0 +1,573 @@
+/** @file
+ This file contains a structure definition for the ACPI 2.0 Multiple APIC
+ Description Table (MADT). Any changes to the MADT table require updating the
+ respective structure count in Madt.h and then adding the structure to the
+ MADT defined in this file.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+//
+// Statements that include other files
+//
+
+#include "Madt.h"
+
+//
+// Multiple APIC Description Table
+//
+
+EFI_ACPI_6_3_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = {
+ {
+ {
+ EFI_ACPI_6_3_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE,
+ sizeof (EFI_ACPI_6_3_MULTIPLE_APIC_DESCRIPTION_TABLE),
+ EFI_ACPI_6_3_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION,
+
+ //
+ // Checksum will be updated at runtime
+ //
+ 0x00,
+
+ //
+ // It is expected that these values will be programmed at runtime
+ //
+ { ' ', ' ', ' ', ' ', ' ', ' ' },
+
+ 0,
+ EFI_ACPI_OEM_MADT_REVISION,
+ 0,
+ 0
+ },
+
+ //
+ // MADT specific fields
+ //
+ FixedPcdGet64 (PcdApicLocalAddress),
+ EFI_ACPI_6_3_MULTIPLE_APIC_FLAGS
+ },
+
+ //
+ // Sample Processor Local APIC Structure
+ //
+ //EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC, // Type
+ //sizeof (EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC_STRUCTURE), // Length
+ //0x00 // Processor ID
+ //0x00 // Local APIC ID
+ //0x00000000, // Flags - Disabled (until initialized by platform driver)
+ {
+ {
+ EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC, // Type
+ sizeof (EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC_STRUCTURE), // Length
+ 0x01, // Processor ID
+ 0xFF, // Local APIC ID
+ 0x00000000 // Flags - Disabled (until initialized by platform driver)
+ },
+ {
+ EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC, // Type
+ sizeof (EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC_STRUCTURE), // Length
+ 0x02, // Processor ID
+ 0xFF, // Local APIC ID
+ 0x00000000 // Flags - Disabled (until initialized by platform driver)
+ },
+ {
+ EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC, // Type
+ sizeof (EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC_STRUCTURE), // Length
+ 0x03, // Processor ID
+ 0xFF, // Local APIC ID
+ 0x00000000 // Flags - Disabled (until initialized by platform driver)
+ },
+ {
+ EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC, // Type
+ sizeof (EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC_STRUCTURE), // Length
+ 0x04, // Processor ID
+ 0xFF, // Local APIC ID
+ 0x00000000 // Flags - Disabled (until initialized by platform driver)
+ },
+ {
+ EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC, // Type
+ sizeof (EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC_STRUCTURE), // Length
+ 0x05, // Processor ID
+ 0xFF, // Local APIC ID
+ 0x00000000 // Flags - Disabled (until initialized by platform driver)
+ },
+ {
+ EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC, // Type
+ sizeof (EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC_STRUCTURE), // Length
+ 0x06, // Processor ID
+ 0xFF, // Local APIC ID
+ 0x00000000 // Flags - Disabled (until initialized by platform driver)
+ },
+ {
+ EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC, // Type
+ sizeof (EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC_STRUCTURE), // Length
+ 0x07, // Processor ID
+ 0xFF, // Local APIC ID
+ 0x00000000 // Flags - Disabled (until initialized by platform driver)
+ },
+ {
+ EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC, // Type
+ sizeof (EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC_STRUCTURE), // Length
+ 0x08, // Processor ID
+ 0xFF, // Local APIC ID
+ 0x00000000 // Flags - Disabled (until initialized by platform driver)
+ },
+ {
+ EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC, // Type
+ sizeof (EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC_STRUCTURE), // Length
+ 0x09, // Processor ID
+ 0xFF, // Local APIC ID
+ 0x00000000 // Flags - Disabled (until initialized by platform driver)
+ },
+ {
+ EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC, // Type
+ sizeof (EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC_STRUCTURE), // Length
+ 0x0A, // Processor ID
+ 0xFF, // Local APIC ID
+ 0x00000000 // Flags - Disabled (until initialized by platform driver)
+ },
+ {
+ EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC, // Type
+ sizeof (EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC_STRUCTURE), // Length
+ 0x0B, // Processor ID
+ 0xFF, // Local APIC ID
+ 0x00000000 // Flags - Disabled (until initialized by platform driver)
+ },
+ {
+ EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC, // Type
+ sizeof (EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC_STRUCTURE), // Length
+ 0x0C, // Processor ID
+ 0xFF, // Local APIC ID
+ 0x00000000 // Flags - Disabled (until initialized by platform driver)
+ },
+ {
+ EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC, // Type
+ sizeof (EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC_STRUCTURE), // Length
+ 0x0D, // Processor ID
+ 0xFF, // Local APIC ID
+ 0x00000000 // Flags - Disabled (until initialized by platform driver)
+ },
+ {
+ EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC, // Type
+ sizeof (EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC_STRUCTURE), // Length
+ 0x0E, // Processor ID
+ 0xFF, // Local APIC ID
+ 0x00000000 // Flags - Disabled (until initialized by platform driver)
+ },
+ {
+ EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC, // Type
+ sizeof (EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC_STRUCTURE), // Length
+ 0x0F, // Processor ID
+ 0xFF, // Local APIC ID
+ 0x00000000 // Flags - Disabled (until initialized by platform driver)
+ },
+ {
+ EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC, // Type
+ sizeof (EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC_STRUCTURE), // Length
+ 0x10, // Processor ID
+ 0xFF, // Local APIC ID
+ 0x00000000 // Flags - Disabled (until initialized by platform driver)
+ },
+ {
+ EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC, // Type
+ sizeof (EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC_STRUCTURE), // Length
+ 0x11, // Processor ID
+ 0xFF, // Local APIC ID
+ 0x00000000 // Flags - Disabled (until initialized by platform driver)
+ },
+ {
+ EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC, // Type
+ sizeof (EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC_STRUCTURE), // Length
+ 0x12, // Processor ID
+ 0xFF, // Local APIC ID
+ 0x00000000 // Flags - Disabled (until initialized by platform driver)
+ },
+ {
+ EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC, // Type
+ sizeof (EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC_STRUCTURE), // Length
+ 0x13, // Processor ID
+ 0xFF, // Local APIC ID
+ 0x00000000 // Flags - Disabled (until initialized by platform driver)
+ },
+ {
+ EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC, // Type
+ sizeof (EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC_STRUCTURE), // Length
+ 0x14, // Processor ID
+ 0xFF, // Local APIC ID
+ 0x00000000 // Flags - Disabled (until initialized by platform driver)
+ },
+ {
+ EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC, // Type
+ sizeof (EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC_STRUCTURE), // Length
+ 0x15, // Processor ID
+ 0xFF, // Local APIC ID
+ 0x00000000 // Flags - Disabled (until initialized by platform driver)
+ },
+ {
+ EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC, // Type
+ sizeof (EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC_STRUCTURE), // Length
+ 0x16, // Processor ID
+ 0xFF, // Local APIC ID
+ 0x00000000 // Flags - Disabled (until initialized by platform driver)
+ },
+ {
+ EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC, // Type
+ sizeof (EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC_STRUCTURE), // Length
+ 0x17, // Processor ID
+ 0xFF, // Local APIC ID
+ 0x00000000 // Flags - Disabled (until initialized by platform driver)
+ },
+ {
+ EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC, // Type
+ sizeof (EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC_STRUCTURE), // Length
+ 0x18, // Processor ID
+ 0xFF, // Local APIC ID
+ 0x00000000 // Flags - Disabled (until initialized by platform driver)
+ },
+ {
+ EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC, // Type
+ sizeof (EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC_STRUCTURE), // Length
+ 0x19, // Processor ID
+ 0xFF, // Local APIC ID
+ 0x00000000 // Flags - Disabled (until initialized by platform driver)
+ },
+ {
+ EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC, // Type
+ sizeof (EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC_STRUCTURE), // Length
+ 0x1A, // Processor ID
+ 0xFF, // Local APIC ID
+ 0x00000000 // Flags - Disabled (until initialized by platform driver)
+ },
+ {
+ EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC, // Type
+ sizeof (EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC_STRUCTURE), // Length
+ 0x1B, // Processor ID
+ 0xFF, // Local APIC ID
+ 0x00000000 // Flags - Disabled (until initialized by platform driver)
+ },
+ {
+ EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC, // Type
+ sizeof (EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC_STRUCTURE), // Length
+ 0x1C, // Processor ID
+ 0xFF, // Local APIC ID
+ 0x00000000 // Flags - Disabled (until initialized by platform driver)
+ },
+ {
+ EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC, // Type
+ sizeof (EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC_STRUCTURE), // Length
+ 0x1D, // Processor ID
+ 0xFF, // Local APIC ID
+ 0x00000000 // Flags - Disabled (until initialized by platform driver)
+ },
+ {
+ EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC, // Type
+ sizeof (EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC_STRUCTURE), // Length
+ 0x1E, // Processor ID
+ 0xFF, // Local APIC ID
+ 0x00000000 // Flags - Disabled (until initialized by platform driver)
+ },
+ {
+ EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC, // Type
+ sizeof (EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC_STRUCTURE), // Length
+ 0x1F, // Processor ID
+ 0xFF, // Local APIC ID
+ 0x00000000 // Flags - Disabled (until initialized by platform driver)
+ },
+ {
+ EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC, // Type
+ sizeof (EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC_STRUCTURE), // Length
+ 0x20, // Processor ID
+ 0xFF, // Local APIC ID
+ 0x00000000 // Flags - Disabled (until initialized by platform driver)
+ }
+ },
+
+ //
+ // Sample IO APIC Structure
+ //
+ //EFI_ACPI_6_3_IO_APIC, // Type
+ //sizeof (EFI_ACPI_6_3_IO_APIC_STRUCTURE), // Length
+ //0x00, // IO APIC ID
+ //EFI_ACPI_RESERVED_BYTE, // Reserved
+ //0x00000000, // IO APIC Address (physical)
+ //0x00000000, // Global System Interrupt Base
+ {
+ {
+ //
+ // I/O SAPIC (ICH)
+ //
+ EFI_ACPI_6_3_IO_APIC, // Type
+ sizeof (EFI_ACPI_6_3_IO_APIC_STRUCTURE), // Length
+ FixedPcdGet8 (PcdApicIoIdPch), // IO APIC ID
+ EFI_ACPI_RESERVED_BYTE, // Reserved
+ FixedPcdGet64 (PcdApicIoAddress), // IO APIC Address (physical)
+ 0x18 * 0 // Global System Interrupt Base
+ }
+ },
+ //
+ // Sample Interrupt Source Override Structure
+ //
+ //EFI_ACPI_6_3_INTERRUPT_SOURCE_OVERRIDE, // Type
+ //sizeof (EFI_ACPI_6_3_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE), // Length
+ //0x00, // Bus
+ //0x00, // Source
+ //0x00000000, // Global System Interrupt
+ //0x0000, // Flags
+ {
+ {
+ //
+ // IRQ0=>IRQ2 Interrupt Source Override Structure
+ //
+ EFI_ACPI_6_3_INTERRUPT_SOURCE_OVERRIDE, // Type
+ sizeof (EFI_ACPI_6_3_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE),// Length
+ 0x00, // Bus - ISA
+ 0x00, // Source - IRQ0
+ 0x00000002, // Global System Interrupt - IRQ2
+ 0x0000 // Flags - Conforms to specifications of the bus
+ },
+ {
+ //
+ // ISO (SCI Active High) Interrupt Source Override Structure
+ //
+ EFI_ACPI_6_3_INTERRUPT_SOURCE_OVERRIDE, // Type
+ sizeof (EFI_ACPI_6_3_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE),// Length
+ 0x00, // Bus - ISA
+ 0x09, // Source - IRQ9
+ 0x00000009, // Global System Interrupt - IRQ9
+ 0x000D // Flags - Level-tiggered, Active High
+ }
+ },
+ //
+ // Sample Non-Maskable Interrupt Source Structure
+ //
+ //EFI_ACPI_6_3_NON_MASKABLE_INTERRUPT_SOURCE, // Type
+ //sizeof (EFI_ACPI_6_3_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE), // Length
+ //0x0000, // Flags
+ //0x00000000, // Global System Interrupt
+
+ //
+ // Sample Local APIC NMI Structure
+ //
+ //EFI_ACPI_6_3_LOCAL_APIC_NMI, // Type
+ //sizeof (EFI_ACPI_6_3_LOCAL_APIC_NMI_STRUCTURE), // Length
+ //0x00, // ACPI Processor ID
+ //0x0000, // Flags
+ //0x00, // Local APIC LINT#
+
+ {
+ {
+ EFI_ACPI_6_3_LOCAL_APIC_NMI, // Type
+ sizeof (EFI_ACPI_6_3_LOCAL_APIC_NMI_STRUCTURE), // Length
+ 0x01, // ACPI Processor ID
+ 0x0005, // Flags - Edge-tiggered, Active High
+ 0x01 // Local APIC LINT#
+ },
+ {
+ EFI_ACPI_6_3_LOCAL_APIC_NMI, // Type
+ sizeof (EFI_ACPI_6_3_LOCAL_APIC_NMI_STRUCTURE), // Length
+ 0x02, // ACPI Processor ID
+ 0x0005, // Flags - Edge-tiggered, Active High
+ 0x01 // Local APIC LINT#
+ },
+ {
+ EFI_ACPI_6_3_LOCAL_APIC_NMI, // Type
+ sizeof (EFI_ACPI_6_3_LOCAL_APIC_NMI_STRUCTURE), // Length
+ 0x03, // ACPI Processor ID
+ 0x0005, // Flags - Edge-tiggered, Active High
+ 0x01 // Local APIC LINT#
+ },
+ {
+ EFI_ACPI_6_3_LOCAL_APIC_NMI, // Type
+ sizeof (EFI_ACPI_6_3_LOCAL_APIC_NMI_STRUCTURE), // Length
+ 0x04, // ACPI Processor ID
+ 0x0005, // Flags - Edge-tiggered, Active High
+ 0x01 // Local APIC LINT#
+ },
+ {
+ EFI_ACPI_6_3_LOCAL_APIC_NMI, // Type
+ sizeof (EFI_ACPI_6_3_LOCAL_APIC_NMI_STRUCTURE), // Length
+ 0x05, // ACPI Processor ID
+ 0x0005, // Flags - Edge-tiggered, Active High
+ 0x01 // Local APIC LINT#
+ },
+ {
+ EFI_ACPI_6_3_LOCAL_APIC_NMI, // Type
+ sizeof (EFI_ACPI_6_3_LOCAL_APIC_NMI_STRUCTURE), // Length
+ 0x06, // ACPI Processor ID
+ 0x0005, // Flags - Edge-tiggered, Active High
+ 0x01 // Local APIC LINT#
+ },
+ {
+ EFI_ACPI_6_3_LOCAL_APIC_NMI, // Type
+ sizeof (EFI_ACPI_6_3_LOCAL_APIC_NMI_STRUCTURE), // Length
+ 0x07, // ACPI Processor ID
+ 0x0005, // Flags - Edge-tiggered, Active High
+ 0x01 // Local APIC LINT#
+ },
+ {
+ EFI_ACPI_6_3_LOCAL_APIC_NMI, // Type
+ sizeof (EFI_ACPI_6_3_LOCAL_APIC_NMI_STRUCTURE), // Length
+ 0x08, // ACPI Processor ID
+ 0x0005, // Flags - Edge-tiggered, Active High
+ 0x01 // Local APIC LINT#
+ },
+ {
+ EFI_ACPI_6_3_LOCAL_APIC_NMI, // Type
+ sizeof (EFI_ACPI_6_3_LOCAL_APIC_NMI_STRUCTURE), // Length
+ 0x09, // ACPI Processor ID
+ 0x0005, // Flags - Edge-tiggered, Active High
+ 0x01 // Local APIC LINT#
+ },
+ {
+ EFI_ACPI_6_3_LOCAL_APIC_NMI, // Type
+ sizeof (EFI_ACPI_6_3_LOCAL_APIC_NMI_STRUCTURE), // Length
+ 0x0A, // ACPI Processor ID
+ 0x0005, // Flags - Edge-tiggered, Active High
+ 0x01 // Local APIC LINT#
+ },
+ {
+ EFI_ACPI_6_3_LOCAL_APIC_NMI, // Type
+ sizeof (EFI_ACPI_6_3_LOCAL_APIC_NMI_STRUCTURE), // Length
+ 0x0B, // ACPI Processor ID
+ 0x0005, // Flags - Edge-tiggered, Active High
+ 0x01 // Local APIC LINT#
+ },
+ {
+ EFI_ACPI_6_3_LOCAL_APIC_NMI, // Type
+ sizeof (EFI_ACPI_6_3_LOCAL_APIC_NMI_STRUCTURE), // Length
+ 0x0C, // ACPI Processor ID
+ 0x0005, // Flags - Edge-tiggered, Active High
+ 0x01 // Local APIC LINT#
+ },
+ {
+ EFI_ACPI_6_3_LOCAL_APIC_NMI, // Type
+ sizeof (EFI_ACPI_6_3_LOCAL_APIC_NMI_STRUCTURE), // Length
+ 0x0D, // ACPI Processor ID
+ 0x0005, // Flags - Edge-tiggered, Active High
+ 0x01 // Local APIC LINT#
+ },
+ {
+ EFI_ACPI_6_3_LOCAL_APIC_NMI, // Type
+ sizeof (EFI_ACPI_6_3_LOCAL_APIC_NMI_STRUCTURE), // Length
+ 0x0E, // ACPI Processor ID
+ 0x0005, // Flags - Edge-tiggered, Active High
+ 0x01 // Local APIC LINT#
+ },
+ {
+ EFI_ACPI_6_3_LOCAL_APIC_NMI, // Type
+ sizeof (EFI_ACPI_6_3_LOCAL_APIC_NMI_STRUCTURE), // Length
+ 0x0F, // ACPI Processor ID
+ 0x0005, // Flags - Edge-tiggered, Active High
+ 0x01 // Local APIC LINT#
+ },
+ {
+ EFI_ACPI_6_3_LOCAL_APIC_NMI, // Type
+ sizeof (EFI_ACPI_6_3_LOCAL_APIC_NMI_STRUCTURE), // Length
+ 0x10, // ACPI Processor ID
+ 0x0005, // Flags - Edge-tiggered, Active High
+ 0x01 // Local APIC LINT#
+ },
+ {
+ EFI_ACPI_6_3_LOCAL_APIC_NMI, // Type
+ sizeof (EFI_ACPI_6_3_LOCAL_APIC_NMI_STRUCTURE), // Length
+ 0x11, // ACPI Processor ID
+ 0x0005, // Flags - Edge-tiggered, Active High
+ 0x01 // Local APIC LINT#
+ },
+ {
+ EFI_ACPI_6_3_LOCAL_APIC_NMI, // Type
+ sizeof (EFI_ACPI_6_3_LOCAL_APIC_NMI_STRUCTURE), // Length
+ 0x12, // ACPI Processor ID
+ 0x0005, // Flags - Edge-tiggered, Active High
+ 0x01 // Local APIC LINT#
+ },
+ {
+ EFI_ACPI_6_3_LOCAL_APIC_NMI, // Type
+ sizeof (EFI_ACPI_6_3_LOCAL_APIC_NMI_STRUCTURE), // Length
+ 0x13, // ACPI Processor ID
+ 0x0005, // Flags - Edge-tiggered, Active High
+ 0x01 // Local APIC LINT#
+ },
+ {
+ EFI_ACPI_6_3_LOCAL_APIC_NMI, // Type
+ sizeof (EFI_ACPI_6_3_LOCAL_APIC_NMI_STRUCTURE), // Length
+ 0x14, // ACPI Processor ID
+ 0x0005, // Flags - Edge-tiggered, Active High
+ 0x01 // Local APIC LINT#
+ },
+ {
+ EFI_ACPI_6_3_LOCAL_APIC_NMI, // Type
+ sizeof (EFI_ACPI_6_3_LOCAL_APIC_NMI_STRUCTURE), // Length
+ 0x15, // ACPI Processor ID
+ 0x0005, // Flags - Edge-tiggered, Active High
+ 0x01 // Local APIC LINT#
+ },
+ {
+ EFI_ACPI_6_3_LOCAL_APIC_NMI, // Type
+ sizeof (EFI_ACPI_6_3_LOCAL_APIC_NMI_STRUCTURE), // Length
+ 0x16, // ACPI Processor ID
+ 0x0005, // Flags - Edge-tiggered, Active High
+ 0x01 // Local APIC LINT#
+ },
+ {
+ EFI_ACPI_6_3_LOCAL_APIC_NMI, // Type
+ sizeof (EFI_ACPI_6_3_LOCAL_APIC_NMI_STRUCTURE), // Length
+ 0x17, // ACPI Processor ID
+ 0x0005, // Flags - Edge-tiggered, Active High
+ 0x01 // Local APIC LINT#
+ },
+ {
+ EFI_ACPI_6_3_LOCAL_APIC_NMI, // Type
+ sizeof (EFI_ACPI_6_3_LOCAL_APIC_NMI_STRUCTURE), // Length
+ 0x00, // ACPI Processor ID
+ 0x0005, // Flags - Edge-tiggered, Active High
+ 0x01 // Local APIC LINT#
+ }
+ }
+
+ //
+ // Sample Local APIC Address Override Structure
+ //
+ //EFI_ACPI_6_3_LOCAL_APIC_ADDRESS_OVERRIDE, // Type
+ //sizeof (EFI_ACPI_6_3_LOCAL_APIC_ADDRESS_OVERRIDE_STRUCTURE), // Length
+ //EFI_ACPI_RESERVED_WORD, // Reserved
+ //0x0000000000000000, // Local APIC Address
+
+ //
+ // Sample Platform Interrupt Sources Structure
+ //
+ //EFI_ACPI_6_3_PLATFORM_INTERRUPT_SOURCES, // Type
+ //sizeof (EFI_ACPI_6_3_PLATFORM_INTERRUPT_SOURCES_STRUCTURE), // Length
+ //0x0000, // Flags
+ //0x00, // Interrupt Type
+ //0x00, // Processor ID
+ //0x00, // Processor EID
+ //0x00, // IO SAPIC Vector
+ //0x00000000, // Global System Interrupt
+ //EFI_ACPI_RESERVED_DWORD, // Reserved
+
+};
+
+#ifdef __GNUC__
+VOID*
+ReferenceAcpiTable (
+ VOID
+ )
+
+{
+ //
+ // Reference the table being generated to prevent the optimizer from removing the
+ // data structure from the executable
+ //
+ return (VOID*)&Madt;
+}
+#else
+VOID
+main (
+ VOID
+ )
+{
+}
+#endif
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AcpiTables/Madt/Madt.h b/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AcpiTables/Madt/Madt.h
new file mode 100644
index 0000000000..b06b6efecd
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AcpiTables/Madt/Madt.h
@@ -0,0 +1,226 @@
+/** @file
+ This file describes the contents of the ACPI Multiple APIC Description
+ Table (MADT).
+ To make changes to the MADT, it is necessary to update the count for the
+ APIC structure being updated, and to modify table found in Madt.c.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _MADT_H_
+#define _MADT_H_
+
+//
+// Statements that include other files
+//
+
+#include <IndustryStandard/Acpi.h>
+
+//
+// MADT Definitions
+//
+
+#define EFI_ACPI_OEM_MADT_REVISION 0x00000001
+
+
+//
+// Multiple APIC Flags are defined in AcpiX.0.h
+//
+#define EFI_ACPI_6_3_MULTIPLE_APIC_FLAGS (EFI_ACPI_6_3_PCAT_COMPAT)
+
+//
+// Define the number of each table type.
+// This is where the table layout is modified.
+//
+
+#define EFI_ACPI_PROCESSOR_LOCAL_APIC_COUNT 32
+#define EFI_ACPI_IO_APIC_COUNT 1
+#define EFI_ACPI_INTERRUPT_SOURCE_OVERRIDE_COUNT 2
+#define EFI_ACPI_NON_MASKABLE_INTERRUPT_SOURCE_COUNT 0
+#define EFI_ACPI_LOCAL_APIC_NMI_COUNT 24
+#define EFI_ACPI_LOCAL_APIC_ADDRESS_OVERRIDE_COUNT 0
+#define EFI_ACPI_IO_SAPIC_COUNT 0
+#define EFI_ACPI_PROCESSOR_LOCAL_SAPIC_COUNT 0
+#define EFI_ACPI_PLATFORM_INTERRUPT_SOURCES_COUNT 0
+#define EFI_ACPI_PROCESSOR_LOCAL_X2APIC_COUNT 32
+#define EFI_ACPI_LOCAL_X2APIC_NMI_COUNT 1
+
+//
+// MADT structure
+//
+
+//
+// Ensure proper structure formats
+//
+#pragma pack (1)
+
+//
+// ACPI 1.0 Table structure
+//
+typedef struct {
+ EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header;
+
+#if EFI_ACPI_PROCESSOR_LOCAL_APIC_COUNT > 0
+ EFI_ACPI_1_0_PROCESSOR_LOCAL_APIC_STRUCTURE LocalApic[EFI_ACPI_PROCESSOR_LOCAL_APIC_COUNT];
+#endif
+
+#if EFI_ACPI_IO_APIC_COUNT > 0
+ EFI_ACPI_1_0_IO_APIC_STRUCTURE IoApic[EFI_ACPI_IO_APIC_COUNT];
+#endif
+
+#if EFI_ACPI_INTERRUPT_SOURCE_OVERRIDE_COUNT > 0
+ EFI_ACPI_1_0_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE Iso[EFI_ACPI_INTERRUPT_SOURCE_OVERRIDE_COUNT];
+#endif
+
+#if EFI_ACPI_NON_MASKABLE_INTERRUPT_SOURCE_COUNT > 0
+ EFI_ACPI_1_0_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE NmiSource[EFI_ACPI_NON_MASKABLE_INTERRUPT_SOURCE_COUNT];
+#endif
+
+#if EFI_ACPI_LOCAL_APIC_NMI_COUNT > 0
+ EFI_ACPI_1_0_LOCAL_APIC_NMI_STRUCTURE LocalApicNmi[EFI_ACPI_LOCAL_APIC_NMI_COUNT];
+#endif
+
+#if EFI_ACPI_LOCAL_APIC_ADDRESS_OVERRIDE_COUNT > 0
+ EFI_ACPI_1_0_LOCAL_APIC_ADDRESS_OVERRIDE_STRUCTURE LocalApicOverride[EFI_ACPI_LOCAL_APIC_OVERRIDE_COUNT];
+#endif
+
+} EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE;
+
+//
+// ACPI 2.0 Table structure
+//
+typedef struct {
+ EFI_ACPI_2_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header;
+
+#if EFI_ACPI_PROCESSOR_LOCAL_APIC_COUNT > 0
+ EFI_ACPI_2_0_PROCESSOR_LOCAL_APIC_STRUCTURE LocalApic[EFI_ACPI_PROCESSOR_LOCAL_APIC_COUNT];
+#endif
+
+#if EFI_ACPI_IO_APIC_COUNT > 0
+ EFI_ACPI_2_0_IO_APIC_STRUCTURE IoApic[EFI_ACPI_IO_APIC_COUNT];
+#endif
+
+#if EFI_ACPI_INTERRUPT_SOURCE_OVERRIDE_COUNT > 0
+ EFI_ACPI_2_0_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE Iso[EFI_ACPI_INTERRUPT_SOURCE_OVERRIDE_COUNT];
+#endif
+
+#if EFI_ACPI_NON_MASKABLE_INTERRUPT_SOURCE_COUNT > 0
+ EFI_ACPI_2_0_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE NmiSource[EFI_ACPI_NON_MASKABLE_INTERRUPT_SOURCE_COUNT];
+#endif
+
+#if EFI_ACPI_LOCAL_APIC_NMI_COUNT > 0
+ EFI_ACPI_2_0_LOCAL_APIC_NMI_STRUCTURE LocalApicNmi[EFI_ACPI_LOCAL_APIC_NMI_COUNT];
+#endif
+
+#if EFI_ACPI_LOCAL_APIC_ADDRESS_OVERRIDE_COUNT > 0
+ EFI_ACPI_2_0_LOCAL_APIC_ADDRESS_OVERRIDE_STRUCTURE LocalApicOverride[EFI_ACPI_LOCAL_APIC_OVERRIDE_COUNT];
+#endif
+
+#if EFI_ACPI_IO_SAPIC_COUNT > 0
+ EFI_ACPI_2_0_IO_SAPIC_STRUCTURE IoSapic[EFI_ACPI_IO_SAPIC_COUNT];
+#endif
+
+#if EFI_ACPI_PROCESSOR_LOCAL_SAPIC_COUNT > 0
+ EFI_ACPI_2_0_PROCESSOR_LOCAL_SAPIC_STRUCTURE LocalSapic[EFI_ACPI_PROCESSOR_LOCAL_SAPIC_COUNT];
+#endif
+
+#if EFI_ACPI_PLATFORM_INTERRUPT_SOURCES_COUNT > 0
+ EFI_ACPI_2_0_PLATFORM_INTERRUPT_SOURCES_STRUCTURE PlatformInterruptSources[EFI_ACPI_PLATFORM_INTERRUPT_SOURCES_COUNT];
+#endif
+
+} EFI_ACPI_2_0_MULTIPLE_APIC_DESCRIPTION_TABLE;
+
+//
+// ACPI 6.3 APIC Table structure
+//
+typedef struct {
+ EFI_ACPI_6_3_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header;
+
+#if EFI_ACPI_PROCESSOR_LOCAL_APIC_COUNT > 0 // Type 0x09
+ EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC_STRUCTURE LocalApic[EFI_ACPI_PROCESSOR_LOCAL_APIC_COUNT];
+#endif
+
+#if EFI_ACPI_IO_APIC_COUNT > 0 // Type 0x01
+ EFI_ACPI_6_3_IO_APIC_STRUCTURE IoApic[EFI_ACPI_IO_APIC_COUNT];
+#endif
+
+#if EFI_ACPI_INTERRUPT_SOURCE_OVERRIDE_COUNT > 0 // Type 0x02
+ EFI_ACPI_6_3_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE Iso[EFI_ACPI_INTERRUPT_SOURCE_OVERRIDE_COUNT];
+#endif
+
+#if EFI_ACPI_NON_MASKABLE_INTERRUPT_SOURCE_COUNT > 0 // Type 0x03
+ EFI_ACPI_6_3_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE NmiSource[EFI_ACPI_NON_MASKABLE_INTERRUPT_SOURCE_COUNT];
+#endif
+
+#if EFI_ACPI_LOCAL_APIC_NMI_COUNT > 0 // Type 0x0A
+ EFI_ACPI_6_3_LOCAL_APIC_NMI_STRUCTURE LocalApicNmi[EFI_ACPI_LOCAL_APIC_NMI_COUNT];
+#endif
+
+#if EFI_ACPI_LOCAL_APIC_ADDRESS_OVERRIDE_COUNT > 0 // Type 0x05
+ EFI_ACPI_6_3_LOCAL_APIC_ADDRESS_OVERRIDE_STRUCTURE LocalApicOverride[EFI_ACPI_LOCAL_APIC_OVERRIDE_COUNT];
+#endif
+
+#if EFI_ACPI_IO_SAPIC_COUNT > 0 // Type 0x06
+ EFI_ACPI_6_3_IO_SAPIC_STRUCTURE IoSapic[EFI_ACPI_IO_SAPIC_COUNT];
+#endif
+
+#if EFI_ACPI_PROCESSOR_LOCAL_SAPIC_COUNT > 0 // Type 0x07 : This table changes in madt 2.0
+ EFI_ACPI_6_3_PROCESSOR_LOCAL_SAPIC_STRUCTURE LocalSapic[EFI_ACPI_PROCESSOR_LOCAL_SAPIC_COUNT];
+#endif
+
+#if EFI_ACPI_PLATFORM_INTERRUPT_SOURCES_COUNT > 0 // Type 0x08
+ EFI_ACPI_6_3_PLATFORM_INTERRUPT_SOURCES_STRUCTURE PlatformInterruptSources[EFI_ACPI_PLATFORM_INTERRUPT_SOURCES_COUNT];
+#endif
+
+} EFI_ACPI_6_3_MULTIPLE_APIC_DESCRIPTION_TABLE;
+
+
+//
+// ACPI 6.3 X2APIC Table structure
+//
+typedef struct {
+ EFI_ACPI_6_3_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header;
+
+#if EFI_ACPI_PROCESSOR_LOCAL_X2APIC_COUNT > 0 // Type 0x09
+ EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC_STRUCTURE LocalX2Apic[EFI_ACPI_PROCESSOR_LOCAL_X2APIC_COUNT];
+#endif
+
+#if EFI_ACPI_IO_APIC_COUNT > 0 // Type 0x01
+ EFI_ACPI_6_3_IO_APIC_STRUCTURE IoApic[EFI_ACPI_IO_APIC_COUNT];
+#endif
+
+#if EFI_ACPI_INTERRUPT_SOURCE_OVERRIDE_COUNT > 0 // Type 0x02
+ EFI_ACPI_6_3_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE Iso[EFI_ACPI_INTERRUPT_SOURCE_OVERRIDE_COUNT];
+#endif
+
+#if EFI_ACPI_NON_MASKABLE_INTERRUPT_SOURCE_COUNT > 0 // Type 0x03
+ EFI_ACPI_6_3_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE NmiSource[EFI_ACPI_NON_MASKABLE_INTERRUPT_SOURCE_COUNT];
+#endif
+
+#if EFI_ACPI_LOCAL_X2APIC_NMI_COUNT > 0 // Type 0x0A
+ EFI_ACPI_6_3_LOCAL_X2APIC_NMI_STRUCTURE X2ApicNmi[EFI_ACPI_LOCAL_X2APIC_NMI_COUNT];
+#endif
+
+#if EFI_ACPI_LOCAL_APIC_ADDRESS_OVERRIDE_COUNT > 0 // Type 0x05
+ EFI_ACPI_6_3_LOCAL_APIC_ADDRESS_OVERRIDE_STRUCTURE LocalApicOverride[EFI_ACPI_LOCAL_APIC_OVERRIDE_COUNT];
+#endif
+
+#if EFI_ACPI_IO_SAPIC_COUNT > 0 // Type 0x06
+ EFI_ACPI_6_3_IO_SAPIC_STRUCTURE IoSapic[EFI_ACPI_IO_SAPIC_COUNT];
+#endif
+
+#if EFI_ACPI_PROCESSOR_LOCAL_SAPIC_COUNT > 0 // Type 0x07 : This table changes in madt 2.0
+ EFI_ACPI_6_3_PROCESSOR_LOCAL_SAPIC_STRUCTURE LocalSapic[EFI_ACPI_PROCESSOR_LOCAL_SAPIC_COUNT];
+#endif
+
+#if EFI_ACPI_PLATFORM_INTERRUPT_SOURCES_COUNT > 0 // Type 0x08
+ EFI_ACPI_6_3_PLATFORM_INTERRUPT_SOURCES_STRUCTURE PlatformInterruptSources[EFI_ACPI_PLATFORM_INTERRUPT_SOURCES_COUNT];
+#endif
+
+} EFI_ACPI_6_3_MULTIPLE_X2APIC_DESCRIPTION_TABLE;
+
+#pragma pack ()
+
+#endif
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AcpiTables/Madt/MadtX2Apic.act b/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AcpiTables/Madt/MadtX2Apic.act
new file mode 100644
index 0000000000..b6d4b6bd11
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AcpiTables/Madt/MadtX2Apic.act
@@ -0,0 +1,522 @@
+/** @file
+ This file contains a structure definition for the ACPI 6.3 Multiple APIC
+ Description Table (MADT). Any changes to the MADT table require updating the
+ respective structure count in Madt.h and then adding the structure to the
+ MADT defined in this file.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+//
+// Statements that include other files
+//
+
+#include "Madt.h"
+
+//
+// Multiple APIC Description Table
+//
+
+EFI_ACPI_6_3_MULTIPLE_X2APIC_DESCRIPTION_TABLE Madtx2Apic = {
+ {
+ {
+ EFI_ACPI_6_3_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE,
+ sizeof (EFI_ACPI_6_3_MULTIPLE_APIC_DESCRIPTION_TABLE),
+ EFI_ACPI_6_3_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION,
+
+ //
+ // Checksum will be updated at runtime
+ //
+ 0x00,
+
+ //
+ // It is expected that these values will be programmed at runtime
+ //
+ { ' ', ' ', ' ', ' ', ' ', ' ' },
+
+ 0,
+ EFI_ACPI_OEM_MADT_REVISION,
+ 0,
+ 0
+ },
+
+ //
+ // MADT specific fields
+ //
+ FixedPcdGet64 (PcdApicLocalAddress),
+ EFI_ACPI_6_3_MULTIPLE_APIC_FLAGS
+ },
+
+ //
+ // Sample Processor Local X2APIC Structure
+ //
+ //EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC, // Type 0x09
+ //sizeof (EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC_STRUCTURE), // Length
+ //EFI_ACPI_RESERVED_BYTE, // Reserved
+ //EFI_ACPI_RESERVED_BYTE, // Reserved
+ //0xFFFFFFFF, // Local X2APIC ID
+ //0x00000000, // Flags - Disabled (until initialized by platform driver)
+ //0x00000000, // Processor ID
+ {
+ {
+ EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC, // Type
+ sizeof (EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC_STRUCTURE), // Length
+ {
+ EFI_ACPI_RESERVED_BYTE, // Reserved
+ EFI_ACPI_RESERVED_BYTE // Reserved
+ },
+ 0xFFFFFFFF, // Local X2APIC ID
+ 0x00000000, // Flags - Disabled (until initialized by platform driver)
+ 0x00000001, // Processor ID
+ },
+ {
+ EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC, // Type
+ sizeof (EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC_STRUCTURE), // Length
+ {
+ EFI_ACPI_RESERVED_BYTE, // Reserved
+ EFI_ACPI_RESERVED_BYTE // Reserved
+ },
+ 0xFFFFFFFF, // Local X2APIC ID
+ 0x00000000, // Flags - Disabled (until initialized by platform driver)
+ 0x00000002, // Processor ID
+ },
+ {
+ EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC, // Type
+ sizeof (EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC_STRUCTURE), // Length
+ {
+ EFI_ACPI_RESERVED_BYTE, // Reserved
+ EFI_ACPI_RESERVED_BYTE // Reserved
+ },
+ 0xFFFFFFFF, // Local X2APIC ID
+ 0x00000000, // Flags - Disabled (until initialized by platform driver)
+ 0x00000003, // Processor ID
+ },
+ {
+ EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC, // Type
+ sizeof (EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC_STRUCTURE), // Length
+ {
+ EFI_ACPI_RESERVED_BYTE, // Reserved
+ EFI_ACPI_RESERVED_BYTE // Reserved
+ },
+ 0xFFFFFFFF, // Local X2APIC ID
+ 0x00000000, // Flags - Disabled (until initialized by platform driver)
+ 0x00000004, // Processor ID
+ },
+ {
+ EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC, // Type
+ sizeof (EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC_STRUCTURE), // Length
+ {
+ EFI_ACPI_RESERVED_BYTE, // Reserved
+ EFI_ACPI_RESERVED_BYTE // Reserved
+ },
+ 0xFFFFFFFF, // Local X2APIC ID
+ 0x00000000, // Flags - Disabled (until initialized by platform driver)
+ 0x00000005, // Processor ID
+ },
+ {
+ EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC, // Type
+ sizeof (EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC_STRUCTURE), // Length
+ {
+ EFI_ACPI_RESERVED_BYTE, // Reserved
+ EFI_ACPI_RESERVED_BYTE // Reserved
+ },
+ 0xFFFFFFFF, // Local X2APIC ID
+ 0x00000000, // Flags - Disabled (until initialized by platform driver)
+ 0x00000006, // Processor ID
+ },
+ {
+ EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC, // Type
+ sizeof (EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC_STRUCTURE), // Length
+ {
+ EFI_ACPI_RESERVED_BYTE, // Reserved
+ EFI_ACPI_RESERVED_BYTE // Reserved
+ },
+ 0xFFFFFFFF, // Local X2APIC ID
+ 0x00000000, // Flags - Disabled (until initialized by platform driver)
+ 0x00000007, // Processor ID
+ },
+ {
+ EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC, // Type
+ sizeof (EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC_STRUCTURE), // Length
+ {
+ EFI_ACPI_RESERVED_BYTE, // Reserved
+ EFI_ACPI_RESERVED_BYTE // Reserved
+ },
+ 0xFFFFFFFF, // Local X2APIC ID
+ 0x00000000, // Flags - Disabled (until initialized by platform driver)
+ 0x00000008, // Processor ID
+ },
+ {
+ EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC, // Type
+ sizeof (EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC_STRUCTURE), // Length
+ {
+ EFI_ACPI_RESERVED_BYTE, // Reserved
+ EFI_ACPI_RESERVED_BYTE // Reserved
+ },
+ 0xFFFFFFFF, // Local X2APIC ID
+ 0x00000000, // Flags - Disabled (until initialized by platform driver)
+ 0x00000009, // Processor ID
+ },
+ {
+ EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC, // Type
+ sizeof (EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC_STRUCTURE), // Length
+ {
+ EFI_ACPI_RESERVED_BYTE, // Reserved
+ EFI_ACPI_RESERVED_BYTE // Reserved
+ },
+ 0xFFFFFFFF, // Local X2APIC ID
+ 0x00000000, // Flags - Disabled (until initialized by platform driver)
+ 0x0000000A, // Processor ID
+ },
+ {
+ EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC, // Type
+ sizeof (EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC_STRUCTURE), // Length
+ {
+ EFI_ACPI_RESERVED_BYTE, // Reserved
+ EFI_ACPI_RESERVED_BYTE // Reserved
+ },
+ 0xFFFFFFFF, // Local X2APIC ID
+ 0x00000000, // Flags - Disabled (until initialized by platform driver)
+ 0x0000000B, // Processor ID
+ },
+ {
+ EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC, // Type
+ sizeof (EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC_STRUCTURE), // Length
+ {
+ EFI_ACPI_RESERVED_BYTE, // Reserved
+ EFI_ACPI_RESERVED_BYTE // Reserved
+ },
+ 0xFFFFFFFF, // Local X2APIC ID
+ 0x00000000, // Flags - Disabled (until initialized by platform driver)
+ 0x0000000C, // Processor ID
+ },
+ {
+ EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC, // Type
+ sizeof (EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC_STRUCTURE), // Length
+ {
+ EFI_ACPI_RESERVED_BYTE, // Reserved
+ EFI_ACPI_RESERVED_BYTE // Reserved
+ },
+ 0xFFFFFFFF, // Local X2APIC ID
+ 0x00000000, // Flags - Disabled (until initialized by platform driver)
+ 0x0000000D, // Processor ID
+ },
+ {
+ EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC, // Type
+ sizeof (EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC_STRUCTURE), // Length
+ {
+ EFI_ACPI_RESERVED_BYTE, // Reserved
+ EFI_ACPI_RESERVED_BYTE // Reserved
+ },
+ 0xFFFFFFFF, // Local X2APIC ID
+ 0x00000000, // Flags - Disabled (until initialized by platform driver)
+ 0x0000000E, // Processor ID
+ },
+ {
+ EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC, // Type
+ sizeof (EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC_STRUCTURE), // Length
+ {
+ EFI_ACPI_RESERVED_BYTE, // Reserved
+ EFI_ACPI_RESERVED_BYTE // Reserved
+ },
+ 0xFFFFFFFF, // Local X2APIC ID
+ 0x00000000, // Flags - Disabled (until initialized by platform driver)
+ 0x0000000F, // Processor ID
+ },
+ {
+ EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC, // Type
+ sizeof (EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC_STRUCTURE), // Length
+ {
+ EFI_ACPI_RESERVED_BYTE, // Reserved
+ EFI_ACPI_RESERVED_BYTE // Reserved
+ },
+ 0xFFFFFFFF, // Local X2APIC ID
+ 0x00000000, // Flags - Disabled (until initialized by platform driver)
+ 0x00000010, // Processor ID
+ },
+ {
+ EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC, // Type
+ sizeof (EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC_STRUCTURE), // Length
+ {
+ EFI_ACPI_RESERVED_BYTE, // Reserved
+ EFI_ACPI_RESERVED_BYTE // Reserved
+ },
+ 0xFFFFFFFF, // Local X2APIC ID
+ 0x00000000, // Flags - Disabled (until initialized by platform driver)
+ 0x00000011, // Processor ID
+ },
+ {
+ EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC, // Type
+ sizeof (EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC_STRUCTURE), // Length
+ {
+ EFI_ACPI_RESERVED_BYTE, // Reserved
+ EFI_ACPI_RESERVED_BYTE // Reserved
+ },
+ 0xFFFFFFFF, // Local X2APIC ID
+ 0x00000000, // Flags - Disabled (until initialized by platform driver)
+ 0x00000012, // Processor ID
+ },
+ {
+ EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC, // Type
+ sizeof (EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC_STRUCTURE), // Length
+ {
+ EFI_ACPI_RESERVED_BYTE, // Reserved
+ EFI_ACPI_RESERVED_BYTE // Reserved
+ },
+ 0xFFFFFFFF, // Local X2APIC ID
+ 0x00000000, // Flags - Disabled (until initialized by platform driver)
+ 0x00000013, // Processor ID
+ },
+ {
+ EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC, // Type
+ sizeof (EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC_STRUCTURE), // Length
+ {
+ EFI_ACPI_RESERVED_BYTE, // Reserved
+ EFI_ACPI_RESERVED_BYTE // Reserved
+ },
+ 0xFFFFFFFF, // Local X2APIC ID
+ 0x00000000, // Flags - Disabled (until initialized by platform driver)
+ 0x00000014, // Processor ID
+ },
+ {
+ EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC, // Type
+ sizeof (EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC_STRUCTURE), // Length
+ {
+ EFI_ACPI_RESERVED_BYTE, // Reserved
+ EFI_ACPI_RESERVED_BYTE // Reserved
+ },
+ 0xFFFFFFFF, // Local X2APIC ID
+ 0x00000000, // Flags - Disabled (until initialized by platform driver)
+ 0x00000015, // Processor ID
+ },
+ {
+ EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC, // Type
+ sizeof (EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC_STRUCTURE), // Length
+ {
+ EFI_ACPI_RESERVED_BYTE, // Reserved
+ EFI_ACPI_RESERVED_BYTE // Reserved
+ },
+ 0xFFFFFFFF, // Local X2APIC ID
+ 0x00000000, // Flags - Disabled (until initialized by platform driver)
+ 0x00000016, // Processor ID
+ },
+ {
+ EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC, // Type
+ sizeof (EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC_STRUCTURE), // Length
+ {
+ EFI_ACPI_RESERVED_BYTE, // Reserved
+ EFI_ACPI_RESERVED_BYTE // Reserved
+ },
+ 0xFFFFFFFF, // Local X2APIC ID
+ 0x00000000, // Flags - Disabled (until initialized by platform driver)
+ 0x00000017, // Processor ID
+ },
+ {
+ EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC, // Type
+ sizeof (EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC_STRUCTURE), // Length
+ {
+ EFI_ACPI_RESERVED_BYTE, // Reserved
+ EFI_ACPI_RESERVED_BYTE // Reserved
+ },
+ 0xFFFFFFFF, // Local X2APIC ID
+ 0x00000000, // Flags - Disabled (until initialized by platform driver)
+ 0x00000018, // Processor ID
+ },
+ {
+ EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC, // Type
+ sizeof (EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC_STRUCTURE), // Length
+ {
+ EFI_ACPI_RESERVED_BYTE, // Reserved
+ EFI_ACPI_RESERVED_BYTE // Reserved
+ },
+ 0xFFFFFFFF, // Local X2APIC ID
+ 0x00000000, // Flags - Disabled (until initialized by platform driver)
+ 0x00000019, // Processor ID
+ },
+ {
+ EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC, // Type
+ sizeof (EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC_STRUCTURE), // Length
+ {
+ EFI_ACPI_RESERVED_BYTE, // Reserved
+ EFI_ACPI_RESERVED_BYTE // Reserved
+ },
+ 0xFFFFFFFF, // Local X2APIC ID
+ 0x00000000, // Flags - Disabled (until initialized by platform driver)
+ 0x0000001A, // Processor ID
+ },
+ {
+ EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC, // Type
+ sizeof (EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC_STRUCTURE), // Length
+ {
+ EFI_ACPI_RESERVED_BYTE, // Reserved
+ EFI_ACPI_RESERVED_BYTE // Reserved
+ },
+ 0xFFFFFFFF, // Local X2APIC ID
+ 0x00000000, // Flags - Disabled (until initialized by platform driver)
+ 0x0000001B, // Processor ID
+ },
+ {
+ EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC, // Type
+ sizeof (EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC_STRUCTURE), // Length
+ {
+ EFI_ACPI_RESERVED_BYTE, // Reserved
+ EFI_ACPI_RESERVED_BYTE // Reserved
+ },
+ 0xFFFFFFFF, // Local X2APIC ID
+ 0x00000000, // Flags - Disabled (until initialized by platform driver)
+ 0x0000001C, // Processor ID
+ },
+ {
+ EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC, // Type
+ sizeof (EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC_STRUCTURE), // Length
+ {
+ EFI_ACPI_RESERVED_BYTE, // Reserved
+ EFI_ACPI_RESERVED_BYTE // Reserved
+ },
+ 0xFFFFFFFF, // Local X2APIC ID
+ 0x00000000, // Flags - Disabled (until initialized by platform driver)
+ 0x0000001D, // Processor ID
+ },
+ {
+ EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC, // Type
+ sizeof (EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC_STRUCTURE), // Length
+ {
+ EFI_ACPI_RESERVED_BYTE, // Reserved
+ EFI_ACPI_RESERVED_BYTE // Reserved
+ },
+ 0xFFFFFFFF, // Local X2APIC ID
+ 0x00000000, // Flags - Disabled (until initialized by platform driver)
+ 0x0000001E, // Processor ID
+ },
+ {
+ EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC, // Type
+ sizeof (EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC_STRUCTURE), // Length
+ {
+ EFI_ACPI_RESERVED_BYTE, // Reserved
+ EFI_ACPI_RESERVED_BYTE // Reserved
+ },
+ 0xFFFFFFFF, // Local X2APIC ID
+ 0x00000000, // Flags - Disabled (until initialized by platform driver)
+ 0x0000001F, // Processor ID
+ },
+ {
+ EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC, // Type
+ sizeof (EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC_STRUCTURE), // Length
+ {
+ EFI_ACPI_RESERVED_BYTE, // Reserved
+ EFI_ACPI_RESERVED_BYTE // Reserved
+ },
+ 0xFFFFFFFF, // Local X2APIC ID
+ 0x00000000, // Flags - Disabled (until initialized by platform driver)
+ 0x00000020, // Processor ID
+ }
+ },
+
+ //
+ // Sample IO APIC Structure
+ //
+ //EFI_ACPI_6_3_IO_APIC, // Type
+ //sizeof (EFI_ACPI_6_3_IO_APIC_STRUCTURE), // Length
+ //0x00, // IO APIC ID
+ //EFI_ACPI_RESERVED_BYTE, // Reserved
+ //0x00000000, // IO APIC Address (physical)
+ //0x00000000, // Global System Interrupt Base
+ {
+ {
+ //
+ // I/O SAPIC (ICH)
+ //
+ EFI_ACPI_6_3_IO_APIC, // Type
+ sizeof (EFI_ACPI_6_3_IO_APIC_STRUCTURE), // Length
+ FixedPcdGet8 (PcdApicIoIdPch), // IO APIC ID
+ EFI_ACPI_RESERVED_BYTE, // Reserved
+ FixedPcdGet64 (PcdApicIoAddress), // IO APIC Address (physical)
+ 0x18 * 0 // Global System Interrupt Base
+ }
+ },
+
+ //
+ // Sample Interrupt Source Override Structure
+ //
+ //EFI_ACPI_6_3_INTERRUPT_SOURCE_OVERRIDE, // Type
+ //sizeof (EFI_ACPI_6_3_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE), // Length
+ //0x00, // Bus
+ //0x00, // Source
+ //0x00000000, // Global System Interrupt
+ //0x0000, // Flags
+ {
+ {
+ //
+ // IRQ0=>IRQ2 Interrupt Source Override Structure
+ //
+ EFI_ACPI_6_3_INTERRUPT_SOURCE_OVERRIDE, // Type
+ sizeof (EFI_ACPI_6_3_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE),// Length
+ 0x00, // Bus - ISA
+ 0x00, // Source - IRQ0
+ 0x00000002, // Global System Interrupt - IRQ2
+ 0x0000 // Flags - Conforms to specifications of the bus
+ },
+ {
+ //
+ // ISO (SCI Active High) Interrupt Source Override Structure
+ //
+ EFI_ACPI_6_3_INTERRUPT_SOURCE_OVERRIDE, // Type
+ sizeof (EFI_ACPI_6_3_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE),// Length
+ 0x00, // Bus - ISA
+ 0x09, // Source - IRQ9
+ 0x00000009, // Global System Interrupt - IRQ9
+ 0x000D // Flags - Level-tiggered, Active High
+ }
+ },
+
+ //
+ // Sample Local X2APIC NMI Structure
+ //
+ //EFI_ACPI_6_3_LOCAL_X2APIC_NMI, // Type 0x0A
+ //sizeof (EFI_ACPI_6_3_LOCAL_X2APIC_NMI_STRUCTURE), // Length 0x0C
+ //0x000D, // Flags - Level-tiggered, Active High
+ //0xFFFFFFFF, // Processor ID
+ //0x01, // Local APIC LINT#
+ //EFI_ACPI_RESERVED_BYTE, // Reserved
+ //EFI_ACPI_RESERVED_BYTE, // Reserved
+ //EFI_ACPI_RESERVED_BYTE, // Reserved
+ {
+ {
+ EFI_ACPI_6_3_LOCAL_X2APIC_NMI, // Type
+ sizeof (EFI_ACPI_6_3_LOCAL_X2APIC_NMI_STRUCTURE), // Length
+ 0x000D, // Flags - Level-tiggered, Active High
+ 0xFFFFFFFF, // Processor ID
+ 0x01, // Local APIC LINT#
+ {
+ EFI_ACPI_RESERVED_BYTE, // Reserved
+ EFI_ACPI_RESERVED_BYTE, // Reserved
+ EFI_ACPI_RESERVED_BYTE // Reserved
+ }
+ }
+ }
+
+};
+
+#ifdef __GNUC__
+VOID*
+ReferenceAcpiTable (
+ VOID
+ )
+
+{
+ //
+ // Reference the table being generated to prevent the optimizer from removing the
+ // data structure from the executable
+ //
+ return (VOID*)&Madtx2Apic;
+}
+#else
+VOID
+main (
+ VOID
+ )
+{
+}
+#endif
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AcpiTables/Mcfg/Mcfg.act b/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AcpiTables/Mcfg/Mcfg.act
new file mode 100644
index 0000000000..47f2a15336
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AcpiTables/Mcfg/Mcfg.act
@@ -0,0 +1,91 @@
+/** @file
+ This file contains a structure definition for the ACPI Memory Mapped Configuration
+ Address Space table (MCFG). Any changes to the number of entries in the table require
+ updating the structure count in Mcfg.h and then adding the structure to the
+ MCFG defined in this file. The table layout is defined in Mcfg.h and the
+ table contents are defined in the MemoryMappedConfigurationSpaceAccessTable.h.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+//
+// Statements that include other files
+//
+
+#include "Mcfg.h"
+
+//
+// Multiple APIC Description Table
+//
+
+EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_DESCRIPTION_TABLE Madt = {
+ {
+ EFI_ACPI_3_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE,
+ sizeof (EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_DESCRIPTION_TABLE),
+ EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_TABLE_REVISION,
+
+ //
+ // Checksum will be updated at runtime
+ //
+ 0x00,
+
+ //
+ // It is expected that these values will be programmed at runtime
+ //
+ { ' ', ' ', ' ', ' ', ' ', ' ' },
+
+ 0,
+ EFI_ACPI_OEM_MCFG_REVISION,
+ 0,
+ 0
+ },
+
+ //
+ // Reserved
+ //
+ 0x0000000000000000,
+
+ //
+ // MCFG specific fields
+ //
+ {
+ {
+ 0x0000000000000000, // BaseAddress, will be updated by AcpiPlatform
+ 0x0000, // PciSegmentGroupNumber
+ 0x00, // StartBusNumber
+ 0x00, // EndBusNumber, will be updated by AcpiPlatform
+ 0x00000000 // Reserved
+ },
+ {
+ 0x0000000000000000, // BaseAddress, will be updated by AcpiPlatform
+ 0x0001, // PciSegmentGroupNumber
+ 0x00, // StartBusNumber
+ 0xFF, // EndBusNumber, If extra segment is presented, it must support Bus Number from 0x00 ~ 0xFF
+ 0x00000000 // Reserved
+ }
+ }
+};
+
+#ifdef __GNUC__
+VOID*
+ReferenceAcpiTable (
+ VOID
+ )
+
+{
+ //
+ // Reference the table being generated to prevent the optimizer from removing the
+ // data structure from the exeutable
+ //
+ return (VOID*)&Madt;
+}
+#else
+VOID
+main (
+ VOID
+ )
+{
+}
+#endif
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AcpiTables/Mcfg/Mcfg.h b/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AcpiTables/Mcfg/Mcfg.h
new file mode 100644
index 0000000000..627d66a81d
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AcpiTables/Mcfg/Mcfg.h
@@ -0,0 +1,53 @@
+/** @file
+ This file describes the contents of the ACPI Memory Mapped Configuration
+ Space Access Table (MCFG).
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _MCFG_H_
+#define _MCFG_H_
+
+//
+// Statements that include other files
+//
+
+#include <IndustryStandard/Acpi30.h>
+#include <IndustryStandard/MemoryMappedConfigurationSpaceAccessTable.h>
+
+//
+// MCFG Definitions
+//
+
+#define EFI_ACPI_OEM_MCFG_REVISION 0x00000001
+
+//
+// Define the number of allocation structures so that we can build the table structure.
+//
+#define EFI_ACPI_ALLOCATION_STRUCTURE_COUNT 2
+
+//
+// MCFG structure
+//
+
+//
+// Ensure proper structure formats
+//
+#pragma pack (1)
+
+//
+// MCFG Table structure
+//
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT64 Reserved;
+#if EFI_ACPI_ALLOCATION_STRUCTURE_COUNT > 0
+ EFI_ACPI_MEMORY_MAPPED_ENHANCED_CONFIGURATION_SPACE_BASE_ADDRESS_ALLOCATION_STRUCTURE AllocationStructure[EFI_ACPI_ALLOCATION_STRUCTURE_COUNT];
+#endif
+} EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_DESCRIPTION_TABLE;
+
+#pragma pack ()
+
+#endif
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AdvancedAcpiDxe/AcpiByteStream.h b/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AdvancedAcpiDxe/AcpiByteStream.h
new file mode 100644
index 0000000000..b2b6cdf77c
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AdvancedAcpiDxe/AcpiByteStream.h
@@ -0,0 +1,137 @@
+/**@file
+ Byte stream structures for ACPI
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _ACPI_BYTE_STREAM_H_
+#define _ACPI_BYTE_STREAM_H_
+
+#include <IndustryStandard/Acpi.h>
+
+// @todo: Push these macros to Acpi.h file in Edk2 core.
+
+//
+// Definition block ecoding
+//
+
+//
+// External byte stream values and offsets
+//
+#define ACPI_EXTERNAL_PCI_BUS_NUMBER_OFFSET 0xA
+
+
+#define ACPI_SCOPE_PCI_BUS_NUMBER_OFFSET 0x9
+
+
+
+#define ACPI_NAME_OBJECT_STRING_OFFSET 0x6
+
+
+#define ACPI_UNIQUE_ID_NUMBER_OFFSET 0x5
+
+
+#define ACPI_BYTE_PREFIX_OPCODE 0x0A
+#define ACPI_WORD_PREFIX_OPCODE 0x0B
+
+#define ACPI_I2C_RESOURCE_CONTROLLER_NUMBER_OFFSET 0x1F
+
+#define ACPI_STA_RETURN_VALUE_OFFSET 0x9
+#define ACPI_STA_RETURN_VALUE_DEVICE_ENABLED 0xF
+#define ACPI_STA_RETURN_VALUE_DEVICE_DISABLED 0x0
+
+#define ACPI_GPIO_RESOURCE_TYPE 0x1
+#define ACPI_GPIO_RESOURCE_TYPE_INTERRUPT 0x1
+#define ACPI_GPIO_RESOURCE_TYPE_IO 0x2
+
+#define ACPI_I2C_RESOURCE_TYPE 0x2
+
+#define ASCII_0_ORDINAL ((UINT32) '0')
+
+typedef struct {
+ UINT8 GpioConnectionDescriptor; // 0x8C
+ UINT8 Length1;
+ UINT8 Length2;
+ UINT8 RevisionId;
+ UINT8 GpioConnectionType; // 0x0 - Interrupt, 0x01 - IO Connection, 0x02-0xFF reserved
+ UINT8 GeneralFlags1;
+ UINT8 GeneralFlags2;
+ UINT8 InterruptAndIoFlags1;
+ UINT8 InterruptAndIoFlags2;
+ UINT8 PinConfiguration;
+ UINT8 OutputDriveStrength1;
+ UINT8 OutputDriveStrength2;
+ UINT8 DebounceTimeOut1;
+ UINT8 DebounceTimeOut2;
+ UINT8 PinTableOffset1;
+ UINT8 PinTableOffset2;
+ UINT8 ResourceSourceIndex;
+ UINT8 ResourceSourceNameOffset1;
+ UINT8 ResourceSourceNameOffset2;
+ UINT8 VendorDataOffset1;
+ UINT8 VendorDataOffset2;
+ UINT8 VendorDataLength1;
+ UINT8 VendorDataLength2;
+ UINT8 PinNumber1;
+ UINT8 PinNumber2;
+ CHAR8 ResourceSource[15];
+} GPIO_RESOURCE;
+
+typedef enum {
+ GpioInterrupt,
+ GpioIo
+} GPIO_CONNECTION_TYPE;
+
+typedef struct {
+ UINT8 I2cBusConnectionDescriptor; // 0x8E
+ UINT8 Length1;
+ UINT8 Length2;
+ UINT8 RevisionId;
+ UINT8 ResourceSourceIndex;
+ UINT8 SerialBusType; // 0x1 for I2C
+ UINT8 GeneralFlags;
+ UINT8 TypeSpecificFlags1;
+ UINT8 TypeSpecificFlags2;
+ UINT8 TypeSpecificRevisionId; // 0x1 for I2C
+ UINT8 TypeDataLength1; // minimum value 0x6
+ UINT8 TypeDataLength2; // minimum value 0x0
+ UINT32 ConnectionSpeed;
+ UINT16 SlaveAddress;
+ CHAR8 ResourceSource[15];
+} I2C_SERIAL_BUS_RESOURCE;
+
+typedef struct {
+ UINT8 ResourceType;
+ UINT16 GpioNumber;
+ UINT8 GpioResourceType;
+ BOOLEAN Shared;
+} GPIO_RESOURCE_DATA;
+
+typedef struct {
+ UINT8 ResourceType;
+ UINT32 I2cSlaveAddress;
+ UINT32 ConnectionSpeed;
+ UINT8 I2cSliceNumber;
+} I2C_RESOURCE_DATA;
+
+typedef struct {
+ CHAR8 DeviceName[4];
+ CHAR8 HardwareId[8];
+ CHAR8 CompatibilityId[8];
+ UINT32 UniqueId;
+ UINT8 Address;
+ CHAR8 DosDeviceName[32];
+ UINT8 EnableStatus;
+ UINT8 NumberOfResources;
+} SSDT_DEVICE_DATA;
+
+typedef struct {
+ EFI_GUID Guid;
+ UINT8 Revision;
+ UINT16 Count;
+ UINT8 Rsvd[5];
+} PCT_ACPI_BLOCK_HDR;
+
+#endif
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AdvancedAcpiDxe/AcpiPlatform.c b/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AdvancedAcpiDxe/AcpiPlatform.c
new file mode 100644
index 0000000000..3a70d0b1b7
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AdvancedAcpiDxe/AcpiPlatform.c
@@ -0,0 +1,1716 @@
+/** @file
+ Advanced ACPI Driver
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+#include <Base.h>
+#include <Uefi.h>
+#include <Library/HobLib.h>
+#include <Guid/HobList.h>
+#include <Protocol/FirmwareVolume2.h>
+#include <PlatformBoardId.h>
+#include <IndustryStandard/AcpiAml.h>
+#include <IndustryStandard/Pci30.h>
+#include "AcpiPlatform.h"
+#include <Library/PciSegmentLib.h>
+#include <Library/PchInfoLib.h>
+#include <Library/PchPcieRpLib.h>
+#include <Library/GpioLib.h>
+#include <Library/EspiLib.h>
+#include <Library/PchPciBdfLib.h>
+#include <PlatformBoardConfig.h>
+#include <Library/CpuPlatformLib.h>
+#include <Protocol/VariableLock.h>
+#include <Mcfg.h>
+#include <Library/GraphicsInfoLib.h>
+#include "GenSsdtLib.h"
+// Global variables
+//
+GLOBAL_REMOVE_IF_UNREFERENCED VOID *mGfxNvsAddress;
+GLOBAL_REMOVE_IF_UNREFERENCED PLATFORM_NVS_AREA_PROTOCOL mPlatformNvsAreaProtocol;
+
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_CPU_IO2_PROTOCOL *mCpuIo;
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_CPU_ID_ORDER_MAP *mCpuApicIdOrderTable;
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_CPU_APIC_ID_REORDER_MAP *mCpuApicIdReorderTable;
+GLOBAL_REMOVE_IF_UNREFERENCED UINTN mNumberOfCpus;
+GLOBAL_REMOVE_IF_UNREFERENCED UINTN mNumberOfEnabledCpus;
+GLOBAL_REMOVE_IF_UNREFERENCED BOOLEAN IsX2ApicMode;
+
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_CPU_PACKAGE_INFO mSbspPackageInfo;
+//
+// Function implementations
+//
+
+/**
+ Install Soc ACPI Table
+
+ @param[in] *SsdtTableGuid Pointer to GUID that identifies new SSDT table
+ @param[in] Signature Signature of the table
+
+**/
+VOID
+STATIC
+InstallSocAcpiTable (
+ IN EFI_GUID *SsdtTableGuid,
+ IN UINT64 Signature
+ )
+{
+ EFI_STATUS Status;
+ EFI_HANDLE *HandleBuffer;
+ UINTN NumberOfHandles;
+ UINTN Index;
+ INTN Instance;
+ UINTN Size;
+ UINT32 FvStatus;
+ UINTN TableHandle;
+ EFI_FV_FILETYPE FileType;
+ EFI_FV_FILE_ATTRIBUTES Attributes;
+ EFI_FIRMWARE_VOLUME2_PROTOCOL *FwVol;
+ EFI_ACPI_TABLE_PROTOCOL *AcpiTable;
+ EFI_ACPI_DESCRIPTION_HEADER *TableHeader;
+ EFI_ACPI_COMMON_HEADER *Table;
+
+ FwVol = NULL;
+ Table = NULL;
+
+ //
+ // Locate FV protocol.
+ //
+ Status = gBS->LocateHandleBuffer (
+ ByProtocol,
+ &gEfiFirmwareVolume2ProtocolGuid,
+ NULL,
+ &NumberOfHandles,
+ &HandleBuffer
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Look for FV with ACPI storage file
+ //
+ for (Index = 0; Index < NumberOfHandles; Index++) {
+ //
+ // Get the protocol on this handle
+ // This should not fail because of LocateHandleBuffer
+ //
+ Status = gBS->HandleProtocol (
+ HandleBuffer[Index],
+ &gEfiFirmwareVolume2ProtocolGuid,
+ (VOID **) &FwVol
+ );
+ ASSERT_EFI_ERROR (Status);
+ if (FwVol == NULL) {
+ return;
+ }
+ //
+ // See if it has the ACPI storage file
+ //
+ Size = 0;
+ FvStatus = 0;
+ Status = FwVol->ReadFile (
+ FwVol,
+ SsdtTableGuid,
+ NULL,
+ &Size,
+ &FileType,
+ &Attributes,
+ &FvStatus
+ );
+ if (!EFI_ERROR (Status)) {
+ break;
+ }
+ }
+ //
+ // Free any allocated buffers
+ //
+ FreePool (HandleBuffer);
+
+ //
+ // Sanity check that we found our data file
+ //
+ ASSERT (FwVol);
+
+ //
+ // Locate ACPI tables
+ //
+ Status = gBS->LocateProtocol (&gEfiAcpiTableProtocolGuid, NULL, (VOID **) &AcpiTable);
+
+ //
+ // Read tables from the storage file.
+ //
+ if (FwVol == NULL) {
+ ASSERT_EFI_ERROR (EFI_NOT_FOUND);
+ return;
+ }
+ Instance = 0;
+
+ while (Status == EFI_SUCCESS) {
+ //
+ // Read the ACPI tables
+ //
+ Status = FwVol->ReadSection (
+ FwVol,
+ SsdtTableGuid,
+ EFI_SECTION_RAW,
+ Instance,
+ (VOID **) &Table,
+ &Size,
+ &FvStatus
+ );
+ if (!EFI_ERROR (Status)) {
+ TableHeader = (EFI_ACPI_DESCRIPTION_HEADER *) Table;
+
+ if (((EFI_ACPI_DESCRIPTION_HEADER *) TableHeader)->OemTableId == Signature) {
+ TableHandle = 0;
+ //
+ // Add the table
+ //
+ Status = AcpiTable->InstallAcpiTable (
+ AcpiTable,
+ TableHeader,
+ TableHeader->Length,
+ &TableHandle
+ );
+ }
+
+ //
+ // Increment the instance
+ //
+ Instance++;
+ Table = NULL;
+ }
+ }
+}
+
+/**
+ Install Xhci ACPI Table
+**/
+VOID
+InstallXhciAcpiTable (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+ EFI_FIRMWARE_VOLUME2_PROTOCOL *FwVol;
+ EFI_ACPI_COMMON_HEADER *CurrentTable;
+ UINT32 FvStatus;
+ UINTN Size;
+ UINTN TableHandle;
+ INTN Instance;
+ EFI_ACPI_TABLE_PROTOCOL *AcpiTable;
+ EFI_ACPI_DESCRIPTION_HEADER *TableHeader;
+ EFI_GUID EfiAcpiMultiTableStorageGuid;
+
+ EfiAcpiMultiTableStorageGuid = gAcpiTableStorageGuid;
+ Instance = 0;
+ TableHandle = 0;
+ CurrentTable = NULL;
+ FwVol = NULL;
+
+ DEBUG ((DEBUG_INFO, "InstallXhciAcpiTable\n"));
+ //
+ // Update OEM table ID
+ //
+ if (PcdGet64 (PcdXhciAcpiTableSignature) == 0) {
+ DEBUG ((DEBUG_INFO, "InstallXhciAcpiTable: Cannot find PcdXhciAcpiTableSignature\n"));
+ return;
+ }
+
+ //
+ // Find the AcpiSupport protocol
+ //
+ Status = LocateSupportProtocol (
+ &gEfiAcpiTableProtocolGuid,
+ EfiAcpiMultiTableStorageGuid,
+ (VOID **) &AcpiTable,
+ FALSE
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Locate the firmware volume protocol
+ //
+ Status = LocateSupportProtocol (
+ &gEfiFirmwareVolume2ProtocolGuid,
+ EfiAcpiMultiTableStorageGuid,
+ (VOID **) &FwVol,
+ TRUE
+ );
+
+ //
+ // Read tables from the storage file.
+ //
+ while (Status == EFI_SUCCESS) {
+ Status = FwVol->ReadSection (
+ FwVol,
+ &EfiAcpiMultiTableStorageGuid,
+ EFI_SECTION_RAW,
+ Instance,
+ (VOID **) &CurrentTable,
+ &Size,
+ &FvStatus
+ );
+
+ if (!EFI_ERROR (Status)) {
+
+ TableHeader = (EFI_ACPI_DESCRIPTION_HEADER *) CurrentTable;
+
+ if (TableHeader->OemTableId == PcdGet64 (PcdXhciAcpiTableSignature)) {
+ DEBUG ((DEBUG_INFO, "Install xhci table: %x\n", TableHeader->OemTableId));
+ //
+ // Add the table
+ //
+ TableHandle = 0;
+
+ Status = AcpiTable->InstallAcpiTable (
+ AcpiTable,
+ CurrentTable,
+ CurrentTable->Length,
+ &TableHandle
+ );
+
+ break;
+ }
+
+ //
+ // Increment the instance
+ //
+ Instance++;
+ gBS->FreePool (CurrentTable);
+ CurrentTable = NULL;
+ }
+ }
+
+ if (CurrentTable != NULL) {
+ gBS->FreePool (CurrentTable);
+ CurrentTable = NULL;
+ }
+}
+
+/**
+ Locate the first instance of a protocol. If the protocol requested is an
+ FV protocol, then it will return the first FV that contains the ACPI table
+ storage file.
+
+ @param[in] Protocol The protocol to find.
+ @param[in] Instance Return pointer to the first instance of the protocol.
+ @param[in] Type TRUE if the desired protocol is a FV protocol.
+
+ @retval EFI_SUCCESS The function completed successfully.
+ @retval EFI_NOT_FOUND The protocol could not be located.
+ @retval EFI_OUT_OF_RESOURCES There are not enough resources to find the protocol.
+**/
+EFI_STATUS
+LocateSupportProtocol (
+ IN EFI_GUID *Protocol,
+ IN EFI_GUID gEfiAcpiMultiTableStorageGuid,
+ OUT VOID **Instance,
+ IN BOOLEAN Type
+ )
+{
+ EFI_STATUS Status;
+ EFI_HANDLE *HandleBuffer;
+ UINTN NumberOfHandles;
+ EFI_FV_FILETYPE FileType;
+ UINT32 FvStatus;
+ EFI_FV_FILE_ATTRIBUTES Attributes;
+ UINTN Size;
+ UINTN Index;
+
+ //
+ // Locate protocol.
+ //
+ Status = gBS->LocateHandleBuffer (
+ ByProtocol,
+ Protocol,
+ NULL,
+ &NumberOfHandles,
+ &HandleBuffer
+ );
+ if (EFI_ERROR (Status)) {
+ //
+ // Defined errors at this time are not found and out of resources.
+ //
+ return Status;
+ }
+
+ //
+ // Looking for FV with ACPI storage file
+ //
+ for (Index = 0; Index < NumberOfHandles; Index++) {
+
+ //
+ // Get the protocol on this handle
+ // This should not fail because of LocateHandleBuffer
+ //
+ Status = gBS->HandleProtocol (
+ HandleBuffer[Index],
+ Protocol,
+ Instance
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ if (!Type) {
+
+ //
+ // Not looking for the FV protocol, so find the first instance of the
+ // protocol. There should not be any errors because our handle buffer
+ // should always contain at least one or LocateHandleBuffer would have
+ // returned not found.
+ //
+ break;
+ }
+
+ //
+ // See if it has the ACPI storage file
+ //
+ Size = 0;
+ FvStatus = 0;
+ Status = ((EFI_FIRMWARE_VOLUME2_PROTOCOL *) (*Instance))->ReadFile (
+ *Instance,
+ &gEfiAcpiMultiTableStorageGuid,
+ NULL,
+ &Size,
+ &FileType,
+ &Attributes,
+ &FvStatus
+ );
+
+ //
+ // If we found it, then we are done
+ //
+ if (Status == EFI_SUCCESS) {
+ break;
+ }
+ }
+
+ //
+ // Our exit status is determined by the success of the previous operations
+ // If the protocol was found, Instance already points to it.
+ //
+ //
+ // Free any allocated buffers
+ //
+ FreePool (HandleBuffer);
+
+ return Status;
+}
+
+/**
+ This function will update any runtime platform specific information.
+ This currently includes:
+ Setting OEM table values, ID, table ID, creator ID and creator revision.
+ Enabling the proper processor entries in the APIC tables
+ It also indicates with which ACPI table version the table belongs.
+
+ @param[in] Table The table to update
+ @param[in] Version Where to install this table
+
+ @retval EFI_SUCCESS Updated tables commplete.
+**/
+EFI_STATUS
+PlatformUpdateTables (
+ IN OUT EFI_ACPI_COMMON_HEADER *Table,
+ IN OUT EFI_ACPI_TABLE_VERSION *Version
+ )
+{
+ EFI_ACPI_DESCRIPTION_HEADER *TableHeader;
+ UINT8 *CurrPtr;
+ UINT8 *TmpDsdtPointer;
+ UINT8 *EndPtr;
+ EFI_ACPI_1_0_PROCESSOR_LOCAL_APIC_STRUCTURE *ApicPtr;
+ EFI_STATUS Status;
+ EFI_MP_SERVICES_PROTOCOL *MpService;
+
+ UINT8 MaximumDsdtPointLength;
+
+ EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;
+ UINT32 LocalApicCounter;
+
+
+ CurrPtr = NULL;
+ EndPtr = NULL;
+ ApicPtr = NULL;
+
+ LocalApicCounter = 0;
+ MaximumDsdtPointLength = 20;
+
+ //
+ // This will be accurate except for FACS structure
+ //
+ TableHeader = (EFI_ACPI_DESCRIPTION_HEADER *) Table;
+
+ //
+ // Update the OEM and creator information for every table except FACS.
+ //
+ if (Table->Signature != EFI_ACPI_1_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE) {
+ if ((Table->Signature == EFI_ACPI_1_0_SECONDARY_SYSTEM_DESCRIPTION_TABLE_SIGNATURE) &&
+ (CompareMem (&TableHeader->OemId, "Rtd3", 4) == 0)) {
+ // For SsdtRtd3 table, "OemId" update is done later
+ } else {
+ CopyMem (TableHeader->OemId, PcdGetPtr (PcdAcpiDefaultOemId), sizeof (TableHeader->OemId));
+ }
+
+ //
+ // Skip OEM table ID and creator information for SSDT tables, since these are
+ // created by an ASL compiler and the creator information is useful.
+ //
+ if (Table->Signature != EFI_ACPI_1_0_SECONDARY_SYSTEM_DESCRIPTION_TABLE_SIGNATURE) {
+ //
+ // Set through patchable PCD value
+ //
+ TableHeader->OemTableId = PcdGet64 (PcdAcpiDefaultOemTableId);
+ TableHeader->OemRevision = PcdGet32(PcdAcpiDefaultOemRevision);
+
+ //
+ // Update creator information
+ //
+ TableHeader->CreatorId = PcdGet32 (PcdAcpiDefaultCreatorId);
+ TableHeader->CreatorRevision = PcdGet32 (PcdAcpiDefaultCreatorRevision) ;
+ }
+ }
+
+ //
+ // Locate the PCI IO protocol
+ //
+ Status = gBS->LocateProtocol (
+ &gEfiPciRootBridgeIoProtocolGuid,
+ NULL,
+ (VOID **) &PciRootBridgeIo
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Locate the MP services protocol
+ // Find the MP Protocol. This is an MP platform, so MP protocol must be there.
+ //
+ Status = gBS->LocateProtocol (
+ &gEfiMpServiceProtocolGuid,
+ NULL,
+ (VOID **) &MpService
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Get supported CPU Interrupt model (xApic or x2Apic)
+ //
+ IsX2ApicMode = (GetApicMode() == LOCAL_APIC_MODE_X2APIC) ? TRUE : FALSE;
+
+ //
+ // By default, a table belongs in all ACPI table versions published.
+ // Some tables will override this because they have different versions of the table.
+ //
+ *Version = EFI_ACPI_TABLE_VERSION_1_0B | EFI_ACPI_TABLE_VERSION_2_0 | EFI_ACPI_TABLE_VERSION_3_0;
+
+ //
+ // Update the various table types with the necessary updates
+ //
+ switch (Table->Signature) {
+
+ case EFI_ACPI_1_0_APIC_SIGNATURE:
+ //
+ // if not MP and not APIC then don't publish the APIC tables.
+ //
+ //@todo mSystemConfiguration.ApicEnabled default value is 1. So, the following logic is not executed.
+ //if (mSystemConfiguration.ApicEnabled == 0) {
+ // *Version = EFI_ACPI_TABLE_VERSION_NONE;
+ // break;
+ //}
+ CurrPtr = (UINT8 *) &((EFI_ACPI_DESCRIPTION_HEADER *) Table)[1];
+ CurrPtr = CurrPtr + 8;
+ //
+ // Size of Local APIC Address & Flag
+ //
+ EndPtr = (UINT8 *) Table;
+ EndPtr = EndPtr + Table->Length;
+
+ ApicPtr = (EFI_ACPI_1_0_PROCESSOR_LOCAL_APIC_STRUCTURE *) CurrPtr;
+ DEBUG((DEBUG_INFO, "ApicPtr Type = %x \n ", ApicPtr->Type));
+ if ((IsX2ApicMode && ApicPtr->Type == EFI_ACPI_1_0_PROCESSOR_LOCAL_APIC) ||(!IsX2ApicMode && ApicPtr->Type == EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC)) {
+ // Lets skip the MADT table in below cases:
+ // 1. MADT table with Local APIC records when X2Apic Mode is enabled.
+ // 2. MADT table with x2Apic records when xApic Mode is enabled.
+
+ *Version = EFI_ACPI_TABLE_VERSION_NONE;
+ break;
+ }
+
+ //
+ // Call for Local APIC ID Reorder
+ //
+ SortCpuLocalApicInTable(MpService);
+
+ while (CurrPtr < EndPtr) {
+ ApicPtr = (EFI_ACPI_1_0_PROCESSOR_LOCAL_APIC_STRUCTURE *) CurrPtr;
+
+ //
+ // Check table entry type
+ //
+ if ((ApicPtr->Type == EFI_ACPI_1_0_PROCESSOR_LOCAL_APIC) || (ApicPtr->Type == EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC)) {
+ AppendCpuMapTableEntry (
+ ApicPtr,
+ LocalApicCounter
+ );
+ LocalApicCounter++;
+ }
+
+ //
+ // Go to the next structure in the APIC table
+ //
+ CurrPtr = CurrPtr + ApicPtr->Length;
+ }
+ break;
+
+ case EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE:
+ //
+ // Fix up all FACP Table values if configuration requires it.
+ // This code fixes up the following Table values:
+ // (1) C2/C3/CST Enable FACP values
+ // (2) RTC S4 Flag
+ //
+ {
+ EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE *FadtPointer;
+
+ FadtPointer = (EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE *) Table;
+
+ //
+ // Check the version of the table
+ //
+ *Version = EFI_ACPI_TABLE_VERSION_NONE;
+ if (FadtPointer->Header.Revision == EFI_ACPI_1_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION) {
+ *Version = EFI_ACPI_TABLE_VERSION_NONE;
+ } else if (FadtPointer->Header.Revision == EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION) {
+ *Version = EFI_ACPI_TABLE_VERSION_1_0B | EFI_ACPI_TABLE_VERSION_2_0;
+ } else if (FadtPointer->Header.Revision == EFI_ACPI_3_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION) {
+ *Version = EFI_ACPI_TABLE_VERSION_1_0B | EFI_ACPI_TABLE_VERSION_3_0;
+ } else if (FadtPointer->Header.Revision == EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION) {
+ *Version = EFI_ACPI_TABLE_VERSION_1_0B | EFI_ACPI_TABLE_VERSION_5_0;
+ } else if (FadtPointer->Header.Revision == EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE_REVISION) {
+ *Version = EFI_ACPI_TABLE_VERSION_5_0;
+ } else if (FadtPointer->Header.Revision == EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE_REVISION) {
+ *Version = EFI_ACPI_TABLE_VERSION_5_0;
+ }
+
+
+ //
+ // Modify Preferred_PM_Profile field based on Board SKU's. Default is set to Mobile
+ //
+ FadtPointer->PreferredPmProfile = PcdGet8 (PcdPreferredPmProfile);
+
+
+ //
+ // PME WAKE supported, set PCI_EXP_WAK, BIT14 of Fixed feature flags.
+ //
+ FadtPointer->Flags |= (EFI_ACPI_6_0_PCI_EXP_WAK);
+
+ FadtPointer->Flags &= ~(EFI_ACPI_2_0_PWR_BUTTON); // clear indicates the power button is handled as a fixed feature programming model
+
+ //
+ // 1. set header revision.
+ //
+ FadtPointer->Header.Revision = EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE_REVISION;
+
+ //
+ // 2. set all GAR register AccessSize to valid value.
+ //
+ ((EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE *)FadtPointer)->ResetReg.AccessSize = EFI_ACPI_6_3_BYTE;
+ ((EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE *)FadtPointer)->XPm1aEvtBlk.AccessSize = EFI_ACPI_6_3_WORD;
+ ((EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE *)FadtPointer)->XPm1bEvtBlk.AccessSize = EFI_ACPI_6_3_WORD;
+ ((EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE *)FadtPointer)->XPm1aCntBlk.AccessSize = EFI_ACPI_6_3_WORD;
+ ((EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE *)FadtPointer)->XPm1bCntBlk.AccessSize = EFI_ACPI_6_3_WORD;
+ ((EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE *)FadtPointer)->XPm2CntBlk.AccessSize = EFI_ACPI_6_3_BYTE;
+ ((EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE *)FadtPointer)->XPmTmrBlk.AccessSize = EFI_ACPI_6_3_DWORD;
+ ((EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE *)FadtPointer)->XGpe0Blk.AccessSize = EFI_ACPI_6_3_BYTE;
+ ((EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE *)FadtPointer)->XGpe1Blk.AccessSize = EFI_ACPI_6_3_BYTE;
+
+ //
+ // SLEEP_CONTROL_REG and SLEEP_STATUS_REG are optional
+ // Only implement in HW-Reduced ACPI system
+ // In non-HW-Reduced system will remain all 0 as default
+ //
+ if ((FadtPointer->Flags & EFI_ACPI_6_3_HW_REDUCED_ACPI) != 0) {
+ //
+ // If the HW_REDUCED_ACPI flag in the table is set, OSPM will ignore fields related to the ACPI HW
+ //
+ ((EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE *)FadtPointer)->SleepControlReg.AddressSpaceId = 0x1;
+ ((EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE *)FadtPointer)->SleepControlReg.RegisterBitWidth = 0x8;
+ ((EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE *)FadtPointer)->SleepControlReg.RegisterBitOffset = 0;
+ ((EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE *)FadtPointer)->SleepControlReg.AccessSize = EFI_ACPI_6_3_DWORD;
+ ((EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE *)FadtPointer)->SleepControlReg.Address = EFI_ACPI_PM1A_EVT_BLK_ADDRESS + 4;
+
+ ((EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE *)FadtPointer)->SleepStatusReg.AddressSpaceId = 0x1;
+ ((EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE *)FadtPointer)->SleepStatusReg.RegisterBitWidth = 0x8;
+ ((EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE *)FadtPointer)->SleepStatusReg.RegisterBitOffset = 0;
+ ((EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE *)FadtPointer)->SleepStatusReg.AccessSize = EFI_ACPI_6_3_DWORD;
+ ((EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE *)FadtPointer)->SleepStatusReg.Address = EFI_ACPI_PM1A_EVT_BLK_ADDRESS;
+ }
+
+ //
+ // Set the S4BiosReq to 0 as we don't support it in the FACS for TGL.
+ //
+ FadtPointer->S4BiosReq = 0;
+
+ //@todo RtcS4WakeEnable and PmTimerEnable default value is 1. So, the following logic is not executed.
+ ////
+ //// Check if RTC S4 is enabled
+ ////
+ //if (!mSystemConfiguration.RtcS4WakeEnable) {
+
+ // //
+ // // Clear the S4 RTC flag
+ // //
+ // FadtPointer->Flags &= ~EFI_ACPI_2_0_RTC_S4;
+ //}
+
+ ////
+ //// Check if PM timer is enabled
+ ////
+ //if (!mSystemConfiguration.PmTimerEnable) {
+
+ // //
+ // // Clear the PM timer flag
+ // //
+ // FadtPointer->Flags &= ~EFI_ACPI_3_0_USE_PLATFORM_CLOCK;
+ //}
+ }
+ break;
+
+ case EFI_ACPI_1_0_PERSISTENT_SYSTEM_DESCRIPTION_TABLE_SIGNATURE:
+ //
+ // These items only belong in the 1.0 tables.
+ //
+ *Version = EFI_ACPI_TABLE_VERSION_1_0B;
+ break;
+
+ case EFI_ACPI_2_0_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE:
+ //
+ // Fix up the AML code in the DSDT affected by end user options.
+ // Fix up the following ASL Code:
+ // (1) ACPI Global NVS Memory Base and Size.
+ // (2) ACPI Graphics NVS Memory Base and Size.
+ // (3) SMBus I/O Base.
+ // (4) Thermal Management Methods.
+ //
+ {
+ UINT8 *DsdtPointer;
+ UINT32 *Signature;
+ UINT8 *Operation;
+ UINT32 *Address;
+ UINT8 *Value;
+ UINT16 *Size;
+ //
+ // Loop through the ASL looking for values that we must fix up.
+ //
+ CurrPtr = (UINT8 *) Table;
+ for (DsdtPointer = CurrPtr;
+ DsdtPointer < (CurrPtr + ((EFI_ACPI_COMMON_HEADER *) CurrPtr)->Length - sizeof (UINT32));
+ DsdtPointer++
+ ) {
+ Signature = (UINT32 *) DsdtPointer;
+ switch (*Signature) {
+ //
+ // GNVS operation region
+ //
+ case (SIGNATURE_32 ('G', 'N', 'V', 'S')):
+ //
+ // Conditional match. For Region Objects, the Operator will always be the
+ // byte immediately before the specific name. Therefore, subtract 1 to check
+ // the Operator.
+ //
+ Operation = DsdtPointer - 1;
+ if (*Operation == AML_EXT_REGION_OP) {
+ Address = (UINT32 *) (DsdtPointer + 6);
+ *Address = (UINT32) (UINTN) mPlatformNvsAreaProtocol.Area;
+ Size = (UINT16 *) (DsdtPointer + 11);
+ *Size = sizeof (PLATFORM_NVS_AREA);
+ }
+ break;
+
+ //
+ // _UPC method for Device (\_SB.PC00.XHCI.RHUB)
+ //
+ case (SIGNATURE_32('H', 'S', '1', '3')):
+ for (TmpDsdtPointer = DsdtPointer;
+ TmpDsdtPointer <= DsdtPointer + MaximumDsdtPointLength;
+ TmpDsdtPointer++){
+ Signature = (UINT32 *) TmpDsdtPointer;
+ switch (*Signature) {
+ case(SIGNATURE_32('U', 'P', 'C', 'P')):
+ Value = (UINT8 *)((UINT32 *)TmpDsdtPointer + 2);
+ break;
+ default:
+ //
+ // Do nothing.
+ //
+ break;
+ }
+ }
+ break;
+
+
+
+ default:
+ //
+ // Do nothing.
+ //
+ break;
+ }
+ }
+ }
+ break;
+
+ case EFI_ACPI_3_0_HIGH_PRECISION_EVENT_TIMER_TABLE_SIGNATURE:
+ break;
+
+ case EFI_ACPI_3_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE:
+ //
+ // Update MCFG base and end bus number
+ //
+ ((EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_DESCRIPTION_TABLE *) Table)->AllocationStructure[0].BaseAddress
+ = PcdGet64 (PcdPciExpressBaseAddress);
+
+ ((EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_DESCRIPTION_TABLE *) Table)->AllocationStructure[0].EndBusNumber
+ = (UINT8)(PcdGet32 (PcdPciExpressRegionLength) / 0x100000) - 1;
+
+
+ {
+ ((EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_DESCRIPTION_TABLE *) Table)->Header.Length -= sizeof (EFI_ACPI_MEMORY_MAPPED_ENHANCED_CONFIGURATION_SPACE_BASE_ADDRESS_ALLOCATION_STRUCTURE);
+ }
+ break;
+
+ case EFI_ACPI_5_0_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE_SIGNATURE:
+ //
+ // If EC is not present, don't publish the table.
+ //
+ if (mPlatformNvsAreaProtocol.Area->EcAvailable == PLATFORM_NVS_DEVICE_DISABLE) {
+ *Version = EFI_ACPI_TABLE_VERSION_NONE;
+ }
+ break;
+
+/* @todo Need to uncomment once MSFT fully implements uPEP
+ case SIGNATURE_32 ('L', 'P', 'I', 'T'):
+ //
+ // If L0s is disabled in setup, don't publish the table.
+ //
+ if (mSystemConfiguration.LowPowerS0Idle == 0) {
+ *Version = EFI_ACPI_TABLE_VERSION_NONE;
+ }
+ break;
+*/
+ case EFI_ACPI_1_0_SECONDARY_SYSTEM_DESCRIPTION_TABLE_SIGNATURE:
+ {
+ UINT8 *TablePointer;
+ UINT32 *Signature;
+
+ //
+ // Do not load the xHCI table. It is handled by separate function.
+ //
+ if (CompareMem (&TableHeader->OemTableId, "xh_", 3) == 0) {
+ DEBUG((DEBUG_INFO,"TableHeader->OemTableId = %x\n ", TableHeader->OemTableId));
+ *Version = EFI_ACPI_TABLE_VERSION_NONE;
+ }
+
+ //
+ // Load SSDT tables for the platforms based on boardID; default to RVP tables.
+ // Load Ther_Rvp for all others.
+ //
+ if (CompareMem (&TableHeader->OemTableId, "Ther_Rvp", 8) == 0) {
+ CurrPtr = (UINT8 *) Table;
+ for (TablePointer = CurrPtr;TablePointer < (CurrPtr + ((EFI_ACPI_COMMON_HEADER *) CurrPtr)->Length - sizeof (UINT32));TablePointer++)
+ {
+ Signature = (UINT32 *) TablePointer;
+ switch (*Signature) {
+ }
+ }
+ }
+
+ //
+ // Load RTD3 SSDT table for ADL RVP SKUs
+ // Note: "OemId" field is used to indentify whether SSDT table is for RTD3 usage
+ //
+ if ((CompareMem (&TableHeader->OemId, "Rtd3", 4) == 0)) {
+ //
+ // OemId should be replaced with PcdAcpiDefaultOemId
+ //
+ CopyMem (TableHeader->OemId, PcdGetPtr (PcdAcpiDefaultOemId), sizeof (TableHeader->OemId));
+ //
+ // set default = none
+ //
+ *Version = EFI_ACPI_TABLE_VERSION_NONE;
+ } // Load RTD3 SSDT table
+ }
+ break;
+
+ default:
+ break;
+ }
+ return EFI_SUCCESS;
+}
+
+/**
+ This function calculates RCR based on PCI Device ID and Vendor ID from the devices
+ available on the platform.
+ It also includes other instances of BIOS change to calculate CRC and provides as
+ HWSignature filed in FADT table.
+**/
+VOID
+IsHardwareChange (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+ UINTN Index;
+ UINTN HandleCount;
+ EFI_HANDLE *HandleBuffer;
+ EFI_PCI_IO_PROTOCOL *PciIo;
+ UINT32 CRC;
+ UINT32 *HWChange;
+ UINTN HWChangeSize;
+ UINT32 PciId;
+ UINTN Handle;
+ EFI_ACPI_2_0_FIRMWARE_ACPI_CONTROL_STRUCTURE *FacsPtr;
+ EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE *pFADT;
+
+ HandleCount = 0;
+ HandleBuffer = NULL;
+
+ Status = gBS->LocateHandleBuffer (
+ ByProtocol,
+ &gEfiPciIoProtocolGuid,
+ NULL,
+ &HandleCount,
+ &HandleBuffer
+ );
+ if (EFI_ERROR (Status)) {
+ return; // PciIO protocol not installed yet!
+ }
+
+ if (HandleCount > 0x1FFF) { // PCI config space max limit
+ return;
+ }
+
+ //
+ // Allocate memory for HWChange and add additional entrie for
+ // pFADT->XDsdt
+ //
+ HWChangeSize = HandleCount + 1;
+ HWChange = AllocateZeroPool( sizeof(UINT32) * HWChangeSize );
+ ASSERT( HWChange != NULL );
+
+ if (HWChange == NULL) return;
+
+ //
+ // add HWChange inputs: PCI devices
+ //
+ for (Index = 0; HandleCount > 0; HandleCount--) {
+ PciId = 0;
+ Status = gBS->HandleProtocol (HandleBuffer[Index], &gEfiPciIoProtocolGuid, (VOID **) &PciIo);
+ if (!EFI_ERROR (Status)) {
+ Status = PciIo->Pci.Read (PciIo, EfiPciIoWidthUint32, 0, 1, &PciId);
+ if (EFI_ERROR (Status)) {
+ continue;
+ }
+ HWChange[Index++] = PciId;
+ }
+ }
+
+ //
+ // Locate FACP Table
+ //
+ Handle = 0;
+ Status = LocateAcpiTableBySignature (
+ EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE,
+ (EFI_ACPI_DESCRIPTION_HEADER **) &pFADT,
+ &Handle
+ );
+ if (EFI_ERROR (Status) || (pFADT == NULL)) {
+ return; //Table not found or out of memory resource for pFADT table
+ }
+
+ //
+ // add HWChange inputs: others
+ //
+ HWChange[Index++] = (UINT32)pFADT->XDsdt;
+
+ //
+ // Calculate CRC value with HWChange data.
+ //
+ Status = gBS->CalculateCrc32(HWChange, sizeof(UINT32) * HWChangeSize, &CRC);
+ DEBUG((DEBUG_INFO,"CRC = %x and Status = %r\n", CRC, Status));
+
+ //
+ // Set HardwareSignature value based on CRC value.
+ //
+ FacsPtr = (EFI_ACPI_2_0_FIRMWARE_ACPI_CONTROL_STRUCTURE *)(UINTN)pFADT->FirmwareCtrl;
+ FacsPtr->HardwareSignature = CRC;
+ FreePool( HWChange );
+}
+
+EFI_STATUS
+PublishAcpiTablesFromFv (
+ IN EFI_GUID gEfiAcpiMultiTableStorageGuid
+ )
+{
+ EFI_STATUS Status;
+ EFI_FIRMWARE_VOLUME2_PROTOCOL *FwVol;
+ EFI_ACPI_COMMON_HEADER *CurrentTable;
+ UINT32 FvStatus;
+ UINTN Size;
+ EFI_ACPI_TABLE_VERSION Version;
+ UINTN TableHandle;
+ INTN Instance;
+ EFI_ACPI_TABLE_PROTOCOL *AcpiTable;
+
+ Instance = 0;
+ TableHandle = 0;
+ CurrentTable = NULL;
+ FwVol = NULL;
+
+ //
+ // Find the AcpiSupport protocol
+ //
+ Status = LocateSupportProtocol (
+ &gEfiAcpiTableProtocolGuid,
+ gEfiAcpiMultiTableStorageGuid,
+ (VOID **) &AcpiTable,
+ FALSE
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Locate the firmware volume protocol
+ //
+ Status = LocateSupportProtocol (
+ &gEfiFirmwareVolume2ProtocolGuid,
+ gEfiAcpiMultiTableStorageGuid,
+ (VOID **) &FwVol,
+ TRUE
+ );
+
+ /* TODO: Hang at native mode. Need to find the cause
+ * when the related drivers are finished for native support. */
+ //ASSERT_EFI_ERROR (Status);
+
+ //
+ // Read tables from the storage file.
+ //
+ while (Status == EFI_SUCCESS) {
+ Status = FwVol->ReadSection (
+ FwVol,
+ &gEfiAcpiMultiTableStorageGuid,
+ EFI_SECTION_RAW,
+ Instance,
+ (VOID **) &CurrentTable,
+ &Size,
+ &FvStatus
+ );
+
+ if (!EFI_ERROR (Status)) {
+
+ //
+ // Perform any table specific updates.
+ //
+ PlatformUpdateTables (CurrentTable, &Version);
+
+ //
+ // Add the table
+ //
+ TableHandle = 0;
+
+ if (Version != EFI_ACPI_TABLE_VERSION_NONE) {
+ DEBUG((DEBUG_INFO, "[Advanced ACPI] Installing table: %x : %x\n", CurrentTable->Signature, CurrentTable));
+ Status = AcpiTable->InstallAcpiTable (
+ AcpiTable,
+ CurrentTable,
+ CurrentTable->Length,
+ &TableHandle
+ );
+ }
+
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Increment the instance
+ //
+ Instance++;
+ gBS->FreePool (CurrentTable);
+ CurrentTable = NULL;
+ }
+
+ if (CurrentTable != NULL) {
+ gBS->FreePool (CurrentTable);
+ CurrentTable = NULL;
+ }
+ }
+
+ //
+ // Finished
+ //
+ return EFI_SUCCESS;
+}
+
+
+/**
+ Allocate MemoryType below 4G memory address.
+
+ @param[in] Size - Size of memory to allocate.
+ @param[in] Buffer - Allocated address for output.
+
+ @retval EFI_SUCCESS - Memory successfully allocated.
+ @retval Other - Other errors occur.
+
+**/
+EFI_STATUS
+AllocateMemoryBelow4G (
+ IN EFI_MEMORY_TYPE MemoryType,
+ IN UINTN Size,
+ OUT VOID **Buffer
+ )
+{
+ UINTN Pages;
+ EFI_PHYSICAL_ADDRESS Address;
+ EFI_STATUS Status;
+
+ Pages = EFI_SIZE_TO_PAGES (Size);
+ Address = 0xffffffff;
+
+ Status = (gBS->AllocatePages) (
+ AllocateMaxAddress,
+ MemoryType,
+ Pages,
+ &Address
+ );
+
+ *Buffer = (VOID *) (UINTN) Address;
+
+ return Status;
+}
+
+
+VOID
+EFIAPI
+AcpiEndOfDxeEvent (
+ EFI_EVENT Event,
+ VOID *ParentImageHandle
+ )
+{
+
+ if (Event != NULL) {
+ gBS->CloseEvent(Event);
+ }
+
+
+ //
+ // Install xHCI SSDT ACPI Table
+ //
+ InstallXhciAcpiTable ();
+
+ //
+ // Install Soc Gpe SSDT ACPI Table
+ //
+ InstallSocAcpiTable (&gSocGpeSsdtAcpiTableStorageGuid, SIGNATURE_64 ('S', 'o', 'c', 'G', 'p', 'e', ' ', 0));
+
+ //
+ // Install Soc Common SSDT ACPI Table
+ //
+ InstallSocAcpiTable (&gSocCmnSsdtAcpiTableStorageGuid, SIGNATURE_64 ('S', 'o', 'c', 'C', 'm', 'n', ' ', 0));
+
+ //
+ // Calculate Hardware Signature value based on current platform configurations
+ //
+ IsHardwareChange();
+
+}
+
+/**
+ Convert string containing GUID in the canonical form:
+ "aabbccdd-eeff-gghh-iijj-kkllmmnnoopp"
+ where aa - pp are unicode hexadecimal digits
+ to the buffer format to be used in ACPI, byte ordering:
+ [Byte 0] gg, hh, ee, ff, aa, bb, cc, dd [Byte 7]
+ [Byte 8] pp, oo, nn, mm, ll, kk, jj, ii [Byte 16]
+
+ @param[in] GuidString - GUID String null terminated (aligned on a 16-bit boundary)
+ @param[out] AcpiGuidPart1 - First half of buffer (bytes 0 - 7)
+ @param[out] AcpiGuidPart2 - Second half of buffer (bytes 8 - 16)
+
+ @retval EFI_SUCCESS - String converted successfully.
+ @retval EFI_UNSUPPORTED - Wrong input string format.
+
+**/
+EFI_STATUS
+GuidStringToAcpiBuffer (
+ IN CHAR16 *GuidString,
+ OUT UINT64 *AcpiGuidPart1,
+ OUT UINT64 *AcpiGuidPart2
+ )
+{
+ UINT32 GuidTempPart32 = 0;
+ UINT16 GuidTempPart16 = 0;
+ UINT8 GuidPartIndex;
+
+ DEBUG((DEBUG_INFO,"GuidStringToAcpiBuffer() - GUID = %s\n", GuidString));
+
+ for (GuidPartIndex = 0; GuidPartIndex < 4; GuidPartIndex++) {
+ switch (GuidPartIndex){
+ case 0:
+ GuidTempPart32 = SwapBytes32((UINT32)StrHexToUint64(GuidString));
+ *AcpiGuidPart1 = ((UINT64)GuidTempPart32 << 0x20);
+ break;
+ case 1:
+ GuidTempPart16 = SwapBytes16((UINT16)StrHexToUint64(GuidString));
+ *AcpiGuidPart1 += ((UINT64)GuidTempPart16 << 0x10);
+ break;
+ case 2:
+ GuidTempPart16 = SwapBytes16((UINT16)StrHexToUint64(GuidString));
+ *AcpiGuidPart1 += ((UINT64)GuidTempPart16);
+ break;
+ case 3:
+ GuidTempPart16 = (UINT16)StrHexToUint64(GuidString);
+ break;
+ default:
+ return EFI_UNSUPPORTED;
+ }
+
+ while ((*GuidString != L'-') && (*GuidString != L'\0')) {
+ GuidString++;
+ }
+
+ if (*GuidString == L'-') {
+ GuidString++;
+ } else {
+ return EFI_UNSUPPORTED;
+ }
+ }
+
+ *AcpiGuidPart2 = ((UINT64)GuidTempPart16 << 0x30) + StrHexToUint64(GuidString);
+
+ // Switch endianess because it will be swapped again in ACPI Buffer object
+ *AcpiGuidPart1 = SwapBytes64(*AcpiGuidPart1);
+ *AcpiGuidPart2 = SwapBytes64(*AcpiGuidPart2);
+
+ return EFI_SUCCESS;
+}
+
+
+/**
+ ACPI Platform driver installation function.
+
+ @param[in] ImageHandle Handle for this drivers loaded image protocol.
+ @param[in] SystemTable EFI system table.
+
+ @retval EFI_SUCCESS The driver installed without error.
+ @retval EFI_ABORTED The driver encountered an error and could not complete installation of
+ the ACPI tables.
+
+**/
+EFI_STATUS
+EFIAPI
+InstallAcpiPlatform (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUS Status;
+ EFI_HANDLE Handle;
+ CPUID_VERSION_INFO_EAX CpuidVersionInfoEax;
+ EFI_MP_SERVICES_PROTOCOL *MpService;
+ EFI_EVENT EndOfDxeEvent;
+
+
+
+ Handle = NULL;
+ mCpuApicIdOrderTable = NULL;
+ mCpuApicIdReorderTable = NULL;
+
+ AsmCpuid (
+ CPUID_VERSION_INFO,
+ &CpuidVersionInfoEax.Uint32,
+ NULL,
+ NULL,
+ NULL
+ );
+
+ //
+ // Locate the MP services protocol
+ // Find the MP Protocol. This is an MP platform, so MP protocol must be there.
+ //
+ Status = gBS->LocateProtocol (
+ &gEfiMpServiceProtocolGuid,
+ NULL,
+ (VOID **) &MpService
+ );
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ //
+ // Determine the number of processors
+ //
+ MpService->GetNumberOfProcessors (
+ MpService,
+ &mNumberOfCpus,
+ &mNumberOfEnabledCpus
+ );
+
+ DEBUG ((DEBUG_INFO, "mNumberOfCpus - %x,mNumberOfEnabledCpus - %x\n", mNumberOfCpus, mNumberOfEnabledCpus));
+ mCpuApicIdOrderTable = AllocateZeroPool (mNumberOfCpus * sizeof (EFI_CPU_ID_ORDER_MAP));
+ if (mCpuApicIdOrderTable == NULL) {
+ return EFI_UNSUPPORTED;
+ }
+ mCpuApicIdReorderTable = AllocateZeroPool (mNumberOfCpus * sizeof (EFI_CPU_APIC_ID_REORDER_MAP));
+ if (mCpuApicIdReorderTable == NULL) {
+ return EFI_UNSUPPORTED;
+ }
+
+ //
+ // Allocate and initialize the NVS area for SMM and ASL communication.
+ //
+ AcpiGnvsInit((VOID **) &mPlatformNvsAreaProtocol.Area);
+
+ //
+ // Create an End of DXE event.
+ //
+ Status = gBS->CreateEventEx (
+ EVT_NOTIFY_SIGNAL,
+ TPL_CALLBACK,
+ AcpiEndOfDxeEvent,
+ NULL,
+ &gEfiEndOfDxeEventGroupGuid,
+ &EndOfDxeEvent
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ Status = gBS->InstallMultipleProtocolInterfaces (
+ &Handle,
+ &gPlatformNvsAreaProtocolGuid,
+ &mPlatformNvsAreaProtocol,
+ NULL
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Allocate NVS area for VBIOS. This is not currently used.
+ //
+ Status = AllocateMemoryBelow4G (
+ EfiACPIMemoryNVS,
+ 0x10000,
+ &mGfxNvsAddress
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Generate ACPI tables from configuration data
+ //
+ Status = GenerateSsdtFromConfigFile();
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Platform ACPI Tables
+ //
+ PublishAcpiTablesFromFv(gAcpiTableStorageGuid);
+
+ //
+ // Reference Code ACPI Tables
+ //
+ PublishAcpiTablesFromFv(gRcAcpiTableStorageGuid);
+
+
+ //
+ // Finished
+ //
+ return EFI_SUCCESS;
+}
+
+/**
+ Sort ordering of CPUs according to the priorities of cores and threads.
+ ** ASSUMPTION: 1) single CPU package systsem wide; 2) two threads per core
+
+ @param[in] MpService The MP servicde protocol (used to retrievel MP info)
+
+ @retval EFI_SUCCESS The driver installed without error.
+
+**/
+EFI_STATUS
+SortCpuLocalApicInTable (
+ IN EFI_MP_SERVICES_PROTOCOL *MpService
+ )
+{
+ EFI_PROCESSOR_INFORMATION *MpContext;
+ UINT8 Index;
+ UINTN BspIndex;
+ UINT8 CurrProcessor;
+ EFI_STATUS Status;
+ UINT8 MaxCpuCore;
+ UINT8 MaxCpuThread;
+
+ MpContext = NULL;
+ MaxCpuCore = 0;
+ MaxCpuThread = 0;
+
+ Status = MpService->WhoAmI (
+ MpService,
+ &BspIndex
+ );
+
+ //
+ // Fill mCpuApicIdOrderTable
+ //
+ for (CurrProcessor = 0; CurrProcessor < mNumberOfCpus; CurrProcessor++) {
+
+ MpContext = AllocatePool (sizeof(EFI_PROCESSOR_INFORMATION));
+ ASSERT (MpContext != NULL);
+ Status = MpService->GetProcessorInfo (
+ MpService,
+ CurrProcessor,
+ MpContext
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ if (MpContext == NULL) {
+ return Status;
+ }
+ mCpuApicIdOrderTable[CurrProcessor].ApicId = (UINT32) MpContext->ProcessorId;
+ DEBUG((DEBUG_INFO, "The CurrProcessor 0x%x ApicId is 0x%x\n", CurrProcessor, mCpuApicIdOrderTable[CurrProcessor].ApicId));
+ mCpuApicIdOrderTable[CurrProcessor].Flags = (MpContext->StatusFlag & PROCESSOR_ENABLED_BIT)? 1: 0;
+ mCpuApicIdOrderTable[CurrProcessor].Package = (UINT8) MpContext->Location.Package;
+ mCpuApicIdOrderTable[CurrProcessor].Die = (UINT8) 0;
+ mCpuApicIdOrderTable[CurrProcessor].Core = (UINT8) MpContext->Location.Core;
+ mCpuApicIdOrderTable[CurrProcessor].Thread = (UINT8) MpContext->Location.Thread;
+
+ if (MaxCpuThread < (UINT8) MpContext->Location.Thread) {
+ MaxCpuThread = (UINT8) MpContext->Location.Thread;
+ }
+
+ if (MaxCpuCore < (UINT8) MpContext->Location.Core) {
+ MaxCpuCore = (UINT8) MpContext->Location.Core;
+ }
+ }
+
+ //
+ // Do some statistics about the SBSP package
+ //
+ for (CurrProcessor = 0; CurrProcessor < mNumberOfCpus; CurrProcessor++) {
+ if (CurrProcessor == BspIndex) {
+ mSbspPackageInfo.BspApicId = mCpuApicIdOrderTable[CurrProcessor].ApicId;
+ mSbspPackageInfo.PackageNo = mCpuApicIdOrderTable[CurrProcessor].Package;
+ mSbspPackageInfo.TotalThreads = 0;
+ mSbspPackageInfo.CoreNo = 0;
+ mSbspPackageInfo.LogicalThreadNo = 0;
+ }
+ }
+
+ for (CurrProcessor = 0; CurrProcessor < mNumberOfCpus; CurrProcessor++) {
+ if (mCpuApicIdOrderTable[CurrProcessor].Package == mSbspPackageInfo.PackageNo) {
+ mSbspPackageInfo.TotalThreads++;
+ if (mCpuApicIdOrderTable[CurrProcessor].Thread == 0) {
+ mSbspPackageInfo.CoreNo++;
+ } else {
+ mSbspPackageInfo.LogicalThreadNo++;
+ }
+ }
+ }
+
+ //
+ // Output debug info
+ //
+ for (Index = 0; Index < mNumberOfCpus; Index++) {
+ DEBUG((DEBUG_INFO, "Package = %x, Die = %x, Core = %x, Thread = %x, ApicId = %x\n", \
+ mCpuApicIdOrderTable[Index].Package, \
+ mCpuApicIdOrderTable[Index].Die, \
+ mCpuApicIdOrderTable[Index].Core, \
+ mCpuApicIdOrderTable[Index].Thread, \
+ mCpuApicIdOrderTable[Index].ApicId));
+ }
+
+ DEBUG((DEBUG_INFO, "MaxCpuCore = %x\n", MaxCpuCore));
+ DEBUG((DEBUG_INFO, "MaxCpuThread = %x\n\n", MaxCpuThread));
+ DEBUG((DEBUG_INFO, "mSbspPackageInfo.BspApicId = %x\n", mSbspPackageInfo.BspApicId));
+ DEBUG((DEBUG_INFO, "mSbspPackageInfo.TotalThreads = %x\n", mSbspPackageInfo.TotalThreads));
+ DEBUG((DEBUG_INFO, "mSbspPackageInfo.PackageNo = %x\n", mSbspPackageInfo.PackageNo));
+ DEBUG((DEBUG_INFO, "mSbspPackageInfo.CoreNo = %x\n", mSbspPackageInfo.CoreNo));
+ DEBUG((DEBUG_INFO, "mSbspPackageInfo.LogicalThreadNo = %x\n", mSbspPackageInfo.LogicalThreadNo));
+
+ //
+ // First entry is always SBSP
+ //
+ CurrProcessor = 0;
+ mCpuApicIdReorderTable[CurrProcessor].ApicId = mSbspPackageInfo.BspApicId;
+ mCpuApicIdReorderTable[CurrProcessor].Package = mSbspPackageInfo.PackageNo;
+ mCpuApicIdReorderTable[CurrProcessor].Flags = 1;
+ CurrProcessor++;
+
+ //
+ // Output debug info
+ //
+ for (Index = 0; Index < mNumberOfCpus; Index++) {
+ DEBUG((DEBUG_INFO, "Index = %x, ApicId = %x, Package = %x\n", \
+ Index, \
+ mCpuApicIdOrderTable[Index].ApicId, \
+ mCpuApicIdOrderTable[Index].Package));
+ }
+
+ FreePool (MpContext);
+
+ return EFI_SUCCESS;
+}
+
+
+EFI_STATUS
+AppendCpuMapTableEntry (
+ IN EFI_ACPI_1_0_PROCESSOR_LOCAL_APIC_STRUCTURE *AcpiLocalApic,
+ IN UINT32 LocalApicCounter
+ )
+{
+ EFI_STATUS Status = EFI_SUCCESS;
+ EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC_STRUCTURE *LocalX2ApicPtr;
+
+ if (AcpiLocalApic->Type == EFI_ACPI_1_0_PROCESSOR_LOCAL_APIC) {
+ if (LocalApicCounter < mNumberOfCpus) {
+ AcpiLocalApic->Flags = (UINT8)mCpuApicIdOrderTable[LocalApicCounter].Flags;
+ AcpiLocalApic->ApicId = (UINT8)mCpuApicIdOrderTable[LocalApicCounter].ApicId;
+ //
+ // Make AcpiProcessorIds 0-based
+ //
+ AcpiLocalApic->AcpiProcessorId = (UINT8)LocalApicCounter;
+ } else {
+ AcpiLocalApic->Flags = 0;
+ AcpiLocalApic->ApicId = 0xFF;
+ //
+ // Make AcpiProcessorIds 0-based
+ //
+ AcpiLocalApic->AcpiProcessorId = (UINT8)LocalApicCounter;
+ Status = EFI_UNSUPPORTED;
+ }
+
+ //
+ // Display the results
+ //
+ DEBUG((DEBUG_INFO, "AcpiLocalApic: AcpiProcessorId=%x, ApicId=%x, Flags=%x\n", \
+ AcpiLocalApic->AcpiProcessorId, \
+ AcpiLocalApic->ApicId, \
+ AcpiLocalApic->Flags));
+ } else if (AcpiLocalApic->Type == EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC) {
+ LocalX2ApicPtr = (EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC_STRUCTURE *)AcpiLocalApic;
+ if (LocalApicCounter < mNumberOfCpus) {
+ LocalX2ApicPtr->Flags = (UINT8)mCpuApicIdOrderTable[LocalApicCounter].Flags;
+ LocalX2ApicPtr->X2ApicId = mCpuApicIdOrderTable[LocalApicCounter].ApicId;
+ LocalX2ApicPtr->AcpiProcessorUid = LocalApicCounter;
+ } else {
+ LocalX2ApicPtr->Flags = 0;
+ LocalX2ApicPtr->X2ApicId = (UINT32)-1;
+ LocalX2ApicPtr->AcpiProcessorUid = LocalApicCounter;
+ Status = EFI_UNSUPPORTED;
+ }
+ //
+ // Display the results
+ //
+ DEBUG((DEBUG_INFO, "AcpiLocalx2Apic: AcpiProcessorId=%x, ApicId=%x, Flags=%x\n", \
+ LocalX2ApicPtr->AcpiProcessorUid, \
+ LocalX2ApicPtr->X2ApicId, \
+ LocalX2ApicPtr->Flags));
+ } else {
+ Status = EFI_UNSUPPORTED;
+ }
+ return Status;
+}
+
+/**
+ I/O work flow to wait input buffer empty in given time.
+
+ @param[in] Timeout Wating time.
+
+ @retval EFI_TIMEOUT if input is still not empty in given time.
+ @retval EFI_SUCCESS input is empty.
+**/
+EFI_STATUS
+WaitInputEmpty (
+ IN UINTN Timeout
+ )
+{
+ UINTN Delay;
+ UINT8 Data;
+
+ Delay = Timeout / 50;
+
+ do {
+ Data = IoRead8 (KBC_CMD_STS_PORT);
+
+ //
+ // Check keyboard controller status bit 0 and 1 (Output Buffer and Input Buffer status)
+ //
+ if ((Data & KBC_OUTB) != 0) {
+ IoRead8 (KBC_DATA_PORT);
+ } else if ((Data & KBC_INPB) == 0) {
+ break;
+ }
+
+ gBS->Stall (50);
+ Delay--;
+ } while (Delay != 0);
+
+ if (Delay == 0) {
+ return EFI_TIMEOUT;
+ }
+
+ return EFI_SUCCESS;
+}
+
+/**
+ I/O work flow to wait output buffer full in given time.
+
+ @param[in] Timeout given time
+
+ @retval EFI_TIMEOUT output is not full in given time
+ @retval EFI_SUCCESS output is full in given time.
+**/
+EFI_STATUS
+WaitOutputFull (
+ IN UINTN Timeout
+ )
+{
+ UINTN Delay;
+ UINT8 Data;
+
+ Delay = Timeout / 50;
+
+ do {
+ Data = IoRead8 (KBC_CMD_STS_PORT);
+
+ //
+ // Check keyboard controller status bit 0(output buffer status)
+ // & bit5(output buffer for auxiliary device)
+ //
+ if ((Data & (KBC_OUTB | KBC_AUXB)) == (KBC_OUTB | KBC_AUXB)) {
+ break;
+ }
+
+ gBS->Stall (50);
+ Delay--;
+ } while (Delay != 0);
+
+ if (Delay == 0) {
+ return EFI_TIMEOUT;
+ }
+
+ return EFI_SUCCESS;
+}
+
+/**
+ I/O work flow of in 8042 Aux data.
+
+ @param Data Buffer holding return value.
+
+ @retval EFI_SUCCESS Success to excute I/O work flow
+ @retval EFI_TIMEOUT Keyboard controller time out.
+**/
+EFI_STATUS
+In8042AuxData (
+ IN OUT UINT8 *Data
+ )
+{
+ EFI_STATUS Status;
+
+ //
+ // wait for output data
+ //
+ Status = WaitOutputFull (BAT_TIMEOUT);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ *Data = IoRead8 (KBC_DATA_PORT);
+
+ return EFI_SUCCESS;
+}
+
+/**
+ I/O work flow of outing 8042 Aux command.
+
+ @param Command Aux I/O command
+
+ @retval EFI_SUCCESS Success to excute I/O work flow
+ @retval EFI_TIMEOUT Keyboard controller time out.
+**/
+EFI_STATUS
+Out8042AuxCommand (
+ IN UINT8 Command
+ )
+{
+ EFI_STATUS Status;
+ UINT8 Data;
+
+ //
+ // Wait keyboard controller input buffer empty
+ //
+ Status = WaitInputEmpty (TIMEOUT);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+ //
+ // Send write to auxiliary device command
+ //
+ Data = WRITE_AUX_DEV;
+ IoWrite8 (KBC_CMD_STS_PORT, Data);
+
+ Status = WaitInputEmpty (TIMEOUT);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+ //
+ // Send auxiliary device command
+ //
+ IoWrite8 (KBC_DATA_PORT, Command);
+
+ //
+ // Read return code
+ //
+ Status = In8042AuxData (&Data);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ if (Data == PS2_ACK) {
+ //
+ // Receive mouse acknowledge, command send success
+ //
+ return EFI_SUCCESS;
+
+ } else if (Data == PS2_RESEND) {
+ //
+ // Resend command
+ //
+ Status = Out8042AuxCommand (Command);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ } else {
+ //
+ // Invalid return code
+ //
+ return EFI_DEVICE_ERROR;
+
+ }
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Issue command to enable Ps2 mouse.
+
+ @return Status of command issuing.
+**/
+EFI_STATUS
+PS2MouseEnable (
+ VOID
+ )
+{
+ //
+ // Send auxiliary command to enable mouse
+ //
+ return Out8042AuxCommand (ENABLE_CMD);
+}
+
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AdvancedAcpiDxe/AcpiPlatform.h b/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AdvancedAcpiDxe/AcpiPlatform.h
new file mode 100644
index 0000000000..11b21cd675
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AdvancedAcpiDxe/AcpiPlatform.h
@@ -0,0 +1,142 @@
+/** @file
+ This is an implementation of the Advanced ACPI driver.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _ACPI_PLATFORM_H_
+#define _ACPI_PLATFORM_H_
+
+//
+// Statements that include other header files
+//
+
+#include <IndustryStandard/Acpi.h>
+#include <Guid/EventGroup.h>
+#include <Guid/GlobalVariable.h>
+#include <Library/UefiLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/UefiRuntimeServicesTableLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/IoLib.h>
+#include <Library/PcdLib.h>
+#include <Library/LocalApicLib.h>
+#include <Protocol/CpuIo2.h>
+#include <Protocol/AcpiTable.h>
+#include <Protocol/PciRootBridgeIo.h>
+#include <Protocol/MpService.h>
+#include <Register/Cpuid.h>
+#include <Protocol/PciIo.h>
+#include <Library/PchCycleDecodingLib.h>
+
+#include <IndustryStandard/HighPrecisionEventTimerTable.h>
+#include <Library/DxeAcpiGnvsInitLib.h>
+
+#include <Register/PchRegs.h>
+
+//
+// Produced protocols
+//
+#include <Protocol/PlatformNvsArea.h>
+
+#include <Platform.h>
+#include <Library/AslUpdateLib.h>
+
+#include <Acpi/AcpiTables/Fadt/Fadt6.3.h>
+
+//
+// ACPI table information used to initialize tables.
+//
+
+#define NAT_CONFIG_INDEX 0x2E
+#define NAT_CONFIG_DATA 0x2F
+#define WPCN381U_CONFIG_INDEX 0x2E
+#define WPCN381U_CONFIG_DATA 0x2F
+#define WPCN381U_CHIP_ID 0xF4
+#define WDCP376_CHIP_ID 0xF1
+
+#define KBC_DATA_PORT 0x60
+#define KBC_CMD_STS_PORT 0x64
+
+#define ENABLE_CMD 0xf4
+#define WRITE_AUX_DEV 0xd4
+
+#define PS2_ACK 0xfa
+#define PS2_RESEND 0xfe
+
+#define KBC_INPB 0x02
+#define KBC_OUTB 0x01
+#define KBC_AUXB 0x20
+
+#define TIMEOUT 50000
+#define BAT_TIMEOUT 5000
+
+#define IO_EXPANDER_DISABLED 0xFF
+
+typedef struct {
+ UINT32 ApicId;
+ UINT32 Flags;
+ UINT8 Package;
+ UINT8 Die;
+ UINT8 Core;
+ UINT8 Thread;
+} EFI_CPU_ID_ORDER_MAP;
+
+typedef struct {
+ UINT8 Package;
+ UINT32 ApicId;
+ UINT32 Flags;
+} EFI_CPU_APIC_ID_REORDER_MAP;
+
+typedef struct {
+ UINT32 BspApicId;
+ UINT8 TotalThreads;
+ UINT8 PackageNo;
+ UINT8 CoreNo;
+ UINT8 LogicalThreadNo;
+} EFI_CPU_PACKAGE_INFO;
+
+//
+// Function definitions
+//
+EFI_STATUS
+LocateSupportProtocol (
+ IN EFI_GUID *Protocol,
+ IN EFI_GUID gEfiAcpiMultiTableStorageGuid,
+ OUT VOID **Instance,
+ IN BOOLEAN Type
+ );
+
+/**
+ Entry point of the ACPI platform driver.
+
+ @param[in] ImageHandle A handle for the image that is initializing this driver
+ @param[in] SystemTable A pointer to the EFI system table
+
+ @retval EFI_SUCCESS The driver installed without error.
+ @retval EFI_ABORTED The driver encountered an error and could not complete
+ installation of the ACPI tables.
+**/
+EFI_STATUS
+EFIAPI
+InstallAcpiPlatform (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ );
+
+EFI_STATUS
+SortCpuLocalApicInTable (
+ IN EFI_MP_SERVICES_PROTOCOL *MpService
+ );
+
+EFI_STATUS
+AppendCpuMapTableEntry (
+ IN EFI_ACPI_1_0_PROCESSOR_LOCAL_APIC_STRUCTURE *AcpiLocalApic,
+ IN UINT32 LocalApicCounter
+ );
+
+#endif
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AdvancedAcpiDxe/AdvancedAcpiDxe.inf b/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AdvancedAcpiDxe/AdvancedAcpiDxe.inf
new file mode 100644
index 0000000000..0e38852fbf
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AdvancedAcpiDxe/AdvancedAcpiDxe.inf
@@ -0,0 +1,154 @@
+### @file
+# Component information file for AdvancedAcpiDxe module
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+# @par Glossary:
+###
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = AdvancedAcpiDxe
+ FILE_GUID = C3E69EB2-0429-4BD6-AE4A-8CA02FBACC2E
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+ ENTRY_POINT = InstallAcpiPlatform
+
+[Sources.common]
+ AcpiPlatform.h
+ AcpiPlatform.c
+ GenSsdtLib.c
+ GenSsdtLib.h
+ AcpiByteStream.h
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ UefiCpuPkg/UefiCpuPkg.dec
+ AlderlakeSiliconPkg/SiPkg.dec
+ AlderlakeOpenBoardPkg/OpenBoardPkg.dec
+ IntelSiliconPkg/IntelSiliconPkg.dec
+
+[LibraryClasses]
+ UefiDriverEntryPoint
+ BaseLib
+ DebugLib
+ IoLib
+ PcdLib
+ AslUpdateLib
+ DxeAcpiGnvsInitLib
+ UefiBootServicesTableLib
+ UefiRuntimeServicesTableLib
+ BaseMemoryLib
+ MemoryAllocationLib
+ PchCycleDecodingLib
+ PchInfoLib
+ PchPcieRpLib
+ PciSegmentLib
+ HobLib
+ GpioLib
+ EspiLib
+ CpuPlatformLib
+ GraphicsInfoLib
+ PchPciBdfLib
+ LocalApicLib
+
+[Pcd]
+ gSiPkgTokenSpaceGuid.PcdPciExpressRegionLength ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdRealBattery1Control ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdRealBattery2Control ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdNCT6776FCOM ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdNCT6776FSIO ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdNCT6776FHWMON ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdH8S2113SIO ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdH8S2113UAR ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdSmcRuntimeSciPin ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdVirtualButtonVolumeUpSupport ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdVirtualButtonVolumeDownSupport ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdVirtualButtonHomeButtonSupport ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdVirtualButtonRotationLockSupport ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdSlateModeSwitchSupport ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdPmPowerButtonGpioPin ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdAcpiEnableAllButtonSupport ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdAcpiHidDriverButtonSupport ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdTsOnDimmTemperature ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdBatteryPresent ## CONSUMES
+ gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemTableId ## CONSUMES
+ gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemRevision
+ gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorId
+ gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorRevision
+ gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemId
+
+ # DXE PCD
+ gBoardModuleTokenSpaceGuid.PcdXhciAcpiTableSignature ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdPreferredPmProfile ## CONSUMES
+
+ gBoardModuleTokenSpaceGuid.PcdBoardRtd3TableSignature ## CONSUMES
+
+ gBoardModuleTokenSpaceGuid.PcdEnableVoltageMargining ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdPlatformGeneration ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdBoardId ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdBoardRev ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdBoardType ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdPlatformType ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdPlatformFlavor ## CONSUMES
+
+ gBoardModuleTokenSpaceGuid.PcdBoardUcmcGpio1 ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdBoardUcmcGpio2 ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdBoardUcmcGpio3 ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdBoardUcmcGpio4 ## CONSUMES
+
+ # Onboard MR 1 GPIO configuration PCDs
+ gBoardModuleTokenSpaceGuid.PcdOnBoardMr1PowerEnableGpioNo ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdOnBoardMr1PowerEnableGpioPolarity ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdOnBoardMr1WakeGpioPin ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdOnBoardMr1RootPort ## CONSUMES
+
+ # Onboard MR 2 GPIO configuration PCDs
+ gBoardModuleTokenSpaceGuid.PcdOnBoardMr2PowerEnableGpioNo ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdOnBoardMr2PowerEnableGpioPolarity ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdOnBoardMr2WakeGpioPin ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdOnBoardMr2RootPort ## CONSUMES
+
+ # PCH SATA port GPIO configuration PCDs
+ gBoardModuleTokenSpaceGuid.PcdPchSataPortPwrEnableGpioNo ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdPchSataPortPwrEnableGpioPolarity ## CONSUMES
+
+ # ACPI configuration file data
+ gBoardModuleTokenSpaceGuid.PcdBoardAcpiData ## CONSUMES
+
+[FixedPcd]
+ gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress
+ gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress
+ gSiPkgTokenSpaceGuid.PcdAdlLpSupport ## CONSUMES
+ gSiPkgTokenSpaceGuid.PcdAdlSSupport ## CONSUMES
+
+[Protocols]
+ gEfiAcpiTableProtocolGuid ## CONSUMES
+ gEfiFirmwareVolume2ProtocolGuid ## CONSUMES
+ gEfiPciRootBridgeIoProtocolGuid ## CONSUMES
+ gEfiMpServiceProtocolGuid ## CONSUMES
+ gEfiPciIoProtocolGuid ## CONSUMES
+ gIgdOpRegionProtocolGuid ## CONSUMES
+ gPchSerialIoUartDebugInfoProtocolGuid ## CONSUMES
+ gEfiCpuIo2ProtocolGuid ## CONSUMES
+ gEfiSimpleFileSystemProtocolGuid ## CONSUMES
+ gPlatformNvsAreaProtocolGuid ## PRODUCES
+
+[Guids]
+ gAcpiTableStorageGuid ## CONSUMES
+ gRcAcpiTableStorageGuid ## CONSUMES
+ gEfiHobListGuid ## CONSUMES
+ gEfiFileInfoGuid ## CONSUMES
+ gEfiEndOfDxeEventGroupGuid ## CONSUMES
+ gSocGpeSsdtAcpiTableStorageGuid ## CONSUMES
+ gSocCmnSsdtAcpiTableStorageGuid ## CONSUMES
+
+[Depex]
+ gEfiAcpiTableProtocolGuid AND
+ gEfiFirmwareVolume2ProtocolGuid AND
+ gEfiCpuIo2ProtocolGuid AND
+ gEfiMpServiceProtocolGuid AND
+ gEfiPciRootBridgeIoProtocolGuid
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AdvancedAcpiDxe/GenSsdtLib.c b/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AdvancedAcpiDxe/GenSsdtLib.c
new file mode 100644
index 0000000000..0234d06cc3
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AdvancedAcpiDxe/GenSsdtLib.c
@@ -0,0 +1,474 @@
+/** @file
+ ACPI SSDT table generation library
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "AcpiByteStream.h"
+#include <Base.h>
+#include <Uefi.h>
+#include <Library/BaseLib.h>
+#include <Library/HobLib.h>
+#include <Guid/HobList.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <IndustryStandard/Acpi.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Protocol/AcpiTable.h>
+#include <Protocol/AcpiSystemDescriptionTable.h>
+#include <Library/MemoryAllocationLib.h>
+
+GLOBAL_REMOVE_IF_UNREFERENCED UINT8 SsdtHeader [] = {
+ 0x53,0x53,0x44,0x54,0x08,0x01,0x00,0x00, /* 00000000 "SSDT...." */
+ 0x02,0x06,0x49,0x6E,0x74,0x65,0x6C,0x20, /* 00000008 "..Intel " */
+ 0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20, /* 00000010 " " */
+ 0x01,0x00,0x00,0x00,0x49,0x4E,0x54,0x4C, /* 00000018 "....INTL" */
+ 0x27,0x05,0x16,0x20, /* 00000020 "'.. " */
+ 0xA0,0x0F,0x00 /* 00000024 "..." */
+};
+
+GLOBAL_REMOVE_IF_UNREFERENCED UINT8 SsdtExternalDualName [] = {
+ 0x15,0x5C,0x2E,0x5F,0x53,0x42,0x5F,0x50, /* 00000000 ".\._SB_P" */
+ 0x43,0x49,0x58,0x06,0x00 /* 00000008 "CIX.." */
+};
+
+GLOBAL_REMOVE_IF_UNREFERENCED UINT8 SsdtScopePkgLengthEncoding [] = {
+ 0x10, 0x00, 0x00, 0x00, 0x00 /* 00000000 "....." */
+};
+
+GLOBAL_REMOVE_IF_UNREFERENCED UINT8 SsdtScopeDualName [] = {
+ 0x5C,0x2E,0x5F,0x53,0x42, /* 00000000 "\._SB" */
+ 0x5F,0x50,0x43,0x49,0x58 /* 00000008 "_PCIX" */
+};
+
+GLOBAL_REMOVE_IF_UNREFERENCED UINT8 SsdtDevicePkgLengthEncoding [] = {
+ 0x5B,0x82,0x00,0x00,0x00,0x00 /* 00000000 "......" */
+};
+
+GLOBAL_REMOVE_IF_UNREFERENCED UINT8 SsdtDeviceName [] = {
+ 0x54,0x4D,0x50,0x31 /* 00000000 "TMP1" */
+};
+
+GLOBAL_REMOVE_IF_UNREFERENCED UINT8 SsdtHardwareId [] = {
+ 0x08,0x5F,0x48,0x49,0x44,0x0D,0x49,0x4E, /* 00000000 "._HID.IN" */
+ 0x54,0x30,0x30,0x30,0x30,0x30,0x00 /* 00000008 "T0000." */
+};
+
+GLOBAL_REMOVE_IF_UNREFERENCED UINT8 SsdtCompatibleId [] = {
+ 0x08,0x5F,0x43,0x49,0x44,0x0D,0x49,0x4E, /* 00000000 "._CID.IN" */
+ 0x54,0x30,0x30,0x30,0x30,0x30,0x00 /* 00000008 "T0000." */
+};
+
+GLOBAL_REMOVE_IF_UNREFERENCED UINT8 SsdtUniqueId [] = {
+ 0x08,0x5F,0x55,0x49,0x44,0x00 /* 00000000 "._UID." */
+};
+
+GLOBAL_REMOVE_IF_UNREFERENCED UINT8 SsdtCurrentResourceSettings [] = {
+ 0x08,0x5F,0x43,0x52,0x53, /* 00000000 "._CRS" */
+};
+
+GLOBAL_REMOVE_IF_UNREFERENCED UINT8 SsdtBufferPkgLengthEncoding [] = {
+ 0x11,0x00,0x00
+};
+
+GLOBAL_REMOVE_IF_UNREFERENCED UINT8 SsdtCrsPkgLengthEncoding [] = {
+ 0x00,0x00, 0x00 /* 00000000 "....." */
+};
+
+GLOBAL_REMOVE_IF_UNREFERENCED UINT8 SsdtGpioResource [] = {
+ 0x8C,0x20,0x00,0x01,0x01,0x01,0x00,0x02, /* 00000000 ". ......" */
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x17,0x00, /* 00000008 "........" */
+ 0x00,0x19,0x00,0x23,0x00,0x00,0x00,0x03, /* 00000010 "...#...." */
+ 0x00,0x5C,0x5F,0x53,0x42,0x2E,0x47,0x50, /* 00000018 ".\_SB.GP" */
+ 0x49,0x30,0x00, /* 00000020 "I0." */
+};
+
+GLOBAL_REMOVE_IF_UNREFERENCED UINT8 SsdtI2cSerialBusResource [] = {
+ 0x8E,0x1E,0x00,0x01,0x00,0x01,0x02,0x00, /* 00000000 "........" */
+ 0x00,0x01,0x06,0x00,0x80,0x1A,0x06,0x00, /* 00000008 "........" */
+ 0x22,0x00,0x5C,0x5F,0x53,0x42,0x2E,0x50, /* 00000010 "".\_SB.P" */
+ 0x43,0x49,0x30,0x2E,0x49,0x32,0x43,0x58, /* 00000018 "CI0.I2CX" */
+ 0x00 /* 00000020 "." */
+};
+
+GLOBAL_REMOVE_IF_UNREFERENCED UINT8 SsdtStatusMethod [] = {
+ 0x14,0x09,0x5F,0x53,0x54,0x41,0x00, /* 00000000 ".._STA." */
+ 0xA4,0x0A,0x0F /* 00000008 "..." */
+};
+
+GLOBAL_REMOVE_IF_UNREFERENCED UINT8 SsdtResourceTemplateEndTag [] = {
+ 0x79, 0x00
+};
+
+EFI_STATUS
+GetTableSize(
+ IN UINT8 *AcpiDataBase,
+ OUT UINT32 *SsdtTableSize
+ )
+{
+ UINTN GpioResources;
+ UINTN I2cResources;
+ UINT32 ResourceBufferLength;
+ UINT32 DevicePackageLength;
+ UINT32 ScopePackageLength;
+ UINT32 ResourceSize;
+ UINTN i;
+ UINTN ResourceOffset;
+ UINT8 ResourceType;
+ UINTN NextResource;
+ EFI_ACPI_SDT_HEADER *SsdtTableInfo;
+ SSDT_DEVICE_DATA *SsdtDeviceInfo;
+ UINT32 Size;
+ UINT8 *PrintData;
+
+ //
+ // Get table info from HOB
+ //
+ SsdtTableInfo = (EFI_ACPI_SDT_HEADER *) AcpiDataBase;
+ SsdtDeviceInfo = (SSDT_DEVICE_DATA *) (AcpiDataBase + sizeof(EFI_ACPI_SDT_HEADER));
+ ResourceOffset = sizeof(EFI_ACPI_SDT_HEADER) + sizeof(SSDT_DEVICE_DATA) - sizeof(UINT8);
+ NextResource = 0;
+ GpioResources = 0;
+ I2cResources = 0;
+ ResourceSize = 0;
+
+ Size = SsdtTableInfo->Length;
+
+ DEBUG_CODE_BEGIN();
+ DEBUG((DEBUG_INFO, "GenSsdt AcpiData print:\n"));
+ for (PrintData = AcpiDataBase; PrintData<(AcpiDataBase + Size); PrintData++) {
+ DEBUG((DEBUG_INFO, "%x ", *PrintData));
+ }
+ DEBUG((DEBUG_INFO, "\n"));
+ DEBUG_CODE_END();
+
+ DEBUG((DEBUG_INFO, "NumberOfResources: %x \n", SsdtDeviceInfo->NumberOfResources));
+
+ for (i = 0; i < SsdtDeviceInfo->NumberOfResources; i++) {
+ ResourceType = *(AcpiDataBase + ResourceOffset + NextResource);
+ DEBUG((DEBUG_INFO, "ResourceType: %x ", ResourceType));
+ switch (ResourceType) {
+ case ACPI_GPIO_RESOURCE_TYPE :
+ {
+ ResourceSize = ResourceSize + sizeof(GPIO_RESOURCE_DATA);
+ NextResource = NextResource + sizeof(GPIO_RESOURCE_DATA) - sizeof(UINT8);
+ GpioResources++;
+ break;
+ }
+ case ACPI_I2C_RESOURCE_TYPE :
+ {
+ ResourceSize = ResourceSize + sizeof(I2C_RESOURCE_DATA);
+ NextResource = NextResource + sizeof(I2C_RESOURCE_DATA) - sizeof(UINT8);
+ I2cResources++;
+ break;
+ }
+ default :
+ DEBUG ((DEBUG_INFO, "Unsupported resource type.\n"));
+ break;
+ }
+ }
+ DEBUG((DEBUG_INFO, "GenSsdt GpioResources:%d I2cResources:%d\n", GpioResources, I2cResources));
+ //
+ // Calculate the size of table to be generated
+ //
+ ResourceBufferLength = (UINT32) ((GpioResources * sizeof(SsdtGpioResource)) +
+ (I2cResources * sizeof(SsdtI2cSerialBusResource)) +
+ sizeof(SsdtResourceTemplateEndTag));
+ DEBUG((DEBUG_INFO, "GenSsdt ResourceBufferLength: 0x%x\n", ResourceBufferLength));
+
+ DevicePackageLength = (UINT32) (sizeof(SsdtDeviceName) + sizeof(SsdtHardwareId) +
+ sizeof(SsdtCompatibleId) + sizeof(SsdtUniqueId) +
+ sizeof(SsdtCurrentResourceSettings) + ResourceBufferLength +
+ sizeof(SsdtStatusMethod));
+ DEBUG((DEBUG_INFO, "GenSsdt DevicePkgLength: 0x%x\n", DevicePackageLength));
+
+ if (ResourceBufferLength < 254) {
+ SsdtCrsPkgLengthEncoding[0] = ACPI_BYTE_PREFIX_OPCODE;
+ SsdtCrsPkgLengthEncoding[1] = (UINT8) ResourceBufferLength;
+ DevicePackageLength = DevicePackageLength + 2; //Adding Package length encoding size
+ DEBUG((DEBUG_INFO, "GenSsdt CrsPkgLengthEncoding1: 0x%x\n", SsdtCrsPkgLengthEncoding[1]));
+ } else if (ResourceBufferLength < 65533) {
+ SsdtCrsPkgLengthEncoding[0] = ACPI_WORD_PREFIX_OPCODE;
+ SsdtCrsPkgLengthEncoding[1] = (UINT8) (ResourceBufferLength & 0x00FF);
+ SsdtCrsPkgLengthEncoding[2] = (UINT8) ((ResourceBufferLength & 0xFF00) >> 8);
+ DevicePackageLength = DevicePackageLength + 3; //Adding Package length encoding size
+ DEBUG((DEBUG_INFO, "GenSsdt CrsPkgLengthEncoding1: 0x%x\n", SsdtCrsPkgLengthEncoding[1]));
+ DEBUG((DEBUG_INFO, "GenSsdt CrsPkgLengthEncoding2: 0x%x\n", SsdtCrsPkgLengthEncoding[2]));
+ }
+
+ if (ResourceBufferLength < 61) {
+ SsdtBufferPkgLengthEncoding[1] = (UINT8) ResourceBufferLength + 3; //Taking CrsPackageLength encoding into account
+ DevicePackageLength = DevicePackageLength + 2; //Adding Package length encoding size
+ DEBUG((DEBUG_INFO, "GenSsdt BufferPkgLengthEncoding1: 0x%x\n", SsdtBufferPkgLengthEncoding[1]));
+ } else if (ResourceBufferLength < 4095) {
+ SsdtBufferPkgLengthEncoding[1] = 0x40 | ((UINT8)((ResourceBufferLength + 5) & 0x00F)); //Taking CrsPackageLength encoding into account
+ SsdtBufferPkgLengthEncoding[2] = (UINT8) (((ResourceBufferLength + 5) & 0xFF0) >> 4); //Taking CrsPackageLength encoding into account
+ DevicePackageLength = DevicePackageLength + 3; //Adding Package length encoding size
+ DEBUG((DEBUG_INFO, "GenSsdt BufferPkgLengthEncoding1: 0x%x\n", SsdtBufferPkgLengthEncoding[1]));
+ DEBUG((DEBUG_INFO, "GenSsdt BufferPkgLengthEncoding2: 0x%x\n", SsdtBufferPkgLengthEncoding[2]));
+ }
+
+ ScopePackageLength = 0;
+ if (DevicePackageLength < 63) {
+ SsdtDevicePkgLengthEncoding[2] = (UINT8) DevicePackageLength;
+ ScopePackageLength = ScopePackageLength + 3;
+ DEBUG((DEBUG_INFO, "GenSsdt DevicePkgLengthEncoding2: 0x%x\n", SsdtDevicePkgLengthEncoding[2]));
+ } else if (DevicePackageLength < 4094) {
+ SsdtDevicePkgLengthEncoding[2] = 0x40 | ((UINT8)((DevicePackageLength + 2) & 0x00F));
+ SsdtDevicePkgLengthEncoding[3] = (UINT8) (((DevicePackageLength + 2) & 0xFF0) >> 4);
+ ScopePackageLength = ScopePackageLength + 4;
+ DEBUG((DEBUG_INFO, "GenSsdt DevicePkgLengthEncoding2: 0x%x\n", SsdtDevicePkgLengthEncoding[2]));
+ DEBUG((DEBUG_INFO, "GenSsdt DevicePkgLengthEncoding3: 0x%x\n", SsdtDevicePkgLengthEncoding[3]));
+ }
+
+ ScopePackageLength = ScopePackageLength + sizeof(SsdtScopeDualName) + DevicePackageLength;
+ if (ScopePackageLength < 63) {
+ SsdtScopePkgLengthEncoding[1] = (UINT8) ScopePackageLength;
+ DEBUG((DEBUG_INFO, "GenSsdt ScopePkgLengthEncoding1: 0x%x\n", SsdtScopePkgLengthEncoding[1]));
+ } else if (ScopePackageLength < 4094) {
+ ScopePackageLength = ScopePackageLength + 2;
+ SsdtScopePkgLengthEncoding[1] = 0x40 | ((UINT8)(ScopePackageLength & 0x00F));
+ SsdtScopePkgLengthEncoding[2] = (UINT8) ((ScopePackageLength & 0xFF0) >> 4);
+ DEBUG((DEBUG_INFO, "GenSsdt ScopePkgLengthEncoding1: 0x%x\n", SsdtScopePkgLengthEncoding[1]));
+ DEBUG((DEBUG_INFO, "GenSsdt ScopePkgLengthEncoding2: 0x%x\n", SsdtScopePkgLengthEncoding[2]));
+ }
+
+ *SsdtTableSize = (UINT32) (sizeof(SsdtHeader) + sizeof(SsdtExternalDualName) + ScopePackageLength + 1);
+
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+CreateAcpiTableInMemory (
+ IN UINT8 *AcpiDataBase,
+ IN UINT32 *SsdtTableSize,
+ OUT UINT8 *CurrentTable
+ )
+{
+ UINT8 *CurrentTablePointer;
+ EFI_ACPI_SDT_HEADER *AcpiTableHeader;
+ EFI_ACPI_SDT_HEADER *SsdtTableInfo;
+ SSDT_DEVICE_DATA *SsdtDeviceInfo;
+ GPIO_RESOURCE_DATA *GpioResourceInfo;
+ I2C_RESOURCE_DATA *I2cResourceInfo;
+ GPIO_RESOURCE *TempGpioResource;
+ I2C_SERIAL_BUS_RESOURCE *TempI2cResource;
+ UINTN i;
+ UINTN ResourceOffset;
+ UINT8 ResourceType;
+ UINTN NextResource;
+ UINT32 Size;
+
+ SsdtTableInfo = (EFI_ACPI_SDT_HEADER *) AcpiDataBase;
+ SsdtDeviceInfo = (SSDT_DEVICE_DATA *) (AcpiDataBase + sizeof(EFI_ACPI_SDT_HEADER));
+ ResourceOffset = sizeof(EFI_ACPI_SDT_HEADER) + sizeof(SSDT_DEVICE_DATA) - sizeof(UINT8);
+ //
+ // Copy SSDT content to allocated space
+ //
+ CurrentTablePointer = (UINT8 *) CurrentTable;
+ CopyMem(CurrentTablePointer, &SsdtHeader, sizeof(SsdtHeader));
+ AcpiTableHeader = (EFI_ACPI_SDT_HEADER *) CurrentTablePointer;
+ AcpiTableHeader->Length = *SsdtTableSize;
+ CopyMem(AcpiTableHeader->OemId, SsdtTableInfo->OemId, 6);
+ CopyMem(AcpiTableHeader->OemTableId, SsdtTableInfo->OemTableId, 8);
+
+ CurrentTablePointer = (UINT8 *) (CurrentTable + sizeof(SsdtHeader));
+ CopyMem(CurrentTablePointer, &SsdtExternalDualName, sizeof(SsdtExternalDualName));
+ *(CHAR8 *) (CurrentTablePointer + ACPI_EXTERNAL_PCI_BUS_NUMBER_OFFSET) = '0'; //PCI bus 0
+
+ CurrentTablePointer = (UINT8 *) (CurrentTablePointer + sizeof(SsdtExternalDualName));
+ Size = ((SsdtScopePkgLengthEncoding[1] & 0xC0) >> 6) + 2;
+ CopyMem(CurrentTablePointer, &SsdtScopePkgLengthEncoding, Size);
+
+ CurrentTablePointer = (UINT8 *) (CurrentTablePointer + Size);
+ CopyMem(CurrentTablePointer, &SsdtScopeDualName, sizeof(SsdtScopeDualName));
+ *(CHAR8 *) (CurrentTablePointer + ACPI_SCOPE_PCI_BUS_NUMBER_OFFSET) = '0'; //PCI bus 0
+
+ CurrentTablePointer = (UINT8 *) (CurrentTablePointer + sizeof(SsdtScopeDualName));
+ Size = ((SsdtDevicePkgLengthEncoding[2] & 0xC0) >> 6) + 3;
+ CopyMem(CurrentTablePointer, &SsdtDevicePkgLengthEncoding, Size);
+
+ CurrentTablePointer = (UINT8 *) (CurrentTablePointer + Size);
+ CopyMem(&SsdtDeviceName, SsdtDeviceInfo->DeviceName, 4);
+ CopyMem(CurrentTablePointer, &SsdtDeviceName, sizeof(SsdtDeviceName));
+
+ CurrentTablePointer = (UINT8 *) (CurrentTablePointer + sizeof(SsdtDeviceName));
+ CopyMem(CurrentTablePointer, &SsdtHardwareId, sizeof(SsdtHardwareId));
+ CopyMem(CurrentTablePointer + ACPI_NAME_OBJECT_STRING_OFFSET, SsdtDeviceInfo->HardwareId, 8);
+
+ CurrentTablePointer = (UINT8 *) (CurrentTablePointer + sizeof(SsdtHardwareId));
+ CopyMem(CurrentTablePointer, &SsdtCompatibleId, sizeof(SsdtCompatibleId));
+ CopyMem(CurrentTablePointer + ACPI_NAME_OBJECT_STRING_OFFSET, SsdtDeviceInfo->CompatibilityId, 8);
+
+ CurrentTablePointer = (UINT8 *) (CurrentTablePointer + sizeof(SsdtCompatibleId));
+ SsdtUniqueId[ACPI_UNIQUE_ID_NUMBER_OFFSET] = (UINT8) SsdtDeviceInfo->UniqueId;
+ CopyMem(CurrentTablePointer, &SsdtUniqueId, sizeof(SsdtUniqueId));
+
+ CurrentTablePointer = (UINT8 *) (CurrentTablePointer + sizeof(SsdtUniqueId));
+ CopyMem(CurrentTablePointer, &SsdtCurrentResourceSettings, sizeof(SsdtCurrentResourceSettings));
+
+ CurrentTablePointer = (UINT8 *) (CurrentTablePointer + sizeof(SsdtCurrentResourceSettings));
+ Size = ((SsdtBufferPkgLengthEncoding[1] & 0xC0) >> 6) + 2;
+ CopyMem(CurrentTablePointer, &SsdtBufferPkgLengthEncoding, Size);
+
+ CurrentTablePointer = (UINT8 *) (CurrentTablePointer + Size);
+ if (SsdtCrsPkgLengthEncoding[0] == ACPI_BYTE_PREFIX_OPCODE) {
+ Size = 2;
+ } else if (SsdtCrsPkgLengthEncoding[0] == ACPI_WORD_PREFIX_OPCODE) {
+ Size = 3;
+ }
+ CopyMem(CurrentTablePointer, &SsdtCrsPkgLengthEncoding, Size);
+
+ CurrentTablePointer = (UINT8 *) (CurrentTablePointer + Size);
+ NextResource = 0;
+ for (i = 0; i < SsdtDeviceInfo->NumberOfResources; i++) {
+ ResourceType = *(UINT8 *)(AcpiDataBase + ResourceOffset + NextResource);
+ switch (ResourceType) {
+ case ACPI_GPIO_RESOURCE_TYPE :
+ {
+ CopyMem(CurrentTablePointer, &SsdtGpioResource, sizeof(SsdtGpioResource));
+ TempGpioResource = (GPIO_RESOURCE *) CurrentTablePointer;
+ DEBUG((DEBUG_INFO, "TempGpioConnDesc: %x\n", TempGpioResource->GpioConnectionDescriptor));
+ DEBUG((DEBUG_INFO, "TempGpioResourceNumber1 before: %x\n", TempGpioResource->PinNumber1));
+ DEBUG((DEBUG_INFO, "TempGpioResourceNumber2 before: %x\n", TempGpioResource->PinNumber2));
+ GpioResourceInfo = (GPIO_RESOURCE_DATA *) (AcpiDataBase + ResourceOffset + NextResource);
+ if (GpioResourceInfo->GpioResourceType == ACPI_GPIO_RESOURCE_TYPE_INTERRUPT) {
+ TempGpioResource->GpioConnectionType = GpioInterrupt;
+ TempGpioResource->InterruptAndIoFlags1 |= 0x10;
+ TempGpioResource->PinNumber1 = GpioResourceInfo->GpioNumber & 0x00FF;
+ TempGpioResource->PinNumber2 = (GpioResourceInfo->GpioNumber & 0xFF00) >> 8;
+ } else if (GpioResourceInfo->GpioResourceType == ACPI_GPIO_RESOURCE_TYPE_IO) {
+ TempGpioResource->GpioConnectionType = GpioIo;
+ TempGpioResource->InterruptAndIoFlags1 &= 0x0F;
+ TempGpioResource->PinNumber1 = GpioResourceInfo->GpioNumber & 0x00FF;
+ TempGpioResource->PinNumber2 = (GpioResourceInfo->GpioNumber & 0xFF00) >> 8;
+ }
+ DEBUG((DEBUG_INFO, "TempGpioResourceNumber1 after: %x\n", TempGpioResource->PinNumber1));
+ DEBUG((DEBUG_INFO, "TempGpioResourceNumber2 after: %x\n", TempGpioResource->PinNumber2));
+ NextResource = NextResource + sizeof(GPIO_RESOURCE_DATA) - sizeof(UINT8);
+ CurrentTablePointer = CurrentTablePointer + sizeof(SsdtGpioResource);
+
+ break;
+ }
+ case ACPI_I2C_RESOURCE_TYPE :
+ {
+ CopyMem(CurrentTablePointer, &SsdtI2cSerialBusResource, sizeof(SsdtI2cSerialBusResource));
+ TempI2cResource = (I2C_SERIAL_BUS_RESOURCE *) CurrentTablePointer;
+ I2cResourceInfo = (I2C_RESOURCE_DATA *) (AcpiDataBase + ResourceOffset + NextResource);
+ TempI2cResource->SlaveAddress = (UINT16) I2cResourceInfo->I2cSlaveAddress;
+ TempI2cResource->ConnectionSpeed = I2cResourceInfo->ConnectionSpeed;
+ *(CurrentTablePointer + ACPI_I2C_RESOURCE_CONTROLLER_NUMBER_OFFSET) = I2cResourceInfo->I2cSliceNumber + ASCII_0_ORDINAL;
+ NextResource = NextResource + sizeof(I2C_RESOURCE_DATA) - sizeof(UINT8);
+ CurrentTablePointer = CurrentTablePointer + sizeof(SsdtI2cSerialBusResource);
+
+ break;
+ }
+ }
+ }
+ CopyMem(CurrentTablePointer, &SsdtResourceTemplateEndTag, sizeof(SsdtResourceTemplateEndTag));
+ CurrentTablePointer = CurrentTablePointer + sizeof(SsdtResourceTemplateEndTag);
+ if (SsdtDeviceInfo->EnableStatus == TRUE) {
+ SsdtStatusMethod[ACPI_STA_RETURN_VALUE_OFFSET] = ACPI_STA_RETURN_VALUE_DEVICE_ENABLED;
+ } else {
+ SsdtStatusMethod[ACPI_STA_RETURN_VALUE_OFFSET] = ACPI_STA_RETURN_VALUE_DEVICE_DISABLED;
+ }
+ CopyMem(CurrentTablePointer, &SsdtStatusMethod, sizeof(SsdtStatusMethod));
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Generate SSDTs from ACPI data available in BIOS board files
+ or ACPI data generated from PCT tool FVs
+**/
+EFI_STATUS
+GenerateSsdtFromConfigFile (
+ VOID
+)
+{
+ EFI_STATUS Status = EFI_SUCCESS;
+ UINTN Pages;
+ UINT8 *CurrentTable;
+ EFI_ACPI_TABLE_PROTOCOL *AcpiTable;
+ EFI_ACPI_SDT_HEADER *AcpiTableHeader;
+ UINT32 SsdtTableSize;
+ UINT8 *PctAcpiDataBase;
+ UINTN i,j;
+ UINT8 *PrintData;
+ UINTN TableHandle;
+ PCT_ACPI_BLOCK_HDR *PctAcpiDataHeader;
+ UINT16 TableCount;
+ UINT8 *AcpiDataPointer;
+
+ DEBUG((DEBUG_INFO, "GenSsdt start\n"));
+ Status = gBS->LocateProtocol (&gEfiAcpiTableProtocolGuid, NULL, (VOID **) &AcpiTable);
+ ASSERT_EFI_ERROR(Status);
+
+ //
+ // Look for ACPI data HOB from PCT
+ //
+ PctAcpiDataBase = (UINT8 *) PcdGetPtr(PcdBoardAcpiData);
+ if (PctAcpiDataBase == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ if (*PctAcpiDataBase != 0) {
+ PctAcpiDataHeader = (PCT_ACPI_BLOCK_HDR *) PctAcpiDataBase;
+ AcpiDataPointer = (UINT8 *) (PctAcpiDataBase + sizeof(PCT_ACPI_BLOCK_HDR));
+ // Get number of tables to be generated
+ TableCount = PctAcpiDataHeader->Count;
+ for (i=0; i<TableCount; i++) {
+ // Calculate table size to be created
+ Status = GetTableSize(AcpiDataPointer, &SsdtTableSize);
+ ASSERT_EFI_ERROR (Status);
+
+ // Allocate memory for SSDT
+ Pages = EFI_SIZE_TO_PAGES(SsdtTableSize);
+ Status = (gBS->AllocatePages) (
+ AllocateMaxAddress,
+ EfiACPIMemoryNVS,
+ Pages,
+ (EFI_PHYSICAL_ADDRESS *) &CurrentTable
+ );
+ ASSERT_EFI_ERROR (Status);
+ ZeroMem ((VOID *) CurrentTable, SsdtTableSize);
+
+ //Copy SSDT content to allocated space
+ Status = CreateAcpiTableInMemory(AcpiDataPointer, &SsdtTableSize, CurrentTable);
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Dump table content from memory
+ //
+ DEBUG_CODE_BEGIN();
+ PrintData = (UINT8 *)CurrentTable;
+ DEBUG((DEBUG_INFO, "GenSsdt TableDump:\n"));
+ for (j=0; j<SsdtTableSize; j++) {
+ DEBUG((DEBUG_INFO, "%02x ", *PrintData));
+ PrintData++;
+ }
+ DEBUG((DEBUG_INFO, "\n"));
+ DEBUG_CODE_END();
+
+ TableHandle = 0;
+ AcpiTableHeader = (EFI_ACPI_SDT_HEADER *)CurrentTable;
+
+ //
+ // Install SSDT
+ //
+ Status = AcpiTable->InstallAcpiTable (
+ AcpiTable,
+ CurrentTable,
+ AcpiTableHeader->Length,
+ &TableHandle
+ );
+
+ ASSERT_EFI_ERROR(Status);
+
+ AcpiDataPointer += ((EFI_ACPI_SDT_HEADER *) AcpiDataPointer)->Length;
+ }
+ }
+ return Status;
+}
\ No newline at end of file
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AdvancedAcpiDxe/GenSsdtLib.h b/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AdvancedAcpiDxe/GenSsdtLib.h
new file mode 100644
index 0000000000..0cb3a4aaef
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AdvancedAcpiDxe/GenSsdtLib.h
@@ -0,0 +1,17 @@
+/** @file
+ This is an implementation of the ACPI platform driver.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _GEN_SSDT_LIB_H_
+#define _GEN_SSDT_LIB_H_
+
+EFI_STATUS
+GenerateSsdtFromConfigFile (
+ VOID
+);
+
+#endif
--
2.36.1.windows.1
^ permalink raw reply related [flat|nested] 6+ messages in thread* [PATCH 6/6] AlderlakeOpenBoardPkg: Add Library Instances
[not found] <cover.1686770061.git.saloni.kasbekar@intel.com>
` (4 preceding siblings ...)
2023-06-14 19:17 ` [PATCH 5/6] AlderlakeOpenBoardPkg: Adds the Policy Module Saloni Kasbekar
@ 2023-06-14 19:17 ` Saloni Kasbekar
5 siblings, 0 replies; 6+ messages in thread
From: Saloni Kasbekar @ 2023-06-14 19:17 UTC (permalink / raw)
To: devel
Cc: Saloni Kasbekar, Sai Chaganty, Nate DeSimone, Isaac Oram,
Rosen Chuang
Adds the following libraries
- BasePlatformHookLib
- DxeAcpiGnvsInitLib
- PeiBoardConfigLib
- PeiGetFvInfoLib
- PeiReportFvLib
- SmmSpiFlashCommonLib
Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Isaac Oram <isaac.w.oram@intel.com>
Cc: Rosen Chuang <rosen.chuang@intel.com>
Signed-off-by: Saloni Kasbekar <saloni.kasbekar@intel.com>
---
.../BasePlatformHookLib/BasePlatformHookLib.c | 38 +
.../BasePlatformHookLib.inf | 48 +
.../DxeAcpiGnvsInitLib/DxeAcpiGnvsInitLib.c | 62 +
.../DxeAcpiGnvsInitLib/DxeAcpiGnvsInitLib.inf | 34 +
.../PeiBoardConfigLib/PeiBoardConfigLib.c | 252 ++++
.../PeiBoardConfigLib/PeiBoardConfigLib.inf | 73 ++
.../Library/PeiBoardConfigLib/PeiSpdTables.c | 1041 +++++++++++++++++
.../Library/PeiGetFvInfoLib/PeiGetFvInfoLib.c | 89 ++
.../PeiGetFvInfoLib/PeiGetFvInfoLib.inf | 34 +
.../Library/PeiReportFvLib/PeiReportFvLib.c | 372 ++++++
.../Library/PeiReportFvLib/PeiReportFvLib.inf | 78 ++
.../SmmSpiFlashCommonLib.inf | 52 +
.../SmmSpiFlashCommonLib/SpiFlashCommon.c | 215 ++++
.../SpiFlashCommonSmmLib.c | 64 +
14 files changed, 2452 insertions(+)
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Library/BasePlatformHookLib/BasePlatformHookLib.c
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Library/BasePlatformHookLib/BasePlatformHookLib.inf
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Library/DxeAcpiGnvsInitLib/DxeAcpiGnvsInitLib.c
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Library/DxeAcpiGnvsInitLib/DxeAcpiGnvsInitLib.inf
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Library/PeiBoardConfigLib/PeiBoardConfigLib.c
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Library/PeiBoardConfigLib/PeiBoardConfigLib.inf
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Library/PeiBoardConfigLib/PeiSpdTables.c
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Library/PeiGetFvInfoLib/PeiGetFvInfoLib.c
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Library/PeiGetFvInfoLib/PeiGetFvInfoLib.inf
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Library/PeiReportFvLib/PeiReportFvLib.c
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Library/PeiReportFvLib/PeiReportFvLib.inf
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Library/SmmSpiFlashCommonLib/SmmSpiFlashCommonLib.inf
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Library/SmmSpiFlashCommonLib/SpiFlashCommon.c
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Library/SmmSpiFlashCommonLib/SpiFlashCommonSmmLib.c
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Library/BasePlatformHookLib/BasePlatformHookLib.c b/Platform/Intel/AlderlakeOpenBoardPkg/Library/BasePlatformHookLib/BasePlatformHookLib.c
new file mode 100644
index 0000000000..cccb1e18cc
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Library/BasePlatformHookLib/BasePlatformHookLib.c
@@ -0,0 +1,38 @@
+/** @file
+ Platform Hook Library instances
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Uefi/UefiBaseType.h>
+#include <Library/PchCycleDecodingLib.h>
+
+
+/**
+ Performs platform specific initialization required for the CPU to access
+ the hardware associated with a SerialPortLib instance. This function does
+ not initialize the serial port hardware itself. Instead, it initializes
+ hardware devices that are required for the CPU to access the serial port
+ hardware. This function may be called more than once.
+
+ @retval RETURN_SUCCESS The platform specific initialization succeeded.
+ @retval RETURN_DEVICE_ERROR The platform specific initialization could not be completed.
+
+**/
+RETURN_STATUS
+EFIAPI
+PlatformHookSerialPortInitialize (
+ VOID
+ )
+{
+
+ //
+ // Enable I/O decoding for COM1(3F8h-3FFh), COM2(2F8h-2FFh), I/O port 2Eh/2Fh, 4Eh/4Fh, 60h/64Fh and 62h/66h.
+ //
+ PchLpcIoDecodeRangesSet (PcdGet16 (PcdLpcIoDecodeRange));
+ PchLpcIoEnableDecodingSet (PcdGet16 (PchLpcIoEnableDecoding));
+
+ return RETURN_SUCCESS;
+}
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Library/BasePlatformHookLib/BasePlatformHookLib.inf b/Platform/Intel/AlderlakeOpenBoardPkg/Library/BasePlatformHookLib/BasePlatformHookLib.inf
new file mode 100644
index 0000000000..19458e7724
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Library/BasePlatformHookLib/BasePlatformHookLib.inf
@@ -0,0 +1,48 @@
+### @file
+# Platform Hook Library instance for Alderlake Mobile/Desktop CRB.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+###
+
+[Defines]
+ INF_VERSION = 0x00010017
+ BASE_NAME = BasePlatformHookLib
+ FILE_GUID = E22ADCC6-ED90-4A90-9837-C8E7FF9E963D
+ VERSION_STRING = 1.0
+ MODULE_TYPE = BASE
+ LIBRARY_CLASS = PlatformHookLib
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = IA32 X64 IPF EBC
+#
+
+[LibraryClasses]
+ BaseLib
+ IoLib
+ PciSegmentLib
+ PciLib
+ PchCycleDecodingLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ MinPlatformPkg/MinPlatformPkg.dec
+ AlderlakeOpenBoardPkg/OpenBoardPkg.dec
+ AlderlakeSiliconPkg/SiPkg.dec
+
+[Pcd]
+ gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdLpcSioIndexPort ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdLpcSioDataPort ## CONSUMES
+
+[FixedPcd]
+ gBoardModuleTokenSpaceGuid.PcdLpcSioConfigDefaultPort ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdSioBaseAddress ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdLpcIoDecodeRange ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PchLpcIoEnableDecoding ## CONSUMES
+
+[Sources]
+ BasePlatformHookLib.c
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Library/DxeAcpiGnvsInitLib/DxeAcpiGnvsInitLib.c b/Platform/Intel/AlderlakeOpenBoardPkg/Library/DxeAcpiGnvsInitLib/DxeAcpiGnvsInitLib.c
new file mode 100644
index 0000000000..3aef72ea52
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Library/DxeAcpiGnvsInitLib/DxeAcpiGnvsInitLib.c
@@ -0,0 +1,62 @@
+/** @file
+ Acpi Gnvs Init Library.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Uefi.h>
+#include <Library/IoLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+
+#include <Protocol/PlatformNvsArea.h>
+#include <Library/DxeAcpiGnvsInitLib.h>
+
+/**
+@brief
+ Global NVS initialize.
+
+ @param[in] PlatformNvsAreaPtr - Pointer of global NVS area
+
+ @retval EFI_SUCCESS - Allocate Global NVS completed.
+ @retval EFI_OUT_OF_RESOURCES - Failed to allocate required page for PlatformNvsAreaProtocol.
+**/
+EFI_STATUS
+EFIAPI
+AcpiGnvsInit (
+ IN OUT VOID **PlatformNvsAreaPtr
+ )
+{
+ UINTN Pages;
+ EFI_PHYSICAL_ADDRESS Address;
+ EFI_STATUS Status;
+ PLATFORM_NVS_AREA_PROTOCOL *PlatformNvsAreaProtocol;
+
+ Pages = EFI_SIZE_TO_PAGES (sizeof (PLATFORM_NVS_AREA));
+ Address = 0xffffffff; // allocate address below 4G.
+
+ Status = gBS->AllocatePages (
+ AllocateMaxAddress,
+ EfiACPIMemoryNVS,
+ Pages,
+ &Address
+ );
+ ASSERT_EFI_ERROR (Status);
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+
+ *PlatformNvsAreaPtr = (VOID *) (UINTN) Address;
+ SetMem (*PlatformNvsAreaPtr, sizeof (PLATFORM_NVS_AREA), 0);
+
+ //
+ // PlatformNvsAreaProtocol default value init here...
+ //
+ PlatformNvsAreaProtocol = (PLATFORM_NVS_AREA_PROTOCOL *) &Address;
+
+ return EFI_SUCCESS;
+}
+
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Library/DxeAcpiGnvsInitLib/DxeAcpiGnvsInitLib.inf b/Platform/Intel/AlderlakeOpenBoardPkg/Library/DxeAcpiGnvsInitLib/DxeAcpiGnvsInitLib.inf
new file mode 100644
index 0000000000..f9ec542f50
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Library/DxeAcpiGnvsInitLib/DxeAcpiGnvsInitLib.inf
@@ -0,0 +1,34 @@
+### @file
+# Component description file for the DxeAcpiGnvsInitLib
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+###
+
+[Defines]
+ INF_VERSION = 0x00010017
+ BASE_NAME = DxeAcpiGnvsInitLib
+ FILE_GUID = 9972077E-00AA-4F66-8CDA-E53CBD74A2F9
+ VERSION_STRING = 1.0
+ MODULE_TYPE = BASE
+ LIBRARY_CLASS = DxeAcpiGnvsInitLib
+
+[LibraryClasses]
+ BaseLib
+ DebugLib
+ IoLib
+ BaseMemoryLib
+ UefiBootServicesTableLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ AlderlakeOpenBoardPkg/OpenBoardPkg.dec
+ AlderlakeSiliconPkg/SiPkg.dec
+
+[Sources]
+ DxeAcpiGnvsInitLib.c
+
+[Pcd]
+ # gSiPkgTokenSpaceGuid.PcdAdlLpSupport ## CONSUMES
+ # gSiPkgTokenSpaceGuid.PcdAdlSSupport ## CONSUMES
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Library/PeiBoardConfigLib/PeiBoardConfigLib.c b/Platform/Intel/AlderlakeOpenBoardPkg/Library/PeiBoardConfigLib/PeiBoardConfigLib.c
new file mode 100644
index 0000000000..7b041e9315
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Library/PeiBoardConfigLib/PeiBoardConfigLib.c
@@ -0,0 +1,252 @@
+/** @file
+ Implementation of PeiBoardConfigLib.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <PiPei.h>
+#include <Library/DebugLib.h>
+#include <Library/PcdLib.h>
+#include <Library/PostCodeLib.h>
+#include <Library/TimerLib.h>
+
+#include <Library/GpioLib.h>
+
+#include <PlatformBoardType.h>
+#include <PlatformBoardId.h>
+#include <PlatformBoardConfig.h>
+#include <Ppi/ReadOnlyVariable2.h>
+#include <Library/PeiServicesLib.h>
+#include <Library/PmcLib.h>
+#include <Library/BoardConfigLib.h>
+
+
+
+VOID
+EFIAPI
+InternalUpdateRvpBoardConfig (
+ IN OUT UINT16 BoardId
+ )
+{
+ UINT8 BoardType;
+ UINT8 PlatformType;
+ UINT8 PlatformFlavor;
+
+ //
+ // Update Board Type/Platform Type/Platform Flavor
+ //
+ switch (BoardId) {
+ case BoardIdAdlPDdr5Rvp:
+ BoardType = BoardTypeRvp;
+ PlatformType = TypeUltUlx;
+ PlatformFlavor = FlavorMobile;
+ if(PcdSet64S (PcdAcpiDefaultOemTableId, ACPI_OEM_TABLE_ID_ADL_P_M) != EFI_SUCCESS)
+ {
+ DEBUG ((DEBUG_INFO, "Set PcdAcpiDefaultOemTableId error!!!\n"));
+ }
+ break;
+
+ default:
+ BoardType = BoardTypeRvp;
+ PlatformType = TypeUnknown;
+ PlatformFlavor = FlavorUnknown;
+ break;
+ }
+
+ PcdSet8S (PcdBoardType, BoardType);
+ PcdSet8S (PcdPlatformType, PlatformType);
+ PcdSet8S (PcdPlatformFlavor, PlatformFlavor);
+
+ DEBUG ((DEBUG_INFO, "PcdAcpiDefaultOemTableId is 0x%llX\n", PcdGet64 (PcdAcpiDefaultOemTableId)));
+}
+
+/**
+ Procedure to detect current board HW configuration.
+
+**/
+VOID
+GetBoardConfig (
+ VOID
+ )
+{
+ UINT16 BoardId;
+
+ //
+ // Get Platform Info and fill the PCD
+ //
+ BoardId = BoardIdAdlPDdr5Rvp;
+ PcdSet8S (PcdBoardType, BoardTypeMax);
+ PcdSet16S (PcdBoardId, BoardId);
+ //
+ // update RVP board config
+ //
+ InternalUpdateRvpBoardConfig (BoardId);
+
+ DEBUG ((DEBUG_INFO, "Platform Information:\n"));
+ DEBUG ((DEBUG_INFO, "PlatformType: %x\n", PcdGet8 (PcdPlatformType)));
+ DEBUG ((DEBUG_INFO, "PlatformFlavor: %x\n", PcdGet8 (PcdPlatformFlavor)));
+ DEBUG ((DEBUG_INFO, "BoardID: 0x%x\n", BoardId));
+ DEBUG ((DEBUG_INFO, "BoardType: %x\n", PcdGet8 (PcdBoardType)));
+
+}
+
+/**
+ Count the number of GPIO settings in the Table.
+
+ @param[in] GpioTable The pointer of GPIO config table
+ @param[out] GpioCount The number of GPIO config entries
+**/
+VOID
+GetGpioTableSize (
+ GPIO_INIT_CONFIG *GpioTable,
+ OUT UINT16 *GpioCount
+ )
+{
+ *GpioCount = 0;
+ if(GpioTable != NULL) {
+ while (GpioTable[*GpioCount].GpioPad != 0 && *GpioCount < MAX_GPIO_PINS) {
+ DEBUG ((DEBUG_INFO, "GpioTable[%d]->GpioPad = %x \n", *GpioCount, GpioTable[*GpioCount].GpioPad));
+ (*GpioCount) ++;
+ }
+ } else {
+ DEBUG ((DEBUG_INFO, "GpioTable is NULL\n"));
+ }
+ DEBUG ((DEBUG_INFO, "GetGpioTableSize() GpioCount = %d\n", *GpioCount));
+}
+
+/**
+Configure GPIO Table setting to PcdBoardGpioTablePreMem && PcdBoardGpioTable
+
+@param[in] GpioTable The pointer of GPIO config table
+@param[in] IsPostMem Is call from PostMem/PreMem
+ True - PostMem, False - PreMem
+**/
+VOID
+ConfigureGpioTabletoPCD(
+ IN GPIO_INIT_CONFIG *GpioTable,
+ IN UINT16 IsPostMem
+ )
+{
+ UINT16 GpioCount = 0;
+ UINTN Size = 0;
+ EFI_STATUS Status = EFI_SUCCESS;
+ BOOLEAN DisableVpdGpioTable = FALSE;
+
+ DEBUG ((DEBUG_INFO, "ConfigureGpioTabletoPCD() Start\n"));
+
+ DisableVpdGpioTable = (BOOLEAN) PcdGetBool (PcdDisableVpdGpioTable);
+ DEBUG((DEBUG_INFO, "PcdDisableVpdGpioTable = %d\n", DisableVpdGpioTable));
+ if (!DisableVpdGpioTable) {
+ if (GpioTable != NULL) {
+ GetGpioTableSize (GpioTable, &GpioCount);
+ if (GpioCount) {
+ if (IsPostMem == POST_MEM) { // Post Mem GPIO Configuration
+ if (GpioCount >= MAX_GPIO_PINS) {
+ DEBUG ((DEBUG_ERROR, "GpioTable entries exceeds limit, Configure only MAX_GPIO_PINS Pins.\n"));
+ GpioCount = MAX_GPIO_PINS;
+ }
+ DEBUG ((DEBUG_INFO, "GpioTable Count = %d\n", GpioCount));
+ Size = (UINTN) (GpioCount * sizeof (GPIO_INIT_CONFIG));
+ Status = PcdSetPtrS (PcdBoardGpioTable, &Size, GpioTable);
+ } else if (IsPostMem == PRE_MEM) { // Pre Mem GPIO Configuration
+ if (GpioCount >= MAX_PRE_MEM_GPIO_PINS) {
+ DEBUG ((DEBUG_ERROR, "PreMem GpioTable entries exceeds limit, Configure only MAX_PRE_MEM_GPIO_PINS Pins.\n"));
+ GpioCount = MAX_PRE_MEM_GPIO_PINS;
+ }
+ DEBUG ((DEBUG_INFO, "GpioTable Count = %d\n", GpioCount));
+ Size = (UINTN) (GpioCount * sizeof (GPIO_INIT_CONFIG));
+ Status = PcdSetPtrS (PcdBoardGpioTablePreMem, &Size, GpioTable);
+ } else if (IsPostMem == EARLY_PRE_MEM) { // Pre Mem GPIO Configuration
+ if (GpioCount >= MAX_PRE_MEM_GPIO_PINS) {
+ DEBUG((DEBUG_ERROR, "EarlyPreMem GpioTable entries exceeds limit, Configure only MAX_PRE_MEM_GPIO_PINS Pins.\n"));
+ GpioCount = MAX_PRE_MEM_GPIO_PINS;
+ }
+ DEBUG((DEBUG_INFO, "EarlyPreMem GpioTable Count = %d\n", GpioCount));
+ Size = (UINTN)(GpioCount * sizeof(GPIO_INIT_CONFIG));
+ Status = PcdSetPtrS(PcdBoardGpioTableEarlyPreMem, &Size, GpioTable);
+ }
+ ASSERT_EFI_ERROR (Status);
+ } else {
+ DEBUG ((DEBUG_INFO, "GpioTable is Empty\n"));
+ }
+ } else {
+ DEBUG ((DEBUG_INFO, "GpioTable is NULL\n"));
+ }
+ } else {
+ DEBUG ((DEBUG_INFO, "PcdDisableVpdGpioTable is TRUE, GPIO Tables will be updated by PCT PEIM \n"));
+ }
+
+ DEBUG ((DEBUG_INFO, "ConfigureGpioTabletoPCD() End\n"));
+}
+
+/**
+ Configures GPIO
+
+ @param[in] GpioTable Point to Platform Gpio table
+ @param[in] GpioTableCount Number of Gpio table entries
+**/
+STATIC
+VOID
+ConfigureGpio (
+ IN GPIO_INIT_CONFIG *GpioTable,
+ IN UINT16 GpioTableCount
+ )
+{
+ EFI_STATUS Status;
+
+ DEBUG ((DEBUG_INFO, "ConfigureGpio() Start\n"));
+
+ Status = GpioConfigurePads (GpioTableCount, GpioTable);
+ ASSERT_EFI_ERROR (Status);
+
+ DEBUG ((DEBUG_INFO, "ConfigureGpio() End\n"));
+}
+
+/**
+ Configure GPIO Before Memory is initialized.
+
+ @param[in] GpioTable Pointer to Gpio table
+**/
+VOID
+GpioInit (
+ IN GPIO_INIT_CONFIG *GpioTable
+ )
+{
+ UINT16 GpioCount;
+
+ if (GpioTable != 0) {
+ GpioCount = 0;
+ GetGpioTableSize (GpioTable, &GpioCount);
+ if (GpioCount != 0) {
+ ConfigureGpio ((VOID *) GpioTable, (UINTN) GpioCount);
+ }
+ }
+}
+
+/**
+ Update Cpu Xhci Port Enable Map PCD from SaSetup data.
+
+**/
+VOID
+EFIAPI
+TcssUpdateCpuXhciPortEnableMapPcd (
+ VOID
+ )
+{
+ UINT8 PortEnableMask;
+ UINT8 PortEnableMap;
+
+ DEBUG ((DEBUG_INFO, "[TCSS] TcssUpdateCpuXhciPortEnableMapPcd: Start\n"));
+ PortEnableMask = 0x0F; // Enable Mask for All 4 CPU USB Port.
+ PortEnableMap = PcdGet8 (PcdCpuXhciPortSupportMap); // Get Board Capability Map set Cpu Xhci Port.
+
+
+ DEBUG ((DEBUG_INFO, "[TCSS] Cpu Usb Port Enable Mask is = 0x%x\n", PortEnableMask));
+ PortEnableMap &= PortEnableMask; // Apply the Mask calculated from SaSetup Data.
+ DEBUG ((DEBUG_INFO, "[TCSS] Cpu Usb Port Enable Map in Post-Mem is = 0x%x\n", PortEnableMap));
+ PcdSet8S (PcdCpuUsb30PortEnable, PortEnableMap);
+ DEBUG ((DEBUG_INFO, "[TCSS] TcssUpdateCpuXhciPortEnableMapPcd: End\n"));
+}
+
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Library/PeiBoardConfigLib/PeiBoardConfigLib.inf b/Platform/Intel/AlderlakeOpenBoardPkg/Library/PeiBoardConfigLib/PeiBoardConfigLib.inf
new file mode 100644
index 0000000000..4e3f3d375b
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Library/PeiBoardConfigLib/PeiBoardConfigLib.inf
@@ -0,0 +1,73 @@
+### @file
+# Component information file for BaseBoardConfigLib.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+###
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = PeiBoardConfigLib
+ FILE_GUID = AA9812A8-1BA6-40AD-A846-50D0BC29C38C
+ MODULE_TYPE = PEIM
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = BoardConfigLib|PEIM
+
+[LibraryClasses]
+ DebugLib
+ PcdLib
+ PostCodeLib
+ TimerLib
+ PeiServicesLib
+ PmcLib
+ GpioLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ AlderlakeSiliconPkg/SiPkg.dec
+ AlderlakeOpenBoardPkg/OpenBoardPkg.dec
+
+[Sources]
+ PeiBoardConfigLib.c
+ PeiSpdTables.c
+
+[Ppis]
+ gEfiPeiReadOnlyVariable2PpiGuid ## CONSUMES
+
+[Pcd]
+ gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemTableId ## PRODUCES ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdBoardId ## PRODUCES ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdBoardBomId ## PRODUCES ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdBoardRev ## PRODUCES ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdSpdPresent ## PRODUCES ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdBoardType ## PRODUCES ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdPlatformType ## PRODUCES ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdPlatformFlavor ## PRODUCES ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdPlatformGeneration ## CONSUMES
+
+ # GPIO Group Tier
+ gBoardModuleTokenSpaceGuid.PcdGpioGroupToGpeDw0
+ gBoardModuleTokenSpaceGuid.PcdGpioGroupToGpeDw1
+ gBoardModuleTokenSpaceGuid.PcdGpioGroupToGpeDw2
+
+ gBoardModuleTokenSpaceGuid.PcdDisableVpdGpioTable
+ gBoardModuleTokenSpaceGuid.PcdBoardGpioTable
+ gBoardModuleTokenSpaceGuid.PcdBoardGpioTablePreMem
+ gBoardModuleTokenSpaceGuid.PcdBoardGpioTableEarlyPreMem
+ gBoardModuleTokenSpaceGuid.PcdDisplayId ## PRODUCES ## CONSUMES
+
+ # Cpu USB XHCI Port Enable Mapping
+ gBoardModuleTokenSpaceGuid.PcdCpuXhciPortSupportMap
+ gBoardModuleTokenSpaceGuid.PcdCpuUsb30PortEnable
+
+[FixedPcd]
+ gSiPkgTokenSpaceGuid.PcdAdlLpSupport ## CONSUMES
+ gSiPkgTokenSpaceGuid.PcdAdlSSupport ## CONSUMES
+
+[Guids]
+ gBoardInfoVariableGuid
+
+[Depex]
+ gEfiPeiReadOnlyVariable2PpiGuid
\ No newline at end of file
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Library/PeiBoardConfigLib/PeiSpdTables.c b/Platform/Intel/AlderlakeOpenBoardPkg/Library/PeiBoardConfigLib/PeiSpdTables.c
new file mode 100644
index 0000000000..37cd660014
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Library/PeiBoardConfigLib/PeiSpdTables.c
@@ -0,0 +1,1041 @@
+/** @file
+ SPD tables for ADL boards.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+// LPDDR4 200b
+// Samsung K4F6E304Hx-MGCJ
+// or Hynix H9HCNNNBUUxLHR-NMx
+// or Micron MT53B512M32D2NP-053
+// 3733, 32-34-34-79
+GLOBAL_REMOVE_IF_UNREFERENCED const UINT8 mLpddr4Ddp8Gb200bSpd[] = {
+ 0x23, ///< 0 384 SPD bytes used, 512 total
+ 0x11, ///< 1 SPD Revision 1.1
+ 0x10, ///< 2 DRAM Type: LPDDR4 SDRAM
+ 0x0E, ///< 3 Module Type: Not Hybrid (DRAM only) / Non-DIMM Solution (on-board DRAM)
+ 0x15, ///< 4 8 Banks, no bank groups, 8 Gb SDRAM density
+ 0x19, ///< 5 15 Rows, 10 Columns
+ 0x91, ///< 6 Non-Monolithic DRAM Device, 2 die, 1 Channels per package, Signal Loading Matrix 1
+ 0x08, ///< 7 SDRAM Optional Features: tMAW = 8192 * tREFI, Unlimited MAC
+ 0x00, ///< 8 SDRAM Thermal / Refresh options: Reserved
+ 0x40, ///< 9 Other SDRAM Optional Features: Post package repair supported, one row per bank group, Soft PPR not supported
+ 0x00, ///< 10 Reserved
+ 0x00, ///< 11 Module Nominal Voltage: Reserved
+ 0x0A, ///< 12 Module Organization: 2 Ranks, x16 Device Width per Channel
+ 0x01, ///< 13 Module Memory Bus width: 1 Channels, 16 bits channel width, no ECC
+ 0x00, ///< 14 Module Thermal Sensor: none
+ 0x00, ///< 15 Extended Module Type: Reserved
+ 0x00, ///< 16 Signal Loading: not specified
+ 0x00, ///< 17 MTB = 0.125ns, FTB = 1 ps
+ 0x05, ///< 18 tCKAVGmin = 0.536 ns (LPDDR4-3733)
+ 0x0F, ///< 19 tCKAVGmax = 1.875 ns
+ 0x92, ///< 20 CAS Latencies supported (First Byte) : 14, 10, 6
+ 0x54, ///< 21 CAS Latencies supported (Second Byte): 28, 24, 20
+ 0x01, ///< 22 CAS Latencies supported (Third Byte) : 32
+ 0x00, ///< 23 CAS Latencies supported (Fourth Byte):
+ 0x8A, ///< 24 Minimum CAS Latency (tAAmin) = 17.14 ns
+ 0x00, ///< 25 Read and Write Latency Set options: Write Latency Set A and DBI-Read Disabled
+ 0x90, ///< 26 Minimum RAS-to-CAS delay (tRCDmin) = 18 ns
+ 0xA8, ///< 27 Row precharge time for all banks (tRPab) = 21 ns
+ 0x90, ///< 28 Minimum row precharge time (tRPmin) = 18 ns
+ 0xA0, ///< 29 tRFCab = 180 ns (8 Gb dual-channel die)
+ 0x05, ///< 30 tRFCab MSB
+ 0xD0, ///< 31 tRFCpb = 90 ns (8 Gb dual-channel die)
+ 0x02, ///< 32 tRFCpb MSB
+ 0, 0, 0, 0, 0, 0, 0, ///< 33 - 39
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 40 - 49
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 50 - 59
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 60 - 69
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 70 - 79
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 80 - 89
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 90 - 99
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 100 - 109
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 110 - 119
+ 0x00, ///< 120 FTB for Row precharge time per bank (tRPpb) = 18 ns
+ 0x00, ///< 121 FTB for Row precharge time for all banks (tRPab) = 21 ns
+ 0x00, ///< 122 FTB for Minimum RAS-to-CAS delay (tRCDmin) = 18 ns
+ 0x92, ///< 123 FTB for tAAmin = 17.14 ns
+ 0x00, ///< 124 FTB for tCKAVGmax = 1.875 ns
+ 0xA7, ///< 125 FTB for tCKAVGmin = 0.536 ns (LPDDR4-3733)
+ 0x00, ///< 126 CRC A
+ 0x00, ///< 127 CRC B
+ 0, 0, ///< 128 - 129
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 130 - 139
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 140 - 149
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 150 - 159
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 160 - 169
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 170 - 179
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 180 - 189
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 190 - 199
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 200 - 209
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 210 - 219
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 220 - 229
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 230 - 239
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 240 - 249
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 250 - 259
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 260 - 269
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 270 - 279
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 280 - 289
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 290 - 299
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 300 - 309
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 310 - 319
+ 0x00, ///< 320 Module Manufacturer ID Code, Least Significant Byte
+ 0x00, ///< 321 Module Manufacturer ID Code, Most Significant Byte
+ 0x00, ///< 322 Module Manufacturing Location
+ 0x00, ///< 323 Module Manufacturing Date Year
+ 0x00, ///< 324 Module Manufacturing Date Week
+ 0x20, ///< 325 Module Serial Number A
+ 0x00, ///< 326 Module Serial Number B
+ 0x00, ///< 327 Module Serial Number C
+ 0x00, ///< 328 Module Serial Number D
+ 0x20, 0x20, 0x20, 0x20, 0x20, ///< 329 - 333 Module Part Number: Unused bytes coded as ASCII Blanks (0x20)
+ 0x20, 0x20, 0x20, 0x20, 0x20, ///< 334 - 338 Module Part Number
+ 0x20, 0x20, 0x20, 0x20, 0x20, ///< 339 - 343 Module Part Number
+ 0x20, 0x20, 0x20, 0x20, 0x20, ///< 344 - 348 Module Part Number
+ 0x00, ///< 349 Module Revision Code
+ 0x00, ///< 350 DRAM Manufacturer ID Code, Least Significant Byte
+ 0x00, ///< 351 DRAM Manufacturer ID Code, Most Significant Byte
+ 0x00 ///< 352 DRAM Stepping
+ ///< 353 - 511 are zeroes, no need to keep them, reduce BIOS image size
+};
+
+// LPDDR4X 556b
+// Micron MT53D512M64D4RQ-046 WT:E
+// 4266
+GLOBAL_REMOVE_IF_UNREFERENCED const UINT8 mLpddr4xQdp4Gb556bSpd[] = {
+ 0x23, ///< 0 384 SPD bytes used, 512 total
+ 0x11, ///< 1 SPD Revision 1.1
+ 0x11, ///< 2 DRAM Type: LPDDR4x SDRAM
+ 0x0E, ///< 3 Module Type: Not Hybrid (DRAM only) / Non-DIMM Solution (on-board DRAM)
+ 0x15, ///< 4 8 Banks, no bank groups, 8 Gb SDRAM density
+ 0x21, ///< 5 16 Row bits, 10 Column bits
+ 0xB9, ///< 6 Non-Monolithic DRAM Device, 4 dies, 2 Channels per die, Signal Loading not specified
+ 0x08, ///< 7 SDRAM Optional Features: tMAW = 8192 * tREFI, Unlimited MAC
+ 0x00, ///< 8 SDRAM Thermal / Refresh options: Reserved
+ 0x40, ///< 9 Other SDRAM Optional Features: Post package repair supported, one row per bank group, Soft PPR not supported
+ 0x00, ///< 10 Reserved
+ 0x00, ///< 11 Module Nominal Voltage: Reserved
+ 0x02, ///< 12 Module Organization: 1 Ranks, x16 Device Width per Channel
+ 0x01, ///< 13 Module Memory Bus width: 1 Channels, 16 bits channel width, no ECC
+ 0x00, ///< 14 Module Thermal Sensor: none
+ 0x00, ///< 15 Extended Module Type: Reserved
+ 0x00, ///< 16 Signal Loading: Not Specific
+ 0x00, ///< 17 MTB = 0.125ns, FTB = 1 ps
+ 0x04, ///< 18 tCKAVGmin = 0.536 ns (LPDDR4-3733)
+ 0x0F, ///< 19 tCKAVGmax = 1.875 ns
+ 0x92, ///< 20 CAS Latencies supported (First Byte) : 14, 10, 6
+ 0x54, ///< 21 CAS Latencies supported (Second Byte): 28, 24, 20
+ 0x05, ///< 22 CAS Latencies supported (Third Byte) : 32
+ 0x00, ///< 23 CAS Latencies supported (Fourth Byte):
+ 0x87, ///< 24 Minimum CAS Latency (tAAmin) = 17.14 ns
+ 0x00, ///< 25 Read and Write Latency Set options: Write Latency Set A and DBI-Read Disabled
+ 0x90, ///< 26 Minimum RAS-to-CAS delay (tRCDmin) = 18 ns
+ 0xA8, ///< 27 Row precharge time for all banks (tRPab) = 21 ns
+ 0x90, ///< 28 Minimum row precharge time (tRPmin) = 18 ns
+ 0xC0, ///< 29 tRFCab = 280 ns (8 Gb single-channel die)
+ 0x08, ///< 30 tRFCab MSB
+ 0x60, ///< 31 tRFCpb = 140 ns (8 Gb single-channel die)
+ 0x04, ///< 32 tRFCpb MSB
+ 0, 0, 0, 0, 0, 0, 0, ///< 33 - 39
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 40 - 49
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 50 - 59
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 60 - 69
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 70 - 79
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 80 - 89
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 90 - 99
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 100 - 109
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 110 - 119
+ 0x00, ///< 120 FTB for Row precharge time per bank (tRPpb) = 18 ns
+ 0x00, ///< 121 FTB for Row precharge time for all banks (tRPab) = 21 ns
+ 0x00, ///< 122 FTB for Minimum RAS-to-CAS delay (tRCDmin) = 18 ns
+ 0xE5, ///< 123 FTB for tAAmin = 17.14 ns (FTB = -0.11 ns)
+ 0x00, ///< 124 FTB for tCKAVGmax = 1.875 ns (FTB = 0 ns)
+ 0xE1, ///< 125 FTB for tCKAVGmin = 0.536 ns (FTB = -.089 ns) (LPDDR4-3733)
+ 0x85, ///< 126 CRC A
+ 0x85, ///< 127 CRC B
+ 0, 0, ///< 128 - 129
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 130 - 139
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 140 - 149
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 150 - 159
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 160 - 169
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 170 - 179
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 180 - 189
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 190 - 199
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 200 - 209
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 210 - 219
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 220 - 229
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 230 - 239
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 240 - 249
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 250 - 259
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 260 - 269
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 270 - 279
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 280 - 289
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 290 - 299
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 300 - 309
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 310 - 319
+ 0x00, ///< 320 Module Manufacturer ID Code, Least Significant Byte
+ 0x00, ///< 321 Module Manufacturer ID Code, Most Significant Byte
+ 0x00, ///< 322 Module Manufacturing Location
+ 0x00, ///< 323 Module Manufacturing Date Year
+ 0x00, ///< 324 Module Manufacturing Date Week
+ 0x56, ///< 325 Module Serial Number A
+ 0x00, ///< 326 Module Serial Number B
+ 0x00, ///< 327 Module Serial Number C
+ 0x00, ///< 328 Module Serial Number D
+ 0x20, 0x20, 0x20, 0x20, 0x20, ///< 329 - 333 Module Part Number: Unused bytes coded as ASCII Blanks (0x20)
+ 0x20, 0x20, 0x20, 0x20, 0x20, ///< 334 - 338 Module Part Number
+ 0x20, 0x20, 0x20, 0x20, 0x20, ///< 339 - 343 Module Part Number
+ 0x20, 0x20, 0x20, 0x20, 0x20, ///< 344 - 348 Module Part Number
+ 0x00, ///< 349 Module Revision Code
+ 0x00, ///< 350 DRAM Manufacturer ID Code, Least Significant Byte
+ 0x00, ///< 351 DRAM Manufacturer ID Code, Most Significant Byte
+ 0x00 ///< 352 DRAM Stepping
+ ///< 353 - 511 are zeroes, no need to keep them, reduce BIOS image size
+};
+
+// LPDDR4X 432b
+// Samsung K3UH7H70MM-JGCJ
+// 3733, 32-34-34-79
+GLOBAL_REMOVE_IF_UNREFERENCED const UINT8 mLpddr4xQdp16Gb432bSpd[] = {
+ 0x23, ///< 0 384 SPD bytes used, 512 total
+ 0x11, ///< 1 SPD Revision 1.1
+ 0x11, ///< 2 DRAM Type: LPDDR4x SDRAM
+ 0x0E, ///< 3 Module Type: Not Hybrid (DRAM only) / Non-DIMM Solution (on-board DRAM)
+ 0x16, ///< 4 8 Banks, no bank groups, 16 Gb SDRAM density
+ 0x21, ///< 5 16 Row bits, 10 Column bits
+ 0xB4, ///< 6 Non-Monolithic DRAM Device, 4 dies, 2 Channels per die, Signal Loading not specified
+ 0x08, ///< 7 SDRAM Optional Features: tMAW = 8192 * tREFI, Unlimited MAC
+ 0x00, ///< 8 SDRAM Thermal / Refresh options: Reserved
+ 0x40, ///< 9 Other SDRAM Optional Features: Post package repair supported, one row per bank group, Soft PPR not supported
+ 0x00, ///< 10 Reserved
+ 0x00, ///< 11 Module Nominal Voltage: Reserved
+ 0x0A, ///< 12 Module Organization: 2 Ranks, x16 Device Width per Channel
+ 0x01, ///< 13 Module Memory Bus width: 1 Channels, 16 bits channel width, no ECC
+ 0x00, ///< 14 Module Thermal Sensor: none
+ 0x00, ///< 15 Extended Module Type: Reserved
+ 0x48, ///< 16 Signal Loading: Data/Strobe/Mask: 2 loads, CAC: 2 loads, CS: 1 load
+ 0x00, ///< 17 MTB = 0.125ns, FTB = 1 ps
+ 0x05, ///< 18 tCKAVGmin = 0.536 ns (LPDDR4-3733)
+ 0x0F, ///< 19 tCKAVGmax = 1.875 ns
+ 0x92, ///< 20 CAS Latencies supported (First Byte) : 14, 10, 6
+ 0x54, ///< 21 CAS Latencies supported (Second Byte): 28, 24, 20
+ 0x01, ///< 22 CAS Latencies supported (Third Byte) : 32
+ 0x00, ///< 23 CAS Latencies supported (Fourth Byte):
+ 0x8A, ///< 24 Minimum CAS Latency (tAAmin) = 17.14 ns
+ 0x00, ///< 25 Read and Write Latency Set options: Write Latency Set A and DBI-Read Disabled
+ 0x90, ///< 26 Minimum RAS-to-CAS delay (tRCDmin) = 18 ns
+ 0xA8, ///< 27 Row precharge time for all banks (tRPab) = 21 ns
+ 0x90, ///< 28 Minimum row precharge time (tRPmin) = 18 ns
+ 0xC0, ///< 29 tRFCab = 280 ns (16 Gb dual-channel die)
+ 0x08, ///< 30 tRFCab MSB
+ 0x60, ///< 31 tRFCpb = 140 ns (16 Gb dual-channel die)
+ 0x04, ///< 32 tRFCpb MSB
+ 0, 0, 0, 0, 0, 0, 0, ///< 33 - 39
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 40 - 49
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 50 - 59
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 60 - 69
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 70 - 79
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 80 - 89
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 90 - 99
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 100 - 109
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 110 - 119
+ 0x00, ///< 120 FTB for Row precharge time per bank (tRPpb) = 18 ns
+ 0x00, ///< 121 FTB for Row precharge time for all banks (tRPab) = 21 ns
+ 0x00, ///< 122 FTB for Minimum RAS-to-CAS delay (tRCDmin) = 18 ns
+ 0x92, ///< 123 FTB for tAAmin = 17.14 ns (FTB = -0.11 ns)
+ 0x00, ///< 124 FTB for tCKAVGmax = 1.875 ns (FTB = 0 ns)
+ 0xA7, ///< 125 FTB for tCKAVGmin = 0.536 ns (FTB = -.089 ns) (LPDDR4-3733)
+ 0x00, ///< 126 CRC A
+ 0x00, ///< 127 CRC B
+ 0, 0, ///< 128 - 129
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 130 - 139
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 140 - 149
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 150 - 159
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 160 - 169
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 170 - 179
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 180 - 189
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 190 - 199
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 200 - 209
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 210 - 219
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 220 - 229
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 230 - 239
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 240 - 249
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 250 - 259
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 260 - 269
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 270 - 279
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 280 - 289
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 290 - 299
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 300 - 309
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 310 - 319
+ 0x00, ///< 320 Module Manufacturer ID Code, Least Significant Byte
+ 0x00, ///< 321 Module Manufacturer ID Code, Most Significant Byte
+ 0x00, ///< 322 Module Manufacturing Location
+ 0x00, ///< 323 Module Manufacturing Date Year
+ 0x00, ///< 324 Module Manufacturing Date Week
+ 0x43, ///< 325 Module Serial Number A
+ 0x00, ///< 326 Module Serial Number B
+ 0x00, ///< 327 Module Serial Number C
+ 0x00, ///< 328 Module Serial Number D
+ 0x20, 0x20, 0x20, 0x20, 0x20, ///< 329 - 333 Module Part Number: Unused bytes coded as ASCII Blanks (0x20)
+ 0x20, 0x20, 0x20, 0x20, 0x20, ///< 334 - 338 Module Part Number
+ 0x20, 0x20, 0x20, 0x20, 0x20, ///< 339 - 343 Module Part Number
+ 0x20, 0x20, 0x20, 0x20, 0x20, ///< 344 - 348 Module Part Number
+ 0x00, ///< 349 Module Revision Code
+ 0x80, ///< 350 DRAM Manufacturer ID Code, Least Significant Byte
+ 0xCE, ///< 351 DRAM Manufacturer ID Code, Most Significant Byte
+ 0x00 ///< 352 DRAM Stepping
+ ///< 353 - 511 are zeroes, no need to keep them, reduce BIOS image size
+};
+
+// LPDDR4X 556b
+// Micron MT53D1G64D8SQ-046
+// 4266
+GLOBAL_REMOVE_IF_UNREFERENCED const UINT8 mLpddr4xOdp8Gb556bSpd[] = {
+ 0x23, ///< 0 384 SPD bytes used, 512 total
+ 0x11, ///< 1 SPD Revision 1.1
+ 0x11, ///< 2 DRAM Type: LPDDR4x SDRAM
+ 0x0E, ///< 3 Module Type: Not Hybrid (DRAM only) / Non-DIMM Solution (on-board DRAM)
+ 0x1B, ///< 4 8 Banks, no bank groups, 6 Gb SDRAM density
+ 0x21, ///< 5 15 Rows, 10 Columns
+ 0xF8, ///< 6 Non-Monolithic DRAM Device, 8 die, 4 Channels per package, Signal Loading Matrix 1
+ 0x08, ///< 7 SDRAM Optional Features: tMAW = 8192 * tREFI, Unlimited MAC
+ 0x00, ///< 8 SDRAM Thermal / Refresh options: Reserved
+ 0x40, ///< 9 Other SDRAM Optional Features: Post package repair supported, one row per bank group, Soft PPR not supported
+ 0x00, ///< 10 Reserved
+ 0x00, ///< 11 Module Nominal Voltage: Reserved
+ 0x0A, ///< 12 Module Organization: 2 Ranks, x16 Device Width per Channel
+ 0x01, ///< 13 Module Memory Bus width: 1 Channels, 16 bits channel width, no ECC
+ 0x00, ///< 14 Module Thermal Sensor: none
+ 0x00, ///< 15 Extended Module Type: Reserved
+ 0x00, ///< 16 Signal Loading: Not Specific
+ 0x00, ///< 17 MTB = 0.125ns, FTB = 1 ps
+ 0x05, ///< 18 tCKAVGmin = 0.536 ns (LPDDR4-3733)
+ 0x0F, ///< 19 tCKAVGmax = 1.875 ns
+ 0x92, ///< 20 CAS Latencies supported (First Byte) : 14, 10, 6
+ 0x54, ///< 21 CAS Latencies supported (Second Byte): 28, 24, 20
+ 0x01, ///< 22 CAS Latencies supported (Third Byte) : 32
+ 0x00, ///< 23 CAS Latencies supported (Fourth Byte):
+ 0x8A, ///< 24 Minimum CAS Latency (tAAmin) = 17.14 ns
+ 0x00, ///< 25 Read and Write Latency Set options: Write Latency Set A and DBI-Read Disabled
+ 0x90, ///< 26 Minimum RAS-to-CAS delay (tRCDmin) = 18 ns
+ 0xA8, ///< 27 Row precharge time for all banks (tRPab) = 21 ns
+ 0x90, ///< 28 Minimum row precharge time (tRPmin) = 18 ns
+ 0xC0, ///< 29 tRFCab = 280 ns (8 Gb single-channel die)
+ 0x08, ///< 30 tRFCab MSB
+ 0x60, ///< 31 tRFCpb = 140 ns (8 Gb single-channel die)
+ 0x04, ///< 32 tRFCpb MSB
+ 0, 0, 0, 0, 0, 0, 0, ///< 33 - 39
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 40 - 49
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 50 - 59
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 60 - 69
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 70 - 79
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 80 - 89
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 90 - 99
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 100 - 109
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 110 - 119
+ 0x00, ///< 120 FTB for Row precharge time per bank (tRPpb) = 18 ns
+ 0x00, ///< 121 FTB for Row precharge time for all banks (tRPab) = 21 ns
+ 0x00, ///< 122 FTB for Minimum RAS-to-CAS delay (tRCDmin) = 18 ns
+ 0x92, ///< 123 FTB for tAAmin = 17.14 ns (FTB = -0.11 ns)
+ 0x00, ///< 124 FTB for tCKAVGmax = 1.875 ns (FTB = 0 ns)
+ 0xA7, ///< 125 FTB for tCKAVGmin = 0.536 ns (FTB = -.089 ns) (LPDDR4-3733)
+ 0x00, ///< 126 CRC A
+ 0x00, ///< 127 CRC B
+ 0, 0, ///< 128 - 129
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 130 - 139
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 140 - 149
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 150 - 159
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 160 - 169
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 170 - 179
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 180 - 189
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 190 - 199
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 200 - 209
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 210 - 219
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 220 - 229
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 230 - 239
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 240 - 249
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 250 - 259
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 260 - 269
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 270 - 279
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 280 - 289
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 290 - 299
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 300 - 309
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 310 - 319
+ 0x00, ///< 320 Module Manufacturer ID Code, Least Significant Byte
+ 0x00, ///< 321 Module Manufacturer ID Code, Most Significant Byte
+ 0x00, ///< 322 Module Manufacturing Location
+ 0x00, ///< 323 Module Manufacturing Date Year
+ 0x00, ///< 324 Module Manufacturing Date Week
+ 0x56, ///< 325 Module Serial Number A
+ 0x00, ///< 326 Module Serial Number B
+ 0x00, ///< 327 Module Serial Number C
+ 0x00, ///< 328 Module Serial Number D
+ 0x20, 0x20, 0x20, 0x20, 0x20, ///< 329 - 333 Module Part Number: Unused bytes coded as ASCII Blanks (0x20)
+ 0x20, 0x20, 0x20, 0x20, 0x20, ///< 334 - 338 Module Part Number
+ 0x20, 0x20, 0x20, 0x20, 0x20, ///< 339 - 343 Module Part Number
+ 0x20, 0x20, 0x20, 0x20, 0x20, ///< 344 - 348 Module Part Number
+ 0x00, ///< 349 Module Revision Code
+ 0x00, ///< 350 DRAM Manufacturer ID Code, Least Significant Byte
+ 0x00, ///< 351 DRAM Manufacturer ID Code, Most Significant Byte
+ 0x00 ///< 352 DRAM Stepping
+ ///< 353 - 511 are zeroes, no need to keep them, reduce BIOS image size
+};
+
+GLOBAL_REMOVE_IF_UNREFERENCED const UINT8 mLpddr4Ddp16Gb200b1rSpd[] = {
+ 0x23, ///< 0 384 SPD bytes used, 512 total
+ 0x10, ///< 1 SPD Revision 1.0
+ 0x11, ///< 2 DRAM Type: LPDDR4X SDRAM
+ 0x0E, ///< 3 Module Type: Not Hybrid (DRAM only) / Non-DIMM Solution (on-board DRAM)
+ 0x15, ///< 4 8 Banks, no bank groups, 8 Gb SDRAM density
+ 0x19, ///< 5 15 Rows, 10 Columns
+ 0x95, ///< 6 Non-Monolithic DRAM Device, 2 die, 2 Channels per package, Signal Loading Matrix 1
+ 0x08, ///< 7 SDRAM Optional Features: tMAW = 8192 * tREFI, Unlimited MAC
+ 0x00, ///< 8 SDRAM Thermal / Refresh options: Reserved
+ 0x40, ///< 9 Other SDRAM Optional Features: Post package repair supported, one row per bank group, Soft PPR not supported
+ 0x00, ///< 10 Reserved
+ 0x00, ///< 11 Module Nominal Voltage: Reserved
+ 0x02, ///< 12 Module Organization: 1 Ranks, x16 Device Width per Channel
+ 0x01, ///< 13 Module Memory Bus width: 1 Channels, 16 bits channel width, no ECC
+ 0x00, ///< 14 Module Thermal Sensor: none
+ 0x00, ///< 15 Extended Module Type: Reserved
+ 0x48, ///< 16 Signal Loading: Data/Strobe/Mask: 2 loads, CAC: 2 loads, CS: 1 load
+ 0x00, ///< 17 MTB = 0.125ns, FTB = 1 ps
+ 0x04, ///< 18 tCKAVGmin = 0.469 ns (LPDDR4-4267)
+ 0xFF, ///< 19 tCKAVGmax = 32.002 ns
+ 0x92, ///< 20 CAS Latencies supported (First Byte) : 14, 10, 6
+ 0x55, ///< 21 CAS Latencies supported (Second Byte): 28, 24, 20, 16
+ 0x00, ///< 22 CAS Latencies supported (Third Byte) :
+ 0x00, ///< 23 CAS Latencies supported (Fourth Byte):
+ 0x8C, ///< 24 Minimum CAS Latency (tAAmin) = 17.5 ns
+ 0x00, ///< 25 Read and Write Latency Set options: Write Latency Set A and DBI-Read Disabled
+ 0x90, ///< 26 Minimum RAS-to-CAS delay (tRCDmin) = 18 ns
+ 0xA8, ///< 27 Row precharge time for all banks (tRPab) = 21 ns
+ 0x90, ///< 28 Minimum row precharge time (tRPmin) = 18 ns
+ 0x90, ///< 29 tRFCab = 210 ns (16 Gb dual-channel die)
+ 0x06, ///< 30 tRFCab MSB
+ 0xD0, ///< 31 tRFCpb = 90 ns (16 Gb dual-channel die)
+ 0x02, ///< 32 tRFCpb MSB
+ 0, 0, 0, 0, 0, 0, 0, ///< 33 - 39
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 40 - 49
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 50 - 59
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 60 - 69
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 70 - 79
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 80 - 89
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 90 - 99
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 100 - 109
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 110 - 119
+ 0x00, ///< 120 FTB for Row precharge time per bank (tRPpb) = 18 ns
+ 0x00, ///< 121 FTB for Row precharge time for all banks (tRPab) = 21 ns
+ 0x00, ///< 122 FTB for Minimum RAS-to-CAS delay (tRCDmin) = 18 ns
+ 0x00, ///< 123 FTB for tAAmin = 17.5 ns
+ 0x7F, ///< 124 FTB for tCKAVGmax = 32.002 ns
+ 0xE1, ///< 125 FTB for tCKAVGmin = 0.469 ns (LPDDR4-4267)
+ 0x00, ///< 126 CRC A
+ 0x00, ///< 127 CRC B
+ 0, 0, ///< 128 - 129
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 130 - 139
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 140 - 149
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 150 - 159
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 160 - 169
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 170 - 179
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 180 - 189
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 190 - 199
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 200 - 209
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 210 - 219
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 220 - 229
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 230 - 239
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 240 - 249
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 250 - 259
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 260 - 269
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 270 - 279
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 280 - 289
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 290 - 299
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 300 - 309
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 310 - 319
+ 0x00, ///< 320 Module Manufacturer ID Code, Least Significant Byte
+ 0x00, ///< 321 Module Manufacturer ID Code, Most Significant Byte
+ 0x00, ///< 322 Module Manufacturing Location
+ 0x00, ///< 323 Module Manufacturing Date Year
+ 0x00, ///< 324 Module Manufacturing Date Week
+ 0x55, ///< 325 Module Serial Number A
+ 0x00, ///< 326 Module Serial Number B
+ 0x00, ///< 327 Module Serial Number C
+ 0x00, ///< 328 Module Serial Number D
+ 0x20, 0x20, 0x20, 0x20, 0x20, ///< 329 - 333 Module Part Number: Unused bytes coded as ASCII Blanks (0x20)
+ 0x20, 0x20, 0x20, 0x20, 0x20, ///< 334 - 338 Module Part Number
+ 0x20, 0x20, 0x20, 0x20, 0x20, ///< 339 - 343 Module Part Number
+ 0x20, 0x20, 0x20, 0x20, 0x20, ///< 344 - 348 Module Part Number
+ 0x00, ///< 349 Module Revision Code
+ 0x00, ///< 350 DRAM Manufacturer ID Code, Least Significant Byte
+ 0x00, ///< 351 DRAM Manufacturer ID Code, Most Significant Byte
+ 0x00 ///< 352 DRAM Stepping
+ ///< 353 - 511 are zeroes, no need to keep them, reduce BIOS image size
+};
+
+// LPDDR5 496b 12Gb die, QDP 1x16
+// Samsung K3LK2K20BM-BGCN
+// 5500, ??-??-??-??
+// 16 Banks, 4 bank groups, 12Gb SDRAM density
+// 16 Row bits, 10 Column bits
+// Non-Monolithic DRAM Device, 4 dies, 4 Channels per die,
+GLOBAL_REMOVE_IF_UNREFERENCED const UINT8 mLpddr5xQdp12Gb496bSpd[] = {
+ // ************************************
+ // Placeholder need correct SPD for LP5
+ // ************************************
+ 0x23, ///< 0 384 SPD bytes used, 512 total
+ 0x10, ///< 1 SPD Revision 1.0
+ 0x13, ///< 2 DRAM Type: LPDDR5 SDRAM
+ 0x0E, ///< 3 Module Type: Not Hybrid (DRAM only) / Non-DIMM Solution (on-board DRAM)
+ 0x88, ///< 4 8 Banks, no bank groups, 12 Gb SDRAM density
+ 0x29, ///< 5 17 Rows, 10 Columns
+ 0xB8, ///< 6 Non-Monolithic DRAM Device, 4 die, 4 Channels per package, Signal Loading Matrix 1
+ 0x08, ///< 7 SDRAM Optional Features: tMAW = 8192 * tREFI, Unlimited MAC
+ 0x00, ///< 8 SDRAM Thermal / Refresh options: Reserved
+ 0x40, ///< 9 Other SDRAM Optional Features: Post package repair supported, one row per bank group, Soft PPR not supported
+ 0x00, ///< 10 Reserved
+ 0x00, ///< 11 Module Nominal Voltage: Reserved
+ 0x02, ///< 12 Module Organization: 1 Ranks, x16 Device Width per Channel
+ 0x01, ///< 13 Module Memory Bus width: 1 Channels, 16 bits channel width, no ECC
+ 0x00, ///< 14 Module Thermal Sensor: none
+ 0x00, ///< 15 Extended Module Type: Reserved
+ 0x48, ///< 16 Signal Loading: Data/Strobe/Mask: 2 loads, CAC: 2 loads, CS: 1 load
+ 0x00, ///< 17 MTB = 0.125ns, FTB = 1 ps
+ 0x05, ///< 18 tCKAVGmin = 0.625 ns (LPDDR4-3200)
+ 0xFF, ///< 19 tCKAVGmax = 32.002 ns
+ 0x92, ///< 20 CAS Latencies supported (First Byte) : 14, 10, 6
+ 0x55, ///< 21 CAS Latencies supported (Second Byte): 28, 24, 20, 16
+ 0x00, ///< 22 CAS Latencies supported (Third Byte) :
+ 0x00, ///< 23 CAS Latencies supported (Fourth Byte):
+ 0x8C, ///< 24 Minimum CAS Latency (tAAmin) = 17.5 ns
+ 0x00, ///< 25 Read and Write Latency Set options: Write Latency Set A and DBI-Read Disabled
+ 0x90, ///< 26 Minimum RAS-to-CAS delay (tRCDmin) = 18 ns
+ 0xA8, ///< 27 Row precharge time for all banks (tRPab) = 21 ns
+ 0x90, ///< 28 Minimum row precharge time (tRPmin) = 18 ns
+ 0x90, ///< 29 tRFCab = 210 ns (16 Gb dual-channel die)
+ 0x06, ///< 30 tRFCab MSB
+ 0xD0, ///< 31 tRFCpb = 90 ns (16 Gb dual-channel die)
+ 0x02, ///< 32 tRFCpb MSB
+ 0, 0, 0, 0, 0, 0, 0, ///< 33 - 39
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 40 - 49
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 50 - 59
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 60 - 69
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 70 - 79
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 80 - 89
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 90 - 99
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 100 - 109
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 110 - 119
+ 0x00, ///< 120 FTB for Row precharge time per bank (tRPpb) = 18 ns
+ 0x00, ///< 121 FTB for Row precharge time for all banks (tRPab) = 21 ns
+ 0x00, ///< 122 FTB for Minimum RAS-to-CAS delay (tRCDmin) = 18 ns
+ 0x00, ///< 123 FTB for tAAmin = 17.5 ns
+ 0x7F, ///< 124 FTB for tCKAVGmax = 32.002 ns
+ 0x00, ///< 125 FTB for tCKAVGmin = 0.469 ns (LPDDR4-4267)
+ 0x00, ///< 126 CRC A
+ 0x00, ///< 127 CRC B
+ 0, 0, ///< 128 - 129
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 130 - 139
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 140 - 149
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 150 - 159
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 160 - 169
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 170 - 179
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 180 - 189
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 190 - 199
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 200 - 209
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 210 - 219
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 220 - 229
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 230 - 239
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 240 - 249
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 250 - 259
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 260 - 269
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 270 - 279
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 280 - 289
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 290 - 299
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 300 - 309
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 310 - 319
+ 0x00, ///< 320 Module Manufacturer ID Code, Least Significant Byte
+ 0x00, ///< 321 Module Manufacturer ID Code, Most Significant Byte
+ 0x00, ///< 322 Module Manufacturing Location
+ 0x00, ///< 323 Module Manufacturing Date Year
+ 0x00, ///< 324 Module Manufacturing Date Week
+ 0x20, ///< 325 Module ID: Module Serial Number
+ 0x00, ///< 326 Module Serial Number B
+ 0x00, ///< 327 Module Serial Number C
+ 0x00, ///< 328 Module Serial Number D
+ 0x20, 0x20, 0x20, 0x20, 0x20, ///< 329 - 333 Module Part Number: Unused bytes coded as ASCII Blanks (0x20)
+ 0x20, 0x20, 0x20, 0x20, 0x20, ///< 334 - 338 Module Part Number
+ 0x20, 0x20, 0x20, 0x20, 0x20, ///< 339 - 343 Module Part Number
+ 0x20, 0x20, 0x20, 0x20, 0x20, ///< 344 - 348 Module Part Number
+ 0x00, ///< 349 Module Revision Code
+ 0x00, ///< 350 DRAM Manufacturer ID Code, Least Significant Byte
+ 0x00, ///< 351 DRAM Manufacturer ID Code, Most Significant Byte
+ 0x00 ///< 352 DRAM Stepping
+ ///< 353 - 511 are zeroes, no need to keep them, reduce BIOS image size
+};
+
+// LPDDR4X 200b 16Gb die, DDP, 2 channel per die, 2x8
+// Samsung K4U6E3S4AA-MGCL
+// 4267, 36-39-39-90
+// 1 rank per channel, 2 SDRAMs per channel, 2x8GB = 16GB total per channel
+GLOBAL_REMOVE_IF_UNREFERENCED const UINT8 mLpddr4xDdp16Gb200bSpd[] = {
+ 0x23, ///< 0 384 SPD bytes used, 512 total
+ 0x10, ///< 1 SPD Revision 1.0
+ 0x11, ///< 2 DRAM Type: LPDDR4x SDRAM
+ 0x0E, ///< 3 Module Type: Not Hybrid (DRAM only) / Non-DIMM Solution (on-board DRAM)
+ 0x15, ///< 4 8 Banks, no bank groups, 16 Gb SDRAM density
+ 0x19, ///< 5 5 15 Rows, 10 Columns
+ 0x94, ///< 6 Non-Monolithic DRAM Device, 2 die, 1 Channels per package, Signal Loading Matrix 1
+ 0x08, ///< 7 SDRAM Optional Features: tMAW = 8192 * tREFI, Unlimited MAC
+ 0x00, ///< 8 SDRAM Thermal / Refresh options: Reserved
+ 0x40, ///< 9 Other SDRAM Optional Features: Post package repair supported, one row per bank group, Soft PPR not supported
+ 0x00, ///< 10 Reserved
+ 0x00, ///< 11 Module Nominal Voltage: Reserved
+ 0x02, ///< 12 Module Organization: 1 Ranks, x16 Device Width per Channel
+ 0x01, ///< 13 Module Memory Bus width: 1 Channels, 16 bits channel width, no ECC
+ 0x00, ///< 14 Module Thermal Sensor: none
+ 0x00, ///< 15 Extended Module Type: Reserved
+ 0x48, ///< 16 Signal Loading: Data/Strobe/Mask: 2 loads, CAC: 2 loads, CS: 1 load
+ 0x00, ///< 17 MTB = 0.125ns, FTB = 1 ps
+ 0x05, ///< 18 tCKAVGmin = 0.625 ns (LPDDR4-3200)
+ 0xFF, ///< 19 tCKAVGmax = 32.002 ns
+ 0x92, ///< 20 CAS Latencies supported (First Byte) : 14, 10, 6
+ 0x55, ///< 21 CAS Latencies supported (Second Byte): 28, 24, 20, 16
+ 0x00, ///< 22 CAS Latencies supported (Third Byte) :
+ 0x00, ///< 23 CAS Latencies supported (Fourth Byte):
+ 0x8C, ///< 24 Minimum CAS Latency (tAAmin) = 17.5 ns
+ 0x00, ///< 25 Read and Write Latency Set options: Write Latency Set A and DBI-Read Disabled
+ 0x90, ///< 26 Minimum RAS-to-CAS delay (tRCDmin) = 18 ns
+ 0xA8, ///< 27 Row precharge time for all banks (tRPab) = 21 ns
+ 0x90, ///< 28 Minimum row precharge time (tRPmin) = 18 ns
+ 0x90, ///< 29 tRFCab = 210 ns (16 Gb dual-channel die)
+ 0x06, ///< 30 tRFCab MSB
+ 0xD0, ///< 31 tRFCpb = 90 ns (16 Gb dual-channel die)
+ 0x02, ///< 32 tRFCpb MSB
+ 0, 0, 0, 0, 0, 0, 0, ///< 33 - 39
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 40 - 49
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 50 - 59
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 60 - 69
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 70 - 79
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 80 - 89
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 90 - 99
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 100 - 109
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 110 - 119
+ 0x00, ///< 120 FTB for Row precharge time per bank (tRPpb) = 18 ns
+ 0x00, ///< 121 FTB for Row precharge time for all banks (tRPab) = 21 ns
+ 0x00, ///< 122 FTB for Minimum RAS-to-CAS delay (tRCDmin) = 18 ns
+ 0x00, ///< 123 FTB for tAAmin = 17.5 ns
+ 0x7F, ///< 124 FTB for tCKAVGmax = 32.002 ns
+ 0x00, ///< 125 FTB for tCKAVGmin = 0.469 ns (LPDDR4-4267)
+ 0x00, ///< 126 CRC A
+ 0x00, ///< 127 CRC B
+ 0, 0, ///< 128 - 129
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 130 - 139
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 140 - 149
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 150 - 159
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 160 - 169
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 170 - 179
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 180 - 189
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 190 - 199
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 200 - 209
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 210 - 219
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 220 - 229
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 230 - 239
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 240 - 249
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 250 - 259
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 260 - 269
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 270 - 279
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 280 - 289
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 290 - 299
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 300 - 309
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 310 - 319
+ 0x00, ///< 320 Module Manufacturer ID Code, Least Significant Byte
+ 0x00, ///< 321 Module Manufacturer ID Code, Most Significant Byte
+ 0x00, ///< 322 Module Manufacturing Location
+ 0x00, ///< 323 Module Manufacturing Date Year
+ 0x00, ///< 324 Module Manufacturing Date Week
+ 0x20, ///< 325 Module ID: Module Serial Number
+ 0x00, ///< 326 Module Serial Number B
+ 0x00, ///< 327 Module Serial Number C
+ 0x00, ///< 328 Module Serial Number D
+ 0x20, 0x20, 0x20, 0x20, 0x20, ///< 329 - 333 Module Part Number: Unused bytes coded as ASCII Blanks (0x20)
+ 0x20, 0x20, 0x20, 0x20, 0x20, ///< 334 - 338 Module Part Number
+ 0x20, 0x20, 0x20, 0x20, 0x20, ///< 339 - 343 Module Part Number
+ 0x20, 0x20, 0x20, 0x20, 0x20, ///< 344 - 348 Module Part Number
+ 0x00, ///< 349 Module Revision Code
+ 0x00, ///< 350 DRAM Manufacturer ID Code, Least Significant Byte
+ 0x00, ///< 351 DRAM Manufacturer ID Code, Most Significant Byte
+ 0x00 ///< 352 DRAM Stepping
+ ///< 353 - 511 are zeroes, no need to keep them, reduce BIOS image size
+};
+
+// LPDDR4X 200b 16Gb die, 2 channel per die, 2x8
+// Micron MT53E1G32D4NQ-046
+// 3200
+GLOBAL_REMOVE_IF_UNREFERENCED const UINT8 mLpddr4xQdp16Gb200bSpd[] = {
+ 0x23, ///< 0 384 SPD bytes used, 512 total
+ 0x12, ///< 1 SPD Revision 1.0
+ 0x11, ///< 2 DRAM Type: LPDDR4x SDRAM
+ 0x0E, ///< 3 Module Type: Not Hybrid (DRAM only) / Non-DIMM Solution (on-board DRAM)
+ 0x15, ///< 4 8 Banks, no bank groups, 16 Gb SDRAM density
+ 0x21, ///< 5 5 15 Rows, 10 Columns
+ 0xB1, ///< 6 Non-Monolithic DRAM Device, 2 die, 1 Channels per package, Signal Loading Matrix 1
+ 0x08, ///< 7 SDRAM Optional Features: tMAW = 8192 * tREFI, Unlimited MAC
+ 0x00, ///< 8 SDRAM Thermal / Refresh options: Reserved
+ 0x40, ///< 9 Other SDRAM Optional Features: Post package repair supported, one row per bank group, Soft PPR not supported
+ 0x00, ///< 10 Reserved
+ 0x00, ///< 11 Module Nominal Voltage: Reserved
+ 0x0A, ///< 12 Module Organization: 1 Ranks, x16 Device Width per Channel
+ 0x01, ///< 13 Module Memory Bus width: 1 Channels, 16 bits channel width, no ECC
+ 0x00, ///< 14 Module Thermal Sensor: none
+ 0x00, ///< 15 Extended Module Type: Reserved
+ 0x48, ///< 16 Signal Loading: Data/Strobe/Mask: 2 loads, CAC: 2 loads, CS: 1 load
+ 0x00, ///< 17 MTB = 0.125ns, FTB = 1 ps
+ 0x04, ///< 18 tCKAVGmin = 0.625 ns (LPDDR4-3200)
+ 0x00, ///< 19 tCKAVGmax = 32.002 ns
+ 0xD2, ///< 20 CAS Latencies supported (First Byte) : 14, 10, 6
+ 0x54, ///< 21 CAS Latencies supported (Second Byte): 28, 24, 20, 16
+ 0x01, ///< 22 CAS Latencies supported (Third Byte) :
+ 0x00, ///< 23 CAS Latencies supported (Fourth Byte):
+ 0x87, ///< 24 Minimum CAS Latency (tAAmin) = 17.5 ns
+ 0x40, ///< 25 Read and Write Latency Set options: Write Latency Set A and DBI-Read Disabled
+ 0x90, ///< 26 Minimum RAS-to-CAS delay (tRCDmin) = 18 ns
+ 0xA8, ///< 27 Row precharge time for all banks (tRPab) = 21 ns
+ 0x90, ///< 28 Minimum row precharge time (tRPmin) = 18 ns
+ 0xC0, ///< 29 tRFCab = 210 ns (16 Gb dual-channel die)
+ 0x08, ///< 30 tRFCab MSB
+ 0x60, ///< 31 tRFCpb = 90 ns (16 Gb dual-channel die)
+ 0x04, ///< 32 tRFCpb MSB
+ 0, 0, 0, 0, 0, 0, 0, ///< 33 - 39
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 40 - 49
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 50 - 59
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 60 - 69
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 70 - 79
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 80 - 89
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 90 - 99
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 100 - 109
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 110 - 119
+ 0x00, ///< 120 FTB for Row precharge time per bank (tRPpb) = 18 ns
+ 0x00, ///< 121 FTB for Row precharge time for all banks (tRPab) = 21 ns
+ 0x00, ///< 122 FTB for Minimum RAS-to-CAS delay (tRCDmin) = 18 ns
+ 0xE4, ///< 123 FTB for tAAmin = 17.5 ns
+ 0x00, ///< 124 FTB for tCKAVGmax = 32.002 ns
+ 0x60, ///< 125 FTB for tCKAVGmin = 0.469 ns (LPDDR4-4267)
+ 0xA1, ///< 126 CRC A
+ 0xAC, ///< 127 CRC B
+ 0, 0, ///< 128 - 129
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 130 - 139
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 140 - 149
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 150 - 159
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 160 - 169
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 170 - 179
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 180 - 189
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 190 - 199
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 200 - 209
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 210 - 219
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 220 - 229
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 230 - 239
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 240 - 249
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 250 - 259
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 260 - 269
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 270 - 279
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 280 - 289
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 290 - 299
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 300 - 309
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 310 - 319
+ 0x00, ///< 320 Module Manufacturer ID Code, Least Significant Byte
+ 0x00, ///< 321 Module Manufacturer ID Code, Most Significant Byte
+ 0x00, ///< 322 Module Manufacturing Location
+ 0x00, ///< 323 Module Manufacturing Date Year
+ 0x00, ///< 324 Module Manufacturing Date Week
+ 0x20, ///< 325 Module ID: Module Serial Number
+ 0x00, ///< 326 Module Serial Number B
+ 0x00, ///< 327 Module Serial Number C
+ 0x00, ///< 328 Module Serial Number D
+ 0x20, 0x20, 0x20, 0x20, 0x20, ///< 329 - 333 Module Part Number: Unused bytes coded as ASCII Blanks (0x20)
+ 0x20, 0x20, 0x20, 0x20, 0x20, ///< 334 - 338 Module Part Number
+ 0x20, 0x20, 0x20, 0x20, 0x20, ///< 339 - 343 Module Part Number
+ 0x20, 0x20, 0x20, 0x20, 0x20, ///< 344 - 348 Module Part Number
+ 0x00, ///< 349 Module Revision Code
+ 0x00, ///< 350 DRAM Manufacturer ID Code, Least Significant Byte
+ 0x00, ///< 351 DRAM Manufacturer ID Code, Most Significant Byte
+ 0x00 ///< 352 DRAM Stepping
+ ///< 353 - 511 are zeroes, no need to keep them, reduce BIOS image size
+};
+
+GLOBAL_REMOVE_IF_UNREFERENCED const UINT8 mDdr5Spd_1Rx8[] = {
+ 0x30,///< 0 1024 SPD bytes total
+ 0x08,///< 1 SPD Revision 0.8
+ 0x12,///< 2 DRAM Type: DDR5 SDRAM
+ 0x03,///< 3 Module Type: Not Hybrid (DRAM only) / SO-DIMM Solution
+ 0x04,///< 4 Monolithic SDRAM, 16 Gb SDRAM density
+ 0x00,///< 5 16 Rows, 10 Columns
+ 0x20,///< 6 x8 SDRAM I/O Width
+ 0x62,///< 7 8 Bank Groups, 4 Banks per Bank Group
+ 0x00,///< 8 Secondary SDRAM Density and Package
+ 0x00,///< 9 Secondary SDRAM Addressing
+ 0x00,///< 10 Secondary SDRAM I/O Width
+ 0x00,///< 11 Secondary BankGroups and Banks per Bank Group
+ 0x60,///< 12 PPR Supported, One row per bank group, Soft PPR Supported
+ 0x00,///< 13 Commercial Temperature Grade, 0 to 85 C
+ 0x00,///< 14 Reserved
+ 0x00,///< 15 Reserved
+ 0x00,///< 16 SDRAM Nominal Voltage VDD: 1.1V
+ 0x00,///< 17 SDRAM Nominal Voltage VDDQ: 1.1V
+ 0x00,///< 18 SDRAM Nominal Voltage VPP: 1.8V
+ 0x00,///< 19 Reserved
+ 0xA1,///< 20 tCKAVGmin LSB
+ 0x01,///< 21 tCKAVGmin MSB
+ 0xE8,///< 22 tCKAVGmax LSB
+ 0x03,///< 23 tCKAVGmax MSB
+ 0x72,///< 24 CAS Latencies supported (First Byte) : 32, 30, 28, 22
+ 0x15,///< 25 CAS Latencies supported (Second Byte): 44, 40, 36
+ 0x00,///< 26 CAS Latencies supported (Third Byte) :
+ 0x00,///< 27 CAS Latencies supported (Fourth Byte):
+ 0x00,///< 28 CAS Latencies supported (Fifth Byte) :
+ 0x00,///< 29 Reserved
+ 0x1E,///< 30 Minimum CAS Latency (tAAmin) LSB
+ 0x41,///< 31 Minimum CAS Latency (tAAmin) MSB
+ 0x1E,///< 32 Minimum RAS-to-CAS delay (tRCDmin) LSB
+ 0x41,///< 33 Minimum RAS-to-CAS delay (tRCDmin) MSB
+ 0x1E,///< 34 Minimum Row Precharge delay (tRPmin) LSB
+ 0x41,///< 35 Minimum Row Precharge delay (tRPmin) MSB
+ 0x00,///< 36 Minimum Active to Precharge delay (tRASmin) LSB
+ 0x7D,///< 37 Minimum Active to Precharge delay (tRASmin) MSB
+ 0x1E,///< 38 Minimum Active to Active/Refresh delay (tRCmin) LSB
+ 0xBE,///< 39 Minimum Active to Active/Refresh delay (tRCmin) MSB
+ 0x30,///< 40 Minimum Write Recovery time (tWRmin) LSB
+ 0x75,///< 41 Minimum Write Recovery time (tWRmin) MSB
+ 0x27,///< 42 Refresh Recovery Delay (tRFC1min) LSB
+ 0x01,///< 43 Refresh Recovery Delay (tRFC1min) MSB
+ 0xA0,///< 44 Refresh Recovery Delay (tRFC2min) MSB
+ 0x00,///< 45 Refresh Recovery Delay (tRFC2min) MSB
+ 0x82,///< 46 Refresh Recovery Delay (tRFCsbmin) MSB
+ 0x00,///< 47 Refresh Recovery Delay (tRFCsbmin) MSB
+ 0, 0, ///< 48 - 49
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 50 - 59
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 60 - 69
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 70 - 79
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 80 - 89
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 90 - 99
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 100 - 109
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 110 - 119
+ 0, 0, 0, 0, 0, 0, ///< 120 - 125
+ 0x47, ///< 126 CRC Bytes 0 - 127 LSB
+ 0xAE, ///< 127 CRC Bytes 0 - 127 MSB
+ 0, 0, ///< 128 - 129
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 130 - 139
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 140 - 149
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 150 - 159
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 160 - 169
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 170 - 179
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 180 - 189
+ 0, 0, ///< 190 - 191
+ 0x08, ///< 192 SPD Revision for Module Information: 0.8
+ 0x00, ///< 193 Reserved
+ 0xC2, ///< 194 SPD Manufacturer ID First Byte
+ 0xC4, ///< 195 SPD Manufacturer ID Second Byte
+ 0x80, ///< 196 SPD Device Type
+ 0x00, ///< 197 SPD Device Revision
+ 0x80, ///< 198 PMIC0 Manufacturer ID First Byte
+ 0xB3, ///< 199 PMIC0 Manufacturer ID Second Byte
+ 0x80, ///< 200 PMIC0 Device Type
+ 0x11, ///< 201 PMIC0 Device Revision
+ 0, 0, 0, 0, ///< 202 - 205 PMIC1
+ 0, 0, 0, 0, ///< 206 - 209 PMIC2
+ 0x80, ///< 210 Thermal Sensors Manufacturer ID First Byte
+ 0xB3, ///< 211 Thermal Sensors Manufacturer ID First Byte
+ 0x80, ///< 212 Thermal Sensors Device Type
+ 0x11, ///< 213 Thermal Sensors Device Revision
+ 0, 0, 0, 0, 0, 0, ///< 214 - 219
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 220 - 229
+ 0x0F, ///< 230 Module Nominal Height
+ 0x10, ///< 231 Module Nominal Thickness
+ 0x00, ///< 232 Reference Raw Card Used
+ 0x01, ///< 233 1 Row of DRAM on Module
+ 0x01, ///< 234 1 Rank, 8 bits SDRAM data width per channel
+ 0x22, ///< 235 2 Channels per DIMM, 32 bits per Channel
+ 0, 0, 0, 0, ///< 236 - 239
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 240 - 249
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 250 - 259
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 260 - 269
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 270 - 279
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 280 - 289
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 290 - 299
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 300 - 309
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 310 - 319
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 320 - 329
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 330 - 339
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 340 - 349
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 350 - 359
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 360 - 369
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 370 - 379
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 380 - 389
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 390 - 399
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 400 - 409
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 410 - 419
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 420 - 429
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 430 - 439
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ///< 440 - 445
+ 0x9C, ///< 446 CRC for Bytes 128 - 253 LSB
+ 0xAD, ///< 447 CRC for Bytes 128 - 253 MSB
+ 0, 0, ///< 448 - 449
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 450 - 459
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 460 - 469
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 470 - 479
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 480 - 489
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 490 - 499
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 500 - 509
+ 0, 0, ///< 510 - 511
+ 0x80, ///< 512 Module Manufacturer ID First Byte
+ 0xAD, ///< 513 Module Manufacturer ID Second Byte
+ 0x00, ///< 514 Module Manufacturing Location
+ 0, 0, ///< 515 - 516 Module Manufacturing Date
+ 0, 0, 0, 0, ///< 517 - 520 Module Serial Number
+ 0x54, 0x4D, 0x43, 0x41, 0x32, 0x47, 0x53, 0x36, 0x41, 0x4A, ///< 521 - 530
+ 0x52, 0x38, 0x43, 0x2D, 0x45, 0x42, 0x20, 0x20, 0x20, 0x20, ///< 531 - 540
+ 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, ///< 541 - 550
+ 0x00, ///< 551 Module Revision Code
+ 0x80, ///< 552 DRAM Manufacturer ID First Byte
+ 0xAD ///< 553 DRAM Manufacturer ID Second Byte
+ ///< 554 - 1023 are zeroes, no need to keep them, save PEI FV size
+};
+
+GLOBAL_REMOVE_IF_UNREFERENCED const UINT8 mDdr5Spd_2Rx8[] = {
+ 0x30,///< 0 1024 SPD bytes total
+ 0x08,///< 1 SPD Revision 0.8
+ 0x12,///< 2 DRAM Type: DDR5 SDRAM
+ 0x03,///< 3 Module Type: Not Hybrid (DRAM only) / SO-DIMM Solution
+ 0x04,///< 4 Monolithic SDRAM, 16 Gb SDRAM density
+ 0x00,///< 5 16 Rows, 10 Columns
+ 0x20,///< 6 x8 SDRAM I/O Width
+ 0x62,///< 7 8 Bank Groups, 4 Banks per Bank Group
+ 0x00,///< 8 Secondary SDRAM Density and Package
+ 0x00,///< 9 Secondary SDRAM Addressing
+ 0x00,///< 10 Secondary SDRAM I/O Width
+ 0x00,///< 11 Secondary BankGroups and Banks per Bank Group
+ 0x60,///< 12 PPR Supported, One row per bank group, Soft PPR Supported
+ 0x00,///< 13 Commercial Temperature Grade, 0 to 85 C
+ 0x00,///< 14 Reserved
+ 0x00,///< 15 Reserved
+ 0x00,///< 16 SDRAM Nominal Voltage VDD: 1.1V
+ 0x00,///< 17 SDRAM Nominal Voltage VDDQ: 1.1V
+ 0x00,///< 18 SDRAM Nominal Voltage VPP: 1.8V
+ 0x00,///< 19 Reserved
+ 0xA1,///< 20 tCKAVGmin LSB
+ 0x01,///< 21 tCKAVGmin MSB
+ 0xE8,///< 22 tCKAVGmax LSB
+ 0x03,///< 23 tCKAVGmax MSB
+ 0x72,///< 24 CAS Latencies supported (First Byte) : 32, 30, 28, 22
+ 0x15,///< 25 CAS Latencies supported (Second Byte): 44, 40, 36
+ 0x00,///< 26 CAS Latencies supported (Third Byte) :
+ 0x00,///< 27 CAS Latencies supported (Fourth Byte):
+ 0x00,///< 28 CAS Latencies supported (Fifth Byte) :
+ 0x00,///< 29 Reserved
+ 0x1E,///< 30 Minimum CAS Latency (tAAmin) LSB
+ 0x41,///< 31 Minimum CAS Latency (tAAmin) MSB
+ 0x1E,///< 32 Minimum RAS-to-CAS delay (tRCDmin) LSB
+ 0x41,///< 33 Minimum RAS-to-CAS delay (tRCDmin) MSB
+ 0x1E,///< 34 Minimum Row Precharge delay (tRPmin) LSB
+ 0x41,///< 35 Minimum Row Precharge delay (tRPmin) MSB
+ 0x00,///< 36 Minimum Active to Precharge delay (tRASmin) LSB
+ 0x7D,///< 37 Minimum Active to Precharge delay (tRASmin) MSB
+ 0x1E,///< 38 Minimum Active to Active/Refresh delay (tRCmin) LSB
+ 0xBE,///< 39 Minimum Active to Active/Refresh delay (tRCmin) MSB
+ 0x30,///< 40 Minimum Write Recovery time (tWRmin) LSB
+ 0x75,///< 41 Minimum Write Recovery time (tWRmin) MSB
+ 0x27,///< 42 Refresh Recovery Delay (tRFC1min) LSB
+ 0x01,///< 43 Refresh Recovery Delay (tRFC1min) MSB
+ 0xA0,///< 44 Refresh Recovery Delay (tRFC2min) MSB
+ 0x00,///< 45 Refresh Recovery Delay (tRFC2min) MSB
+ 0x82,///< 46 Refresh Recovery Delay (tRFCsbmin) MSB
+ 0x00,///< 47 Refresh Recovery Delay (tRFCsbmin) MSB
+ 0, 0, ///< 48 - 49
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 50 - 59
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 60 - 69
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 70 - 79
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 80 - 89
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 90 - 99
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 100 - 109
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 110 - 119
+ 0, 0, 0, 0, 0, 0, ///< 120 - 125
+ 0x47, ///< 126 CRC Bytes 0 - 127 LSB
+ 0xAE, ///< 127 CRC Bytes 0 - 127 MSB
+ 0, 0, ///< 128 - 129
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 130 - 139
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 140 - 149
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 150 - 159
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 160 - 169
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 170 - 179
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 180 - 189
+ 0, 0, ///< 190 - 191
+ 0x08, ///< 192 SPD Revision for Module Information: 0.8
+ 0x00, ///< 193 Reserved
+ 0xC2, ///< 194 SPD Manufacturer ID First Byte
+ 0xC4, ///< 195 SPD Manufacturer ID Second Byte
+ 0x80, ///< 196 SPD Device Type
+ 0x00, ///< 197 SPD Device Revision
+ 0x80, ///< 198 PMIC0 Manufacturer ID First Byte
+ 0xB3, ///< 199 PMIC0 Manufacturer ID Second Byte
+ 0x80, ///< 200 PMIC0 Device Type
+ 0x11, ///< 201 PMIC0 Device Revision
+ 0, 0, 0, 0, ///< 202 - 205 PMIC1
+ 0, 0, 0, 0, ///< 206 - 209 PMIC2
+ 0x80, ///< 210 Thermal Sensors Manufacturer ID First Byte
+ 0xB3, ///< 211 Thermal Sensors Manufacturer ID First Byte
+ 0x80, ///< 212 Thermal Sensors Device Type
+ 0x11, ///< 213 Thermal Sensors Device Revision
+ 0, 0, 0, 0, 0, 0, ///< 214 - 219
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 220 - 229
+ 0x0F, ///< 230 Module Nominal Height
+ 0x10, ///< 231 Module Nominal Thickness
+ 0x00, ///< 232 Reference Raw Card Used
+ 0x01, ///< 233 1 Row of DRAM on Module
+ 0x08, ///< 234 Module Organization: 2 Package Ranks; symmetrical rank mix
+ 0x22, ///< 235 2 Channels per DIMM, 32 bits per Channel
+ 0, 0, 0, 0, ///< 236 - 239
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 240 - 249
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 250 - 259
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 260 - 269
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 270 - 279
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 280 - 289
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 290 - 299
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 300 - 309
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 310 - 319
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 320 - 329
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 330 - 339
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 340 - 349
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 350 - 359
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 360 - 369
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 370 - 379
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 380 - 389
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 390 - 399
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 400 - 409
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 410 - 419
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 420 - 429
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 430 - 439
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ///< 440 - 445
+ 0x9C, ///< 446 CRC for Bytes 128 - 253 LSB
+ 0xAD, ///< 447 CRC for Bytes 128 - 253 MSB
+ 0, 0, ///< 448 - 449
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 450 - 459
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 460 - 469
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 470 - 479
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 480 - 489
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 490 - 499
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 500 - 509
+ 0, 0, ///< 510 - 511
+ 0x80, ///< 512 Module Manufacturer ID First Byte
+ 0xAD, ///< 513 Module Manufacturer ID Second Byte
+ 0x00, ///< 514 Module Manufacturing Location
+ 0, 0, ///< 515 - 516 Module Manufacturing Date
+ 0, 0, 0, 0, ///< 517 - 520 Module Serial Number
+ 0x54, 0x4D, 0x43, 0x41, 0x32, 0x47, 0x53, 0x36, 0x41, 0x4A, ///< 521 - 530
+ 0x52, 0x38, 0x43, 0x2D, 0x45, 0x42, 0x20, 0x20, 0x20, 0x20, ///< 531 - 540
+ 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, ///< 541 - 550
+ 0x00, ///< 551 Module Revision Code
+ 0x80, ///< 552 DRAM Manufacturer ID First Byte
+ 0xAD ///< 553 DRAM Manufacturer ID Second Byte
+ ///< 554 - 1023 are zeroes, no need to keep them, save PEI FV size
+};
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Library/PeiGetFvInfoLib/PeiGetFvInfoLib.c b/Platform/Intel/AlderlakeOpenBoardPkg/Library/PeiGetFvInfoLib/PeiGetFvInfoLib.c
new file mode 100644
index 0000000000..eb6e0a0f4b
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Library/PeiGetFvInfoLib/PeiGetFvInfoLib.c
@@ -0,0 +1,89 @@
+/** @file
+ Helper Library for PEI Graphics PEIM
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Library/PeiGetFvInfoLib.h>
+#include <Ppi/FirmwareVolume.h>
+#include <Pi/PiPeiCis.h>
+#include <Core/Pei/PeiMain.h>
+#include <Library/PeiServicesLib.h>
+#include <Library/HobLib.h>
+
+/**
+ PeiGetSectionFromFv finds the file in FV and gets file Address and Size
+
+ @param[in] NameGuid - File GUID
+ @param[out] Address - Pointer to the File Address
+ @param[out] Size - Pointer to File Size
+
+ @retval EFI_SUCCESS Successfull in reading the section from FV
+ @retval EFI_NOT_FOUND File not found
+**/
+EFI_STATUS
+EFIAPI
+PeiGetSectionFromFv (
+ IN CONST EFI_GUID NameGuid,
+ OUT VOID **Address,
+ OUT UINT32 *Size
+ )
+{
+ EFI_STATUS Status;
+ EFI_PEI_FIRMWARE_VOLUME_PPI *FvPpi;
+ EFI_FV_FILE_INFO FvFileInfo;
+ PEI_CORE_FV_HANDLE *CoreFvHandle;
+ EFI_PEI_FILE_HANDLE FileHandle;
+ EFI_GUID *FileGuid;
+ EFI_COMMON_SECTION_HEADER *Section;
+ EFI_HOB_GUID_TYPE *GuidHob;
+ VOID *HobData;
+
+ Status = PeiServicesLocatePpi(
+ &gEfiFirmwareFileSystem2Guid,
+ 0,
+ NULL,
+ (VOID **)&FvPpi
+ );
+ ASSERT_EFI_ERROR(Status);
+
+ GuidHob = GetFirstGuidHob (&gPlatformInitFvLocationGuid);
+ if (GuidHob != NULL) {
+ HobData = *(VOID **)GET_GUID_HOB_DATA(GuidHob);
+ CoreFvHandle = (PEI_CORE_FV_HANDLE *) HobData;
+
+ //
+ // File typically resides in current FV or previous FV, so searching both of them.
+ //
+ Status = FvPpi->FindFileByName (FvPpi, &NameGuid, &CoreFvHandle->FvHandle, &FileHandle);
+
+ if (!EFI_ERROR(Status) && FileHandle != NULL) {
+
+ DEBUG((DEBUG_INFO, "Find SectionByType \n"));
+
+ Status = FvPpi->FindSectionByType(FvPpi, EFI_SECTION_RAW, FileHandle, (VOID **)&FileGuid);
+ if (!EFI_ERROR(Status)) {
+
+ DEBUG((DEBUG_INFO, "GetFileInfo \n"));
+
+ Status = FvPpi->GetFileInfo(FvPpi, FileHandle, &FvFileInfo);
+ Section = (EFI_COMMON_SECTION_HEADER *)FvFileInfo.Buffer;
+
+ if (IS_SECTION2(Section)) {
+ ASSERT(SECTION2_SIZE(Section) > 0x00FFFFFF);
+ *Size = SECTION2_SIZE(Section) - sizeof (EFI_COMMON_SECTION_HEADER2);
+ *Address = ((UINT8 *)Section + sizeof (EFI_COMMON_SECTION_HEADER2));
+ } else {
+ *Size = SECTION_SIZE(Section) - sizeof (EFI_COMMON_SECTION_HEADER);
+ *Address = ((UINT8 *)Section + sizeof (EFI_COMMON_SECTION_HEADER));
+ }
+ return EFI_SUCCESS;
+ }
+ }
+ } else {
+ DEBUG ((DEBUG_INFO, "Hob not found\n"));
+ }
+ return EFI_NOT_FOUND;
+}
\ No newline at end of file
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Library/PeiGetFvInfoLib/PeiGetFvInfoLib.inf b/Platform/Intel/AlderlakeOpenBoardPkg/Library/PeiGetFvInfoLib/PeiGetFvInfoLib.inf
new file mode 100644
index 0000000000..1701fb15fe
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Library/PeiGetFvInfoLib/PeiGetFvInfoLib.inf
@@ -0,0 +1,34 @@
+### @file
+# Component description file for PeiGetFvInfo library.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+###
+
+[Defines]
+ INF_VERSION = 0x00010017
+ BASE_NAME = PeiGetFvInfoLib
+ FILE_GUID = C2584BE4-2CCD-418C-9205-A2031CE75861
+ VERSION_STRING = 1.0
+ MODULE_TYPE = PEIM
+ LIBRARY_CLASS = PeiGetFvInfoLib
+
+[LibraryClasses]
+ BaseMemoryLib
+ BaseLib
+ DebugLib
+ DebugPrintErrorLevelLib
+ HobLib
+ PeiServicesLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ AlderlakeOpenBoardPkg/OpenBoardPkg.dec
+
+[Sources]
+ PeiGetFvInfoLib.c
+
+[Guids]
+ gPlatformInitFvLocationGuid ## CONSUMES
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Library/PeiReportFvLib/PeiReportFvLib.c b/Platform/Intel/AlderlakeOpenBoardPkg/Library/PeiReportFvLib/PeiReportFvLib.c
new file mode 100644
index 0000000000..fa6dc70e6b
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Library/PeiReportFvLib/PeiReportFvLib.c
@@ -0,0 +1,372 @@
+/** @file
+
+ Source code file for the Report Firmware Volume (FV) library
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Base.h>
+#include <PiPei.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/HobLib.h>
+#include <Library/PcdLib.h>
+#include <Library/PeiServicesLib.h>
+#include <Library/ReportFvLib.h>
+#include <Guid/FirmwareFileSystem2.h>
+#include <Ppi/FirmwareVolumeInfo.h>
+#include <Ppi/ReadOnlyVariable2.h>
+#include <Library/PcdLib.h>
+#include <Pi/PiStatusCode.h>
+#include <Library/MtrrLib.h>
+#include <Library/ReportStatusCodeLib.h>
+
+EFI_STATUS
+EFIAPI
+InstallFvExtendedPostMemoryCallback (
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
+ IN VOID *Ppi
+ );
+
+EFI_STATUS
+EFIAPI
+InstallFvExtendedAdvancedCallback (
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
+ IN VOID *Ppi
+ );
+
+/**
+ Notify list for FV installation to the memory for Extended BIOS Region.
+ Each entry of the notify list may need to be registered based on a boot path.
+ Make sure what FV is installed by each callback and notify them per needs.
+**/
+static EFI_PEI_NOTIFY_DESCRIPTOR mExtendedBiosDecodeReadyNotifyList [] = {
+ {
+ (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
+ &gExtendedBiosDecodeReadyPpiGuid,
+ InstallFvExtendedPostMemoryCallback
+ },
+ {
+ (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
+ &gExtendedBiosDecodeReadyPpiGuid,
+ InstallFvExtendedAdvancedCallback
+ },
+};
+
+VOID
+PrintFvHeaderInfo (
+ EFI_FIRMWARE_VOLUME_HEADER *FvHeader
+ );
+
+VOID
+ReportPreMemFv (
+ VOID
+ )
+{
+ /*
+ Note : FSP FVs except FSP-T FV are installed in IntelFsp2Wrapper Pkg or FspPkg in Dispatch mode.
+ */
+ if (FixedPcdGetBool (PcdFspWrapperBootMode)) {
+ DEBUG ((DEBUG_INFO, "Install FlashFvFspT - 0x%x, 0x%x\n", PcdGet32 (PcdFlashFvFspTBase), PcdGet32 (PcdFlashFvFspTSize)));
+ PeiServicesInstallFvInfo2Ppi (
+ &(((EFI_FIRMWARE_VOLUME_HEADER *) (UINTN) PcdGet32 (PcdFlashFvFspTBase))->FileSystemGuid),
+ (VOID *) (UINTN) PcdGet32 (PcdFlashFvFspTBase),
+ PcdGet32 (PcdFlashFvFspTSize),
+ NULL,
+ NULL,
+ 0
+ );
+ }
+
+
+ DEBUG ((DEBUG_INFO, "Install FlashFvFirmwareBinaries - 0x%x, 0x%x\n", PcdGet32 (PcdFlashFvFirmwareBinariesBase), PcdGet32 (PcdFlashFvFirmwareBinariesSize)));
+ PeiServicesInstallFvInfo2Ppi (
+ &(((EFI_FIRMWARE_VOLUME_HEADER *) (UINTN) PcdGet32 (PcdFlashFvFirmwareBinariesBase))->FileSystemGuid),
+ (VOID *) (UINTN) PcdGet32 (PcdFlashFvFirmwareBinariesBase),
+ PcdGet32 (PcdFlashFvFirmwareBinariesSize),
+ NULL,
+ NULL,
+ 0
+ );
+}
+
+/**
+ FvCnvUncompact section dependency PPI
+**/
+static EFI_PEI_PPI_DESCRIPTOR mFvCnvDispatchFlagPpi = {
+ (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
+ &gPeiFvCnvDispatchFlagPpiGuid,
+ NULL
+};
+
+/**
+ This function call checks if this is after capsule update by BootStateAfterCapsule variable.
+ The variable is set to TRUE at the end of capsule update process.
+ The boot paths always require all FVs to be installed
+ so UEFI global boot option variables are initialized.
+
+ @retval TRUE This is the first boot after capsule update.
+ @retval FALSE This is NOT the first boot after capsule update.
+**/
+BOOLEAN
+IsAfterCapsule (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+ EFI_PEI_READ_ONLY_VARIABLE2_PPI *VariablePpi;
+ BOOLEAN BootStateAfterCapsule;
+ BOOLEAN IsAfterCapsule;
+ BootStateAfterCapsule = FALSE;
+ IsAfterCapsule = FALSE;
+
+ Status = PeiServicesLocatePpi (
+ &gEfiPeiReadOnlyVariable2PpiGuid,
+ 0,
+ NULL,
+ (VOID **)&VariablePpi
+ );
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "IsAfterCapsule : Read Only Variable PPI is not found.\n"));
+ ASSERT_EFI_ERROR (Status);
+ return FALSE;
+ }
+
+
+ return IsAfterCapsule;
+}
+
+/**
+ This function call installs section dependency PPIs for the child FVs in Optional FV.
+
+ @param[out] *Installed Return TRUE if section dependencies in Optional FV are installed.
+ Return FALSE when none of section dependencies in Optional FV are installed.
+
+ @retval EFI_SUCCESS Section dependency installation completes successfully.
+ @retval Others Section dependency installation fails to complete.
+**/
+EFI_STATUS
+InstallOptionalFvDependency (
+ OUT BOOLEAN *Installed
+ )
+{
+ EFI_STATUS Status;
+
+ Status = EFI_SUCCESS;
+ *Installed = FALSE;
+
+#if FixedPcdGet8(PcdFspModeSelection) == 0 // #if Dispatch Mode
+ if (IsAfterCapsule ()) {
+#endif
+ DEBUG ((DEBUG_INFO, "InstallOptionalFvDependency : Installing FvCnvUncompact dependency.\n"));
+ Status = PeiServicesInstallPpi (&mFvCnvDispatchFlagPpi);
+ *Installed = TRUE;
+ ASSERT_EFI_ERROR (Status);
+#if FixedPcdGet8(PcdFspModeSelection) == 0 // #if Dispatch Mode
+ }
+#endif
+ return Status;
+}
+VOID
+ReportPostMemFv (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+ EFI_BOOT_MODE BootMode;
+ EFI_HOB_GUID_TYPE *GuidHob;
+ BOOLEAN IsOptFvDependencyInstalled;
+ IsOptFvDependencyInstalled = FALSE;
+
+ Status = PeiServicesGetBootMode (&BootMode);
+ ASSERT_EFI_ERROR (Status);
+
+ /*
+ Note : FSP FVs except FSP-T FV are installed in IntelFsp2WrapperPkg or FspPkg.
+ */
+
+ ///
+ /// Build HOB for DXE
+ ///
+ if (BootMode == BOOT_IN_RECOVERY_MODE) {
+ ///
+ /// Prepare the recovery service
+ ///
+ } else {
+ GuidHob = GetFirstGuidHob (&gBiosInfoRecoveryGuid);
+ if (GuidHob == NULL) {
+ DEBUG ((DEBUG_INFO, "Install FlashFvSecurity - 0x%x, 0x%x\n", PcdGet32 (PcdFlashFvSecurityBase), PcdGet32 (PcdFlashFvSecuritySize)));
+ PeiServicesInstallFvInfo2Ppi (
+ &(((EFI_FIRMWARE_VOLUME_HEADER *) (UINTN) PcdGet32 (PcdFlashFvSecurityBase))->FileSystemGuid),
+ (VOID *) (UINTN) PcdGet32 (PcdFlashFvSecurityBase),
+ PcdGet32 (PcdFlashFvSecuritySize),
+ NULL,
+ NULL,
+ 0
+ );
+ if (BootMode != BOOT_ON_S3_RESUME) {
+ DEBUG ((DEBUG_INFO, "Install FlashFvAdvanced - 0x%x, 0x%x\n", PcdGet32 (PcdFlashFvAdvancedBase), PcdGet32 (PcdFlashFvAdvancedSize)));
+ PeiServicesInstallFvInfo2Ppi (
+ &(((EFI_FIRMWARE_VOLUME_HEADER *) (UINTN) PcdGet32 (PcdFlashFvAdvancedBase))->FileSystemGuid),
+ (VOID *) (UINTN) PcdGet32 (PcdFlashFvAdvancedBase),
+ PcdGet32 (PcdFlashFvAdvancedSize),
+ NULL,
+ NULL,
+ 0
+ );
+ DEBUG ((DEBUG_INFO, "Install FlashFvUefiBoot - 0x%x, 0x%x\n", PcdGet32 (PcdFlashFvUefiBootBase), PcdGet32 (PcdFlashFvUefiBootSize)));
+ PeiServicesInstallFvInfo2Ppi (
+ &(((EFI_FIRMWARE_VOLUME_HEADER *) (UINTN) PcdGet32 (PcdFlashFvUefiBootBase))->FileSystemGuid),
+ (VOID *) (UINTN) PcdGet32 (PcdFlashFvUefiBootBase),
+ PcdGet32 (PcdFlashFvUefiBootSize),
+ NULL,
+ NULL,
+ 0
+ );
+ DEBUG ((DEBUG_INFO, "Install FlashFvOsBoot - 0x%x, 0x%x\n", PcdGet32 (PcdFlashFvOsBootBase), PcdGet32 (PcdFlashFvOsBootSize)));
+ PeiServicesInstallFvInfo2Ppi (
+ &(((EFI_FIRMWARE_VOLUME_HEADER *) (UINTN) PcdGet32 (PcdFlashFvOsBootBase))->FileSystemGuid),
+ (VOID *) (UINTN) PcdGet32 (PcdFlashFvOsBootBase),
+ PcdGet32 (PcdFlashFvOsBootSize),
+ NULL,
+ NULL,
+ 0
+ );
+ Status = InstallOptionalFvDependency (&IsOptFvDependencyInstalled);
+ if (!EFI_ERROR (Status) && IsOptFvDependencyInstalled) {
+ DEBUG ((DEBUG_INFO, "Install FlashFvOptional - 0x%x, 0x%x\n", PcdGet32 (PcdFlashFvOptionalBase), PcdGet32 (PcdFlashFvOptionalSize)));
+ PeiServicesInstallFvInfo2Ppi (
+ &(((EFI_FIRMWARE_VOLUME_HEADER *) (UINTN) PcdGet32 (PcdFlashFvOptionalBase))->FileSystemGuid),
+ (VOID *) (UINTN) PcdGet32 (PcdFlashFvOptionalBase),
+ PcdGet32 (PcdFlashFvOptionalSize),
+ NULL,
+ NULL,
+ 0
+ );
+ }
+ }
+ Status = PeiServicesNotifyPpi (&mExtendedBiosDecodeReadyNotifyList [1]);
+ ASSERT_EFI_ERROR (Status);
+ }
+ DEBUG ((DEBUG_INFO, "Install FlashFvPostMemory - 0x%x, 0x%x\n", PcdGet32 (PcdFlashFvPostMemoryBase), PcdGet32 (PcdFlashFvPostMemorySize)));
+ PeiServicesInstallFvInfo2Ppi (
+ &(((EFI_FIRMWARE_VOLUME_HEADER *) (UINTN) PcdGet32 (PcdFlashFvPostMemoryBase))->FileSystemGuid),
+ (VOID *) (UINTN) PcdGet32 (PcdFlashFvPostMemoryBase),
+ PcdGet32 (PcdFlashFvPostMemorySize),
+ NULL,
+ NULL,
+ 0
+ );
+
+ Status = PeiServicesNotifyPpi (&mExtendedBiosDecodeReadyNotifyList [0]);
+ ASSERT_EFI_ERROR (Status);
+
+ if (BootMode != BOOT_ON_S3_RESUME) {
+ BuildFvHob (
+ (UINTN) FixedPcdGet32 (PcdFlashFvMicrocodeBase),
+ (UINTN) FixedPcdGet32 (PcdFlashFvMicrocodeSize)
+ );
+ DEBUG ((DEBUG_INFO, "Build FlashFvMicrocode Hob - 0x%x, 0x%x\n", PcdGet32 (PcdFlashFvMicrocodeBase), PcdGet32 (PcdFlashFvMicrocodeSize)));
+
+ }
+ }
+
+ //
+ // Report resource HOB for flash FV
+ //
+ BuildResourceDescriptorHob (
+ EFI_RESOURCE_MEMORY_MAPPED_IO,
+ (EFI_RESOURCE_ATTRIBUTE_PRESENT |
+ EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
+ EFI_RESOURCE_ATTRIBUTE_WRITE_PROTECTABLE),
+ (UINTN) PcdGet32 (PcdFlashAreaBaseAddress),
+ (UINTN) PcdGet32 (PcdFlashAreaSize)
+ );
+ BuildMemoryAllocationHob (
+ (UINTN) PcdGet32 (PcdFlashAreaBaseAddress),
+ (UINTN) PcdGet32 (PcdFlashAreaSize),
+ EfiMemoryMappedIO
+ );
+}
+
+
+/**
+ Callback on Extended BIOS Decode Ready Ppi so Extended PostMemory FV is installed to the memory
+ for Extended BIOS Region. The callback is called regardless of Extended BIOS Region support
+ in platform code.
+
+ @param[in] PeiServices General purpose services available to every PEIM.
+ @param[in] NotifyDescriptor The notification structure this PEIM registered on install.
+ @param[in] Ppi The gExtendedBiosDecodeReady PPI. Not used.
+
+ @retval EFI_SUCCESS Always returns EFI_SUCCESS
+**/
+EFI_STATUS
+EFIAPI
+InstallFvExtendedPostMemoryCallback (
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
+ IN VOID *Ppi
+ )
+{
+ DEBUG ((DEBUG_INFO, "Extended BIOS Region is not supported by the image. No FV installed here\n"));
+ return EFI_SUCCESS;
+}
+
+
+/**
+ Callback on Extended BIOS Decode Ready Ppi so Extended Advanced FV is installed to the memory
+ for Extended BIOS Region. The callback is called regardless of Extended BIOS Region support in
+ platform code. Extended Advanced FV contains DXE phase drivers only and may want to be skipped
+ on S3 path for responsiveness.
+
+ @param[in] PeiServices General purpose services available to every PEIM.
+ @param[in] NotifyDescriptor The notification structure this PEIM registered on install.
+ @param[in] Ppi The gExtendedBiosDecodeReady PPI. Not used.
+
+ @retval EFI_SUCCESS Always returns EFI_SUCCESS
+**/
+EFI_STATUS
+EFIAPI
+InstallFvExtendedAdvancedCallback (
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
+ IN VOID *Ppi
+ )
+{
+ DEBUG ((DEBUG_INFO, "Extended BIOS Region is not supported by the image. No FV installed here\n"));
+ return EFI_SUCCESS;
+}
+
+
+/**
+ Debug support function to output detailed information on a firmware volume being installed.
+ Setting DEBUG_PROPERTY_DEBUG_CODE_ENABLED bit of PcdDebugProperyMask lets the function to be
+ included in a module. Refer to DEBUG_CODE macro.
+
+ @param[in] FvHeader Pointer to firmware volume header
+**/
+VOID
+PrintFvHeaderInfo (
+ EFI_FIRMWARE_VOLUME_HEADER *FvHeader
+ )
+{
+ DEBUG_CODE (
+ EFI_FIRMWARE_VOLUME_EXT_HEADER *FvExtHeader;
+ EFI_FFS_FILE_HEADER *FfsHeader;
+
+ DEBUG ((DEBUG_INFO, "[ FV @ 0x%x ] \n", FvHeader));
+ DEBUG ((DEBUG_INFO, " FV File System : %g \n", &FvHeader->FileSystemGuid));
+ if (FvHeader->ExtHeaderOffset != 0) {
+ FvExtHeader = (EFI_FIRMWARE_VOLUME_EXT_HEADER *) ((UINT8 *) FvHeader + FvHeader->ExtHeaderOffset);
+ FfsHeader = (EFI_FFS_FILE_HEADER *) ((UINT8 *) FvExtHeader + FvExtHeader->ExtHeaderSize);
+ FfsHeader = (EFI_FFS_FILE_HEADER *) ALIGN_POINTER (FfsHeader, 8);
+ DEBUG ((DEBUG_INFO, " FV GUID : %g \n", &FvExtHeader->FvName));
+ DEBUG ((DEBUG_INFO, " File GUID : %g \n", &FfsHeader->Name));
+ }
+ );
+}
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Library/PeiReportFvLib/PeiReportFvLib.inf b/Platform/Intel/AlderlakeOpenBoardPkg/Library/PeiReportFvLib/PeiReportFvLib.inf
new file mode 100644
index 0000000000..9e0035d445
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Library/PeiReportFvLib/PeiReportFvLib.inf
@@ -0,0 +1,78 @@
+## @file
+# Component information file for the PEI Report Firmware Volume (FV) library.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010017
+ BASE_NAME = PeiReportFvLib
+ FILE_GUID = 44328FA5-E4DD-4A15-ABDF-C6584AC363D9
+ VERSION_STRING = 1.0
+ MODULE_TYPE = PEIM
+ LIBRARY_CLASS = ReportFvLib
+
+[LibraryClasses]
+ BaseMemoryLib
+ DebugLib
+ HobLib
+ PeiServicesLib
+ PcdLib
+ MtrrLib
+ ReportStatusCodeLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ MinPlatformPkg/MinPlatformPkg.dec
+ AlderlakeSiliconPkg/SiPkg.dec
+ AlderlakeOpenBoardPkg/OpenBoardPkg.dec
+ IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec
+ UefiCpuPkg/UefiCpuPkg.dec
+
+
+[Sources]
+ PeiReportFvLib.c
+
+[Ppis]
+ gEfiPeiReadOnlyVariable2PpiGuid ## CONSUMES
+ gPeiFvCnvDispatchFlagPpiGuid ## PRODUCES
+ gExtendedBiosDecodeReadyPpiGuid ## CONSUMES
+
+[Guids]
+ gBiosInfoRecoveryGuid
+
+[Pcd]
+ gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTBase ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSize ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryBase ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootBase ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootBase ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityBase ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedBase ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdFlashFvFirmwareBinariesBase ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdFlashFvFirmwareBinariesSize ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdFlashFvOptionalBase ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdFlashFvOptionalSize ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryBase ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemorySize ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdFlashFvExtendedPostMemoryBase ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdFlashFvExtendedPostMemorySize ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdFlashFvExtendedAdvancedBase ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdFlashFvExtendedAdvancedSize ## CONSUMES
+
+ [FixedPcd]
+ gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection ## CONSUMES
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Library/SmmSpiFlashCommonLib/SmmSpiFlashCommonLib.inf b/Platform/Intel/AlderlakeOpenBoardPkg/Library/SmmSpiFlashCommonLib/SmmSpiFlashCommonLib.inf
new file mode 100644
index 0000000000..ea2f464b99
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Library/SmmSpiFlashCommonLib/SmmSpiFlashCommonLib.inf
@@ -0,0 +1,52 @@
+### @file
+# SMM Library instance of Spi Flash Common Library Class
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+###
+
+[Defines]
+ INF_VERSION = 0x00010017
+ BASE_NAME = SmmSpiFlashCommonLib
+ FILE_GUID = 9632D96E-E849-4217-9217-DC500B8AAE47
+ VERSION_STRING = 1.0
+ MODULE_TYPE = DXE_SMM_DRIVER
+ LIBRARY_CLASS = SpiFlashCommonLib|DXE_SMM_DRIVER
+ CONSTRUCTOR = SmmSpiFlashCommonLibConstructor
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = IA32 X64
+#
+
+[LibraryClasses]
+ IoLib
+ MemoryAllocationLib
+ BaseLib
+ UefiLib
+ SmmServicesTableLib
+ BaseMemoryLib
+ DebugLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ AlderlakeSiliconPkg/SiPkg.dec
+ AlderlakeOpenBoardPkg/OpenBoardPkg.dec
+
+[Pcd]
+ gSiPkgTokenSpaceGuid.PcdBiosAreaBaseAddress ## CONSUMES
+ gSiPkgTokenSpaceGuid.PcdBiosSize ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdFlashExtendRegionSizeInUse ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdFlashExtendRegionOffset ## CONSUMES
+ gPlatformModuleTokenSpaceGuid.PcdExtendedBiosRegionSupport ## CONSUMES
+
+[Sources]
+ SpiFlashCommonSmmLib.c
+ SpiFlashCommon.c
+
+[Protocols]
+ gPchSmmSpiProtocolGuid ## CONSUMES
+
+[Depex.X64.DXE_SMM_DRIVER]
+ gPchSmmSpiProtocolGuid
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Library/SmmSpiFlashCommonLib/SpiFlashCommon.c b/Platform/Intel/AlderlakeOpenBoardPkg/Library/SmmSpiFlashCommonLib/SpiFlashCommon.c
new file mode 100644
index 0000000000..3f7c52ac73
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Library/SmmSpiFlashCommonLib/SpiFlashCommon.c
@@ -0,0 +1,215 @@
+/** @file
+ Wrap EFI_SPI_PROTOCOL to provide some library level interfaces
+ for module use.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+
+**/
+
+#include <Library/SpiFlashCommon.h>
+#include <Library/IoLib.h>
+
+PCH_SPI_PROTOCOL *mSpiProtocol;
+
+//
+// Variables for boottime and runtime usage.
+//
+UINTN mBiosAreaBaseAddress = 0;
+UINTN mBiosSize = 0;
+UINTN mBiosOffset = 0;
+
+/**
+ Enable block protection on the Serial Flash device.
+
+ @retval EFI_SUCCESS Operation is successful.
+ @retval EFI_DEVICE_ERROR If there is any device errors.
+
+**/
+EFI_STATUS
+EFIAPI
+SpiFlashLock (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+
+ Status = EFI_SUCCESS;
+
+ return Status;
+}
+
+/**
+ Read NumBytes bytes of data from the address specified by
+ PAddress into Buffer.
+
+ @param[in] Address The starting physical address of the read.
+ @param[in,out] NumBytes On input, the number of bytes to read. On output, the number
+ of bytes actually read.
+ @param[out] Buffer The destination data buffer for the read.
+
+ @retval EFI_SUCCESS Operation is successful.
+ @retval EFI_DEVICE_ERROR If there is any device errors.
+
+**/
+EFI_STATUS
+EFIAPI
+SpiFlashRead (
+ IN UINTN Address,
+ IN OUT UINT32 *NumBytes,
+ OUT UINT8 *Buffer
+ )
+{
+ ASSERT ((NumBytes != NULL) && (Buffer != NULL));
+ if ((NumBytes == NULL) || (Buffer == NULL)) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ //
+ // This function is implemented specifically for those platforms
+ // at which the SPI device is memory mapped for read. So this
+ // function just do a memory copy for Spi Flash Read.
+ //
+ CopyMem (Buffer, (VOID *) Address, *NumBytes);
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Write NumBytes bytes of data from Buffer to the address specified by
+ PAddresss.
+
+ @param[in] Address The starting physical address of the write.
+ @param[in,out] NumBytes On input, the number of bytes to write. On output,
+ the actual number of bytes written.
+ @param[in] Buffer The source data buffer for the write.
+
+ @retval EFI_SUCCESS Operation is successful.
+ @retval EFI_DEVICE_ERROR If there is any device errors.
+ @retval EFI_INVALID_PARAMETER Invalid parameter.
+ @retval EFI_BAD_BUFFER_SIZE DataSectionSize in BGUP header exceeds the
+ size ofBIOS Guard script buffer
+
+**/
+EFI_STATUS
+EFIAPI
+SpiFlashWrite (
+ IN UINTN Address,
+ IN OUT UINT32 *NumBytes,
+ IN UINT8 *Buffer
+ )
+{
+ EFI_STATUS Status;
+ UINTN Offset;
+ UINT32 Length;
+ UINT32 RemainingBytes;
+
+ ASSERT ((NumBytes != NULL) && (Buffer != NULL));
+ if ((NumBytes == NULL) || (Buffer == NULL)) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ ASSERT (Address >= mBiosAreaBaseAddress);
+ if (Address < mBiosAreaBaseAddress) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ Offset = Address - mBiosAreaBaseAddress;
+
+ ASSERT ((*NumBytes + Offset) <= mBiosSize);
+ if ((*NumBytes + Offset) > mBiosSize) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ Status = EFI_SUCCESS;
+ RemainingBytes = *NumBytes;
+
+ while (RemainingBytes > 0) {
+ if (RemainingBytes > SECTOR_SIZE_4KB) {
+ Length = SECTOR_SIZE_4KB;
+ } else {
+ Length = RemainingBytes;
+ }
+ Status = mSpiProtocol->FlashWrite (
+ mSpiProtocol,
+ FlashRegionBios,
+ (UINT32) Offset,
+ Length,
+ Buffer
+ );
+ if (EFI_ERROR (Status)) {
+ break;
+ }
+ RemainingBytes -= Length;
+ Offset += Length;
+ Buffer += Length;
+ }
+
+ //
+ // Actual number of bytes written
+ //
+ *NumBytes -= RemainingBytes;
+
+ return Status;
+}
+
+/**
+ Erase the block starting at Address.
+
+ @param[in] Address The starting physical address of the block to be erased.
+ This library assume that caller garantee that the PAddress
+ is at the starting address of this block.
+ @param[in] NumBytes On input, the number of bytes of the logical block to be erased.
+ On output, the actual number of bytes erased.
+
+ @retval EFI_SUCCESS. Operation is successful.
+ @retval EFI_DEVICE_ERROR If there is any device errors.
+ @retval EFI_INVALID_PARAMETER Invalid parameter.
+
+**/
+EFI_STATUS
+EFIAPI
+SpiFlashBlockErase (
+ IN UINTN Address,
+ IN UINTN *NumBytes
+ )
+{
+ EFI_STATUS Status;
+ UINTN Offset;
+ UINTN RemainingBytes;
+
+ ASSERT (NumBytes != NULL);
+ if (NumBytes == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ ASSERT (Address >= mBiosAreaBaseAddress);
+ if (Address < mBiosAreaBaseAddress) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ Offset = Address - mBiosAreaBaseAddress;
+
+ ASSERT ((*NumBytes % SECTOR_SIZE_4KB) == 0);
+ if ((*NumBytes % SECTOR_SIZE_4KB) != 0) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ ASSERT ((*NumBytes + Offset) <= mBiosSize);
+ if ((*NumBytes + Offset) > mBiosSize) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ Status = EFI_SUCCESS;
+ RemainingBytes = *NumBytes;
+
+ Status = mSpiProtocol->FlashErase (
+ mSpiProtocol,
+ FlashRegionBios,
+ (UINT32) Offset,
+ (UINT32) RemainingBytes
+ );
+ return Status;
+}
+
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Library/SmmSpiFlashCommonLib/SpiFlashCommonSmmLib.c b/Platform/Intel/AlderlakeOpenBoardPkg/Library/SmmSpiFlashCommonLib/SpiFlashCommonSmmLib.c
new file mode 100644
index 0000000000..7d74162d43
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Library/SmmSpiFlashCommonLib/SpiFlashCommonSmmLib.c
@@ -0,0 +1,64 @@
+/** @file
+ SMM Library instance of SPI Flash Common Library Class
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+
+**/
+
+#include <Library/SpiFlashCommon.h>
+#include <Library/SmmServicesTableLib.h>
+
+extern PCH_SPI_PROTOCOL *mSpiProtocol;
+
+extern UINTN mBiosAreaBaseAddress;
+extern UINTN mBiosSize;
+extern UINTN mBiosOffset;
+
+/**
+ The library constructuor.
+
+ The function does the necessary initialization work for this library
+ instance.
+
+ @param[in] ImageHandle The firmware allocated handle for the UEFI image.
+ @param[in] SystemTable A pointer to the EFI system table.
+
+ @retval EFI_SUCCESS The function always return EFI_SUCCESS for now.
+ It will ASSERT on error for debug version.
+ @retval EFI_ERROR Please reference LocateProtocol for error code details.
+**/
+EFI_STATUS
+EFIAPI
+SmmSpiFlashCommonLibConstructor (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUS Status;
+ UINT32 BaseAddr;
+ UINT32 RegionSize;
+
+#if FixedPcdGetBool(PcdExtendedBiosRegionSupport) == 0
+ mBiosAreaBaseAddress = (UINTN)PcdGet32 (PcdBiosAreaBaseAddress);
+ mBiosSize = (UINTN)PcdGet32 (PcdBiosSize);
+#else
+ mBiosAreaBaseAddress = (UINTN) PcdGet32 (PcdBiosAreaBaseAddress) + (UINTN) PcdGet32 (PcdFlashExtendRegionOffset);
+ mBiosSize = 0x1000000 + (UINTN) PcdGet32 (PcdFlashExtendRegionSizeInUse);
+#endif
+ //
+ // Locate the SMM SPI protocol.
+ //
+ Status = gSmst->SmmLocateProtocol (
+ &gPchSmmSpiProtocolGuid,
+ NULL,
+ (VOID **) &mSpiProtocol
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ mSpiProtocol->GetRegionAddress (mSpiProtocol, FlashRegionBios, &BaseAddr, &RegionSize);
+ mBiosOffset = BaseAddr;
+
+ return Status;
+}
--
2.36.1.windows.1
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