From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [63.128.21.124]) by mx.groups.io with SMTP id smtpd.web09.33862.1605039962254920631 for ; Tue, 10 Nov 2020 12:26:02 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=@redhat.com header.s=mimecast20190719 header.b=JUIzlHLV; spf=pass (domain: redhat.com, ip: 63.128.21.124, mailfrom: lersek@redhat.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1605039961; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=QuqEWBGQANA8m65m+rveyJBdrsNTQytIMN30c497Ud8=; b=JUIzlHLVaE2L0P2DVWzm2NYUfi46Y/u4AjQLR72kr1l6Gjq5T0nk7LGiW2nPnp2MBjpIXB EhuowdXOZSrKoI4gmaDgtfbmdXTLjNUsi0LbSLIBNGN800fPyBkU4+D4OS/B8Pb6zvn9CM TOeeWWsKZGILvz0g+A3D06IlEgYzZlA= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-48-aFYk7go_NmuywvNo1LIuPg-1; Tue, 10 Nov 2020 15:25:59 -0500 X-MC-Unique: aFYk7go_NmuywvNo1LIuPg-1 Received: from smtp.corp.redhat.com (int-mx04.intmail.prod.int.phx2.redhat.com [10.5.11.14]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 30AA9804750; Tue, 10 Nov 2020 20:25:58 +0000 (UTC) Received: from lacos-laptop-7.usersys.redhat.com (ovpn-112-118.ams2.redhat.com [10.36.112.118]) by smtp.corp.redhat.com (Postfix) with ESMTP id 8A7875D9D2; Tue, 10 Nov 2020 20:25:56 +0000 (UTC) Subject: Re: [PATCH v6 2/2] UefiCpuPkg/PiSmmCpuDxeSmm: Reflect page table depth with page table address To: Sheng Wei , devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Rahul Kumar , Jiewen Yao References: <20201110022430.19560-1-w.sheng@intel.com> <20201110022430.19560-3-w.sheng@intel.com> From: "Laszlo Ersek" Message-ID: Date: Tue, 10 Nov 2020 21:25:55 +0100 MIME-Version: 1.0 In-Reply-To: <20201110022430.19560-3-w.sheng@intel.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.14 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=lersek@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit On 11/10/20 03:24, Sheng Wei wrote: > @@ -1114,11 +1145,10 @@ SetPageTableAttributes ( > BOOLEAN IsSplitted; > BOOLEAN PageTableSplitted; > BOOLEAN CetEnabled; > - IA32_CR4 Cr4; > BOOLEAN Enable5LevelPaging; > + UINT64 *PageTableBase = NULL; > > - Cr4.UintN = AsmReadCr4 (); > - Enable5LevelPaging = (BOOLEAN) (Cr4.Bits.LA57 == 1); > + GetPageTable ((UINTN *)&PageTableBase, &Enable5LevelPaging); > > // > // Don't mark page table memory as read-only if > @@ -1164,7 +1194,7 @@ SetPageTableAttributes ( > PageTableSplitted = FALSE; > L5PageTable = NULL; > if (Enable5LevelPaging) { > - L5PageTable = (UINT64 *)GetPageTableBase (); > + L5PageTable = PageTableBase; > SmmSetMemoryAttributesEx ((EFI_PHYSICAL_ADDRESS)(UINTN)L5PageTable, SIZE_4KB, EFI_MEMORY_RO, &IsSplitted); > PageTableSplitted = (PageTableSplitted || IsSplitted); > } > @@ -1176,7 +1206,7 @@ SetPageTableAttributes ( > continue; > } > } else { > - L4PageTable = (UINT64 *)GetPageTableBase (); > + L4PageTable = PageTableBase; > } > SmmSetMemoryAttributesEx ((EFI_PHYSICAL_ADDRESS)(UINTN)L4PageTable, SIZE_4KB, EFI_MEMORY_RO, &IsSplitted); > PageTableSplitted = (PageTableSplitted || IsSplitted); > (14) Are you sure that we never need to re-read the CR3 register inside the outermost loop? I would feel safer if you didn't place the GetPageTable() call at the top of the function (replacing the AsmReadCr4() call). Instead, I suggest placing GetPageTable() near the top of the outermost loop (the one that is repeated as long as we split pages). Here's what I suggest, for "UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c": > diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c > index 810985df20ae..52b8eac9cdaf 100644 > --- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c > +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c > @@ -1112,16 +1112,13 @@ SetPageTableAttributes ( > UINT64 *L4PageTable; > UINT64 *L5PageTable; > BOOLEAN IsSplitted; > BOOLEAN PageTableSplitted; > BOOLEAN CetEnabled; > - IA32_CR4 Cr4; > + UINTN PageTableBase; > BOOLEAN Enable5LevelPaging; > > - Cr4.UintN = AsmReadCr4 (); > - Enable5LevelPaging = (BOOLEAN) (Cr4.Bits.LA57 == 1); > - > // > // Don't mark page table memory as read-only if > // - no restriction on access to non-SMRAM memory; or > // - SMM heap guard feature enabled; or > // BIT2: SMM page guard enabled > @@ -1161,24 +1158,27 @@ SetPageTableAttributes ( > > do { > DEBUG ((DEBUG_INFO, "Start...\n")); > PageTableSplitted = FALSE; > L5PageTable = NULL; > + > + GetPageTableBase (&PageTableBase, &Enable5LevelPaging); > + > if (Enable5LevelPaging) { > - L5PageTable = (UINT64 *)GetPageTableBase (); > - SmmSetMemoryAttributesEx ((EFI_PHYSICAL_ADDRESS)(UINTN)L5PageTable, SIZE_4KB, EFI_MEMORY_RO, &IsSplitted); > + L5PageTable = (UINT64 *)PageTableBase; > + SmmSetMemoryAttributesEx ((EFI_PHYSICAL_ADDRESS)PageTableBase, SIZE_4KB, EFI_MEMORY_RO, &IsSplitted); > PageTableSplitted = (PageTableSplitted || IsSplitted); > } > > for (Index5 = 0; Index5 < (Enable5LevelPaging ? SIZE_4KB/sizeof(UINT64) : 1); Index5++) { > if (Enable5LevelPaging) { > L4PageTable = (UINT64 *)(UINTN)(L5PageTable[Index5] & ~mAddressEncMask & PAGING_4K_ADDRESS_MASK_64); > if (L4PageTable == NULL) { > continue; > } > } else { > - L4PageTable = (UINT64 *)GetPageTableBase (); > + L4PageTable = (UINT64 *)PageTableBase; > } > SmmSetMemoryAttributesEx ((EFI_PHYSICAL_ADDRESS)(UINTN)L4PageTable, SIZE_4KB, EFI_MEMORY_RO, &IsSplitted); > PageTableSplitted = (PageTableSplitted || IsSplitted); > > for (Index4 = 0; Index4 < SIZE_4KB/sizeof(UINT64); Index4++) { This way, we preserve the pre-patch behavior that the page table base is re-read *exactly once* per outermost loop iteration. My proposal matches the IA32 version more closely as well -- in the IA32 version too, GetPageTableBase() is called near the top of the outermost loop. It is true that we re-read "Enable5LevelPaging" as well once per outermost iteration, but (IMO) that's fine. It's a consequence of binding "PageTableBase" and "Enable5LevelPaging" together (which is a good thing), and re-reading "Enable5LevelPaging" once per outermost iteration is not costly. Thanks Laszlo