* [edk2-devel] [PATCH v2 01/10] AlderlakeSiliconPkg/IpBlock: Add CpuPcieRp, Espi, Gpio components
@ 2023-09-15 4:45 Saloni Kasbekar
2023-09-15 4:45 ` [edk2-devel] [PATCH v2 02/10] AlderlakeSiliconPkg/IpBlock: Add Graphics, HostBridge, PcieRp components Saloni Kasbekar
` (11 more replies)
0 siblings, 12 replies; 41+ messages in thread
From: Saloni Kasbekar @ 2023-09-15 4:45 UTC (permalink / raw)
To: devel; +Cc: Saloni Kasbekar, Sai Chaganty, Nate DeSimone, Rosen Chuang
Adds the following modules:
- IpBlock/CpuPcieRp/Include
- IpBlock/Espi/Library
- IpBlock/Gpio/IncludePrivate
- IpBlock/Gpio/Library
- IpBlock/Gpio/LibraryPrivate
Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Rosen Chuang <rosen.chuang@intel.com>
Signed-off-by: Saloni Kasbekar <saloni.kasbekar@intel.com>
---
.../IpBlock/CpuPcieRp/Include/CpuPcieInfo.h | 25 +
.../Espi/Library/PeiDxeSmmEspiLib/EspiLib.c | 58 ++
.../PeiDxeSmmEspiLib/PeiDxeSmmEspiLib.inf | 38 ++
.../IncludePrivate/Library/GpioHelpersLib.h | 50 ++
.../IncludePrivate/Library/GpioNativePads.h | 245 ++++++++
.../IncludePrivate/Library/GpioPrivateLib.h | 350 +++++++++++
.../Gpio/Library/PeiDxeSmmGpioLib/GpioInit.c | 546 ++++++++++++++++++
.../Gpio/Library/PeiDxeSmmGpioLib/GpioLib.c | 522 +++++++++++++++++
.../Library/PeiDxeSmmGpioLib/GpioLibrary.h | 29 +
.../Library/PeiDxeSmmGpioLib/GpioNativeLib.c | 177 ++++++
.../PeiDxeSmmGpioLib/PeiDxeSmmGpioLib.inf | 44 ++
.../BaseGpioHelpersLibNull.c | 51 ++
.../BaseGpioHelpersLibNull.inf | 25 +
.../GpioNativePrivateLibInternal.h | 48 ++
.../PeiDxeSmmGpioPrivateLib/GpioPrivateLib.c | 267 +++++++++
.../GpioPrivateLibPch.c | 172 ++++++
.../GpioPrivateLibVer2.c | 81 +++
.../PeiDxeSmmGpioPrivateLibVer2.inf | 40 ++
.../PeiGpioHelpersLib/PeiGpioHelpersLib.c | 218 +++++++
.../PeiGpioHelpersLib/PeiGpioHelpersLib.inf | 46 ++
20 files changed, 3032 insertions(+)
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/CpuPcieRp/Include/CpuPcieInfo.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Espi/Library/PeiDxeSmmEspiLib/EspiLib.c
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Espi/Library/PeiDxeSmmEspiLib/PeiDxeSmmEspiLib.inf
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/IncludePrivate/Library/GpioHelpersLib.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/IncludePrivate/Library/GpioNativePads.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/IncludePrivate/Library/GpioPrivateLib.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/Library/PeiDxeSmmGpioLib/GpioInit.c
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/Library/PeiDxeSmmGpioLib/GpioLib.c
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/Library/PeiDxeSmmGpioLib/GpioLibrary.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/Library/PeiDxeSmmGpioLib/GpioNativeLib.c
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/Library/PeiDxeSmmGpioLib/PeiDxeSmmGpioLib.inf
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/BaseGpioHelpersLibNull/BaseGpioHelpersLibNull.c
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/BaseGpioHelpersLibNull/BaseGpioHelpersLibNull.inf
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiDxeSmmGpioPrivateLib/GpioNativePrivateLibInternal.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiDxeSmmGpioPrivateLib/GpioPrivateLib.c
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiDxeSmmGpioPrivateLib/GpioPrivateLibPch.c
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiDxeSmmGpioPrivateLib/GpioPrivateLibVer2.c
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiDxeSmmGpioPrivateLib/PeiDxeSmmGpioPrivateLibVer2.inf
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiGpioHelpersLib/PeiGpioHelpersLib.c
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiGpioHelpersLib/PeiGpioHelpersLib.inf
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/CpuPcieRp/Include/CpuPcieInfo.h b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/CpuPcieRp/Include/CpuPcieInfo.h
new file mode 100644
index 0000000000..a6f8b16d10
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/CpuPcieRp/Include/CpuPcieInfo.h
@@ -0,0 +1,25 @@
+/** @file
+ This file contains definitions of PCIe controller information
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _CPU_PCIE_INFO_H_
+#define _CPU_PCIE_INFO_H_
+
+#define PCIE_HWEQ_COEFFS_MAX 5
+
+
+//
+// SA PCI Express* Port configuration
+//
+
+#define CPU_PCIE_MAX_ROOT_PORTS 4
+#define CPU_PCIE_MAX_CONTROLLERS 3
+
+#define SA_PEG_MAX_FUN 0x04
+#define SA_PEG_MAX_LANE 0x14
+
+
+
+#endif
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Espi/Library/PeiDxeSmmEspiLib/EspiLib.c b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Espi/Library/PeiDxeSmmEspiLib/EspiLib.c
new file mode 100644
index 0000000000..2e4d1375ca
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Espi/Library/PeiDxeSmmEspiLib/EspiLib.c
@@ -0,0 +1,58 @@
+/** @file
+ This file contains routines for eSPI
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#include <Base.h>
+#include <Uefi/UefiBaseType.h>
+#include <Library/IoLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/EspiLib.h>
+#include <Library/PchPcrLib.h>
+#include <Library/PchInfoLib.h>
+#include <Library/TimerLib.h>
+#include <PchLimits.h>
+#include <Register/PchPcrRegs.h>
+#include <Register/PchRegsLpc.h>
+
+
+/**
+ Checks if second device capability is enabled
+
+ @retval TRUE There's second device
+ @retval FALSE There's no second device
+**/
+BOOLEAN
+IsEspiSecondSlaveSupported (
+ VOID
+ )
+{
+ return ((PchPcrRead32 (PID_ESPISPI, R_ESPI_PCR_SOFTSTRAPS) & B_ESPI_PCR_SOFTSTRAPS_CS1_EN) != 0);
+}
+
+
+/**
+ Is eSPI enabled in strap.
+
+ @retval TRUE Espi is enabled in strap
+ @retval FALSE Espi is disabled in strap
+**/
+BOOLEAN
+IsEspiEnabled (
+ VOID
+ )
+{
+ return (PchPcrRead32 (PID_ESPISPI, R_ESPI_PCR_CFG_VAL) & B_ESPI_PCR_CFG_VAL_ESPI_EN) != 0;
+}
+
+typedef enum {
+ EspiSlaveOperationConfigRead,
+ EspiSlaveOperationConfigWrite,
+ EspiSlaveOperationStatusRead,
+ EspiSlaveOperationInBandReset
+} ESPI_SLAVE_OPERATION;
+
+
+
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Espi/Library/PeiDxeSmmEspiLib/PeiDxeSmmEspiLib.inf b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Espi/Library/PeiDxeSmmEspiLib/PeiDxeSmmEspiLib.inf
new file mode 100644
index 0000000000..e8db1e4e8d
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Espi/Library/PeiDxeSmmEspiLib/PeiDxeSmmEspiLib.inf
@@ -0,0 +1,38 @@
+## @file
+# Component description file for the PeiDxeSmmPchEspiLib
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+
+[Defines]
+INF_VERSION = 0x00010017
+BASE_NAME = PeiDxeSmmEspiLib
+FILE_GUID = 7F25F990-7989-4413-B414-1EDE557E9389
+VERSION_STRING = 1.0
+MODULE_TYPE = BASE
+LIBRARY_CLASS = EspiLib
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = IA32 X64 IPF EBC
+#
+
+
+
+[LibraryClasses]
+BaseLib
+IoLib
+DebugLib
+PchPcrLib
+TimerLib
+
+
+[Packages]
+MdePkg/MdePkg.dec
+AlderlakeSiliconPkg/SiPkg.dec
+
+
+[Sources]
+EspiLib.c
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/IncludePrivate/Library/GpioHelpersLib.h b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/IncludePrivate/Library/GpioHelpersLib.h
new file mode 100644
index 0000000000..cf67c81ed0
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/IncludePrivate/Library/GpioHelpersLib.h
@@ -0,0 +1,50 @@
+/** @file
+ Header file for GPIO Helpers Lib implementation.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _GPIO_HELPERS_LIB_H_
+#define _GPIO_HELPERS_LIB_H_
+
+#include <Library/GpioConfig.h>
+
+/**
+ This procedure stores GPIO group data about pads which PadConfig needs to be unlocked.
+
+ @param[in] GroupIndex GPIO group index
+ @param[in] DwNum DWORD index for a group.
+ For group which has less then 32 pads per group DwNum must be 0.
+ @param[in] PadsToLock DWORD bitmask for pads which are going to be left unlocked
+ Bit position - PadNumber
+ Bit value - 0: Skip, 1: Leave unlocked
+
+ @retval Status
+**/
+EFI_STATUS
+GpioStoreGroupDwUnlockPadConfigData (
+ IN UINT32 GroupIndex,
+ IN UINT32 DwNum,
+ IN UINT32 UnlockedPads
+ );
+
+/**
+ This procedure stores GPIO group data about pads which Output state needs to be unlocked.
+
+ @param[in] GroupIndex GPIO group index
+ @param[in] DwNum DWORD index for a group.
+ For group which has less then 32 pads per group DwNum must be 0.
+ @param[in] PadsToLock DWORD bitmask for pads which are going to be left unlocked
+ Bit position - PadNumber
+ Bit value - 0: Skip, 1: Leave unlocked
+
+ @retval Status
+**/
+EFI_STATUS
+GpioStoreGroupDwUnlockOutputData (
+ IN UINT32 GroupIndex,
+ IN UINT32 DwNum,
+ IN UINT32 UnlockedPads
+ );
+
+#endif // _GPIO_HELPERS_LIB_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/IncludePrivate/Library/GpioNativePads.h b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/IncludePrivate/Library/GpioNativePads.h
new file mode 100644
index 0000000000..dbd13963fa
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/IncludePrivate/Library/GpioNativePads.h
@@ -0,0 +1,245 @@
+/** @file
+ Header file for GPIO Native pads support
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _GPIO_NATIVE_PADS_H_
+#define _GPIO_NATIVE_PADS_H_
+
+//
+// GpioPad can contain additional information used to provide data on
+// native functions. Please refer to description of GPIO_NATIVE_PAD
+//
+// FFFF CCCC TTTG GGGG TTTT TTTP PPPP PPPP
+//
+// F - 2^4 = 16, native function number
+// C - 2^4 = 16, chipset ID
+// T - 2^10 = 1024 , abstract type representing native mode of a pad (e.g. SERIALIO_UART2_TX)
+// G - 2^5 = 32, group
+// P - 2^9 = 512, pad number
+//
+// F & T contain additional optional settings used for native pads
+//
+#define GPIO_NATIVE_PAD_DEF(GpioNativePad, NativeMode, NativeFunction) \
+ (GpioNativePad | (NativeMode << 28) | ((NativeFunction & 0x7F) << 9) | ((NativeFunction & 0x380) << 14))
+
+#define GPIO_NATIVE_GET_FUNCTION(GpioNativePad) ((((GpioNativePad) & 0xFE00) >> 9) | (((GpioNativePad) & 0xE00000) >> 14))
+#define GPIO_NATIVE_GET_PAD_FN(GpioNativePad) (((GpioNativePad) >> 28) & 0xF)
+#define GPIO_NATIVE_GET_PAD_MODE(GpioNativePad) ((GPIO_NATIVE_GET_PAD_FN(GpioNativePad) << 1) | 1)
+#define GPIO_NATIVE_TO_GPIO_PAD(GpioNativePad) (GpioNativePad & 0xF1F01FF)
+
+//
+// Below defines and macros are used to build abstract type
+// to help encode native pin information in GPIO_PAD
+//
+
+//
+// Macro used to define GPIO native function.
+// <Min,Max> defines range that can be used to encode given native signal.
+// Numbering must be unique and cannot overlap.
+// If there are many instances of similar signal (e.g. per controller) the lower
+// word will store value for a given instance in the form: Min + Instance
+// Upper word (Max) is left untouched and later used for verification
+//
+#define GPIO_NATIVE_FUNCTION_DEF(Min, Max) (((Max) << 16) + (Min))
+#define GPIO_NATIVE_FUNCTION_GET_MAX(NativeFunction) (((NativeFunction) >> 16) & 0xFFFF)
+#define GPIO_NATIVE_FUNCTION_GET_VALUE(NativeFunction) ((NativeFunction) & 0xFFFF)
+
+//
+// Macro GPIO_NATIVE_FUNCTION_GET_SIGNAL is created as synonym to macro GPIO_NATIVE_FUNCTION_GET_MAX
+// GPIO_NATIVE_FUNCTION_GET_SIGNAL used with below defines is more descriptive and easier to read
+// ex.
+// - GPIO_NATIVE_FUNCTION_GET_SIGNAL(GPIO_SERIAL_IO_UART_RX)
+// - GPIO_NATIVE_FUNCTION_GET_SIGNAL(GPIO_ISH_GP)
+// - ...
+//
+#define GPIO_NATIVE_FUNCTION_GET_SIGNAL(NativeFunction) (GPIO_NATIVE_FUNCTION_GET_MAX(NativeFunction))
+
+//
+// GPIO native modes
+// Those defines are internal to this header.
+// GPIO_FUNCTION_<IP>_<signal>(index) defines should be used by other modules instead.
+//
+#define GPIO_SERIAL_IO_UART_RX GPIO_NATIVE_FUNCTION_DEF(1,8)
+#define GPIO_SERIAL_IO_UART_TX GPIO_NATIVE_FUNCTION_DEF(9,16)
+#define GPIO_SERIAL_IO_UART_RTS GPIO_NATIVE_FUNCTION_DEF(17,24)
+#define GPIO_SERIAL_IO_UART_CTS GPIO_NATIVE_FUNCTION_DEF(25,31)
+#define GPIO_SERIAL_IO_SPI_MOSI GPIO_NATIVE_FUNCTION_DEF(32,39)
+#define GPIO_SERIAL_IO_SPI_MISO GPIO_NATIVE_FUNCTION_DEF(40,47)
+#define GPIO_SERIAL_IO_SPI_CLK GPIO_NATIVE_FUNCTION_DEF(48,55)
+#define GPIO_SERIAL_IO_SPI_CS GPIO_NATIVE_FUNCTION_DEF(56,71)
+#define GPIO_ISH_GP GPIO_NATIVE_FUNCTION_DEF(80,143)
+#define GPIO_ISH_UART_RX GPIO_NATIVE_FUNCTION_DEF(144,151)
+#define GPIO_ISH_UART_TX GPIO_NATIVE_FUNCTION_DEF(152,159)
+#define GPIO_ISH_UART_RTS GPIO_NATIVE_FUNCTION_DEF(160,167)
+#define GPIO_ISH_UART_CTS GPIO_NATIVE_FUNCTION_DEF(168,175)
+#define GPIO_ISH_SPI_MOSI GPIO_NATIVE_FUNCTION_DEF(184,191)
+#define GPIO_ISH_SPI_MISO GPIO_NATIVE_FUNCTION_DEF(192,199)
+#define GPIO_ISH_SPI_CLK GPIO_NATIVE_FUNCTION_DEF(200,207)
+#define GPIO_ISH_SPI_CS GPIO_NATIVE_FUNCTION_DEF(208,223)
+#define GPIO_ISH_I2C_SCL GPIO_NATIVE_FUNCTION_DEF(232,239)
+#define GPIO_ISH_I2C_SDA GPIO_NATIVE_FUNCTION_DEF(240,247)
+#define GPIO_THC_SPI_INT GPIO_NATIVE_FUNCTION_DEF(248,251)
+#define GPIO_DMIC_DATA GPIO_NATIVE_FUNCTION_DEF(258,261)
+#define GPIO_DMIC_CLKA GPIO_NATIVE_FUNCTION_DEF(262,265)
+#define GPIO_DMIC_CLKB GPIO_NATIVE_FUNCTION_DEF(266,269)
+#define GPIO_DDSP_HPD0 GPIO_NATIVE_FUNCTION_DEF(270,285)
+#define GPIO_PANEL_AVDD_EN GPIO_NATIVE_FUNCTION_DEF(286,289)
+#define GPIO_PANEL_BKLTEN GPIO_NATIVE_FUNCTION_DEF(290,293)
+#define GPIO_PANEL_BKLTCTL GPIO_NATIVE_FUNCTION_DEF(294,297)
+#define GPIO_PANEL_RESET GPIO_NATIVE_FUNCTION_DEF(298,301)
+#define GPIO_PANEL_AVEE_EN GPIO_NATIVE_FUNCTION_DEF(302,305)
+#define GPIO_PANEL_VIO_EN GPIO_NATIVE_FUNCTION_DEF(306,309)
+#define GPIO_PANEL_HPD GPIO_NATIVE_FUNCTION_DEF(310,313)
+#define GPIO_PANEL_TE_EN GPIO_NATIVE_FUNCTION_DEF(314,317)
+#define GPIO_HDMI_GMBUS_SCL GPIO_NATIVE_FUNCTION_DEF(318,325)
+#define GPIO_HDMI_GMBUS_SDA GPIO_NATIVE_FUNCTION_DEF(326,333)
+#define GPIO_SERIAL_IO_I2C_SCL GPIO_NATIVE_FUNCTION_DEF(338,353)
+#define GPIO_SERIAL_IO_I2C_SDA GPIO_NATIVE_FUNCTION_DEF(354,369)
+#define GPIO_SD_DATA GPIO_NATIVE_FUNCTION_DEF(374,377)
+#define GPIO_EMMC_DATA GPIO_NATIVE_FUNCTION_DEF(384,391)
+#define GPIO_THC_CLK_LOOPBACK GPIO_NATIVE_FUNCTION_DEF(395,396)
+#define GPIO_MIPI_PANEL_RESET GPIO_NATIVE_FUNCTION_DEF(401,404)
+#define GPIO_MIPI_SEC_POW_EN_AVEE GPIO_NATIVE_FUNCTION_DEF(405,408)
+#define GPIO_MIPI_SEC_POW_EN_AVDD GPIO_NATIVE_FUNCTION_DEF(409,412)
+#define GPIO_THC_WOT GPIO_NATIVE_FUNCTION_DEF(413,414)
+#define GPIO_SATA_DEVSLP GPIO_NATIVE_FUNCTION_DEF(415,446)
+#define GPIO_PCIE_CLKREQ GPIO_NATIVE_FUNCTION_DEF(447,478)
+
+//
+// Serial IO UART
+//
+
+#define GPIO_FUNCTION_SERIAL_IO_UART_RX(UartDev) (GPIO_SERIAL_IO_UART_RX + ((UINT32)UartDev))
+#define GPIO_FUNCTION_SERIAL_IO_UART_TX(UartDev) (GPIO_SERIAL_IO_UART_TX + ((UINT32)UartDev))
+#define GPIO_FUNCTION_SERIAL_IO_UART_RTS(UartDev) (GPIO_SERIAL_IO_UART_RTS + ((UINT32)UartDev))
+#define GPIO_FUNCTION_SERIAL_IO_UART_CTS(UartDev) (GPIO_SERIAL_IO_UART_CTS + ((UINT32)UartDev))
+
+//
+// Serial IO SPI
+//
+#define GPIO_SERIAL_IO_SPI_RANGE 8 // Number of SerialIo SPIx controllers supported in GPIO_NATIVE_PAD encoding
+
+#define GPIO_FUNCTION_SERIAL_IO_SPI_MOSI(SpiDev) (GPIO_SERIAL_IO_SPI_MOSI + ((UINT32)SpiDev))
+#define GPIO_FUNCTION_SERIAL_IO_SPI_MISO(SpiDev) (GPIO_SERIAL_IO_SPI_MISO + ((UINT32)SpiDev))
+#define GPIO_FUNCTION_SERIAL_IO_SPI_CLK(SpiDev) (GPIO_SERIAL_IO_SPI_CLK + ((UINT32)SpiDev))
+#define GPIO_FUNCTION_SERIAL_IO_SPI_CS(SpiDev, CsNum) (GPIO_SERIAL_IO_SPI_CS + ((UINT32)SpiDev) + ((UINT32)CsNum) * GPIO_SERIAL_IO_SPI_RANGE)
+
+//
+// Serial IO I2C
+//
+
+#define GPIO_FUNCTION_SERIAL_IO_I2C_SCL(I2cDev) (GPIO_SERIAL_IO_I2C_SCL + ((UINT32)I2cDev))
+#define GPIO_FUNCTION_SERIAL_IO_I2C_SDA(I2cDev) (GPIO_SERIAL_IO_I2C_SDA + ((UINT32)I2cDev))
+
+//
+// ISH GP
+//
+
+#define GPIO_FUNCTION_ISH_GP(GpNum) (GPIO_ISH_GP + ((UINT32)GpNum))
+
+//
+// ISH UART
+//
+
+#define GPIO_FUNCTION_ISH_UART_RX(UartDev) (GPIO_ISH_UART_RX + ((UINT32)UartDev))
+#define GPIO_FUNCTION_ISH_UART_TX(UartDev) (GPIO_ISH_UART_TX + ((UINT32)UartDev))
+#define GPIO_FUNCTION_ISH_UART_RTS(UartDev) (GPIO_ISH_UART_RTS + ((UINT32)UartDev))
+#define GPIO_FUNCTION_ISH_UART_CTS(UartDev) (GPIO_ISH_UART_CTS + ((UINT32)UartDev))
+
+//
+// ISH SPI
+//
+#define GPIO_ISH_SPI_RANGE 8 // Number of ISH SPI controllers supported in GPIO_NATIVE_PAD encoding
+
+#define GPIO_FUNCTION_ISH_SPI_MOSI(SpiDev) (GPIO_ISH_SPI_MOSI + ((UINT32)SpiDev))
+#define GPIO_FUNCTION_ISH_SPI_MISO(SpiDev) (GPIO_ISH_SPI_MISO + ((UINT32)SpiDev))
+#define GPIO_FUNCTION_ISH_SPI_CLK(SpiDev) (GPIO_ISH_SPI_CLK + ((UINT32)SpiDev))
+#define GPIO_FUNCTION_ISH_SPI_CS(SpiDev, CsNum) (GPIO_ISH_SPI_CS + ((UINT32)SpiDev) + ((UINT32)CsNum) * GPIO_ISH_SPI_RANGE)
+
+//
+// ISH I2C
+//
+
+#define GPIO_FUNCTION_ISH_I2C_SCL(I2cDev) (GPIO_ISH_I2C_SCL + ((UINT32)I2cDev))
+#define GPIO_FUNCTION_ISH_I2C_SDA(I2cDev) (GPIO_ISH_I2C_SDA + ((UINT32)I2cDev))
+
+//
+// SD Card
+//
+#define GPIO_FUNCTION_SD_DATA(Index) (GPIO_SD_DATA + ((UINT32)Index))
+
+//
+// EMMC
+//
+#define GPIO_FUNCTION_EMMC_DATA(Index) (GPIO_EMMC_DATA + ((UINT32)Index))
+
+//
+// THC SPI
+//
+
+#define GPIO_FUNCTION_THC_SPI_INT(SpiDev) (GPIO_THC_SPI_INT + ((UINT32)SpiDev))
+#define GPIO_FUNCTION_THC_CLK_LOOPBACK(SpiDev) (GPIO_THC_CLK_LOOPBACK + ((UINT32)SpiDev))
+#define GPIO_FUNCTION_THC_WOT(SpiDev) (GPIO_THC_WOT + ((UINT32)SpiDev))
+
+
+//
+// DMIC
+//
+
+#define GPIO_FUNCTION_DMIC_DATA(DmicDev) (GPIO_DMIC_DATA + ((UINT32)DmicDev))
+#define GPIO_FUNCTION_DMIC_CLKA(DmicDev) (GPIO_DMIC_CLKA + ((UINT32)DmicDev))
+#define GPIO_FUNCTION_DMIC_CLKB(DmicDev) (GPIO_DMIC_CLKB + ((UINT32)DmicDev))
+#define GPIO_FUNCTION_DMIC_CLK(DmicDev) (GPIO_DMIC_CLKA + ((UINT32)DmicDev)) // If there is no split between channel A/B use A range for such Clocks
+
+
+//
+// DDSP HPD
+//
+
+#define GPIO_FUNCTION_DDSP_HPD(HpdIndex) \
+ (HpdIndex > 7) ? GPIO_DDSP_HPD0 + 8 + (HpdIndex) - 'A' : GPIO_DDSP_HPD0 + HpdIndex
+
+//
+// HDMI_GMBUS
+//
+
+#define GPIO_FUNCTION_HDMI_SCL(DdiPort) (GPIO_HDMI_GMBUS_SCL + ((UINT32)DdiPort))
+#define GPIO_FUNCTION_HDMI_SDA(DdiPort) (GPIO_HDMI_GMBUS_SDA + ((UINT32)DdiPort))
+
+//
+// Panel
+//
+
+#define GPIO_FUNCTION_PANEL_AVDD_EN(PanelDev) (GPIO_PANEL_AVDD_EN + ((UINT32)PanelDev))
+#define GPIO_FUNCTION_PANEL_BKLTEN(PanelDev) (GPIO_PANEL_BKLTEN + ((UINT32)PanelDev))
+#define GPIO_FUNCTION_PANEL_BKLTCTL(PanelDev) (GPIO_PANEL_BKLTCTL + ((UINT32)PanelDev))
+#define GPIO_FUNCTION_PANEL_RESET(PanelDev) (GPIO_PANEL_RESET + ((UINT32)PanelDev))
+#define GPIO_FUNCTION_PANEL_AVEE_EN(PanelDev) (GPIO_PANEL_AVEE_EN + ((UINT32)PanelDev))
+#define GPIO_FUNCTION_PANEL_VIO_EN(PanelDev) (GPIO_PANEL_VIO_EN + ((UINT32)PanelDev))
+#define GPIO_FUNCTION_PANEL_HPD(PanelDev) (GPIO_PANEL_HPD + ((UINT32)PanelDev))
+#define GPIO_FUNCTION_PANEL_TE_EN(PanelDev) (GPIO_PANEL_TE_EN + ((UINT32)PanelDev))
+
+//
+// MIPI
+//
+#define GPIO_FUNCTION_MIPI_PANEL_RESET(PanelDev) (GPIO_MIPI_PANEL_RESET + ((UINT32)PanelDev))
+#define GPIO_FUNCTION_MIPI_SEC_POW_EN_AVEE(PanelDev) (GPIO_MIPI_SEC_POW_EN_AVEE + ((UINT32)PanelDev))
+#define GPIO_FUNCTION_MIPI_SEC_POW_EN_AVDD(PanelDev) (GPIO_MIPI_SEC_POW_EN_AVDD + ((UINT32)PanelDev))
+
+
+//
+// SATA DevSlp
+//
+#define GPIO_SATA_DEVSLP_RANGE 32 // Number of SATA DevSlp instances per controller supported in GPIO_NATIVE_PAD encoding
+
+#define GPIO_FUNCTION_SATA_DEVSLP(CsNum, SataDevSlpIndex) (GPIO_SATA_DEVSLP + ((UINT32)SataDevSlpIndex) + ((UINT32)CsNum) * GPIO_SATA_DEVSLP_RANGE)
+
+//
+// SRC CLKREQ
+//
+
+#define GPIO_FUNCTION_PCIE_CLKREQ(ClkReqIndex) (GPIO_PCIE_CLKREQ + ((UINT32)ClkReqIndex))
+
+#endif // _GPIO_NATIVE_PADS_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/IncludePrivate/Library/GpioPrivateLib.h b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/IncludePrivate/Library/GpioPrivateLib.h
new file mode 100644
index 0000000000..a757a4b057
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/IncludePrivate/Library/GpioPrivateLib.h
@@ -0,0 +1,350 @@
+/** @file
+ Header file for GpioPrivateLib.
+ All function in this library is available for PEI, DXE, and SMM,
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _GPIO_PRIVATE_LIB_H_
+#define _GPIO_PRIVATE_LIB_H_
+
+#include <Uefi/UefiBaseType.h>
+#include <Library/GpioConfig.h>
+#include <Library/PchPcrLib.h>
+
+/**
+ GPIO Standby State configuration
+ Standby State options for GPIO Pads
+**/
+typedef enum {
+ GpioIosStateDefault = 0x0,
+ GpioIosStateLatchLastValue = (0x0 << 1) | 0x01, ///< Latch last value driven on TX, TX Enable and RX Enable
+ GpioIosStateTx0Rx0RxDis = (0x1 << 1) | 0x01, ///< TX: 0, RX: 0 (internally), RX disabled
+ GpioIosStateTx0Rx1RxDis = (0x2 << 1) | 0x01, ///< TX: 0, RX: 1 (internally), RX disabled
+ GpioIosStateTx1Rx0RxDis = (0x3 << 1) | 0x01, ///< TX: 1, RX: 0 (internally), RX disabled
+ GpioIosStateTx1Rx1RxDis = (0x4 << 1) | 0x01, ///< TX: 1, RX: 1 (internally), RX disabled
+ GpioIosStateTx0RxEn = (0x5 << 1) | 0x01, ///< TX: 0, RX enabled
+ GpioIosStateTx1RxEn = (0x6 << 1) | 0x01, ///< TX: 1, RX enabled
+ GpioIosStateHizRx0 = (0x7 << 1) | 0x01, ///< Hi-Z, RX: 0 (internally)
+ GpioIosStateHizRx1 = (0x8 << 1) | 0x01, ///< Hi-Z, RX: 1 (internally)
+ GpioIosStateTxDisRxEn = (0x9 << 1) | 0x01, ///< TX Disabled and RX Enabled (i.e. wake or interrupt)
+ GpioIosStateMasked = (0xF << 1) | 0x01 ///< IO Standby signal is masked for this pad. In this mode, a pad operates as if IOStandby has not been asserted.
+} GPIO_IOSTANDBY_STATE;
+
+/**
+ GPIO Standby Term configuration
+ Standby Termination options for GPIO Pads
+**/
+typedef enum {
+ GpioIosTermDefault = 0x00,
+ GpioIosTermSame = (0x00 << 1) | 0x01, ///< Same as state specified in Term
+ GpioIosTermPuDisPdDis = (0x01 << 1) | 0x01, ///< Disable Pullup and Pulldown
+ GpioIosTermPuDisPdEn = (0x02 << 1) | 0x01, ///< Enable Pulldown
+ GpioIosTermPuEnPdDis = (0x03 << 1) | 0x01 ///< Enable Pullup
+} GPIO_IOSTANDBY_TERM;
+
+//
+// Structure for native pin data
+//
+typedef struct {
+ GPIO_PAD Pad;
+ GPIO_PAD_MODE Mode;
+ GPIO_IOSTANDBY_STATE IosState;
+ GPIO_IOSTANDBY_TERM IosTerm;
+} GPIO_PAD_NATIVE_FUNCTION;
+
+//
+// Structure for Serial GPIO pin definition
+//
+typedef struct {
+ GPIO_PAD_NATIVE_FUNCTION Sclock;
+ GPIO_PAD_NATIVE_FUNCTION Sload;
+ GPIO_PAD_NATIVE_FUNCTION Sdataout;
+} SGPIO_PINS;
+
+//
+// Structure for USB Virtual Wire OverCurrent Pad Mode group
+//
+typedef struct {
+ GPIO_PAD OcRxPad;
+ GPIO_PAD OcTxPad;
+} GPIO_VWOC_FUNCTION;
+
+//
+// Below defines are based on GPIO_CONFIG structure fields
+//
+#define B_GPIO_PAD_MODE_MASK 0xF
+#define N_GPIO_PAD_MODE_BIT_POS 0
+#define B_GPIO_DIRECTION_DIR_MASK 0x7
+#define N_GPIO_DIRECTION_DIR_BIT_POS 0
+#define B_GPIO_DIRECTION_INV_MASK 0x18
+#define N_GPIO_DIRECTION_INV_BIT_POS 3
+#define B_GPIO_OUTPUT_MASK 0x3
+#define N_GPIO_OUTPUT_BIT_POS 0
+#define N_GPIO_INT_CONFIG_INT_SOURCE_BIT_POS 0
+#define N_GPIO_INT_CONFIG_INT_TYPE_BIT_POS 5
+#define N_GPIO_ELECTRICAL_CONFIG_TERMINATION_BIT_POS 0
+#define N_GPIO_OTHER_CONFIG_RXRAW_BIT_POS 0
+
+//
+// Structure for storing information about registers offset, community,
+// maximal pad number for available groups
+//
+typedef struct {
+ PCH_SBI_PID Community;
+ UINT16 PadOwnOffset;
+ UINT16 HostOwnOffset;
+ UINT16 GpiIsOffset;
+ UINT16 GpiIeOffset;
+ UINT16 GpiGpeStsOffset;
+ UINT16 GpiGpeEnOffset;
+ UINT16 SmiStsOffset;
+ UINT16 SmiEnOffset;
+ UINT16 NmiStsOffset;
+ UINT16 NmiEnOffset;
+ UINT16 PadCfgLockOffset;
+ UINT16 PadCfgLockTxOffset;
+ UINT16 PadCfgOffset;
+ UINT16 PadPerGroup;
+} GPIO_GROUP_INFO;
+
+//
+// If in GPIO_GROUP_INFO structure certain register doesn't exist
+// it will have value equal to NO_REGISTER_FOR_PROPERTY
+//
+#define NO_REGISTER_FOR_PROPERTY 0xFFFF
+
+#define GPIO_PAD_DEF(Group,Pad) (UINT32)(((Group) << 16) + (Pad))
+#define GPIO_GROUP_DEF(GroupIndex,ChipsetId) ((GroupIndex) | ((ChipsetId) << 8))
+#define GPIO_GET_GROUP_INDEX(Group) ((Group) & 0x1F)
+#define GPIO_GET_GROUP_FROM_PAD(GpioPad) (((GpioPad) & 0x0F1F0000) >> 16)
+#define GPIO_GET_GROUP_INDEX_FROM_PAD(GpioPad) GPIO_GET_GROUP_INDEX (GPIO_GET_GROUP_FROM_PAD(GpioPad))
+#define GPIO_GET_PAD_NUMBER(GpioPad) ((GpioPad) & 0x1FF)
+#define GPIO_GET_CHIPSET_ID(GpioPad) (((GpioPad) >> 24) & 0xF)
+
+#define GPIO_GET_PAD_POSITION(PadNumber) ((PadNumber) % 32)
+#define GPIO_GET_DW_NUM(PadNumber) ((PadNumber) / 32u)
+
+/**
+ This procedure will retrieve address and length of GPIO info table
+
+ @param[out] GpioGroupInfoTableLength Length of GPIO group table
+
+ @retval Pointer to GPIO group table
+**/
+CONST GPIO_GROUP_INFO*
+GpioGetGroupInfoTable (
+ OUT UINT32 *GpioGroupInfoTableLength
+ );
+
+typedef struct {
+ CONST CHAR8* GpioGroupPrefix;
+ CONST GPIO_PAD FirstUniqueGpio;
+ CONST CHAR8** GroupUniqueNames;
+ CONST UINT32 UniqueNamesTableSize;
+} GPIO_GROUP_NAME_INFO;
+
+//
+// Helper macros for initializing GPIO_GROUP_NAME_INFO structures
+//
+#define GPIO_GROUP_NAME(GroupName,FirstUniqueGpio,GroupUniqueNamesTable) \
+ {GroupName, FirstUniqueGpio, GroupUniqueNamesTable, ARRAY_SIZE (GroupUniqueNamesTable)}
+
+#define GPIO_GROUP_NAME_BASIC(GroupName) \
+ {GroupName, 0, NULL, 0}
+
+/**
+ Get GPIO Chipset ID specific to PCH generation and series
+**/
+UINT32
+GpioGetThisChipsetId (
+ VOID
+ );
+
+/**
+ This procedure is used to check if GpioPad is valid for certain chipset
+
+ @param[in] GpioPad GPIO pad
+
+ @retval TRUE This pin is valid on this chipset
+ FALSE Incorrect pin
+**/
+BOOLEAN
+GpioIsCorrectPadForThisChipset (
+ IN GPIO_PAD GpioPad
+ );
+
+
+/**
+ This procedure is used by PchSmiDispatcher and will return information
+ needed to register GPI SMI.
+
+ @param[in] Index GPI SMI number
+ @param[out] GpioPin GPIO pin
+ @param[out] GpiSmiBitOffset GPI SMI bit position within GpiSmi Registers
+ @param[out] GpiHostSwOwnRegAddress Address of HOSTSW_OWN register
+ @param[out] GpiSmiStsRegAddress Address of GPI SMI status register
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid group or pad number
+**/
+EFI_STATUS
+GpioGetPadAndSmiRegs (
+ IN UINT32 Index,
+ OUT GPIO_PAD *GpioPin,
+ OUT UINT8 *GpiSmiBitOffset,
+ OUT UINT32 *GpiHostSwOwnRegAddress,
+ OUT UINT32 *GpiSmiStsRegAddress
+ );
+
+/**
+ This procedure calculates Pad Configuration Register DW offset
+
+ @param[in] GpioPad GPIO pad
+ @param[in] DwReg Index of the configuration register
+
+ @retval DW Register offset
+**/
+UINT32
+GpioGetGpioPadCfgAddressFromGpioPad (
+ IN GPIO_PAD GpioPad,
+ IN UINT32 DwReg
+ );
+
+
+/**
+ This procedure will check if GpioPad argument is valid.
+ Function will check below conditions:
+ - GpioPad represents a pad for current PCH
+ - GpioPad belongs to valid GpioGroup
+ - GPIO PadNumber is not greater than number of pads for this group
+
+ @param[in] GpioPad GPIO pad
+
+ @retval TRUE GPIO pad is valid and can be used with GPIO lib API
+ @retval FALSE GPIO pad is invalid and cannot be used with GPIO lib API
+**/
+BOOLEAN
+GpioIsPadValid (
+ IN GPIO_PAD GpioPad
+ );
+
+/**
+ This procedure will read GPIO Pad Configuration register
+
+ @param[in] GpioPad GPIO pad
+ @param[in] DwReg Choose PADCFG register: 0:DW0, 1:DW1
+
+ @retval PadCfgRegValue PADCFG_DWx value
+**/
+UINT32
+GpioReadPadCfgReg (
+ IN GPIO_PAD GpioPad,
+ IN UINT8 DwReg
+ );
+
+/**
+ Check if 0x13 opcode supported for writing to GPIO lock unlock register
+
+ @retval TRUE It's supported
+ @retval FALSE It's not supported
+**/
+BOOLEAN
+IsGpioLockOpcodeSupported (
+ VOID
+ );
+
+/**
+ Gpio Minimum Set
+
+ Set of Gpio Minimum function to use in Pre Mem phase.
+ To optimise execution and reduce memory footprint thse minimum version
+ of 'full' functions are stripped from:
+ - GpioPad PCH validation
+ - GpioPad Group belonging validation
+ - GpioPad Host ownership validation
+ - IoStandbyState configuration
+ The use of below functions has to be careful and with full
+ understanding of all pros and cons. Please refer to GpioPrivateLib.c
+ to familiarize with details of implementation.
+**/
+
+/**
+ This procedure reads GPIO register
+
+ @param[in] GpioGroupInfo Pointer to GPIO group table info
+ @param[in] Register Register offset
+
+ @retval Register value or "F"s in case of errors
+**/
+UINT32
+GpioRegisterAccessRead32 (
+ IN CONST GPIO_GROUP_INFO *GpioGroupInfo,
+ IN UINT32 Register
+ );
+
+/**
+ This procedure writes GPIO register
+
+ @param[in] GpioGroupInfo Pointer to GPIO group table info
+ @param[in] Register Register offset
+ @param[in] AndValue And value
+ @param[in] OrValue Or value
+
+ @retval EFI_DEVICE_ERROR vGPIO BAR not programmed
+ EFI_SUCCESS Operation completed successfully
+**/
+EFI_STATUS
+GpioRegisterAccessAndThenOr32 (
+ IN CONST GPIO_GROUP_INFO *GpioGroupInfo,
+ IN UINT32 Register,
+ IN UINT32 AndValue,
+ IN UINT32 OrValue
+ );
+
+/**
+ This procedure will calculate PADCFG register value based on GpioConfig data
+ The procedure can be various depending on chipset generation.
+ Available configuration options and corresponding registers fields
+ can distributed in different way in configuration registers.
+
+ @param[in] GpioPad GPIO Pad
+ @param[in] GpioConfig GPIO Configuration data
+ @param[out] PadCfgDwReg PADCFG DWx register value
+ @param[out] PadCfgDwRegMask Mask with PADCFG DWx register bits to be modified
+
+ @retval Status
+**/
+EFI_STATUS
+GpioPadCfgRegValueFromGpioConfig (
+ IN GPIO_PAD GpioPad,
+ IN CONST GPIO_CONFIG *GpioConfig,
+ OUT UINT32 *PadCfgDwReg,
+ OUT UINT32 *PadCfgDwRegMask
+ );
+
+/**
+ This procedure will write GPIO Lock/LockTx register
+ - For PCH SBI message is used.
+ - For IBL MMIO access is used.
+
+ @param[in] RegValue GPIO register (Lock or LockTx) value
+ @param[in] RegOffset GPIO register (Lock or LockTx) base offset
+ @param[in] DwNum Register number for current group.
+ For group which has less then 32 pads per group DwNum must be 0.
+ @param[in] GpioGroupInfo Pointer to GPIO group table info
+ @param[in] GroupIndex GPIO group index in the GpioGroupInfo table
+
+ @retval EFI_SUCCESS The function completed successfully
+ EFI_UNSUPPORTED Feature is not supported for this group or pad
+**/
+EFI_STATUS
+GpioInternalWriteLockRegister (
+ IN UINT32 RegValue,
+ IN UINT32 RegOffset,
+ IN UINT32 DwNum,
+ IN CONST GPIO_GROUP_INFO *GpioGroupInfo,
+ IN UINT32 GroupIndex
+ );
+
+#endif // _GPIO_PRIVATE_LIB_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/Library/PeiDxeSmmGpioLib/GpioInit.c b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/Library/PeiDxeSmmGpioLib/GpioInit.c
new file mode 100644
index 0000000000..cf6f92a50d
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/Library/PeiDxeSmmGpioLib/GpioInit.c
@@ -0,0 +1,546 @@
+/** @file
+ This file contains routines for GPIO initialization
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#include "GpioLibrary.h"
+
+//
+// GPIO_GROUP_DW_DATA structure is used by GpioConfigurePch function
+// to cache values which will be programmed into respective GPIO registers
+// after all GpioPads are processed. This way MMIO accesses are decreased
+// and instead of doing one programming for one GpioPad there is only
+// one access for whole register.
+//
+typedef struct {
+ UINT32 HostSoftOwnReg;
+ UINT32 HostSoftOwnRegMask;
+ UINT32 GpiGpeEnReg;
+ UINT32 GpiGpeEnRegMask;
+ UINT32 GpiNmiEnReg;
+ UINT32 GpiNmiEnRegMask;
+ UINT32 GpiSmiEnReg;
+ UINT32 GpiSmiEnRegMask;
+ UINT32 ConfigUnlockMask;
+ UINT32 OutputUnlockMask;
+} GPIO_GROUP_DW_DATA;
+
+//
+// GPIO_GROUP_DW_NUMBER contains number of DWords required to
+// store Pad data for all groups. Each pad uses one bit.
+//
+// For Cannonlake only vGPIO group has >32 pads but those pads
+// will not be accessed by this function so GPIO_GROUP_DW_NUMBER can be 1
+//
+#define GPIO_GROUP_DW_NUMBER 1
+
+/**
+ Get GPIO DW Register values (HOSTSW_OWN, GPE_EN, NMI_EN, Lock).
+
+ @param[in] PadNumber GPIO pad number
+ @param[in] GpioConfig GPIO Config data
+ @param[in out] DwRegsValues Values for GPIO DW Registers
+
+ @retval None
+**/
+STATIC
+VOID
+GpioDwRegValueFromGpioConfig (
+ IN UINT32 PadNumber,
+ IN CONST GPIO_CONFIG *GpioConfig,
+ IN OUT GPIO_GROUP_DW_DATA *GroupDwData
+ )
+{
+ UINT32 PadBitPosition;
+ UINT32 DwNum;
+
+ PadBitPosition = GPIO_GET_PAD_POSITION (PadNumber);
+ DwNum = GPIO_GET_DW_NUM (PadNumber);
+
+ if (DwNum >= GPIO_GROUP_DW_NUMBER) {
+ ASSERT (FALSE);
+ return;
+ }
+ //
+ // Update value to be programmed in HOSTSW_OWN register
+ //
+ GroupDwData[DwNum].HostSoftOwnRegMask |= (GpioConfig->HostSoftPadOwn & 0x1) << PadBitPosition;
+ GroupDwData[DwNum].HostSoftOwnReg |= (GpioConfig->HostSoftPadOwn >> 0x1) << PadBitPosition;
+
+ //
+ // Update value to be programmed in GPI_GPE_EN register
+ //
+ GroupDwData[DwNum].GpiGpeEnRegMask |= (GpioConfig->InterruptConfig & 0x1) << PadBitPosition;
+ GroupDwData[DwNum].GpiGpeEnReg |= ((GpioConfig->InterruptConfig & GpioIntSci) >> 3) << PadBitPosition;
+
+ //
+ // Update value to be programmed in GPI_NMI_EN register
+ //
+ GroupDwData[DwNum].GpiNmiEnRegMask |= (GpioConfig->InterruptConfig & 0x1) << PadBitPosition;
+ GroupDwData[DwNum].GpiNmiEnReg |= ((GpioConfig->InterruptConfig & GpioIntNmi) >> 1) << PadBitPosition;
+
+ //
+ // Update value to be programmed in GPI_SMI_EN register
+ GroupDwData[DwNum].GpiSmiEnRegMask |= (GpioConfig->InterruptConfig & 0x1) << PadBitPosition;
+ GroupDwData[DwNum].GpiSmiEnReg |= ((GpioConfig->InterruptConfig & GpioIntSmi) >> 2) << PadBitPosition;
+ if ((GpioConfig->InterruptConfig & GpioIntSmi) == GpioIntSmi) {
+ GroupDwData[DwNum].HostSoftOwnRegMask |= 1 << PadBitPosition;
+ GroupDwData[DwNum].HostSoftOwnReg |= 1 << PadBitPosition;
+ }
+
+ //
+ // Update information on Pad Configuration Lock
+ //
+ GroupDwData[DwNum].ConfigUnlockMask |= ((GpioConfig->LockConfig >> 1) & 0x1) << PadBitPosition;
+
+ //
+ // Update information on Pad Configuration Lock Tx
+ //
+ GroupDwData[DwNum].OutputUnlockMask |= ((GpioConfig->LockConfig >> 3) & 0x1) << PadBitPosition;
+
+ //
+ // if pad in GpioMode is an output default action should be to leave output unlocked
+ //
+ if ((GpioConfig->PadMode == GpioPadModeGpio) &&
+ (GpioConfig->Direction == GpioDirOut) &&
+ ((GpioConfig->LockConfig & B_GPIO_LOCK_CONFIG_OUTPUT_LOCK_MASK) == GpioLockDefault)) {
+ GroupDwData[DwNum].OutputUnlockMask |= 0x1 << PadBitPosition;
+ }
+}
+
+/**
+ This internal procedure will scan GPIO initialization table and unlock
+ all pads present in it
+
+ @param[in] NumberOfItem Number of GPIO pad records in table
+ @param[in] GpioInitTableAddress GPIO initialization table
+ @param[in] Index Index of GPIO Initialization table record
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid group or pad number
+**/
+STATIC
+EFI_STATUS
+GpioUnlockPadsForAGroup (
+ IN UINT32 NumberOfItems,
+ IN GPIO_INIT_CONFIG *GpioInitTableAddress,
+ IN UINT32 Index
+ )
+{
+ UINT32 PadsToUnlock[GPIO_GROUP_DW_NUMBER];
+ UINT32 DwNum;
+ UINT32 PadBitPosition;
+ CONST GPIO_GROUP_INFO *GpioGroupInfo;
+ UINT32 GpioGroupInfoLength;
+ CONST GPIO_INIT_CONFIG *GpioData;
+ GPIO_GROUP Group;
+ UINT32 GroupIndex;
+ UINT32 PadNumber;
+
+ GpioGroupInfo = GpioGetGroupInfoTable (&GpioGroupInfoLength);
+
+ GpioData = &GpioInitTableAddress[Index];
+ Group = GpioGetGroupFromGpioPad (GpioData->GpioPad);
+ GroupIndex = GpioGetGroupIndexFromGpioPad (GpioData->GpioPad);
+
+ ZeroMem (PadsToUnlock, sizeof (PadsToUnlock));
+ //
+ // Loop through pads for one group. If pad belongs to a different group then
+ // break and move to register programming.
+ //
+ while (Index < NumberOfItems) {
+
+ GpioData = &GpioInitTableAddress[Index];
+ if (GroupIndex != GpioGetGroupIndexFromGpioPad (GpioData->GpioPad)) {
+ //if next pad is from different group then break loop
+ break;
+ }
+
+ PadNumber = GpioGetPadNumberFromGpioPad (GpioData->GpioPad);
+ //
+ // Check if legal pin number
+ //
+ if (PadNumber >= GpioGroupInfo[GroupIndex].PadPerGroup) {
+ DEBUG ((DEBUG_ERROR, "GPIO ERROR: Pin number (%d) exceeds possible range for group %d\n", PadNumber, GroupIndex));
+ return EFI_INVALID_PARAMETER;
+ }
+
+ PadBitPosition = GPIO_GET_PAD_POSITION (PadNumber);
+ DwNum = GPIO_GET_DW_NUM (PadNumber);
+
+ if (DwNum >= GPIO_GROUP_DW_NUMBER) {
+ ASSERT (FALSE);
+ return EFI_UNSUPPORTED;
+ }
+ //
+ // Update pads which need to be unlocked
+ //
+ PadsToUnlock[DwNum] |= 0x1 << PadBitPosition;
+
+ //Move to next item
+ Index++;
+ }
+
+ for (DwNum = 0; DwNum <= GPIO_GET_DW_NUM (GpioGroupInfo[GroupIndex].PadPerGroup - 1); DwNum++) {
+ //
+ // Unlock pads
+ //
+ if (PadsToUnlock[DwNum] != 0) {
+ GpioUnlockPadCfgForGroupDw (Group, DwNum, PadsToUnlock[DwNum]);
+ GpioUnlockPadCfgTxForGroupDw (Group, DwNum, PadsToUnlock[DwNum]);
+ }
+ }
+
+ return EFI_SUCCESS;
+}
+
+/**
+ This procedure will initialize multiple PCH GPIO pins
+
+ @param[in] NumberofItem Number of GPIO pads to be updated
+ @param[in] GpioInitTableAddress GPIO initialization table
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid group or pad number
+**/
+STATIC
+EFI_STATUS
+GpioConfigurePch (
+ IN UINT32 NumberOfItems,
+ IN GPIO_INIT_CONFIG *GpioInitTableAddress
+ )
+{
+ UINT32 Index;
+ UINT32 PadCfgDwReg[GPIO_PADCFG_DW_REG_NUMBER];
+ UINT32 PadCfgDwRegMask[GPIO_PADCFG_DW_REG_NUMBER];
+ UINT32 PadCfgReg;
+ GPIO_GROUP_DW_DATA GroupDwData[GPIO_GROUP_DW_NUMBER];
+ UINT32 DwNum;
+ CONST GPIO_GROUP_INFO *GpioGroupInfo;
+ UINT32 GpioGroupInfoLength;
+ GPIO_PAD_OWN PadOwnVal;
+ CONST GPIO_INIT_CONFIG *GpioData;
+ UINT32 GroupIndex;
+ UINT32 PadNumber;
+ UINT32 DwRegIndex;
+
+ PadOwnVal = GpioPadOwnHost;
+
+ GpioGroupInfo = GpioGetGroupInfoTable (&GpioGroupInfoLength);
+
+ Index = 0;
+ while (Index < NumberOfItems) {
+
+ GpioData = &GpioInitTableAddress[Index];
+ GroupIndex = GpioGetGroupIndexFromGpioPad (GpioData->GpioPad);
+
+ DEBUG_CODE_BEGIN();
+ if (!GpioIsCorrectPadForThisChipset (GpioData->GpioPad)) {
+ DEBUG ((DEBUG_ERROR, "GPIO ERROR: Incorrect GpioPad (0x%08x) used on this chipset!\n", GpioData->GpioPad));
+ ASSERT (FALSE);
+ return EFI_UNSUPPORTED;
+ }
+ DEBUG_CODE_END ();
+
+ //
+ // Unlock pads for a given group which are going to be reconfigured
+ //
+ //
+ // Because PADCFGLOCK/LOCKTX register reset domain is Powergood, lock settings
+ // will get back to default only after G3 or DeepSx transition. On the other hand GpioPads
+ // configuration is controlled by a configurable type of reset - PadRstCfg. This means that if
+ // PadRstCfg != Powergood GpioPad will have its configuration locked despite it being not the
+ // one desired by BIOS. Before reconfiguring all pads they will get unlocked.
+ //
+ GpioUnlockPadsForAGroup (NumberOfItems, GpioInitTableAddress, Index);
+
+ ZeroMem (GroupDwData, sizeof (GroupDwData));
+ //
+ // Loop through pads for one group. If pad belongs to a different group then
+ // break and move to register programming.
+ //
+ while (Index < NumberOfItems) {
+
+ GpioData = &GpioInitTableAddress[Index];
+ if (GroupIndex != GpioGetGroupIndexFromGpioPad (GpioData->GpioPad)) {
+ //if next pad is from different group then break loop
+ break;
+ }
+
+ PadNumber = GpioGetPadNumberFromGpioPad (GpioData->GpioPad);
+
+ DEBUG_CODE_BEGIN ();
+ //
+ // Check if legal pin number
+ //
+ if (PadNumber >= GpioGroupInfo[GroupIndex].PadPerGroup) {
+ DEBUG ((DEBUG_ERROR, "GPIO ERROR: Pin number (%d) exceeds possible range for group %d\n", PadNumber, GroupIndex));
+ return EFI_INVALID_PARAMETER;
+ }
+
+ //
+ // Check if selected GPIO Pad is not owned by CSME/ISH
+ //
+ GpioGetPadOwnership (GpioData->GpioPad, &PadOwnVal);
+
+ if (PadOwnVal != GpioPadOwnHost) {
+ DEBUG ((DEBUG_ERROR, "GPIO ERROR: Accessing pad not owned by host (Group=%d, Pad=%d)!\n", GroupIndex, PadNumber));
+ DEBUG ((DEBUG_ERROR, "** Please make sure the GPIO usage in sync between CSME and BIOS configuration. \n"));
+ DEBUG ((DEBUG_ERROR, "** All the GPIO occupied by CSME should not do any configuration by BIOS.\n"));
+ //Move to next item
+ goto move_to_next_index;
+ }
+
+ //
+ // Check if Pad enabled for SCI is to be in unlocked state
+ //
+ if (((GpioData->GpioConfig.InterruptConfig & GpioIntSci) == GpioIntSci) &&
+ ((GpioData->GpioConfig.LockConfig & B_GPIO_LOCK_CONFIG_PAD_CONF_LOCK_MASK) != GpioPadConfigUnlock)){
+ DEBUG ((DEBUG_ERROR, "GPIO ERROR: GPIO used for SCI is not unlocked!\n"));
+ ASSERT (FALSE);
+ return EFI_INVALID_PARAMETER;
+ }
+ DEBUG_CODE_END ();
+
+ ZeroMem (PadCfgDwReg, sizeof (PadCfgDwReg));
+ ZeroMem (PadCfgDwRegMask, sizeof (PadCfgDwRegMask));
+ //
+ // Get GPIO PADCFG register value from GPIO config data
+ //
+ GpioPadCfgRegValueFromGpioConfig (
+ GpioData->GpioPad,
+ &GpioData->GpioConfig,
+ PadCfgDwReg,
+ PadCfgDwRegMask
+ );
+
+ //
+ // Write PADCFG DW0, DW1, DW2 registers
+ //
+ for (DwRegIndex = 0; DwRegIndex <= 2; DwRegIndex++) {
+ PadCfgReg = GpioGetGpioPadCfgAddressFromGpioPad (GpioData->GpioPad, DwRegIndex);
+ if (PadCfgReg != 0) {
+ GpioRegisterAccessAndThenOr32 (&GpioGroupInfo[GroupIndex], PadCfgReg, ~PadCfgDwRegMask[DwRegIndex], PadCfgDwReg[DwRegIndex]);
+ }
+ }
+
+ //
+ // Get GPIO DW register values from GPIO config data
+ //
+ GpioDwRegValueFromGpioConfig (
+ PadNumber,
+ &GpioData->GpioConfig,
+ GroupDwData
+ );
+
+ move_to_next_index:
+ //Move to next item
+ Index++;
+ }
+
+ for (DwNum = 0; DwNum <= GPIO_GET_DW_NUM (GpioGroupInfo[GroupIndex].PadPerGroup); DwNum++) {
+ //
+ // Write HOSTSW_OWN registers
+ //
+ if (GpioGroupInfo[GroupIndex].HostOwnOffset != NO_REGISTER_FOR_PROPERTY) {
+ GpioRegisterAccessAndThenOr32 (
+ &GpioGroupInfo[GroupIndex],
+ GpioGroupInfo[GroupIndex].HostOwnOffset + DwNum * 0x4,
+ ~GroupDwData[DwNum].HostSoftOwnRegMask,
+ GroupDwData[DwNum].HostSoftOwnReg
+ );
+ }
+
+ //
+ // Write GPI_GPE_EN registers
+ //
+ if (GpioGroupInfo[GroupIndex].GpiGpeEnOffset != NO_REGISTER_FOR_PROPERTY) {
+ GpioRegisterAccessAndThenOr32 (
+ &GpioGroupInfo[GroupIndex],
+ GpioGroupInfo[GroupIndex].GpiGpeEnOffset + DwNum * 0x4,
+ ~GroupDwData[DwNum].GpiGpeEnRegMask,
+ GroupDwData[DwNum].GpiGpeEnReg
+ );
+ }
+
+ //
+ // Write GPI_NMI_EN registers
+ //
+ if (GpioGroupInfo[GroupIndex].NmiEnOffset != NO_REGISTER_FOR_PROPERTY) {
+ GpioRegisterAccessAndThenOr32 (
+ &GpioGroupInfo[GroupIndex],
+ GpioGroupInfo[GroupIndex].NmiEnOffset + DwNum * 0x4,
+ ~GroupDwData[DwNum].GpiNmiEnRegMask,
+ GroupDwData[DwNum].GpiNmiEnReg
+ );
+ } else if (GroupDwData[DwNum].GpiNmiEnReg != 0x0) {
+ DEBUG ((DEBUG_ERROR, "GPIO ERROR: Group %d has no pads supporting NMI\n", GroupIndex));
+ ASSERT_EFI_ERROR (EFI_UNSUPPORTED);
+ }
+
+ //
+ // Write GPI_SMI_EN registers
+ //
+ if (GpioGroupInfo[GroupIndex].SmiEnOffset != NO_REGISTER_FOR_PROPERTY) {
+ GpioRegisterAccessAndThenOr32 (
+ &GpioGroupInfo[GroupIndex],
+ GpioGroupInfo[GroupIndex].SmiEnOffset + DwNum * 0x4,
+ ~GroupDwData[DwNum].GpiSmiEnRegMask,
+ GroupDwData[DwNum].GpiSmiEnReg
+ );
+ } else if (GroupDwData[DwNum].GpiSmiEnReg != 0x0) {
+ DEBUG ((DEBUG_ERROR, "GPIO ERROR: Group %d has no pads supporting SMI\n", GroupIndex));
+ ASSERT_EFI_ERROR (EFI_UNSUPPORTED);
+ }
+
+ //
+ // Update Pad Configuration unlock data
+ //
+ if (GroupDwData[DwNum].ConfigUnlockMask) {
+ GpioStoreGroupDwUnlockPadConfigData (GroupIndex, DwNum, GroupDwData[DwNum].ConfigUnlockMask);
+ }
+
+ //
+ // Update Pad Output unlock data
+ //
+ if (GroupDwData[DwNum].OutputUnlockMask) {
+ GpioStoreGroupDwUnlockOutputData (GroupIndex, DwNum, GroupDwData[DwNum].OutputUnlockMask);
+ }
+ }
+ }
+
+ return EFI_SUCCESS;
+}
+
+/**
+ This procedure will clear all status bits of any GPIO interrupts.
+
+ @param[in] none
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid group or pad number
+**/
+STATIC
+EFI_STATUS
+GpioClearAllGpioInterrupts (
+ VOID
+ )
+{
+ GPIO_GROUP Group;
+ CONST GPIO_GROUP_INFO *GpioGroupInfo;
+ GPIO_GROUP GpioGroupLowest;
+ GPIO_GROUP GpioGroupHighest;
+ UINT32 GroupIndex;
+ UINT32 GpioGroupInfoLength;
+ UINT32 DwNum;
+
+ GpioGroupInfo = GpioGetGroupInfoTable (&GpioGroupInfoLength);
+
+ GpioGroupLowest = GpioGetLowestGroup ();
+ GpioGroupHighest = GpioGetHighestGroup ();
+
+ for (Group = GpioGroupLowest; Group <= GpioGroupHighest; Group++) {
+ GroupIndex = GpioGetGroupIndexFromGroup (Group);
+ //
+ // Check if group has GPI IS register
+ //
+ if (GpioGroupInfo[GroupIndex].GpiIsOffset != NO_REGISTER_FOR_PROPERTY) {
+ //
+ // Clear all GPI_IS Status bits by writing '1'
+ //
+ for (DwNum = 0; DwNum <= GPIO_GET_DW_NUM (GpioGroupInfo[GroupIndex].PadPerGroup); DwNum++) {
+ GpioRegisterAccessAndThenOr32 (
+ &GpioGroupInfo[GroupIndex],
+ GpioGroupInfo[GroupIndex].GpiIsOffset + DwNum * 0x4,
+ ~(UINT32)0,
+ 0xFFFFFFFF
+ );
+ }
+ }
+
+ //
+ // Check if group has GPI_GPE_STS register
+ //
+ if (GpioGroupInfo[GroupIndex].GpiGpeStsOffset != NO_REGISTER_FOR_PROPERTY) {
+ //
+ // Clear all GPI_GPE_STS Status bits by writing '1'
+ //
+ for (DwNum = 0; DwNum <= GPIO_GET_DW_NUM (GpioGroupInfo[GroupIndex].PadPerGroup); DwNum++) {
+ GpioRegisterAccessAndThenOr32 (
+ &GpioGroupInfo[GroupIndex],
+ GpioGroupInfo[GroupIndex].GpiGpeStsOffset + DwNum * 0x4,
+ ~(UINT32)0,
+ 0xFFFFFFFF
+ );
+ }
+ }
+
+ //
+ // Check if group has SMI_STS register
+ //
+ if (GpioGroupInfo[GroupIndex].SmiStsOffset != NO_REGISTER_FOR_PROPERTY) {
+ //
+ // Clear all SMI_STS Status bits by writing '1'
+ //
+ for (DwNum = 0; DwNum <= GPIO_GET_DW_NUM (GpioGroupInfo[GroupIndex].PadPerGroup); DwNum++) {
+ GpioRegisterAccessAndThenOr32 (
+ &GpioGroupInfo[GroupIndex],
+ GpioGroupInfo[GroupIndex].SmiStsOffset + DwNum * 4,
+ ~(UINT32)0,
+ 0xFFFFFFFF
+ );
+ }
+ }
+
+ //
+ // Check if group has NMI_STS register
+ //
+ if (GpioGroupInfo[GroupIndex].NmiStsOffset != NO_REGISTER_FOR_PROPERTY) {
+ //
+ // Clear all NMI_STS Status bits by writing '1'
+ //
+ for (DwNum = 0; DwNum <= GPIO_GET_DW_NUM (GpioGroupInfo[GroupIndex].PadPerGroup); DwNum++) {
+ GpioRegisterAccessAndThenOr32 (
+ &GpioGroupInfo[GroupIndex],
+ GpioGroupInfo[GroupIndex].NmiStsOffset + DwNum * 4,
+ ~(UINT32)0,
+ 0xFFFFFFFF
+ );
+ }
+ }
+
+ }
+ return EFI_SUCCESS;
+}
+
+/**
+ This procedure will initialize multiple GPIO pins. Use GPIO_INIT_CONFIG structure.
+ Structure contains fields that can be used to configure each pad.
+ Pad not configured using GPIO_INIT_CONFIG will be left with hardware default values.
+ Separate fields could be set to hardware default if it does not matter, except
+ GpioPad and PadMode.
+ Function will work in most efficient way if pads which belong to the same group are
+ placed in adjacent records of the table.
+ Although function can enable pads for Native mode, such programming is done
+ by reference code when enabling related silicon feature.
+
+ @param[in] NumberofItem Number of GPIO pads to be updated
+ @param[in] GpioInitTableAddress GPIO initialization table
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid group or pad number
+**/
+EFI_STATUS
+GpioConfigurePads (
+ IN UINT32 NumberOfItems,
+ IN GPIO_INIT_CONFIG *GpioInitTableAddress
+ )
+{
+ EFI_STATUS Status;
+
+ Status = GpioConfigurePch (NumberOfItems, GpioInitTableAddress);
+
+ GpioClearAllGpioInterrupts ();
+ return Status;
+}
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/Library/PeiDxeSmmGpioLib/GpioLib.c b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/Library/PeiDxeSmmGpioLib/GpioLib.c
new file mode 100644
index 0000000000..19daed97c0
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/Library/PeiDxeSmmGpioLib/GpioLib.c
@@ -0,0 +1,522 @@
+/** @file
+ This file contains routines for GPIO
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#include "GpioLibrary.h"
+#include <Register/PchPcrRegs.h>
+
+/**
+ This procedure will check if GpioGroup argument is correct and
+ supplied DW reg number can be used for this group to access DW registers.
+ Function will check below conditions:
+ - Valid GpioGroup
+ - DwNum is has valid value for this group
+
+ @param[in] Group GPIO group
+ @param[in] DwNum Register number for current group (parameter applicable in accessing whole register).
+ For group which has less then 32 pads per group DwNum must be 0.
+
+ @retval TRUE DW Reg number and GpioGroup is valid
+ @retval FALSE DW Reg number and GpioGroup is invalid
+**/
+STATIC
+BOOLEAN
+GpioIsGroupAndDwNumValid (
+ IN GPIO_GROUP Group,
+ IN UINT32 DwNum
+ )
+{
+ UINT32 GroupIndex;
+ CONST GPIO_GROUP_INFO *GpioGroupInfo;
+ UINT32 GpioGroupInfoLength;
+
+ GpioGroupInfo = GpioGetGroupInfoTable (&GpioGroupInfoLength);
+
+ GroupIndex = GpioGetGroupIndexFromGroup (Group);
+
+ if ((Group < GpioGetLowestGroup ()) || (Group > GpioGetHighestGroup ()) || (GroupIndex >= GpioGroupInfoLength)) {
+ DEBUG ((DEBUG_ERROR, "GPIO ERROR: Group argument (%d) is not within range of possible groups for this PCH\n", GroupIndex));
+ goto Error;
+ }
+
+ //
+ // Check if DwNum argument does not exceed number of DWord registers
+ // resulting from available pads for certain group
+ //
+ if (DwNum > GPIO_GET_DW_NUM (GpioGroupInfo[GroupIndex].PadPerGroup - 1)){
+ goto Error;
+ }
+
+ return TRUE;
+Error:
+ ASSERT (FALSE);
+ return FALSE;
+}
+
+//
+// Possible registers to be accessed using GpioReadReg()/GpioWriteReg() functions
+//
+typedef enum {
+ GpioHostOwnershipRegister = 0,
+ GpioGpeEnableRegister,
+ GpioGpeStatusRegister,
+ GpioSmiEnableRegister,
+ GpioSmiStatusRegister,
+ GpioNmiEnableRegister,
+ GpioPadConfigLockRegister,
+ GpioPadLockOutputRegister
+} GPIO_REG;
+
+/**
+ This procedure will read GPIO register
+
+ @param[in] RegType GPIO register type
+ @param[in] Group GPIO group
+ @param[in] DwNum Register number for current group (parameter applicable in accessing whole register).
+ For group which has less then 32 pads per group DwNum must be 0.
+ @param[out] ReadVal Read data
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_UNSUPPORTED Feature is not supported for this group or pad
+**/
+STATIC
+EFI_STATUS
+GpioReadReg (
+ IN GPIO_REG RegType,
+ IN GPIO_GROUP Group,
+ IN UINT32 DwNum,
+ OUT UINT32 *ReadVal
+ )
+{
+ UINT32 RegOffset;
+ UINT32 GroupIndex;
+ CONST GPIO_GROUP_INFO *GpioGroupInfo;
+ UINT32 GpioGroupInfoLength;
+
+ RegOffset = NO_REGISTER_FOR_PROPERTY;
+ GroupIndex = GpioGetGroupIndexFromGroup (Group);
+
+ GpioGroupInfo = GpioGetGroupInfoTable (&GpioGroupInfoLength);
+
+ switch (RegType) {
+ case GpioHostOwnershipRegister:
+ RegOffset = GpioGroupInfo[GroupIndex].HostOwnOffset;
+ break;
+ case GpioGpeEnableRegister:
+ RegOffset = GpioGroupInfo[GroupIndex].GpiGpeEnOffset;
+ break;
+ case GpioGpeStatusRegister:
+ RegOffset = GpioGroupInfo[GroupIndex].GpiGpeStsOffset;
+ break;
+ case GpioSmiEnableRegister:
+ RegOffset = GpioGroupInfo[GroupIndex].SmiEnOffset;
+ break;
+ case GpioSmiStatusRegister:
+ RegOffset = GpioGroupInfo[GroupIndex].SmiStsOffset;
+ break;
+ case GpioNmiEnableRegister:
+ RegOffset = GpioGroupInfo[GroupIndex].NmiEnOffset;
+ break;
+ case GpioPadConfigLockRegister:
+ RegOffset = GpioGroupInfo[GroupIndex].PadCfgLockOffset;
+ break;
+ case GpioPadLockOutputRegister:
+ RegOffset = GpioGroupInfo[GroupIndex].PadCfgLockTxOffset;
+ break;
+ default:
+ break;
+ }
+
+ //
+ // Check if selected register exists
+ //
+ if (RegOffset == NO_REGISTER_FOR_PROPERTY) {
+ return EFI_UNSUPPORTED;
+ }
+
+ //
+ // If there are more then 32 pads per group then certain
+ // group information would be split into more then one DWord register.
+ //
+ if ((RegType == GpioPadConfigLockRegister) || (RegType == GpioPadLockOutputRegister)) {
+ //
+ // PadConfigLock and OutputLock registers when used for group containing more than 32 pads
+ // are not placed in a continuous way, e.g:
+ // 0x0 - PadConfigLock_DW0
+ // 0x4 - OutputLock_DW0
+ // 0x8 - PadConfigLock_DW1
+ // 0xC - OutputLock_DW1
+ //
+ RegOffset += DwNum * 0x8;
+ } else {
+ RegOffset += DwNum * 0x4;
+ }
+
+ *ReadVal = GpioRegisterAccessRead32 (&GpioGroupInfo[GroupIndex], RegOffset);
+
+ return EFI_SUCCESS;
+}
+
+/**
+ This procedure will write GPIO register
+
+ @param[in] RegType GPIO register type
+ @param[in] Group GPIO group
+ @param[in] DwNum Register number for current group (parameter applicable in accessing whole register).
+ For group which has less then 32 pads per group DwNum must be 0.
+ @param[in] RegAndMask Mask which will be AND'ed with register value
+ @param[in] RegOrMask Mask which will be OR'ed with register value
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_UNSUPPORTED Feature is not supported for this group or pad
+**/
+STATIC
+EFI_STATUS
+GpioWriteReg (
+ IN GPIO_REG RegType,
+ IN GPIO_GROUP Group,
+ IN UINT32 DwNum,
+ IN UINT32 RegAndMask,
+ IN UINT32 RegOrMask
+ )
+{
+ UINT32 RegOffset;
+ UINT32 GroupIndex;
+ CONST GPIO_GROUP_INFO *GpioGroupInfo;
+ UINT32 GpioGroupInfoLength;
+ UINT32 PadCfgLock;
+ BOOLEAN Lockable;
+
+ Lockable = FALSE;
+ PadCfgLock = 0;
+ RegOffset = NO_REGISTER_FOR_PROPERTY;
+ GroupIndex = GpioGetGroupIndexFromGroup (Group);
+
+ GpioGroupInfo = GpioGetGroupInfoTable (&GpioGroupInfoLength);
+
+ switch (RegType) {
+ case GpioHostOwnershipRegister:
+ RegOffset = GpioGroupInfo[GroupIndex].HostOwnOffset;
+ break;
+ case GpioGpeEnableRegister:
+ RegOffset = GpioGroupInfo[GroupIndex].GpiGpeEnOffset;
+ Lockable = TRUE;
+ break;
+ case GpioGpeStatusRegister:
+ RegOffset = GpioGroupInfo[GroupIndex].GpiGpeStsOffset;
+ break;
+ case GpioSmiEnableRegister:
+ RegOffset = GpioGroupInfo[GroupIndex].SmiEnOffset;
+ Lockable = TRUE;
+ break;
+ case GpioSmiStatusRegister:
+ RegOffset = GpioGroupInfo[GroupIndex].SmiStsOffset;
+ break;
+ case GpioNmiEnableRegister:
+ RegOffset = GpioGroupInfo[GroupIndex].NmiEnOffset;
+ Lockable = TRUE;
+ break;
+ case GpioPadConfigLockRegister:
+ case GpioPadLockOutputRegister:
+ default:
+ break;
+ }
+
+ //
+ // Check if selected register exists
+ //
+ if (RegOffset == NO_REGISTER_FOR_PROPERTY) {
+ return EFI_UNSUPPORTED;
+ }
+
+ if (Lockable) {
+ GpioGetPadCfgLockForGroupDw (Group, DwNum, &PadCfgLock);
+ if (PadCfgLock) {
+ //
+ // Check if for pads which are going to be reconfigured lock is set.
+ //
+ if ((~RegAndMask | RegOrMask) & PadCfgLock) {
+ //
+ // Unlock all pads for this Group DW reg for simplicity
+ // even if not all of those pads will have their settings reprogrammed
+ //
+ GpioUnlockPadCfgForGroupDw (Group, DwNum, PadCfgLock);
+ } else {
+ //
+ // No need to perform an unlock as pads which are going to be reconfigured
+ // are not in locked state
+ //
+ PadCfgLock = 0;
+ }
+ }
+ }
+
+ //
+ // If there are more then 32 pads per group then certain
+ // group information would be split into more then one DWord register.
+ //
+ RegOffset += DwNum * 0x4;
+
+ GpioRegisterAccessAndThenOr32 (&GpioGroupInfo[GroupIndex], RegOffset, RegAndMask,RegOrMask);
+
+ if (Lockable && PadCfgLock) {
+ //
+ // Lock previously unlocked pads
+ //
+ GpioLockPadCfgForGroupDw (Group, DwNum, PadCfgLock);
+ }
+
+ return EFI_SUCCESS;
+}
+
+/**
+ This procedure will write GPIO Lock/LockTx register using SBI.
+
+ @param[in] RegType GPIO register (Lock or LockTx)
+ @param[in] Group GPIO group number
+ @param[in] DwNum Register number for current group.
+ For group which has less then 32 pads per group DwNum must be 0.
+ @param[in] LockRegAndMask Mask which will be AND'ed with Lock register value
+ @param[in] LockRegOrMask Mask which will be Or'ed with Lock register value
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_UNSUPPORTED Feature is not supported for this group or pad
+**/
+STATIC
+EFI_STATUS
+GpioWriteLockReg (
+ IN GPIO_REG RegType,
+ IN GPIO_GROUP Group,
+ IN UINT32 DwNum,
+ IN UINT32 LockRegAndMask,
+ IN UINT32 LockRegOrMask
+ )
+{
+ CONST GPIO_GROUP_INFO *GpioGroupInfo;
+ UINT32 GpioGroupInfoLength;
+ UINT32 RegOffset;
+ UINT32 OldLockVal;
+ UINT32 NewLockVal;
+ UINT32 GroupIndex;
+
+ OldLockVal = 0;
+ NewLockVal = 0;
+
+ RegOffset = NO_REGISTER_FOR_PROPERTY;
+ GroupIndex = GpioGetGroupIndexFromGroup (Group);
+
+ GpioGroupInfo = GpioGetGroupInfoTable (&GpioGroupInfoLength);
+
+ switch (RegType) {
+ case GpioPadConfigLockRegister:
+ RegOffset = GpioGroupInfo[GroupIndex].PadCfgLockOffset;
+ GpioGetPadCfgLockForGroupDw (Group, DwNum, &OldLockVal);
+ break;
+ case GpioPadLockOutputRegister:
+ RegOffset = GpioGroupInfo[GroupIndex].PadCfgLockTxOffset;
+ GpioGetPadCfgLockTxForGroupDw (Group, DwNum, &OldLockVal);
+ break;
+ default:
+ break;
+ }
+
+ //
+ // Check if selected register exists
+ //
+ if (RegOffset == NO_REGISTER_FOR_PROPERTY) {
+ return EFI_UNSUPPORTED;
+ }
+
+ NewLockVal = (OldLockVal & LockRegAndMask) | LockRegOrMask;
+
+ return GpioInternalWriteLockRegister (NewLockVal, RegOffset, DwNum, GpioGroupInfo, GroupIndex);
+}
+
+/**
+ This procedure will get Gpio Pad Ownership
+
+ @param[in] GpioPad GPIO pad
+ @param[out] PadOwnVal Value of Pad Ownership
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid group or pad number
+**/
+EFI_STATUS
+GpioGetPadOwnership (
+ IN GPIO_PAD GpioPad,
+ OUT GPIO_PAD_OWN *PadOwnVal
+ )
+{
+ UINT32 Mask;
+ UINT32 RegOffset;
+ UINT32 GroupIndex;
+ UINT32 PadNumber;
+ CONST GPIO_GROUP_INFO *GpioGroupInfo;
+ UINT32 GpioGroupInfoLength;
+ UINT32 PadOwnRegValue;
+
+ if (!GpioIsPadValid (GpioPad)) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ GroupIndex = GpioGetGroupIndexFromGpioPad (GpioPad);
+ PadNumber = GpioGetPadNumberFromGpioPad (GpioPad);
+
+ GpioGroupInfo = GpioGetGroupInfoTable (&GpioGroupInfoLength);
+
+ //
+ // Check if selected register exists
+ //
+ if (GpioGroupInfo[GroupIndex].PadOwnOffset == NO_REGISTER_FOR_PROPERTY) {
+ *PadOwnVal = GpioPadOwnHost;
+ return EFI_UNSUPPORTED;
+ }
+ //
+ // Calculate RegOffset using Pad Ownership offset and GPIO Pad number.
+ // One DWord register contains information for 8 pads.
+ //
+ RegOffset = GpioGroupInfo[GroupIndex].PadOwnOffset + (PadNumber >> 3) * 0x4;
+
+ //
+ // Calculate pad bit position within DWord register
+ //
+ PadNumber %= 8;
+ Mask = (BIT1 | BIT0) << (PadNumber * 4);
+
+ PadOwnRegValue = GpioRegisterAccessRead32 (&GpioGroupInfo[GroupIndex], RegOffset);
+
+ *PadOwnVal = (GPIO_PAD_OWN) ((PadOwnRegValue & Mask) >> (PadNumber * 4));
+
+ return EFI_SUCCESS;
+}
+
+/**
+ This procedure will check state of Pad Config Lock for pads within one group
+
+ @param[in] Group GPIO group
+ @param[in] DwNum PadCfgLock register number for current group.
+ For group which has less then 32 pads per group DwNum must be 0.
+ @param[out] PadCfgLockRegVal Value of PadCfgLock register
+ Bit position - PadNumber
+ Bit value - 0: NotLocked, 1: Locked
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid group or DwNum parameter number
+**/
+EFI_STATUS
+GpioGetPadCfgLockForGroupDw (
+ IN GPIO_GROUP Group,
+ IN UINT32 DwNum,
+ OUT UINT32 *PadCfgLockRegVal
+ )
+{
+ if (!GpioIsGroupAndDwNumValid (Group, DwNum)) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ return GpioReadReg (
+ GpioPadConfigLockRegister,
+ Group,
+ DwNum,
+ PadCfgLockRegVal
+ );
+}
+/**
+ This procedure will check state of Pad Config Tx Lock for pads within one group
+
+ @param[in] Group GPIO group
+ @param[in] DwNum PadCfgLockTx register number for current group.
+ For group which has less then 32 pads per group DwNum must be 0.
+ @param[out] PadCfgLockTxRegVal Value of PadCfgLockTx register
+ Bit position - PadNumber
+ Bit value - 0: NotLockedTx, 1: LockedTx
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid group or DwNum parameter number
+**/
+EFI_STATUS
+GpioGetPadCfgLockTxForGroupDw (
+ IN GPIO_GROUP Group,
+ IN UINT32 DwNum,
+ OUT UINT32 *PadCfgLockTxRegVal
+ )
+{
+ if (!GpioIsGroupAndDwNumValid (Group, DwNum)) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ return GpioReadReg (
+ GpioPadLockOutputRegister,
+ Group,
+ DwNum,
+ PadCfgLockTxRegVal
+ );
+}
+/**
+ This procedure will clear PadCfgLock for selected pads within one group.
+ This function should be used only inside SMI.
+
+ @param[in] Group GPIO group
+ @param[in] DwNum PadCfgLock register number for current group.
+ For group which has less then 32 pads per group DwNum must be 0.
+ @param[in] PadsToUnlock Bitmask for pads which are going to be unlocked,
+ Bit position - PadNumber
+ Bit value - 0: DoNotUnlock, 1: Unlock
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid group or pad number
+**/
+EFI_STATUS
+GpioUnlockPadCfgForGroupDw (
+ IN GPIO_GROUP Group,
+ IN UINT32 DwNum,
+ IN UINT32 PadsToUnlock
+ )
+{
+ if (!GpioIsGroupAndDwNumValid (Group, DwNum)) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ return GpioWriteLockReg (
+ GpioPadConfigLockRegister,
+ Group,
+ DwNum,
+ ~PadsToUnlock,
+ 0
+ );
+}
+/**
+ This procedure will clear PadCfgLockTx for selected pads within one group.
+ This function should be used only inside SMI.
+
+ @param[in] Group GPIO group
+ @param[in] DwNum PadCfgLockTx register number for current group.
+ For group which has less then 32 pads per group DwNum must be 0.
+ @param[in] PadsToUnlockTx Bitmask for pads which are going to be unlocked,
+ Bit position - PadNumber
+ Bit value - 0: DoNotUnLockTx, 1: LockTx
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid group or pad number
+**/
+EFI_STATUS
+GpioUnlockPadCfgTxForGroupDw (
+ IN GPIO_GROUP Group,
+ IN UINT32 DwNum,
+ IN UINT32 PadsToUnlockTx
+ )
+{
+ if (!GpioIsGroupAndDwNumValid (Group, DwNum)) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ return GpioWriteLockReg (
+ GpioPadLockOutputRegister,
+ Group,
+ DwNum,
+ ~PadsToUnlockTx,
+ 0
+ );
+}
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/Library/PeiDxeSmmGpioLib/GpioLibrary.h b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/Library/PeiDxeSmmGpioLib/GpioLibrary.h
new file mode 100644
index 0000000000..2c2b4ee75c
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/Library/PeiDxeSmmGpioLib/GpioLibrary.h
@@ -0,0 +1,29 @@
+/** @file
+ Header file for GPIO Lib implementation.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _GPIO_LIBRARY_H_
+#define _GPIO_LIBRARY_H_
+
+#include <Base.h>
+#include <Uefi/UefiBaseType.h>
+#include <Library/IoLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/GpioLib.h>
+#include <Library/GpioNativeLib.h>
+#include <Library/GpioPrivateLib.h>
+#include <Library/PchInfoLib.h>
+#include <Library/PchCycleDecodingLib.h>
+#include <Library/PmcPrivateLib.h>
+#include <Library/GpioHelpersLib.h>
+#include <Register/GpioRegs.h>
+
+//
+// Number of PADCFG_DW registers
+//
+#define GPIO_PADCFG_DW_REG_NUMBER 4
+
+#endif // _GPIO_LIBRARY_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/Library/PeiDxeSmmGpioLib/GpioNativeLib.c b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/Library/PeiDxeSmmGpioLib/GpioNativeLib.c
new file mode 100644
index 0000000000..4e4c53e588
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/Library/PeiDxeSmmGpioLib/GpioNativeLib.c
@@ -0,0 +1,177 @@
+/** @file
+ This file contains routines for GPIO native and chipset specific usage
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#include "GpioLibrary.h"
+
+/**
+ This procedure will get number of pads for certain GPIO group
+
+ @param[in] Group GPIO group number
+
+ @retval Value Pad number for group
+ If illegal group number then return 0
+**/
+UINT32
+GpioGetPadPerGroup (
+ IN GPIO_GROUP Group
+ )
+{
+ CONST GPIO_GROUP_INFO *GpioGroupInfo;
+ UINT32 GpioGroupInfoLength;
+ UINT32 GroupIndex;
+ //
+ // Check if group argument exceeds GPIO GROUP INFO array
+ //
+ GpioGroupInfo = GpioGetGroupInfoTable (&GpioGroupInfoLength);
+ GroupIndex = GpioGetGroupIndexFromGroup (Group);
+
+ if ((UINTN) GroupIndex >= GpioGroupInfoLength) {
+ return 0;
+ } else {
+ return GpioGroupInfo[GroupIndex].PadPerGroup;
+ }
+}
+
+/**
+ This procedure will get number of groups
+
+ @param[in] none
+
+ @retval Value Group number
+**/
+UINT32
+GpioGetNumberOfGroups (
+ VOID
+ )
+{
+ UINT32 GpioGroupInfoLength;
+
+ GpioGetGroupInfoTable (&GpioGroupInfoLength);
+ return GpioGroupInfoLength;
+}
+/**
+ This procedure will get lowest group
+
+ @param[in] none
+
+ @retval Value Lowest Group
+**/
+GPIO_GROUP
+GpioGetLowestGroup (
+ VOID
+ )
+{
+ return GpioGetGroupFromGroupIndex (0);
+}
+/**
+ This procedure will get highest group
+
+ @param[in] none
+
+ @retval Value Highest Group
+**/
+GPIO_GROUP
+GpioGetHighestGroup (
+ VOID
+ )
+{
+ return GpioGetGroupFromGroupIndex (GpioGetNumberOfGroups () - 1);
+}
+
+/**
+ This procedure will get group number
+
+ @param[in] GpioPad Gpio Pad
+
+ @retval Value Group number
+**/
+GPIO_GROUP
+GpioGetGroupFromGpioPad (
+ IN GPIO_PAD GpioPad
+ )
+{
+ return GPIO_GET_GROUP_FROM_PAD (GpioPad);
+}
+
+/**
+ This procedure will get group index (0 based)
+
+ @param[in] GpioPad Gpio Pad
+
+ @retval Value Group Index
+**/
+UINT32
+GpioGetGroupIndexFromGpioPad (
+ IN GPIO_PAD GpioPad
+ )
+{
+ return (UINT32) GPIO_GET_GROUP_INDEX_FROM_PAD (GpioPad);
+}
+
+/**
+ This procedure will get group index (0 based) from group
+
+ @param[in] GpioGroup Gpio Group
+
+ @retval Value Group Index
+**/
+UINT32
+GpioGetGroupIndexFromGroup (
+ IN GPIO_GROUP GpioGroup
+ )
+{
+ return (UINT32) GPIO_GET_GROUP_INDEX (GpioGroup);
+}
+
+/**
+ This procedure will get group from group index (0 based)
+
+ @param[in] GroupIndex Group Index
+
+ @retval GpioGroup Gpio Group
+**/
+GPIO_GROUP
+GpioGetGroupFromGroupIndex (
+ IN UINT32 GroupIndex
+ )
+{
+ return GPIO_GROUP_DEF (GroupIndex, GpioGetThisChipsetId ());
+}
+
+/**
+ This procedure will get pad number (0 based) from Gpio Pad
+
+ @param[in] GpioPad Gpio Pad
+
+ @retval Value Pad Number
+**/
+UINT32
+GpioGetPadNumberFromGpioPad (
+ IN GPIO_PAD GpioPad
+ )
+{
+ return (UINT32) GPIO_GET_PAD_NUMBER (GpioPad);
+}
+/**
+ This procedure will return GpioPad from Group and PadNumber
+
+ @param[in] Group GPIO group
+ @param[in] PadNumber GPIO PadNumber
+
+ @retval GpioPad GpioPad
+**/
+GPIO_PAD
+GpioGetGpioPadFromGroupAndPadNumber (
+ IN GPIO_GROUP Group,
+ IN UINT32 PadNumber
+ )
+{
+ if (IsPchLp ()) {
+ return GPIO_PAD_DEF (Group,PadNumber);
+ } else {
+ return GPIO_PAD_DEF (Group,PadNumber);
+ }
+}
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/Library/PeiDxeSmmGpioLib/PeiDxeSmmGpioLib.inf b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/Library/PeiDxeSmmGpioLib/PeiDxeSmmGpioLib.inf
new file mode 100644
index 0000000000..21fb4417c1
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/Library/PeiDxeSmmGpioLib/PeiDxeSmmGpioLib.inf
@@ -0,0 +1,44 @@
+## @file
+# Component description file for the PeiDxeSmmGpioLib
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+
+[Defines]
+INF_VERSION = 0x00010017
+BASE_NAME = PeiDxeSmmGpioLib
+FILE_GUID = 16EC5CA8-8195-4847-B6CB-662BD7B763F2
+VERSION_STRING = 1.0
+MODULE_TYPE = BASE
+LIBRARY_CLASS = GpioLib
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = IA32 X64 IPF EBC
+#
+
+
+
+[LibraryClasses]
+BaseLib
+IoLib
+DebugLib
+PrintLib
+PchCycleDecodingLib
+PchSbiAccessLib
+PmcPrivateLib
+GpioPrivateLib
+GpioHelpersLib
+
+[Packages]
+MdePkg/MdePkg.dec
+AlderlakeSiliconPkg/SiPkg.dec
+
+
+[Sources]
+GpioLib.c
+GpioNativeLib.c
+GpioInit.c
+GpioLibrary.h
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/BaseGpioHelpersLibNull/BaseGpioHelpersLibNull.c b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/BaseGpioHelpersLibNull/BaseGpioHelpersLibNull.c
new file mode 100644
index 0000000000..b4b6c14329
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/BaseGpioHelpersLibNull/BaseGpioHelpersLibNull.c
@@ -0,0 +1,51 @@
+/** @file
+ This file contains NULL implementation for GPIO Helpers Lib
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#include <Uefi/UefiBaseType.h>
+#include <Library/GpioConfig.h>
+
+/**
+ This procedure stores GPIO group data about pads which PadConfig needs to be unlocked.
+
+ @param[in] GroupIndex GPIO group index
+ @param[in] DwNum DWORD index for a group.
+ For group which has less then 32 pads per group DwNum must be 0.
+ @param[in] UnlockedPads DWORD bitmask for pads which are going to be left unlocked
+ Bit position - PadNumber
+ Bit value - 0: Skip, 1: Leave unlocked
+
+ @retval Status
+**/
+EFI_STATUS
+GpioStoreGroupDwUnlockPadConfigData (
+ IN UINT32 GroupIndex,
+ IN UINT32 DwNum,
+ IN UINT32 UnlockedPads
+ )
+{
+ return EFI_SUCCESS;
+}
+
+/**
+ This procedure stores GPIO group data about pads which Output state needs to be unlocked.
+
+ @param[in] GroupIndex GPIO group index
+ @param[in] DwNum DWORD index for a group.
+ For group which has less then 32 pads per group DwNum must be 0.
+ @param[in] UnlockedPads DWORD bitmask for pads which are going to be left unlocked
+ Bit position - PadNumber
+ Bit value - 0: Skip, 1: Leave unlocked
+ @retval Status
+**/
+EFI_STATUS
+GpioStoreGroupDwUnlockOutputData (
+ IN UINT32 GroupIndex,
+ IN UINT32 DwNum,
+ IN UINT32 UnlockedPads
+ )
+{
+ return EFI_SUCCESS;
+}
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/BaseGpioHelpersLibNull/BaseGpioHelpersLibNull.inf b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/BaseGpioHelpersLibNull/BaseGpioHelpersLibNull.inf
new file mode 100644
index 0000000000..91d81af4b9
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/BaseGpioHelpersLibNull/BaseGpioHelpersLibNull.inf
@@ -0,0 +1,25 @@
+## @file
+# Component description file for the NULL GpioHelpersLib
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+
+[Defines]
+INF_VERSION = 0x00010017
+BASE_NAME = BaseGpioHelpersLib
+FILE_GUID = AB282608-2A50-4AE3-9242-64064ECF40D4
+VERSION_STRING = 1.0
+MODULE_TYPE = BASE
+LIBRARY_CLASS = GpioHelpersLib
+
+
+[Packages]
+MdePkg/MdePkg.dec
+AlderlakeSiliconPkg/SiPkg.dec
+
+
+[Sources]
+BaseGpioHelpersLibNull.c
+
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiDxeSmmGpioPrivateLib/GpioNativePrivateLibInternal.h b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiDxeSmmGpioPrivateLib/GpioNativePrivateLibInternal.h
new file mode 100644
index 0000000000..480990cb62
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiDxeSmmGpioPrivateLib/GpioNativePrivateLibInternal.h
@@ -0,0 +1,48 @@
+/** @file
+ Header file for GPIO Private Lib Internal functions.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _GPIO_NATIVE_PRIVATE_LIB_INTERNAL_H_
+#define _GPIO_NATIVE_PRIVATE_LIB_INTERNAL_H_
+
+#include <Library/GpioPrivateLib.h>
+
+
+/**
+ This function provides recommended GPIO IO Standby configuration for a given native function
+
+ @param[in] PadFunction PadFunction for a specific native signal. Please refer to GpioNativePads.h
+ @param[out] StandbyState IO Standby State for specified native function
+ @param[out] StandbyTerm IO Standby Termination for specified native function
+
+ @retval Status
+**/
+EFI_STATUS
+GpioGetFunctionIoStandbyConfig (
+ IN UINT32 PadFunction,
+ OUT GPIO_IOSTANDBY_STATE *StandbyState,
+ OUT GPIO_IOSTANDBY_TERM *StandbyTerm
+ );
+
+/**
+ This procedure will calculate PADCFG register value based on GpioConfig data
+ For physical/local/hard (not virtual) GPIO pads
+
+ @param[in] GpioPad GPIO Pad
+ @param[in] GpioConfig GPIO Configuration data
+ @param[out] PadCfgDwReg PADCFG DWx register value
+ @param[out] PadCfgDwRegMask Mask with PADCFG DWx register bits to be modified
+
+ @retval Status
+**/
+EFI_STATUS
+GpioPadCfgRegValueFromGpioConfigHardGpio (
+ IN GPIO_PAD GpioPad,
+ IN CONST GPIO_CONFIG *GpioConfig,
+ OUT UINT32 *PadCfgDwReg,
+ OUT UINT32 *PadCfgDwRegMask
+ );
+
+#endif // _GPIO_NATIVE_PRIVATE_LIB_INTERNAL_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiDxeSmmGpioPrivateLib/GpioPrivateLib.c b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiDxeSmmGpioPrivateLib/GpioPrivateLib.c
new file mode 100644
index 0000000000..7d5fa9fafd
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiDxeSmmGpioPrivateLib/GpioPrivateLib.c
@@ -0,0 +1,267 @@
+/** @file
+ This file contains GPIO routines for RC usage
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#include <Base.h>
+#include <Uefi/UefiBaseType.h>
+#include <Library/IoLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/GpioLib.h>
+#include <Library/GpioNativeLib.h>
+#include <Library/GpioPrivateLib.h>
+#include <Library/GpioNativePads.h>
+#include <Register/GpioRegs.h>
+#include "GpioNativePrivateLibInternal.h"
+
+/**
+ This procedure is used to check if GpioPad is valid for certain chipset
+
+ @param[in] GpioPad GPIO pad
+
+ @retval TRUE This pin is valid on this chipset
+ FALSE Incorrect pin
+**/
+BOOLEAN
+GpioIsCorrectPadForThisChipset (
+ IN GPIO_PAD GpioPad
+ )
+{
+ return ((GPIO_GET_CHIPSET_ID (GpioPad) == GpioGetThisChipsetId ()) &&
+ (GpioGetGroupIndexFromGpioPad (GpioPad) < GpioGetNumberOfGroups ()));
+}
+
+/**
+ This procedure is used by PchSmiDispatcher and will return information
+ needed to register GPI SMI.
+
+ @param[in] Index GPI SMI number
+ @param[out] GpioPin GPIO pin
+ @param[out] GpiSmiBitOffset GPI SMI bit position within GpiSmi Registers
+ @param[out] GpiHostSwOwnRegAddress Address of HOSTSW_OWN register
+ @param[out] GpiSmiStsRegAddress Address of GPI SMI status register
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid group or pad number
+**/
+EFI_STATUS
+GpioGetPadAndSmiRegs (
+ IN UINT32 Index,
+ OUT GPIO_PAD *GpioPin,
+ OUT UINT8 *GpiSmiBitOffset,
+ OUT UINT32 *GpiHostSwOwnRegAddress,
+ OUT UINT32 *GpiSmiStsRegAddress
+ )
+{
+ UINT32 GroupIndex;
+ UINT32 PadNumber;
+ CONST GPIO_GROUP_INFO *GpioGroupInfo;
+ GPIO_GROUP GpioGroup;
+ UINT32 GpioGroupInfoLength;
+ UINT32 SmiStsRegOffset;
+ UINT32 HostSwOwnRegOffset;
+ GPIO_PAD_OWN PadOwnVal;
+
+ GpioGroupInfo = GpioGetGroupInfoTable (&GpioGroupInfoLength);
+
+ PadNumber = 0;
+ GroupIndex = 0;
+ for (GroupIndex = 0; GroupIndex < GpioGroupInfoLength; GroupIndex++) {
+ PadNumber = Index;
+ if (PadNumber < GpioGroupInfo[GroupIndex].PadPerGroup) {
+ //
+ // Found group and pad number
+ //
+ break;
+ }
+ Index = Index - GpioGroupInfo[GroupIndex].PadPerGroup;
+ }
+
+ //
+ // Check if legal pad number
+ //
+ if (PadNumber >= GpioGroupInfo[GroupIndex].PadPerGroup){
+ return EFI_INVALID_PARAMETER;
+ }
+
+ //
+ // Check if selected group has GPI SMI Enable and Status registers
+ //
+ if (GpioGroupInfo[GroupIndex].SmiEnOffset == NO_REGISTER_FOR_PROPERTY) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ GpioGroup = GpioGetGroupFromGroupIndex (GroupIndex);
+ *GpioPin = GpioGetGpioPadFromGroupAndPadNumber (GpioGroup, PadNumber);
+
+ DEBUG_CODE_BEGIN ();
+ //
+ // Check if selected GPIO Pad is not owned by CSME/ISH/IE
+ //
+ GpioGetPadOwnership (*GpioPin, &PadOwnVal);
+ if (PadOwnVal != GpioPadOwnHost) {
+ DEBUG ((DEBUG_ERROR, "GPIO ERROR: GPIO not owned by host!\n"));
+ return EFI_INVALID_PARAMETER;
+ }
+ DEBUG_CODE_END ();
+
+ *GpiSmiBitOffset = (UINT8)(PadNumber % 32);
+
+ HostSwOwnRegOffset = GpioGroupInfo[GroupIndex].HostOwnOffset + (PadNumber / 32) * 0x4;
+ *GpiHostSwOwnRegAddress = PCH_PCR_ADDRESS (GpioGroupInfo[GroupIndex].Community, HostSwOwnRegOffset);
+
+ SmiStsRegOffset = GpioGroupInfo[GroupIndex].SmiStsOffset + (PadNumber / 32) * 0x4;
+ *GpiSmiStsRegAddress = PCH_PCR_ADDRESS (GpioGroupInfo[GroupIndex].Community, SmiStsRegOffset);
+
+ return EFI_SUCCESS;
+}
+
+/**
+ This procedure will check if GpioPad argument is valid.
+ Function will check below conditions:
+ - GpioPad represents a pad for current PCH
+ - GpioPad belongs to valid GpioGroup
+ - GPIO PadNumber is not greater than number of pads for this group
+
+ @param[in] GpioPad GPIO pad
+
+ @retval TRUE GPIO pad is valid and can be used with GPIO lib API
+ @retval FALSE GPIO pad is invalid and cannot be used with GPIO lib API
+**/
+BOOLEAN
+GpioIsPadValid (
+ IN GPIO_PAD GpioPad
+ )
+{
+ CONST GPIO_GROUP_INFO *GpioGroupInfo;
+ UINT32 GpioGroupInfoLength;
+ UINT32 PadNumber;
+ UINT32 GroupIndex;
+
+ if (!GpioIsCorrectPadForThisChipset (GpioPad)) {
+ DEBUG ((DEBUG_ERROR, "GPIO ERROR: Incorrect GpioPad (0x%08x) used on this chipset!\n", GpioPad));
+ goto Error;
+ }
+
+ GpioGroupInfo = GpioGetGroupInfoTable (&GpioGroupInfoLength);
+
+ //
+ // Check if legal pin number
+ //
+ GroupIndex = GpioGetGroupIndexFromGpioPad (GpioPad);
+ PadNumber = GpioGetPadNumberFromGpioPad (GpioPad);
+ if (PadNumber >= GpioGroupInfo[GroupIndex].PadPerGroup) {
+ DEBUG ((DEBUG_ERROR, "GPIO ERROR: Pin number (%d) exceeds range of group (max: %d)\n",
+ PadNumber,
+ GpioGroupInfo[GroupIndex].PadPerGroup));
+ goto Error;
+ }
+
+ return TRUE;
+Error:
+ ASSERT (FALSE);
+ return FALSE;
+}
+
+/**
+ This procedure will read GPIO Pad Configuration register
+
+ @param[in] GpioPad GPIO pad
+ @param[in] DwReg Choose PADCFG register: 0:DW0, 1:DW1
+
+ @retval PadCfgRegValue PADCFG_DWx value
+**/
+UINT32
+GpioReadPadCfgReg (
+ IN GPIO_PAD GpioPad,
+ IN UINT8 DwReg
+ )
+{
+ UINT32 PadCfgReg;
+ CONST GPIO_GROUP_INFO *GpioGroupInfo;
+ UINT32 GpioGroupInfoLength;
+ UINT32 GroupIndex;
+
+ GroupIndex = GpioGetGroupIndexFromGpioPad (GpioPad);
+ GpioGroupInfo = GpioGetGroupInfoTable (&GpioGroupInfoLength);
+
+ //
+ // Create Pad Configuration register offset
+ //
+ PadCfgReg = GpioGetGpioPadCfgAddressFromGpioPad (GpioPad, DwReg);
+ return GpioRegisterAccessRead32 (&GpioGroupInfo[GroupIndex], PadCfgReg);
+}
+
+
+/**
+ This procedure will calculate PADCFG register value based on GpioConfig data
+ For physical/local/hard (not virtual) GPIO pads
+
+ @param[in] GpioPad GPIO Pad
+ @param[in] GpioConfig GPIO Configuration data
+ @param[out] PadCfgDwReg PADCFG DWx register value
+ @param[out] PadCfgDwRegMask Mask with PADCFG DWx register bits to be modified
+
+ @retval Status
+**/
+EFI_STATUS
+GpioPadCfgRegValueFromGpioConfigHardGpio (
+ IN GPIO_PAD GpioPad,
+ IN CONST GPIO_CONFIG *GpioConfig,
+ OUT UINT32 *PadCfgDwReg,
+ OUT UINT32 *PadCfgDwRegMask
+ )
+{
+ //
+ // Configure how interrupt is triggered (RxEvCfg)
+ //
+ PadCfgDwRegMask[0] |= ((((GpioConfig->InterruptConfig & B_GPIO_INT_CONFIG_INT_TYPE_MASK) >> N_GPIO_INT_CONFIG_INT_TYPE_BIT_POS) == GpioHardwareDefault) ? 0x0 : B_GPIO_PCR_RX_LVL_EDG);
+ PadCfgDwReg[0] |= (((GpioConfig->InterruptConfig & B_GPIO_INT_CONFIG_INT_TYPE_MASK) >> (N_GPIO_INT_CONFIG_INT_TYPE_BIT_POS + 1)) << N_GPIO_PCR_RX_LVL_EDG);
+
+ //
+ // Configure interrupt generation (GPIRoutIOxAPIC/SCI/SMI/NMI)
+ //
+ PadCfgDwRegMask[0] |= ((((GpioConfig->InterruptConfig & B_GPIO_INT_CONFIG_INT_SOURCE_MASK) >> N_GPIO_INT_CONFIG_INT_SOURCE_BIT_POS) == GpioHardwareDefault) ? 0x0 : (B_GPIO_PCR_RX_NMI_ROUTE | B_GPIO_PCR_RX_SCI_ROUTE | B_GPIO_PCR_RX_SMI_ROUTE | B_GPIO_PCR_RX_APIC_ROUTE));
+ PadCfgDwReg[0] |= (((GpioConfig->InterruptConfig & B_GPIO_INT_CONFIG_INT_SOURCE_MASK) >> (N_GPIO_INT_CONFIG_INT_SOURCE_BIT_POS + 1)) << N_GPIO_PCR_RX_NMI_ROUTE);
+
+ //
+ // Configure GPIO direction (GPIORxDis and GPIOTxDis)
+ //
+ PadCfgDwRegMask[0] |= ((((GpioConfig->Direction & B_GPIO_DIRECTION_DIR_MASK) >> N_GPIO_DIRECTION_DIR_BIT_POS) == GpioHardwareDefault) ? 0x0 : (B_GPIO_PCR_RXDIS | B_GPIO_PCR_TXDIS));
+ PadCfgDwReg[0] |= (((GpioConfig->Direction & B_GPIO_DIRECTION_DIR_MASK) >> (N_GPIO_DIRECTION_DIR_BIT_POS + 1)) << N_GPIO_PCR_TXDIS);
+
+ //
+ // Configure GPIO input inversion (RXINV)
+ //
+ PadCfgDwRegMask[0] |= ((((GpioConfig->Direction & B_GPIO_DIRECTION_INV_MASK) >> N_GPIO_DIRECTION_INV_BIT_POS) == GpioHardwareDefault) ? 0x0 : B_GPIO_PCR_RXINV);
+ PadCfgDwReg[0] |= (((GpioConfig->Direction & B_GPIO_DIRECTION_INV_MASK) >> (N_GPIO_DIRECTION_INV_BIT_POS + 1)) << N_GPIO_PCR_RXINV);
+
+ //
+ // Configure GPIO output state (GPIOTxState)
+ //
+ PadCfgDwRegMask[0] |= ((((GpioConfig->OutputState & B_GPIO_OUTPUT_MASK) >> N_GPIO_OUTPUT_BIT_POS) == GpioHardwareDefault) ? 0x0 : B_GPIO_PCR_TX_STATE);
+ PadCfgDwReg[0] |= (((GpioConfig->OutputState & B_GPIO_OUTPUT_MASK) >> (N_GPIO_OUTPUT_BIT_POS + 1)) << N_GPIO_PCR_TX_STATE);
+
+ //
+ // Configure GPIO RX raw override to '1' (RXRAW1)
+ //
+ PadCfgDwRegMask[0] |= ((((GpioConfig->OtherSettings & B_GPIO_OTHER_CONFIG_RXRAW_MASK) >> N_GPIO_OTHER_CONFIG_RXRAW_BIT_POS) == GpioHardwareDefault) ? 0x0 : B_GPIO_PCR_RX_RAW1);
+ PadCfgDwReg[0] |= (((GpioConfig->OtherSettings & B_GPIO_OTHER_CONFIG_RXRAW_MASK) >> (N_GPIO_OTHER_CONFIG_RXRAW_BIT_POS + 1)) << N_GPIO_PCR_RX_RAW1);
+
+ //
+ // Configure GPIO Pad Mode (PMode)
+ //
+ PadCfgDwRegMask[0] |= ((((GpioConfig->PadMode & B_GPIO_PAD_MODE_MASK) >> N_GPIO_PAD_MODE_BIT_POS) == GpioHardwareDefault) ? 0x0 : B_GPIO_PCR_PAD_MODE);
+ PadCfgDwReg[0] |= (((GpioConfig->PadMode & B_GPIO_PAD_MODE_MASK) >> (N_GPIO_PAD_MODE_BIT_POS + 1)) << N_GPIO_PCR_PAD_MODE);
+
+ //
+ // Configure GPIO termination (Term)
+ //
+ PadCfgDwRegMask[1] |= ((((GpioConfig->ElectricalConfig & B_GPIO_ELECTRICAL_CONFIG_TERMINATION_MASK) >> N_GPIO_ELECTRICAL_CONFIG_TERMINATION_BIT_POS) == GpioHardwareDefault) ? 0x0 : B_GPIO_PCR_TERM);
+ PadCfgDwReg[1] |= (((GpioConfig->ElectricalConfig & B_GPIO_ELECTRICAL_CONFIG_TERMINATION_MASK) >> (N_GPIO_ELECTRICAL_CONFIG_TERMINATION_BIT_POS + 1)) << N_GPIO_PCR_TERM);
+
+ return EFI_SUCCESS;
+}
+
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiDxeSmmGpioPrivateLib/GpioPrivateLibPch.c b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiDxeSmmGpioPrivateLib/GpioPrivateLibPch.c
new file mode 100644
index 0000000000..3d16fd2acd
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiDxeSmmGpioPrivateLib/GpioPrivateLibPch.c
@@ -0,0 +1,172 @@
+/** @file
+ This file contains hard/physical/local (not virtual) GPIO information
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#include <Uefi/UefiBaseType.h>
+#include <Library/GpioLib.h>
+#include <Library/GpioPrivateLib.h>
+#include <Library/GpioNativeLib.h>
+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+#include <Library/PchSbiAccessLib.h>
+#include <Register/GpioRegs.h>
+#include "GpioNativePrivateLibInternal.h"
+
+/**
+ This procedure calculates Pad Configuration Register DW offset
+
+ @param[in] GpioPad GPIO pad
+ @param[in] DwReg Index of the configuration register
+
+ @retval DW Register offset
+**/
+UINT32
+GpioGetGpioPadCfgAddressFromGpioPad (
+ IN GPIO_PAD GpioPad,
+ IN UINT32 DwReg
+ )
+{
+ UINT32 PadCfgRegAddress;
+ CONST GPIO_GROUP_INFO *GpioGroupInfo;
+ UINT32 GpioGroupInfoLength;
+ UINT32 GroupIndex;
+ UINT32 PadNumber;
+
+ GroupIndex = GpioGetGroupIndexFromGpioPad (GpioPad);
+ PadNumber = GpioGetPadNumberFromGpioPad (GpioPad);
+
+ GpioGroupInfo = GpioGetGroupInfoTable (&GpioGroupInfoLength);
+
+ //
+ // Create Pad Configuration register offset
+ //
+ PadCfgRegAddress = GpioGroupInfo[GroupIndex].PadCfgOffset + DwReg * 4 + S_GPIO_PCR_PADCFG * PadNumber;
+
+ return PadCfgRegAddress;
+}
+
+/**
+ This procedure reads GPIO register
+
+ @param[in] GpioGroupInfo Pointer to GPIO group table info
+ @param[in] Register Register offset
+
+ @retval Register value or "F"s in case of errors
+**/
+UINT32
+GpioRegisterAccessRead32 (
+ IN CONST GPIO_GROUP_INFO *GpioGroupInfo,
+ IN UINT32 Register
+ )
+{
+ return MmioRead32 (PCH_PCR_ADDRESS (GpioGroupInfo->Community, Register));
+}
+
+/**
+ This procedure writes GPIO register
+
+ @param[in] GpioGroupInfo Pointer to GPIO group table info
+ @param[in] Register Register offset
+ @param[in] AndValue And value
+ @param[in] OrValue Or value
+
+ @retval EFI_SUCCESS Operation completed successfully
+**/
+EFI_STATUS
+GpioRegisterAccessAndThenOr32 (
+ IN CONST GPIO_GROUP_INFO *GpioGroupInfo,
+ IN UINT32 Register,
+ IN UINT32 AndValue,
+ IN UINT32 OrValue
+ )
+{
+ MmioAndThenOr32 (
+ PCH_PCR_ADDRESS (GpioGroupInfo->Community, Register),
+ AndValue,
+ OrValue
+ );
+ return EFI_SUCCESS;
+}
+
+/**
+ This procedure will calculate PADCFG register value based on GpioConfig data
+
+ @param[in] GpioPad GPIO Pad
+ @param[in] GpioConfig GPIO Configuration data
+ @param[out] PadCfgDwReg PADCFG DWx register value
+ @param[out] PadCfgDwRegMask Mask with PADCFG DWx register bits to be modified
+
+ @retval Status
+**/
+EFI_STATUS
+GpioPadCfgRegValueFromGpioConfig (
+ IN GPIO_PAD GpioPad,
+ IN CONST GPIO_CONFIG *GpioConfig,
+ OUT UINT32 *PadCfgDwReg,
+ OUT UINT32 *PadCfgDwRegMask
+ )
+{
+ return GpioPadCfgRegValueFromGpioConfigHardGpio (GpioPad, GpioConfig, PadCfgDwReg, PadCfgDwRegMask);
+}
+
+/**
+ This procedure will write GPIO Lock/LockTx register
+ - For PCH SBI message is used.
+
+ @param[in] RegValue GPIO register (Lock or LockTx) value
+ @param[in] RegOffset GPIO register (Lock or LockTx) base offset
+ @param[in] DwNum Register number for current group.
+ For group which has less then 32 pads per group DwNum must be 0.
+ @param[in] GpioGroupInfo Pointer to GPIO group table info
+ @param[in] GroupIndex GPIO group index in the GpioGroupInfo table
+
+ @retval EFI_SUCCESS The function completed successfully
+ EFI_UNSUPPORTED Feature is not supported for this group or pad
+**/
+EFI_STATUS
+GpioInternalWriteLockRegister (
+ IN UINT32 RegValue,
+ IN UINT32 RegOffset,
+ IN UINT32 DwNum,
+ IN CONST GPIO_GROUP_INFO *GpioGroupInfo,
+ IN UINT32 GroupIndex
+ )
+{
+ EFI_STATUS Status;
+ PCH_SBI_OPCODE Opcode;
+ UINT8 Response;
+
+ //
+ // If there are more then 32 pads per group then certain
+ // group information would be split into more then one DWord register.
+ // PadConfigLock and OutputLock registers when used for group containing more than 32 pads
+ // are not placed in a continuous way, e.g:
+ // 0x0 - PadConfigLock_DW0
+ // 0x4 - OutputLock_DW0
+ // 0x8 - PadConfigLock_DW1
+ // 0xC - OutputLock_DW1
+ //
+ RegOffset += DwNum * 0x8;
+
+ if (IsGpioLockOpcodeSupported ()) {
+ Opcode = GpioLockUnlock;
+ } else {
+ Opcode = PrivateControlWrite;
+ }
+
+ Status = PchSbiExecutionEx (
+ GpioGroupInfo[GroupIndex].Community,
+ RegOffset,
+ Opcode,
+ FALSE,
+ 0x000F,
+ 0x0000,
+ 0x0000,
+ &RegValue,
+ &Response
+ );
+ ASSERT_EFI_ERROR (Status);
+ return Status;
+}
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiDxeSmmGpioPrivateLib/GpioPrivateLibVer2.c b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiDxeSmmGpioPrivateLib/GpioPrivateLibVer2.c
new file mode 100644
index 0000000000..1348643553
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiDxeSmmGpioPrivateLib/GpioPrivateLibVer2.c
@@ -0,0 +1,81 @@
+/** @file
+ This file contains VER2 specific GPIO information
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#include <Uefi/UefiBaseType.h>
+#include <Library/DebugLib.h>
+#include <Library/PchInfoLib.h>
+#include <Library/GpioLib.h>
+#include <Library/GpioNativeLib.h>
+#include <Library/GpioNativePads.h>
+#include <Library/GpioPrivateLib.h>
+#include <Library/GpioHelpersLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/IoLib.h>
+#include <Register/GpioRegsVer2.h>
+#include <Register/PchPcrRegs.h>
+#include <Register/GpioRegs.h>
+#include <Pins/GpioPinsVer2Lp.h>
+#include <GpioNativePrivateLibInternal.h>
+#include <Library/PcdLib.h>
+GLOBAL_REMOVE_IF_UNREFERENCED GPIO_GROUP_INFO mPchLpGpioGroupInfo[] = {
+ {PID_GPIOCOM0, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_PAD_OWN, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_HOSTSW_OWN, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_GPI_IS, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_GPI_IE, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_GPI_GPE_STS, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_GPI_GPE_EN, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_SMI_STS, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_SMI_EN, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_NMI_STS, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_NMI_EN, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_PADCFGLOCK, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_PADCFGLOCKTX, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_PADCFG_OFFSET, GPIO_VER2_PCH_LP_GPIO_GPP_B_PAD_MAX}, //TGL PCH-LP GPP_B
+ {PID_GPIOCOM0, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, 0},
+ {PID_GPIOCOM0, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_A_PAD_OWN, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_A_HOSTSW_OWN, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_A_GPI_IS, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_A_GPI_IE, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_A_GPI_GPE_STS, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_A_GPI_GPE_EN, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_A_PADCFGLOCK, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_A_PADCFGLOCKTX, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_A_PADCFG_OFFSET, GPIO_VER2_PCH_LP_GPIO_GPP_A_PAD_MAX}, //TGL PCH-LP GPP_A
+ {PID_GPIOCOM5, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_R_PAD_OWN, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_R_HOSTSW_OWN, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_R_GPI_IS, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_R_GPI_IE, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_R_GPI_GPE_STS, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_R_GPI_GPE_EN, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_R_PADCFGLOCK, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_R_PADCFGLOCKTX, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_R_PADCFG_OFFSET, GPIO_VER2_PCH_LP_GPIO_GPP_R_PAD_MAX}, //TGL PCH-LP GPP_R
+ {PID_GPIOCOM5, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, 0},
+ {PID_GPIOCOM2, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPD_PAD_OWN, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPD_HOSTSW_OWN, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPD_GPI_IS, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPD_GPI_IE, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPD_GPI_GPE_STS, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPD_GPI_GPE_EN, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPD_PADCFGLOCK, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPD_PADCFGLOCKTX, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPD_PADCFG_OFFSET, GPIO_VER2_PCH_LP_GPIO_GPD_PAD_MAX}, //TGL PCH-LP GPD
+ {PID_GPIOCOM1, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_S_PAD_OWN, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_S_HOSTSW_OWN, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_S_GPI_IS, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_S_GPI_IE, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_S_GPI_GPE_STS, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_S_GPI_GPE_EN, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_S_PADCFGLOCK, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_S_PADCFGLOCKTX, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_S_PADCFG_OFFSET, GPIO_VER2_PCH_LP_GPIO_GPP_S_PAD_MAX}, //TGL PCH-LP GPP_S
+ {PID_GPIOCOM1, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_H_PAD_OWN, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_H_HOSTSW_OWN, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_H_GPI_IS, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_H_GPI_IE, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_H_GPI_GPE_STS, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_H_GPI_GPE_EN, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_H_PADCFGLOCK, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_H_PADCFGLOCKTX, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_H_PADCFG_OFFSET, GPIO_VER2_PCH_LP_GPIO_GPP_H_PAD_MAX}, //TGL PCH-LP GPP_H
+ {PID_GPIOCOM1, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_PAD_OWN, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_HOSTSW_OWN, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_GPI_IS, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_GPI_IE, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_GPI_GPE_STS, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_GPI_GPE_EN, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_SMI_STS, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_SMI_EN, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_NMI_STS, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_NMI_EN, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_PADCFGLOCK, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_PADCFGLOCKTX, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_PADCFG_OFFSET, GPIO_VER2_PCH_LP_GPIO_GPP_D_PAD_MAX}, //TGL PCH-LP GPP_D
+ {PID_GPIOCOM1, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, 0},
+ {PID_GPIOCOM1, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, 0},
+ {PID_GPIOCOM4, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_PAD_OWN, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_HOSTSW_OWN, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_GPI_IS, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_GPI_IE, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_GPI_GPE_STS, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_GPI_GPE_EN, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_SMI_STS, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_SMI_EN, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_NMI_STS, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_NMI_EN, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_PADCFGLOCK, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_PADCFGLOCKTX, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_PADCFG_OFFSET, GPIO_VER2_PCH_LP_GPIO_GPP_C_PAD_MAX}, //TGL PCH-LP GPP_C
+ {PID_GPIOCOM4, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_F_PAD_OWN, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_F_HOSTSW_OWN, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_F_GPI_IS, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_F_GPI_IE, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_F_GPI_GPE_STS, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_F_GPI_GPE_EN, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_F_PADCFGLOCK, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_F_PADCFGLOCKTX, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_F_PADCFG_OFFSET, GPIO_VER2_PCH_LP_GPIO_GPP_F_PAD_MAX}, //TGL PCH-LP GPP_F
+ {PID_GPIOCOM4, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, 0},
+ {PID_GPIOCOM4, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_PAD_OWN, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_HOSTSW_OWN, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_GPI_IS, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_GPI_IE, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_GPI_GPE_STS, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_GPI_GPE_EN, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_SMI_STS, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_SMI_EN, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_NMI_STS, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_NMI_EN, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_PADCFGLOCK, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_PADCFGLOCKTX, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_PADCFG_OFFSET, GPIO_VER2_PCH_LP_GPIO_GPP_E_PAD_MAX}, //TGL PCH-LP GPP_E
+};
+
+/**
+ This procedure will retrieve address and length of GPIO info table
+
+ @param[out] GpioGroupInfoTableLength Length of GPIO group table
+
+ @retval Pointer to GPIO group table
+
+**/
+CONST GPIO_GROUP_INFO*
+GpioGetGroupInfoTable (
+ OUT UINT32 *GpioGroupInfoTableLength
+ )
+{
+ *GpioGroupInfoTableLength = ARRAY_SIZE (mPchLpGpioGroupInfo);
+ return mPchLpGpioGroupInfo;
+}
+
+/**
+ Get GPIO Chipset ID specific to PCH generation and series
+**/
+UINT32
+GpioGetThisChipsetId (
+ VOID
+ )
+{
+ return GPIO_VER2_LP_CHIPSET_ID;
+}
+
+/**
+ Check if 0x13 opcode supported for writing to GPIO lock unlock register
+
+ @retval TRUE It's supported
+ @retval FALSE It's not supported
+**/
+BOOLEAN
+IsGpioLockOpcodeSupported (
+ VOID
+ )
+{
+ return TRUE;
+}
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiDxeSmmGpioPrivateLib/PeiDxeSmmGpioPrivateLibVer2.inf b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiDxeSmmGpioPrivateLib/PeiDxeSmmGpioPrivateLibVer2.inf
new file mode 100644
index 0000000000..2e9a6b7336
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiDxeSmmGpioPrivateLib/PeiDxeSmmGpioPrivateLibVer2.inf
@@ -0,0 +1,40 @@
+## @file
+# Component description file for the PeiDxeSmmGpioPrivateLib
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+[Defines]
+INF_VERSION = 0x00010017
+BASE_NAME = PeiDxeSmmGpioPrivateLibVer2
+FILE_GUID = 680A81B0-A087-4687-B5B4-146DA30042D6
+VERSION_STRING = 1.0
+MODULE_TYPE = BASE
+LIBRARY_CLASS = GpioPrivateLib
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = IA32 X64 IPF EBC
+#
+
+
+[LibraryClasses]
+ BaseLib
+ IoLib
+ DebugLib
+ PmcLib
+ PchInfoLib
+ GpioLib
+ GpioHelpersLib
+
+
+[Packages]
+ MdePkg/MdePkg.dec
+ AlderlakeSiliconPkg/SiPkg.dec
+
+
+[Sources]
+ GpioPrivateLib.c
+ GpioPrivateLibVer2.c
+ GpioPrivateLibPch.c
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiGpioHelpersLib/PeiGpioHelpersLib.c b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiGpioHelpersLib/PeiGpioHelpersLib.c
new file mode 100644
index 0000000000..9d47e6bfd5
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiGpioHelpersLib/PeiGpioHelpersLib.c
@@ -0,0 +1,218 @@
+/** @file
+ This file contains routines for PEI GPIO Helpers Lib
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#include <Library/HobLib.h>
+#include <Base.h>
+#include <Uefi/UefiBaseType.h>
+#include <Library/IoLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/GpioNativeLib.h>
+#include <Library/GpioPrivateLib.h>
+#include <Library/GpioHelpersLib.h>
+#include <Library/PeiServicesLib.h>
+#include <Library/ConfigBlockLib.h>
+#include <Ppi/SiPolicy.h>
+
+extern EFI_GUID gGpioLibUnlockHobGuid;
+
+//
+// GPIO Lock HOB
+// Stores information on GPIO pads that should be left unlocked
+//
+typedef struct {
+ //
+ // GPIO PadConfig unlock data
+ //
+ UINT32 PadConfig;
+ //
+ // GPIO Output unlock data
+ //
+ UINT32 OutputState;
+} GPIO_UNLOCK_HOB_DATA;
+
+/**
+ This procedure will get index of GPIO Unlock HOB structure for selected GroupIndex and DwNum.
+
+ @param[in] GroupIndex GPIO group index
+ @param[in] DwNum DWORD index for a group.
+ For group which has less then 32 pads per group DwNum must be 0.
+
+ @retval GpioUnlockHobIndex
+**/
+STATIC
+UINT32
+GpioUnlockDataIndex (
+ IN UINT32 GroupIndex,
+ IN UINT32 DwNum
+ )
+{
+ UINT32 GpioUnlockDataIndex;
+ UINT32 Index;
+
+ GpioUnlockDataIndex = 0;
+
+ for (Index = 0; Index < GroupIndex; Index++) {
+ GpioUnlockDataIndex += GPIO_GET_DW_NUM (GpioGetPadPerGroup (GpioGetGroupFromGroupIndex (Index))) + 1;
+ }
+
+ GpioUnlockDataIndex += DwNum;
+ return GpioUnlockDataIndex;
+}
+
+/**
+ This procedure will create GPIO HOB for storing unlock data
+
+ @retval Pointer to GPIO Unlock data structure
+**/
+STATIC
+GPIO_UNLOCK_HOB_DATA*
+GpioCreateUnlockData (
+ VOID
+ )
+{
+ VOID *HobData;
+ GPIO_GROUP Group;
+ GPIO_GROUP GroupMin;
+ GPIO_GROUP GroupMax;
+ UINT32 GpioUnlockDataRecords;
+
+ GroupMin = GpioGetLowestGroup ();
+ GroupMax = GpioGetHighestGroup ();
+ GpioUnlockDataRecords = 0;
+
+ for (Group = GroupMin; Group <= GroupMax; Group++) {
+ GpioUnlockDataRecords += GPIO_GET_DW_NUM (GpioGetPadPerGroup (Group)) + 1;
+ }
+
+ HobData = BuildGuidHob (&gGpioLibUnlockHobGuid, GpioUnlockDataRecords * sizeof (GPIO_UNLOCK_HOB_DATA));
+ if (HobData == NULL) {
+ return NULL;
+ }
+
+ ZeroMem (HobData, GpioUnlockDataRecords * sizeof (GPIO_UNLOCK_HOB_DATA));
+
+ return (GPIO_UNLOCK_HOB_DATA*)HobData;
+}
+
+/**
+ This procedure will Get GPIO Unlock data structure for storing unlock data.
+ If HOB doesn't exist it will be created.
+
+ @param[out] GpioUnlockData pointer to GPIO Unlock data structure
+
+ @retval Length number of GPIO unlock data records
+**/
+STATIC
+UINT32
+GpioGetUnlockData (
+ GPIO_UNLOCK_HOB_DATA **GpioUnlockData
+ )
+{
+ VOID *Hob;
+
+ Hob = GetFirstGuidHob (&gGpioLibUnlockHobGuid);
+ if (Hob == NULL) {
+ //
+ // It is the first time this function is used so create the HOB
+ //
+ *GpioUnlockData = GpioCreateUnlockData ();
+ if (*GpioUnlockData == NULL) {
+ return 0;
+ }
+ Hob = GetFirstGuidHob (&gGpioLibUnlockHobGuid);
+ } else {
+ *GpioUnlockData = (GPIO_UNLOCK_HOB_DATA*) GET_GUID_HOB_DATA (Hob);
+ }
+ return GET_GUID_HOB_DATA_SIZE (Hob) / sizeof (GPIO_UNLOCK_HOB_DATA);
+}
+
+/**
+ This procedure stores GPIO group data about pads which PadConfig needs to be unlocked.
+
+ @param[in] GroupIndex GPIO group index
+ @param[in] DwNum DWORD index for a group.
+ For group which has less then 32 pads per group DwNum must be 0.
+ @param[in] UnlockedPads DWORD bitmask for pads which are going to be left unlocked
+ Bit position - PadNumber
+ Bit value - 0: Skip, 1: Leave unlocked
+
+ @retval Status
+**/
+EFI_STATUS
+GpioStoreGroupDwUnlockPadConfigData (
+ IN UINT32 GroupIndex,
+ IN UINT32 DwNum,
+ IN UINT32 UnlockedPads
+ )
+{
+ GPIO_UNLOCK_HOB_DATA *GpioUnlockData;
+ UINT32 Length;
+ UINT32 Index;
+
+ if (UnlockedPads == 0) {
+ //
+ // No pads to be left unlocked
+ //
+ return EFI_SUCCESS;
+ }
+
+ Length = GpioGetUnlockData (&GpioUnlockData);
+ if (Length == 0) {
+ return EFI_NOT_FOUND;
+ }
+
+ Index = GpioUnlockDataIndex (GroupIndex, DwNum);
+ if (Index >= Length) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ GpioUnlockData[Index].PadConfig |= UnlockedPads;
+ return EFI_SUCCESS;
+}
+
+/**
+ This procedure stores GPIO group data about pads which Output state needs to be unlocked.
+
+ @param[in] GroupIndex GPIO group index
+ @param[in] DwNum DWORD index for a group.
+ For group which has less then 32 pads per group DwNum must be 0.
+ @param[in] UnlockedPads DWORD bitmask for pads which are going to be left unlocked
+ Bit position - PadNumber
+ Bit value - 0: Skip, 1: Leave unlocked
+ @retval Status
+**/
+EFI_STATUS
+GpioStoreGroupDwUnlockOutputData (
+ IN UINT32 GroupIndex,
+ IN UINT32 DwNum,
+ IN UINT32 UnlockedPads
+ )
+{
+ GPIO_UNLOCK_HOB_DATA *GpioUnlockData;
+ UINT32 Length;
+ UINT32 Index;
+
+ if (UnlockedPads == 0) {
+ //
+ // No pads to be left unlocked
+ //
+ return EFI_SUCCESS;
+ }
+
+ Length = GpioGetUnlockData (&GpioUnlockData);
+ if (Length == 0) {
+ return EFI_NOT_FOUND;
+ }
+
+ Index = GpioUnlockDataIndex (GroupIndex, DwNum);
+ if (Index >= Length) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ GpioUnlockData[Index].OutputState |= UnlockedPads;
+ return EFI_SUCCESS;
+}
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiGpioHelpersLib/PeiGpioHelpersLib.inf b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiGpioHelpersLib/PeiGpioHelpersLib.inf
new file mode 100644
index 0000000000..c1886b22f9
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiGpioHelpersLib/PeiGpioHelpersLib.inf
@@ -0,0 +1,46 @@
+## @file
+# Component description file for the PeiGpioHelpersLib
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+
+[Defines]
+INF_VERSION = 0x00010017
+BASE_NAME = PeiGpioHelpersLib
+FILE_GUID = 1838E1E7-3CC4-4A74-90D9-B421EF2A579F
+VERSION_STRING = 1.0
+MODULE_TYPE = PEIM
+LIBRARY_CLASS = GpioHelpersLib
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = IA32 X64 IPF EBC
+#
+
+
+[LibraryClasses]
+BaseLib
+IoLib
+DebugLib
+HobLib
+GpioLib
+ConfigBlockLib
+PeiServicesLib
+
+
+[Packages]
+MdePkg/MdePkg.dec
+AlderlakeSiliconPkg/SiPkg.dec
+
+
+[Sources]
+PeiGpioHelpersLib.c
+
+
+[Guids]
+gGpioLibUnlockHobGuid
+
+[Ppis]
+gSiPreMemPolicyPpiGuid
--
2.36.1.windows.1
-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#108677): https://edk2.groups.io/g/devel/message/108677
Mute This Topic: https://groups.io/mt/101373944/7686176
Group Owner: devel+owner@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [rebecca@openfw.io]
-=-=-=-=-=-=-=-=-=-=-=-
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [edk2-devel] [PATCH v2 02/10] AlderlakeSiliconPkg/IpBlock: Add Graphics, HostBridge, PcieRp components
2023-09-15 4:45 [edk2-devel] [PATCH v2 01/10] AlderlakeSiliconPkg/IpBlock: Add CpuPcieRp, Espi, Gpio components Saloni Kasbekar
@ 2023-09-15 4:45 ` Saloni Kasbekar
2023-09-15 5:42 ` Chaganty, Rangasai V
2023-09-15 23:56 ` Nate DeSimone
2023-09-15 4:45 ` [edk2-devel] [PATCH v2 03/10] AlderlakeSiliconPkg/IpBlock: Add P2sb, PchDmi components Saloni Kasbekar
` (10 subsequent siblings)
11 siblings, 2 replies; 41+ messages in thread
From: Saloni Kasbekar @ 2023-09-15 4:45 UTC (permalink / raw)
To: devel; +Cc: Saloni Kasbekar, Sai Chaganty, Nate DeSimone, Rosen Chuang
Adds the following modules:
- IpBlock/Graphics/Include
- IpBlock/Graphics/IncludePrivate
- IpBlock/Graphics/Library
- IpBlock/Graphics/LibraryPrivate
- IpBlock/HostBridge/IncludePrivate
- IpBlock/PcieRp/Library
Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Rosen Chuang <rosen.chuang@intel.com>
Signed-off-by: Saloni Kasbekar <saloni.kasbekar@intel.com>
---
.../Include/Ppi/GraphicsPlatformPolicyPpi.h | 76 +++++++++++
.../Library/DxeGraphicsPolicyLib.h | 71 +++++++++++
.../Library/DxeIgdOpRegionInitLib.h | 115 +++++++++++++++++
.../GraphicsInfoLibVer1.c | 52 ++++++++
.../GraphicsInfoLibVer1.inf | 33 +++++
.../DxeGraphicsPolicyLib.c | 116 +++++++++++++++++
.../DxeGraphicsPolicyLib.inf | 36 ++++++
.../DxeIgdOpRegionInit.c | 119 ++++++++++++++++++
.../DxeIgdOpRegionInitLib.inf | 47 +++++++
.../IncludePrivate/HostBridgeDataHob.h | 25 ++++
.../PchPcieRpLibInternal.h | 20 +++
.../PeiDxeSmmPchPcieRpLib/PchPcieRpLibVer2.c | 71 +++++++++++
.../PeiDxeSmmPchPcieRpLibVer2.inf | 37 ++++++
13 files changed, 818 insertions(+)
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/Include/Ppi/GraphicsPlatformPolicyPpi.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/IncludePrivate/Library/DxeGraphicsPolicyLib.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/IncludePrivate/Library/DxeIgdOpRegionInitLib.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/Library/PeiDxeSmmGraphicsInfoLib/GraphicsInfoLibVer1.c
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/Library/PeiDxeSmmGraphicsInfoLib/GraphicsInfoLibVer1.inf
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/LibraryPrivate/DxeGraphicsPolicyLib/DxeGraphicsPolicyLib.c
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/LibraryPrivate/DxeGraphicsPolicyLib/DxeGraphicsPolicyLib.inf
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/LibraryPrivate/DxeIgdOpRegionInitLib/DxeIgdOpRegionInit.c
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/LibraryPrivate/DxeIgdOpRegionInitLib/DxeIgdOpRegionInitLib.inf
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/HostBridge/IncludePrivate/HostBridgeDataHob.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PcieRp/Library/PeiDxeSmmPchPcieRpLib/PchPcieRpLibInternal.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PcieRp/Library/PeiDxeSmmPchPcieRpLib/PchPcieRpLibVer2.c
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PcieRp/Library/PeiDxeSmmPchPcieRpLib/PeiDxeSmmPchPcieRpLibVer2.inf
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/Include/Ppi/GraphicsPlatformPolicyPpi.h b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/Include/Ppi/GraphicsPlatformPolicyPpi.h
new file mode 100644
index 0000000000..a8f67061a5
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/Include/Ppi/GraphicsPlatformPolicyPpi.h
@@ -0,0 +1,76 @@
+/** @file
+ The PEI_GRAPHICS_PLATFORM_POLICY_PPI provides platform information to PEI Graphics PEIM.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PEI_GRAPHICS_PLATFORM_POLICY_PPI_H_
+#define _PEI_GRAPHICS_PLATFORM_POLICY_PPI_H_
+
+/**
+ Globally unique identifier for PEI platform policy PPI.
+**/
+#define PEI_GRAPHICS_PLATFORM_POLICY_PPI_GUID \
+{ \
+ 0x4eabcd09, 0x43d3, 0x4b4d, { 0xb7, 0x3d, 0x43, 0xc8, 0xd9, 0x89, 0x99, 0x5 } \
+}
+
+#define PEI_GRAPHICS_PLATFORM_POLICY_REVISION 1
+
+/**
+Pre-declaration of PEI graphics platform policy PPI.
+**/
+typedef struct _PEI_GRAPHICS_PLATFORM_POLICY_PPI PEI_GRAPHICS_PLATFORM_POLICY_PPI;
+
+/**
+ Enum defining the different lid status values
+**/
+typedef enum {
+ LidClosed,
+ LidOpen,
+ LidStatusMax
+} LID_STATUS;
+
+/**
+ This function gets the platform lid status for LFP displays.
+
+ @param[out] CurrentLidStatus Output variable to store the lid status.
+
+ @retval EFI_SUCCESS Correct lid status is returned.
+ @retval EFI_UNSUPPORTED Platform does not support lid.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *GET_PLATFORM_LID_STATUS) (
+ OUT LID_STATUS *CurrentLidStatus
+ );
+
+/**
+ This function gets the base address of loaded VBT.
+
+ @param[out] VbtAddress Starting address of the VBT is returned in this parameter.
+ @param[out] VbtSize Size of the VBT is returned in this parameter.
+
+ @retval EFI_SUCCESS If the VBT is loaded and parameters contain valid values.
+ @return Other error codes meaning VBT is not loaded and parameters contain invalid values.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *GET_VBT_DATA) (
+ OUT EFI_PHYSICAL_ADDRESS *VbtAddress,
+ OUT UINT32 *VbtSize
+ );
+
+/**
+ This defines the PEI Graphics Platform Policy PPI structure.
+**/
+struct _PEI_GRAPHICS_PLATFORM_POLICY_PPI {
+ UINT32 Revision; ///< Revision of current implementation.
+ GET_PLATFORM_LID_STATUS GetPlatformLidStatus; ///< Function Pointer for get platform lid status.
+ GET_VBT_DATA GetVbtData; ///< Function pointer for get vbt data.
+};
+
+extern EFI_GUID gPeiGraphicsPlatformPpiGuid;
+
+#endif
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/IncludePrivate/Library/DxeGraphicsPolicyLib.h b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/IncludePrivate/Library/DxeGraphicsPolicyLib.h
new file mode 100644
index 0000000000..0347d4c94c
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/IncludePrivate/Library/DxeGraphicsPolicyLib.h
@@ -0,0 +1,71 @@
+/** @file
+ Header file for the DXE Graphics Policy Init library.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _DXE_GRAPHICS_POLICY_LIB_H_
+#define _DXE_GRAPHICS_POLICY_LIB_H_
+
+#include <Uefi.h>
+#include <Library/DebugLib.h>
+#include <Library/UefiLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Protocol/SaPolicy.h>
+#include <ConfigBlock.h>
+#include <GraphicsConfig.h>
+#include <Library/SiConfigBlockLib.h>
+
+#define WORD_FIELD_VALID_BIT BIT15
+
+extern EFI_GUID gGraphicsDxeConfigGuid;
+
+/**
+ This function prints the Graphics DXE phase policy.
+
+ @param[in] SaPolicy - SA DXE Policy protocol
+**/
+VOID
+GraphicsDxePolicyPrint (
+ IN SA_POLICY_PROTOCOL *SaPolicy
+ );
+
+/**
+ This function Load default Graphics DXE policy.
+
+ @param[in] ConfigBlockPointer The pointer to add Graphics config block
+**/
+VOID
+LoadIgdDxeDefault (
+ IN VOID *ConfigBlockPointer
+ );
+
+
+/**
+ Get DXE Graphics config block table total size.
+
+ @retval Size of DXE Graphics config block table
+**/
+UINT16
+EFIAPI
+GraphicsGetConfigBlockTotalSizeDxe (
+ VOID
+ );
+
+/**
+ GraphicsAddConfigBlocksDxe add all DXE Graphics config block.
+
+ @param[in] ConfigBlockTableAddress The pointer to add SA config blocks
+
+ @retval EFI_SUCCESS The policy default is initialized.
+ @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer
+**/
+EFI_STATUS
+EFIAPI
+GraphicsAddConfigBlocksDxe (
+ IN VOID *ConfigBlockTableAddress
+ );
+
+#endif // _DXE_GRAPHICs_POLICY_LIBRARY_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/IncludePrivate/Library/DxeIgdOpRegionInitLib.h b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/IncludePrivate/Library/DxeIgdOpRegionInitLib.h
new file mode 100644
index 0000000000..02e4988b2b
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/IncludePrivate/Library/DxeIgdOpRegionInitLib.h
@@ -0,0 +1,115 @@
+/** @file
+ This is part of the implementation of an Intel Graphics drivers OpRegion /
+ Software SCI interface between system BIOS, ASL code, and Graphics drivers.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _DXE_IGD_OPREGION_INIT_LIB_H_
+#define _DXE_IGD_OPREGION_INIT_LIB_H_
+
+///
+/// Statements that include other header files.
+///
+#include <Uefi.h>
+#include <Uefi/UefiBaseType.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <IndustryStandard/Pci.h>
+#include <Library/ConfigBlockLib.h>
+#include <Library/PciSegmentLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/IoLib.h>
+#include <Library/DebugLib.h>
+#include <Library/HobLib.h>
+#include <Library/UefiLib.h>
+#include <Library/S3BootScriptLib.h>
+#include <Register/IgdRegs.h>
+#include <SiConfigHob.h>
+#include <Register/SaRegsHostBridge.h>
+///
+/// Driver Consumed Protocol Prototypes
+///
+#include <Protocol/PciIo.h>
+#include <Protocol/PciRootBridgeIo.h>
+#include <Protocol/SaPolicy.h>
+///
+/// Driver Produced Protocol Prototypes
+///
+#include <Protocol/IgdOpRegion.h>
+
+#pragma pack(push, 1)
+///
+///
+/// OpRegion (Miscellaneous) defines.
+///
+/// OpRegion Header defines.
+///
+typedef UINT16 STRING_REF;
+///
+/// Typedef stuctures
+///
+typedef struct {
+ UINT16 Signature; /// 0xAA55
+ UINT8 Size512;
+ UINT8 Reserved[21];
+ UINT16 PcirOffset;
+ UINT16 VbtOffset;
+} INTEL_VBIOS_OPTION_ROM_HEADER;
+
+typedef struct {
+ UINT32 Signature; /// "PCIR"
+ UINT16 VendorId; /// 0x8086
+ UINT16 DeviceId;
+ UINT16 Reserved0;
+ UINT16 Length;
+ UINT8 Revision;
+ UINT8 ClassCode[3];
+ UINT16 ImageLength;
+ UINT16 CodeRevision;
+ UINT8 CodeType;
+ UINT8 Indicator;
+ UINT16 Reserved1;
+} INTEL_VBIOS_PCIR_STRUCTURE;
+
+typedef struct {
+ UINT8 HeaderSignature[20];
+ UINT16 HeaderVersion;
+ UINT16 HeaderSize;
+ UINT16 HeaderVbtSize;
+ UINT8 HeaderVbtCheckSum;
+ UINT8 HeaderReserved;
+ UINT32 HeaderOffsetVbtDataBlock;
+ UINT32 HeaderOffsetAim1;
+ UINT32 HeaderOffsetAim2;
+ UINT32 HeaderOffsetAim3;
+ UINT32 HeaderOffsetAim4;
+ UINT8 DataHeaderSignature[16];
+ UINT16 DataHeaderVersion;
+ UINT16 DataHeaderSize;
+ UINT16 DataHeaderDataBlockSize;
+ UINT8 CoreBlockId;
+ UINT16 CoreBlockSize;
+ UINT16 CoreBlockBiosSize;
+ UINT8 CoreBlockBiosType;
+ UINT8 CoreBlockReleaseStatus;
+ UINT8 CoreBlockHWSupported;
+ UINT8 CoreBlockIntegratedHW;
+ UINT8 CoreBlockBiosBuild[4];
+ UINT8 CoreBlockBiosSignOn[155];
+} VBIOS_VBT_STRUCTURE;
+#pragma pack(pop)
+///
+/// Driver Private Function definitions
+///
+
+/**
+ Update Graphics OpRegion after PCI enumeration.
+
+ @retval EFI_SUCCESS - The function completed successfully.
+**/
+EFI_STATUS
+UpdateIgdOpRegionEndOfDxe (
+ VOID
+ );
+#endif
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/Library/PeiDxeSmmGraphicsInfoLib/GraphicsInfoLibVer1.c b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/Library/PeiDxeSmmGraphicsInfoLib/GraphicsInfoLibVer1.c
new file mode 100644
index 0000000000..9dd9b33a49
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/Library/PeiDxeSmmGraphicsInfoLib/GraphicsInfoLibVer1.c
@@ -0,0 +1,52 @@
+/** @file
+ Source file for common Graphics Info Lib.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#include <Library/GraphicsInfoLib.h>
+#include <Register/IgdRegs.h>
+#include <Library/TimerLib.h>
+#include <Base.h>
+
+/**
+ GetIgdBusNumber: Get IGD Bus Number
+
+ @retval PCI bus number for IGD
+**/
+UINT8
+GetIgdBusNumber (
+ VOID
+ )
+{
+ return (UINT8) IGD_BUS_NUM;
+}
+
+/**
+ GetIgdDevNumber: Get IGD Dev Number
+
+ @retval PCI dev number for IGD
+**/
+UINT8
+GetIgdDevNumber (
+ VOID
+ )
+{
+ return (UINT8) IGD_DEV_NUM;
+}
+
+/**
+ GetIgdFunNumber: Get IGD Fun Number
+
+ @retval PCI fun number for IGD
+**/
+UINT8
+GetIgdFuncNumber (
+ VOID
+ )
+{
+ return (UINT8) IGD_FUN_NUM;
+}
+
+
+
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/Library/PeiDxeSmmGraphicsInfoLib/GraphicsInfoLibVer1.inf b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/Library/PeiDxeSmmGraphicsInfoLib/GraphicsInfoLibVer1.inf
new file mode 100644
index 0000000000..ca363ce105
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/Library/PeiDxeSmmGraphicsInfoLib/GraphicsInfoLibVer1.inf
@@ -0,0 +1,33 @@
+## @file
+# Graphics information library.
+#
+# All function in this library is available for PEI, DXE, and SMM,
+# But do not support UEFI RUNTIME environment call.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+
+[Defines]
+INF_VERSION = 0x00010017
+BASE_NAME = PeiDxeSmmGraphicsInfoLib
+FILE_GUID = AE4D5DE8-F092-4B2A-8003-F1A4CCBDC3E4
+VERSION_STRING = 1.0
+MODULE_TYPE = BASE
+LIBRARY_CLASS = GraphicsInfoLib
+
+[LibraryClasses]
+BaseLib
+IoLib
+DebugLib
+BaseMemoryLib
+PciSegmentLib
+TimerLib
+
+[Packages]
+MdePkg/MdePkg.dec
+AlderlakeSiliconPkg/SiPkg.dec
+
+[Sources]
+GraphicsInfoLibVer1.c
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/LibraryPrivate/DxeGraphicsPolicyLib/DxeGraphicsPolicyLib.c b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/LibraryPrivate/DxeGraphicsPolicyLib/DxeGraphicsPolicyLib.c
new file mode 100644
index 0000000000..a9344b424d
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/LibraryPrivate/DxeGraphicsPolicyLib/DxeGraphicsPolicyLib.c
@@ -0,0 +1,116 @@
+/** @file
+ This file provide services for DXE phase Graphics policy default initialization.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <Library/DxeGraphicsPolicyLib.h>
+
+/**
+ This function prints the Graphics DXE phase policy.
+
+ @param[in] SaPolicy - SA DXE Policy protocol
+**/
+VOID
+GraphicsDxePolicyPrint (
+ IN SA_POLICY_PROTOCOL *SaPolicy
+ )
+{
+ EFI_STATUS Status;
+ GRAPHICS_DXE_CONFIG *GraphicsDxeConfig;
+
+ //
+ // Get requisite IP Config Blocks which needs to be used here
+ //
+ Status = GetConfigBlock ((VOID *) SaPolicy, &gGraphicsDxeConfigGuid, (VOID *)&GraphicsDxeConfig);
+ ASSERT_EFI_ERROR (Status);
+
+
+ DEBUG_CODE_BEGIN ();
+ DEBUG ((DEBUG_INFO, "\n------------------------ Graphics Policy (DXE) print BEGIN -----------------\n"));
+ DEBUG ((DEBUG_INFO, " Revision : %d\n", GraphicsDxeConfig->Header.Revision));
+ ASSERT (GraphicsDxeConfig->Header.Revision == GRAPHICS_DXE_CONFIG_REVISION);
+ DEBUG ((DEBUG_INFO, "\n------------------------ Graphics Policy (DXE) print END -----------------\n"));
+ DEBUG_CODE_END ();
+
+ return;
+}
+
+
+/**
+ This function Load default Graphics DXE policy.
+
+ @param[in] ConfigBlockPointer The pointer to add Graphics config block
+**/
+VOID
+LoadIgdDxeDefault (
+ IN VOID *ConfigBlockPointer
+ )
+{
+ GRAPHICS_DXE_CONFIG *GraphicsDxeConfig;
+
+ GraphicsDxeConfig = ConfigBlockPointer;
+
+ ///
+ /// Initialize the Graphics configuration
+ ///
+ GraphicsDxeConfig->PlatformConfig = 1;
+ GraphicsDxeConfig->AlsEnable = 2;
+ GraphicsDxeConfig->BacklightControlSupport = 2;
+ GraphicsDxeConfig->IgdBlcConfig = 2;
+ GraphicsDxeConfig->GfxTurboIMON = 31;
+ ///
+ /// <EXAMPLE> Create a static Backlight Brightness Level Duty cycle Mapping Table
+ /// Possible 20 entries (example used 11), each 16 bits as follows:
+ /// [15] = Field Valid bit, [14:08] = Level in Percentage (0-64h), [07:00] = Desired duty cycle (0 - FFh).
+ ///
+ GraphicsDxeConfig->BCLM[0] = (0x0000 + WORD_FIELD_VALID_BIT); ///< 0%
+ GraphicsDxeConfig->BCLM[1] = (0x0A19 + WORD_FIELD_VALID_BIT); ///< 10%
+ GraphicsDxeConfig->BCLM[2] = (0x1433 + WORD_FIELD_VALID_BIT); ///< 20%
+ GraphicsDxeConfig->BCLM[3] = (0x1E4C + WORD_FIELD_VALID_BIT); ///< 30%
+ GraphicsDxeConfig->BCLM[4] = (0x2866 + WORD_FIELD_VALID_BIT); ///< 40%
+ GraphicsDxeConfig->BCLM[5] = (0x327F + WORD_FIELD_VALID_BIT); ///< 50%
+ GraphicsDxeConfig->BCLM[6] = (0x3C99 + WORD_FIELD_VALID_BIT); ///< 60%
+ GraphicsDxeConfig->BCLM[7] = (0x46B2 + WORD_FIELD_VALID_BIT); ///< 70%
+ GraphicsDxeConfig->BCLM[8] = (0x50CC + WORD_FIELD_VALID_BIT); ///< 80%
+ GraphicsDxeConfig->BCLM[9] = (0x5AE5 + WORD_FIELD_VALID_BIT); ///< 90%
+ GraphicsDxeConfig->BCLM[10] = (0x64FF + WORD_FIELD_VALID_BIT); ///< 100%
+}
+
+static COMPONENT_BLOCK_ENTRY mGraphicsDxeIpBlocks = {
+ &gGraphicsDxeConfigGuid, sizeof (GRAPHICS_DXE_CONFIG), GRAPHICS_DXE_CONFIG_REVISION, LoadIgdDxeDefault};
+
+
+/**
+ Get DXE Graphics config block table total size.
+
+ @retval Size of DXE Graphics config block table
+**/
+UINT16
+EFIAPI
+GraphicsGetConfigBlockTotalSizeDxe (
+ VOID
+ )
+{
+ return mGraphicsDxeIpBlocks.Size;
+}
+
+/**
+ GraphicsAddConfigBlocksDxe add all DXE Graphics config block.
+
+ @param[in] ConfigBlockTableAddress The pointer to add SA config blocks
+
+ @retval EFI_SUCCESS The policy default is initialized.
+ @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer
+**/
+EFI_STATUS
+EFIAPI
+GraphicsAddConfigBlocksDxe (
+ IN VOID *ConfigBlockTableAddress
+ )
+{
+ EFI_STATUS Status;
+ Status = AddComponentConfigBlocks (ConfigBlockTableAddress, &mGraphicsDxeIpBlocks, 1);
+ return Status;
+}
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/LibraryPrivate/DxeGraphicsPolicyLib/DxeGraphicsPolicyLib.inf b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/LibraryPrivate/DxeGraphicsPolicyLib/DxeGraphicsPolicyLib.inf
new file mode 100644
index 0000000000..0fd6aba0bb
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/LibraryPrivate/DxeGraphicsPolicyLib/DxeGraphicsPolicyLib.inf
@@ -0,0 +1,36 @@
+## @file
+# Component description file for the DXE Graphics Policy Init library.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+[Defines]
+INF_VERSION = 0x00010017
+BASE_NAME = DxeGraphicsPolicyLib
+FILE_GUID = C6190599-287E-40F9-9B46-EE112A322EBF
+VERSION_STRING = 1.0
+MODULE_TYPE = BASE
+LIBRARY_CLASS = DxeGraphicsPolicyLib
+
+[LibraryClasses]
+BaseMemoryLib
+UefiRuntimeServicesTableLib
+UefiBootServicesTableLib
+DebugLib
+PostCodeLib
+ConfigBlockLib
+HobLib
+SiConfigBlockLib
+
+[Packages]
+MdePkg/MdePkg.dec
+AlderlakeSiliconPkg/SiPkg.dec
+
+[Sources]
+DxeGraphicsPolicyLib.c
+
+[Guids]
+gGraphicsDxeConfigGuid
+
+[Pcd]
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/LibraryPrivate/DxeIgdOpRegionInitLib/DxeIgdOpRegionInit.c b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/LibraryPrivate/DxeIgdOpRegionInitLib/DxeIgdOpRegionInit.c
new file mode 100644
index 0000000000..b3c9d28078
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/LibraryPrivate/DxeIgdOpRegionInitLib/DxeIgdOpRegionInit.c
@@ -0,0 +1,119 @@
+/** @file
+ This is part of the implementation of an Intel Graphics drivers OpRegion /
+ Software SCI interface between system BIOS, ASL code, and Graphics drivers.
+ The code in this file will load the driver and initialize the interface
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <Library/DxeIgdOpRegionInitLib.h>
+
+
+
+GLOBAL_REMOVE_IF_UNREFERENCED IGD_OPREGION_PROTOCOL mIgdOpRegion;
+
+
+/**
+ Update Graphics OpRegion after PCI enumeration.
+
+ @param[in] void - None
+ @retval EFI_SUCCESS - The function completed successfully.
+**/
+EFI_STATUS
+UpdateIgdOpRegionEndOfDxe (
+ VOID
+)
+{
+ EFI_STATUS Status;
+ UINTN HandleCount;
+ EFI_HANDLE *HandleBuffer;
+ UINTN Index;
+ EFI_PCI_IO_PROTOCOL *PciIo;
+ PCI_TYPE00 Pci;
+ UINTN Segment;
+ UINTN Bus;
+ UINTN Device;
+ UINTN Function;
+
+ Bus = 0;
+ Device = 0;
+ Function = 0;
+
+ DEBUG ((DEBUG_INFO, "UpdateIgdOpRegionEndOfDxe\n"));
+
+ mIgdOpRegion.OpRegion->Header.PCON |= BIT8; //Set External Gfx Adapter field is valid
+ mIgdOpRegion.OpRegion->Header.PCON &= (UINT32) (~BIT7); //Assume No External Gfx Adapter
+
+ ///
+ /// Get all PCI IO protocols handles
+ ///
+ Status = gBS->LocateHandleBuffer (
+ ByProtocol,
+ &gEfiPciIoProtocolGuid,
+ NULL,
+ &HandleCount,
+ &HandleBuffer
+ );
+
+ if (!EFI_ERROR (Status)) {
+ for (Index = 0; Index < HandleCount; Index++) {
+ ///
+ /// Get the PCI IO Protocol Interface corresponding to each handle
+ ///
+ Status = gBS->HandleProtocol (
+ HandleBuffer[Index],
+ &gEfiPciIoProtocolGuid,
+ (VOID **) &PciIo
+ );
+
+ if (!EFI_ERROR (Status)) {
+ ///
+ /// Read the PCI configuration space
+ ///
+ Status = PciIo->Pci.Read (
+ PciIo,
+ EfiPciIoWidthUint32,
+ 0,
+ sizeof (Pci) / sizeof (UINT32),
+ &Pci
+ );
+
+ ///
+ /// Find the display controllers devices
+ ///
+ if (!EFI_ERROR (Status) && IS_PCI_DISPLAY (&Pci)) {
+ Status = PciIo->GetLocation (
+ PciIo,
+ &Segment,
+ &Bus,
+ &Device,
+ &Function
+ );
+
+ //
+ // Assumption: Onboard devices will be sits on Bus no 0, while external devices will be sits on Bus no > 0
+ //
+ if (!EFI_ERROR (Status) && (Bus > 0)) {
+ //External Gfx Adapter Detected and Available
+ DEBUG ((DEBUG_INFO, "PCON - External Gfx Adapter Detected and Available\n"));
+ mIgdOpRegion.OpRegion->Header.PCON |= BIT7;
+ break;
+ }
+ }
+ }
+ }
+ }
+
+ ///
+ /// Free any allocated buffers
+ ///
+ if (HandleBuffer != NULL) {
+ FreePool (HandleBuffer);
+ }
+
+ ///
+ /// Return final status
+ ///
+ return Status;
+}
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/LibraryPrivate/DxeIgdOpRegionInitLib/DxeIgdOpRegionInitLib.inf b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/LibraryPrivate/DxeIgdOpRegionInitLib/DxeIgdOpRegionInitLib.inf
new file mode 100644
index 0000000000..e3a56d5563
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/LibraryPrivate/DxeIgdOpRegionInitLib/DxeIgdOpRegionInitLib.inf
@@ -0,0 +1,47 @@
+## @file
+# Component description file for the Dxe IGD OpRegion library.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+[Defines]
+INF_VERSION = 0x00010017
+BASE_NAME = DxeIgdOpRegionInitLib
+FILE_GUID = 18D47D72-555E-475B-A4E4-AD20C3BD8B15
+VERSION_STRING = 1.0
+MODULE_TYPE = DXE_DRIVER
+UEFI_SPECIFICATION_VERSION = 2.00
+LIBRARY_CLASS = DxeIgdOpRegionInitLib
+
+[LibraryClasses]
+UefiLib
+UefiRuntimeServicesTableLib
+UefiBootServicesTableLib
+DebugLib
+PostCodeLib
+ConfigBlockLib
+PciSegmentLib
+BaseMemoryLib
+MemoryAllocationLib
+IoLib
+S3BootScriptLib
+
+[Packages]
+MdePkg/MdePkg.dec
+AlderlakeSiliconPkg/SiPkg.dec
+IntelSiliconPkg/IntelSiliconPkg.dec
+
+[Pcd]
+gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress
+
+[Sources]
+DxeIgdOpRegionInit.c
+
+[Guids]
+gGraphicsDxeConfigGuid ## CONSUMES
+
+[Protocols]
+gIgdOpRegionProtocolGuid ## PRODUCES
+gSaPolicyProtocolGuid ## CONSUMES
+gEfiPciIoProtocolGuid ## CONSUMES
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/HostBridge/IncludePrivate/HostBridgeDataHob.h b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/HostBridge/IncludePrivate/HostBridgeDataHob.h
new file mode 100644
index 0000000000..671e821342
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/HostBridge/IncludePrivate/HostBridgeDataHob.h
@@ -0,0 +1,25 @@
+/** @file
+ The GUID definition for Host Bridge Data Hob
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _HOST_BRIDGE_DATA_HOB_H_
+#define _HOST_BRIDGE_DATA_HOB_H_
+
+#include <Base.h>
+
+extern EFI_GUID gHostBridgeDataHobGuid;
+#pragma pack (push,1)
+
+///
+/// Host Bridge Data Hob
+///
+typedef struct {
+ EFI_HOB_GUID_TYPE EfiHobGuidType; ///< GUID Hob type structure for gSaDataHobGuid
+ UINT8 EnableAbove4GBMmio; ///< 0=Disable above 4GB MMIO resource support, 1=Enable above 4GB MMIO resource support
+ BOOLEAN SkipPamLock; ///< 0=All PAM registers will be locked in System Agent code, 1=Do not lock PAM registers in System Agent code.
+ UINT8 Rsvd1[2]; ///< Reserved for future use
+} HOST_BRIDGE_DATA_HOB;
+#pragma pack (pop)
+#endif
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PcieRp/Library/PeiDxeSmmPchPcieRpLib/PchPcieRpLibInternal.h b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PcieRp/Library/PeiDxeSmmPchPcieRpLib/PchPcieRpLibInternal.h
new file mode 100644
index 0000000000..e2be00fae7
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PcieRp/Library/PeiDxeSmmPchPcieRpLib/PchPcieRpLibInternal.h
@@ -0,0 +1,20 @@
+/** @file
+ PCIE root port library.
+ All function in this library is available for PEI, DXE, and SMM,
+ But do not support UEFI RUNTIME environment call.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PCH_PCIE_RP_LIB_INTERNAL_H_
+#define _PCH_PCIE_RP_LIB_INTERNAL_H_
+
+typedef struct {
+ UINT8 DevNum;
+ UINT8 Pid;
+ UINT8 RpNumBase;
+} PCH_PCIE_CONTROLLER_INFO;
+
+#endif
+
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PcieRp/Library/PeiDxeSmmPchPcieRpLib/PchPcieRpLibVer2.c b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PcieRp/Library/PeiDxeSmmPchPcieRpLib/PchPcieRpLibVer2.c
new file mode 100644
index 0000000000..0702792597
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PcieRp/Library/PeiDxeSmmPchPcieRpLib/PchPcieRpLibVer2.c
@@ -0,0 +1,71 @@
+/** @file
+ PCIE root port library.
+ All function in this library is available for PEI, DXE, and SMM,
+ But do not support UEFI RUNTIME environment call.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <Base.h>
+#include <Uefi/UefiBaseType.h>
+#include <Library/IoLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseLib.h>
+#include <Library/PciSegmentLib.h>
+#include <Library/PchInfoLib.h>
+#include <Library/PchPcrLib.h>
+#include <Library/PchPcieRpLib.h>
+#include <Register/PchRegs.h>
+#include <PchBdfAssignment.h>
+#include <PchPcieRpInfo.h>
+#include <Register/PchPcieRpRegs.h>
+#include <Register/PchPcrRegs.h>
+
+#include "PchPcieRpLibInternal.h"
+
+GLOBAL_REMOVE_IF_UNREFERENCED PCH_PCIE_CONTROLLER_INFO mPchPcieControllerInfo[] = {
+ { PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_1, PID_SPA, 0 },
+ { PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_5, PID_SPB, 4 },
+ { PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_9, PID_SPC, 8 },
+ { PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_13, PID_SPD, 12 },
+ { PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_17, PID_SPE, 16 }, // PCH-H only
+ { PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_21, PID_SPF, 20 } // PCH-H only
+};
+
+/**
+ Get Pch Pcie Root Port Device and Function Number by Root Port physical Number
+
+ @param[in] RpNumber Root port physical number. (0-based)
+ @param[out] RpDev Return corresponding root port device number.
+ @param[out] RpFun Return corresponding root port function number.
+
+ @retval EFI_SUCCESS Root port device and function is retrieved
+ @retval EFI_INVALID_PARAMETER RpNumber is invalid
+**/
+EFI_STATUS
+EFIAPI
+GetPchPcieRpDevFun (
+ IN UINTN RpNumber,
+ OUT UINTN *RpDev,
+ OUT UINTN *RpFun
+ )
+{
+ UINTN Index;
+ UINTN FuncIndex;
+ UINT32 PciePcd;
+
+ if (RpNumber >= GetPchMaxPciePortNum ()) {
+ DEBUG ((DEBUG_ERROR, "GetPchPcieRpDevFun invalid RpNumber %x", RpNumber));
+ ASSERT (FALSE);
+ return EFI_INVALID_PARAMETER;
+ }
+
+ Index = RpNumber / PCH_PCIE_CONTROLLER_PORTS;
+ FuncIndex = RpNumber - mPchPcieControllerInfo[Index].RpNumBase;
+ *RpDev = mPchPcieControllerInfo[Index].DevNum;
+ PciePcd = PchPcrRead32 (mPchPcieControllerInfo[Index].Pid, R_SPX_PCR_PCD);
+ *RpFun = (PciePcd >> (FuncIndex * S_SPX_PCR_PCD_RP_FIELD)) & B_SPX_PCR_PCD_RP1FN;
+
+ return EFI_SUCCESS;
+}
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PcieRp/Library/PeiDxeSmmPchPcieRpLib/PeiDxeSmmPchPcieRpLibVer2.inf b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PcieRp/Library/PeiDxeSmmPchPcieRpLib/PeiDxeSmmPchPcieRpLibVer2.inf
new file mode 100644
index 0000000000..0acafbfc43
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PcieRp/Library/PeiDxeSmmPchPcieRpLib/PeiDxeSmmPchPcieRpLibVer2.inf
@@ -0,0 +1,37 @@
+## @file
+# PCIE root port Library.
+#
+# All function in this library is available for PEI, DXE, and SMM,
+# But do not support UEFI RUNTIME environment call.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+
+[Defines]
+INF_VERSION = 0x00010017
+BASE_NAME = PeiDxeSmmPchPcieRpLib
+FILE_GUID = B522981C-E0C5-4E04-A82A-C61D4F0B2C75
+VERSION_STRING = 1.0
+MODULE_TYPE = BASE
+LIBRARY_CLASS = PchPcieRpLib
+
+
+[LibraryClasses]
+BaseLib
+IoLib
+DebugLib
+PciSegmentLib
+PchInfoLib
+PchPcrLib
+
+
+[Packages]
+MdePkg/MdePkg.dec
+AlderlakeSiliconPkg/SiPkg.dec
+
+
+[Sources]
+PchPcieRpLibVer2.c
+
--
2.36.1.windows.1
-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#108678): https://edk2.groups.io/g/devel/message/108678
Mute This Topic: https://groups.io/mt/101373945/7686176
Group Owner: devel+owner@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [rebecca@openfw.io]
-=-=-=-=-=-=-=-=-=-=-=-
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [edk2-devel] [PATCH v2 03/10] AlderlakeSiliconPkg/IpBlock: Add P2sb, PchDmi components
2023-09-15 4:45 [edk2-devel] [PATCH v2 01/10] AlderlakeSiliconPkg/IpBlock: Add CpuPcieRp, Espi, Gpio components Saloni Kasbekar
2023-09-15 4:45 ` [edk2-devel] [PATCH v2 02/10] AlderlakeSiliconPkg/IpBlock: Add Graphics, HostBridge, PcieRp components Saloni Kasbekar
@ 2023-09-15 4:45 ` Saloni Kasbekar
2023-09-15 5:42 ` Chaganty, Rangasai V
2023-09-15 23:56 ` Nate DeSimone
2023-09-15 4:45 ` [edk2-devel] [PATCH v2 04/10] AlderlakeSiliconPkg/IpBlock: Add Pmc, Spi components Saloni Kasbekar
` (9 subsequent siblings)
11 siblings, 2 replies; 41+ messages in thread
From: Saloni Kasbekar @ 2023-09-15 4:45 UTC (permalink / raw)
To: devel; +Cc: Saloni Kasbekar, Sai Chaganty, Nate DeSimone, Rosen Chuang
Adds the following modules:
- IpBlock/P2sb/IncludePrivate
- IpBlock/P2sb/Library
- IpBlock/P2sb/LibraryPrivate
- IpBlock/PchDmi/IncludePrivate
- IpBlock/PchDmi/LibraryPrivate
Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Rosen Chuang <rosen.chuang@intel.com>
Signed-off-by: Saloni Kasbekar <saloni.kasbekar@intel.com>
---
.../Library/P2SbSidebandAccessLib.h | 105 +++++++
.../IncludePrivate/Library/PchSbiAccessLib.h | 58 ++++
.../P2sb/IncludePrivate/P2SbController.h | 32 +++
.../P2sb/IncludePrivate/Register/P2sbRegs.h | 53 ++++
.../Library/PeiDxeSmmPchPcrLib/PchPcrLib.c | 266 ++++++++++++++++++
.../PeiDxeSmmPchPcrLib/PeiDxeSmmPchPcrLib.inf | 35 +++
.../PeiDxeSmmP2SbSidebandAccessLib.c | 208 ++++++++++++++
.../PeiDxeSmmP2SbSidebandAccessLib.inf | 30 ++
.../PchSbiAccessLib.c | 72 +++++
.../PeiDxeSmmPchSbiAccessLib.inf | 35 +++
.../PchDmi/IncludePrivate/Library/PchDmiLib.h | 60 ++++
.../PeiDxeSmmPchDmiLib/PchDmi14.c | 34 +++
.../PeiDxeSmmPchDmiLib/PchDmi14.h | 22 ++
.../PeiDxeSmmPchDmiLib/PchDmiLib.c | 110 ++++++++
.../PeiDxeSmmPchDmiLib/PeiDxeSmmPchDmiLib.inf | 43 +++
15 files changed, 1163 insertions(+)
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/IncludePrivate/Library/P2SbSidebandAccessLib.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/IncludePrivate/Library/PchSbiAccessLib.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/IncludePrivate/P2SbController.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/IncludePrivate/Register/P2sbRegs.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/Library/PeiDxeSmmPchPcrLib/PchPcrLib.c
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/Library/PeiDxeSmmPchPcrLib/PeiDxeSmmPchPcrLib.inf
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/LibraryPrivate/PeiDxeSmmP2SbSidebandAccessLib/PeiDxeSmmP2SbSidebandAccessLib.c
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/LibraryPrivate/PeiDxeSmmP2SbSidebandAccessLib/PeiDxeSmmP2SbSidebandAccessLib.inf
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/LibraryPrivate/PeiDxeSmmPchSbiAccessLib/PchSbiAccessLib.c
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/LibraryPrivate/PeiDxeSmmPchSbiAccessLib/PeiDxeSmmPchSbiAccessLib.inf
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PchDmi/IncludePrivate/Library/PchDmiLib.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivate/PeiDxeSmmPchDmiLib/PchDmi14.c
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivate/PeiDxeSmmPchDmiLib/PchDmi14.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivate/PeiDxeSmmPchDmiLib/PchDmiLib.c
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivate/PeiDxeSmmPchDmiLib/PeiDxeSmmPchDmiLib.inf
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/IncludePrivate/Library/P2SbSidebandAccessLib.h b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/IncludePrivate/Library/P2SbSidebandAccessLib.h
new file mode 100644
index 0000000000..e364508eb4
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/IncludePrivate/Library/P2SbSidebandAccessLib.h
@@ -0,0 +1,105 @@
+/** @file
+ Header for P2SbSidebandAccessLib
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _P2SB_SIDEBAND_ACCESS_LIB_H_
+#define _P2SB_SIDEBAND_ACCESS_LIB_H_
+
+#include <RegisterAccess.h>
+#include <P2SbController.h>
+#include <Library/PchPcrLib.h> // For PCH_SBI_PID definition
+
+typedef PCH_SBI_PID P2SB_PID;
+
+typedef enum {
+ P2SbMemory = 0,
+ P2SbPciConfig,
+ P2SbPrivateConfig
+} P2SB_REGISTER_SPACE;
+
+typedef enum {
+ MemoryRead = 0x0,
+ MemoryWrite = 0x1,
+ PciConfigRead = 0x4,
+ PciConfigWrite = 0x5,
+ PrivateControlRead = 0x6,
+ PrivateControlWrite = 0x7,
+ GpioLockUnlock = 0x13
+} P2SB_SBI_OPCODE;
+
+typedef enum {
+ SBI_SUCCESSFUL = 0,
+ SBI_UNSUCCESSFUL = 1,
+ SBI_POWERDOWN = 2,
+ SBI_MIXED = 3,
+ SBI_INVALID_RESPONSE
+} P2SB_SBI_RESPONSE;
+
+typedef enum {
+ P2SbMmioAccess = 0,
+ P2SbMsgAccess
+} P2SB_SIDEBAND_ACCESS_METHOD;
+
+/**
+ REGISTER_ACCESS for P2SB device to support access to sideband registers.
+ Be sure to keep first member of this structure as REGISTER_ACCESS to allow
+ for correct casting between caller who sees this structure as REGISTER_ACCESS
+ and calle who will cast it to P2SB_SIDEBAND_REGISTER_ACCESS.
+**/
+typedef struct {
+ REGISTER_ACCESS Access;
+ P2SB_SIDEBAND_ACCESS_METHOD AccessMethod;
+ P2SB_PID P2SbPid;
+ UINT16 Fid;
+ P2SB_REGISTER_SPACE RegisterSpace;
+ BOOLEAN PostedWrites;
+ P2SB_CONTROLLER *P2SbCtrl;
+} P2SB_SIDEBAND_REGISTER_ACCESS;
+
+/**
+ Full function for executing P2SB SBI message
+ Take care of that there is no lock protection when using SBI programming in both POST time and SMI.
+ It will clash with POST time SBI programming when SMI happen.
+ Programmer MUST do the save and restore opration while using the PchSbiExecution inside SMI
+ to prevent from racing condition.
+ This function will reveal P2SB and hide P2SB if it's originally hidden. If more than one SBI access
+ needed, it's better to unhide the P2SB before calling and hide it back after done.
+
+ When the return value is "EFI_SUCCESS", the "Response" do not need to be checked as it would have been
+ SBI_SUCCESS. If the return value is "EFI_DEVICE_ERROR", then this would provide additional information
+ when needed.
+
+ @param[in] P2sbBase P2SB PCI config base
+ @param[in] Pid Port ID of the SBI message
+ @param[in] Offset Offset of the SBI message
+ @param[in] Opcode Opcode
+ @param[in] Posted Posted message
+ @param[in] Fbe First byte enable
+ @param[in] Bar Bar
+ @param[in] Fid Function ID
+ @param[in, out] Data32 Read/Write data
+ @param[out] Response Response
+
+ @retval EFI_SUCCESS Successfully completed.
+ @retval EFI_DEVICE_ERROR Transaction fail
+ @retval EFI_INVALID_PARAMETER Invalid parameter
+ @retval EFI_TIMEOUT Timeout while waiting for response
+**/
+EFI_STATUS
+P2SbSbiExecutionEx (
+ IN UINT64 P2sbBase,
+ IN P2SB_PID Pid,
+ IN UINT64 Offset,
+ IN P2SB_SBI_OPCODE Opcode,
+ IN BOOLEAN Posted,
+ IN UINT16 Fbe,
+ IN UINT16 Bar,
+ IN UINT16 Fid,
+ IN OUT UINT32 *Data32,
+ OUT UINT8 *Response
+ );
+
+#endif
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/IncludePrivate/Library/PchSbiAccessLib.h b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/IncludePrivate/Library/PchSbiAccessLib.h
new file mode 100644
index 0000000000..a46d8fb649
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/IncludePrivate/Library/PchSbiAccessLib.h
@@ -0,0 +1,58 @@
+/** @file
+ Header file for PchSbiAccessLib.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _PCH_SBI_ACCESS_LIB_H_
+#define _PCH_SBI_ACCESS_LIB_H_
+
+#include <Library/PchPcrLib.h>
+#include <Library/P2SbSidebandAccessLib.h>
+
+typedef P2SB_SBI_OPCODE PCH_SBI_OPCODE ;
+
+typedef P2SB_SBI_RESPONSE PCH_SBI_RESPONSE;
+
+/**
+ Full function for executing PCH SBI message
+ Take care of that there is no lock protection when using SBI programming in both POST time and SMI.
+ It will clash with POST time SBI programming when SMI happen.
+ Programmer MUST do the save and restore opration while using the PchSbiExecution inside SMI
+ to prevent from racing condition.
+ This function will reveal P2SB and hide P2SB if it's originally hidden. If more than one SBI access
+ needed, it's better to unhide the P2SB before calling and hide it back after done.
+
+ When the return value is "EFI_SUCCESS", the "Response" do not need to be checked as it would have been
+ SBI_SUCCESS. If the return value is "EFI_DEVICE_ERROR", then this would provide additional information
+ when needed.
+
+ @param[in] Pid Port ID of the SBI message
+ @param[in] Offset Offset of the SBI message
+ @param[in] Opcode Opcode
+ @param[in] Posted Posted message
+ @param[in] Fbe First byte enable
+ @param[in] Bar Bar
+ @param[in] Fid Function ID
+ @param[in, out] Data32 Read/Write data
+ @param[out] Response Response
+
+ @retval EFI_SUCCESS Successfully completed.
+ @retval EFI_DEVICE_ERROR Transaction fail
+ @retval EFI_INVALID_PARAMETER Invalid parameter
+ @retval EFI_TIMEOUT Timeout while waiting for response
+**/
+EFI_STATUS
+PchSbiExecutionEx (
+ IN PCH_SBI_PID Pid,
+ IN UINT64 Offset,
+ IN PCH_SBI_OPCODE Opcode,
+ IN BOOLEAN Posted,
+ IN UINT16 Fbe,
+ IN UINT16 Bar,
+ IN UINT16 Fid,
+ IN OUT UINT32 *Data32,
+ OUT UINT8 *Response
+ );
+
+#endif // _PCH_SBI_ACCESS_LIB_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/IncludePrivate/P2SbController.h b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/IncludePrivate/P2SbController.h
new file mode 100644
index 0000000000..51c67d4624
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/IncludePrivate/P2SbController.h
@@ -0,0 +1,32 @@
+/** @file
+ P2SB controller
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _P2SB_CONTROLLER_H_
+#define _P2SB_CONTROLLER_H_
+
+/**
+ P2SB structure
+ Stores information required to access to registers
+ like base address, S:B:D:F etc.
+ and definitions specific to P2SB.
+**/
+typedef struct {
+ /**
+ P2SB controller PCI config space address
+ in PCI Segment Library representation.
+ **/
+ UINT64 PciCfgBaseAddr;
+ /**
+ P2SB controller MMIO base address
+ **/
+ UINT64 Mmio;
+ /**
+ HPET MMIO base address
+ **/
+ UINT64 HpetMmio;
+} P2SB_CONTROLLER;
+
+#endif // _P2SB_CONTROLLER_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/IncludePrivate/Register/P2sbRegs.h b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/IncludePrivate/Register/P2sbRegs.h
new file mode 100644
index 0000000000..ffe35411f7
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/IncludePrivate/Register/P2sbRegs.h
@@ -0,0 +1,53 @@
+/** @file
+ Register names for PCH P2SB device
+
+ Conventions:
+
+ - Register definition format:
+ Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_RegisterName
+ - Prefix:
+ Definitions beginning with "R_" are registers
+ Definitions beginning with "B_" are bits within registers
+ Definitions beginning with "V_" are meaningful values within the bits
+ Definitions beginning with "S_" are register size
+ Definitions beginning with "N_" are the bit position
+ - [GenerationName]:
+ Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc.).
+ Register name without GenerationName applies to all generations.
+ - [ComponentName]:
+ This field indicates the component name that the register belongs to (e.g. PCH, SA etc.)
+ Register name without ComponentName applies to all components.
+ Register that is specific to -H denoted by "_PCH_H_" in component name.
+ Register that is specific to -LP denoted by "_PCH_LP_" in component name.
+ - SubsystemName:
+ This field indicates the subsystem name of the component that the register belongs to
+ (e.g. PCIE, USB, SATA, GPIO, PMC etc.).
+ - RegisterSpace:
+ MEM - MMIO space register of subsystem.
+ IO - IO space register of subsystem.
+ PCR - Private configuration register of subsystem.
+ CFG - PCI configuration space register of subsystem.
+ - RegisterName:
+ Full register name.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _P2SB_REGS_H_
+#define _P2SB_REGS_H_
+
+//
+// Definition for SBI
+//
+#define R_P2SB_CFG_SBIADDR 0xD0
+#define R_P2SB_CFG_SBIDATA 0xD4
+#define R_P2SB_CFG_SBISTAT 0xD8
+#define B_P2SB_CFG_SBISTAT_OPCODE 0xFF00
+#define B_P2SB_CFG_SBISTAT_POSTED BIT7
+#define B_P2SB_CFG_SBISTAT_RESPONSE 0x0006
+#define N_P2SB_CFG_SBISTAT_RESPONSE 1
+#define B_P2SB_CFG_SBISTAT_INITRDY BIT0
+#define R_P2SB_CFG_SBIRID 0xDA
+#define R_P2SB_CFG_SBIEXTADDR 0xDC
+
+#endif
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/Library/PeiDxeSmmPchPcrLib/PchPcrLib.c b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/Library/PeiDxeSmmPchPcrLib/PchPcrLib.c
new file mode 100644
index 0000000000..a5b18613bc
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/Library/PeiDxeSmmPchPcrLib/PchPcrLib.c
@@ -0,0 +1,266 @@
+/** @file
+ PCH PCR library.
+ All function in this library is available for PEI, DXE, and SMM,
+ But do not support UEFI RUNTIME environment call.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <Base.h>
+#include <Uefi/UefiBaseType.h>
+#include <Library/IoLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseLib.h>
+#include <Library/PchInfoLib.h>
+#include <Library/PchPcrLib.h>
+#include <Library/PchSbiAccessLib.h>
+#include <Library/PciSegmentLib.h>
+#include <Register/PchPcrRegs.h>
+
+#ifndef MDEPKG_NDEBUG
+/**
+ Checks if the offset is valid for a given memory access width. Offset must align to width size.
+
+ @param[in] Offset Offset of a register
+ @param[in] Size Size of memory access in bytes
+
+ @retval FALSE Offset is not valid for a given memory access
+ @retval TRUE Offset is valid
+**/
+STATIC
+BOOLEAN
+PchIsPcrOffsetValid (
+ IN UINT32 Offset,
+ IN UINTN Size
+ )
+{
+ if (!IsP2sb20bPcrSupported ()) {
+ if (((Offset & (Size - 1)) != 0) || (Offset > 0xFFFF)) {
+ DEBUG ((DEBUG_ERROR, "PCR offset error. Invalid Offset: %x Size: %x", Offset, Size));
+ return FALSE;
+ } else {
+ return TRUE;
+ }
+ } else {
+ if (((Offset & (Size - 1)) != 0) || (Offset > 0xFFFFF)) {
+ DEBUG ((DEBUG_ERROR, "PCR offset error. Invalid Offset: %x Size: %x", Offset, Size));
+ return FALSE;
+ } else {
+ return TRUE;
+ }
+ }
+}
+#endif
+
+/**
+ Read PCR register.
+ It returns PCR register and size in 4bytes.
+ The Offset should not exceed 0xFFFF and must be aligned with size.
+
+ @param[in] Pid Port ID
+ @param[in] Offset Register offset of this Port ID
+
+ @retval UINT32 PCR register value.
+**/
+UINT32
+PchPcrRead32 (
+ IN PCH_SBI_PID Pid,
+ IN UINT32 Offset
+ )
+{
+#ifndef MDEPKG_NDEBUG
+ ASSERT (PchIsPcrOffsetValid (Offset, 4));
+#endif
+ return MmioRead32 (PCH_PCR_ADDRESS (Pid, Offset));
+}
+
+/**
+ Read PCR register.
+ It returns PCR register and size in 2bytes.
+ The Offset should not exceed 0xFFFF and must be aligned with size.
+
+ @param[in] Pid Port ID
+ @param[in] Offset Register offset of this Port ID
+
+ @retval UINT16 PCR register value.
+**/
+UINT16
+PchPcrRead16 (
+ IN PCH_SBI_PID Pid,
+ IN UINT32 Offset
+ )
+{
+#ifndef MDEPKG_NDEBUG
+ ASSERT (PchIsPcrOffsetValid (Offset, 2));
+#endif
+ return MmioRead16 (PCH_PCR_ADDRESS (Pid, Offset));
+}
+
+/**
+ Read PCR register.
+ It returns PCR register and size in 1bytes.
+ The Offset should not exceed 0xFFFF and must be aligned with size.
+
+ @param[in] Pid Port ID
+ @param[in] Offset Register offset of this Port ID
+
+ @retval UINT8 PCR register value
+**/
+UINT8
+PchPcrRead8 (
+ IN PCH_SBI_PID Pid,
+ IN UINT32 Offset
+ )
+{
+ return MmioRead8 (PCH_PCR_ADDRESS (Pid, Offset));
+}
+
+/**
+ Write PCR register.
+ It programs PCR register and size in 4bytes.
+ The Offset should not exceed 0xFFFF and must be aligned with size.
+
+ @param[in] Pid Port ID
+ @param[in] Offset Register offset of Port ID.
+ @param[in] Data Input Data. Must be the same size as Size parameter.
+
+ @retval UINT32 Value written to register
+**/
+UINT32
+PchPcrWrite32 (
+ IN PCH_SBI_PID Pid,
+ IN UINT32 Offset,
+ IN UINT32 Data
+ )
+{
+#ifndef MDEPKG_NDEBUG
+ ASSERT (PchIsPcrOffsetValid (Offset, 4));
+#endif
+ MmioWrite32 (PCH_PCR_ADDRESS (Pid, Offset), Data);
+
+ return Data;
+
+}
+
+/**
+ Write PCR register.
+ It programs PCR register and size in 2bytes.
+ The Offset should not exceed 0xFFFF and must be aligned with size.
+
+ @param[in] Pid Port ID
+ @param[in] Offset Register offset of Port ID.
+ @param[in] Data Input Data. Must be the same size as Size parameter.
+
+ @retval UINT16 Value written to register
+**/
+UINT16
+PchPcrWrite16 (
+ IN PCH_SBI_PID Pid,
+ IN UINT32 Offset,
+ IN UINT16 Data
+ )
+{
+#ifndef MDEPKG_NDEBUG
+ ASSERT (PchIsPcrOffsetValid (Offset, 2));
+#endif
+ MmioWrite16 (PCH_PCR_ADDRESS (Pid, Offset), Data);
+
+ return Data;
+}
+
+/**
+ Write PCR register.
+ It programs PCR register and size in 1bytes.
+ The Offset should not exceed 0xFFFF and must be aligned with size.
+
+ @param[in] Pid Port ID
+ @param[in] Offset Register offset of Port ID.
+ @param[in] Data Input Data. Must be the same size as Size parameter.
+
+ @retval UINT8 Value written to register
+**/
+UINT8
+PchPcrWrite8 (
+ IN PCH_SBI_PID Pid,
+ IN UINT32 Offset,
+ IN UINT8 Data
+ )
+{
+
+ MmioWrite8 (PCH_PCR_ADDRESS (Pid, Offset), Data);
+
+ return Data;
+}
+
+/**
+ Write PCR register.
+ It programs PCR register and size in 4bytes.
+ The Offset should not exceed 0xFFFF and must be aligned with size.
+
+ @param[in] Pid Port ID
+ @param[in] Offset Register offset of Port ID.
+ @param[in] AndData AND Data. Must be the same size as Size parameter.
+ @param[in] OrData OR Data. Must be the same size as Size parameter.
+
+ @retval UINT32 Value written to register
+
+**/
+UINT32
+PchPcrAndThenOr32 (
+ IN PCH_SBI_PID Pid,
+ IN UINT32 Offset,
+ IN UINT32 AndData,
+ IN UINT32 OrData
+ )
+{
+ return PchPcrWrite32 (Pid, Offset, (PchPcrRead32 (Pid, Offset) & AndData) | OrData);
+}
+
+/**
+ Write PCR register.
+ It programs PCR register and size in 2bytes.
+ The Offset should not exceed 0xFFFF and must be aligned with size.
+
+ @param[in] Pid Port ID
+ @param[in] Offset Register offset of Port ID.
+ @param[in] AndData AND Data. Must be the same size as Size parameter.
+ @param[in] OrData OR Data. Must be the same size as Size parameter.
+
+ @retval UINT16 Value written to register
+
+**/
+UINT16
+PchPcrAndThenOr16 (
+ IN PCH_SBI_PID Pid,
+ IN UINT32 Offset,
+ IN UINT16 AndData,
+ IN UINT16 OrData
+ )
+{
+ return PchPcrWrite16 (Pid, Offset, (PchPcrRead16 (Pid, Offset) & AndData) | OrData);
+}
+
+/**
+ Write PCR register.
+ It programs PCR register and size in 1bytes.
+ The Offset should not exceed 0xFFFF and must be aligned with size.
+
+ @param[in] Pid Port ID
+ @param[in] Offset Register offset of Port ID.
+ @param[in] AndData AND Data. Must be the same size as Size parameter.
+ @param[in] OrData OR Data. Must be the same size as Size parameter.
+
+ @retval UINT8 Value written to register
+
+**/
+UINT8
+PchPcrAndThenOr8 (
+ IN PCH_SBI_PID Pid,
+ IN UINT32 Offset,
+ IN UINT8 AndData,
+ IN UINT8 OrData
+ )
+{
+ return PchPcrWrite8 (Pid, Offset, (PchPcrRead8 (Pid, Offset) & AndData) | OrData);
+}
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/Library/PeiDxeSmmPchPcrLib/PeiDxeSmmPchPcrLib.inf b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/Library/PeiDxeSmmPchPcrLib/PeiDxeSmmPchPcrLib.inf
new file mode 100644
index 0000000000..5e1b4914d8
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/Library/PeiDxeSmmPchPcrLib/PeiDxeSmmPchPcrLib.inf
@@ -0,0 +1,35 @@
+## @file
+# PCH PCR Library.
+#
+# All function in this library is available for PEI, DXE, and SMM,
+# But do not support UEFI RUNTIME environment call.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+
+[Defines]
+INF_VERSION = 0x00010017
+BASE_NAME = PeiDxeSmmPchPcrLib
+FILE_GUID = 117C8D19-445B-46BF-B624-109F63709375
+VERSION_STRING = 1.0
+MODULE_TYPE = BASE
+LIBRARY_CLASS = PchPcrLib
+
+
+[LibraryClasses]
+BaseLib
+IoLib
+DebugLib
+PchInfoLib
+PchSbiAccessLib
+PciSegmentLib
+
+[Packages]
+MdePkg/MdePkg.dec
+AlderlakeSiliconPkg/SiPkg.dec
+
+
+[Sources]
+PchPcrLib.c
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/LibraryPrivate/PeiDxeSmmP2SbSidebandAccessLib/PeiDxeSmmP2SbSidebandAccessLib.c b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/LibraryPrivate/PeiDxeSmmP2SbSidebandAccessLib/PeiDxeSmmP2SbSidebandAccessLib.c
new file mode 100644
index 0000000000..52ec8fd9e1
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/LibraryPrivate/PeiDxeSmmP2SbSidebandAccessLib/PeiDxeSmmP2SbSidebandAccessLib.c
@@ -0,0 +1,208 @@
+/** @file
+ P2SB sideband access lib
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <Base.h>
+#include <Uefi/UefiBaseType.h>
+#include <Library/IoLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseLib.h>
+#include <Library/PchInfoLib.h>
+#include <Library/P2SbSidebandAccessLib.h>
+#include <Library/PciSegmentLib.h>
+#include <Library/PchSbiAccessLib.h>
+#include <Register/P2sbRegs.h>
+#include <IndustryStandard/Pci30.h>
+
+#define P2SB_PCR_ADDRESS(MmioBase, Pid, Offset) ((UINTN) MmioBase | (UINT32) (((Offset) & 0x0F0000) << 8) | ((UINT8)(Pid) << 16) | (UINT16) ((Offset) & 0xFFFF))
+
+/**
+ Full function for executing P2SB SBI message
+ Take care of that there is no lock protection when using SBI programming in both POST time and SMI.
+ It will clash with POST time SBI programming when SMI happen.
+ Programmer MUST do the save and restore opration while using the PchSbiExecution inside SMI
+ to prevent from racing condition.
+ This function will reveal P2SB and hide P2SB if it's originally hidden. If more than one SBI access
+ needed, it's better to unhide the P2SB before calling and hide it back after done.
+
+ When the return value is "EFI_SUCCESS", the "Response" do not need to be checked as it would have been
+ SBI_SUCCESS. If the return value is "EFI_DEVICE_ERROR", then this would provide additional information
+ when needed.
+
+ @param[in] P2sbBase P2SB PCI config base
+ @param[in] Pid Port ID of the SBI message
+ @param[in] Offset Offset of the SBI message
+ @param[in] Opcode Opcode
+ @param[in] Posted Posted message
+ @param[in] Fbe First byte enable
+ @param[in] Bar Bar
+ @param[in] Fid Function ID
+ @param[in, out] Data32 Read/Write data
+ @param[out] Response Response
+
+ @retval EFI_SUCCESS Successfully completed.
+ @retval EFI_DEVICE_ERROR Transaction fail
+ @retval EFI_INVALID_PARAMETER Invalid parameter
+ @retval EFI_TIMEOUT Timeout while waiting for response
+**/
+EFI_STATUS
+P2SbSbiExecutionEx (
+ IN UINT64 P2sbBase,
+ IN P2SB_PID Pid,
+ IN UINT64 Offset,
+ IN P2SB_SBI_OPCODE Opcode,
+ IN BOOLEAN Posted,
+ IN UINT16 Fbe,
+ IN UINT16 Bar,
+ IN UINT16 Fid,
+ IN OUT UINT32 *Data32,
+ OUT UINT8 *Response
+ )
+{
+ INT32 Timeout;
+ UINT16 SbiStat;
+
+ //
+ // Check opcode valid
+ //
+ switch (Opcode) {
+ case MemoryRead:
+ case MemoryWrite:
+ case PciConfigRead:
+ case PciConfigWrite:
+ case PrivateControlRead:
+ case PrivateControlWrite:
+ case GpioLockUnlock:
+ break;
+ default:
+ return EFI_INVALID_PARAMETER;
+ break;
+ }
+
+ if (PciSegmentRead16 (P2sbBase + PCI_VENDOR_ID_OFFSET) == 0xFFFF) {
+ ASSERT (FALSE);
+ return EFI_DEVICE_ERROR;
+ }
+ ///
+ /// BWG Section 2.2.1
+ /// 1. Poll P2SB PCI offset D8h[0] = 0b
+ /// Make sure the previous opeartion is completed.
+ ///
+ Timeout = 0xFFFFFFF;
+ while (Timeout > 0) {
+ SbiStat = PciSegmentRead16 (P2sbBase + R_P2SB_CFG_SBISTAT);
+ if ((SbiStat & B_P2SB_CFG_SBISTAT_INITRDY) == 0) {
+ break;
+ }
+ Timeout--;
+ }
+ if (Timeout == 0) {
+ return EFI_TIMEOUT;
+ }
+ //
+ // Initial Response status
+ //
+ *Response = SBI_INVALID_RESPONSE;
+ SbiStat = 0;
+ ///
+ /// 2. Write P2SB PCI offset D0h[31:0] with Address and Destination Port ID
+ ///
+ PciSegmentWrite32 (P2sbBase + R_P2SB_CFG_SBIADDR, (UINT32) ((Pid << 24) | (UINT16) Offset));
+ ///
+ /// 3. Write P2SB PCI offset DCh[31:0] with extended address, which is expected to be 0 in CNL PCH.
+ ///
+ PciSegmentWrite32 (P2sbBase + R_P2SB_CFG_SBIEXTADDR, (UINT32) RShiftU64 (Offset, 16));
+ ///
+ /// 5. Set P2SB PCI offset D8h[15:8] = 00000110b for read
+ /// Set P2SB PCI offset D8h[15:8] = 00000111b for write
+ //
+ // Set SBISTAT[15:8] to the opcode passed in
+ // Set SBISTAT[7] to the posted passed in
+ //
+ PciSegmentAndThenOr16 (
+ (P2sbBase + R_P2SB_CFG_SBISTAT),
+ (UINT16) ~(B_P2SB_CFG_SBISTAT_OPCODE | B_P2SB_CFG_SBISTAT_POSTED),
+ (UINT16) ((Opcode << 8) | (Posted << 7))
+ );
+ ///
+ /// 6. Write P2SB PCI offset DAh[15:0] = F000h
+ ///
+ //
+ // Set RID[15:0] = Fbe << 12 | Bar << 8 | Fid
+ //
+ PciSegmentWrite16 (
+ (P2sbBase + R_P2SB_CFG_SBIRID),
+ (((Fbe & 0x000F) << 12) | ((Bar & 0x0007) << 8) | (Fid & 0x00FF))
+ );
+
+ switch (Opcode) {
+ case MemoryWrite:
+ case PciConfigWrite:
+ case PrivateControlWrite:
+ case GpioLockUnlock:
+ ///
+ /// 4. Write P2SB PCI offset D4h[31:0] with the intended data accordingly
+ ///
+ PciSegmentWrite32 ((P2sbBase + R_P2SB_CFG_SBIDATA), *Data32);
+ break;
+ default:
+ ///
+ /// 4. Write P2SB PCI offset D4h[31:0] with dummy data such as 0,
+ /// because all D0-DFh register range must be touched in CNL PCH
+ /// for a successful SBI transaction.
+ ///
+ PciSegmentWrite32 ((P2sbBase + R_P2SB_CFG_SBIDATA), 0);
+ break;
+ }
+ ///
+ /// 7. Set P2SB PCI offset D8h[0] = 1b, Poll P2SB PCI offset D8h[0] = 0b
+ ///
+ //
+ // Set SBISTAT[0] = 1b, trigger the SBI operation
+ //
+ PciSegmentOr16 (P2sbBase + R_P2SB_CFG_SBISTAT, (UINT16) B_P2SB_CFG_SBISTAT_INITRDY);
+ //
+ // Poll SBISTAT[0] = 0b, Polling for Busy bit
+ //
+ Timeout = 0xFFFFFFF;
+ while (Timeout > 0) {
+ SbiStat = PciSegmentRead16 (P2sbBase + R_P2SB_CFG_SBISTAT);
+ if ((SbiStat & B_P2SB_CFG_SBISTAT_INITRDY) == 0) {
+ break;
+ }
+ Timeout--;
+ }
+ if (Timeout == 0) {
+ //
+ // If timeout, it's fatal error.
+ //
+ return EFI_TIMEOUT;
+ } else {
+ ///
+ /// 8. Check if P2SB PCI offset D8h[2:1] = 00b for successful transaction
+ ///
+ *Response = (UINT8) ((SbiStat & B_P2SB_CFG_SBISTAT_RESPONSE) >> N_P2SB_CFG_SBISTAT_RESPONSE);
+ if (*Response == SBI_SUCCESSFUL) {
+ switch (Opcode) {
+ case MemoryRead:
+ case PciConfigRead:
+ case PrivateControlRead:
+ ///
+ /// 9. Read P2SB PCI offset D4h[31:0] for SBI data
+ ///
+ *Data32 = PciSegmentRead32 (P2sbBase + R_P2SB_CFG_SBIDATA);
+ break;
+ default:
+ break;
+ }
+ return EFI_SUCCESS;
+ } else if (*Response == SBI_POWERDOWN) {
+ return EFI_NO_RESPONSE;
+ } else {
+ return EFI_DEVICE_ERROR;
+ }
+ }
+}
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/LibraryPrivate/PeiDxeSmmP2SbSidebandAccessLib/PeiDxeSmmP2SbSidebandAccessLib.inf b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/LibraryPrivate/PeiDxeSmmP2SbSidebandAccessLib/PeiDxeSmmP2SbSidebandAccessLib.inf
new file mode 100644
index 0000000000..9530e56940
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/LibraryPrivate/PeiDxeSmmP2SbSidebandAccessLib/PeiDxeSmmP2SbSidebandAccessLib.inf
@@ -0,0 +1,30 @@
+## @file
+# Library for accessing sideband register banks via the P2SB router.
+#
+# All function in this library is available for PEI, DXE, and SMM,
+# But do not support UEFI RUNTIME environment call.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+
+[Defines]
+INF_VERSION = 0x00010017
+BASE_NAME = PeiDxeSmmP2SbSidebandAccessLib
+FILE_GUID = 425C479D-A489-4382-8C28-59A3521A24FF
+VERSION_STRING = 1.0
+MODULE_TYPE = BASE
+LIBRARY_CLASS = P2SbSidebandAccessLib
+
+[LibraryClasses]
+BaseLib
+IoLib
+DebugLib
+
+[Packages]
+MdePkg/MdePkg.dec
+AlderlakeSiliconPkg/SiPkg.dec
+
+[Sources]
+PeiDxeSmmP2SbSidebandAccessLib.c
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/LibraryPrivate/PeiDxeSmmPchSbiAccessLib/PchSbiAccessLib.c b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/LibraryPrivate/PeiDxeSmmPchSbiAccessLib/PchSbiAccessLib.c
new file mode 100644
index 0000000000..1f7bb82692
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/LibraryPrivate/PeiDxeSmmPchSbiAccessLib/PchSbiAccessLib.c
@@ -0,0 +1,72 @@
+/** @file
+ PCH SBI access library.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <Base.h>
+#include <Uefi/UefiBaseType.h>
+#include <Library/IoLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseLib.h>
+#include <Library/PchSbiAccessLib.h>
+#include <Library/P2SbSidebandAccessLib.h>
+#include <Library/PchPciBdfLib.h>
+#include <Register/PchRegs.h>
+#include <Register/P2sbRegs.h>
+
+/**
+ Full function for executing PCH SBI message
+ Take care of that there is no lock protection when using SBI programming in both POST time and SMI.
+ It will clash with POST time SBI programming when SMI happen.
+ Programmer MUST do the save and restore opration while using the PchSbiExecution inside SMI
+ to prevent from racing condition.
+ This function will reveal P2SB and hide P2SB if it's originally hidden. If more than one SBI access
+ needed, it's better to unhide the P2SB before calling and hide it back after done.
+
+ When the return value is "EFI_SUCCESS", the "Response" do not need to be checked as it would have been
+ SBI_SUCCESS. If the return value is "EFI_DEVICE_ERROR", then this would provide additional information
+ when needed.
+
+ @param[in] Pid Port ID of the SBI message
+ @param[in] Offset Offset of the SBI message
+ @param[in] Opcode Opcode
+ @param[in] Posted Posted message
+ @param[in] Fbe First byte enable
+ @param[in] Bar Bar
+ @param[in] Fid Function ID
+ @param[in, out] Data32 Read/Write data
+ @param[out] Response Response
+
+ @retval EFI_SUCCESS Successfully completed.
+ @retval EFI_DEVICE_ERROR Transaction fail
+ @retval EFI_INVALID_PARAMETER Invalid parameter
+ @retval EFI_TIMEOUT Timeout while waiting for response
+**/
+EFI_STATUS
+PchSbiExecutionEx (
+ IN PCH_SBI_PID Pid,
+ IN UINT64 Offset,
+ IN PCH_SBI_OPCODE Opcode,
+ IN BOOLEAN Posted,
+ IN UINT16 Fbe,
+ IN UINT16 Bar,
+ IN UINT16 Fid,
+ IN OUT UINT32 *Data32,
+ OUT UINT8 *Response
+ )
+{
+ return P2SbSbiExecutionEx (
+ P2sbPciCfgBase (),
+ Pid,
+ Offset,
+ Opcode,
+ Posted,
+ Fbe,
+ Bar,
+ Fid,
+ Data32,
+ Response
+ );
+}
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/LibraryPrivate/PeiDxeSmmPchSbiAccessLib/PeiDxeSmmPchSbiAccessLib.inf b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/LibraryPrivate/PeiDxeSmmPchSbiAccessLib/PeiDxeSmmPchSbiAccessLib.inf
new file mode 100644
index 0000000000..a28a90c74b
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/LibraryPrivate/PeiDxeSmmPchSbiAccessLib/PeiDxeSmmPchSbiAccessLib.inf
@@ -0,0 +1,35 @@
+## @file
+# PCH SBI access library.
+#
+# All function in this library is available for PEI, DXE, and SMM,
+# But do not support UEFI RUNTIME environment call.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+
+[Defines]
+INF_VERSION = 0x00010017
+BASE_NAME = PeiDxeSmmPchSbiAccessLib
+FILE_GUID = 96ECB0FB-A975-4DC8-B88A-D90C3378CE87
+VERSION_STRING = 1.0
+MODULE_TYPE = BASE
+LIBRARY_CLASS = PchSbiAccessLib
+
+
+[LibraryClasses]
+BaseLib
+IoLib
+DebugLib
+PchPciBdfLib
+P2SbSidebandAccessLib
+
+
+[Packages]
+MdePkg/MdePkg.dec
+AlderlakeSiliconPkg/SiPkg.dec
+
+
+[Sources]
+PchSbiAccessLib.c
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PchDmi/IncludePrivate/Library/PchDmiLib.h b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PchDmi/IncludePrivate/Library/PchDmiLib.h
new file mode 100644
index 0000000000..efbb76f6be
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PchDmi/IncludePrivate/Library/PchDmiLib.h
@@ -0,0 +1,60 @@
+/** @file
+ Header file for PchDmiLib.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _PCH_DMI_LIB_H_
+#define _PCH_DMI_LIB_H_
+
+/**
+ This function checks if DMI Secured Register Lock (SRL) is set
+
+ @retval SRL state
+**/
+BOOLEAN
+IsPchDmiLocked (
+ VOID
+ );
+
+/**
+ Get PCH TCO base address.
+
+ @retval Address Address of TCO base address.
+**/
+UINT16
+PchDmiGetTcoBase (
+ VOID
+ );
+
+/**
+ Set PCH LPC/eSPI IO decode ranges in DMI
+ Please check EDS for detail of LPC/eSPI IO decode ranges bit definition.
+ Bit 12: FDD range
+ Bit 9:8: LPT range
+ Bit 6:4: ComB range
+ Bit 2:0: ComA range
+
+ @param[in] LpcIoDecodeRanges LPC/eSPI IO decode ranges bit settings.
+
+ @retval EFI_SUCCESS Successfully completed.
+ @retval EFI_UNSUPPORTED DMIC.SRL is set.
+**/
+EFI_STATUS
+PchDmiSetLpcIoDecodeRanges (
+ IN UINT16 LpcIoDecodeRanges
+ );
+
+/**
+ Set PCH LPC/eSPI IO enable decoding in DMI
+
+ @param[in] LpcIoEnableDecoding LPC/eSPI IO enable decoding bit settings.
+
+ @retval EFI_SUCCESS Successfully completed.
+ @retval EFI_UNSUPPORTED DMIC.SRL is set.
+**/
+EFI_STATUS
+PchDmiSetLpcIoEnable (
+ IN UINT16 LpcIoEnableDecoding
+ );
+#endif // _PCH_DMI_LIB_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivate/PeiDxeSmmPchDmiLib/PchDmi14.c b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivate/PeiDxeSmmPchDmiLib/PchDmi14.c
new file mode 100644
index 0000000000..9f49790372
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivate/PeiDxeSmmPchDmiLib/PchDmi14.c
@@ -0,0 +1,34 @@
+/** @file
+ This file contains functions for PCH DMI SIP14
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <Base.h>
+#include <Uefi/UefiBaseType.h>
+#include <Library/IoLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseLib.h>
+#include <Library/PchInfoLib.h>
+#include <Library/PchPcrLib.h>
+#include <Library/PchDmiLib.h>
+#include <Library/PchCycleDecodingLib.h>
+#include <Library/PchPcrLib.h>
+#include <Library/PchInfoLib.h>
+#include <Register/PchDmiRegs.h>
+#include <Register/PchDmi14Regs.h>
+#include <Register/PchPcrRegs.h>
+
+/**
+ This function checks if DMI SIP14 Secured Register Lock (SRL) is set
+
+ @retval SRL state
+**/
+BOOLEAN
+IsPchDmi14Locked (
+ VOID
+ )
+{
+ return ((PchPcrRead32 (PID_DMI, R_PCH_DMI14_PCR_DMIC) & B_PCH_DMI14_PCR_DMIC_SRL) != 0);
+}
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivate/PeiDxeSmmPchDmiLib/PchDmi14.h b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivate/PeiDxeSmmPchDmiLib/PchDmi14.h
new file mode 100644
index 0000000000..494caebb4a
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivate/PeiDxeSmmPchDmiLib/PchDmi14.h
@@ -0,0 +1,22 @@
+/** @file
+ Internal header file for PCH DMI library for SIP14
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef __PCH_DMI_14_H__
+#define __PCH_DMI_14_H__
+
+#include <Library/PchDmiLib.h>
+
+/**
+ This function checks if DMI SIP14 Secured Register Lock (SRL) is set
+
+ @retval SRL state
+**/
+BOOLEAN
+IsPchDmi14Locked (
+ VOID
+ );
+
+#endif
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivate/PeiDxeSmmPchDmiLib/PchDmiLib.c b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivate/PeiDxeSmmPchDmiLib/PchDmiLib.c
new file mode 100644
index 0000000000..3d5436f1a3
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivate/PeiDxeSmmPchDmiLib/PchDmiLib.c
@@ -0,0 +1,110 @@
+/** @file
+ PCH DMI library.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#include <Base.h>
+#include <Uefi/UefiBaseType.h>
+#include <Library/IoLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseLib.h>
+#include <Library/PchInfoLib.h>
+#include <Library/PchPcrLib.h>
+#include <Library/PchDmiLib.h>
+#include <Library/PchCycleDecodingLib.h>
+#include <Register/PchPcrRegs.h>
+#include <Register/PchDmiRegs.h>
+#include <Register/PchRegsLpc.h>
+
+#include "PchDmi14.h"
+
+/**
+ This function checks if DMI Secured Register Lock (SRL) is set
+
+ @retval SRL state
+**/
+BOOLEAN
+IsPchDmiLocked (
+ VOID
+ )
+{
+ return IsPchDmi14Locked ();
+}
+
+/**
+ Get PCH TCO base address.
+
+ @retval Address Address of TCO base address.
+**/
+UINT16
+PchDmiGetTcoBase (
+ VOID
+ )
+{
+ //
+ // Read "TCO Base Address" PCR[DMI] + 2778h[15:5]
+ //
+ return (PchPcrRead16 (PID_DMI, R_PCH_DMI_PCR_TCOBASE) & B_PCH_DMI_PCR_TCOBASE_TCOBA);
+}
+
+/**
+ Set PCH LPC/eSPI IO decode ranges in DMI
+ Please check EDS for detail of LPC/eSPI IO decode ranges bit definition.
+ Bit 12: FDD range
+ Bit 9:8: LPT range
+ Bit 6:4: ComB range
+ Bit 2:0: ComA range
+
+ @param[in] LpcIoDecodeRanges LPC/eSPI IO decode ranges bit settings.
+
+ @retval EFI_SUCCESS Successfully completed.
+ @retval EFI_UNSUPPORTED DMIC.SRL is set.
+**/
+EFI_STATUS
+PchDmiSetLpcIoDecodeRanges (
+ IN UINT16 LpcIoDecodeRanges
+ )
+{
+ //
+ // This cycle decoding is only allowed to set when DMI is not locked.
+ //
+ if (IsPchDmiLocked ()) {
+ ASSERT (FALSE);
+ return EFI_UNSUPPORTED;
+ }
+
+ //
+ // program LPC I/O Decode Ranges, PCR[DMI] + 2770h[15:0] to the same value programmed in LPC/eSPI PCI offset 80h.
+ //
+ PchPcrWrite16 (PID_DMI, R_PCH_DMI_PCR_LPCIOD, LpcIoDecodeRanges);
+ return EFI_SUCCESS;
+}
+
+/**
+ Set PCH LPC/eSPI IO enable decoding in DMI
+
+ @param[in] LpcIoEnableDecoding LPC/eSPI IO enable decoding bit settings.
+
+ @retval EFI_SUCCESS Successfully completed.
+ @retval EFI_UNSUPPORTED DMIC.SRL is set.
+**/
+EFI_STATUS
+PchDmiSetLpcIoEnable (
+ IN UINT16 LpcIoEnableDecoding
+ )
+{
+ //
+ // This cycle decoding is only allowed to set when DMI is not locked.
+ //
+ if (IsPchDmiLocked ()) {
+ ASSERT (FALSE);
+ return EFI_UNSUPPORTED;
+ }
+
+ //
+ // program LPC I/O Decode Ranges, PCR[DMI] + 2774h[15:0] to the same value programmed in LPC/eSPI PCI offset 82h.
+ //
+ PchPcrWrite16 (PID_DMI, R_PCH_DMI_PCR_LPCIOE, LpcIoEnableDecoding);
+ return EFI_SUCCESS;
+}
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivate/PeiDxeSmmPchDmiLib/PeiDxeSmmPchDmiLib.inf b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivate/PeiDxeSmmPchDmiLib/PeiDxeSmmPchDmiLib.inf
new file mode 100644
index 0000000000..4e92117be3
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivate/PeiDxeSmmPchDmiLib/PeiDxeSmmPchDmiLib.inf
@@ -0,0 +1,43 @@
+## @file
+# Component description file for the PeiDxeSmmPchDmiLib
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+[Defines]
+INF_VERSION = 0x00010017
+BASE_NAME = PeiDxeSmmPchDmiLib
+FILE_GUID = 067DC1C4-2668-4F06-9921-307514B66B34
+VERSION_STRING = 1.0
+MODULE_TYPE = BASE
+LIBRARY_CLASS = PchDmiLib
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = IA32 X64
+#
+
+[LibraryClasses]
+ BaseLib
+ IoLib
+ DebugLib
+ PchInfoLib
+ PchPcrLib
+
+
+[Packages]
+ MdePkg/MdePkg.dec
+ AlderlakeSiliconPkg/SiPkg.dec
+
+
+[Sources]
+ PchDmiLib.c
+ PchDmi14.c
+ PchDmi14.h
+
+[Guids]
+ gPchDmiConfigGuid ## CONSUMES
+ gPchDmiPreMemConfigGuid ## CONSUMES
+
+[Pcd]
--
2.36.1.windows.1
-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#108679): https://edk2.groups.io/g/devel/message/108679
Mute This Topic: https://groups.io/mt/101373946/7686176
Group Owner: devel+owner@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [rebecca@openfw.io]
-=-=-=-=-=-=-=-=-=-=-=-
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [edk2-devel] [PATCH v2 04/10] AlderlakeSiliconPkg/IpBlock: Add Pmc, Spi components
2023-09-15 4:45 [edk2-devel] [PATCH v2 01/10] AlderlakeSiliconPkg/IpBlock: Add CpuPcieRp, Espi, Gpio components Saloni Kasbekar
2023-09-15 4:45 ` [edk2-devel] [PATCH v2 02/10] AlderlakeSiliconPkg/IpBlock: Add Graphics, HostBridge, PcieRp components Saloni Kasbekar
2023-09-15 4:45 ` [edk2-devel] [PATCH v2 03/10] AlderlakeSiliconPkg/IpBlock: Add P2sb, PchDmi components Saloni Kasbekar
@ 2023-09-15 4:45 ` Saloni Kasbekar
2023-09-15 5:42 ` Chaganty, Rangasai V
2023-09-15 23:56 ` Nate DeSimone
2023-09-15 4:45 ` [edk2-devel] [PATCH v2 05/10] AlderlakeSiliconPkg/Include: Add ConfigBlock headers Saloni Kasbekar
` (8 subsequent siblings)
11 siblings, 2 replies; 41+ messages in thread
From: Saloni Kasbekar @ 2023-09-15 4:45 UTC (permalink / raw)
To: devel; +Cc: Saloni Kasbekar, Sai Chaganty, Nate DeSimone, Rosen Chuang
Adds the following modules:
- IpBlock/Pmc/IncludePrivate
- IpBlock/Pmc/Library
- IpBlock/Pmc/LibraryPrivate
- IpBlock/Spi/IncludePrivate
- IpBlock/Spi/Library
- IpBlock/Spi/LibraryPrivate
- IpBlock/Spi/Smm
Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Rosen Chuang <rosen.chuang@intel.com>
Signed-off-by: Saloni Kasbekar <saloni.kasbekar@intel.com>
---
.../IncludePrivate/Library/PmcPrivateLib.h | 47 +
.../IpBlock/Pmc/IncludePrivate/PmcSocConfig.h | 67 +
.../PeiDxeSmmPmcLib/PeiDxeSmmPmcLib.inf | 38 +
.../Pmc/Library/PeiDxeSmmPmcLib/PmcLib.c | 50 +
.../PeiDxeSmmPmcPrivateLib.inf | 43 +
.../PeiDxeSmmPmcPrivateLib/PmcPrivateLib.c | 86 ++
.../Spi/IncludePrivate/Library/SpiCommonLib.h | 376 ++++++
.../Spi/IncludePrivate/Register/SpiRegs.h | 116 ++
.../IpBlock/Spi/Library/PeiSpiLib/PchSpi.c | 209 +++
.../Spi/Library/PeiSpiLib/PeiSpiLib.inf | 41 +
.../BaseSpiCommonLib/BaseSpiCommonLib.inf | 29 +
.../BaseSpiCommonLib/SpiCommon.c | 1127 +++++++++++++++++
.../AlderlakeSiliconPkg/IpBlock/Spi/Smm/Spi.c | 387 ++++++
.../IpBlock/Spi/Smm/SpiSmm.inf | 46 +
14 files changed, 2662 insertions(+)
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Pmc/IncludePrivate/Library/PmcPrivateLib.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Pmc/IncludePrivate/PmcSocConfig.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Pmc/Library/PeiDxeSmmPmcLib/PeiDxeSmmPmcLib.inf
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Pmc/Library/PeiDxeSmmPmcLib/PmcLib.c
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Pmc/LibraryPrivate/PeiDxeSmmPmcPrivateLib/PeiDxeSmmPmcPrivateLib.inf
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Pmc/LibraryPrivate/PeiDxeSmmPmcPrivateLib/PmcPrivateLib.c
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/IncludePrivate/Library/SpiCommonLib.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/IncludePrivate/Register/SpiRegs.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/Library/PeiSpiLib/PchSpi.c
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/Library/PeiSpiLib/PeiSpiLib.inf
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/LibraryPrivate/BaseSpiCommonLib/BaseSpiCommonLib.inf
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/LibraryPrivate/BaseSpiCommonLib/SpiCommon.c
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/Smm/Spi.c
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/Smm/SpiSmm.inf
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Pmc/IncludePrivate/Library/PmcPrivateLib.h b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Pmc/IncludePrivate/Library/PmcPrivateLib.h
new file mode 100644
index 0000000000..6ec244b127
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Pmc/IncludePrivate/Library/PmcPrivateLib.h
@@ -0,0 +1,47 @@
+/** @file
+ Header file for private PmcLib.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _PMC_PRIVATE_LIB_H_
+#define _PMC_PRIVATE_LIB_H_
+
+#include <Library/PmcLib.h>
+#include "Register/PmcRegs.h"
+
+typedef enum {
+ PmcSwSmiRate1p5ms = 0,
+ PmcSwSmiRate16ms,
+ PmcSwSmiRate32ms,
+ PmcSwSmiRate64ms
+} PMC_SWSMI_RATE;
+
+/**
+ This function sets SW SMI Rate.
+
+ @param[in] SwSmiRate Refer to PMC_SWSMI_RATE for possible values
+**/
+VOID
+PmcSetSwSmiRate (
+ IN PMC_SWSMI_RATE SwSmiRate
+ );
+
+typedef enum {
+ PmcPeriodicSmiRate8s = 0,
+ PmcPeriodicSmiRate16s,
+ PmcPeriodicSmiRate32s,
+ PmcPeriodicSmiRate64s
+} PMC_PERIODIC_SMI_RATE;
+
+/**
+ This function sets Periodic SMI Rate.
+
+ @param[in] PeriodicSmiRate Refer to PMC_PERIODIC_SMI_RATE for possible values
+**/
+VOID
+PmcSetPeriodicSmiRate (
+ IN PMC_PERIODIC_SMI_RATE PeriodicSmiRate
+ );
+
+#endif // _PMC_PRIVATE_LIB_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Pmc/IncludePrivate/PmcSocConfig.h b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Pmc/IncludePrivate/PmcSocConfig.h
new file mode 100644
index 0000000000..523a84a180
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Pmc/IncludePrivate/PmcSocConfig.h
@@ -0,0 +1,67 @@
+/** @file
+ PMC SoC configuration
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PMC_SOC_CONFIGURATION_H_
+#define _PMC_SOC_CONFIGURATION_H_
+
+typedef enum {
+ AdrSinglePhase = 0,
+ AdrDualPhase
+} ADR_PHASE_TYPE;
+
+typedef enum {
+ AdrGpioB = 0,
+ AdrGpioC
+} ADR_GPIO;
+
+typedef enum {
+ AdrOverPmSync = 0,
+ AdrOverDmi
+} ADR_MSG_INTERFACE;
+
+typedef struct {
+ BOOLEAN Supported;
+ ADR_PHASE_TYPE AdrPhaseType;
+ ADR_GPIO AdrGpio;
+ ADR_MSG_INTERFACE AdrMsgInterface;
+ //
+ // On some designs ADR_GEN_CFG has been moved in the HW.
+ // Set this to if ADR_GEN_CFG is located at 0x1908
+ //
+ BOOLEAN AdrGenCfgMoved;
+} PMC_ADR_SOC_CONFIG;
+
+typedef struct {
+ BOOLEAN CppmCgInterfaceVersion;
+ BOOLEAN LpmSupported;
+ UINT8 LpmInterfaceVersion;
+ BOOLEAN OsIdleSupported;
+ BOOLEAN TimedGpioSupported;
+ UINT32 CpuIovrRampTime;
+ BOOLEAN PsOnSupported;
+ BOOLEAN ModPhySusPgSupported;
+ UINT8 SciIrq;
+ BOOLEAN FabricPowerGatingCppmQualificationEnable;
+ BOOLEAN EspiBoot;
+ BOOLEAN UsbDbcConnected;
+ UINT32 Usb3LanesConnectedBitmask;
+ BOOLEAN DisableIosfSbClockGating;
+ BOOLEAN SkipModPhyGatingPolicy;
+ PMC_ADR_SOC_CONFIG AdrSocConfig;
+ BOOLEAN AllSbrIdleQualifierEnable;
+ UINT32 LpmPriVal; ///< Low Power Mode Priority
+
+} PMC_SOC_CONFIG;
+
+typedef struct {
+ BOOLEAN OverrideFetRampTime;
+ UINT8 FetRampTime;
+ UINT8 IsFetRampTime;
+ UINT16 FuseDownloadDelayUs;
+} PMC_FIVR_SOC_CONFIG;
+
+#endif
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Pmc/Library/PeiDxeSmmPmcLib/PeiDxeSmmPmcLib.inf b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Pmc/Library/PeiDxeSmmPmcLib/PeiDxeSmmPmcLib.inf
new file mode 100644
index 0000000000..e9784ceb9c
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Pmc/Library/PeiDxeSmmPmcLib/PeiDxeSmmPmcLib.inf
@@ -0,0 +1,38 @@
+## @file
+# PEI/DXE/SMM PCH PMC Lib.
+#
+# All function in this library is available for PEI, DXE, and SMM,
+# But do not support UEFI RUNTIME environment call.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+[Defines]
+ INF_VERSION = 0x00010017
+ BASE_NAME = PeiDxeSmmPmcLib
+ FILE_GUID = 9D60C364-5086-41E3-BC9D-C62AB7233DBF
+ VERSION_STRING = 1.0
+ MODULE_TYPE = BASE
+ LIBRARY_CLASS = PmcLib
+
+[LibraryClasses]
+ BaseLib
+ IoLib
+ DebugLib
+ PciSegmentLib
+ PchCycleDecodingLib
+ PchPcrLib
+ PchInfoLib
+ PmcPrivateLib
+ BaseMemoryLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ AlderlakeSiliconPkg/SiPkg.dec
+
+[Pcd]
+ gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress
+
+[Sources]
+ PmcLib.c
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Pmc/Library/PeiDxeSmmPmcLib/PmcLib.c b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Pmc/Library/PeiDxeSmmPmcLib/PmcLib.c
new file mode 100644
index 0000000000..91e741a294
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Pmc/Library/PeiDxeSmmPmcLib/PmcLib.c
@@ -0,0 +1,50 @@
+/** @file
+ PCH PMC Library.
+ All function in this library is available for PEI, DXE, and SMM,
+ But do not support UEFI RUNTIME environment call.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <Base.h>
+#include <Uefi/UefiBaseType.h>
+#include <Library/IoLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/PciSegmentLib.h>
+#include <Library/PchCycleDecodingLib.h>
+#include <Library/PmcLib.h>
+#include <Library/PchPcrLib.h>
+#include <Library/PchInfoLib.h>
+#include <Library/PmcPrivateLib.h>
+#include <PchReservedResources.h>
+#include <Register/PmcRegs.h>
+#include <Register/PchRegs.h>
+
+/**
+ Get PCH ACPI base address.
+
+ @retval Address Address of PWRM base address.
+**/
+UINT16
+PmcGetAcpiBase (
+ VOID
+ )
+{
+ return PcdGet16 (PcdAcpiBaseAddress);
+}
+
+/**
+ Get PCH PWRM base address.
+
+ @retval Address Address of PWRM base address.
+**/
+UINT32
+PmcGetPwrmBase (
+ VOID
+ )
+{
+ return PCH_PWRM_BASE_ADDRESS;
+}
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Pmc/LibraryPrivate/PeiDxeSmmPmcPrivateLib/PeiDxeSmmPmcPrivateLib.inf b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Pmc/LibraryPrivate/PeiDxeSmmPmcPrivateLib/PeiDxeSmmPmcPrivateLib.inf
new file mode 100644
index 0000000000..e6693f767d
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Pmc/LibraryPrivate/PeiDxeSmmPmcPrivateLib/PeiDxeSmmPmcPrivateLib.inf
@@ -0,0 +1,43 @@
+## @file
+# PEI/DXE/SMM PCH PMC Private Lib.
+#
+# All function in this library is available for PEI, DXE, and SMM,
+# But do not support UEFI RUNTIME environment call.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+
+[Defines]
+INF_VERSION = 0x00010017
+BASE_NAME = PeiDxeSmmPmcPrivateLib
+FILE_GUID = EB69B12B-6D4C-4B12-BB31-66CBCC4C1DC7
+VERSION_STRING = 1.0
+MODULE_TYPE = BASE
+LIBRARY_CLASS = PmcPrivateLib
+
+
+[LibraryClasses]
+BaseLib
+IoLib
+DebugLib
+TimerLib
+PciSegmentLib
+PmcLib
+BaseMemoryLib
+PchPciBdfLib
+
+[Packages]
+MdePkg/MdePkg.dec
+AlderlakeSiliconPkg/SiPkg.dec
+
+
+[Pcd]
+gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress
+
+[FixedPcd]
+
+[Sources]
+PmcPrivateLib.c
+
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Pmc/LibraryPrivate/PeiDxeSmmPmcPrivateLib/PmcPrivateLib.c b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Pmc/LibraryPrivate/PeiDxeSmmPmcPrivateLib/PmcPrivateLib.c
new file mode 100644
index 0000000000..b720305d15
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Pmc/LibraryPrivate/PeiDxeSmmPmcPrivateLib/PmcPrivateLib.c
@@ -0,0 +1,86 @@
+/** @file
+ PCH private PMC Library for all PCH generations.
+ All function in this library is available for PEI, DXE, and SMM,
+ But do not support UEFI RUNTIME environment call.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <Base.h>
+#include <Uefi/UefiBaseType.h>
+#include <Library/IoLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/PmcLib.h>
+#include <Library/PciSegmentLib.h>
+#include <Library/TimerLib.h>
+#include <Library/PmcPrivateLib.h>
+#include <PchReservedResources.h>
+#include <Register/PchRegs.h>
+#include <Register/PmcRegs.h>
+#include <IndustryStandard/Pci30.h>
+#include <Library/PchPciBdfLib.h>
+
+
+/**
+ This function sets SW SMI Rate.
+
+ @param[in] SwSmiRate Refer to PMC_SWSMI_RATE for possible values
+**/
+VOID
+PmcSetSwSmiRate (
+ IN PMC_SWSMI_RATE SwSmiRate
+ )
+{
+ UINT32 PchPwrmBase;
+ STATIC UINT8 SwSmiRateRegVal[4] = {
+ V_PMC_PWRM_GEN_PMCON_A_SWSMI_RTSL_1_5MS,
+ V_PMC_PWRM_GEN_PMCON_A_SWSMI_RTSL_16MS,
+ V_PMC_PWRM_GEN_PMCON_A_SWSMI_RTSL_32MS,
+ V_PMC_PWRM_GEN_PMCON_A_SWSMI_RTSL_64MS
+ };
+
+ ASSERT (SwSmiRate <= PmcSwSmiRate64ms);
+
+ PchPwrmBase = PmcGetPwrmBase ();
+
+ //
+ // SWSMI_RATE_SEL BIT (PWRMBASE offset 1020h[7:6]) bits are in RTC well
+ //
+ MmioAndThenOr8 (
+ PchPwrmBase + R_PMC_PWRM_GEN_PMCON_A,
+ (UINT8)~B_PMC_PWRM_GEN_PMCON_A_SWSMI_RTSL,
+ SwSmiRateRegVal[SwSmiRate]
+ );
+}
+
+/**
+ This function sets Periodic SMI Rate.
+
+ @param[in] PeriodicSmiRate Refer to PMC_PERIODIC_SMI_RATE for possible values
+**/
+VOID
+PmcSetPeriodicSmiRate (
+ IN PMC_PERIODIC_SMI_RATE PeriodicSmiRate
+ )
+{
+ UINT32 PchPwrmBase;
+ STATIC UINT8 PeriodicSmiRateRegVal[4] = {
+ V_PMC_PWRM_GEN_PMCON_A_PER_SMI_8S,
+ V_PMC_PWRM_GEN_PMCON_A_PER_SMI_16S,
+ V_PMC_PWRM_GEN_PMCON_A_PER_SMI_32S,
+ V_PMC_PWRM_GEN_PMCON_A_PER_SMI_64S
+ };
+
+ ASSERT (PeriodicSmiRate <= PmcPeriodicSmiRate64s);
+
+ PchPwrmBase = PmcGetPwrmBase ();
+
+ MmioAndThenOr8 (
+ PchPwrmBase + R_PMC_PWRM_GEN_PMCON_A,
+ (UINT8)~B_PMC_PWRM_GEN_PMCON_A_PER_SMI_SEL,
+ PeriodicSmiRateRegVal[PeriodicSmiRate]
+ );
+}
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/IncludePrivate/Library/SpiCommonLib.h b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/IncludePrivate/Library/SpiCommonLib.h
new file mode 100644
index 0000000000..e13718c9e9
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/IncludePrivate/Library/SpiCommonLib.h
@@ -0,0 +1,376 @@
+/** @file
+ Header file for the PCH SPI Common Driver.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _SPI_COMMON_LIB_H_
+#define _SPI_COMMON_LIB_H_
+
+#include <Protocol/Spi.h>
+
+//
+// Maximum time allowed while waiting the SPI cycle to complete
+// Wait Time = 6 seconds = 6000000 microseconds
+// Wait Period = 10 microseconds
+//
+#define SPI_WAIT_TIME 6000000 ///< Wait Time = 6 seconds = 6000000 microseconds
+
+#define SPI_WAIT_PERIOD 10 ///< Wait Period = 10 microseconds
+
+///
+/// Flash cycle Type
+///
+typedef enum {
+ FlashCycleRead,
+ FlashCycleWrite,
+ FlashCycleErase,
+ FlashCycleReadSfdp,
+ FlashCycleReadJedecId,
+ FlashCycleWriteStatus,
+ FlashCycleReadStatus,
+ FlashCycleMax
+} FLASH_CYCLE_TYPE;
+
+///
+/// Flash Component Number
+///
+typedef enum {
+ FlashComponent0,
+ FlashComponent1,
+ FlashComponentMax
+} FLASH_COMPONENT_NUM;
+
+///
+/// Private data structure definitions for the driver
+///
+#define PCH_SPI_PRIVATE_DATA_SIGNATURE SIGNATURE_32 ('P', 'S', 'P', 'I')
+
+typedef struct {
+ UINT32 Signature;
+ EFI_HANDLE Handle;
+ PCH_SPI_PROTOCOL SpiProtocol;
+ UINT16 PchAcpiBase;
+ UINT64 PchSpiBase;
+ UINT8 ReadPermission;
+ UINT8 WritePermission;
+ UINT32 SfdpVscc0Value;
+ UINT32 SfdpVscc1Value;
+ UINT16 PchStrapBaseAddr;
+ UINT16 PchStrapSize;
+ UINT16 CpuStrapBaseAddr;
+ UINT16 CpuStrapSize;
+ UINT8 NumberOfComponents;
+ UINT32 Component1StartAddr;
+ UINT32 TotalFlashSize;
+} SPI_INSTANCE;
+
+#define SPI_INSTANCE_FROM_SPIPROTOCOL(a) CR (a, SPI_INSTANCE, SpiProtocol, PCH_SPI_PRIVATE_DATA_SIGNATURE)
+
+//
+// Function prototypes used by the SPI protocol.
+//
+
+/**
+ Initialize an SPI protocol instance.
+
+ @param[in] SpiInstance Pointer to SpiInstance to initialize
+
+ @retval EFI_SUCCESS The protocol instance was properly initialized
+ @exception EFI_UNSUPPORTED The PCH is not supported by this module
+**/
+EFI_STATUS
+SpiProtocolConstructor (
+ IN SPI_INSTANCE *SpiInstance
+ );
+
+/**
+ This function is a hook for Spi to disable BIOS Write Protect
+
+ @retval EFI_SUCCESS The protocol instance was properly initialized
+ @retval EFI_ACCESS_DENIED The BIOS Region can only be updated in SMM phase
+
+**/
+EFI_STATUS
+EFIAPI
+DisableBiosWriteProtect (
+ VOID
+ );
+
+/**
+ This function is a hook for Spi to enable BIOS Write Protect
+
+
+**/
+VOID
+EFIAPI
+EnableBiosWriteProtect (
+ VOID
+ );
+
+/**
+ Acquire pch spi mmio address.
+
+ @param[in] SpiInstance Pointer to SpiInstance to initialize
+
+ @retval PchSpiBar0 return SPI MMIO address
+**/
+UINTN
+AcquireSpiBar0 (
+ IN SPI_INSTANCE *SpiInstance
+ );
+
+/**
+ Release pch spi mmio address.
+
+ @param[in] SpiInstance Pointer to SpiInstance to initialize
+
+ @retval None
+**/
+VOID
+ReleaseSpiBar0 (
+ IN SPI_INSTANCE *SpiInstance
+ );
+
+/**
+ Check if it's granted to do flash write.
+
+ @retval TRUE It's secure to do flash write.
+ @retval FALSE It's not secure to do flash write.
+**/
+BOOLEAN
+IsSpiFlashWriteGranted (
+ VOID
+ );
+
+/**
+ Check if a save and restore of the SPI controller state is necessary
+
+ @retval TRUE It's necessary to save and restore SPI controller state
+ @retval FALSE It's not necessary to save and restore SPI controller state
+**/
+BOOLEAN
+IsSpiControllerSaveRestoreEnabled (
+ VOID
+ );
+
+/**
+ Read data from the flash part.
+
+ @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
+ @param[in] FlashRegionType The Flash Region type for flash cycle which is listed in the Descriptor.
+ @param[in] Address The Flash Linear Address must fall within a region for which BIOS has access permissions.
+ @param[in] ByteCount Number of bytes in the data portion of the SPI cycle.
+ @param[out] Buffer The Pointer to caller-allocated buffer containing the dada received.
+ It is the caller's responsibility to make sure Buffer is large enough for the total number of bytes read.
+
+ @retval EFI_SUCCESS Command succeed.
+ @retval EFI_INVALID_PARAMETER The parameters specified are not valid.
+ @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
+**/
+EFI_STATUS
+EFIAPI
+SpiProtocolFlashRead (
+ IN PCH_SPI_PROTOCOL *This,
+ IN FLASH_REGION_TYPE FlashRegionType,
+ IN UINT32 Address,
+ IN UINT32 ByteCount,
+ OUT UINT8 *Buffer
+ );
+
+/**
+ Write data to the flash part.
+
+ @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
+ @param[in] FlashRegionType The Flash Region type for flash cycle which is listed in the Descriptor.
+ @param[in] Address The Flash Linear Address must fall within a region for which BIOS has access permissions.
+ @param[in] ByteCount Number of bytes in the data portion of the SPI cycle.
+ @param[in] Buffer Pointer to caller-allocated buffer containing the data sent during the SPI cycle.
+
+ @retval EFI_SUCCESS Command succeed.
+ @retval EFI_INVALID_PARAMETER The parameters specified are not valid.
+ @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
+**/
+EFI_STATUS
+EFIAPI
+SpiProtocolFlashWrite (
+ IN PCH_SPI_PROTOCOL *This,
+ IN FLASH_REGION_TYPE FlashRegionType,
+ IN UINT32 Address,
+ IN UINT32 ByteCount,
+ IN UINT8 *Buffer
+ );
+
+/**
+ Erase some area on the flash part.
+
+ @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
+ @param[in] FlashRegionType The Flash Region type for flash cycle which is listed in the Descriptor.
+ @param[in] Address The Flash Linear Address must fall within a region for which BIOS has access permissions.
+ @param[in] ByteCount Number of bytes in the data portion of the SPI cycle.
+
+ @retval EFI_SUCCESS Command succeed.
+ @retval EFI_INVALID_PARAMETER The parameters specified are not valid.
+ @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
+**/
+EFI_STATUS
+EFIAPI
+SpiProtocolFlashErase (
+ IN PCH_SPI_PROTOCOL *This,
+ IN FLASH_REGION_TYPE FlashRegionType,
+ IN UINT32 Address,
+ IN UINT32 ByteCount
+ );
+
+/**
+ Read SFDP data from the flash part.
+
+ @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
+ @param[in] ComponentNumber The Componen Number for chip select
+ @param[in] Address The starting byte address for SFDP data read.
+ @param[in] ByteCount Number of bytes in SFDP data portion of the SPI cycle
+ @param[out] SfdpData The Pointer to caller-allocated buffer containing the SFDP data received
+ It is the caller's responsibility to make sure Buffer is large enough for the total number of bytes read
+
+ @retval EFI_SUCCESS Command succeed.
+ @retval EFI_INVALID_PARAMETER The parameters specified are not valid.
+ @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
+**/
+EFI_STATUS
+EFIAPI
+SpiProtocolFlashReadSfdp (
+ IN PCH_SPI_PROTOCOL *This,
+ IN UINT8 ComponentNumber,
+ IN UINT32 Address,
+ IN UINT32 ByteCount,
+ OUT UINT8 *SfdpData
+ );
+
+/**
+ Read Jedec Id from the flash part.
+
+ @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
+ @param[in] ComponentNumber The Componen Number for chip select
+ @param[in] ByteCount Number of bytes in JedecId data portion of the SPI cycle, the data size is 3 typically
+ @param[out] JedecId The Pointer to caller-allocated buffer containing JEDEC ID received
+ It is the caller's responsibility to make sure Buffer is large enough for the total number of bytes read.
+
+ @retval EFI_SUCCESS Command succeed.
+ @retval EFI_INVALID_PARAMETER The parameters specified are not valid.
+ @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
+**/
+EFI_STATUS
+EFIAPI
+SpiProtocolFlashReadJedecId (
+ IN PCH_SPI_PROTOCOL *This,
+ IN UINT8 ComponentNumber,
+ IN UINT32 ByteCount,
+ OUT UINT8 *JedecId
+ );
+
+/**
+ Write the status register in the flash part.
+
+ @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
+ @param[in] ByteCount Number of bytes in Status data portion of the SPI cycle, the data size is 1 typically
+ @param[in] StatusValue The Pointer to caller-allocated buffer containing the value of Status register writing
+
+ @retval EFI_SUCCESS Command succeed.
+ @retval EFI_INVALID_PARAMETER The parameters specified are not valid.
+ @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
+**/
+EFI_STATUS
+EFIAPI
+SpiProtocolFlashWriteStatus (
+ IN PCH_SPI_PROTOCOL *This,
+ IN UINT32 ByteCount,
+ IN UINT8 *StatusValue
+ );
+
+/**
+ Read status register in the flash part.
+
+ @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
+ @param[in] ByteCount Number of bytes in Status data portion of the SPI cycle, the data size is 1 typically
+ @param[out] StatusValue The Pointer to caller-allocated buffer containing the value of Status register received.
+
+ @retval EFI_SUCCESS Command succeed.
+ @retval EFI_INVALID_PARAMETER The parameters specified are not valid.
+ @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
+**/
+EFI_STATUS
+EFIAPI
+SpiProtocolFlashReadStatus (
+ IN PCH_SPI_PROTOCOL *This,
+ IN UINT32 ByteCount,
+ OUT UINT8 *StatusValue
+ );
+
+/**
+ Get the SPI region base and size, based on the enum type
+
+ @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
+ @param[in] FlashRegionType The Flash Region type for for the base address which is listed in the Descriptor.
+ @param[out] BaseAddress The Flash Linear Address for the Region 'n' Base
+ @param[out] RegionSize The size for the Region 'n'
+
+ @retval EFI_SUCCESS Read success
+ @retval EFI_INVALID_PARAMETER Invalid region type given
+ @retval EFI_DEVICE_ERROR The region is not used
+**/
+EFI_STATUS
+EFIAPI
+SpiProtocolGetRegionAddress (
+ IN PCH_SPI_PROTOCOL *This,
+ IN FLASH_REGION_TYPE FlashRegionType,
+ OUT UINT32 *BaseAddress,
+ OUT UINT32 *RegionSize
+ );
+
+/**
+ Read PCH Soft Strap Values
+
+ @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
+ @param[in] SoftStrapAddr PCH Soft Strap address offset from FPSBA.
+ @param[in] ByteCount Number of bytes in SoftStrap data portion of the SPI cycle
+ @param[out] SoftStrapValue The Pointer to caller-allocated buffer containing PCH Soft Strap Value.
+ If the value of ByteCount is 0, the data type of SoftStrapValue should be UINT16 and SoftStrapValue will be PCH Soft Strap Length
+ It is the caller's responsibility to make sure Buffer is large enough for the total number of bytes read.
+
+ @retval EFI_SUCCESS Command succeed.
+ @retval EFI_INVALID_PARAMETER The parameters specified are not valid.
+ @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
+**/
+EFI_STATUS
+EFIAPI
+SpiProtocolReadPchSoftStrap (
+ IN PCH_SPI_PROTOCOL *This,
+ IN UINT32 SoftStrapAddr,
+ IN UINT32 ByteCount,
+ OUT VOID *SoftStrapValue
+ );
+
+/**
+ Read CPU Soft Strap Values
+
+ @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
+ @param[in] SoftStrapAddr CPU Soft Strap address offset from FCPUSBA.
+ @param[in] ByteCount Number of bytes in SoftStrap data portion of the SPI cycle.
+ @param[out] SoftStrapValue The Pointer to caller-allocated buffer containing CPU Soft Strap Value.
+ If the value of ByteCount is 0, the data type of SoftStrapValue should be UINT16 and SoftStrapValue will be PCH Soft Strap Length
+ It is the caller's responsibility to make sure Buffer is large enough for the total number of bytes read.
+
+ @retval EFI_SUCCESS Command succeed.
+ @retval EFI_INVALID_PARAMETER The parameters specified are not valid.
+ @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
+**/
+EFI_STATUS
+EFIAPI
+SpiProtocolReadCpuSoftStrap (
+ IN PCH_SPI_PROTOCOL *This,
+ IN UINT32 SoftStrapAddr,
+ IN UINT32 ByteCount,
+ OUT VOID *SoftStrapValue
+ );
+
+#endif
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/IncludePrivate/Register/SpiRegs.h b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/IncludePrivate/Register/SpiRegs.h
new file mode 100644
index 0000000000..5cb4791142
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/IncludePrivate/Register/SpiRegs.h
@@ -0,0 +1,116 @@
+/** @file
+ Register names for PCH SPI device.
+
+ Conventions:
+
+ - Register definition format:
+ Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_RegisterName
+ - Prefix:
+ Definitions beginning with "R_" are registers
+ Definitions beginning with "B_" are bits within registers
+ Definitions beginning with "V_" are meaningful values within the bits
+ Definitions beginning with "S_" are register size
+ Definitions beginning with "N_" are the bit position
+ - [GenerationName]:
+ Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc.).
+ Register name without GenerationName applies to all generations.
+ - [ComponentName]:
+ This field indicates the component name that the register belongs to (e.g. PCH, SA etc.)
+ Register name without ComponentName applies to all components.
+ Register that is specific to -H denoted by "_PCH_H_" in component name.
+ Register that is specific to -LP denoted by "_PCH_LP_" in component name.
+ - SubsystemName:
+ This field indicates the subsystem name of the component that the register belongs to
+ (e.g. PCIE, USB, SATA, GPIO, PMC etc.).
+ - RegisterSpace:
+ MEM - MMIO space register of subsystem.
+ IO - IO space register of subsystem.
+ PCR - Private configuration register of subsystem.
+ CFG - PCI configuration space register of subsystem.
+ - RegisterName:
+ Full register name.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _SPI_REGS_H_
+#define _SPI_REGS_H_
+
+//
+// SPI Registers
+//
+#define R_SPI_CFG_BAR0 0x10
+#define B_SPI_CFG_BAR0_MASK 0x0FFF
+
+
+#define R_SPI_CFG_BC 0xDC
+#define S_SPI_CFG_BC 4
+#define N_SPI_CFG_BC_ASE_BWP 11
+#define B_SPI_CFG_BC_ASE_BWP BIT11
+#define N_SPI_CFG_BC_ASYNC_SS 10
+#define B_SPI_CFG_BC_ASYNC_SS BIT10
+#define N_SPI_CFG_BC_SYNC_SS 8
+#define B_SPI_CFG_BC_SYNC_SS BIT8
+#define B_SPI_CFG_BC_BILD BIT7
+#define B_SPI_CFG_BC_EISS BIT5 ///< Enable InSMM.STS
+#define B_SPI_CFG_BC_SRC (BIT3 | BIT2)
+#define N_SPI_CFG_BC_SRC 2
+#define V_SPI_CFG_BC_SRC_PREF_DIS_CACHE_DIS 0x01 ///< No prefetching and no caching
+#define N_SPI_CFG_BC_BLE 1
+#define B_SPI_CFG_BC_WPD BIT0 ///< Write Protect Disable
+
+//
+// BIOS Flash Program Registers (based on SPI_BAR0)
+//
+#define R_SPI_MEM_HSFSC 0x04 ///< Hardware Sequencing Flash Status and Control Register(32bits)
+#define B_SPI_MEM_HSFSC_FDBC_MASK 0x3F000000 ///< Flash Data Byte Count ( <= 64), Count = (Value in this field) + 1.
+#define N_SPI_MEM_HSFSC_FDBC 24
+#define B_SPI_MEM_HSFSC_CYCLE_MASK 0x001E0000 ///< Flash Cycle.
+#define N_SPI_MEM_HSFSC_CYCLE 17
+#define V_SPI_MEM_HSFSC_CYCLE_READ 0 ///< Flash Cycle Read
+#define V_SPI_MEM_HSFSC_CYCLE_WRITE 2 ///< Flash Cycle Write
+#define V_SPI_MEM_HSFSC_CYCLE_4K_ERASE 3 ///< Flash Cycle 4K Block Erase
+#define V_SPI_MEM_HSFSC_CYCLE_64K_ERASE 4 ///< Flash Cycle 64K Sector Erase
+#define V_SPI_MEM_HSFSC_CYCLE_READ_SFDP 5 ///< Flash Cycle Read SFDP
+#define V_SPI_MEM_HSFSC_CYCLE_READ_JEDEC_ID 6 ///< Flash Cycle Read JEDEC ID
+#define V_SPI_MEM_HSFSC_CYCLE_WRITE_STATUS 7 ///< Flash Cycle Write Status
+#define V_SPI_MEM_HSFSC_CYCLE_READ_STATUS 8 ///< Flash Cycle Read Status
+#define B_SPI_MEM_HSFSC_CYCLE_FGO BIT16 ///< Flash Cycle Go.
+#define B_SPI_MEM_HSFSC_FDV BIT14 ///< Flash Descriptor Valid, once valid software can use hareware sequencing regs
+#define B_SPI_MEM_HSFSC_WRSDIS BIT11 ///< Write Status Disable
+#define B_SPI_MEM_HSFSC_SAF_CE BIT8 ///< SAF ctype error
+#define B_SPI_MEM_HSFSC_SAF_LE BIT6 ///< SAF link error
+#define B_SPI_MEM_HSFSC_SCIP BIT5 ///< SPI cycle in progress
+#define B_SPI_MEM_HSFSC_SAF_DLE BIT4 ///< SAF Data length error
+#define B_SPI_MEM_HSFSC_SAF_ERROR BIT3 ///< SAF Error
+#define B_SPI_MEM_HSFSC_AEL BIT2 ///< Access Error Log
+#define B_SPI_MEM_HSFSC_FCERR BIT1 ///< Flash Cycle Error
+#define B_SPI_MEM_HSFSC_FDONE BIT0 ///< Flash Cycle Done
+#define R_SPI_MEM_FADDR 0x08 ///< SPI Flash Address
+#define B_SPI_MEM_FADDR_MASK 0x07FFFFFF ///< SPI Flash Address Mask (0~26bit)
+#define R_SPI_MEM_FDATA00 0x10 ///< SPI Data 00 (32 bits)
+#define R_SPI_MEM_FRAP 0x50 ///< Flash Region Access Permissions Register
+#define B_SPI_MEM_FRAP_BRWA_MASK 0x0000FF00 ///< BIOS Region Write Access MASK, Region0~7 - 0: Flash Descriptor; 1: BIOS; 2: ME; 3: GbE; 4: PlatformData
+#define N_SPI_MEM_FRAP_BRWA 8 ///< BIOS Region Write Access bit position
+#define B_SPI_MEM_FRAP_BRRA_MASK 0x000000FF ///< BIOS Region Read Access MASK, Region0~7 - 0: Flash Descriptor; 1: BIOS; 2: ME; 3: GbE; 4: PlatformData
+#define R_SPI_MEM_FREG0_FLASHD 0x54 ///< Flash Region 0(Flash Descriptor)(32bits)
+#define S_SPI_MEM_FREGX 4 ///< Size of Flash Region register
+#define B_SPI_MEM_FREGX_LIMIT_MASK 0x7FFF0000 ///< Flash Region Limit [30:16] represents [26:12], [11:0] are assumed to be FFFh
+#define N_SPI_MEM_FREGX_LIMIT 16 ///< Region limit bit position
+#define N_SPI_MEM_FREGX_LIMIT_REPR 12 ///< Region limit bit represents position
+#define B_SPI_MEM_FREGX_BASE_MASK 0x00007FFF ///< Flash Region Base, [14:0] represents [26:12]
+#define N_SPI_MEM_FREGX_BASE 0 ///< Region base bit position
+#define N_SPI_MEM_FREGX_BASE_REPR 12 ///< Region base bit represents position
+#define R_SPI_MEM_FDOC 0xB4 ///< Flash Descriptor Observability Control Register(32 bits)
+#define B_SPI_MEM_FDOC_FDSS_MASK (BIT14 | BIT13 | BIT12) ///< Flash Descritor Section Select
+#define V_SPI_MEM_FDOC_FDSS_FSDM 0x0000 ///< Flash Signature and Descriptor Map
+#define V_SPI_MEM_FDOC_FDSS_COMP 0x1000 ///< Component
+
+#define B_SPI_MEM_FDOC_FDSI_MASK 0x0FFC ///< Flash Descriptor Section Index
+#define R_SPI_MEM_FDOD 0xB8 ///< Flash Descriptor Observability Data Register(32 bits)
+#define R_SPI_MEM_SFDP0_VSCC0 0xC4 ///< Vendor Specific Component Capabilities Register(32 bits)
+
+#define B_SPI_MEM_SFDPX_VSCCX_EO_64K BIT29 ///< 64k Erase valid (EO_64k_valid)
+#define R_SPI_MEM_SFDP1_VSCC1 0xC8 ///< Vendor Specific Component Capabilities Register(32 bits)
+
+#endif
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/Library/PeiSpiLib/PchSpi.c b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/Library/PeiSpiLib/PchSpi.c
new file mode 100644
index 0000000000..aaf4e1790f
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/Library/PeiSpiLib/PchSpi.c
@@ -0,0 +1,209 @@
+/** @file
+ PCH SPI PEI Library implements the SPI Host Controller Compatibility Interface.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#include <Library/IoLib.h>
+#include <Library/DebugLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/PeiServicesLib.h>
+#include <Library/PciSegmentLib.h>
+#include <Ppi/Spi.h>
+#include <Library/SpiCommonLib.h>
+#include <PchReservedResources.h>
+#include <IndustryStandard/Pci30.h>
+#include <Register/PchRegs.h>
+#include <Register/PchRegsLpc.h>
+#include <Register/SpiRegs.h>
+#include <Library/PchPciBdfLib.h>
+
+typedef struct {
+ EFI_PEI_PPI_DESCRIPTOR PpiDescriptor;
+ SPI_INSTANCE SpiInstance;
+} PEI_SPI_INSTANCE;
+
+/**
+ PCI Enumeratuion is not done till later in DXE
+ Initlialize SPI BAR0 to a default value till enumeration is done
+ also enable memory space decoding for SPI
+
+**/
+VOID
+InitSpiBar0 (
+ VOID
+ )
+{
+ UINT64 PchSpiBase;
+ PchSpiBase = SpiPciCfgBase ();
+ PciSegmentWrite32 (PchSpiBase + R_SPI_CFG_BAR0, PCH_SPI_BASE_ADDRESS);
+ PciSegmentOr32 (PchSpiBase + PCI_COMMAND_OFFSET, EFI_PCI_COMMAND_MEMORY_SPACE);
+}
+
+/**
+ This function Initial SPI services
+
+ @retval EFI_STATUS Results of the installation of the SPI services
+**/
+EFI_STATUS
+EFIAPI
+SpiServiceInit (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+ PEI_SPI_INSTANCE *PeiSpiInstance;
+ SPI_INSTANCE *SpiInstance;
+ PCH_SPI_PPI *SpiPpi;
+
+ Status = PeiServicesLocatePpi (
+ &gPchSpiPpiGuid,
+ 0,
+ NULL,
+ (VOID **)&SpiPpi
+ );
+
+ if (Status != EFI_SUCCESS) {
+ DEBUG ((DEBUG_INFO, "SpiServiceInit() Start\n"));
+
+ //
+ // PCI Enumeratuion is not done till later in DXE
+ // Initlialize SPI BAR0 to a default value till enumeration is done
+ // also enable memory space decoding for SPI
+ //
+ InitSpiBar0 ();
+
+ PeiSpiInstance = (PEI_SPI_INSTANCE *) AllocateZeroPool (sizeof (PEI_SPI_INSTANCE));
+ if (NULL == PeiSpiInstance) {
+ return EFI_OUT_OF_RESOURCES;
+ }
+
+ SpiInstance = &(PeiSpiInstance->SpiInstance);
+ SpiProtocolConstructor (SpiInstance);
+
+ PeiSpiInstance->PpiDescriptor.Flags = EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST;
+ PeiSpiInstance->PpiDescriptor.Guid = &gPchSpiPpiGuid;
+ PeiSpiInstance->PpiDescriptor.Ppi = &(SpiInstance->SpiProtocol);
+
+ ///
+ /// Install the SPI PPI
+ ///
+ DEBUG ((DEBUG_INFO, "SPI PPI Installed\n"));
+ Status = PeiServicesInstallPpi (&PeiSpiInstance->PpiDescriptor);
+ ASSERT_EFI_ERROR (Status);
+
+ DEBUG ((DEBUG_INFO, "SpiServiceInit() End\n"));
+ }
+ else {
+ DEBUG ((DEBUG_INFO, "SPI PPI already installed\n"));
+ }
+ return Status;
+}
+
+/**
+ Acquire pch spi mmio address.
+
+ @param[in] SpiInstance Pointer to SpiInstance to initialize
+
+ @retval PchSpiBar0 return SPI MMIO address
+**/
+UINTN
+AcquireSpiBar0 (
+ IN SPI_INSTANCE *SpiInstance
+ )
+{
+ return PciSegmentRead32 (SpiInstance->PchSpiBase + R_SPI_CFG_BAR0) & ~(B_SPI_CFG_BAR0_MASK);
+}
+
+/**
+ Release pch spi mmio address. Do nothing.
+
+ @param[in] SpiInstance Pointer to SpiInstance to initialize
+
+ @retval None
+**/
+VOID
+ReleaseSpiBar0 (
+ IN SPI_INSTANCE *SpiInstance
+ )
+{
+}
+
+/**
+ This function is a hook for Spi to disable BIOS Write Protect
+
+ @retval EFI_SUCCESS The protocol instance was properly initialized
+ @retval EFI_ACCESS_DENIED The BIOS Region can only be updated in SMM phase
+
+**/
+EFI_STATUS
+EFIAPI
+DisableBiosWriteProtect (
+ VOID
+ )
+{
+ UINT64 SpiBaseAddress;
+
+ SpiBaseAddress = SpiPciCfgBase ();
+ if ((PciSegmentRead8 (SpiBaseAddress + R_SPI_CFG_BC) & B_SPI_CFG_BC_EISS) != 0) {
+ return EFI_ACCESS_DENIED;
+ }
+ ///
+ /// Enable the access to the BIOS space for both read and write cycles
+ ///
+ PciSegmentOr8 (
+ SpiBaseAddress + R_SPI_CFG_BC,
+ B_SPI_CFG_BC_WPD
+ );
+
+ return EFI_SUCCESS;
+}
+
+/**
+ This function is a hook for Spi to enable BIOS Write Protect
+**/
+VOID
+EFIAPI
+EnableBiosWriteProtect (
+ VOID
+ )
+{
+ UINT64 SpiBaseAddress;
+
+ SpiBaseAddress = SpiPciCfgBase ();
+ ///
+ /// Disable the access to the BIOS space for write cycles
+ ///
+ PciSegmentAnd8 (
+ SpiBaseAddress + R_SPI_CFG_BC,
+ (UINT8) (~B_SPI_CFG_BC_WPD)
+ );
+}
+
+/**
+ Check if it's granted to do flash write.
+
+ @retval TRUE It's secure to do flash write.
+ @retval FALSE It's not secure to do flash write.
+**/
+BOOLEAN
+IsSpiFlashWriteGranted (
+ VOID
+ )
+{
+ return TRUE;
+}
+
+/**
+ Check if a save and restore of the SPI controller state is necessary
+
+ @retval TRUE It's necessary to save and restore SPI controller state
+ @retval FALSE It's not necessary to save and restore SPI controller state
+**/
+BOOLEAN
+IsSpiControllerSaveRestoreEnabled (
+ VOID
+ )
+{
+ return FALSE;
+}
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/Library/PeiSpiLib/PeiSpiLib.inf b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/Library/PeiSpiLib/PeiSpiLib.inf
new file mode 100644
index 0000000000..c3bf6d02a1
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/Library/PeiSpiLib/PeiSpiLib.inf
@@ -0,0 +1,41 @@
+## @file
+# Component description file for PCH Reset Lib Pei Phase
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+[Defines]
+INF_VERSION = 0x00010017
+BASE_NAME = PeiSpiLib
+FILE_GUID = 4998447D-7948-448F-AB75-96E24E18FF23
+VERSION_STRING = 1.0
+MODULE_TYPE = PEIM
+LIBRARY_CLASS = SpiLib
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = IA32 X64 IPF
+#
+
+[LibraryClasses]
+DebugLib
+PeiServicesLib
+PeiServicesTablePointerLib
+MemoryAllocationLib
+PciSegmentLib
+SpiCommonLib
+PchPciBdfLib
+
+[Packages]
+MdePkg/MdePkg.dec
+AlderlakeSiliconPkg/SiPkg.dec
+
+
+[Sources]
+PchSpi.c
+
+
+[Ppis]
+gPchSpiPpiGuid ## PRODUCES
+
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/LibraryPrivate/BaseSpiCommonLib/BaseSpiCommonLib.inf b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/LibraryPrivate/BaseSpiCommonLib/BaseSpiCommonLib.inf
new file mode 100644
index 0000000000..25ab91940c
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/LibraryPrivate/BaseSpiCommonLib/BaseSpiCommonLib.inf
@@ -0,0 +1,29 @@
+## @file
+# Component description file for the PchSpiCommonLib
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = BaseSpiCommonLib
+ FILE_GUID = A37CB67E-7D85-45B3-B07E-BF65BDB603E8
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = SpiCommonLib
+
+[Sources]
+ SpiCommon.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ AlderlakeSiliconPkg/SiPkg.dec
+
+[LibraryClasses]
+ IoLib
+ DebugLib
+ PmcLib
+ PchPciBdfLib
+
+[Pcd]
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/LibraryPrivate/BaseSpiCommonLib/SpiCommon.c b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/LibraryPrivate/BaseSpiCommonLib/SpiCommon.c
new file mode 100644
index 0000000000..ab51521f14
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/LibraryPrivate/BaseSpiCommonLib/SpiCommon.c
@@ -0,0 +1,1127 @@
+/** @file
+ PCH SPI Common Driver implements the SPI Host Controller Compatibility Interface.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#include <Uefi/UefiBaseType.h>
+#include <Library/BaseLib.h>
+#include <Library/IoLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <IndustryStandard/Pci30.h>
+#include <Library/PmcLib.h>
+#include <Library/PciSegmentLib.h>
+#include <Protocol/Spi.h>
+#include <Library/SpiCommonLib.h>
+#include <Register/PchRegs.h>
+#include <Register/SpiRegs.h>
+#include <Register/FlashRegs.h>
+#include <Register/PmcRegs.h>
+#include <Library/PchPciBdfLib.h>
+
+#define DEFAULT_CPU_STRAP_BASE_OFFSET 0x300 // Default CPU Straps base offset
+#define B_SPI_MEM_HSFSC_SAVE_MASK (B_SPI_MEM_HSFSC_FDBC_MASK | B_SPI_MEM_HSFSC_CYCLE_MASK)
+
+/**
+ Initialize an SPI protocol instance.
+
+ @param[in] SpiInstance Pointer to SpiInstance to initialize
+
+ @retval EFI_SUCCESS The protocol instance was properly initialized
+ @exception EFI_UNSUPPORTED The PCH is not supported by this module
+**/
+EFI_STATUS
+SpiProtocolConstructor (
+ IN SPI_INSTANCE *SpiInstance
+ )
+{
+ UINTN PchSpiBar0;
+ UINT32 Data32;
+ UINT16 Mdtba;
+ EFI_STATUS Status;
+
+ //
+ // Initialize the SPI protocol instance
+ //
+ SpiInstance->Signature = PCH_SPI_PRIVATE_DATA_SIGNATURE;
+ SpiInstance->Handle = NULL;
+ SpiInstance->SpiProtocol.Revision = PCH_SPI_SERVICES_REVISION;
+ SpiInstance->SpiProtocol.FlashRead = SpiProtocolFlashRead;
+ SpiInstance->SpiProtocol.FlashWrite = SpiProtocolFlashWrite;
+ SpiInstance->SpiProtocol.FlashErase = SpiProtocolFlashErase;
+ SpiInstance->SpiProtocol.FlashReadSfdp = SpiProtocolFlashReadSfdp;
+ SpiInstance->SpiProtocol.FlashReadJedecId = SpiProtocolFlashReadJedecId;
+ SpiInstance->SpiProtocol.FlashWriteStatus = SpiProtocolFlashWriteStatus;
+ SpiInstance->SpiProtocol.FlashReadStatus = SpiProtocolFlashReadStatus;
+ SpiInstance->SpiProtocol.GetRegionAddress = SpiProtocolGetRegionAddress;
+ SpiInstance->SpiProtocol.ReadPchSoftStrap = SpiProtocolReadPchSoftStrap;
+ SpiInstance->SpiProtocol.ReadCpuSoftStrap = SpiProtocolReadCpuSoftStrap;
+
+ SpiInstance->PchSpiBase = SpiPciCfgBase ();
+
+ SpiInstance->PchAcpiBase = PmcGetAcpiBase ();
+ ASSERT (SpiInstance->PchAcpiBase != 0);
+
+ PchSpiBar0 = PciSegmentRead32 (SpiInstance->PchSpiBase + R_SPI_CFG_BAR0) & ~(B_SPI_CFG_BAR0_MASK);
+ if (PchSpiBar0 == 0) {
+ DEBUG ((DEBUG_ERROR, "ERROR : PchSpiBar0 is invalid!\n"));
+ ASSERT (FALSE);
+ }
+
+ if ((MmioRead32 (PchSpiBar0 + R_SPI_MEM_HSFSC) & B_SPI_MEM_HSFSC_FDV) == 0) {
+ DEBUG ((DEBUG_ERROR, "ERROR : SPI Flash Signature invalid, cannot use the Hardware Sequencing registers!\n"));
+ ASSERT (FALSE);
+ }
+
+ //
+ // Get Region 0 - 7 read Permission bits, region 8 and above are not permitted.
+ //
+ SpiInstance->ReadPermission = MmioRead8 (PchSpiBar0 + R_SPI_MEM_FRAP) & B_SPI_MEM_FRAP_BRRA_MASK;
+ DEBUG ((DEBUG_INFO, "Flash Region read Permission : %0x\n", SpiInstance->ReadPermission));
+ //
+ // Get Region 0 - 7 write Permission bits, region 8 and above are not permitted.
+ //
+ SpiInstance->WritePermission = (UINT8) ((MmioRead16 (PchSpiBar0 + R_SPI_MEM_FRAP) &
+ B_SPI_MEM_FRAP_BRWA_MASK) >> N_SPI_MEM_FRAP_BRWA);
+ DEBUG ((DEBUG_INFO, "Flash Region write Permission : %0x\n", SpiInstance->WritePermission));
+
+ SpiInstance->SfdpVscc0Value = MmioRead32 (PchSpiBar0 + R_SPI_MEM_SFDP0_VSCC0);
+ DEBUG ((DEBUG_INFO, "Component 0 SFDP VSCC value : %0x\n", SpiInstance->SfdpVscc0Value));
+ SpiInstance->SfdpVscc1Value = MmioRead32 (PchSpiBar0 + R_SPI_MEM_SFDP1_VSCC1);
+ DEBUG ((DEBUG_INFO, "Component 1 SFDP VSCC value : %0x\n", SpiInstance->SfdpVscc1Value));
+
+ //
+ // Select to Flash Map 0 Register to get the number of flash Component
+ //
+ MmioAndThenOr32 (
+ PchSpiBar0 + R_SPI_MEM_FDOC,
+ (UINT32) (~(B_SPI_MEM_FDOC_FDSS_MASK | B_SPI_MEM_FDOC_FDSI_MASK)),
+ (UINT32) (V_SPI_MEM_FDOC_FDSS_FSDM | R_FLASH_FDBAR_FLASH_MAP0)
+ );
+
+ //
+ // Copy Zero based Number Of Components
+ //
+ SpiInstance->NumberOfComponents = (UINT8) ((MmioRead16 (PchSpiBar0 + R_SPI_MEM_FDOD) & B_FLASH_FDBAR_NC) >> N_FLASH_FDBAR_NC);
+ DEBUG ((DEBUG_INFO, "Component Number : %0x\n", SpiInstance->NumberOfComponents + 1));
+
+ MmioAndThenOr32 (
+ PchSpiBar0 + R_SPI_MEM_FDOC,
+ (UINT32) (~(B_SPI_MEM_FDOC_FDSS_MASK | B_SPI_MEM_FDOC_FDSI_MASK)),
+ (UINT32) (V_SPI_MEM_FDOC_FDSS_COMP | R_FLASH_FCBA_FLCOMP)
+ );
+
+ //
+ // Copy Component 0 Density
+ //
+ Data32 = MmioRead32 (PchSpiBar0 + R_SPI_MEM_FDOD);
+ if (SpiInstance->NumberOfComponents > 0) {
+ SpiInstance->Component1StartAddr = V_FLASH_FLCOMP_COMP_512KB <<
+ (Data32 & B_FLASH_FLCOMP_COMP0_MASK);
+ DEBUG ((DEBUG_INFO, "Component 1 StartAddr : %0x\n", SpiInstance->Component1StartAddr));
+ SpiInstance->TotalFlashSize = SpiInstance->Component1StartAddr +
+ (V_FLASH_FLCOMP_COMP_512KB <<
+ ((Data32 & B_FLASH_FLCOMP_COMP1_MASK) >>
+ N_FLASH_FLCOMP_COMP1));
+ } else {
+ SpiInstance->TotalFlashSize = V_FLASH_FLCOMP_COMP_512KB <<
+ (Data32 & B_FLASH_FLCOMP_COMP0_MASK);
+ }
+ DEBUG ((DEBUG_INFO, "Total Flash Size : %0x\n", SpiInstance->TotalFlashSize));
+
+ //
+ // Select FLASH_MAP1 to get Flash PCH Strap Base Address
+ //
+ MmioAndThenOr32 (
+ (PchSpiBar0 + R_SPI_MEM_FDOC),
+ (UINT32) (~(B_SPI_MEM_FDOC_FDSS_MASK | B_SPI_MEM_FDOC_FDSI_MASK)),
+ (UINT32) (V_SPI_MEM_FDOC_FDSS_FSDM | R_FLASH_FDBAR_FLASH_MAP1)
+ );
+ //
+ // Align FPSBA with address bits for the PCH Strap portion of flash descriptor
+ //
+ Data32 = MmioRead32 (PchSpiBar0 + R_SPI_MEM_FDOD);
+ SpiInstance->PchStrapBaseAddr = (UINT16) (((Data32 & B_FLASH_FDBAR_FPSBA)
+ >> N_FLASH_FDBAR_FPSBA)
+ << N_FLASH_FDBAR_FPSBA_REPR);
+ DEBUG ((DEBUG_INFO, "PchStrapBaseAddr : %0x\n", SpiInstance->PchStrapBaseAddr));
+ ASSERT (SpiInstance->PchStrapBaseAddr != 0);
+ //
+ // PCH Strap Length, [31:24] represents number of Dwords
+ //
+ SpiInstance->PchStrapSize = (UINT16) (((Data32 & B_FLASH_FDBAR_PCHSL)
+ >> N_FLASH_FDBAR_PCHSL)
+ * sizeof (UINT32));
+ DEBUG ((DEBUG_INFO, "PchStrapSize : %0x\n", SpiInstance->PchStrapSize));
+
+ //
+ // Select FLASH_MAP2 to get Flash CPU Strap Base Address
+ //
+ MmioAndThenOr32 (
+ (PchSpiBar0 + R_SPI_MEM_FDOC),
+ (UINT32) (~(B_SPI_MEM_FDOC_FDSS_MASK | B_SPI_MEM_FDOC_FDSI_MASK)),
+ (UINT32) (V_SPI_MEM_FDOC_FDSS_FSDM | R_FLASH_FDBAR_FLASH_MAP2)
+ );
+ //
+ // Align FPSBA with address bits for the CPU Strap portion of flash descriptor
+ //
+ Data32 = MmioRead32 (PchSpiBar0 + R_SPI_MEM_FDOD);
+ //
+ // CPU Strap Length, [23:16] represents number of Dwords
+ //
+ SpiInstance->CpuStrapSize = (UINT16) (((Data32 & B_FLASH_FDBAR_CPUSL)
+ >> N_FLASH_FDBAR_CPUSL)
+ * sizeof (UINT32));
+
+ //
+ // CPU Strap Address [11:2] represent offset from MDTBA
+ //
+ SpiInstance->CpuStrapBaseAddr = (UINT16) ((Data32 & B_FLASH_FDBAR_FCPUSBA) >> N_FLASH_FDBAR_FCPUSBA);
+ ASSERT (SpiInstance->CpuStrapBaseAddr != 0);
+
+ //
+ // If CPU Strap base address is different than 0x300 need to add MDTBA value for final location
+ //
+ if (SpiInstance->CpuStrapBaseAddr != DEFAULT_CPU_STRAP_BASE_OFFSET) {
+ Status = SpiProtocolFlashRead (&(SpiInstance->SpiProtocol), FlashRegionAll, R_FLASH_UMAP1, sizeof (Data32), (UINT8 *) (&Data32));
+ ASSERT_EFI_ERROR (Status);
+ Mdtba = (UINT16)(((Data32 & B_FLASH_UMAP1_MDTBA) >> N_FLASH_UMAP1_MDTBA) << N_FLASH_UMAP1_MDTBA_REPR);
+ DEBUG ((DEBUG_INFO, "Mdtba : %0x\n", Mdtba));
+ // Add MDTBA offset for final address of CPU Straps
+ SpiInstance->CpuStrapBaseAddr += Mdtba;
+ }
+
+ DEBUG ((DEBUG_INFO, "CpuStrapBaseAddr : %0x\n", SpiInstance->CpuStrapBaseAddr));
+ DEBUG ((DEBUG_INFO, "CpuStrapSize : %0x\n", SpiInstance->CpuStrapSize));
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Delay for at least the request number of microseconds for Runtime usage.
+
+ @param[in] ABase Acpi base address
+ @param[in] Microseconds Number of microseconds to delay.
+
+**/
+VOID
+EFIAPI
+PchPmTimerStallRuntimeSafe (
+ IN UINT16 ABase,
+ IN UINTN Microseconds
+ )
+{
+ UINTN Ticks;
+ UINTN Counts;
+ UINTN CurrentTick;
+ UINTN OriginalTick;
+ UINTN RemainingTick;
+
+ if (Microseconds == 0) {
+ return;
+ }
+
+ OriginalTick = IoRead32 ((UINTN) (ABase + R_ACPI_IO_PM1_TMR)) & B_ACPI_IO_PM1_TMR_TMR_VAL;
+ CurrentTick = OriginalTick;
+
+ //
+ // The timer frequency is 3.579545 MHz, so 1 ms corresponds 3.58 clocks
+ //
+ Ticks = Microseconds * 358 / 100 + OriginalTick + 1;
+
+ //
+ // The loops needed by timer overflow
+ //
+ Counts = Ticks / V_ACPI_IO_PM1_TMR_MAX_VAL;
+
+ //
+ // Remaining clocks within one loop
+ //
+ RemainingTick = Ticks % V_ACPI_IO_PM1_TMR_MAX_VAL;
+
+ //
+ // not intend to use TMROF_STS bit of register PM1_STS, because this adds extra
+ // one I/O operation, and maybe generate SMI
+ //
+ while ((Counts != 0) || (RemainingTick > CurrentTick)) {
+ CurrentTick = IoRead32 ((UINTN) (ABase + R_ACPI_IO_PM1_TMR)) & B_ACPI_IO_PM1_TMR_TMR_VAL;
+ //
+ // Check if timer overflow
+ //
+ if ((CurrentTick < OriginalTick)) {
+ if (Counts != 0) {
+ Counts--;
+ } else {
+ //
+ // If timer overflow and Counts equ to 0, that means we already stalled more than
+ // RemainingTick, break the loop here
+ //
+ break;
+ }
+ }
+
+ OriginalTick = CurrentTick;
+ }
+}
+
+/**
+ Wait execution cycle to complete on the SPI interface.
+
+ @param[in] This The SPI protocol instance
+ @param[in] PchSpiBar0 Spi MMIO base address
+ @param[in] ErrorCheck TRUE if the SpiCycle needs to do the error check
+
+ @retval TRUE SPI cycle completed on the interface.
+ @retval FALSE Time out while waiting the SPI cycle to complete.
+ It's not safe to program the next command on the SPI interface.
+**/
+STATIC
+BOOLEAN
+WaitForSpiCycleComplete (
+ IN PCH_SPI_PROTOCOL *This,
+ IN UINTN PchSpiBar0,
+ IN BOOLEAN ErrorCheck
+ )
+{
+ UINT64 WaitTicks;
+ UINT64 WaitCount;
+ UINT32 Data32;
+ SPI_INSTANCE *SpiInstance;
+
+ SpiInstance = SPI_INSTANCE_FROM_SPIPROTOCOL (This);
+
+ //
+ // Convert the wait period allowed into to tick count
+ //
+ WaitCount = SPI_WAIT_TIME / SPI_WAIT_PERIOD;
+ //
+ // Wait for the SPI cycle to complete.
+ //
+ for (WaitTicks = 0; WaitTicks < WaitCount; WaitTicks++) {
+ Data32 = MmioRead32 (PchSpiBar0 + R_SPI_MEM_HSFSC);
+ if ((Data32 & B_SPI_MEM_HSFSC_SCIP) == 0) {
+ MmioWrite8 (PchSpiBar0 + R_SPI_MEM_HSFSC, B_SPI_MEM_HSFSC_FCERR | B_SPI_MEM_HSFSC_FDONE);
+ if (((Data32 & B_SPI_MEM_HSFSC_FCERR) != 0) && (ErrorCheck == TRUE)) {
+ return FALSE;
+ } else {
+ return TRUE;
+ }
+ }
+ PchPmTimerStallRuntimeSafe (SpiInstance->PchAcpiBase, SPI_WAIT_PERIOD);
+ }
+ return FALSE;
+}
+
+/**
+ This function waits for a pending SPI transaction to complete without clearing
+ status fields
+
+ @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
+ @param[in] PchSpiBar0 SPI MMIO address
+
+ @retval TRUE SPI cycle completed on the interface.
+ @retval FALSE Time out while waiting the SPI cycle to complete.
+ It's not safe to program the next command on the SPI interface.
+**/
+BOOLEAN
+STATIC
+WaitForScipNoClear (
+ IN PCH_SPI_PROTOCOL *This,
+ IN UINTN PchSpiBar0
+ )
+{
+ UINT64 WaitTicks;
+ UINT64 WaitCount;
+ SPI_INSTANCE *SpiInstance;
+ UINT32 Data32;
+
+ SpiInstance = SPI_INSTANCE_FROM_SPIPROTOCOL (This);
+
+ //
+ // Wait for the SPI cycle to complete.
+ //
+ WaitCount = SPI_WAIT_TIME / SPI_WAIT_PERIOD;
+ for (WaitTicks = 0; WaitTicks < WaitCount; WaitTicks++) {
+ Data32 = MmioRead32 (PchSpiBar0 + R_SPI_MEM_HSFSC);
+ if ((Data32 & B_SPI_MEM_HSFSC_SCIP) == 0) {
+ return TRUE;
+ }
+ PchPmTimerStallRuntimeSafe (SpiInstance->PchAcpiBase, SPI_WAIT_PERIOD);
+ }
+ return FALSE;
+}
+
+/**
+ This function sets the FDONE and optionally FCERR bits in the HSFS_CTL register
+
+ @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
+ @param[in] PchSpiBar0 SPI MMIO address
+ @param[in] SetErrorBit Set to TRUE to set the FCERR bit
+
+**/
+VOID
+STATIC
+SetHsfscFdone (
+ IN PCH_SPI_PROTOCOL *This,
+ IN UINTN PchSpiBar0,
+ IN BOOLEAN SetFcErrorBit
+ )
+{
+ EFI_STATUS Status;
+ UINT32 HardwareSpiAddr;
+ UINT32 FlashRegionSize;
+ UINT32 Index;
+ UINT8 DataCount;
+
+ Status = SpiProtocolGetRegionAddress (This, FlashRegionBios, &HardwareSpiAddr, &FlashRegionSize);
+ if (EFI_ERROR (Status)) {
+ return;
+ }
+
+ //
+ // Clear FDONE and FCERR
+ //
+ MmioWrite8 (PchSpiBar0 + R_SPI_MEM_HSFSC, B_SPI_MEM_HSFSC_FCERR | B_SPI_MEM_HSFSC_FDONE);
+
+ //
+ // Fill data buffer
+ //
+ if (SetFcErrorBit) {
+ for (Index = 0; Index < 64; Index += sizeof (UINT32)) {
+ MmioWrite32 (PchSpiBar0 + R_SPI_MEM_FDATA00 + Index, 0xFFFFFFFF);
+ }
+ }
+
+ //
+ // Set the Flash Address
+ //
+ MmioWrite32 (
+ (PchSpiBar0 + R_SPI_MEM_FADDR),
+ (UINT32) (HardwareSpiAddr & B_SPI_MEM_FADDR_MASK)
+ );
+ //
+ // Set Data count, Flash cycle, and Set Go bit to start a cycle
+ //
+ if (SetFcErrorBit) {
+ DataCount = 0x3F;
+ } else {
+ DataCount = 0;
+ }
+ MmioAndThenOr32 (
+ PchSpiBar0 + R_SPI_MEM_HSFSC,
+ (UINT32) (~(B_SPI_MEM_HSFSC_FDBC_MASK | B_SPI_MEM_HSFSC_CYCLE_MASK)),
+ (UINT32) (((DataCount << N_SPI_MEM_HSFSC_FDBC) & B_SPI_MEM_HSFSC_FDBC_MASK) |
+ (V_SPI_MEM_HSFSC_CYCLE_READ << N_SPI_MEM_HSFSC_CYCLE) |
+ B_SPI_MEM_HSFSC_CYCLE_FGO)
+ );
+
+ if (SetFcErrorBit) {
+ //
+ // Intentionally write to FDATA while a cycle is in progress to generate an error
+ //
+ for (Index = 0; Index < 64; Index += sizeof (UINT32)) {
+ MmioWrite32 (PchSpiBar0 + R_SPI_MEM_FDATA00 + Index, 0x0);
+ }
+ }
+
+ WaitForScipNoClear (This, PchSpiBar0);
+}
+
+/**
+ This function sends the programmed SPI command to the device.
+
+ @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
+ @param[in] SpiRegionType The SPI Region type for flash cycle which is listed in the Descriptor
+ @param[in] FlashCycleType The Flash SPI cycle type list in HSFC (Hardware Sequencing Flash Control Register) register
+ @param[in] Address The Flash Linear Address must fall within a region for which BIOS has access permissions.
+ @param[in] ByteCount Number of bytes in the data portion of the SPI cycle.
+ @param[in,out] Buffer Pointer to caller-allocated buffer containing the dada received or sent during the SPI cycle.
+
+ @retval EFI_SUCCESS SPI command completes successfully.
+ @retval EFI_DEVICE_ERROR Device error, the command aborts abnormally.
+ @retval EFI_ACCESS_DENIED Some unrecognized or blocked command encountered in hardware sequencing mode
+ @retval EFI_INVALID_PARAMETER The parameters specified are not valid.
+**/
+STATIC
+EFI_STATUS
+SendSpiCmd (
+ IN PCH_SPI_PROTOCOL *This,
+ IN FLASH_REGION_TYPE FlashRegionType,
+ IN FLASH_CYCLE_TYPE FlashCycleType,
+ IN UINT32 Address,
+ IN UINT32 ByteCount,
+ IN OUT UINT8 *Buffer
+ )
+{
+ UINT32 FdataSave[16];
+ EFI_STATUS Status;
+ UINT32 Index;
+ SPI_INSTANCE *SpiInstance;
+ UINT64 SpiBaseAddress;
+ UINTN PchSpiBar0;
+ UINT32 HardwareSpiAddr;
+ UINT32 FlashRegionSize;
+ UINT32 SpiDataCount;
+ UINT32 FlashCycle;
+ UINT8 BiosCtlSave;
+ UINT32 SmiEnSave;
+ UINT16 ABase;
+ UINT32 HsfstsCtl;
+ UINT32 FaddrSave;
+ UINT32 HsfscSave;
+ BOOLEAN HsfscFdoneSave;
+ BOOLEAN HsfscFcerrSave;
+ BOOLEAN RestoreState;
+
+ //
+ // For flash write, there is a requirement that all CPU threads are in SMM
+ // before the flash protection is disabled.
+ //
+ if ((FlashCycleType == FlashCycleWrite) || (FlashCycleType == FlashCycleErase)) {
+ if (!IsSpiFlashWriteGranted ()) {
+ return EFI_ACCESS_DENIED;
+ }
+ }
+
+ Status = EFI_SUCCESS;
+ SpiInstance = SPI_INSTANCE_FROM_SPIPROTOCOL (This);
+ SpiBaseAddress = SpiInstance->PchSpiBase;
+ ABase = SpiInstance->PchAcpiBase;
+ RestoreState = FALSE;
+
+ //
+ // Disable SMIs to make sure normal mode flash access is not interrupted by an SMI
+ // whose SMI handler accesses flash (e.g. for error logging)
+ //
+ // *** NOTE: if the SMI_LOCK bit is set (i.e., PMC PCI Offset A0h [4]='1'),
+ // clearing B_GBL_SMI_EN will not have effect. In this situation, some other
+ // synchronization methods must be applied here or in the consumer of the
+ // SendSpiCmd. An example method is disabling the specific SMI sources
+ // whose SMI handlers access flash before flash cycle and re-enabling the SMI
+ // sources after the flash cycle .
+ //
+ SmiEnSave = IoRead32 ((UINTN) (ABase + R_ACPI_IO_SMI_EN));
+ IoWrite32 ((UINTN) (ABase + R_ACPI_IO_SMI_EN), SmiEnSave & (UINT32) (~B_ACPI_IO_SMI_EN_GBL_SMI));
+ BiosCtlSave = PciSegmentRead8 (SpiBaseAddress + R_SPI_CFG_BC) & B_SPI_CFG_BC_SRC;
+
+ //
+ // Acquire SPI BAR0
+ //
+ PchSpiBar0 = AcquireSpiBar0 (SpiInstance);
+
+ //
+ // If it's write cycle, disable Prefetching, Caching and disable BIOS Write Protect
+ //
+ if ((FlashCycleType == FlashCycleWrite) ||
+ (FlashCycleType == FlashCycleErase)) {
+ Status = DisableBiosWriteProtect ();
+ if (EFI_ERROR (Status)) {
+ goto SendSpiCmdEnd;
+ }
+ PciSegmentAndThenOr8 (
+ SpiBaseAddress + R_SPI_CFG_BC,
+ (UINT8) (~B_SPI_CFG_BC_SRC),
+ (UINT8) (V_SPI_CFG_BC_SRC_PREF_DIS_CACHE_DIS << N_SPI_CFG_BC_SRC)
+ );
+ }
+
+ //
+ // Save current SPI controller state
+ //
+ if (IsSpiControllerSaveRestoreEnabled ()) {
+ if (!WaitForScipNoClear (This, PchSpiBar0)) {
+ Status = EFI_DEVICE_ERROR;
+ goto SendSpiCmdEnd;
+ }
+ HsfscSave = MmioRead32 (PchSpiBar0 + R_SPI_MEM_HSFSC);
+ HsfscFdoneSave = ((HsfscSave & B_SPI_MEM_HSFSC_FDONE) != 0) ? TRUE : FALSE;
+ HsfscFcerrSave = ((HsfscSave & B_SPI_MEM_HSFSC_FCERR) != 0) ? TRUE : FALSE;
+ HsfscSave &= B_SPI_MEM_HSFSC_SAVE_MASK;
+ FaddrSave = MmioRead32 (PchSpiBar0 + R_SPI_MEM_FADDR);
+ for (Index = 0; Index < 64; Index += sizeof (UINT32)) {
+ FdataSave[Index >> 2] = MmioRead32 (PchSpiBar0 + R_SPI_MEM_FDATA00 + Index);
+ }
+ RestoreState = TRUE;
+ }
+
+ //
+ // Make sure it's safe to program the command.
+ //
+ if (!WaitForSpiCycleComplete (This, PchSpiBar0, FALSE)) {
+ Status = EFI_DEVICE_ERROR;
+ goto SendSpiCmdEnd;
+ }
+
+ //
+ // Check if Write Status isn't disabled in HW Sequencing
+ //
+ if (FlashCycleType == FlashCycleWriteStatus) {
+ HsfstsCtl = MmioRead32 (PchSpiBar0 + R_SPI_MEM_HSFSC);
+ if ((HsfstsCtl & B_SPI_MEM_HSFSC_WRSDIS) != 0) {
+ Status = EFI_ACCESS_DENIED;
+ goto SendSpiCmdEnd;
+ }
+ }
+
+ Status = SpiProtocolGetRegionAddress (This, FlashRegionType, &HardwareSpiAddr, &FlashRegionSize);
+ if (EFI_ERROR (Status)) {
+ goto SendSpiCmdEnd;
+ }
+ HardwareSpiAddr += Address;
+ if ((Address + ByteCount) > FlashRegionSize) {
+ Status = EFI_INVALID_PARAMETER;
+ goto SendSpiCmdEnd;
+ }
+
+ //
+ // Check for PCH SPI hardware sequencing required commands
+ //
+ FlashCycle = 0;
+ switch (FlashCycleType) {
+ case FlashCycleRead:
+ FlashCycle = (UINT32) (V_SPI_MEM_HSFSC_CYCLE_READ << N_SPI_MEM_HSFSC_CYCLE);
+ break;
+ case FlashCycleWrite:
+ FlashCycle = (UINT32) (V_SPI_MEM_HSFSC_CYCLE_WRITE << N_SPI_MEM_HSFSC_CYCLE);
+ break;
+ case FlashCycleErase:
+ if (((ByteCount % SIZE_4KB) != 0) ||
+ ((HardwareSpiAddr % SIZE_4KB) != 0)) {
+ ASSERT (FALSE);
+ Status = EFI_INVALID_PARAMETER;
+ goto SendSpiCmdEnd;
+ }
+ break;
+ case FlashCycleReadSfdp:
+ FlashCycle = (UINT32) (V_SPI_MEM_HSFSC_CYCLE_READ_SFDP << N_SPI_MEM_HSFSC_CYCLE);
+ break;
+ case FlashCycleReadJedecId:
+ FlashCycle = (UINT32) (V_SPI_MEM_HSFSC_CYCLE_READ_JEDEC_ID << N_SPI_MEM_HSFSC_CYCLE);
+ break;
+ case FlashCycleWriteStatus:
+ FlashCycle = (UINT32) (V_SPI_MEM_HSFSC_CYCLE_WRITE_STATUS << N_SPI_MEM_HSFSC_CYCLE);
+ break;
+ case FlashCycleReadStatus:
+ FlashCycle = (UINT32) (V_SPI_MEM_HSFSC_CYCLE_READ_STATUS << N_SPI_MEM_HSFSC_CYCLE);
+ break;
+ default:
+ //
+ // Unrecognized Operation
+ //
+ ASSERT (FALSE);
+ Status = EFI_INVALID_PARAMETER;
+ goto SendSpiCmdEnd;
+ break;
+ }
+
+ do {
+ SpiDataCount = ByteCount;
+ if ((FlashCycleType == FlashCycleRead) ||
+ (FlashCycleType == FlashCycleWrite) ||
+ (FlashCycleType == FlashCycleReadSfdp)) {
+ //
+ // Trim at 256 byte boundary per operation,
+ // - PCH SPI controller requires trimming at 4KB boundary
+ // - Some SPI chips require trimming at 256 byte boundary for write operation
+ // - Trimming has limited performance impact as we can read / write at most 64 bytes
+ // per operation
+ //
+ if (HardwareSpiAddr + ByteCount > ((HardwareSpiAddr + BIT8) &~(BIT8 - 1))) {
+ SpiDataCount = (((UINT32) (HardwareSpiAddr) + BIT8) &~(BIT8 - 1)) - (UINT32) (HardwareSpiAddr);
+ }
+ //
+ // Calculate the number of bytes to shift in/out during the SPI data cycle.
+ // Valid settings for the number of bytes during each data portion of the
+ // PCH SPI cycles are: 0, 1, 2, 3, 4, 5, 6, 7, 8, 16, 24, 32, 40, 48, 56, 64
+ //
+ if (SpiDataCount >= 64) {
+ SpiDataCount = 64;
+ } else if ((SpiDataCount &~0x07) != 0) {
+ SpiDataCount = SpiDataCount &~0x07;
+ }
+ }
+ if (FlashCycleType == FlashCycleErase) {
+ if (((ByteCount / SIZE_64KB) != 0) &&
+ ((ByteCount % SIZE_64KB) == 0) &&
+ ((HardwareSpiAddr % SIZE_64KB) == 0)) {
+ if ((SpiInstance->NumberOfComponents == 0) ||
+ (HardwareSpiAddr < SpiInstance->Component1StartAddr)) {
+ //
+ // Check whether Component0 support 64k Erase
+ //
+ if ((SpiInstance->SfdpVscc0Value & B_SPI_MEM_SFDPX_VSCCX_EO_64K) != 0) {
+ SpiDataCount = SIZE_64KB;
+ } else {
+ SpiDataCount = SIZE_4KB;
+ }
+ } else {
+ //
+ // Check whether Component1 support 64k Erase
+ //
+ if ((SpiInstance->SfdpVscc1Value & B_SPI_MEM_SFDPX_VSCCX_EO_64K) != 0) {
+ SpiDataCount = SIZE_64KB;
+ } else {
+ SpiDataCount = SIZE_4KB;
+ }
+ }
+ } else {
+ SpiDataCount = SIZE_4KB;
+ }
+ if (SpiDataCount == SIZE_4KB) {
+ FlashCycle = (UINT32) (V_SPI_MEM_HSFSC_CYCLE_4K_ERASE << N_SPI_MEM_HSFSC_CYCLE);
+ } else {
+ FlashCycle = (UINT32) (V_SPI_MEM_HSFSC_CYCLE_64K_ERASE << N_SPI_MEM_HSFSC_CYCLE);
+ }
+ }
+ //
+ // If it's write cycle, load data into the SPI data buffer.
+ //
+ if ((FlashCycleType == FlashCycleWrite) || (FlashCycleType == FlashCycleWriteStatus)) {
+ if ((SpiDataCount & 0x07) != 0) {
+ //
+ // Use Byte write if Data Count is 0, 1, 2, 3, 4, 5, 6, 7
+ //
+ for (Index = 0; Index < SpiDataCount; Index++) {
+ MmioWrite8 (PchSpiBar0 + R_SPI_MEM_FDATA00 + Index, Buffer[Index]);
+ }
+ } else {
+ //
+ // Use Dword write if Data Count is 8, 16, 24, 32, 40, 48, 56, 64
+ //
+ for (Index = 0; Index < SpiDataCount; Index += sizeof (UINT32)) {
+ MmioWrite32 (PchSpiBar0 + R_SPI_MEM_FDATA00 + Index, *(UINT32 *) (Buffer + Index));
+ }
+ }
+ }
+
+ //
+ // Set the Flash Address
+ //
+ MmioWrite32 (
+ (PchSpiBar0 + R_SPI_MEM_FADDR),
+ (UINT32) (HardwareSpiAddr & B_SPI_MEM_FADDR_MASK)
+ );
+
+ //
+ // Set Data count, Flash cycle, and Set Go bit to start a cycle
+ //
+ MmioAndThenOr32 (
+ PchSpiBar0 + R_SPI_MEM_HSFSC,
+ (UINT32) (~(B_SPI_MEM_HSFSC_FDBC_MASK | B_SPI_MEM_HSFSC_CYCLE_MASK)),
+ (UINT32) ((((SpiDataCount - 1) << N_SPI_MEM_HSFSC_FDBC) & B_SPI_MEM_HSFSC_FDBC_MASK) | FlashCycle | B_SPI_MEM_HSFSC_CYCLE_FGO)
+ );
+ //
+ // end of command execution
+ //
+ // Wait the SPI cycle to complete.
+ //
+ if (!WaitForSpiCycleComplete (This, PchSpiBar0, TRUE)) {
+ ASSERT (FALSE);
+ Status = EFI_DEVICE_ERROR;
+ goto SendSpiCmdEnd;
+ }
+ //
+ // If it's read cycle, load data into the call's buffer.
+ //
+ if ((FlashCycleType == FlashCycleRead) ||
+ (FlashCycleType == FlashCycleReadSfdp) ||
+ (FlashCycleType == FlashCycleReadJedecId) ||
+ (FlashCycleType == FlashCycleReadStatus)) {
+ if ((SpiDataCount & 0x07) != 0) {
+ //
+ // Use Byte read if Data Count is 0, 1, 2, 3, 4, 5, 6, 7
+ //
+ for (Index = 0; Index < SpiDataCount; Index++) {
+ Buffer[Index] = MmioRead8 (PchSpiBar0 + R_SPI_MEM_FDATA00 + Index);
+ }
+ } else {
+ //
+ // Use Dword read if Data Count is 8, 16, 24, 32, 40, 48, 56, 64
+ //
+ for (Index = 0; Index < SpiDataCount; Index += sizeof (UINT32)) {
+ *(UINT32 *) (Buffer + Index) = MmioRead32 (PchSpiBar0 + R_SPI_MEM_FDATA00 + Index);
+ }
+ }
+ }
+
+ HardwareSpiAddr += SpiDataCount;
+ Buffer += SpiDataCount;
+ ByteCount -= SpiDataCount;
+ } while (ByteCount > 0);
+
+SendSpiCmdEnd:
+ //
+ // Restore SPI controller state
+ //
+ if (RestoreState) {
+ if (HsfscFdoneSave) {
+ SetHsfscFdone (This, PchSpiBar0, HsfscFcerrSave);
+ }
+ MmioAndThenOr32 (
+ PchSpiBar0 + R_SPI_MEM_HSFSC,
+ (UINT32) ~(B_SPI_MEM_HSFSC_SAVE_MASK |
+ B_SPI_MEM_HSFSC_SAF_CE | // This bit clears when set to 1, ensure 0 is written
+ B_SPI_MEM_HSFSC_SAF_LE | // This bit clears when set to 1, ensure 0 is written
+ B_SPI_MEM_HSFSC_SAF_DLE | // This bit clears when set to 1, ensure 0 is written
+ B_SPI_MEM_HSFSC_SAF_ERROR | // This bit clears when set to 1, ensure 0 is written
+ B_SPI_MEM_HSFSC_AEL | // This bit clears when set to 1, ensure 0 is written
+ B_SPI_MEM_HSFSC_FCERR | // This bit clears when set to 1, ensure 0 is written
+ B_SPI_MEM_HSFSC_FDONE), // This bit clears when set to 1, ensure 0 is written
+ HsfscSave
+ );
+ MmioWrite32 (PchSpiBar0 + R_SPI_MEM_FADDR, FaddrSave);
+ for (Index = 0; Index < 64; Index += sizeof (UINT32)) {
+ MmioWrite32 (PchSpiBar0 + R_SPI_MEM_FDATA00 + Index, FdataSave[Index >> 2]);
+ }
+ }
+
+ //
+ // Restore the settings for SPI Prefetching and Caching and enable BIOS Write Protect
+ //
+ if ((FlashCycleType == FlashCycleWrite) ||
+ (FlashCycleType == FlashCycleErase)) {
+ EnableBiosWriteProtect ();
+ PciSegmentAndThenOr8 (
+ SpiBaseAddress + R_SPI_CFG_BC,
+ (UINT8) ~B_SPI_CFG_BC_SRC,
+ BiosCtlSave
+ );
+ }
+ ReleaseSpiBar0 (SpiInstance);
+
+ //
+ // Restore SMIs.
+ //
+ IoWrite32 ((UINTN) (ABase + R_ACPI_IO_SMI_EN), SmiEnSave);
+
+ return Status;
+}
+
+/**
+ Read data from the flash part.
+
+ @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
+ @param[in] FlashRegionType The Flash Region type for flash cycle which is listed in the Descriptor.
+ @param[in] Address The Flash Linear Address must fall within a region for which BIOS has access permissions.
+ @param[in] ByteCount Number of bytes in the data portion of the SPI cycle.
+ @param[out] Buffer The Pointer to caller-allocated buffer containing the dada received.
+ It is the caller's responsibility to make sure Buffer is large enough for the total number of bytes read.
+
+ @retval EFI_SUCCESS Command succeed.
+ @retval EFI_INVALID_PARAMETER The parameters specified are not valid.
+ @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
+**/
+EFI_STATUS
+EFIAPI
+SpiProtocolFlashRead (
+ IN PCH_SPI_PROTOCOL *This,
+ IN FLASH_REGION_TYPE FlashRegionType,
+ IN UINT32 Address,
+ IN UINT32 ByteCount,
+ OUT UINT8 *Buffer
+ )
+{
+ EFI_STATUS Status;
+
+ //
+ // Sends the command to the SPI interface to execute.
+ //
+ Status = SendSpiCmd (
+ This,
+ FlashRegionType,
+ FlashCycleRead,
+ Address,
+ ByteCount,
+ Buffer
+ );
+ return Status;
+}
+
+/**
+ Write data to the flash part.
+
+ @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
+ @param[in] FlashRegionType The Flash Region type for flash cycle which is listed in the Descriptor.
+ @param[in] Address The Flash Linear Address must fall within a region for which BIOS has access permissions.
+ @param[in] ByteCount Number of bytes in the data portion of the SPI cycle.
+ @param[in] Buffer Pointer to caller-allocated buffer containing the data sent during the SPI cycle.
+
+ @retval EFI_SUCCESS Command succeed.
+ @retval EFI_INVALID_PARAMETER The parameters specified are not valid.
+ @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
+**/
+EFI_STATUS
+EFIAPI
+SpiProtocolFlashWrite (
+ IN PCH_SPI_PROTOCOL *This,
+ IN FLASH_REGION_TYPE FlashRegionType,
+ IN UINT32 Address,
+ IN UINT32 ByteCount,
+ IN UINT8 *Buffer
+ )
+{
+ EFI_STATUS Status;
+
+ //
+ // Sends the command to the SPI interface to execute.
+ //
+ Status = SendSpiCmd (
+ This,
+ FlashRegionType,
+ FlashCycleWrite,
+ Address,
+ ByteCount,
+ Buffer
+ );
+ return Status;
+}
+
+/**
+ Erase some area on the flash part.
+
+ @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
+ @param[in] FlashRegionType The Flash Region type for flash cycle which is listed in the Descriptor.
+ @param[in] Address The Flash Linear Address must fall within a region for which BIOS has access permissions.
+ @param[in] ByteCount Number of bytes in the data portion of the SPI cycle.
+
+ @retval EFI_SUCCESS Command succeed.
+ @retval EFI_INVALID_PARAMETER The parameters specified are not valid.
+ @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
+**/
+EFI_STATUS
+EFIAPI
+SpiProtocolFlashErase (
+ IN PCH_SPI_PROTOCOL *This,
+ IN FLASH_REGION_TYPE FlashRegionType,
+ IN UINT32 Address,
+ IN UINT32 ByteCount
+ )
+{
+ EFI_STATUS Status;
+
+ //
+ // Sends the command to the SPI interface to execute.
+ //
+ Status = SendSpiCmd (
+ This,
+ FlashRegionType,
+ FlashCycleErase,
+ Address,
+ ByteCount,
+ NULL
+ );
+ return Status;
+}
+
+/**
+ Read SFDP data from the flash part.
+
+ @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
+ @param[in] ComponentNumber The Componen Number for chip select
+ @param[in] Address The starting byte address for SFDP data read.
+ @param[in] ByteCount Number of bytes in SFDP data portion of the SPI cycle
+ @param[out] SfdpData The Pointer to caller-allocated buffer containing the SFDP data received
+ It is the caller's responsibility to make sure Buffer is large enough for the total number of bytes read
+
+ @retval EFI_SUCCESS Command succeed.
+ @retval EFI_INVALID_PARAMETER The parameters specified are not valid.
+ @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
+ @retval EFI_UNSUPPORTED Unsupported operation with SAF Mode enabled
+**/
+EFI_STATUS
+EFIAPI
+SpiProtocolFlashReadSfdp (
+ IN PCH_SPI_PROTOCOL *This,
+ IN UINT8 ComponentNumber,
+ IN UINT32 Address,
+ IN UINT32 ByteCount,
+ OUT UINT8 *SfdpData
+ )
+{
+ return EFI_SUCCESS;
+}
+
+/**
+ Read Jedec Id from the flash part.
+
+ @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
+ @param[in] ComponentNumber The Componen Number for chip select
+ @param[in] ByteCount Number of bytes in JedecId data portion of the SPI cycle, the data size is 3 typically
+ @param[out] JedecId The Pointer to caller-allocated buffer containing JEDEC ID received
+ It is the caller's responsibility to make sure Buffer is large enough for the total number of bytes read.
+
+ @retval EFI_SUCCESS Command succeed.
+ @retval EFI_INVALID_PARAMETER The parameters specified are not valid.
+ @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
+ @retval EFI_UNSUPPORTED Unsupported operation with SAF Mode enabled
+**/
+EFI_STATUS
+EFIAPI
+SpiProtocolFlashReadJedecId (
+ IN PCH_SPI_PROTOCOL *This,
+ IN UINT8 ComponentNumber,
+ IN UINT32 ByteCount,
+ OUT UINT8 *JedecId
+ )
+{
+ return EFI_SUCCESS;
+}
+
+/**
+ Write the status register in the flash part.
+
+ @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
+ @param[in] ByteCount Number of bytes in Status data portion of the SPI cycle, the data size is 1 typically
+ @param[in] StatusValue The Pointer to caller-allocated buffer containing the value of Status register writing
+
+ @retval EFI_SUCCESS Command succeed.
+ @retval EFI_INVALID_PARAMETER The parameters specified are not valid.
+ @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
+ @retval EFI_UNSUPPORTED Unsupported operation with SAF Mode enabled
+**/
+EFI_STATUS
+EFIAPI
+SpiProtocolFlashWriteStatus (
+ IN PCH_SPI_PROTOCOL *This,
+ IN UINT32 ByteCount,
+ IN UINT8 *StatusValue
+ )
+{
+ return EFI_SUCCESS;
+}
+
+/**
+ Read status register in the flash part.
+
+ @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
+ @param[in] ByteCount Number of bytes in Status data portion of the SPI cycle, the data size is 1 typically
+ @param[out] StatusValue The Pointer to caller-allocated buffer containing the value of Status register received.
+
+ @retval EFI_SUCCESS Command succeed.
+ @retval EFI_INVALID_PARAMETER The parameters specified are not valid.
+ @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
+ @retval EFI_UNSUPPORTED Unsupported operation with SAF Mode enabled
+**/
+EFI_STATUS
+EFIAPI
+SpiProtocolFlashReadStatus (
+ IN PCH_SPI_PROTOCOL *This,
+ IN UINT32 ByteCount,
+ OUT UINT8 *StatusValue
+ )
+{
+ return EFI_SUCCESS;
+}
+
+/**
+ Get the SPI region base and size, based on the enum type
+
+ @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
+ @param[in] FlashRegionType The Flash Region type for for the base address which is listed in the Descriptor.
+ @param[out] BaseAddress The Flash Linear Address for the Region 'n' Base
+ @param[out] RegionSize The size for the Region 'n'
+
+ @retval EFI_SUCCESS Read success
+ @retval EFI_INVALID_PARAMETER Invalid region type given
+ @retval EFI_DEVICE_ERROR The region is not used
+**/
+EFI_STATUS
+EFIAPI
+SpiProtocolGetRegionAddress (
+ IN PCH_SPI_PROTOCOL *This,
+ IN FLASH_REGION_TYPE FlashRegionType,
+ OUT UINT32 *BaseAddress,
+ OUT UINT32 *RegionSize
+ )
+{
+ SPI_INSTANCE *SpiInstance;
+ UINTN PchSpiBar0;
+ UINT32 ReadValue;
+
+ SpiInstance = SPI_INSTANCE_FROM_SPIPROTOCOL (This);
+
+ if (FlashRegionType >= FlashRegionMax) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ if (FlashRegionType == FlashRegionAll) {
+ *BaseAddress = 0;
+ *RegionSize = SpiInstance->TotalFlashSize;
+ return EFI_SUCCESS;
+ }
+
+ PchSpiBar0 = AcquireSpiBar0 (SpiInstance);
+
+ ReadValue = MmioRead32 (PchSpiBar0 + (R_SPI_MEM_FREG0_FLASHD + (S_SPI_MEM_FREGX * ((UINT32) FlashRegionType))));
+
+ ReleaseSpiBar0 (SpiInstance);
+
+ //
+ // If the region is not used, the Region Base is 7FFFh and Region Limit is 0000h
+ //
+ if (ReadValue == B_SPI_MEM_FREGX_BASE_MASK) {
+ return EFI_DEVICE_ERROR;
+ }
+ *BaseAddress = ((ReadValue & B_SPI_MEM_FREGX_BASE_MASK) >> N_SPI_MEM_FREGX_BASE) <<
+ N_SPI_MEM_FREGX_BASE_REPR;
+ //
+ // Region limit address Bits[11:0] are assumed to be FFFh
+ //
+ *RegionSize = ((((ReadValue & B_SPI_MEM_FREGX_LIMIT_MASK) >> N_SPI_MEM_FREGX_LIMIT) + 1) <<
+ N_SPI_MEM_FREGX_LIMIT_REPR) - *BaseAddress;
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Read PCH Soft Strap Values
+
+ @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
+ @param[in] SoftStrapAddr PCH Soft Strap address offset from FPSBA.
+ @param[in] ByteCount Number of bytes in SoftStrap data portion of the SPI cycle
+ @param[out] SoftStrapValue The Pointer to caller-allocated buffer containing PCH Soft Strap Value.
+ If the value of ByteCount is 0, the data type of SoftStrapValue should be UINT16 and SoftStrapValue will be PCH Soft Strap Length
+ It is the caller's responsibility to make sure Buffer is large enough for the total number of bytes read.
+
+ @retval EFI_SUCCESS Command succeed.
+ @retval EFI_INVALID_PARAMETER The parameters specified are not valid.
+ @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
+**/
+EFI_STATUS
+EFIAPI
+SpiProtocolReadPchSoftStrap (
+ IN PCH_SPI_PROTOCOL *This,
+ IN UINT32 SoftStrapAddr,
+ IN UINT32 ByteCount,
+ OUT VOID *SoftStrapValue
+ )
+{
+ return EFI_SUCCESS;
+}
+
+/**
+ Read CPU Soft Strap Values
+
+ @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
+ @param[in] SoftStrapAddr CPU Soft Strap address offset from FCPUSBA.
+ @param[in] ByteCount Number of bytes in SoftStrap data portion of the SPI cycle.
+ @param[out] SoftStrapValue The Pointer to caller-allocated buffer containing CPU Soft Strap Value.
+ If the value of ByteCount is 0, the data type of SoftStrapValue should be UINT16 and SoftStrapValue will be PCH Soft Strap Length
+ It is the caller's responsibility to make sure Buffer is large enough for the total number of bytes read.
+
+ @retval EFI_SUCCESS Command succeed.
+ @retval EFI_INVALID_PARAMETER The parameters specified are not valid.
+ @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
+**/
+EFI_STATUS
+EFIAPI
+SpiProtocolReadCpuSoftStrap (
+ IN PCH_SPI_PROTOCOL *This,
+ IN UINT32 SoftStrapAddr,
+ IN UINT32 ByteCount,
+ OUT VOID *SoftStrapValue
+ )
+{
+ return EFI_SUCCESS;
+}
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/Smm/Spi.c b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/Smm/Spi.c
new file mode 100644
index 0000000000..2dd80eba7c
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/Smm/Spi.c
@@ -0,0 +1,387 @@
+/** @file
+ PCH SPI SMM Driver implements the SPI Host Controller Compatibility Interface.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <Library/IoLib.h>
+#include <Library/DebugLib.h>
+#include <Library/UefiDriverEntryPoint.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/BaseLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/SmmServicesTableLib.h>
+#include <Library/PciSegmentLib.h>
+#include <Protocol/Spi.h>
+#include <Protocol/SmmCpu.h>
+#include <Library/SpiCommonLib.h>
+#include <PchReservedResources.h>
+#include <Library/PchPciBdfLib.h>
+#include <IndustryStandard/Pci30.h>
+#include <Register/PchRegs.h>
+#include <Register/SpiRegs.h>
+
+//
+// Global variables
+//
+GLOBAL_REMOVE_IF_UNREFERENCED SPI_INSTANCE *mSpiInstance;
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_SMM_CPU_PROTOCOL *mSmmCpuProtocol;
+//
+// mPchSpiResvMmioAddr keeps the reserved MMIO range assigned to SPI.
+// In SMM it always set back the reserved MMIO address to SPI BAR0 to ensure the MMIO range
+// won't overlap with SMRAM range, and trusted.
+//
+GLOBAL_REMOVE_IF_UNREFERENCED UINT32 mSpiResvMmioAddr;
+//
+// mPchSpiSavedMmioAddr keeps the MMIO range assigned to SPI by PCI enumeration.
+// In SMM this is used to restore the original value for SPI BAR0 after finishing
+// commands to the SPI controller.
+//
+GLOBAL_REMOVE_IF_UNREFERENCED UINT32 mSpiSavedMmioAddr;
+//
+// mPchSpiBar0RefCount stores the reference count for SPI BAR0.
+//
+GLOBAL_REMOVE_IF_UNREFERENCED UINT32 mPchSpiBar0RefCount;
+//
+// mPchSpiSavedPciCmdReg stores the PCI command register state at the start of the
+// SPI transaction. This is used to restore the original PCI command register
+// state after finishing commands to the SPI controller.
+//
+GLOBAL_REMOVE_IF_UNREFERENCED UINT8 mPchSpiSavedPciCmdReg;
+GLOBAL_REMOVE_IF_UNREFERENCED BOOLEAN mBootServiceExited;
+
+/**
+ This function is invoked at ExitBootServices()
+
+ @param[in] Protocol Protocol unique ID.
+ @param[in] Interface Interface instance.
+ @param[in] Handle The handle on which the interface is installed..
+
+ @retval Status.
+**/
+EFI_STATUS
+EFIAPI
+SpiExitBootServicesCallback (
+ IN CONST EFI_GUID *Protocol,
+ IN VOID *Interface,
+ IN EFI_HANDLE Handle
+ )
+{
+ mBootServiceExited = TRUE;
+ return EFI_SUCCESS;
+}
+
+/**
+ <b>SPI Runtime SMM Module Entry Point</b>\n
+ - <b>Introduction</b>\n
+ The SPI SMM module provide a standard way for other modules to use the PCH SPI Interface in SMM.
+
+ - @pre
+ - EFI_SMM_BASE2_PROTOCOL
+ - Documented in System Management Mode Core Interface Specification .
+
+ - @result
+ The SPI SMM driver produces @link _PCH_SPI_PROTOCOL PCH_SPI_PROTOCOL @endlink with GUID
+ gPchSmmSpiProtocolGuid which is different from SPI RUNTIME driver.
+
+ - <b>Integration Check List</b>\n
+ - This driver supports Descriptor Mode only.
+ - This driver supports Hardware Sequence only.
+ - When using SMM SPI Protocol to perform flash access in an SMI handler,
+ and the SMI occurrence is asynchronous to normal mode code execution,
+ proper synchronization mechanism must be applied, e.g. disable SMI before
+ the normal mode SendSpiCmd() starts and re-enable SMI after
+ the normal mode SendSpiCmd() completes.
+ @note The implementation of SendSpiCmd() uses GBL_SMI_EN in
+ SMI_EN register (ABase + 30h) to disable and enable SMIs. But this may
+ not be effective as platform may well set the SMI_LOCK bit (i.e., PMC PCI Offset A0h [4]).
+ So the synchronization at caller level is likely needed.
+
+ @param[in] ImageHandle Image handle of this driver.
+ @param[in] SystemTable Global system service table.
+
+ @retval EFI_SUCCESS Initialization complete.
+ @exception EFI_UNSUPPORTED The chipset is unsupported by this driver.
+ @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize the driver.
+ @retval EFI_DEVICE_ERROR Device error, driver exits abnormally.
+**/
+EFI_STATUS
+EFIAPI
+InstallPchSpi (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUS Status;
+ VOID *Registration;
+
+ //
+ // Init PCH spi reserved MMIO address.
+ //
+ mSpiResvMmioAddr = PCH_SPI_BASE_ADDRESS;
+ mSpiSavedMmioAddr = 0;
+ mPchSpiBar0RefCount = 0;
+ mPchSpiSavedPciCmdReg = 0;
+ mBootServiceExited = FALSE;
+
+ ///
+ /// Allocate pool for SPI protocol instance
+ ///
+ Status = gSmst->SmmAllocatePool (
+ EfiRuntimeServicesData, /// MemoryType don't care
+ sizeof (SPI_INSTANCE),
+ (VOID **) &mSpiInstance
+ );
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ if (mSpiInstance == NULL) {
+ return EFI_OUT_OF_RESOURCES;
+ }
+
+ ZeroMem ((VOID *) mSpiInstance, sizeof (SPI_INSTANCE));
+ ///
+ /// Initialize the SPI protocol instance
+ ///
+ Status = SpiProtocolConstructor (mSpiInstance);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ //
+ // Register ExitBootServices callback
+ //
+ Status = gSmst->SmmRegisterProtocolNotify (
+ &gEdkiiSmmExitBootServicesProtocolGuid,
+ SpiExitBootServicesCallback,
+ &Registration
+ );
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ //
+ // Install the SMM PCH_SPI_PROTOCOL interface
+ //
+ Status = gSmst->SmmInstallProtocolInterface (
+ &(mSpiInstance->Handle),
+ &gPchSmmSpiProtocolGuid,
+ EFI_NATIVE_INTERFACE,
+ &(mSpiInstance->SpiProtocol)
+ );
+ if (EFI_ERROR (Status)) {
+ gSmst->SmmFreePool (mSpiInstance);
+ return EFI_DEVICE_ERROR;
+ }
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Acquire PCH SPI MMIO address.
+ It is not expected for this BAR0 to change because the SPI device is usually
+ hidden from the OS. But if it is ever different from the preallocated address,
+ reassign it back. In SMM, BAR0 will always be overwritten and the reserved
+ MMIO range for SPI will be returned.
+
+ @param[in] SpiInstance Pointer to SpiInstance to initialize
+
+ @retval PchSpiBar0 return SPI MMIO address
+**/
+UINTN
+AcquireSpiBar0 (
+ IN SPI_INSTANCE *SpiInstance
+ )
+{
+ UINT32 SpiBar0;
+ UINT8 PciCmdReg;
+
+ //
+ // Save original SPI physical MMIO address
+ //
+ SpiBar0 = PciSegmentRead32 (SpiInstance->PchSpiBase + R_SPI_CFG_BAR0) & ~(B_SPI_CFG_BAR0_MASK);
+ PciCmdReg = PciSegmentRead8 (SpiInstance->PchSpiBase + PCI_COMMAND_OFFSET);
+
+ if ((SpiBar0 != mSpiResvMmioAddr) || ((PciCmdReg & EFI_PCI_COMMAND_MEMORY_SPACE) == 0)) {
+ //
+ // Save PCI command register state and BAR value assigned by PCI enumeration
+ //
+ mPchSpiSavedPciCmdReg = PciCmdReg;
+ mSpiSavedMmioAddr = SpiBar0;
+
+ //
+ // Temporary disable MSE, and override with SPI reserved MMIO address, then enable MSE.
+ //
+ PciSegmentAnd8 (SpiInstance->PchSpiBase + PCI_COMMAND_OFFSET, (UINT8) ~EFI_PCI_COMMAND_MEMORY_SPACE);
+ PciSegmentWrite32 (SpiInstance->PchSpiBase + R_SPI_CFG_BAR0, mSpiResvMmioAddr);
+ PciSegmentOr8 (SpiInstance->PchSpiBase + PCI_COMMAND_OFFSET, EFI_PCI_COMMAND_MEMORY_SPACE);
+ } else if (mPchSpiBar0RefCount == 0) {
+ mSpiSavedMmioAddr = 0;
+ mPchSpiSavedPciCmdReg = 0;
+ }
+ mPchSpiBar0RefCount++;
+
+ //
+ // SPIBAR0 will be different before and after PCI enum so need to get it from SPI BAR0 reg.
+ //
+ return mSpiResvMmioAddr;
+}
+
+/**
+ Release PCH SPI MMIO address. If AcquireSpiBar0() previously overwrote the
+ value of BAR0, this function will restore the original value assigned by PCI
+ enumeration
+
+ @param[in] SpiInstance Pointer to SpiInstance to initialize
+
+ @retval None
+**/
+VOID
+ReleaseSpiBar0 (
+ IN SPI_INSTANCE *SpiInstance
+ )
+{
+ //
+ // Reference counting is used here because multiple nested calls to
+ // AcquireSpiBar0()/ReleaseSpiBar0() will cause SpiBar0 to be reprogrammed
+ // back to the original value before access to the SPI controller is done.
+ // Reference counting ensures that the BAR is not restored until after access
+ // is complete.
+ //
+ if (mPchSpiBar0RefCount <= 1) {
+ mPchSpiBar0RefCount = 0;
+ if (mSpiSavedMmioAddr != 0) {
+ //
+ // Temporary disable MSE, restore the original SPI MMIO address, then
+ // restore PCI command register state
+ //
+ PciSegmentAnd8 (SpiInstance->PchSpiBase + PCI_COMMAND_OFFSET, (UINT8)~EFI_PCI_COMMAND_MEMORY_SPACE);
+ PciSegmentWrite32 (SpiInstance->PchSpiBase + R_SPI_CFG_BAR0, mSpiSavedMmioAddr);
+ PciSegmentWrite8 (SpiInstance->PchSpiBase + PCI_COMMAND_OFFSET, mPchSpiSavedPciCmdReg);
+
+ //
+ // Clear saved state
+ //
+ mSpiSavedMmioAddr = 0;
+ mPchSpiSavedPciCmdReg = 0;
+ }
+ } else {
+ mPchSpiBar0RefCount--;
+ }
+}
+
+/**
+ This function is a hook for Spi to disable BIOS Write Protect
+
+ @retval EFI_SUCCESS The protocol instance was properly initialized
+ @retval EFI_ACCESS_DENIED The BIOS Region can only be updated in SMM phase
+
+**/
+EFI_STATUS
+EFIAPI
+DisableBiosWriteProtect (
+ VOID
+ )
+{
+ UINT64 SpiBaseAddress;
+
+ SpiBaseAddress = SpiPciCfgBase ();
+ // Write clear BC_SYNC_SS prior to change WPD from 0 to 1.
+ //
+ PciSegmentOr8 (
+ SpiBaseAddress + R_SPI_CFG_BC + 1,
+ (B_SPI_CFG_BC_SYNC_SS >> 8)
+ );
+ ///
+ /// Set BIOSWE bit (SPI PCI Offset DCh [0]) = 1b
+ /// Enable the access to the BIOS space for both read and write cycles
+ ///
+ PciSegmentOr8 (
+ SpiBaseAddress + R_SPI_CFG_BC,
+ B_SPI_CFG_BC_WPD
+ );
+
+ return EFI_SUCCESS;
+}
+
+/**
+ This function is a hook for Spi to enable BIOS Write Protect
+**/
+VOID
+EFIAPI
+EnableBiosWriteProtect (
+ VOID
+ )
+{
+ UINT64 SpiBaseAddress;
+
+ SpiBaseAddress = SpiPciCfgBase ();
+ ///
+ /// Clear BIOSWE bit (SPI PCI Offset DCh [0]) = 0b
+ /// Disable the access to the BIOS space for write cycles
+ ///
+ PciSegmentAnd8 (
+ SpiBaseAddress + R_SPI_CFG_BC,
+ (UINT8) (~B_SPI_CFG_BC_WPD)
+ );
+
+}
+
+/**
+ Check if it's granted to do flash write.
+
+ @retval TRUE It's secure to do flash write.
+ @retval FALSE It's not secure to do flash write.
+**/
+BOOLEAN
+IsSpiFlashWriteGranted (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+ UINT32 CpuIndex;
+ UINT64 ProcessorId;
+
+ if (mSmmCpuProtocol == NULL) {
+ Status = gSmst->SmmLocateProtocol (&gEfiSmmCpuProtocolGuid, NULL, (VOID **)&mSmmCpuProtocol);
+ ASSERT_EFI_ERROR (Status);
+ if (mSmmCpuProtocol == NULL) {
+ return TRUE;
+ }
+ }
+
+ for (CpuIndex = 0; CpuIndex < gSmst->NumberOfCpus; CpuIndex++) {
+ Status = mSmmCpuProtocol->ReadSaveState (
+ mSmmCpuProtocol,
+ sizeof (ProcessorId),
+ EFI_SMM_SAVE_STATE_REGISTER_PROCESSOR_ID,
+ CpuIndex,
+ &ProcessorId
+ );
+ //
+ // If the processor is in SMM at the time the SMI occurred,
+ // it will return success. Otherwise, EFI_NOT_FOUND is returned.
+ //
+ if (EFI_ERROR (Status)) {
+ return FALSE;
+ }
+ }
+
+ return TRUE;
+}
+
+/**
+ Check if a save and restore of the SPI controller state is necessary
+
+ @retval TRUE It's necessary to save and restore SPI controller state
+ @retval FALSE It's not necessary to save and restore SPI controller state
+**/
+BOOLEAN
+IsSpiControllerSaveRestoreEnabled (
+ VOID
+ )
+{
+ return mBootServiceExited;
+}
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/Smm/SpiSmm.inf b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/Smm/SpiSmm.inf
new file mode 100644
index 0000000000..78913423fb
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/Smm/SpiSmm.inf
@@ -0,0 +1,46 @@
+## @file
+# Component description file for the SPI SMM driver.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+
+[Defines]
+INF_VERSION = 0x00010017
+BASE_NAME = SpiSmm
+FILE_GUID = 27F4917B-A707-4aad-9676-26DF168CBF0D
+VERSION_STRING = 1.0
+MODULE_TYPE = DXE_SMM_DRIVER
+PI_SPECIFICATION_VERSION = 1.10
+ENTRY_POINT = InstallPchSpi
+
+
+[LibraryClasses]
+DebugLib
+IoLib
+UefiDriverEntryPoint
+UefiBootServicesTableLib
+BaseLib
+SmmServicesTableLib
+SpiCommonLib
+PchPciBdfLib
+
+[Packages]
+MdePkg/MdePkg.dec
+AlderlakeSiliconPkg/SiPkg.dec
+
+
+[Sources]
+Spi.c
+
+
+[Protocols]
+gPchSmmSpiProtocolGuid ## PRODUCES
+gEfiSmmCpuProtocolGuid ## CONSUMES
+gEdkiiSmmExitBootServicesProtocolGuid ## CONSUMES
+
+
+[Depex]
+gEfiSmmBase2ProtocolGuid AND # This is for SmmServicesTableLib
+gEfiSmmCpuProtocolGuid
--
2.36.1.windows.1
-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#108680): https://edk2.groups.io/g/devel/message/108680
Mute This Topic: https://groups.io/mt/101373948/7686176
Group Owner: devel+owner@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [rebecca@openfw.io]
-=-=-=-=-=-=-=-=-=-=-=-
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [edk2-devel] [PATCH v2 05/10] AlderlakeSiliconPkg/Include: Add ConfigBlock headers
2023-09-15 4:45 [edk2-devel] [PATCH v2 01/10] AlderlakeSiliconPkg/IpBlock: Add CpuPcieRp, Espi, Gpio components Saloni Kasbekar
` (2 preceding siblings ...)
2023-09-15 4:45 ` [edk2-devel] [PATCH v2 04/10] AlderlakeSiliconPkg/IpBlock: Add Pmc, Spi components Saloni Kasbekar
@ 2023-09-15 4:45 ` Saloni Kasbekar
2023-09-15 5:42 ` Chaganty, Rangasai V
2023-09-15 23:56 ` Nate DeSimone
2023-09-15 4:45 ` [edk2-devel] [PATCH v2 06/10] AlderlakeSiliconPkg/Include: Add Library, Pins, Ppi Includes Saloni Kasbekar
` (7 subsequent siblings)
11 siblings, 2 replies; 41+ messages in thread
From: Saloni Kasbekar @ 2023-09-15 4:45 UTC (permalink / raw)
To: devel; +Cc: Saloni Kasbekar, Sai Chaganty, Nate DeSimone, Rosen Chuang
Adds the header includes for the ConfigBlocks
Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Rosen Chuang <rosen.chuang@intel.com>
Signed-off-by: Saloni Kasbekar <saloni.kasbekar@intel.com>
---
.../CpuPcieRp/Gen3/CpuPcieConfigGen3.h | 48 ++
.../CpuPcieRp/Gen4/CpuPcieConfig.h | 240 ++++++++
.../Include/ConfigBlock/Espi/LpcConfig.h | 38 ++
.../Include/ConfigBlock/Fivr/FivrConfig.h | 183 ++++++
.../Include/ConfigBlock/Gpio/GpioDevConfig.h | 37 ++
.../Graphics/Gen12/GraphicsConfig.h | 212 +++++++
.../HostBridge/Ver1/HostBridgeConfig.h | 58 ++
.../ConfigBlock/Itss/InterruptConfig.h | 38 ++
.../ConfigBlock/Memory/Ver2/MemoryConfig.h | 551 ++++++++++++++++++
.../Include/ConfigBlock/PchDmi/PchDmiConfig.h | 65 +++
.../PcieRp/PchPcieRp/PchPcieRpConfig.h | 180 ++++++
.../Include/ConfigBlock/PcieRp/PcieConfig.h | 408 +++++++++++++
.../ConfigBlock/PcieRp/PciePreMemConfig.h | 36 ++
.../Include/ConfigBlock/Pmc/AdrConfig.h | 76 +++
.../Include/ConfigBlock/Pmc/PmConfig.h | 86 +++
.../Include/ConfigBlock/Rtc/RtcConfig.h | 37 ++
.../ConfigBlock/SerialIo/SerialIoConfig.h | 33 ++
.../Include/ConfigBlock/SiConfig.h | 105 ++++
.../Include/ConfigBlock/SiPreMemConfig.h | 63 ++
.../Include/ConfigBlock/Smbus/SmbusConfig.h | 49 ++
.../ConfigBlock/Spi/FlashProtectionConfig.h | 54 ++
.../Include/ConfigBlock/Tcss/TcssPeiConfig.h | 71 +++
.../Include/ConfigBlock/Vmd/VmdPeiConfig.h | 60 ++
.../Include/ConfigBlock/Wdt/WatchDogConfig.h | 30 +
24 files changed, 2758 insertions(+)
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/CpuPcieRp/Gen3/CpuPcieConfigGen3.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/CpuPcieRp/Gen4/CpuPcieConfig.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Espi/LpcConfig.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Fivr/FivrConfig.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Gpio/GpioDevConfig.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Graphics/Gen12/GraphicsConfig.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/HostBridge/Ver1/HostBridgeConfig.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Itss/InterruptConfig.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Memory/Ver2/MemoryConfig.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/PchDmi/PchDmiConfig.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/PcieRp/PchPcieRp/PchPcieRpConfig.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/PcieRp/PcieConfig.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/PcieRp/PciePreMemConfig.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Pmc/AdrConfig.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Pmc/PmConfig.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Rtc/RtcConfig.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/SerialIo/SerialIoConfig.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/SiConfig.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/SiPreMemConfig.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Smbus/SmbusConfig.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Spi/FlashProtectionConfig.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Tcss/TcssPeiConfig.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Vmd/VmdPeiConfig.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Wdt/WatchDogConfig.h
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/CpuPcieRp/Gen3/CpuPcieConfigGen3.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/CpuPcieRp/Gen3/CpuPcieConfigGen3.h
new file mode 100644
index 0000000000..5b437c8311
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/CpuPcieRp/Gen3/CpuPcieConfigGen3.h
@@ -0,0 +1,48 @@
+/** @file
+Pcie root port policy
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _CPU_PCIE_CONFIG_GEN3_H_
+#define _CPU_PCIE_CONFIG_GEN3_H_
+
+#include <Library/GpioLib.h>
+#include <Library/CpuPcieInfoFruLib.h>
+#include <PcieConfig.h>
+#include <ConfigBlock.h>
+#include <Register/SaRegsHostBridge.h>
+
+#pragma pack(push, 1)
+
+
+#define L0_SET BIT0
+#define L1_SET BIT1
+
+
+///
+/// SA GPIO Data Structure
+///
+typedef struct {
+ GPIO_PAD GpioPad; ///< Offset 0: GPIO Pad
+ UINT8 Value; ///< Offset 4: GPIO Value
+ UINT8 Rsvd0[3]; ///< Offset 5: Reserved for 4 bytes alignment
+ UINT32 Active : 1; ///< Offset 8: 0=Active Low; 1=Active High
+ UINT32 RsvdBits0 : 31;
+} SA_GPIO_INFO_PCIE;
+
+///
+/// SA Board PEG GPIO Info
+///
+typedef struct {
+ SA_GPIO_INFO_PCIE SaPeg0ResetGpio; ///< Offset 0: PEG0 PERST# GPIO assigned, must be a PCH GPIO pin
+ SA_GPIO_INFO_PCIE SaPeg3ResetGpio; ///< Offset 12: PEG3 PERST# GPIO assigned, must be a PCH GPIO pin
+ BOOLEAN GpioSupport; ///< Offset 24: 1=Supported; 0=Not Supported
+ UINT8 Rsvd0[3]; ///< Offset 25: Reserved for 4 bytes alignment
+} PEG_GPIO_DATA;
+
+
+#pragma pack (pop)
+
+#endif // _CPU_PCIE_CONFIG_GEN3_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/CpuPcieRp/Gen4/CpuPcieConfig.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/CpuPcieRp/Gen4/CpuPcieConfig.h
new file mode 100644
index 0000000000..999748d711
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/CpuPcieRp/Gen4/CpuPcieConfig.h
@@ -0,0 +1,240 @@
+/** @file
+ Pcie root port policy
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _CPU_PCIE_CONFIG_H_
+#define _CPU_PCIE_CONFIG_H_
+
+#include <Library/GpioLib.h>
+#include <Library/CpuPcieInfoFruLib.h>
+#include <PcieConfig.h>
+#include <ConfigBlock.h>
+#include <Register/SaRegsHostBridge.h>
+
+#pragma pack(push, 1)
+
+#define CPU_PCIE_RP_PREMEM_CONFIG_REVISION 1
+
+/**
+ Making any setup structure change after code frozen
+ will need to maintain backward compatibility, bump up
+ structure revision and update below history table\n
+ <b>Revision 1</b>: - Initial version.
+**/
+
+#define CPU_PCIE_CONFIG_REVISION 10
+
+#define L0_SET BIT0
+#define L1_SET BIT1
+
+/**
+ CPU PCIe Root Port Pre-Memory Configuration
+ Contains Root Port settings and capabilities
+ <b>Revision 1</b>: - Initial version.
+ <b>Revision 2</b>: - Adding Dekel Suqelch Workaround Setup Variable
+ <b>Revision 3</b>: - Deprecate Dekel Suqelch Workaround Setup Variable
+ <b>Revision 4</b>: - Adding New FOM Setup Variable
+ <b>Revision 5</b>: - Add CdrRelock Policy to CPU_PCIE_RP_PREMEM_CONFIG.
+**/
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Config Block Header
+ /**
+ Root Port enabling mask.
+ Bit0 presents RP1, Bit1 presents RP2, and so on.
+ 0: Disable; <b>1: Enable</b>.
+ **/
+ UINT32 RpEnabledMask;
+ /**
+ Assertion on Link Down GPIOs
+ - <b>Disabled</b> (0x0) : Disable assertion on Link Down GPIOs(Default)
+ - Enabled (0x1) : Enable assertion on Link Down GPIOs
+ **/
+ UINT8 LinkDownGpios;
+ /**
+ Enable ClockReq Messaging
+ - <b>Disabled</> (0x0) : Disable ClockReq Messaging(Default)
+ - Enabled (0x1) : Enable ClockReq Messaging
+ **/
+ UINT8 ClkReqMsgEnable;
+ /**
+ Dekel Recipe Workaround
+ <b>2</b>
+ 1=Minimal, 9=Maximum,
+ **/
+ UINT8 DekelSquelchWa; // Deprecated variable
+ UINT8 Rsvd0[1];
+ /**
+ Determines each PCIE Port speed capability.
+ <b>0: Auto</b>; 1: Gen1; 2: Gen2; 3: Gen3; 4: Gen4 (see: CPU_PCIE_SPEED)
+ **/
+ UINT8 PcieSpeed[CPU_PCIE_MAX_ROOT_PORTS];
+
+ /**
+ Enable ClockReq Messaging Policy is for all Rootports
+ - <b>Disabled</> (0x0) : Disable ClockReq Messaging(Default)
+ - Enabled (0x1) : Enable ClockReq Messaging
+ **/
+ UINT8 ClkReqMsgEnableRp[CPU_PCIE_MAX_ROOT_PORTS];
+ /**
+ To Enable/Disable New FOM
+ <b>0: Disable</b>; 1: Enable
+ **/
+ UINT8 NewFom[CPU_PCIE_MAX_ROOT_PORTS];
+ /**
+ To Enable/Disable CDR Relock
+ <b>0: Disable</b>; 1: Enable
+ **/
+ UINT8 CdrRelock[CPU_PCIE_MAX_ROOT_PORTS];
+} CPU_PCIE_RP_PREMEM_CONFIG;
+
+/**
+ Represent lane specific PCIe Gen3 equalization parameters.
+**/
+typedef struct {
+ UINT8 Cm; ///< Coefficient C-1
+ UINT8 Cp; ///< Coefficient C+1
+ UINT8 PegGen3RootPortPreset; ///< <b>(Test)</b> Used for programming PEG Gen3 preset values per lane. Range: 0-9, 8 is default for each lane
+ UINT8 PegGen3EndPointPreset; ///< <b>(Test)</b> Used for programming PEG Gen3 preset values per lane. Range: 0-9, 7 is default for each lane
+ UINT8 PegGen3EndPointHint; ///< <b>(Test)</b> Hint value per lane for the PEG Gen3 End Point. Range: 0-6, 2 is default for each lane
+ UINT8 PegGen4RootPortPreset; ///< <b>(Test)</b> Used for programming PEG Gen4 preset values per lane. Range: 0-9, 8 is default for each lane
+ UINT8 PegGen4EndPointPreset; ///< <b>(Test)</b> Used for programming PEG Gen4 preset values per lane. Range: 0-9, 7 is default for each lane
+ UINT8 PegGen4EndPointHint; ///< <b>(Test)</b> Hint value per lane for the PEG Gen4 End Point. Range: 0-6, 2 is default for each lane
+} CPU_PCIE_EQ_LANE_PARAM;
+
+/**
+ The CPU_PCI_ROOT_PORT_CONFIG describe the feature and capability of each CPU PCIe root port.
+**/
+typedef struct {
+
+ UINT32 ExtSync : 1; ///< Indicate whether the extended synch is enabled. <b>0: Disable</b>; 1: Enable.
+ UINT32 MultiVcEnabled : 1; ///< Multiple Virtual Channel. 0: Disable; <b>1: Enable</b>
+ UINT32 RsvdBits0 : 30; ///< Reserved bits
+ /**
+ PCIe Gen4 Equalization Method
+ - HwEq (0x1) : Hardware Equalization (Default)
+ - StaticEq (0x2) : Static Equalization
+ **/
+ UINT8 Gen4EqPh3Method;
+ UINT8 FomsCp; ///< FOM Score Board Control Policy
+ UINT8 RsvdBytes0[2]; ///< Reserved bytes
+
+ //
+ // Gen3 Equalization settings
+ //
+ UINT32 Gen3Uptp : 4; ///< <b>(Test)</b> Upstream Port Transmitter Preset used during Gen3 Link Equalization. Used for all lanes. Default is <b>7</b>.
+ UINT32 Gen3Dptp : 4; ///< <b>(Test)</b> Downstream Port Transmiter Preset used during Gen3 Link Equalization. Used for all lanes. Default is <b>7</b>.
+ //
+ // Gen4 Equalization settings
+ //
+ UINT32 Gen4Uptp : 4; ///< <b>(Test)</b> Upstream Port Transmitter Preset used during Gen4 Link Equalization. Used for all lanes. Default is <b>7</b>.
+ UINT32 Gen4Dptp : 4; ///< <b>(Test)</b> Downstream Port Transmiter Preset used during Gen4 Link Equalization. Used for all lanes. Default is <b>7</b>.
+ //
+ // Gen5 Equalization settings
+ //
+ UINT32 Gen5Uptp : 4; ///< <b>(Test)</b> Upstream Port Transmitter Preset used during Gen5 Link Equalization. Used for all lanes. Default is <b>5</b>.
+ UINT32 Gen5Dptp : 4; ///< <b>(Test)</b> Downstream Port Transmiter Preset used during Gen5 Link Equalization. Used for all lanes. Default is <b>7</b>.
+ UINT32 RsvdBits1 : 8; ///< Reserved Bits
+
+ PCIE_ROOT_PORT_COMMON_CONFIG PcieRpCommonConfig; ///< <b>(Test)</b> Includes policies which are common to both SA and PCH RootPort
+
+} CPU_PCIE_ROOT_PORT_CONFIG;
+
+typedef struct {
+ UINT8 PcieGen3PresetCoeffSelection; ///<Gen3 Preset or Coefficient Selection
+ UINT8 PcieGen4PresetCoeffSelection; ///<Gen4 Preset or Coefficient Selection
+ UINT8 PcieGen5PresetCoeffSelection; ///<Gen5 Preset or Coefficient Selection
+ UINT8 Func0LinkDisable; ///< Disable Func0 Port
+} CPU_PCIE_ROOT_PORT_CONFIG2;
+
+/**
+ The CPU_PCIE_CONFIG block describes the expected configuration of the CPU PCI Express controllers
+ <b>Revision 1< / b>:
+ -Initial version.
+ <b>Revision 2</b>:
+ - SlotSelection policy added
+ <b>Revision 3</b>
+ - Deprecate PegGen3ProgramStaticEq and PegGen4ProgramStaticEq
+ <b>Revision 4</b>:
+ - Deprecating SetSecuredRegisterLock
+ <b>Revision 5</b>:
+ - Moved ClockGating policy to PCIE_ROOT_PORT_COMMON_CONFIG
+ - Moved PowerGating policy to PCIE_ROOT_PORT_COMMON_CONFIG
+ - Deprecate VcEnabled policy
+ <b>Revision 7</b>:
+ - Deprecating Gen3PresetCoeffSelection and Gen4PresetCoeffSelection
+ <b>Revision 8</b>:
+ - Added Serl policy
+ <b>Revision 9</b>:
+ - Align revision with CPU_PCIE_CONFIG_REVISION value
+ <b>Revision 10</b>:
+ - Deprecate EqPh3LaneParam.Cm and EqPh3LaneParam.Cp
+**/
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Config Block Header
+ ///
+ /// These members describe the configuration of each SA PCIe root port.
+ ///
+ CPU_PCIE_ROOT_PORT_CONFIG RootPort[CPU_PCIE_MAX_ROOT_PORTS];
+ ///
+ /// Gen3 Equalization settings for physical PCIe lane, index 0 represents PCIe lane 1, etc.
+ /// Corresponding entries are used when root port EqPh3Method is PchPcieEqStaticCoeff (default).
+ ///
+ CPU_PCIE_EQ_LANE_PARAM EqPh3LaneParam[SA_PEG_MAX_LANE]; //@ Deprecated Policy
+ ///
+ /// List of coefficients used during equalization (applicable to both software and hardware EQ)
+ ///
+ PCIE_EQ_PARAM HwEqGen4CoeffList[PCIE_HWEQ_COEFFS_MAX]; //@ Deprecated Policy
+
+ PCIE_COMMON_CONFIG PcieCommonConfig; /// < <b>(Test)</b> Includes policies which are common to both SA and PCH PCIe
+
+ UINT32 FiaProgramming : 1; /// < Skip Fia Configuration and lock if enable
+ // Deprecated Policy
+ /**
+ <b>(Test)</b> Program PEG Gen3 EQ Phase1 Static Presets
+ - Disabled (0x0) : Disable EQ Phase1 Static Presets Programming
+ - <b>Enabled</b> (0x1) : Enable EQ Phase1 Static Presets Programming (Default)
+ **/
+ UINT32 PegGen3ProgramStaticEq : 1;
+
+ // Deprecated Policy
+ /**
+ <b>(Test)</b> Program PEG Gen4 EQ Phase1 Static Presets
+ - Disabled (0x0) : Disable EQ Phase1 Static Presets Programming
+ - <b>Enabled</b> (0x1) : Enable EQ Phase1 Static Presets Programming (Default)
+ **/
+ UINT32 PegGen4ProgramStaticEq : 1;
+ /**
+ <b>(Test)</b> Cpu Pcie Secure Register Lock
+ - Disabled (0x0)
+ - <b>Enabled</b> (0x1)
+ **/
+ UINT32 SetSecuredRegisterLock : 1; // Deprecated Policy
+ ///
+ /// This member allows to select between the PCI Express M2 or CEMx4 slot <b>1: PCIe M2</b>; 0: CEMx4 slot.
+ ///
+ UINT32 SlotSelection : 1;
+
+ UINT32 Serl : 1;
+
+ UINT32 RsvdBits0 : 26;
+
+ /**
+ PCIe device override table
+ The PCIe device table is being used to override PCIe device ASPM settings.
+ This is a pointer points to a 32bit address. And it's only used in PostMem phase.
+ Please refer to PCIE_DEVICE_OVERRIDE structure for the table.
+ Last entry VendorId must be 0.
+ The prototype of this policy is:
+ PCIE_DEVICE_OVERRIDE *PcieDeviceOverrideTablePtr;
+ **/
+ UINT32 PcieDeviceOverrideTablePtr;
+ CPU_PCIE_ROOT_PORT_CONFIG2 RootPort2[CPU_PCIE_MAX_ROOT_PORTS];
+ PCIE_COMMON_CONFIG2 PcieCommonConfig2;
+ } CPU_PCIE_CONFIG;
+
+#pragma pack (pop)
+
+#endif // _CPU_PCIE_CONFIG_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Espi/LpcConfig.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Espi/LpcConfig.h
new file mode 100644
index 0000000000..324facde78
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Espi/LpcConfig.h
@@ -0,0 +1,38 @@
+/** @file
+ Lpc policy
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _LPC_CONFIG_H_
+#define _LPC_CONFIG_H_
+
+#define PCH_LPC_PREMEM_CONFIG_REVISION 1
+extern EFI_GUID gLpcPreMemConfigGuid;
+
+#pragma pack (push,1)
+
+/**
+ This structure contains the policies which are related to LPC.
+**/
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Config Block Header
+ /**
+ Enhance the port 8xh decoding.
+ Original LPC only decodes one byte of port 80h, with this enhancement LPC can decode word or dword of port 80h-83h.
+ @note: this will occupy one LPC generic IO range register. While this is enabled, read from port 80h always return 0x00.
+ 0: Disable, <b>1: Enable</b>
+ **/
+ UINT32 EnhancePort8xhDecoding : 1;
+ /**
+ Hardware Autonomous Enable.
+ When enabled, LPC will automatically engage power gating when it has reached its idle condition.
+ 0: Disable, <b>1: Enable</b>
+ **/
+ UINT32 LpcPmHAE : 1;
+ UINT32 RsvdBits : 30; ///< Reserved bits
+} PCH_LPC_PREMEM_CONFIG;
+
+#pragma pack (pop)
+
+#endif // _LPC_CONFIG_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Fivr/FivrConfig.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Fivr/FivrConfig.h
new file mode 100644
index 0000000000..501e00c0e1
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Fivr/FivrConfig.h
@@ -0,0 +1,183 @@
+/** @file
+ PCH FIVR policy
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _FIVR_CONFIG_H_
+#define _FIVR_CONFIG_H_
+
+/**
+ <b>Revision 1</b>: - Initial version.
+**/
+#define PCH_FIVR_CONFIG_REVISION 1
+extern EFI_GUID gFivrConfigGuid;
+
+#pragma pack (push,1)
+
+/**
+ Rail support in S0ix and Sx
+ Settings other than FivrRailDisabled can be OR'ed
+**/
+typedef enum {
+ FivrRailDisabled = 0,
+ FivrRailInS0i1S0i2 = BIT0,
+ FivrRailInS0i3 = BIT1,
+ FivrRailInS3 = BIT2,
+ FivrRailInS4 = BIT3,
+ FivrRailInS5 = BIT4,
+ FivrRailInS0ix = FivrRailInS0i1S0i2 | FivrRailInS0i3,
+ FivrRailInSx = FivrRailInS3 | FivrRailInS4 | FivrRailInS5,
+ FivrRailAlwaysOn = FivrRailInS0ix | FivrRailInSx
+} FIVR_RAIL_SX_STATE;
+
+typedef enum {
+ FivrRetentionActive = BIT0,
+ FivrNormActive = BIT1,
+ FivrMinActive = BIT2,
+ FivrMinRetention = BIT3
+} FIVR_RAIL_SUPPORTED_VOLTAGE;
+
+/**
+ Structure for V1p05/Vnn VR rail configuration
+**/
+typedef struct {
+ /**
+ Mask to enable the usage of external VR rail in specific S0ix or Sx states
+ Use values from FIVR_RAIL_SX_STATE
+ The default is <b>FivrRailDisabled</b>.
+ **/
+ UINT32 EnabledStates : 6;
+
+ /**
+ VR rail voltage value that will be used in S0i2/S0i3 states.
+ This value is given in 2.5mV increments (0=0mV, 1=2.5mV, 2=5mV...)
+ The default for Vnn is set to <b>420 - 1050 mV</b>.
+ **/
+ UINT32 Voltage : 11;
+ /**
+ @deprecated
+ THIS POLICY IS DEPRECATED, PLEASE USE IccMaximum INSTEAD
+ VR rail Icc Max Value
+ Granularity of this setting is 1mA and maximal possible value is 500mA
+ The default is <b> 0mA </b>.
+ **/
+ UINT32 IccMax : 8;
+ /**
+ UINT32 Alignement
+ **/
+ UINT32 RsvdBits1 : 7;
+ /**
+ This register holds the control hold off values to be used when
+ changing the rail control for external bypass value in us
+ **/
+ UINT32 CtrlRampTmr : 8;
+
+ /**
+ Mask to set the supported configuration in VR rail.
+ Use values from FIVR_RAIL_SUPPORTED_VOLTAGE
+ **/
+ UINT32 SupportedVoltageStates : 4;
+
+ /**
+ VR rail Icc Maximum Value
+ Granularity of this setting is 1mA and maximal possible value is 500mA
+ The default is <b> 0mA </b>.
+ **/
+ UINT32 IccMaximum : 16;
+ /**
+ UINT32 Alignment
+ **/
+ UINT32 RsvdBits2 : 4;
+
+} FIVR_EXT_RAIL_CONFIG;
+
+
+/**
+ Structure for VCCIN_AUX voltage rail configuration
+**/
+typedef struct {
+ /**
+ Transition time in microseconds from Low Current Mode Voltage to High Current Mode Voltage.
+ Voltage transition time required by motherboard voltage regulator when PCH changes
+ the VCCIN_AUX regulator set point from the low current mode voltage and high current mode voltage.
+ This field has 1us resolution.
+ When value is 0 PCH will not transition VCCIN_AUX to low current mode voltage.
+ The default is <b> 0xC </b>.
+ **/
+ UINT8 LowToHighCurModeVolTranTime;
+
+ /**
+ Transition time in microseconds from Retention Mode Voltage to High Current Mode Voltage.
+ Voltage transition time required by motherboard voltage regulator when PCH changes
+ the VCCIN_AUX regulator set point from the retention mode voltage to high current mode voltage.
+ This field has 1us resolution.
+ When value is 0 PCH will not transition VCCIN_AUX to retention voltage.
+ The default is <b> 0x36 </b>.
+ **/
+ UINT8 RetToHighCurModeVolTranTime;
+
+ /**
+ Transition time in microseconds from Retention Mode Voltage to Low Current Mode Voltage.
+ Voltage transition time required by motherboard voltage regulator when PCH changes
+ the VCCIN_AUX regulator set point from the retention mode voltage to low current mode voltage.
+ This field has 1us resolution.
+ When value is 0 PCH will not transition VCCIN_AUX to retention voltage.
+ The default is <b> 0x2B </b>.
+ **/
+ UINT8 RetToLowCurModeVolTranTime;
+ UINT8 RsvdByte1;
+ /**
+ Transition time in microseconds from Off (0V) to High Current Mode Voltage.
+ Voltage transition time required by motherboard voltage regulator when PCH changes
+ the VCCIN_AUX regulator set point from 0V to the high current mode voltage.
+ This field has 1us resolution.
+ 0 = Transition to 0V is disabled
+ Setting this field to 0 sets VCCIN_AUX as a fixed rail that stays on
+ in all S0 & Sx power states after initial start up on G3 exit
+ The default is <b> 0x96 </b>.
+ **/
+ UINT32 OffToHighCurModeVolTranTime : 11;
+ UINT32 RsvdBits1 : 21;
+} FIVR_VCCIN_AUX_CONFIG;
+
+/**
+ The PCH_FIVR_CONFIG block describes FIVR settings.
+**/
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Config Block Header
+ /**
+ External V1P05 VR rail configuration.
+ **/
+ FIVR_EXT_RAIL_CONFIG ExtV1p05Rail;
+ /**
+ External Vnn VR rail configuration.
+ **/
+ FIVR_EXT_RAIL_CONFIG ExtVnnRail;
+ /**
+ Additional External Vnn VR rail configuration that will get applied
+ in Sx entry SMI callback. Required only if External Vnn VR
+ needs different settings for Sx than those specified in ExtVnnRail.
+ **/
+ FIVR_EXT_RAIL_CONFIG ExtVnnRailSx;
+ /**
+ VCCIN_AUX voltage rail configuration.
+ **/
+ FIVR_VCCIN_AUX_CONFIG VccinAux;
+
+ /**
+ Enable/Disable FIVR Dynamic Power Management
+ Default is <b> 1 </b>.
+ **/
+ UINT32 FivrDynPm : 1;
+ /**
+ Enable/Disable Bypass of FIVR configuration
+ Default is <b> 0 </b>.
+ **/
+ UINT32 BypassFivrConfig : 1;
+ UINT32 RsvdBits2 : 30;
+} PCH_FIVR_CONFIG;
+
+#pragma pack (pop)
+
+#endif // _FIVR_CONFIG_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Gpio/GpioDevConfig.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Gpio/GpioDevConfig.h
new file mode 100644
index 0000000000..5652df0259
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Gpio/GpioDevConfig.h
@@ -0,0 +1,37 @@
+/** @file
+ GPIO device policy
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _GPIO_DEV_CONFIG_H_
+#define _GPIO_DEV_CONFIG_H_
+
+extern EFI_GUID gGpioDxeConfigGuid;
+
+#define GPIO_DXE_CONFIG_REVISION 1
+
+#pragma pack (push,1)
+
+/**
+ This structure contains the DXE policies which are related to GPIO device.
+
+ <b>Revision 1:</b>
+ - Inital version.
+**/
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Config Block Header
+ /**
+ If GPIO ACPI device is not used by OS it can be hidden. In such case
+ no other device exposed to the system can reference GPIO device in one
+ of its resources through GpioIo(..) or GpioInt(..) ACPI descriptors.
+ <b>0: Disable</b>; 1: Enable
+ **/
+ UINT32 HideGpioAcpiDevice : 1;
+ UINT32 RsvdBits : 31; ///< Reserved bits
+
+} GPIO_DXE_CONFIG;
+
+#pragma pack (pop)
+
+#endif // _GPIO_DEV_CONFIG_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Graphics/Gen12/GraphicsConfig.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Graphics/Gen12/GraphicsConfig.h
new file mode 100644
index 0000000000..c6a2f36612
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Graphics/Gen12/GraphicsConfig.h
@@ -0,0 +1,212 @@
+/** @file
+ Policy definition for Internal Graphics Config Block.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _GRAPHICS_CONFIG_H_
+#define _GRAPHICS_CONFIG_H_
+#pragma pack(push, 1)
+
+#define GRAPHICS_DXE_CONFIG_REVISION 2
+
+#define MAX_BCLM_ENTRIES 20
+
+
+//
+// DDI defines
+//
+typedef enum {
+ DdiDisable = 0x00,
+ DdiDdcEnable = 0x01,
+} DDI_DDC_TBT_VAL;
+
+typedef enum {
+ DdiHpdDisable = 0x00,
+ DdiHpdEnable = 0x01,
+} DDI_HPD_VAL;
+
+typedef enum {
+ DdiPortDisabled = 0x00,
+ DdiPortEdp = 0x01,
+ DdiPortMipiDsi = 0x02,
+} DDI_PORT_SETTINGS;
+
+/**
+ This structure configures the Native GPIOs for DDI port per VBT settings.
+**/
+typedef struct {
+ UINT8 DdiPortAConfig; /// The Configuration of DDI port A, this settings must match VBT's settings. DdiPortDisabled - No LFP is connected on DdiPortA, <b>DdiPortEdp - Set DdiPortA to eDP</b>, DdiPortMipiDsi - Set DdiPortA to MIPI DSI
+ UINT8 DdiPortBConfig; /// The Configuration of DDI port B, this settings must match VBT's settings. DdiPortDisabled - No LFP is connected on DdiPortB, <b>DdiPortEdp - Set DdiPortB to eDP</b>, DdiPortMipiDsi - Set DdiPortB to MIPI DSI
+ UINT8 DdiPortAHpd; /// The HPD setting of DDI Port A, this settings must match VBT's settings. <b>DdiHpdDisable - Disable HPD</b>, DdiHpdEnable - Enable HPD
+ UINT8 DdiPortBHpd; /// The HPD setting of DDI Port B, this settings must match VBT's settings. DdiHpdDisable - Disable HPD, <b>DdiHpdEnable - Enable HPD</b>
+ UINT8 DdiPortCHpd; /// The HPD setting of DDI Port C, this settings must match VBT's settings. <b>DdiHpdDisable - Disable HPD</b>, DdiHpdEnable - Enable HPD
+ UINT8 DdiPort1Hpd; /// The HPD setting of DDI Port 1, this settings must match VBT's settings. <b>DdiHpdDisable - Disable HPD</b>, DdiHpdEnable - Enable HPD
+ UINT8 DdiPort2Hpd; /// The HPD setting of DDI Port 2, this settings must match VBT's settings. <b>DdiHpdDisable - Disable HPD</b>, DdiHpdEnable - Enable HPD
+ UINT8 DdiPort3Hpd; /// The HPD setting of DDI Port 3, this settings must match VBT's settings. <b>DdiHpdDisable - Disable HPD</b>, DdiHpdEnable - Enable HPD
+ UINT8 DdiPort4Hpd; /// The HPD setting of DDI Port 4, this settings must match VBT's settings. <b>DdiHpdDisable - Disable HPD</b>, DdiHpdEnable - Enable HPD
+ UINT8 DdiPortADdc; /// The DDC setting of DDI Port A, this settings must match VBT's settings. <b>DdiDisable - Disable DDC</b>, DdiDdcEnable - Enable DDC
+ UINT8 DdiPortBDdc; /// The DDC setting of DDI Port B, this settings must match VBT's settings. DdiDisable - Disable DDC, <b>DdiDdcEnable - Enable DDC </b>
+ UINT8 DdiPortCDdc; /// The DDC setting of DDI Port C, this settings must match VBT's settings. <b>DdiDisable - Disable DDC</b>, DdiDdcEnable - Enable DDC
+ UINT8 DdiPort1Ddc; /// The DDC setting of DDI Port 1, this settings must match VBT's settings. <b>DdiDisable - Disable DDC</b>, DdiDdcEnable - Enable DDC
+ UINT8 DdiPort2Ddc; /// The DDC setting of DDI Port 2, this settings must match VBT's settings. <b>DdiDisable - Disable DDC</b>, DdiDdcEnable - Enable DDC
+ UINT8 DdiPort3Ddc; /// The DDC setting of DDI Port 3, this settings must match VBT's settings. <b>DdiDisable - Disable DDC</b>, DdiDdcEnable - Enable DDC
+ UINT8 DdiPort4Ddc; /// The DDC setting of DDI Port 4, this settings must match VBT's settings. <b>DdiDisable - Disable DDC</b>, DdiDdcEnable - Enable DDC
+} DDI_CONFIGURATION;
+
+/**
+ This Configuration block is to configure GT related PreMem data/variables.\n
+ <b>Revision 1</b>:
+ - Initial version.
+**/
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Block Header
+ /**
+ Offset 28
+ Selection of the primary display device: 0=iGFX, 1=PEG, 2=PCIe Graphics on PCH, <b>3=AUTO</b>, 4=Switchable Graphics\n
+ When AUTO mode selected, the priority of display devices is: PCIe Graphics on PCH > PEG > iGFX
+ **/
+ UINT8 PrimaryDisplay;
+ /**
+ Offset 29
+ Intel Gfx Support. It controls enabling/disabling iGfx device.
+ When AUTO mode selected, iGFX will be turned off when external graphics detected.
+ If FALSE, all other polices can be ignored.
+ <b>2 = AUTO</b>;
+ 0 = FALSE;
+ 1 = TRUE.
+ **/
+ UINT8 InternalGraphics;
+ /**
+ Offset 30
+ Pre-allocated memory for iGFX\n
+ 0 = 0MB,1 or 247 = 32MB,\n
+ 2 = 64MB,\n
+ 240 = 4MB, 241 = 8MB,\n
+ 242 = 12MB, 243 = 16MB,\n
+ 244 = 20MB, 245 = 24MB,\n
+ 246 = 28MB, 248 = 36MB,\n
+ 249 = 40MB, 250 = 44MB,\n
+ 251 = 48MB, 252 = 52MB,\n
+ 253 = 56MB,<b> 254 = 60MB</b>,\n
+ <b>Note: enlarging pre-allocated memory for iGFX may need to reduce MmioSize because of 4GB boundary limitation</b>
+ **/
+ UINT16 IgdDvmt50PreAlloc;
+ UINT8 PanelPowerEnable; ///< Offset 32 :<b>(Test)</b> Control for enabling/disabling VDD force bit (Required only for early enabling of eDP panel): 0=FALSE, <b>1=TRUE</b>
+ UINT8 ApertureSize; ///< Offset 33 :Graphics aperture size (256MB is the recommended size as per BWG) : 0=128MB, <b>1=256MB</b>, 3=512MB, 7=1024MB, 15=2048MB.
+ UINT8 GtPsmiSupport; ///< Offset 34 :PSMI support On/Off: <b>0=FALSE</b>, 1=TRUE
+ UINT8 PsmiRegionSize; ///< Offset 35 :Psmi region size: <b>0=32MB</b>, 1=288MB, 2=544MB, 3=800MB, 4=1056MB
+ UINT8 DismSize; ///< Offset 36 :DiSM Size for 2LM Sku: <b>0=0GB</b>, 1=1GB, 2=2GB, 3=3GB, 4=4GB, 5=5GB, 6=6GB, 7=7GB
+ UINT8 DfdRestoreEnable; ///< Offset 37 :(Deprecated) Display memory map programming for DFD Restore <b>0- Disable</b>, 1- Enable
+ UINT16 GttSize; ///< Offset 38 :Selection of iGFX GTT Memory size: 1=2MB, 2=4MB, <b>3=8MB</b>
+ /**
+ Offset 40
+ Temp Address of System Agent GTTMMADR: Default is <b>0xAF000000</b>
+ **/
+ UINT32 GttMmAdr;
+ UINT32 GmAdr; ///< Offset 44 Obsolete not to be used, use GmAdr64
+ DDI_CONFIGURATION DdiConfiguration; ///< Offset 48 DDI configuration, need to match with VBT settings.
+
+ UINT8 GtClosEnable; ///< Offset 50 Gt ClOS
+ UINT8 Rsvd0[7]; ///< Offset 51 Reserved for 4 bytes of alignment
+ /**
+ Offset 58
+ Temp Address of System Agent GMADR: Default is <b>0xB0000000</b>
+ **/
+ UINT64 GmAdr64;
+ UINT16 DeltaT12PowerCycleDelay; ///< Offset 66 Power Cycle Delay required for eDP as per VESA standard.0 - 0 ms, <b>0xFFFF - Auto calculate to max 500 ms<\b>
+ UINT8 DisplayAudioLink; ///< Offset 68 Enable/Disable Display Audio Links in Pre-OS.<b>0- Disable</b>, 1- Enable
+ UINT8 OemT12DelayOverride; ///< Offset 69 :Oem T12 Delay Override <b> Disable<\b>,Enable-Enable T12 Time.
+ UINT8 Rsvd2[4]; ///< Offset 70 Reserved for 4 bytes of alignment
+} GRAPHICS_PEI_PREMEM_CONFIG;
+
+/**
+ This configuration block is to configure IGD related variables used in PostMem PEI.
+ If Intel Gfx Device is not supported, all policies can be ignored.
+ <b>Revision 1</b>:
+ - Initial version.
+ <b>Revision 2</b>:
+ - Removed DfdRestoreEnable.
+ <b>Revision 3</b>:
+ - Removed DdiConfiguration.
+ <b>Revision 4</b>:
+ - Added new CdClock frequency
+ <b>Revision 5</b>:
+ - Added GT Chicket bits
+ <b>Revision 6</b>:
+ - Added LogoPixelHeight and LogoPixelWidth
+ <b>Revision 7</b>:
+ - Added SkipFspGop
+ <b>Revision 8</b>:
+ - Added VerticalResolution and HorizontalResolution
+
+**/
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Block Header
+ UINT8 RenderStandby; ///< Offset 28 :<b>(Test)</b> This field is used to enable or disable RC6 (Render Standby): 0=FALSE, <b>1=TRUE</b>
+ UINT8 PmSupport; ///< Offset 29 :<b>(Test)</b> Configure GT to use along with PM Support TRUE/FALSE: 0=FALSE, <b>1=TRUE</b>
+ /**
+ Offset 30
+ CdClock Frequency select\n
+ <b>0xFF = Auto. Max CdClock freq based on Reference Clk</b> \n
+ 0: 192 Mhz, 1: 307.2 Mhz, 2: 312 Mhz, 3: 324 Mhz, 4: 326.4 Mhz, 5: 552 Mhz, 6: 556.8 Mhz, 7: 648 Mhz, 8: 652.8 Mhz
+
+ **/
+ UINT16 CdClock;
+ UINT8 PeiGraphicsPeimInit; ///< Offset 32 : This policy is used to enable/disable Intel Gfx PEIM.<b>0- Disable</b>, 1- Enable
+ UINT8 CdynmaxClampEnable; ///< Offset 33 : This policy is used to enable/disable CDynmax Clamping Feature (CCF) <b>1- Enable</b>, 0- Disable
+ UINT16 GtFreqMax; ///< Offset 34 : <b>(Test)</b> Max GT frequency limited by user in multiples of 50MHz: Default value which indicates normal frequency is <b>0xFF</b>
+ UINT8 DisableTurboGt; ///< Offset 36 : This policy is used to enable/disable DisableTurboGt <b>0- Disable</b>, 1- Enable
+ UINT8 SkipCdClockInit; ///< Offset 37 : SKip full CD clock initialization. <b>0- Disable</b>, 1- Enable
+ UINT8 RC1pFreqEnable; ///< Offset 38 : This policy is used to enable/disable RC1p Frequency. <b>0- Disable</b>, 1- Enable
+ UINT8 PavpEnable; ///< Offset 39 :IGD PAVP TRUE/FALSE: 0=FALSE, <b>1=TRUE</b>
+ VOID* LogoPtr; ///< Offset 40 Address of Intel Gfx PEIM Logo to be displayed
+ UINT32 LogoSize; ///< Offset 44 Intel Gfx PEIM Logo Size
+ VOID* GraphicsConfigPtr; ///< Offset 48 Address of the Graphics Configuration Table
+ VOID* BltBufferAddress; ///< Offset 52 Address of Blt buffer for PEIM Logo use
+ UINT32 BltBufferSize; ///< Offset 56 The size for Blt Buffer, calculating by PixelWidth * PixelHeight * 4 bytes (the size of EFI_GRAPHICS_OUTPUT_BLT_PIXEL)
+ UINT8 ProgramGtChickenBits; ///< Offset 60 Program GT Chicket bits in GTTMMADR + 0xD00 BITS [3:1].
+ UINT8 SkipFspGop; ///< Offset 61 This policy is used to skip PEIM GOP in FSP.<b>0- Use FSP provided GOP driver</b>, 1- Skip FSP provided GOP driver
+ UINT8 Rsvd1[2]; ///< Offset 62 Reserved for 4 bytes alignment
+ UINT32 LogoPixelHeight; ///< Offset 64 Address of LogoPixelHeight for PEIM Logo use
+ UINT32 LogoPixelWidth; ///< Offset 68 Address of LogoPixelWidth for PEIM Logo use
+ UINT32 VerticalResolution; ///< Offset 72 Address of VerticalResolution for PEIM Logo use
+ UINT32 HorizontalResolution; ///< Offset 76 Address of HorizontalResolution for PEIM Logo use
+} GRAPHICS_PEI_CONFIG;
+
+/**
+ This configuration block is to configure IGD related variables used in DXE.
+ If Intel Gfx Device is not supported or disabled, all policies will be ignored.
+ The data elements should be initialized by a Platform Module.\n
+ <b>Revision 1</b>:
+ - Initial version.
+ <b>Revision 2</b>:
+ - Removed IgdDvmtMemSize.
+**/
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Offset 0-27: Config Block Header
+ UINT32 Size; ///< Offset 28 - 31: This field gives the size of the GOP VBT Data buffer
+ EFI_PHYSICAL_ADDRESS VbtAddress; ///< Offset 32 - 39: This field points to the GOP VBT data buffer
+ UINT8 PlatformConfig; ///< Offset 40: This field gives the Platform Configuration Information (0=Platform is S0ix Capable for ULT SKUs only, <b>1=Platform is not S0ix Capable</b>, 2=Force Platform is S0ix Capable for All SKUs)
+ UINT8 AlsEnable; ///< Offset 41: Ambient Light Sensor Enable: <b>0=Disable</b>, 2=Enable
+ UINT8 BacklightControlSupport; ///< Offset 42: Backlight Control Support: 0=PWM Inverted, <b>2=PWM Normal</b>
+ UINT8 IgdBootType; ///< Offset 43: IGD Boot Type CMOS option: <b>0=Default</b>, 0x01=CRT, 0x04=EFP, 0x08=LFP, 0x20=EFP3, 0x40=EFP2, 0x80=LFP2
+ UINT32 IuerStatusVal; ///< Offset 44 - 47: Offset 16 This field holds the current status of all the supported Ultrabook events (Intel(R) Ultrabook Event Status bits)
+ CHAR16 GopVersion[0x10]; ///< Offset 48 - 79:This field holds the GOP Driver Version. It is an Output Protocol and updated by the Silicon code
+ /**
+ Offset 80: IGD Panel Type CMOS option\n
+ <b>0=Default</b>, 1=640X480LVDS, 2=800X600LVDS, 3=1024X768LVDS, 4=1280X1024LVDS, 5=1400X1050LVDS1\n
+ 6=1400X1050LVDS2, 7=1600X1200LVDS, 8=1280X768LVDS, 9=1680X1050LVDS, 10=1920X1200LVDS, 13=1600X900LVDS\n
+ 14=1280X800LVDS, 15=1280X600LVDS, 16=2048X1536LVDS, 17=1366X768LVDS
+ **/
+ UINT8 IgdPanelType;
+ UINT8 IgdPanelScaling; ///< Offset 81: IGD Panel Scaling: <b>0=AUTO</b>, 1=OFF, 6=Force scaling
+ UINT8 IgdBlcConfig; ///< Offset 82: Backlight Control Support: 0=PWM Inverted, <b>2=PWM Normal</b>
+ UINT8 IgdDvmtMemSize; ///< Offset 83: @deprecated IGD DVMT Memory Size: 1=128MB, <b>2=256MB</b>, 3=MAX
+ UINT8 GfxTurboIMON; ///< Offset 84: IMON Current Value: 14=Minimal, <b>31=Maximum</b>
+ UINT8 Reserved[3]; ///< Offset 85: Reserved for DWORD alignment.
+ UINT16 BCLM[MAX_BCLM_ENTRIES]; ///< Offset 88: IGD Backlight Brightness Level Duty cycle Mapping Table.
+} GRAPHICS_DXE_CONFIG;
+#pragma pack(pop)
+
+#endif // _GRAPHICS_CONFIG_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/HostBridge/Ver1/HostBridgeConfig.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/HostBridge/Ver1/HostBridgeConfig.h
new file mode 100644
index 0000000000..11ef7b119c
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/HostBridge/Ver1/HostBridgeConfig.h
@@ -0,0 +1,58 @@
+/** @file
+ Configurations for HostBridge
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _HOST_BRIDGE_CONFIG_H_
+#define _HOST_BRIDGE_CONFIG_H_
+
+#include <ConfigBlock.h>
+
+
+extern EFI_GUID gHostBridgePeiPreMemConfigGuid;
+extern EFI_GUID gHostBridgePeiConfigGuid;
+
+#pragma pack (push,1)
+
+/**
+ This configuration block describes HostBridge settings in PreMem.\n
+ <b>Revision 1</b>:
+ - Initial version.
+**/
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Block Header
+ UINT32 MchBar; ///< Offset 28 Address of System Agent MCHBAR: <b>0xFEDC0000(TGL)/0xFEA80000(JSL)<b>
+ UINT32 DmiBar; ///< Offset 32 Address of System Agent DMIBAR: <b>0xFEDA0000</b>
+ UINT32 EpBar; ///< Offset 36 Address of System Agent EPBAR: <b>0xFEDA1000</b>
+ UINT32 GdxcBar; ///< Offset 40 Address of System Agent GDXCBAR: <b>0xFED84000</b>
+ UINT32 RegBar; ///< Offset 44 Address of System Agent REGBAR: <b>0xFB000000</b>
+ UINT32 EdramBar; ///< Offset 48 Address of System Agent EDRAMBAR: <b>0xFED80000</b>
+ /**
+ Offset 52 :
+ Size of reserved MMIO space for PCI devices\n
+ <b>0=AUTO</b>, 512=512MB, 768=768MB, 1024=1024MB, 1280=1280MB, 1536=1536MB, 1792=1792MB,
+ 2048=2048MB, 2304=2304MB, 2560=2560MB, 2816=2816MB, 3072=3072MB\n
+ When AUTO mode selected, the MMIO size will be calculated by required MMIO size from PCIe devices detected.
+ **/
+ UINT32 MmioSize;
+ UINT32 MmioSizeAdjustment; ///< Offset 56 Increase (given positive value) or Decrease (given negative value) the Reserved MMIO size when Dynamic Tolud/AUTO mode enabled (in MBs): <b>0=no adjustment</b>
+ UINT8 EnableAbove4GBMmio; ///< Offset 60 Enable/disable above 4GB MMIO resource support: 0=Disable, <b>1=Enable</b>
+ UINT8 Reserved[3]; ///< Offset 61 Reserved for future use.
+} HOST_BRIDGE_PREMEM_CONFIG;
+
+
+/**
+ This configuration block describes HostBridge settings in Post-Mem.\n
+ <b>Revision 1</b>:
+ - Initial version.
+**/
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Block Header
+ UINT8 SkipPamLock; ///< Offset 28 :To skip PAM register locking. @note It is still recommended to set PCI Config space B0: D0: F0: Offset 80h[0]=1 in platform code even Silicon code skipped this.\n <b>0=All PAM registers will be locked in Silicon code</b>, 1=Skip lock PAM registers in Silicon code.
+ UINT8 Reserved[3]; ///< Offset 29 Reserved for future use.
+} HOST_BRIDGE_PEI_CONFIG;
+
+#pragma pack (pop)
+
+#endif
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Itss/InterruptConfig.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Itss/InterruptConfig.h
new file mode 100644
index 0000000000..926c7ab6ab
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Itss/InterruptConfig.h
@@ -0,0 +1,38 @@
+/** @file
+ Interrupt policy
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _INTERRUPT_CONFIG_H_
+#define _INTERRUPT_CONFIG_H_
+
+extern EFI_GUID gInterruptConfigGuid;
+
+#pragma pack (push,1)
+
+//
+// --------------------- Interrupts Config ------------------------------
+//
+typedef enum {
+ PchNoInt, ///< No Interrupt Pin
+ PchIntA,
+ PchIntB,
+ PchIntC,
+ PchIntD
+} PCH_INT_PIN;
+
+///
+/// The PCH_DEVICE_INTERRUPT_CONFIG block describes interrupt pin, IRQ and interrupt mode for PCH device.
+///
+typedef struct {
+ UINT8 Device; ///< Device number
+ UINT8 Function; ///< Device function
+ UINT8 IntX; ///< Interrupt pin: INTA-INTD (see PCH_INT_PIN)
+ UINT8 Irq; ///< IRQ to be set for device.
+} PCH_DEVICE_INTERRUPT_CONFIG;
+
+
+#pragma pack (pop)
+
+#endif // _INTERRUPT_CONFIG_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Memory/Ver2/MemoryConfig.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Memory/Ver2/MemoryConfig.h
new file mode 100644
index 0000000000..2be85da5a8
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Memory/Ver2/MemoryConfig.h
@@ -0,0 +1,551 @@
+/** @file
+ Policy definition of Memory Config Block
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _MEMORY_CONFIG_H_
+#define _MEMORY_CONFIG_H_
+
+
+#pragma pack(push, 1)
+
+// MEMORY_CONFIGURATION_REVISION:
+// 3 - Adds DDR5 PDA Enumeration training
+// 4 - Adds LPDDR4 Command Mirroring
+// 5 - Adds PprEnableType
+// 6 - Removed IbeccParity
+// 7 - Adds MarginLimitCheck training within MEMORY_CONFIGURATION
+// 8 - Adds LpddrRttCa, LpddrRttWr
+// 9 - Adds VddqVoltage, VppVoltage
+// 10 - Changes PprEnableType to PprEnable
+// 11 - Changes DisableDimmChannel to DisableChannel
+// 12 - Added DIMMDFE
+// 13 - Added ExtendedBankHashing
+// 14 - Added IBECC Error Injection knobs: IbeccErrInjControl, IbeccErrInjAddress, IbeccErrInjMask, IbeccErrInjCount
+// 15 - Added DynamicMemoryBoost
+// 16 - Added ReuseAdlDdr5Board
+// 17 - Added RefreshWm; Deprecated RefreshPanicWm and RefreshHpWm
+// 18 - Added DebugValue
+// 19 - Added McRefreshRate; Deprecated McRefresh2X
+// 20 - Added RealtimeMemoryFrequency
+// 21 - Added PeriodicDcc and LpMode
+// 22 - Added Tx Dqs Dcc Training
+// 23 - Added tRFCpb, tRFC2, tRFC4, tRRD_L, tRRD_S, tWTR_L, tCCD_L, tWTR_S
+// 24 - Added EccErrInjAddress, EccErrInjMask, EccErrInjCount
+// 25 - Added FreqLimitMixedConfig, FirstDimmBitMask, UserBd
+// 26 - Added SagvSwitchFactorIA/GT/IO/Stall, SagvHeuristicsDownControl, SagvHeuristicsUpControl
+// 27 - Added DRAMDCA
+// 28 - Added FreqLimitMixedConfig_1R1R_8GB, FreqLimitMixedConfig_1R1R_16GB, FreqLimitMixedConfig_1R1R_8GB_16GB, FreqLimitMixedConfig_2R2R
+// 29 - Added LctCmdEyeWidth
+// 30 - Added FirstDimmBitMaskEcc
+// 31 - Added Lp5BankMode
+// 32 - Added WRDS
+// 33 - Added EARLYDIMMDFE for Early DIMM DFE Training
+// 34 - Added OverloadSAM
+#define MEMORY_CONFIGURATION_REVISION 34
+
+// MEMORY_CONFIG_NO_CRC_REVISION:
+// 3 - adds DDR5 SetMemoryPmicVoltage in SA_FUNCTION_CALLS
+#define MEMORY_CONFIG_NO_CRC_REVISION 3
+
+///
+/// MEMORY_CONFIGURATION interface definitions
+///
+#define MRC_MAX_RCOMP_TARGETS 5
+///
+/// Memory SubSystem Definitions
+///
+#define MEM_CFG_MAX_CONTROLLERS 2
+#define MEM_CFG_MAX_CHANNELS 4
+#define MEM_CFG_MAX_DIMMS 2
+#define MEM_CFG_NUM_BYTES_MAPPED 2
+#define MEM_CFG_MAX_SPD_SIZE 1024
+#define MEM_CFG_MAX_SOCKETS (MEM_CFG_MAX_CONTROLLERS * MEM_CFG_MAX_CHANNELS * MEM_CFG_MAX_DIMMS)
+#ifndef MEM_MAX_SAGV_POINTS
+#define MEM_MAX_SAGV_POINTS 4
+#endif
+#define MEM_MAX_IBECC_REGIONS 8
+
+///
+/// SA SPD profile selections.
+///
+typedef enum {
+ DEFAULT_SPD, ///< Standard DIMM profile select.
+ CUSTOM_PROFILE, ///< XMP enthusiast settings: User specifies various override values
+ XMP_PROFILE_1, ///< XMP enthusiast settings: XMP profile #1
+ XMP_PROFILE_2, ///< XMP enthusiast settings: XMP profile #2
+ XMP_PROFILE_3, ///< XMP enthusiast settings: XMP profile #3
+ XMP_USER_PROFILE_4, ///< XMP enthusiast settings: XMP user profile #4
+ XMP_USER_PROFILE_5, ///< XMP enthusiast settings: XMP user profile #5
+ SPDProfileMax = 0xFF ///< Ensures SA_SPD is UINT8
+} SA_SPD;
+
+///
+/// Define the boot modes used by the SPD read function.
+///
+typedef enum {
+ SpdCold, ///< Cold boot
+ SpdWarm, ///< Warm boot
+ SpdS3, ///< S3 resume
+ SpdFast, ///< Fast boot
+ SpdBootModeMax ///< Delimiter
+} SPD_BOOT_MODE;
+
+/**
+ SPD Data Buffer
+**/
+typedef struct {
+ UINT8 SpdData[MEM_CFG_MAX_CONTROLLERS][MEM_CFG_MAX_CHANNELS][MEM_CFG_MAX_DIMMS][MEM_CFG_MAX_SPD_SIZE]; ///< SpdData
+//Next Field Offset 2048
+} SPD_DATA_BUFFER;
+
+/**
+ DqDqs Mapping
+**/
+typedef struct {
+ UINT8 DqsMapCpu2Dram[MEM_CFG_MAX_CONTROLLERS][MEM_CFG_MAX_CHANNELS][MEM_CFG_NUM_BYTES_MAPPED]; ///< DqsMapCpu2Dram
+ UINT8 DqMapCpu2Dram[MEM_CFG_MAX_CONTROLLERS][MEM_CFG_MAX_CHANNELS][MEM_CFG_NUM_BYTES_MAPPED][8]; ///< DqMapCpu2Dram
+//Next Field Offset 16
+} SA_MEMORY_DQDQS_MAPPING;
+
+/**
+ Rcomp Policies
+**/
+typedef struct {
+ UINT16 RcompResistor; ///< Offset 0: Reference RCOMP resistors on motherboard ~ 100 ohms
+ UINT16 RcompTarget[MRC_MAX_RCOMP_TARGETS]; ///< Offset 1: RCOMP target values for DqOdt, DqDrv, CmdDrv, CtlDrv, ClkDrv
+//Next Field Offset 16
+} SA_MEMORY_RCOMP;
+
+/**
+ SPD Offset Table
+**/
+typedef struct {
+ UINT16 Start; ///< Offset 0
+ UINT16 End; ///< Offset 2
+ UINT8 BootMode; ///< Offset 4
+ UINT8 Reserved3[3]; ///< Offset 5 Reserved for future use
+} SPD_OFFSET_TABLE;
+
+///
+/// SA memory address decode.
+///
+typedef struct
+{
+ UINT8 Controller; ///< Offset 0 Zero based Controller number
+ UINT8 Channel; ///< Offset 1 Zero based Channel number
+ UINT8 Dimm; ///< Offset 2 Zero based DIMM number
+ UINT8 Rank; ///< Offset 3 Zero based Rank number
+ UINT8 BankGroup; ///< Offset 4 Zero based Bank Group number
+ UINT8 Bank; ///< Offset 5 Zero based Bank number
+ UINT16 Cas; ///< Offset 6 Zero based CAS number
+ UINT32 Ras; ///< Offset 8 Zero based RAS number
+} SA_ADDRESS_DECODE;
+
+typedef UINT8 (EFIAPI * SA_IO_READ_8) (UINTN IoAddress); ///< CPU I/O port 8-bit read.
+typedef UINT16 (EFIAPI * SA_IO_READ_16) (UINTN IoAddress); ///< CPU I/O port 16-bit read.
+typedef UINT32 (EFIAPI * SA_IO_READ_32) (UINTN IoAddress); ///< CPU I/O port 32-bit read.
+typedef UINT8 (EFIAPI * SA_IO_WRITE_8) (UINTN IoAddress, UINT8 Value); ///< CPU I/O port 8-bit write.
+typedef UINT16 (EFIAPI * SA_IO_WRITE_16) (UINTN IoAddress, UINT16 Value); ///< CPU I/O port 16-bit write.
+typedef UINT32 (EFIAPI * SA_IO_WRITE_32) (UINTN IoAddress, UINT32 Value); ///< CPU I/O port 32-bit write.
+typedef UINT8 (EFIAPI * SA_MMIO_READ_8) (UINTN Address); ///< Memory Mapped I/O port 8-bit read.
+typedef UINT16 (EFIAPI * SA_MMIO_READ_16) (UINTN Address); ///< Memory Mapped I/O port 16-bit read.
+typedef UINT32 (EFIAPI * SA_MMIO_READ_32) (UINTN Address); ///< Memory Mapped I/O port 32-bit read.
+typedef UINT64 (EFIAPI * SA_MMIO_READ_64) (UINTN Address); ///< Memory Mapped I/O port 64-bit read.
+typedef UINT8 (EFIAPI * SA_MMIO_WRITE_8) (UINTN Address, UINT8 Value); ///< Memory Mapped I/O port 8-bit write.
+typedef UINT16 (EFIAPI * SA_MMIO_WRITE_16) (UINTN Address, UINT16 Value); ///< Memory Mapped I/O port 16-bit write.
+typedef UINT32 (EFIAPI * SA_MMIO_WRITE_32) (UINTN Address, UINT32 Value); ///< Memory Mapped I/O port 32-bit write.
+typedef UINT64 (EFIAPI * SA_MMIO_WRITE_64) (UINTN Address, UINT64 Value); ///< Memory Mapped I/O port 64-bit write.
+typedef UINT8 (EFIAPI * SA_SMBUS_READ_8) (UINTN Address, RETURN_STATUS *Status); ///< Smbus 8-bit read.
+typedef UINT16 (EFIAPI * SA_SMBUS_READ_16) (UINTN Address, RETURN_STATUS *Status); ///< Smbus 16-bit read.
+typedef UINT8 (EFIAPI * SA_SMBUS_WRITE_8) (UINTN Address, UINT8 Value, RETURN_STATUS *Status); ///< Smbus 8-bit write.
+typedef UINT16 (EFIAPI * SA_SMBUS_WRITE_16) (UINTN Address, UINT16 Value, RETURN_STATUS *Status); ///< Smbus 16-bit write.
+typedef UINT32 (EFIAPI * SA_GET_PCI_DEVICE_ADDRESS) (UINT8 Bus, UINT8 Device, UINT8 Function, UINT8 Offset); ///< Get PCI device address.
+typedef UINT32 (EFIAPI * SA_GET_PCIE_DEVICE_ADDRESS) (UINT8 Bus, UINT8 Device, UINT8 Function, UINT8 Offset); ///< Get PCI express device address.
+typedef VOID (EFIAPI * SA_GET_RTC_TIME) (UINT8 *Second, UINT8 *Minute, UINT8 *Hour, UINT8 *Day, UINT8 *Month, UINT16 *Year); ///< Get the current time value.
+typedef UINT64 (EFIAPI * SA_GET_CPU_TIME) (VOID); ///< The current CPU time in milliseconds.
+typedef VOID * (EFIAPI * SA_MEMORY_COPY) (VOID *Destination, CONST VOID *Source, UINTN NumBytes); ///< Perform byte copy operation.
+typedef VOID * (EFIAPI * SA_MEMORY_SET_BYTE) (VOID *Buffer, UINTN NumBytes, UINT8 Value); ///< Perform byte initialization operation.
+typedef VOID * (EFIAPI * SA_MEMORY_SET_WORD) (VOID *Buffer, UINTN NumWords, UINT16 Value); ///< Perform word initialization operation.
+typedef VOID * (EFIAPI * SA_MEMORY_SET_DWORD) (VOID *Buffer, UINTN NumDwords, UINT32 Value); ///< Perform dword initialization operation.
+typedef UINT64 (EFIAPI * SA_LEFT_SHIFT_64) (UINT64 Data, UINTN NumBits); ///< Left shift the 64-bit data value by specified number of bits.
+typedef UINT64 (EFIAPI * SA_RIGHT_SHIFT_64) (UINT64 Data, UINTN NumBits); ///< Right shift the 64-bit data value by specified number of bits.
+typedef UINT64 (EFIAPI * SA_MULT_U64_U32) (UINT64 Multiplicand, UINT32 Multiplier); ///< Multiply a 64-bit data value by a 32-bit data value.
+typedef UINT64 (EFIAPI * SA_DIV_U64_U64) (UINT64 Dividend, UINT64 Divisor, UINT64 *Remainder); ///< Divide a 64-bit data value by a 64-bit data value.
+typedef BOOLEAN (EFIAPI * SA_GET_SPD_DATA) (SPD_BOOT_MODE BootMode, UINT8 SpdAddress, UINT8 *Buffer, UINT8 *Ddr3Table, UINT32 Ddr3TableSize, UINT8 *Ddr4Table, UINT32 Ddr4TableSize, UINT8 *LpddrTable, UINT32 LpddrTableSize); ///< Read the SPD data over the SMBus, at the given SmBus SPD address and copy the data to the data structure.
+typedef UINT8 (EFIAPI * SA_GET_MC_ADDRESS_DECODE) (UINT64 Address, SA_ADDRESS_DECODE *DramAddress);
+typedef UINT8 (EFIAPI * SA_GET_MC_ADDRESS_ENCODE) (SA_ADDRESS_DECODE *DramAddress, UINT64 Address);
+typedef BOOLEAN (EFIAPI * SA_GET_RANDOM_NUMBER) (UINT32 *Rand); ///< Get the next random 32-bit number.
+typedef EFI_STATUS (EFIAPI * SA_CPU_MAILBOX_READ) (UINT32 Type, UINT32 Command, UINT32 *Value, UINT32 *Status); ///< Perform a CPU mailbox read.
+typedef EFI_STATUS (EFIAPI * SA_CPU_MAILBOX_WRITE) (UINT32 Type, UINT32 Command, UINT32 Value, UINT32 *Status); ///< Perform a CPU mailbox write.
+typedef UINT32 (EFIAPI * SA_GET_MEMORY_VDD) (VOID *GlobalData, UINT32 DefaultVdd); ///< Get the current memory voltage (VDD).
+typedef UINT32 (EFIAPI * SA_SET_MEMORY_VDD) (VOID *GlobalData, UINT32 DefaultVdd, UINT32 Value); ///< Set the memory voltage (VDD) to the given value.
+typedef UINT32 (EFIAPI * SA_SET_MEMORY_PMIC_VOLTAGE) (VOID *GlobalData, UINT8 SpdAddress, UINT32 Vdd, UINT32 Vddq, UINT32 Vpp); ///< Set DDR5 memory voltages (VDD, VDDQ, VPP) to the given values.
+typedef UINT32 (EFIAPI * SA_CHECKPOINT) (VOID *GlobalData, UINT32 CheckPoint, VOID *Scratch); ///< Check point that is called at various points in the MRC.
+typedef VOID (EFIAPI * SA_DEBUG_HOOK) (VOID *GlobalData, UINT16 DisplayDebugNumber); ///< Typically used to display to the I/O port 80h.
+typedef UINT8 (EFIAPI * SA_CHANNEL_EXIST) (VOID *Outputs, UINT8 Channel); ///< Returns whether Channel is or is not present.
+typedef INT32 (EFIAPI * SA_PRINTF) (VOID *Debug, UINT32 Level, char *Format, ...); ///< Print to output stream/device.
+typedef VOID (EFIAPI * SA_DEBUG_PRINT) (VOID *String); ///< Output a string to the debug stream/device.
+typedef UINT32 (EFIAPI * SA_CHANGE_MARGIN) (VOID *GlobalData, UINT8 Param, INT32 Value0, INT32 Value1, UINT8 EnMultiCast, UINT8 Channel, UINT8 RankIn, UINT8 Byte, UINT8 BitIn, UINT8 UpdateMrcData, UINT8 SkipWait, UINT32 RegFileParam); ///< Change the margin.
+typedef UINT8 (EFIAPI * SA_SIGN_EXTEND) (UINT8 Value, UINT8 OldMsb, UINT8 NewMsb); ///< Sign extends OldMSB to NewMSB Bits (Eg: Bit 6 to Bit 7).
+typedef VOID (EFIAPI * SA_SHIFT_PI_COMMAND_TRAIN) (VOID *GlobalData, UINT8 Channel, UINT8 Iteration, UINT8 RankMask, UINT8 GroupMask, INT32 NewValue, UINT8 UpdateHost); ///< Move CMD/CTL/CLK/CKE PIs during training.
+typedef VOID (EFIAPI * SA_UPDATE_VREF) (VOID *GlobalData, UINT8 Channel, UINT8 RankMask, UINT16 DeviceMask, UINT8 VrefType, INT32 Offset, BOOLEAN UpdateMrcData, BOOLEAN PDAmode, BOOLEAN SkipWait); ///< Update the Vref value and wait until it is stable.
+typedef UINT8 (EFIAPI * SA_GET_RTC_CMOS) (UINT8 Location); ///< Get the current value of the specified RTC CMOS location.
+typedef UINT64 (EFIAPI * SA_MSR_READ_64) (UINT32 Location); ///< Get the current value of the specified MSR location.
+typedef UINT64 (EFIAPI * SA_MSR_WRITE_64) (UINT32 Location, UINT64 Data); ///< Set the current value of the specified MSR location.
+typedef VOID (EFIAPI * SA_MRC_RETURN_FROM_SMC) (VOID *GlobalData, UINT32 MrcStatus); ///< Hook function after returning from MrcStartMemoryConfiguration()
+typedef VOID (EFIAPI * SA_MRC_DRAM_RESET) (UINT32 PciEBaseAddress, UINT32 ResetValue); ///< Assert or deassert DRAM_RESET# pin; this is used in JEDEC Reset.
+typedef VOID (EFIAPI * SA_DELAY_NS) (VOID *GlobalData, UINT32 DelayNs); ///< Delay (stall) for the given amount of nanoseconds.
+typedef VOID (EFIAPI * SA_SET_LOCK_PRMRR) (UINT64 PrmrrBaseAddress, UINT32 PrmrrSize);
+
+
+///
+/// Function calls into the SA.
+///
+typedef struct {
+ SA_IO_READ_8 IoRead8; ///< Offset 0: - CPU I/O port 8-bit read.
+ SA_IO_READ_16 IoRead16; ///< Offset 4: - CPU I/O port 16-bit read.
+ SA_IO_READ_32 IoRead32; ///< Offset 8: - CPU I/O port 32-bit read.
+ SA_IO_WRITE_8 IoWrite8; ///< Offset 12: - CPU I/O port 8-bit write.
+ SA_IO_WRITE_16 IoWrite16; ///< Offset 16: - CPU I/O port 16-bit write.
+ SA_IO_WRITE_32 IoWrite32; ///< Offset 20: - CPU I/O port 32-bit write.
+ SA_MMIO_READ_8 MmioRead8; ///< Offset 24: - Memory Mapped I/O port 8-bit read.
+ SA_MMIO_READ_16 MmioRead16; ///< Offset 28: - Memory Mapped I/O port 16-bit read.
+ SA_MMIO_READ_32 MmioRead32; ///< Offset 32: - Memory Mapped I/O port 32-bit read.
+ SA_MMIO_READ_64 MmioRead64; ///< Offset 36: - Memory Mapped I/O port 64-bit read.
+ SA_MMIO_WRITE_8 MmioWrite8; ///< Offset 40: - Memory Mapped I/O port 8-bit write.
+ SA_MMIO_WRITE_16 MmioWrite16; ///< Offset 44: - Memory Mapped I/O port 16-bit write.
+ SA_MMIO_WRITE_32 MmioWrite32; ///< Offset 48: - Memory Mapped I/O port 32-bit write.
+ SA_MMIO_WRITE_64 MmioWrite64; ///< Offset 52: - Memory Mapped I/O port 64-bit write.
+ SA_SMBUS_READ_8 SmbusRead8; ///< Offset 56: - Smbus 8-bit read.
+ SA_SMBUS_READ_16 SmbusRead16; ///< Offset 60: - Smbus 16-bit read.
+ SA_SMBUS_WRITE_8 SmbusWrite8; ///< Offset 64: - Smbus 8-bit write.
+ SA_SMBUS_WRITE_16 SmbusWrite16; ///< Offset 68: - Smbus 16-bit write.
+ SA_GET_PCI_DEVICE_ADDRESS GetPciDeviceAddress; ///< Offset 72: - Get PCI device address.
+ SA_GET_PCIE_DEVICE_ADDRESS GetPcieDeviceAddress; ///< Offset 76: - Get PCI express device address.
+ SA_GET_RTC_TIME GetRtcTime; ///< Offset 80: - Get the current time value.
+ SA_GET_CPU_TIME GetCpuTime; ///< Offset 84: - The current CPU time in milliseconds.
+ SA_MEMORY_COPY CopyMem; ///< Offset 88: - Perform byte copy operation.
+ SA_MEMORY_SET_BYTE SetMem; ///< Offset 92: - Perform byte initialization operation.
+ SA_MEMORY_SET_WORD SetMemWord; ///< Offset 96: - Perform word initialization operation.
+ SA_MEMORY_SET_DWORD SetMemDword; ///< Offset 100: - Perform dword initialization operation.
+ SA_LEFT_SHIFT_64 LeftShift64; ///< Offset 104: - Left shift the 64-bit data value by specified number of bits.
+ SA_RIGHT_SHIFT_64 RightShift64; ///< Offset 108: - Right shift the 64-bit data value by specified number of bits.
+ SA_MULT_U64_U32 MultU64x32; ///< Offset 112: - Multiply a 64-bit data value by a 32-bit data value.
+ SA_DIV_U64_U64 DivU64x64; ///< Offset 116: - Divide a 64-bit data value by a 64-bit data value.
+ SA_GET_SPD_DATA GetSpdData; ///< Offset 120: - Read the SPD data over the SMBus, at the given SmBus SPD address and copy the data to the data structure.
+ SA_GET_RANDOM_NUMBER GetRandomNumber; ///< Offset 124: - Get the next random 32-bit number.
+ SA_CPU_MAILBOX_READ CpuMailboxRead; ///< Offset 128: - Perform a CPU mailbox read.
+ SA_CPU_MAILBOX_WRITE CpuMailboxWrite; ///< Offset 132: - Perform a CPU mailbox write.
+ SA_GET_MEMORY_VDD GetMemoryVdd; ///< Offset 136: - Get the current memory voltage (VDD).
+ SA_SET_MEMORY_VDD SetMemoryVdd; ///< Offset 140: - Set the memory voltage (VDD) to the given value.
+ SA_CHECKPOINT CheckPoint; ///< Offset 144: - Check point that is called at various points in the MRC.
+ SA_DEBUG_HOOK DebugHook; ///< Offset 148: - Typically used to display to the I/O port 80h.
+ SA_DEBUG_PRINT DebugPrint; ///< Offset 152: - Output a string to the debug stream/device.
+ SA_GET_RTC_CMOS GetRtcCmos; ///< Offset 156: - Get the current value of the specified RTC CMOS location.
+ SA_MSR_READ_64 ReadMsr64; ///< Offset 160: - Get the current value of the specified MSR location.
+ SA_MSR_WRITE_64 WriteMsr64; ///< Offset 164 - Set the current value of the specified MSR location.
+ SA_MRC_RETURN_FROM_SMC MrcReturnFromSmc; ///< Offset 168 - Hook function after returning from MrcStartMemoryConfiguration()
+ SA_MRC_DRAM_RESET MrcDramReset; ///< Offset 172 - Assert or deassert DRAM_RESET# pin; this is used in JEDEC Reset.
+ SA_DELAY_NS MrcDelayNs; ///< Offset 176 - Delay (stall) for the given amount of nanoseconds.
+ SA_SET_MEMORY_PMIC_VOLTAGE SetMemoryPmicVoltage; ///< Offset 180: - Set the memory voltage (VDD/VDDQ/VPP) by PMIC for DDR5.
+} SA_FUNCTION_CALLS;
+
+///
+/// Function calls into the MRC.
+///
+typedef struct {
+ SA_CHANNEL_EXIST MrcChannelExist; ///< Offset 0: - Returns whether Channel is or is not present.
+ SA_PRINTF MrcPrintf; ///< Offset 4: - Print to output stream/device.
+ SA_CHANGE_MARGIN MrcChangeMargin; ///< Offset 8: - Change the margin.
+ SA_SIGN_EXTEND MrcSignExtend; ///< Offset 12: - Sign extends OldMSB to NewMSB Bits (Eg: Bit 6 to Bit 7).
+ SA_SHIFT_PI_COMMAND_TRAIN ShiftPiCommandTrain; ///< Offset 16: - Move CMD/CTL/CLK/CKE PIs during training.
+ SA_UPDATE_VREF MrcUpdateVref; ///< Offset 20: - Update the Vref value and wait until it is stable.
+} SA_MEMORY_FUNCTIONS;
+
+/**
+ Memory Configuration
+ The contents of this structure are CRC'd by the MRC for option change detection.
+ This structure is copied en mass to the MrcInput structure. If you add fields here, you must update the MrcInput structure.
+ Revision history is at the top of this file
+**/
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Block Header
+ UINT16 Size; ///< Offset 28 The size of this structure, in bytes. Must be the first entry in this structure.
+ UINT8 HobBufferSize; ///< Offset 30 Size of HOB buffer for MRC
+
+ UINT8 SpdProfileSelected; ///< Offset 31 SPD XMP profile selection - for XMP supported DIMM: <b>0=Default DIMM profile</b>, 1=Custom Profile, 2=XMP Profile 1, 3=XMP Profile 2, 4=XMP Profile 3, 5=XMP User Profile 4, 6=XMP User Profile 5
+
+ // The following parameters are used only when SpdProfileSelected is User Defined (CUSTOM_PROFILE)
+ UINT16 tCL; ///< Offset 32 User defined Memory Timing tCL value, valid when SpdProfileSelected is CUSTOM_PROFILE: <b>0=AUTO</b>, 31=Maximum.
+ UINT16 tRCDtRP; ///< Offset 34 User defined Memory Timing tRCD value (same as tRP), valid when SpdProfileSelected is CUSTOM_PROFILE: <b>0=AUTO</b>, 63=Maximum
+ UINT16 tRAS; ///< Offset 36 User defined Memory Timing tRAS value, valid when SpdProfileSelected is CUSTOM_PROFILE: <b>0=AUTO</b>, 64=Maximum.
+ UINT16 tWR; ///< Offset 38 User defined Memory Timing tWR value, valid when SpdProfileSelected is CUSTOM_PROFILE: <b>0=AUTO</b>, legal values: 5, 6, 7, 8, 10, 12, 14, 16, 18, 20, 24.
+ UINT16 tRFC; ///< Offset 40 User defined Memory Timing tRFC value, valid when SpdProfileSelected is CUSTOM_PROFILE: <b>0=AUTO</b>, 1023=Maximum.
+ UINT16 tRRD; ///< Offset 42 User defined Memory Timing tRRD value, valid when SpdProfileSelected is CUSTOM_PROFILE: <b>0=AUTO</b>, 15=Maximum.
+ UINT16 tWTR; ///< Offset 44 User defined Memory Timing tWTR value, valid when SpdProfileSelected is CUSTOM_PROFILE: <b>0=AUTO</b>, 28=Maximum.
+ UINT16 tRTP; ///< Offset 46 User defined Memory Timing tRTP value, valid when SpdProfileSelected is CUSTOM_PROFILE: <b>0=AUTO</b>, 15=Maximum. DDR4 legal values: 5, 6, 7, 8, 9, 10, 12
+ UINT16 tFAW; ///< Offset 48 User defined Memory Timing tFAW value, valid when SpdProfileSelected is CUSTOM_PROFILE: <b>0=AUTO</b>, 63=Maximum.
+ UINT16 tCWL; ///< Offset 50 User defined Memory Timing tCWL value, valid when SpdProfileSelected is CUSTOM_PROFILE: <b>0=AUTO</b>, 20=Maximum.
+ UINT16 tREFI; ///< Offset 52 User defined Memory Timing tREFI value, valid when SpdProfileSelected is CUSTOM_PROFILE: <b>0=AUTO</b>, 65535=Maximum.
+ UINT16 PciIndex; ///< Offset 54 Pci index register address: <b>0xCF8=Default</b>
+ UINT16 PciData; ///< Offset 56 Pci data register address: <b>0xCFC=Default</b>
+ UINT16 VddVoltage; ///< Offset 58 DRAM voltage (Vdd) in millivolts: <b>0=Platform Default (no override)</b>, 1200=1.2V, 1350=1.35V etc.
+ UINT16 Idd3n; ///< Offset 60 EPG Active standby current (Idd3N) in milliamps from DIMM datasheet.
+ UINT16 Idd3p; ///< Offset 62 EPG Active power-down current (Idd3P) in milliamps from DIMM datasheet.
+
+ UINT32 EccSupport:1; ///< Offset 64 Bit 0 - DIMM Ecc Support option - for Desktop only: 0=Disable, <b>1=Enable</b>
+ UINT32 MrcSafeConfig:1; ///< Bit 1 - MRC Safe Mode: <b>0=Disable</b>, 1=Enable
+ UINT32 RemapEnable:1; ///< Bit 2 - This option is used to control whether to enable/disable memory remap above 4GB: 0=Disable, <b>1=Enable</b>.
+ UINT32 ScramblerSupport:1; ///< Bit 3 - Memory scrambler support: 0=Disable, <b>1=Enable</b>
+ UINT32 Vc1ReadMeter:1; ///< Bit 4 - VC1 Read Metering Enable: 0=Disable, <b>1=Enable</b>
+ UINT32 ForceSingleSubchannel:1; ///< Bit 5 - TRUE means use SubChannel0 only (for LPDDR4): <b>0=Disable</b>, 1=Enable
+ UINT32 SimicsFlag:1; ///< Bit 6 - Option to Enable SIMICS: 0=Disable, <b>1=Enable</b>
+ UINT32 Ddr4DdpSharedClock:1; ///< Bit 7 - Select if CLK0 is shared between Rank0 and Rank1 in DDR4 DDP package. <b>0=Not shared</b>, 1=Shared
+ UINT32 SharedZqPin:1; ///< Bit 8 - Select if the ZQ resistor is shared between Ranks in DDR4/LPDDR4 DRAM Packages <b>0=Not Shared</b>, 1=Shared
+ UINT32 LpDqsOscEn:1; ///< Bit 9 - LPDDR Write DQ/DQS Retraining: 0=Disable, <b>1=Enable</b>
+ UINT32 RmtPerTask:1; ///< Bit 10 - Rank Margin Tool Per Task. <b>0 = Disabled</b>, 1 = Enabled
+ UINT32 TrainTrace:1; ///< Bit 11 - Trained state tracing debug. <b>0 = Disabled</b>, 1 = Enabled
+ UINT32 SafeMode:1; ///< Bit 12 - Define if safe mode is enabled for MC/IO
+ UINT32 MsHashEnable:1; ///< Bit 13 - Controller Hash Enable: 0=Disable, <b>1=Enable</b>
+ UINT32 DisPgCloseIdleTimeout:1; ///< Bit 14 - Disable Page Close Idle Timeout: 0=Enable, <b>1=Disable</b>
+ UINT32 Ibecc:1; ///< Bit 15 - In-band ECC: <b>0=Disable</b>, 1=Enable
+ UINT32 IbeccOperationMode:2; ///< Bits 16:17 - In-band ECC Operation Mode: 0=Functional Mode protects requests based on the address range, 1=Makes all requests non protected and ignore range checks, <b>2=Makes all requests protected and ignore range checks</b>
+ UINT32 ChHashOverride:1; ///< Bit 18 - Select if Channel Hash setting values will be taken from input parameters or automatically taken from POR values depending on DRAM type detected.
+ UINT32 EccDftEn:1; ///< Bit 19 - ECC DFT support option
+ UINT32 Write0:1; ///< Bit 20 - Write0 feature (LP5/DDR5): 0=Disable, <b>1=Enable</b>
+ UINT32 ReuseAdlSDdr5Board:1; ///< Bit 21 - Indicate whether adl ddr5 board is reused.
+ UINT32 PeriodicDcc:1; ///< Bit 22 - Periodic DCC: <b>0=Disable</b>, 1=Enable
+ UINT32 LpMode:2; ///< Bit 23:24 - LPMode: <b>0=Auto</b>, 1=Enabled, 2=Disabled, 3=Reserved
+ UINT32 RsvdO64B25to31:7; ///< Bits 25:31 reserved
+ UINT8 DisableChannel[MEM_CFG_MAX_CONTROLLERS][MEM_CFG_MAX_CHANNELS]; ///< Offset 68-75
+ UINT8 Ratio; ///< Offset 76 DDR Frequency ratio, to multiply by 133 or 100 MHz depending on RefClk. <b>0 = Auto</b>
+ UINT8 ProbelessTrace; ///< Offset 77 Probeless Trace: <b>0=Disabled</b>, <b>1=Enabled</b>
+ /**
+ Channel Hash Enable.\n
+ NOTE: BIT7 will interleave the channels at a 2 cache-line granularity, BIT8 at 4 and BIT9 at 8\n
+ 0=BIT6, <B>1=BIT7</B>, 2=BIT8, 3=BIT9
+ **/
+ UINT8 ChHashInterleaveBit; ///< Offset 78 Option to select interleave Address bit. Valid values are 0 - 3 for BITS 6 - 9 (Valid values for BDW are 0-7 for BITS 6 - 13)
+ UINT8 SmramMask; ///< Offset 79 Reserved memory ranges for SMRAM
+ UINT32 BClkFrequency; ///< Offset 80 Base reference clock value, in Hertz: <b>100000000 = 100Hz</b>, 125000000=125Hz, 167000000=167Hz, 250000000=250Hz
+
+ /// Training Algorithms 1 Offset 84
+ UINT32 ECT:1; ///< Bit 0 - Enable/Disable Early Command Training. Note it is not recommended to change this setting from the default value: <b>0=Disable</b>, 1=Enable.
+ UINT32 SOT:1; ///< Bit 1 - Enable/Disable Sense Amp Offset Training. Note it is not recommended to change this setting from the default value: 0=Disable, <b>1=Enable</b>.
+ UINT32 ERDMPRTC2D:1; ///< Bit 2 - Enable/Disable Early ReadMPR Timing Centering 2D. Note it is not recommended to change this setting from the default value: 0=Disable, <b>1=Enable</b>.
+ UINT32 RDMPRT:1; ///< Bit 3 - Enable/Disable Read MPR Training. Note it is not recommended to change this setting from the default value: 0=Disable, <b>1=Enable</b>.
+ UINT32 RCVET:1; ///< Bit 4 - Enable/Disable Receive Enable Training. Note it is not recommended to change this setting from the default value: 0=Disable, <b>1=Enable</b>.
+ UINT32 JWRL:1; ///< Bit 5 - Enable/Disable JEDEC Write Leveling Training. Note it is not recommended to change this setting from the default value: 0=Disable, <b>1=Enable</b>.
+ UINT32 EWRTC2D:1; ///< Bit 6 - Enable/Disable Early Write Time Centering 2D Training. Note it is not recommended to change this setting from the default value: 0=Disable, <b>1=Enable</b>.
+ UINT32 ERDTC2D:1; ///< Bit 7 - Enable/Disable Early Read Time Centering 2D Training. Note it is not recommended to change this setting from the default value: 0=Disable, <b>1=Enable</b>.
+ UINT32 WRTC1D:1; ///< Bit 8 - Enable/Disable 1D Write Timing Centering Training. Note it is not recommended to change this setting from the default value: 0=Disable, <b>1=Enable</b>.
+ UINT32 WRVC1D:1; ///< Bit 9 - Enable/Disable 1D Write Voltage Centering Training. Note it is not recommended to change this setting from the default value: 0=Disable, <b>1=Enable</b>.
+ UINT32 RDTC1D:1; ///< Bit 10 - Enable/Disable 1D Read Timing Centering Training. Note it is not recommended to change this setting from the default value: 0=Disable, <b>1=Enable</b>.
+ UINT32 DIMMODTT:1; ///< Bit 11 - Enable/Disable DIMM ODT Training. Note it is not recommended to change this setting from the default value: <b>0=Disable</b>, 1=Enable.
+ UINT32 DIMMRONT:1; ///< Bit 12 - Enable/Disable DIMM RON training. Note it is not recommended to change this setting from the default value: 0=Disable, <b>1=Enable</b>.
+ UINT32 WRDSEQT:1; ///< Bit 13 - Enable/Disable Write Drive Strength / Equalization Training 2D. Note it is not recommended to change this setting from the default value: <b>0=Disable</b>, 1=Enable.
+ UINT32 WRSRT:1; ///< Bit 14 - Enable/Disable Write Slew Rate traning. Note it is not recommended to change this setting from the default value: 0=Disable, <b>1=Enable.</b>
+ UINT32 RDODTT:1; ///< Bit 15 - Enable/Disable Read ODT Training. Note it is not recommended to change this setting from the default value: <b>0=Disable</b>, 1=Enable.
+ UINT32 RDEQT:1; ///< Bit 16 - Enable/Disable Read Equalization Training. Note it is not recommended to change this setting from the default value: <b>0=Disable</b>, 1=Enable.
+ UINT32 RDAPT:1; ///< Bit 17 - Enable/Disable Read Amplifier Power Training. Note it is not recommended to change this setting from the default value: <b>0=Disable</b>, 1=Enable.
+ UINT32 WRTC2D:1; ///< Bit 18 - Enable/Disable 2D Write Timing Centering Training. Note it is not recommended to change this setting from the default value: 0=Disable, <b>1=Enable</b>.
+ UINT32 RDTC2D:1; ///< Bit 19 - Enable/Disable 2D Read Timing Centering Training. Note it is not recommended to change this setting from the default value: 0=Disable, <b>1=Enable</b>.
+ UINT32 WRVC2D:1; ///< Bit 20 - Enable/Disable 2D Write Voltage Centering Training. Note it is not recommended to change this setting from the default value: 0=Disable, <b>1=Enable</b>.
+ UINT32 RDVC2D:1; ///< Bit 21 - Enable/Disable 2D Read Voltage Centering Training. Note it is not recommended to change this setting from the default value: 0=Disable, <b>1=Enable</b>.
+ UINT32 CMDVC:1; ///< Bit 22 - Enable/Disable Command Vref Centering Training. Note it is not recommended to change this setting from the default value 0=Disable, <b>1=Enable</b>.
+ UINT32 LCT:1; ///< Bit 23 - Enable/Disable Late Command Training. Note it is not recommended to change this setting from the default value: 0=Disable, <b>1=Enable</b>.
+ UINT32 RTL:1; ///< Bit 24 - Enable/Disable Round Trip Latency function. Note it is not recommended to change this setting from the default value: 0=Disable, <b>1=Enable</b>.
+ UINT32 TAT:1; ///< Bit 25 - Enable/Disable Turn Around Time function. Note it is not recommended to change this setting from the default value: <b>0=Disable</b>, 1=Enable.
+ UINT32 RMT:1; ///< Bit 26 - Enable/Disable Rank Margin Tool function: <b>0=Disable</b>, 1=Enable.
+ UINT32 MEMTST:1; ///< Bit 27 - Enable/Disable Memory Test function: <b>0=Disable</b>, 1=Enable.
+ UINT32 ALIASCHK:1; ///< Bit 28 - Enable/Disable DIMM SPD Alias Check: 0=Disable, <b>1=Enable</b>
+ UINT32 RCVENC1D:1; ///< Bit 29 - Enable/Disable Receive Enable Centering Training (LPDDR Only). Note it is not recommended to change this setting from the default value: <b>0=Disable</b>, 1=Enable
+ UINT32 RMC:1; ///< Bit 30 - Enable/Disable Retrain Margin Check. Note it is not recommended to change this setting from the default value: <b>0=Disable</b>, 1=Enable
+ UINT32 WRDSUDT:1; ///< Bit 31 - Enable/Disable Write Drive Strength Up/Dn independently. Note it is not recommended to change this setting from the default value: <b>0=Disable</b>, 1=Enable
+ /// Training Algorithms 2 Offset 88
+ UINT32 DCC : 1; ///< Bit 0 - Enable/Disable Duty Cycle Correction: 0=Disable, 1=Enable.
+ UINT32 RDVC1D : 1; ///< Bit 1 - Enable/Disable Read Voltage Centering 1D: 0=Disable, 1=Enable.
+ UINT32 TXTCO : 1; ///< Bit 2 - Enable/Disable Write TCO Comp Training: 0=Disable, 1=Enable.
+ UINT32 CLKTCO : 1; ///< Bit 3 - Enable/Disable Clock TCO Comp Training: 0=Disable, 1=Enable.
+ UINT32 CMDSR : 1; ///< Bit 4 - Enable/Disable CMD Slew Rate Training: 0=Disable, 1=Enable.
+ UINT32 CMDDSEQ : 1; ///< Bit 5 - Enable/Disable CMD Drive Strength and Tx Equalization: 0=Disable, 1=Enable.
+ UINT32 DIMMODTCA : 1; ///< Bit 6 - Enable/Disable Dimm ODT CA Training: 0=Disable, 1=Enable.
+ UINT32 TXTCODQS : 1; ///< Bit 7 - Enable/Disable Write TCO Dqs Training: 0=Disable, 1=Enable.
+ UINT32 CMDDRUD : 1; ///< Bit 8 - Enable/Disable CMD/CTL Drive Strength Up/Dn 2D: 0=Disable, 1=Enable.
+ UINT32 VCCDLLBP : 1; ///< Bit 9 - Enable/Disable VccDLL bypass to VccIOG training: 0=Disable, 1=Enable.
+ UINT32 PVTTDNLP : 1; ///< Bit 10 - Enable/Disable PanicVttDnLp Training: 0=Disable, 1=Enable.
+ UINT32 RDVREFDC : 1; ///< Bit 11 - Enable/Disable Read Vref Decap Training: 0=Disable, 1=Enable.
+ UINT32 VDDQT : 1; ///< Bit 12 - Enable/Disable Vddq Training: 0=Disable, 1=Enable.
+ UINT32 RMTBIT : 1; ///< Bit 13 - Enable/Disable Rank Margin Tool Per Bit: 0=Disable, 1=Enable.
+ UINT32 PDA : 1; ///< BIT 14 - Enable/Disable PDA Enumeration Training. Note it is not recommended to change this setting from the default value: 0=Disable, <b>1=Enable</b>.
+ UINT32 DIMMDFE : 1; ///< BIT 15 - Enable/Disable DIMM DFE Training: 0=Disable, <b>1=Enable</b>.
+ UINT32 TXDQSDCC : 1; ///< BIT 16 - Enable/Disable TX DQS DCC Training: 0=Disable, <b>1=Enable</b>.
+ UINT32 DRAMDCA : 1; ///< BIT 17 - Enable/Disable DRAM DCA Training: 0=Disable, <b>1=Enable</b>.
+ UINT32 WRDS : 1; ///< BIT 18 - Enable/Disable Write Driver Strength Training: 0=Disable, <b>1=Enable</b>.
+ UINT32 EARLYDIMMDFE : 1; ///< BIT 19 - Enable/Disable EARLY DIMM DFE Training: 0=Disable, <b>1=Enable</b>.
+ UINT32 ReservedBits2 :12; ///< Bits 20:31 - Reserved
+
+ UINT32 MrcTimeMeasure:1; ///< Offset 92 Bit 0 - Enables serial debug level to display the MRC execution times only: <b>0=Disable</b>, 1=Enable
+ UINT32 MrcFastBoot:1; ///< Bit 1 - Enables the MRC fast boot path for faster cold boot execution: 0=Disable, <b>1=Enable</b>
+ UINT32 DqPinsInterleaved:1; ///< Bit 2 - Interleaving mode of DQ/DQS pins which depends on board routing: <b>0=Disable</b>, 1=Enable
+ UINT32 RankInterleave:1; ///< Bit 3 - Rank Interleave Mode: 0=Disable, <b>1=Enable</b>
+ UINT32 EnhancedInterleave:1; ///< Bit 4 - Enhanced Interleave Mode: 0=Disable, <b>1=Enable</b>
+ UINT32 WeaklockEn:1; ///< Bit 5 - Weak Lock Enable: 0=Disable, <b>1=Enable</b>
+ UINT32 ChHashEnable:1; ///< Bit 6 - Channel Hash Enable: 0=Disable, <b>1=Enable</b>
+ UINT32 EnablePwrDn:1; ///< Bit 7 - Enable Power Down control for DDR: 0=PCODE control, <b>1=BIOS control</b>
+ UINT32 EnablePwrDnLpddr:1; ///< Bit 8 - Enable Power Down for LPDDR: 0=PCODE control, <b>1=BIOS control</b>
+ UINT32 SrefCfgEna:1; ///< Bit 9 - Enable Self Refresh: 0=Disable, <b>1=Enable</b>
+ UINT32 ThrtCkeMinDefeatLpddr:1; ///< Bit 10 - Throttler CKE min defeature for LPDDR: 0=Disable, <b>1=Enable</b>
+ UINT32 ThrtCkeMinDefeat:1; ///< Bit 11 - Throttler CKE min defeature: <b>0=Disable</b>, 1=Enable
+ UINT32 AutoSelfRefreshSupport:1; ///< Bit 12 - FALSE = No auto self refresh support, <b>TRUE = auto self refresh support</b>
+ UINT32 ExtTemperatureSupport:1; ///< Bit 13 - FALSE = No extended temperature support, <b>TRUE = extended temperature support</b>
+ UINT32 MobilePlatform:1; ///< Bit 14 - Memory controller device id indicates: <b>TRUE if mobile</b>, FALSE if not. Note: This will be auto-detected and updated.
+ UINT32 Force1Dpc:1; ///< Bit 15 - TRUE means force one DIMM per channel, <b>FALSE means no limit</b>
+ UINT32 ForceSingleRank:1; ///< Bit 16 - TRUE means use Rank0 only (in each DIMM): <b>0=Disable</b>, 1=Enable
+ UINT32 VttTermination:1; ///< Bit 17 - Vtt Termination for Data ODT: <b>0=Disable</b>, 1=Enable
+ UINT32 VttCompForVsshi:1; ///< Bit 18 - Enable/Disable Vtt Comparator For Vsshi: <b>0=Disable</b>, 1=Enable
+ UINT32 ExitOnFailure:1; ///< Bit 19 - MRC option for exit on failure or continue on failure: 0=Disable, <b>1=Enable</b>
+ UINT32 NewFeatureEnable1:1; ///< Bit 20 - Generic enable knob for new feature set 1 <b>0: Disable </b>; 1: Enable
+ UINT32 NewFeatureEnable2:1; ///< Bit 21 - Generic enable knob for new feature set 2 <b>0: Disable </b>; 1: Enable
+ UINT32 RhSelect:2; ///< Bit 22-23 - RH Select: <b>0=Disable</b>, 1=RFM, 2=pTRR
+ UINT32 RefreshPanicWm:4; ///< Bit 24-27 - Deprecated from revision 17. Use RefreshWm instead.
+ UINT32 RefreshHpWm:4; ///< Bit 28-31 - Deprecated from revision 17. Use RefreshWm instead.
+ UINT32 VddSettleWaitTime; ///< Offset 96 Amount of time in microseconds to wait for Vdd to settle on top of 200us required by JEDEC spec: <b>Default=0</b>
+ UINT16 SrefCfgIdleTmr; ///< Offset 100 Self Refresh idle timer: <b>512=Minimal</b>, 65535=Maximum
+ UINT16 ChHashMask; ///< Offset 102 Channel Hash Mask: 0x0001=BIT6 set(Minimal), 0x3FFF=BIT[19:6] set(Maximum), <b>0x30CE= BIT[19:18, 13:12 ,9:7] set</b>
+ UINT16 DdrFreqLimit; ///< Offset 104 Memory Frequency limit: <b>0 = Auto</b>, or memory speed value in MT/s: 1067, 1333, 1600 etc. See the possible values in MrcInterface.h
+ UINT8 MaxRttWr; ///< Offset 106 Maximum DIMM RTT_WR to use in power training: <b>0=ODT Off</b>, 1 = 120 ohms
+ UINT8 ThrtCkeMinTmr; ///< Offset 107 Throttler CKE min timer: 0=Minimal, 0xFF=Maximum, <b>0x00=Default</b>
+ UINT8 ThrtCkeMinTmrLpddr; ///< Offset 108 Throttler CKE min timer for LPDDR: 0=Minimal, 0xFF=Maximum, <b>0x00=Default</b>
+ BOOLEAN PerBankRefresh; ///< Offset 109 Enables and Disables the per bank refresh. This only impacts memory technologies that support PBR: LPDDR4, LPDDR5 and DDR5. FALSE=Disabled, <b>TRUE=Enabled</b>
+ UINT8 SaGv; ///< Offset 110 SA GV: <b>0=Disabled</b>, 1=Point1, 2=Point2, 3=Point3, 4=Point4, 5=Enabled
+ UINT8 NModeSupport; ///< Offset 111 Memory N Mode Support - Enable user to select Auto, 1N or 2N: <b>0=AUTO</b>, 1=1N, 2=2N.
+ UINT8 RefClk; ///< Offset 112 Selects the DDR base reference clock. 0x01 = 100MHz, <b>0x00 = 133MHz</b>
+ UINT8 EnCmdRate; ///< Offset 113 CMD Rate Enable: 0=Disable, 5=2 CMDs, <b>7=3 CMDs</b>, 9=4 CMDs, 11=5 CMDs, 13=6 CMDs, 15=7 CMDs
+ UINT8 Refresh2X; ///< Offset 114 Refresh 2x: <b>0=Disable</b>, 1=Enable for WARM or HOT, 2=Enable for HOT only
+ UINT8 EpgEnable; ///< Offset 115 Enable Energy Performance Gain.
+ UINT8 UserThresholdEnable; ///< Offset 116 Flag to manually select the DIMM CLTM Thermal Threshold, 0=Disable, 1=Enable, <b>0=Default</b>
+ UINT8 UserBudgetEnable; ///< Offset 117 Flag to manually select the Budget Registers for CLTM Memory Dimms , 0=Disable, 1=Enable, <b>0=Default</b>
+ UINT8 RetrainOnFastFail; ///< Offset 118 Restart MRC in Cold mode if SW MemTest fails during Fast flow. 0 = Disabled, <b>1 = Enabled</b>
+ UINT8 PowerDownMode; ///< Offset 119 CKE Power Down Mode: <b>0xFF=AUTO</b>, 0=No Power Down, 1= APD mode, 6=PPD-DLL Off mode
+ UINT8 PwdwnIdleCounter; ///< Offset 120 CKE Power Down Mode Idle Counter: 0=Minimal, 255=Maximum, <b>0x80=0x80 DCLK</b>
+ UINT8 CmdRanksTerminated; ///< Offset 121 LPDDR: Bitmask of ranks that have CA bus terminated. <b>0x01=Default, Rank0 is terminating and Rank1 is non-terminating</b>
+ UINT16 MsHashMask; ///< Offset 122 Controller Hash Mask: 0x0001=BIT6 set(Minimal), 0x3FFF=BIT[19:6] set(Maximum), <b>0x30CE= BIT[19:18, 13:12 ,9:7] set</b>
+ UINT32 Lp5CccConfig; ///< Offset 124 BitMask where bits [3:0] are controller 0 Channel [3:0] and [7:4] are Controller 1 Channel [3:0]. 0 selects Ascending mapping and 1 selects Descending mapping.
+ UINT8 RMTLoopCount; ///< Offset 128 Indicates the Loop Count to be used for Rank Margin Tool Testing: 1=Minimal, 32=Maximum, 0=AUTO, <b>0=Default</b>
+ UINT8 MsHashInterleaveBit; ///< Offset 129 Option to select interleave Address bit. Valid values are 0 - 3 for BITS 6 - 9
+ UINT8 GearRatio; ///< Offset 130 Gear mode when SAGV is disabled: <b>0=Auto</b>, 1 - Gear1, 2 - Gear2, 4 - Gear4.
+ UINT8 Ddr4OneDpc; ///< Offset 131 DDR4 1DPC performance feature: 0 - Disabled; 1 - Enabled on DIMM0 only, 2 - Enabled on DIMM1 only; 3 - Enabled on both DIMMs. (bit [0] - DIMM0, bit [1] - DIMM1)
+ UINT32 BclkRfiFreq[MEM_MAX_SAGV_POINTS]; ///< Offset 132 Bclk RFI Frequency for each SAGV point in Hz units. 98000000Hz = 98MHz <b>0 - No RFI Tuning</b>. Range is 98Mhz-100Mhz.
+ UINT16 SaGvFreq[MEM_MAX_SAGV_POINTS]; ///< Offset 148 Frequency per SAGV point. 0 is Auto, otherwise holds the frequency value expressed as an integer: <b>0=Default</b>, 1067, 1333, 1600, 1800, 1867, etc.
+ UINT8 SaGvGear[MEM_MAX_SAGV_POINTS]; ///< Offset 156 Gear ratio per SAGV point. 0 is Auto, otherwise holds the Gear ratio expressed as an integer: <b>0=Auto</b>, 1, 2, 4
+ UINT8 IbeccProtectedRangeEnable[MEM_MAX_IBECC_REGIONS]; ///< Offset 160 Enable use of address range for ECC Protection: <b>0=Disabled</b>, 1=Enabled
+ UINT32 IbeccProtectedRangeBase[MEM_MAX_IBECC_REGIONS]; ///< Offset 168 Base address for address range of ECC Protection: [0..0x3FFFFFF]
+ UINT32 IbeccProtectedRangeMask[MEM_MAX_IBECC_REGIONS]; ///< Offset 200 Mask address for address range of ECC Protection: [1..0x3FFFFFF]
+
+ UINT8 McRefresh2X; ///< Offset 232 Deprecated from revision 19, use McRefreshRate instead
+ UINT8 Lfsr0Mask; ///< Offset 233 RH pTRR LFSR0 Mask
+ UINT8 Lfsr1Mask; ///< Offset 234 RH pTRR LFSR1 Mask
+ UINT8 CmdMirror; ///< Offset 235 BitMask where bits [3:0] are controller 0 Channel [3:0] and [7:4] are Controller 1 Channel [3:0]. 0 = No Command Mirror and 1 = Command Mirror.
+ UINT8 AllowOppRefBelowWriteThrehold; ///< Offset 236 Option to allow opportunistic refreshes while we don't exit power down.
+ UINT8 WriteThreshold; ///< Offset 237 Option to set number of writes that can be accumulated while CKE is low before CKE is asserted.
+ UINT8 PprEnable; ///< Offset 238 Post-Package Repair: 0: Disabled, 2: Hard PPR
+ UINT8 MarginLimitCheck; ///< Offset 239 Margin limit check enable: <b>0=Disable</b>, 1=L1 only, 2=L2 only, 3=Both L1 and L2
+ UINT16 MarginLimitL2; ///< Offset 240 Margin limit check L2 threshold: <b>100=Default</b>
+ UINT8 LpddrRttWr; ///< Offset 242 Initial RttWr for LP4/5 in Ohms, 0 means Auto
+ UINT8 LpddrRttCa; ///< Offset 243 Initial RttCa for LP4/5 in Ohms, 0 means Auto
+ UINT16 VddqVoltage; ///< Offset 244 DRAM voltage (Vddq) in millivolts: <b>0=Platform Default (no override)</b>, 1200=1.2V, 1350=1.35V etc.
+ UINT16 VppVoltage; ///< Offset 246 DRAM voltage (Vpp) in millivolts: <b>0=Platform Default (no override)</b>, 1800=1.8V, 2050=2.05V etc.
+ UINT8 ExtendedBankHashing; ///< Offset 248 Enable EBH (Extended Bank Hashing): 0=Disabled; <b>1 = Enabled</b>
+ UINT8 DynamicMemoryBoost; ///< Offset 249 Enable/Disable Dynamic Memory Boost Feature. Only valid if SpdProfileSelected is an XMP Profile; otherwise ignored. <b>0=Disabled</b>, 1=Enabled.
+ UINT8 IbeccErrInjControl; ///< Offset 250 In-band ECC: Error Injection Control 0: No Error Injection, 1:Inject Correctable Error Address match, 3:Inject Correctable Error on insertion counter, 5: Inject Uncorrectable Error Address match, 7:Inject Uncorrectable Error on insertion counter
+ UINT8 RealtimeMemoryFrequency; ///< Offset 251 Enable/Disable Realtime Memory Frequency feature. Only valid if SpdProfileSelected is an XMP Profile; otherwise ignored. <b>0=Disabled</b>, 1=Enabled.
+ UINT32 IbeccErrInjCount; ///< Offset 252 Number of transactions between ECC error injection
+ UINT64 IbeccErrInjAddress; ///< Offset 256 Address to match against for ECC error injection
+ UINT64 IbeccErrInjMask; ///< Offset 264 Mask to match against for ECC error injection
+ UINT8 RefreshWm; ///< Offset 272 Refresh Watermarks, 0 = Low, <b>1 = High</b>
+ UINT8 McRefreshRate; ///< Offset 273 Type of solution to be used for RHP - 0/1/2/3 = RefreshNORMAL/Refresh1x/Refresh2x/Refresh4x
+ UINT8 Reserved274[2]; ///< Offset 274-275 Reserved for natural alignment
+ UINT32 DebugValue; ///< Offset 276 Debug Value for general use
+ UINT16 tRFCpb; ///< Offset 280 User defined Memory Timing tRFCpb value, valid when SpdProfileSelected is CUSTOM_PROFILE: <b>0=AUTO</b>, 28=Maximum.
+ UINT16 tRFC2; ///< Offset 282 User defined Memory Timing tRFC2 value, valid when SpdProfileSelected is CUSTOM_PROFILE: <b>0=AUTO</b>, 28=Maximum.
+ UINT16 tRFC4; ///< Offset 284 User defined Memory Timing tRFC4 value, valid when SpdProfileSelected is CUSTOM_PROFILE: <b>0=AUTO</b>, 28=Maximum.
+ UINT16 tRRD_L; ///< Offset 286 User defined Memory Timing tRRD_L value, valid when SpdProfileSelected is CUSTOM_PROFILE: <b>0=AUTO</b>, 28=Maximum.
+ UINT16 tRRD_S; ///< Offset 288 User defined Memory Timing tRRD_S value, valid when SpdProfileSelected is CUSTOM_PROFILE: <b>0=AUTO</b>, 28=Maximum.
+ UINT16 tWTR_L; ///< Offset 290 User defined Memory Timing tWTR_L value, valid when SpdProfileSelected is CUSTOM_PROFILE: <b>0=AUTO</b>, 28=Maximum.
+ UINT16 tCCD_L; ///< Offset 292 User defined Memory Timing tCCD_L value, valid when SpdProfileSelected is CUSTOM_PROFILE: <b>0=AUTO</b>, 28=Maximum.
+ UINT16 tWTR_S; ///< Offset 294 User defined Memory Timing tWTR_S value, valid when SpdProfileSelected is CUSTOM_PROFILE: <b>0=AUTO</b>, 28=Maximum.
+ UINT64 EccErrInjAddress; ///< Offset 296 Address to match against for ECC error injection
+ UINT64 EccErrInjMask; ///< Offset 304 Mask to match against for ECC error injection
+ UINT32 EccErrInjCount; ///< Offset 312 Number of transactions between ECC error injection
+
+
+ UINT16 FreqLimitMixedConfig; ///< Offset 316 Override the reduced speed in mixed 2DPC config or non-POR 2DPC config. <b>0=Auto</b>, otherwise speed in MT/s: 1067, 1333 etc. See the possible values in MrcInterface.h
+ UINT8 FirstDimmBitMask; ///< Offset 318 Defines which DIMM should be populated first on a 2DPC board.
+ ///< 4 bit mask: Bit[0]: MC0 DIMM0, Bit[1]: MC0 DIMM1, Bit[2]: MC1 DIMM0, Bit[3]: MC1 DIMM1.
+ ///< For each MC, the first DIMM to be populated should be set to '1'.
+ ///< Note: this mask is only for non-ECC DIMM.
+ UINT8 UserBd; ///< Offset 319 MrcBoardType
+ ///< 1 - Desktop 1DPC
+ ///< 2 - Desktop 2DPC, Daisy Chain, far DIMM should be populated first
+ ///< 3 - Desktop 2DPC, T-topology with asymmetrical DIMM0/1 routing, has particular DIMM population order
+ ///< 4 - Desktop 2DPC, T-topology with symmetrical DIMM0/1 routing, no particular DIMM population order
+ ///< 5 - ULT Mobile
+ UINT8 SagvSwitchFactorIA; ///< Offset 320 Sagv Switch Factor: <b>1 </b>, 50=Maximum, default 30.
+ UINT8 SagvSwitchFactorGT; ///< Offset 321 Sagv Switch Factor: <b>1 </b>, 50=Maximum, default 30.
+ UINT8 SagvSwitchFactorIO; ///< Offset 322 Sagv Switch Factor: <b>1 </b>, 50=Maximum, default 30.
+ UINT8 SagvSwitchFactorStall; ///< Offset 323 Sagv Switch Factor: <b>1 </b>, 50=Maximum, default 30.
+ UINT8 SagvHeuristicsUpControl;///< Offset 324 Sagv duration in ms before heuristics up: <b>1 </b>, 50=Maximum, default 1ms.
+ UINT8 SagvHeuristicsDownControl; ///< Offset 325 Sagv duration in ms before heuristics down: <b>1 </b>, 50=Maximum, default 1ms.
+ UINT16 FreqLimitMixedConfig_1R1R_8GB; ///< Offset 326 The frequency limit for mixed DIMM configuration 1R1R_8GB (1R 8GB and 1R 8GB in one channel).
+ ///< It's to be set by customer. Customer can connect it to a setup option, or an UPD, etc. By default, the value will be 2000.
+ UINT16 FreqLimitMixedConfig_1R1R_16GB; ///< Offset 328 The frequency limit for mixed DIMM configuration 1R1R_16GB (1R 16GB and 1R 16GB in one channel).
+ ///< It's to be set by customer. Customer can connect it to a setup option, or an UPD, etc. By default, the value will be 2000.
+ UINT16 FreqLimitMixedConfig_1R1R_8GB_16GB; ///< Offset 330 The frequency limit for mixed DIMM configuration 1R1R_8GB_16GB (1R 8GB and 1R 16GB in one channel).
+ ///< It's to be set by customer. Customer can connect it to a setup option, or an UPD, etc. By default, the value will be 2000.
+ UINT16 FreqLimitMixedConfig_2R2R; ///< Offset 332 The frequency limit for mixed DIMM configuration 2R_2R (2R 32GB and 2R 32GB in one channel).
+ ///< It's to be set by customer. Customer can connect it to a setup option, or an UPD, etc. By default, the value will be 2000.
+ UINT16 LctCmdEyeWidth; ///< Offset 334 LCT Command eyewidth
+ UINT8 FirstDimmBitMaskEcc; ///< Offset 336 Defines which ECC DIMM should be populated first on a 2DPC board.
+ ///< 4 bit mask: Bit[0]: MC0 DIMM0, Bit[1]: MC0 DIMM1, Bit[2]: MC1 DIMM0, Bit[3]: MC1 DIMM1.
+ ///< For each MC, the first DIMM to be populated should be set to '1'.
+ ///< For example, if one MC is T-topology, there is no special population rule, can put it as 11 for this MC and it means either D0 or D1 can be
+ ///< be populated firstly.
+ ///< Note: this mask is only for ECC DIMM, not for non-ECC DIMM.
+ UINT8 Lp5BankMode; ///< Offset 337 LP5 Bank Mode
+ UINT8 OverloadSAM; ///< Offset 338 Overload SAM to copy the sagv frquency point.
+ UINT8 Reserved339[5]; ///< Offset 339-343 Reserved for natural alignment
+} MEMORY_CONFIGURATION;
+
+/// Memory Configuration
+/// The contents of this structure are not CRC'd by the MRC for option change detection.
+/// <b>Revision 1</b>: - Initial version.
+/// <b>Revision 2</b>: - Added MemTestOnWarmBoot
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Block Header
+ SA_FUNCTION_CALLS SaCall; ///< Offset 28 Function calls into the SA.
+ SA_MEMORY_FUNCTIONS MrcCall; ///< Offset 212 Function calls into the MRC.
+ SPD_DATA_BUFFER *SpdData; ///< Offset 236 Memory SPD data, will be used by the MRC when SPD SmBus address is zero.
+ SA_MEMORY_DQDQS_MAPPING *DqDqsMap; ///< Offset 240 LPDDR DQ bit and DQS byte swizzling between CPU and DRAM.
+ SA_MEMORY_RCOMP *RcompData; ///< Offset 244 DDR RCOMP resistors and target values.
+ UINT64 PlatformMemorySize; ///< Offset 248 The minimum platform memory size required to pass control into DXE
+ UINT32 CleanMemory:1; ///< Offset 256 Ask MRC to clear memory content: <b>FALSE=Do not Clear Memory</b>; TRUE=Clear Memory
+ UINT32 ReservedBits5:31;
+ /**
+ Sets the serial debug message level\n
+ 0x00 = Disabled\n
+ 0x01 = Errors only\n
+ 0x02 = Errors and Warnings\n
+ <b>0x03 = Errors, Warnings, and Info</b>\n
+ 0x04 = Errors, Warnings, Info, and Events\n
+ 0x05 = Displays Memory Init Execution Time Summary only\n
+ **/
+ UINT8 SerialDebugLevel; ///< Offset 260
+ UINT8 MemTestOnWarmBoot; ///< Offset 261 Run Base Memory Test On WarmBoot: 0=Disabled, <b>1=Enabled</b>
+ UINT8 Reserved11[2]; ///< Offset 262 - 263 Reserved
+} MEMORY_CONFIG_NO_CRC;
+#pragma pack(pop)
+
+#endif // _MEMORY_CONFIG_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/PchDmi/PchDmiConfig.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/PchDmi/PchDmiConfig.h
new file mode 100644
index 0000000000..84cc21091f
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/PchDmi/PchDmiConfig.h
@@ -0,0 +1,65 @@
+/** @file
+ DMI policy
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _PCH_DMI_CONFIG_H_
+#define _PCH_DMI_CONFIG_H_
+
+extern EFI_GUID gPchDmiConfigGuid;
+
+/*
+<b>Revision 1</b>: - Initial version.
+*/
+#define PCH_DMI_PREMEM_CONFIG_REVISION 1
+extern EFI_GUID gPchDmiPreMemConfigGuid;
+
+#pragma pack (push,1)
+
+#define PCH_DMI_HWEQ_COEFFS_MAX 8
+/**
+ Lane specific Dmi Gen3, Gen4 equalization parameters.
+**/
+typedef struct {
+ UINT8 Cm; ///< Coefficient C-1
+ UINT8 Cp; ///< Coefficient C+1
+ UINT8 Rsvd0[2]; ///< Reserved bytes
+} PCH_DMI_EQ_PARAM;
+
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Config Block
+ PCH_DMI_EQ_PARAM DmiHwEqGen3CoeffList[PCH_DMI_HWEQ_COEFFS_MAX];
+ UINT8 DmiHweq;
+ UINT8 Reserved[3];
+} PCH_DMI_PREMEM_CONFIG;
+
+
+/**
+ The PCH_DMI_CONFIG block describes the expected configuration of the PCH for DMI.
+ <b>Revision 1</b>:
+ - Initial version.
+**/
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Config Block Header
+
+ UINT32 PwrOptEnable : 1; ///< <b>0: Disable</b>; 1: Enable DMI Power Optimizer on PCH side.
+ UINT32 DmiAspmCtrl : 8; ///< ASPM configuration on the PCH side of the DMI/OPI Link. Default is <b>PchPcieAspmAutoConfig</b>
+ UINT32 CwbEnable : 1; ///< 0: Disable; <b>1: Enable</b> Central Write Buffer feature configurable and enabled by default
+ UINT32 L1RpCtl : 1; ///< 0: Disable; <b>1: Enable</b> Allow DMI enter L1 when all root ports are in L1, L0s or link down. Disabled by default.
+ /**
+ When set to TRUE turns on:
+ - L1 State Controller Power Gating
+ - L1 State PHY Data Lane Power Gating
+ - PHY Common Lane Power Gating
+ - Hardware Autonomous Enable
+ - PMC Request Enable and Sleep Enable
+ **/
+ UINT32 DmiPowerReduction : 1;
+ UINT32 ClockGating : 1; ///< 0: Disable; 1: Enable clock gating.
+ UINT32 Rsvdbits : 19; ///< Reserved bits
+} PCH_DMI_CONFIG;
+
+#pragma pack (pop)
+
+#endif // _PCH_DMI_CONFIG_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/PcieRp/PchPcieRp/PchPcieRpConfig.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/PcieRp/PchPcieRp/PchPcieRpConfig.h
new file mode 100644
index 0000000000..d97f3b878a
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/PcieRp/PchPcieRp/PchPcieRpConfig.h
@@ -0,0 +1,180 @@
+/** @file
+ PCH Pcie root port policy
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _PCH_PCIERP_CONFIG_H_
+#define _PCH_PCIERP_CONFIG_H_
+
+#include <PchLimits.h>
+#include <PcieConfig.h>
+#include <ConfigBlock.h>
+
+
+
+
+
+/*
+ Making any setup structure change after code frozen
+ will need to maintain backward compatibility, bump up
+ structure revision and update below history table\n
+
+<b>Revision 1</b>: - Initial version.
+*/
+#define PCIE_RP_DXE_CONFIG_REVISION 1
+
+extern EFI_GUID gPchPcieConfigGuid;
+extern EFI_GUID gPcieRpPreMemConfigGuid;
+
+#pragma pack (push,1)
+
+typedef enum {
+ PchPcieOverrideDisabled = 0,
+ PchPcieL1L2Override = 0x01,
+ PchPcieL1SubstatesOverride = 0x02,
+ PchPcieL1L2AndL1SubstatesOverride = 0x03,
+ PchPcieLtrOverride = 0x04
+} PCH_PCIE_OVERRIDE_CONFIG;
+
+///
+/// The values before AutoConfig match the setting of PCI Express Base Specification 1.1, please be careful for adding new feature
+///
+typedef enum {
+ PchPcieAspmDisabled,
+ PchPcieAspmL0s,
+ PchPcieAspmL1,
+ PchPcieAspmL0sL1,
+ PchPcieAspmAutoConfig,
+ PchPcieAspmMax
+} PCH_PCIE_ASPM_CONTROL;
+
+/**
+ Refer to PCH EDS for the PCH implementation values corresponding
+ to below PCI-E spec defined ranges
+**/
+typedef enum {
+ PchPcieL1SubstatesDisabled,
+ PchPcieL1SubstatesL1_1,
+ PchPcieL1SubstatesL1_1_2,
+ PchPcieL1SubstatesMax
+} PCH_PCIE_L1SUBSTATES_CONTROL;
+
+enum PCH_PCIE_MAX_PAYLOAD {
+ PchPcieMaxPayload128 = 0,
+ PchPcieMaxPayload256,
+ PchPcieMaxPayloadMax
+};
+
+
+/**
+ PCH_PCIE_CLOCK describes PCIe source clock generated by PCH.
+**/
+typedef struct {
+ UINT8 Usage; ///< Purpose of given clock (see PCH_PCIE_CLOCK_USAGE). Default: Unused, 0xFF
+ UINT8 ClkReq; ///< ClkSrc - ClkReq mapping. Default: 1:1 mapping with Clock numbers
+ UINT8 RsvdBytes[2]; ///< Reserved byte
+ UINT32 ClkReqGpioPinMux; /// Muxed GPIO details. Refer GPIO_*_MUXING_SRC_CLKREQ_x*
+} PCH_PCIE_CLOCK;
+
+
+/**
+ The PCH_PCI_EXPRESS_ROOT_PORT_CONFIG describe the feature and capability of each PCH PCIe root port.
+**/
+typedef struct {
+ PCIE_ROOT_PORT_COMMON_CONFIG PcieRpCommonConfig; ///an instance of Pcie Common Config
+ UINT8 ExtSync; ///< Indicate whether the extended synch is enabled. <b>0: Disable</b>; 1: Enable.
+ //
+ // Error handlings
+ //
+ UINT8 SystemErrorEnable; ///< Indicate whether the System Error is enabled. <b>0: Disable</b>; 1: Enable.
+ /**
+ The Multiple VC (MVC) supports hardware to avoid HoQ block for latency sensitive TC.
+ Currently it is only applicable to Root Ports with 2pX4 port configuration with 2 VCs,or
+ DMI port configuration with 3 VCs. For Root Ports 2pX4 configuration, two RPs (RP0,
+ RP2) shall support two PCIe VCs (VC0 & VC1) and the other RPs (RP1, RP3) shall be
+ disabled.
+ <b>0: Disable</b>; 1: Enable
+ **/
+ UINT8 MvcEnabled;
+ /**
+ Virtual Pin Port is industry standard introduced to PCIe Hot Plug support in systems
+ when GPIO pins expansion is needed. It is server specific feature.
+ <b>0x00: Default</b>; 0xFF: Disabled
+ **/
+ UINT8 VppPort;
+ UINT8 VppAddress; ///< PCIe Hot Plug VPP SMBus Address. Default is zero.
+ UINT8 RsvdBytes0[3]; ///< Reserved bytes
+} PCH_PCIE_ROOT_PORT_CONFIG;
+
+/**
+ The PCH_PCIE_CONFIG block describes the expected configuration of the PCH PCI Express controllers
+ <b>Revision 1</b>:
+ - Initial version.
+ <b>Revision 2</b>:
+ - Moved EnablePort8xhDecode policy to PCIE_COMMON_CONFIG
+**/
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Config Block Header
+ ///
+ /// These members describe the configuration of each PCH PCIe root port.
+ ///
+ PCIE_COMMON_CONFIG PcieCommonConfig;
+ PCH_PCIE_ROOT_PORT_CONFIG RootPort[PCH_MAX_PCIE_ROOT_PORTS];
+ PCH_PCIE_ROOT_PORT_CONFIG DmiPort;
+
+ ///
+ /// <b>(Test)</b> The Index of PCIe Port that is selected for Port8xh Decode (0 Based)
+ ///
+ UINT8 PchPciePort8xhDecodePortIndex;
+ UINT8 DmiPowerReduction;
+ UINT8 RsvdBytes0[2];
+} PCH_PCIE_CONFIG;
+
+/**
+ The PCH_PCIE_RP_PREMEM_CONFIG block describes early configuration of the PCH PCI Express controllers
+ <b>Revision 1</b>:
+ - Initial version.
+**/
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Config Block Header
+ /**
+ Root Port enabling mask.
+ Bit0 presents RP1, Bit1 presents RP2, and so on.
+ 0: Disable; <b>1: Enable</b>.
+ **/
+ UINT32 RpEnabledMask;
+ /// Configuration of PCIe source clocks
+ ///
+ PCH_PCIE_CLOCK PcieClock[PCH_MAX_PCIE_CLOCKS];
+
+ /**
+ Per Controller Bifurcation Configuration
+ <b>0: Disabled</b>; 1: 4x1; 2: 1x2_2x1; 3: 2x2; 4: 1x4; 5: 4x2; 6: 1x4_2x2; 7: 2x2_1x4; 8: 2x4; 9: 1x8 (see: PCIE_BIFURCATION_CONFIG)
+ **/
+ UINT8 Bifurcation[PCH_MAX_PCIE_CONTROLLERS];
+ UINT8 Rsvd4[(4 - PCH_MAX_PCIE_CONTROLLERS % 4) % 4];
+} PCH_PCIE_RP_PREMEM_CONFIG;
+
+/**
+ The PCIE_RP_DXE_CONFIG block describes the expected configuration of the PCH PCI Express controllers in DXE phase
+
+ <b>Revision 1</b>:
+ - Init version
+**/
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Config Block Header
+
+ /**
+ PCIe device override table
+ The PCIe device table is being used to override PCIe device ASPM settings.
+ And it's only used in DXE phase.
+ Please refer to PCIE_DEVICE_OVERRIDE structure for the table.
+ Last entry VendorId must be 0.
+ **/
+ PCIE_DEVICE_OVERRIDE *PcieDeviceOverrideTablePtr;
+} PCIE_RP_DXE_CONFIG;
+
+#pragma pack (pop)
+
+#endif // _PCH_PCIERP_CONFIG_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/PcieRp/PcieConfig.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/PcieRp/PcieConfig.h
new file mode 100644
index 0000000000..07a5644f43
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/PcieRp/PcieConfig.h
@@ -0,0 +1,408 @@
+/** @file
+ PCIe Config Block
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _PCIE_CONFIG_H_
+#define _PCIE_CONFIG_H_
+#include <CpuPcieInfo.h>
+
+#define PCIE_LINK_EQ_COEFFICIENTS_MAX 10
+#define PCIE_LINK_EQ_PRESETS_MAX 11
+extern EFI_GUID gPcieConfigGuid;
+
+#pragma pack (push,1)
+
+enum PCIE_COMPLETION_TIMEOUT {
+ PcieCompletionTO_Default,
+ PcieCompletionTO_50_100us,
+ PcieCompletionTO_1_10ms,
+ PcieCompletionTO_16_55ms,
+ PcieCompletionTO_65_210ms,
+ PcieCompletionTO_260_900ms,
+ PcieCompletionTO_1_3P5s,
+ PcieCompletionTO_4_13s,
+ PcieCompletionTO_17_64s,
+ PcieCompletionTO_Disabled
+};
+
+typedef enum {
+ PcieAuto,
+ PcieGen1,
+ PcieGen2,
+ PcieGen3,
+ PcieGen4,
+ PcieGen5
+} PCIE_SPEED;
+
+typedef enum {
+ PcieDisabled,
+ PcieL1SUB_1,
+ PcieL1SUB_1_2
+}L1_SUBSTATES;
+
+/**
+ Represent lane specific PCIe Gen3 equalization parameters.
+**/
+typedef struct {
+ UINT8 Cm; ///< Coefficient C-1
+ UINT8 Cp; ///< Coefficient C+1
+ UINT8 Rsvd0[2]; ///< Reserved bytes
+} PCIE_EQ_PARAM;
+
+typedef struct {
+ UINT16 LtrMaxSnoopLatency; ///< <b>(Test)</b> Latency Tolerance Reporting, Max Snoop Latency.
+ UINT16 LtrMaxNoSnoopLatency; ///< <b>(Test)</b> Latency Tolerance Reporting, Max Non-Snoop Latency.
+ UINT8 SnoopLatencyOverrideMode; ///< <b>(Test)</b> Latency Tolerance Reporting, Snoop Latency Override Mode.
+ UINT8 SnoopLatencyOverrideMultiplier; ///< <b>(Test)</b> Latency Tolerance Reporting, Snoop Latency Override Multiplier.
+ UINT16 SnoopLatencyOverrideValue; ///< <b>(Test)</b> Latency Tolerance Reporting, Snoop Latency Override Value.
+ UINT8 NonSnoopLatencyOverrideMode; ///< <b>(Test)</b> Latency Tolerance Reporting, Non-Snoop Latency Override Mode.
+ UINT8 NonSnoopLatencyOverrideMultiplier; ///< <b>(Test)</b> Latency Tolerance Reporting, Non-Snoop Latency Override Multiplier.
+ UINT16 NonSnoopLatencyOverrideValue; ///< <b>(Test)</b> Latency Tolerance Reporting, Non-Snoop Latency Override Value.
+ UINT8 LtrConfigLock; ///< <b>0: Disable</b>; 1: Enable.
+ UINT8 ForceLtrOverride;
+ UINT16 RsvdByte1;
+} PCIE_LTR_CONFIG;
+
+
+/**
+ Specifies the form factor that the slot
+ implements. For custom form factors that
+ do not require any special handling please
+ set PcieFormFactorOther.
+**/
+typedef enum {
+ PcieFormFactorOther = 0,
+ PcieFormFactorCem,
+ PcieFormFactorMiniPci,
+ PcieFormFactorM2,
+ PcieFormFactorOcuLink,
+ PcieFormFactorExpressModule, // Also known as Server IO module(SIOM)
+ PcieFormFactorExpressCard,
+ PcieFormFactorU2 // Also known as SF-8639
+} PCIE_FORM_FACTOR;
+
+typedef enum {
+ PcieLinkHardwareEq = 0, ///< Hardware is responsible for performing coefficient/preset search.
+ PcieLinkFixedEq ///< No coefficient/preset search is performed. Fixed values are used.
+} PCIE_LINK_EQ_METHOD;
+
+typedef enum {
+ PcieLinkEqPresetMode = 0, ///< Use presets during PCIe link equalization
+ PcieLinkEqCoefficientMode ///< Use coefficients during PCIe link equalization
+} PCIE_LINK_EQ_MODE;
+
+typedef struct {
+ UINT32 PreCursor; ///< Pre-cursor coefficient
+ UINT32 PostCursor; ///< Post-cursor coefficient
+} PCIE_LINK_EQ_COEFFICIENTS;
+
+/**
+ PCIe Link EQ Platform Settings
+**/
+typedef struct {
+ UINT8 PcieLinkEqMethod; ///< Tells BIOS which link EQ method should be used for this port. Please refer to PCIE_LINK_EQ_METHOD for details of supported methods. Default: PcieLinkHardwareEq
+ UINT8 PcieLinkEqMode; ///< Tells BIOS which mode should be used for PCIe link EQ. Please refer to PCIE_LINK_EQ_MODE for details of supported modes. Default: depends on SoC
+ /**
+ Specifies if BIOS should perform local transmitter override during phase 2 of EQ process.
+ If enabled value in Ph2LocalTransmitterOverridePreset must be valid.
+ <b>0: Disabled</b>; 1: Enabled
+ **/
+ UINT8 LocalTransmitterOverrideEnable;
+ /**
+ Tells BIOS how many presets/coefficients should be used during link EQ.
+ Entries in the Ph3CoefficientsList or Ph3PresetList(depending on chosen mode) need to be valid up to the number specified in this field.
+ **/
+ UINT8 Ph3NumberOfPresetsOrCoefficients;
+
+ PCIE_LINK_EQ_COEFFICIENTS Ph3CoefficientsList[PCIE_LINK_EQ_COEFFICIENTS_MAX]; ///< List of the PCIe coefficients to be used during equalization process. Only valid if PcieLinkEqMode is PcieLinkEqCoefficientMode
+ UINT32 Ph3PresetList[PCIE_LINK_EQ_PRESETS_MAX]; ///< List of the PCIe preset values to be used during equalization process. Only valid if PcieLinkEqMode is PcieLinkEqPresetMode
+ UINT32 Ph1DownstreamPortTransmitterPreset; ///< Specifies the value of the downstream port transmitter preset to be used during phase 1 of the equalization process. Will be applied to all lanes
+ UINT32 Ph1UpstreamPortTransmitterPreset; ///< Specifies the value of the upstream port transmitter preset to be used during phase 1 of the equalization process. Will be applied to all lanes
+ /**
+ Specifies the preset that should be used during local transmitter override during phase 2 of EQ process.
+ Used only if LocalTransmitterOverrideEnable is TRUE. Will be applied to all PCIe lanes of the root port.
+ Valid up to the PCIE_LINK_EQ_PRESET_MAX value. <b>Default: 0<\b>
+ **/
+ UINT32 Ph2LocalTransmitterOverridePreset;
+ UINT32 PCETTimer; ///< PCET Timer value for single PCIe speed.
+ UINT8 RemotePresetCoeffoverride; ///< Remote Transmitter Preset Coefficient Override for single PCIe speed.
+ /**
+ PCIe Equalization Phase 3 Enable Control
+ - <b>Disabled</b> (0x0) : Disable phase 3 (Default)
+ - Enabled (0x1) : Enable phase 3
+ **/
+ UINT8 EqPh3Bypass;
+ /**
+ PCIe Equalization Phase 2-3 Enable Control
+ - <b>Disabled</b> (0x0) : Disable Phase 2 - Phase 3 (Default)
+ - Enabled (0x1) : Enable Phase 2 - Phase 3
+ **/
+ UINT8 EqPh23Bypass;
+ UINT8 TsLockTimer; ///< 8.0GT/s Training Sequence Wait Latency For Presets / Coefficients Evaluation - Gen3 TS Lock Timer
+} PCIE_LINK_EQ_PLATFORM_SETTINGS;
+
+//Note: This structure will be expanded to hold all common PCIe policies between SA and PCH RootPort
+typedef struct {
+ UINT32 HotPlug : 1; ///< Indicate whether the root port is hot plug available. <b>0: Disable</b>; 1: Enable.
+ UINT32 PmSci : 1; ///< Indicate whether the root port power manager SCI is enabled. 0: Disable; <b>1: Enable</b>.
+ UINT32 TransmitterHalfSwing : 1; ///< Indicate whether the Transmitter Half Swing is enabled. <b>0: Disable</b>; 1: Enable.
+ UINT32 AcsEnabled : 1; ///< Indicate whether the ACS is enabled. 0: Disable; <b>1: Enable</b>.
+ //
+ // Error handlings
+ //
+ UINT32 AdvancedErrorReporting : 1; ///< Indicate whether the Advanced Error Reporting is enabled. <b>0: Disable</b>; 1: Enable.
+ UINT32 UnsupportedRequestReport : 1; ///< Indicate whether the Unsupported Request Report is enabled. <b>0: Disable</b>; 1: Enable.
+ UINT32 FatalErrorReport : 1; ///< Indicate whether the Fatal Error Report is enabled. <b>0: Disable</b>; 1: Enable.
+ UINT32 NoFatalErrorReport : 1; ///< Indicate whether the No Fatal Error Report is enabled. <b>0: Disable</b>; 1: Enable.
+ UINT32 CorrectableErrorReport : 1; ///< Indicate whether the Correctable Error Report is enabled. <b>0: Disable</b>; 1: Enable.
+ UINT32 SystemErrorOnFatalError : 1; ///< Indicate whether the System Error on Fatal Error is enabled. <b>0: Disable</b>; 1: Enable.
+ UINT32 SystemErrorOnNonFatalError : 1; ///< Indicate whether the System Error on Non Fatal Error is enabled. <b>0: Disable</b>; 1: Enable.
+ UINT32 SystemErrorOnCorrectableError : 1; ///< Indicate whether the System Error on Correctable Error is enabled. <b>0: Disable</b>; 1: Enable.
+ /**
+ Max Payload Size supported, Default <b>128B</b>, see enum CPU_PCIE_MAX_PAYLOAD
+ Changes Max Payload Size Supported field in Device Capabilities of the root port.
+ **/
+ UINT32 MaxPayload : 2;
+ UINT32 DpcEnabled : 1; ///< Downstream Port Containment. 0: Disable; <b>1: Enable</b>
+ UINT32 RpDpcExtensionsEnabled : 1; ///< RP Extensions for Downstream Port Containment. 0: Disable; <b>1: Enable</b>
+ /**
+ Indicates how this root port is connected to endpoint. 0: built-in device; <b>1: slot</b>
+ Built-in is incompatible with hotplug-capable ports.
+ **/
+ UINT32 SlotImplemented : 1;
+ UINT32 PtmEnabled : 1; ///< Enables PTM capability
+ UINT32 SlotPowerLimitScale : 2; ///< <b>(Test)</b> Specifies scale used for slot power limit value. Leave as 0 to set to default. Default is <b>zero</b>.
+ UINT32 SlotPowerLimitValue : 12; //< <b>(Test)</b> Specifies upper limit on power supplies by slot. Leave as 0 to set to default. Default is <b>zero</b>.
+ /**
+ Probe CLKREQ# signal before enabling CLKREQ# based power management.
+ Conforming device shall hold CLKREQ# low until CPM is enabled. This feature attempts
+ to verify CLKREQ# signal is connected by testing pad state before enabling CPM.
+ In particular this helps to avoid issues with open-ended PCIe slots.
+ This is only applicable to non hot-plug ports.
+ <b>0: Disable</b>; 1: Enable.
+ **/
+ UINT32 ClkReqDetect : 1;
+ /**
+ Set if the slot supports manually operated retention latch.
+ **/
+ UINT32 MrlSensorPresent : 1;
+ UINT32 RelaxedOrder : 1;
+ UINT32 NoSnoop : 1;
+ ///
+ /// This member describes whether Peer Memory Writes are enabled on the platform. <b>0: Disable</b>; 1: Enable.
+ ///
+ UINT32 EnablePeerMemoryWrite : 1;
+ ///
+ /// This member describes whether the PCI Express Clock Gating for each root port
+ /// is enabled by platform modules. <b>0: Disable</b>; 1: Enable.
+ ///
+ UINT32 ClockGating : 1;
+ ///
+ /// This member describes whether the PCI Express Power Gating for each root port
+ /// is enabled by platform modules. <b>0: Disable</b>; 1: Enable.
+ ///
+ UINT32 PowerGating : 1;
+ UINT32 RsvdBits0 : 25; ///< Reserved bits.
+ /**
+ PCIe Gen3 Equalization Phase 3 Method (see CPU_PCIE_EQ_METHOD).
+ 0: DEPRECATED, hardware equalization; <b>1: hardware equalization</b>; 4: Fixed Coefficients
+ **/
+ UINT8 Gen3EqPh3Method;
+ UINT8 PhysicalSlotNumber; ///< Indicates the slot number for the root port. Default is the value as root port index.
+ UINT8 CompletionTimeout; ///< The completion timeout configuration of the root port (see: CPU_PCIE_COMPLETION_TIMEOUT). Default is <b>PchPcieCompletionTO_Default</b>.
+ //
+ // Power Management
+ //
+ UINT8 Aspm; ///< The ASPM configuration of the root port (see: CPU_PCIE_ASPM_CONTROL). Default is <b>PchPcieAspmAutoConfig</b>.
+ UINT8 L1Substates; ///< The L1 Substates configuration of the root port (see: CPU_PCIE_L1SUBSTATES_CONTROL). Default is <b>PchPcieL1SubstatesL1_1_2</b>.
+ UINT8 LtrEnable; ///< Latency Tolerance Reporting Mechanism. <b>0: Disable</b>; 1: Enable.
+ UINT8 EnableCpm; ///< Enables Clock Power Management; even if disabled, CLKREQ# signal can still be controlled by L1 PM substates mechanism
+ UINT8 PcieSpeed; ///< Contains speed of PCIe bus (see: PCIE_SPEED)
+ /**
+ <b>(Test)</b>
+ Forces LTR override to be permanent
+ The default way LTR override works is:
+ rootport uses LTR override values provided by BIOS until connected device sends an LTR message, then it will use values from the message
+ This settings allows force override of LTR mechanism. If it's enabled, then:
+ rootport will use LTR override values provided by BIOS forever; LTR messages sent from connected device will be ignored
+ **/
+ PCIE_LTR_CONFIG PcieRpLtrConfig; ///< <b>(Test)</b> Latency Tolerance Reporting Policies including LTR limit and Override
+ /**
+ The number of milliseconds reference code will wait for link to exit Detect state for enabled ports
+ before assuming there is no device and potentially disabling the port.
+ It's assumed that the link will exit detect state before root port initialization (sufficient time
+ elapsed since PLTRST de-assertion) therefore default timeout is zero. However this might be useful
+ if device power-up seqence is controlled by BIOS or a specific device requires more time to detect.
+ In case of non-common clock enabled the default timout is 15ms.
+ <b>Default: 0</b>
+ **/
+ UINT16 DetectTimeoutMs;
+ UINT8 FormFactor; // Please check PCIE_FORM_FACTOR for supported values
+ UINT8 L1Low; ///< L1.LOW enable/disable. <b>0: Disable</b>; 1: Enable.
+ UINT8 LinkDownGpios;
+ ///
+ /// <b>0: Use project default equalization settings</b>; 1: Use equalization settings from PcieLinkEqPlatformSettings
+ ///
+ UINT8 OverrideEqualizationDefaults;
+ UINT8 Reserved[2];
+ PCIE_LINK_EQ_PLATFORM_SETTINGS PcieGen3LinkEqPlatformSettings; ///< Global PCIe Gen3 link EQ settings that BIOS will use during PCIe link EQ for every port.
+ PCIE_LINK_EQ_PLATFORM_SETTINGS PcieGen4LinkEqPlatformSettings; ///< Global PCIe Gen4 link EQ settings that BIOS will use during PCIe link EQ for every port.
+ PCIE_LINK_EQ_PLATFORM_SETTINGS PcieGen5LinkEqPlatformSettings; ///< Global PCIe Gen5 link EQ settings that BIOS will use during PCIe link EQ for every port.
+} PCIE_ROOT_PORT_COMMON_CONFIG;
+
+/**
+ PCIe Common Config
+ @note This structure will be expanded to hold all common PCIe policies between SA and PCH
+**/
+typedef struct {
+ /**
+ RpFunctionSwap allows BIOS to use root port function number swapping when root port of function 0 is disabled.
+ A PCIE device can have higher functions only when Function0 exists. To satisfy this requirement,
+ BIOS will always enable Function0 of a device that contains more than 0 enabled root ports.
+ - <b>Enabled: One of enabled root ports get assigned to Function0.</b>
+ This offers no guarantee that any particular root port will be available at a specific DevNr:FuncNr location
+ - Disabled: Root port that corresponds to Function0 will be kept visible even though it might be not used.
+ That way rootport - to - DevNr:FuncNr assignment is constant. This option will impact ports 1, 9, 17.
+ NOTE: This option will not work if ports 1, 9, 17 are fused or configured for RST PCIe storage or disabled through policy
+ In other words, it only affects ports that would become hidden because they have no device connected.
+ NOTE: Disabling function swap may have adverse impact on power management. This option should ONLY
+ be used when each one of root ports 1, 9, 17:
+ - is configured as PCIe and has correctly configured ClkReq signal, or
+ - does not own any mPhy lanes (they are configured as SATA or USB)
+ **/
+ UINT32 RpFunctionSwap : 1;
+ /**
+ Compliance Test Mode shall be enabled when using Compliance Load Board.
+ <b>0: Disable</b>, 1: Enable
+ **/
+ UINT32 ComplianceTestMode : 1;
+ UINT32 RsvdBits0 : 30; ///< Reserved bits
+ ///
+ /// <b>(Test)</b> This member describes whether PCIE root port Port 8xh Decode is enabled. <b>0: Disable</b>; 1: Enable.
+ ///
+ UINT8 EnablePort8xhDecode;
+ UINT8 RsvdBytes0[3];
+ ///
+ /// List of coefficients used during equalization (applicable to both software and hardware EQ)
+ /// Deprecated Policy
+ ///
+ PCIE_EQ_PARAM HwEqGen3CoeffList[PCIE_HWEQ_COEFFS_MAX];
+} PCIE_COMMON_CONFIG;
+
+typedef struct {
+ PCIE_EQ_PARAM HwEqGen3CoeffList[CPU_PCIE_MAX_ROOT_PORTS][PCIE_HWEQ_COEFFS_MAX];
+ PCIE_EQ_PARAM HwEqGen4CoeffList[CPU_PCIE_MAX_ROOT_PORTS][PCIE_HWEQ_COEFFS_MAX];
+ PCIE_EQ_PARAM HwEqGen5CoeffList[CPU_PCIE_MAX_ROOT_PORTS][PCIE_HWEQ_COEFFS_MAX];
+} PCIE_COMMON_CONFIG2;
+
+
+/**
+ PCIe device table entry entry
+
+ The PCIe device table is being used to override PCIe device ASPM settings.
+ To take effect table consisting of such entries must be instelled as PPI
+ on gPchPcieDeviceTablePpiGuid.
+ Last entry VendorId must be 0.
+**/
+typedef struct {
+ UINT16 VendorId; ///< The vendor Id of Pci Express card ASPM setting override, 0xFFFF means any Vendor ID
+ UINT16 DeviceId; ///< The Device Id of Pci Express card ASPM setting override, 0xFFFF means any Device ID
+ UINT8 RevId; ///< The Rev Id of Pci Express card ASPM setting override, 0xFF means all steppings
+ UINT8 BaseClassCode; ///< The Base Class Code of Pci Express card ASPM setting override, 0xFF means all base class
+ UINT8 SubClassCode; ///< The Sub Class Code of Pci Express card ASPM setting override, 0xFF means all sub class
+ UINT8 EndPointAspm; ///< Override device ASPM (see: PCH_PCIE_ASPM_CONTROL)
+ ///< Bit 1 must be set in OverrideConfig for this field to take effect
+ UINT16 OverrideConfig; ///< The override config bitmap (see: PCH_PCIE_OVERRIDE_CONFIG).
+ /**
+ The L1Substates Capability Offset Override. (applicable if bit 2 is set in OverrideConfig)
+ This field can be zero if only the L1 Substate value is going to be override.
+ **/
+ UINT16 L1SubstatesCapOffset;
+ /**
+ L1 Substate Capability Mask. (applicable if bit 2 is set in OverrideConfig)
+ Set to zero then the L1 Substate Capability [3:0] is ignored, and only L1s values are override.
+ Only bit [3:0] are applicable. Other bits are ignored.
+ **/
+ UINT8 L1SubstatesCapMask;
+ /**
+ L1 Substate Port Common Mode Restore Time Override. (applicable if bit 2 is set in OverrideConfig)
+ L1sCommonModeRestoreTime and L1sTpowerOnScale can have a valid value of 0, but not the L1sTpowerOnValue.
+ If L1sTpowerOnValue is zero, all L1sCommonModeRestoreTime, L1sTpowerOnScale, and L1sTpowerOnValue are ignored,
+ and only L1SubstatesCapOffset is override.
+ **/
+ UINT8 L1sCommonModeRestoreTime;
+ /**
+ L1 Substate Port Tpower_on Scale Override. (applicable if bit 2 is set in OverrideConfig)
+ L1sCommonModeRestoreTime and L1sTpowerOnScale can have a valid value of 0, but not the L1sTpowerOnValue.
+ If L1sTpowerOnValue is zero, all L1sCommonModeRestoreTime, L1sTpowerOnScale, and L1sTpowerOnValue are ignored,
+ and only L1SubstatesCapOffset is override.
+ **/
+ UINT8 L1sTpowerOnScale;
+ /**
+ L1 Substate Port Tpower_on Value Override. (applicable if bit 2 is set in OverrideConfig)
+ L1sCommonModeRestoreTime and L1sTpowerOnScale can have a valid value of 0, but not the L1sTpowerOnValue.
+ If L1sTpowerOnValue is zero, all L1sCommonModeRestoreTime, L1sTpowerOnScale, and L1sTpowerOnValue are ignored,
+ and only L1SubstatesCapOffset is override.
+ **/
+ UINT8 L1sTpowerOnValue;
+
+ /**
+ SnoopLatency bit definition
+ Note: All Reserved bits must be set to 0
+
+ BIT[15] - When set to 1b, indicates that the values in bits 9:0 are valid
+ When clear values in bits 9:0 will be ignored
+ BITS[14:13] - Reserved
+ BITS[12:10] - Value in bits 9:0 will be multiplied with the scale in these bits
+ 000b - 1 ns
+ 001b - 32 ns
+ 010b - 1024 ns
+ 011b - 32,768 ns
+ 100b - 1,048,576 ns
+ 101b - 33,554,432 ns
+ 110b - Reserved
+ 111b - Reserved
+ BITS[9:0] - Snoop Latency Value. The value in these bits will be multiplied with
+ the scale in bits 12:10
+
+ This field takes effect only if bit 3 is set in OverrideConfig.
+ **/
+ UINT16 SnoopLatency;
+ /**
+ NonSnoopLatency bit definition
+ Note: All Reserved bits must be set to 0
+
+ BIT[15] - When set to 1b, indicates that the values in bits 9:0 are valid
+ When clear values in bits 9:0 will be ignored
+ BITS[14:13] - Reserved
+ BITS[12:10] - Value in bits 9:0 will be multiplied with the scale in these bits
+ 000b - 1 ns
+ 001b - 32 ns
+ 010b - 1024 ns
+ 011b - 32,768 ns
+ 100b - 1,048,576 ns
+ 101b - 33,554,432 ns
+ 110b - Reserved
+ 111b - Reserved
+ BITS[9:0] - Non Snoop Latency Value. The value in these bits will be multiplied with
+ the scale in bits 12:10
+
+ This field takes effect only if bit 3 is set in OverrideConfig.
+ **/
+ UINT16 NonSnoopLatency;
+
+ /**
+ Forces LTR override to be permanent
+ The default way LTR override works is:
+ rootport uses LTR override values provided by BIOS until connected device sends an LTR message, then it will use values from the message
+ This settings allows force override of LTR mechanism. If it's enabled, then:
+ rootport will use LTR override values provided by BIOS forever; LTR messages sent from connected device will be ignored
+ **/
+ UINT8 ForceLtrOverride;
+ UINT8 Reserved[3];
+} PCIE_DEVICE_OVERRIDE;
+
+#pragma pack (pop)
+#endif // _PCIE_CONFIG_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/PcieRp/PciePreMemConfig.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/PcieRp/PciePreMemConfig.h
new file mode 100644
index 0000000000..fe0be3ec12
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/PcieRp/PciePreMemConfig.h
@@ -0,0 +1,36 @@
+/** @file
+ PCIe Config Block PreMem
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _PCIE_PREMEM_CONFIG_H_
+#define _PCIE_PREMEM_CONFIG_H_
+
+
+extern EFI_GUID gPciePreMemConfigGuid;
+
+#pragma pack (push,1)
+
+/**
+ PCIe IMR Config
+**/
+typedef struct {
+ UINT8 ImrEnabled; ///< PCIe IMR. <b>0: Disable</b>; 1: Enable.
+ UINT8 ImrRpLocation; ///< 0: PCH_PCIe; 1: CPU_PCIe. If PCIeImrEnabled is TRUE then this will use to select the Root port location from PCH PCIe or CPU PCIe.Refer PCIE_IMR_ROOT_PORT_LOCATION above
+ UINT16 ImrSize; ///< PCIe IMR size in megabytes
+ UINT8 ImrRpSelection; ///< Index of root port that is selected for PCIe IMR (0 based)
+ UINT8 Rsvd0[3];
+} PCIE_IMR_CONFIG;
+
+/**
+ PCIe Pre-Memory Configuration
+ <b>Revision 1</b>: - Initial version.
+**/
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Offset 0 - 27 Config Block Header
+ PCIE_IMR_CONFIG PcieImr; ///< IMR Configuration
+} PCIE_PREMEM_CONFIG;
+
+#pragma pack (pop)
+#endif // _PCIE_PREMEM_CONFIG_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Pmc/AdrConfig.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Pmc/AdrConfig.h
new file mode 100644
index 0000000000..35ecb53ed2
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Pmc/AdrConfig.h
@@ -0,0 +1,76 @@
+/** @file
+ ADR policy
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _ADR_CONFIG_H_
+#define _ADR_CONFIG_H_
+
+#include <ConfigBlock.h>
+
+extern EFI_GUID gAdrConfigGuid;
+
+#pragma pack (push,1)
+
+
+/**
+ ADR Source Enable
+**/
+typedef union {
+ struct {
+ UINT32 Reserved1 : 1;
+ UINT32 AdrSrcPbo : 1;
+ UINT32 AdrSrcPmcUncErr : 1;
+ UINT32 AdrSrcPchThrm : 1;
+ UINT32 AdrSrcMePbo : 1;
+ UINT32 AdrSrcCpuThrm : 1;
+ UINT32 AdrSrcMegbl : 1;
+ UINT32 AdrSrcLtReset : 1;
+ UINT32 AdrSrcPmcWdt : 1;
+ UINT32 AdrSrcMeWdt : 1;
+ UINT32 AdrSrcPmcFw : 1;
+ UINT32 AdrSrcPchpwrFlr : 1;
+ UINT32 AdrSrcSyspwrFlr : 1;
+ UINT32 Reserved2 : 1;
+ UINT32 AdrSrcMiaUxsErr : 1;
+ UINT32 AdrSrcMiaUxErr : 1;
+ UINT32 AdrSrcCpuThrmWdt : 1;
+ UINT32 AdrSrcMeUncErr : 1;
+ UINT32 AdrSrcAdrGpio : 1;
+ UINT32 AdrSrcOcwdtNoicc : 1;
+ UINT32 AdrSrcOcwdtIcc : 1;
+ UINT32 AdrSrcCseHecUncErr : 1;
+ UINT32 AdrSrcPmcSramUncErr : 1;
+ UINT32 AdrSrcPmcIromParity : 1;
+ UINT32 AdrSrcPmcRfFusaErr : 1;
+ UINT32 Reserved3 : 4;
+ UINT32 AdrSrcPpbrParityErr : 1;
+ UINT32 Reserved4 : 2;
+ } Field;
+ UINT32 Value;
+} ADR_SOURCE_ENABLE;
+
+/**
+ ADR Configuration
+ <b>Revision 1</b>: - Initial version.
+**/
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Config Block Header
+ UINT32 AdrEn : 2; ///< Determine if Adr is enabled - 0: PLATFORM_POR, 1: FORCE_ENABLE, 2: FORCE_DISABLE
+ UINT32 AdrTimerEn : 2; ///< Determine if Adr timer options are enabled - 0: PLATFORM_POR, 1: FORCE_ENABLE, 2: FORCE_DISABLE
+ UINT32 AdrTimer1Val : 8; ///< Determines the Timeout value used for the ADR timer 1. A value of zero bypasses the timer
+ UINT32 AdrMultiplier1Val : 3; ///< Specifies the tick frequency upon which the timer 1 will increment. ADR_TIMER_SCALE should be used to encode values
+ UINT32 AdrTimer2Val : 8; ///< Determines the Timeout value used for the ADR timer 2. A value of zero bypasses the timer
+ UINT32 AdrMultiplier2Val : 3; ///< Specifies the tick frequency upon which the timer 2 will increment. ADR_TIMER_SCALE should be used to encode values
+ UINT32 AdrHostPartitionReset : 2; ///< Determine if Host Partition Reset is enabled - 0: PLATFORM_POR, 1: FORCE_ENABLE, 2: FORCE_DISABLE
+ UINT32 AdrSrcOverride : 1; ///< Check if default ADR sources will be overriten with custom 0: Not overwritten, 1: Overwritten
+ UINT32 AdrPlatAckEn : 2; ///< Determine if Platform Acknowledge is enabled - 0: PLATFORM_POR, 1: FORCE_ENABLE, 2: FORCE_DISABLE
+ UINT32 ReservedBits : 1;
+ ADR_SOURCE_ENABLE AdrSrcSel; ///< Determine which ADR sources are enabled - 0: Enabled, 1: Disabled
+} ADR_CONFIG;
+
+#pragma pack (pop)
+
+#endif // _ADR_CONFIG_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Pmc/PmConfig.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Pmc/PmConfig.h
new file mode 100644
index 0000000000..0a2ae50e6a
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Pmc/PmConfig.h
@@ -0,0 +1,86 @@
+/** @file
+ Power Management policy
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _PM_CONFIG_H_
+#define _PM_CONFIG_H_
+
+#include <ConfigBlock.h>
+
+extern EFI_GUID gPmConfigGuid;
+
+#pragma pack (push,1)
+
+/**
+ Description of Global Reset Trigger/Event Mask register
+**/
+typedef union {
+ struct {
+ UINT32 Reserved1 : 1;
+ UINT32 Pbo : 1;
+ UINT32 PmcUncErr : 1;
+ UINT32 PchThrm : 1;
+ UINT32 MePbo : 1;
+ UINT32 CpuThrm : 1;
+ UINT32 Megbl : 1;
+ UINT32 LtReset : 1;
+ UINT32 PmcWdt : 1;
+ UINT32 MeWdt : 1;
+ UINT32 PmcFw : 1;
+ UINT32 PchpwrFlr : 1;
+ UINT32 SyspwrFlr : 1;
+ UINT32 Reserved2 : 1;
+ UINT32 MiaUxsErr : 1;
+ UINT32 MiaUxErr : 1;
+ UINT32 CpuThrmWdt : 1;
+ UINT32 MeUncErr : 1;
+ UINT32 AdrGpio : 1;
+ UINT32 OcwdtNoicc : 1;
+ UINT32 OcwdtIcc : 1;
+ UINT32 CseHecUncErr : 1;
+ UINT32 PmcSramUncErr : 1;
+ UINT32 PmcIromParity : 1;
+ UINT32 PmcRfFusaErr : 1;
+ UINT32 Reserved3 : 4;
+ UINT32 PpbrParityErr : 1;
+ UINT32 Reserved4 : 2;
+ } Field;
+ UINT32 Value;
+} PMC_GLOBAL_RESET_MASK;
+
+typedef union {
+ struct {
+ UINT32 HostResetTimeout : 1;
+ UINT32 SxEntryTimeout : 1;
+ UINT32 HostRstProm : 1;
+ UINT32 HsmbMsg : 1;
+ UINT32 Pmc3Strike : 1;
+ UINT32 FwGblrstScratch5 : 1;
+ UINT32 PmcDmaTimeout : 1;
+ UINT32 EspiType7 : 1;
+ UINT32 EspiType8 : 1;
+ UINT32 FwGblRstScratch10 : 1;
+ UINT32 FwGblRstScratch11 : 1;
+ UINT32 LpmFwErr : 1;
+ UINT32 BscanMode : 1;
+ UINT32 SlpLvlRspErr : 1;
+ UINT32 FwGblrstScratch15 : 1;
+ UINT32 FwGblrstScratch16 : 1;
+ UINT32 FwGblrstScratch17 : 1;
+ UINT32 FwGblrstScratch18 : 1;
+ UINT32 FwGblrstScratch19 : 1;
+ UINT32 FwGblrstScratch20 : 1;
+ UINT32 FwGblrstScratch21 : 1;
+ UINT32 FwGblrstScratch22 : 1;
+ UINT32 FwGblrstScratch23 : 1;
+ UINT32 Rsvd : 9;
+ } Field;
+ UINT32 Value;
+} PMC_GLOBAL_RESET_MASK1;
+
+
+#pragma pack (pop)
+
+#endif // _PM_CONFIG_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Rtc/RtcConfig.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Rtc/RtcConfig.h
new file mode 100644
index 0000000000..62f8303558
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Rtc/RtcConfig.h
@@ -0,0 +1,37 @@
+/** @file
+ RTC policy
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _RTC_CONFIG_H_
+#define _RTC_CONFIG_H_
+
+extern EFI_GUID gRtcConfigGuid;
+
+#pragma pack (push,1)
+
+/**
+ The RTC_CONFIG block describes the expected configuration of RTC configuration.
+**/
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Config Block Header
+ /**
+ When set, prevents RTC TS (BUC.TS) from being changed.
+ This BILD bit has different function compared to LPC/eSPI, SPI.
+ 0: Disabled; <b>1: Enabled</b>
+ **/
+ UINT32 BiosInterfaceLock : 1;
+ /**
+ When set, bytes 38h-3Fh in the upper 128bytes bank of RTC RAM are locked
+ and cannot be accessed.
+ Writes will be droipped and reads will not return any guaranteed data.
+ 0: Disabled; <b>1: Enabled</b>
+ **/
+ UINT32 MemoryLock : 1;
+ UINT32 RsvdBits0 : 30;
+} RTC_CONFIG;
+
+#pragma pack (pop)
+
+#endif // _RTC_CONFIG_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/SerialIo/SerialIoConfig.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/SerialIo/SerialIoConfig.h
new file mode 100644
index 0000000000..b5c3b21606
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/SerialIo/SerialIoConfig.h
@@ -0,0 +1,33 @@
+/** @file
+ Serial IO policy
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _SERIAL_IO_CONFIG_H_
+#define _SERIAL_IO_CONFIG_H_
+
+extern EFI_GUID gSerialIoConfigGuid;
+
+#include <SerialIoDevices.h>
+
+#pragma pack (push,1)
+
+/**
+ The SERIAL_IO_CONFIG block provides the configurations to set the Serial IO controllers
+
+ <b>Revision 1:</b>
+ - Inital version.
+ <b>Revision 2:</b>
+ - Modified SPI Config to support pinmux functionality.
+**/
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Config Block Header
+ SERIAL_IO_SPI_CONFIG SpiDeviceConfig[PCH_MAX_SERIALIO_SPI_CONTROLLERS]; ///< SPI Configuration
+ SERIAL_IO_I2C_CONFIG I2cDeviceConfig[PCH_MAX_SERIALIO_I2C_CONTROLLERS]; ///< I2C Configuration
+ SERIAL_IO_UART_CONFIG UartDeviceConfig[PCH_MAX_SERIALIO_UART_CONTROLLERS]; ///< UART Configuration
+} SERIAL_IO_CONFIG;
+
+#pragma pack (pop)
+
+#endif // _SERIAL_IO_CONFIG_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/SiConfig.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/SiConfig.h
new file mode 100644
index 0000000000..5b59f08df2
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/SiConfig.h
@@ -0,0 +1,105 @@
+/** @file
+ Si Config Block
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _SI_CONFIG_H_
+#define _SI_CONFIG_H_
+
+#define SI_CONFIG_REVISION 1
+
+extern EFI_GUID gSiConfigGuid;
+
+
+#pragma pack (push,1)
+
+/**
+ The Silicon Policy allows the platform code to publish a set of configuration
+ information that the RC drivers will use to configure the silicon hardware.
+
+ <b>Revision 1</b>: - Initial version.
+**/
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Offset 0 - 27 Config Block Header
+ //
+ // Platform specific common policies that used by several silicon components.
+ //
+ UINT8 CsmFlag; ///< offset 28 CSM status flag.@deprecated.
+ /**
+ This is used to skip the SSID programming in silicon code.
+ When set to TRUE, silicon code will not do any SSID programming and platform code
+ needs to handle that by itself properly.
+ <b>0: FALSE</b>, 1: TRUE
+ **/
+ UINT8 SkipSsidProgramming; ///< offset 29
+ UINT8 RsvdBytes0[2]; ///< offset 30 - 31
+ /**
+ When SkipSsidProgramming is FALSE, silicon code will use this as default value
+ to program the SVID for all internal devices.
+ <b>0: use silicon default SVID 0x8086 </b>, Non-zero: use customized SVID.
+ **/
+ UINT16 CustomizedSvid; ///< offset 32 - 33
+ /**
+ When SkipSsidProgramming is FALSE, silicon code will use this as default value
+ to program the Sid for all internal devices.
+ <b>0: use silicon default SSID 0x7270 </b>, Non-zero: use customized SSID.
+ **/
+ UINT16 CustomizedSsid; ///< offset 34 - 35
+ UINT32 *SsidTablePtr; ///< offset 36 - 39
+ /**
+ Number of valid enties in SsidTablePtr.
+ This is valid when SkipSsidProgramming is FALSE;
+ <b>Default is 0.</b>
+ **/
+ UINT16 NumberOfSsidTableEntry; ///< offset 40 - 41
+ UINT8 RsvdBytes1[2]; ///< offset 42 - 43
+ /**
+ This is used to skip setting BIOS_DONE MSR during firmware update boot mode.
+ When set to TRUE and boot mode is BOOT_ON_FLASH_UPDATE,
+ skip setting BIOS_DONE MSR at EndofPei.
+ <b>0: FALSE</b>, 1: TRUE
+ **/
+ UINT8 SkipBiosDoneWhenFwUpdate; ///< Offset 44
+ UINT8 RsvdBytes2[3]; ///< Offset 45 - 47
+} SI_CONFIG;
+
+#pragma pack (pop)
+
+
+///
+/// Subsystem Vendor ID / Subsystem ID
+///
+typedef struct {
+ UINT16 SubSystemVendorId;
+ UINT16 SubSystemId;
+} SVID_SID_VALUE;
+
+//
+// Below is to match PCI_SEGMENT_LIB_ADDRESS () which can directly send to PciSegmentRead/Write functions.
+//
+typedef struct {
+ union {
+ struct {
+ UINT32 Register:12;
+ UINT32 Function:3;
+ UINT32 Device:5;
+ UINT32 Bus:8;
+ UINT32 Reserved1:4;
+ UINT32 Segment:16;
+ UINT32 Reserved2:16;
+ } Bits;
+ UINT64 SegBusDevFuncRegister;
+ } Address;
+ SVID_SID_VALUE SvidSidValue;
+ UINT32 Reserved;
+} SVID_SID_INIT_ENTRY;
+
+
+typedef struct {
+ UINT32 SkipBus;
+ UINT32 SkipDevice;
+ UINT32 SkipFunction;
+} SVID_SID_SKIP_TABLE;
+
+#endif // _SI_CONFIG_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/SiPreMemConfig.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/SiPreMemConfig.h
new file mode 100644
index 0000000000..584a0d4169
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/SiPreMemConfig.h
@@ -0,0 +1,63 @@
+/** @file
+ Si Config Block PreMem
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _SI_PREMEM_CONFIG_H_
+#define _SI_PREMEM_CONFIG_H_
+
+#define SI_PREMEM_CONFIG_REVISION 1
+
+extern EFI_GUID gSiPreMemConfigGuid;
+
+typedef enum {
+ ProbeTypeDisabled = 0x00,
+ ProbeTypeDciOob = 0x02,
+ ProbeType2WireDciOob = 0x06,
+ ProbeTypeManual = 0x07,
+ ProbeTypeMax
+} PLATFORM_DEBUG_CONSENT_PROBE_TYPE;
+
+#pragma pack (push,1)
+/**
+ The Silicon PreMem Policy allows the platform code to publish a set of configuration
+ information that the RC drivers will use to configure the silicon hardware.
+
+ <b>Revision 1</b>:
+ - Initial version.
+**/
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Offset 0 - 27 Config Block Header
+ /**
+ Platform Debug Consent
+ As a main switch to enable platform debug capability and relevant settings with specified probe type.
+ Manual: Do not use Platform Debug Consent to override other debug-relevant policies, but the user must set each debug option manually, aimed at advanced users.
+
+ PDC-dependent policies are listed:
+ DciPreMemConfig->DciEn
+ CpuTraceHubConfig->EnableMode
+ CpuTraceHubConfig->CpuTraceHubMemReg0Size
+ CpuTraceHubConfig->CpuTraceHubMemReg1Size
+ PchTraceHubPreMemConfig->EnableMode
+ PchTraceHubPreMemConfig->MemReg0Size
+ PchTraceHubPreMemConfig->MemReg1Size
+
+ Note: DCI OOB (aka BSSB) uses CCA probe.
+ Refer to definition of PLATFORM_DEBUG_CONSENT_PROBE_TYPE
+ <b>0:Disabled</b>; 2:DCI OOB (All + TraceHubs); 6:2-wire DCI OOB (Low power); 7:Manual
+ **/
+ UINT32 PlatformDebugConsent : 4; /// offset 28 - 31
+ UINT32 RsvdBits : 28;
+ /**
+ This is used to skip override boot mode during firmware update boot mode.
+ When set to TRUE and boot mode is BOOT_ON_FLASH_UPDATE,
+ skip setting boot mode to BOOT_WITH_FULL_CONFIGURATION in PEI memory init.
+ <b>0: FALSE</b>, 1: TRUE
+ **/
+ UINT8 SkipOverrideBootModeWhenFwUpdate; /// offset 32
+ UINT8 RsvdBytes[3]; /// offset 33 - 35
+} SI_PREMEM_CONFIG;
+
+#pragma pack (pop)
+#endif // _SI_PREMEM_CONFIG_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Smbus/SmbusConfig.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Smbus/SmbusConfig.h
new file mode 100644
index 0000000000..2fc724552b
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Smbus/SmbusConfig.h
@@ -0,0 +1,49 @@
+/** @file
+ Smbus policy
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _SMBUS_CONFIG_H_
+#define _SMBUS_CONFIG_H_
+
+extern EFI_GUID gSmbusPreMemConfigGuid;
+
+#pragma pack (push,1)
+
+#define PCH_MAX_SMBUS_RESERVED_ADDRESS 128
+
+///
+/// The SMBUS_CONFIG block lists the reserved addresses for non-ARP capable devices in the platform.
+///
+typedef struct {
+ /**
+ Revision 1: Init version
+ **/
+ CONFIG_BLOCK_HEADER Header; ///< Config Block Header
+ /**
+ This member describes whether or not the SMBus controller of PCH should be enabled.
+ 0: Disable; <b>1: Enable</b>.
+ **/
+ UINT32 Enable : 1;
+ UINT32 ArpEnable : 1; ///< Enable SMBus ARP support, <b>0: Disable</b>; 1: Enable.
+ UINT32 DynamicPowerGating : 1; ///< <b>(Test)</b> <b>Disable</b> or Enable Smbus dynamic power gating.
+ ///
+ /// <b>(Test)</b> SPD Write Disable, 0: leave SPD Write Disable bit; <b>1: set SPD Write Disable bit.</b>
+ /// For security recommendations, SPD write disable bit must be set.
+ ///
+ UINT32 SpdWriteDisable : 1;
+ UINT32 SmbAlertEnable : 1; ///< Enable SMBus Alert pin (SMBALERT#). 0: <b>Disabled<b>, 1: Enabled.
+ UINT32 RsvdBits0 : 27; ///< Reserved bits
+ UINT16 SmbusIoBase; ///< SMBUS Base Address (IO space). Default is <b>0xEFA0</b>.
+ UINT8 Rsvd0; ///< Reserved bytes
+ UINT8 NumRsvdSmbusAddresses; ///< The number of elements in the RsvdSmbusAddressTable.
+ /**
+ Array of addresses reserved for non-ARP-capable SMBus devices.
+ **/
+ UINT8 RsvdSmbusAddressTable[PCH_MAX_SMBUS_RESERVED_ADDRESS];
+} PCH_SMBUS_PREMEM_CONFIG;
+
+#pragma pack (pop)
+
+#endif // _SMBUS_CONFIG_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Spi/FlashProtectionConfig.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Spi/FlashProtectionConfig.h
new file mode 100644
index 0000000000..45dc538064
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Spi/FlashProtectionConfig.h
@@ -0,0 +1,54 @@
+/** @file
+ FlashProtection policy
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _FLASH_PROTECTION_CONFIG_H_
+#define _FLASH_PROTECTION_CONFIG_H_
+
+extern EFI_GUID gFlashProtectionConfigGuid;
+
+#pragma pack (push,1)
+
+//
+// Flash Protection Range Register
+//
+#define PCH_FLASH_PROTECTED_RANGES 5
+
+/**
+ Protected Flash Range
+**/
+typedef struct {
+ UINT32 WriteProtectionEnable : 1; ///< Write or erase is blocked by hardware. <b>0: Disable</b>; 1: Enable.
+ UINT32 ReadProtectionEnable : 1; ///< Read is blocked by hardware. <b>0: Disable</b>; 1: Enable.
+ UINT32 RsvdBits : 30; ///< Reserved
+ /**
+ The address of the upper limit of protection
+ This is a left shifted address by 12 bits with address bits 11:0 are assumed to be FFFh for limit comparison
+ **/
+ UINT16 ProtectedRangeLimit;
+ /**
+ The address of the upper limit of protection
+ This is a left shifted address by 12 bits with address bits 11:0 are assumed to be 0
+ **/
+ UINT16 ProtectedRangeBase;
+} PROTECTED_RANGE;
+
+/**
+ The PCH provides a method for blocking writes and reads to specific ranges
+ in the SPI flash when the Protected Ranges are enabled.
+ PROTECTED_RANGE is used to specify if flash protection are enabled,
+ the write protection enable bit and the read protection enable bit,
+ and to specify the upper limit and lower base for each register
+ Platform code is responsible to get the range base by PchGetSpiRegionAddresses routine,
+ and set the limit and base accordingly.
+**/
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Config Block Header
+ PROTECTED_RANGE ProtectRange[PCH_FLASH_PROTECTED_RANGES]; ///< Protected Flash Ranges
+} PCH_FLASH_PROTECTION_CONFIG;
+
+#pragma pack (pop)
+
+#endif // _FLASH_PROTECTION_CONFIG_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Tcss/TcssPeiConfig.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Tcss/TcssPeiConfig.h
new file mode 100644
index 0000000000..95bcaaa951
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Tcss/TcssPeiConfig.h
@@ -0,0 +1,71 @@
+/** @file
+ TCSS PEI policy
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _TCSS_PEI_CONFIG_H_
+#define _TCSS_PEI_CONFIG_H_
+
+#include <ConfigBlock.h>
+
+extern EFI_GUID gTcssPeiConfigGuid;
+
+#pragma pack (push,1)
+
+
+#define MAX_IOM_AUX_BIAS_COUNT 4
+
+///
+/// The IOM_AUX_ORI_PAD_CONFIG describes IOM TypeC port map GPIO pin.
+/// Those GPIO setting for DP Aux Orientation Bias Control when the TypeC port didn't have re-timer.
+/// IOM needs know Pull-Up and Pull-Down pin for Bias control
+///
+typedef struct {
+ UINT32 GpioPullN; ///< GPIO Pull Up Ping number that is for IOM indecate the pull up pin from TypeC port.
+ UINT32 GpioPullP; ///< GPIO Pull Down Ping number that is for IOM indecate the pull down pin from TypeC port.
+} IOM_AUX_ORI_PAD_CONFIG;
+
+///
+/// The IOM_EC_INTERFACE_CONFIG block describes interaction between BIOS and IOM-EC.
+///
+
+typedef struct {
+ UINT32 VccSt; ///< IOM VCCST request. (Not equal to actual VCCST value)
+ UINT32 UsbOverride; ///< IOM to override USB connection.
+ UINT32 D3ColdEnable; ///< Enable/disable D3 Cold support in TCSS
+ UINT32 D3HotEnable; ///< Enable/disable D3 Hot support in TCSS
+} IOM_INTERFACE_CONFIG;
+
+///
+/// The PMC_INTERFACE_CONFIG block describes interaction between BIOS and PMC
+///
+typedef struct {
+ UINT8 PmcPdEnable; ///< PMC PD Solution Enable
+ UINT8 Rsvd[3];
+} PMC_INTERFACE_CONFIG;
+
+///
+/// The TCSS_IOM_PEI_CONFIG block describes IOM Aux/HSL override settings for TCSS.
+///
+typedef struct {
+ UINT16 AuxOri; ///< Bits defining value for IOM Aux Orientation Register
+ UINT16 HslOri; ///< Bits defining value for IOM HSL Orientation Register
+} TCSS_IOM_ORI_OVERRIDE;
+
+///
+/// The TCSS_IOM_PEI_CONFIG block describes IOM settings for TCSS.
+///
+typedef struct {
+ IOM_AUX_ORI_PAD_CONFIG IomAuxPortPad[MAX_IOM_AUX_BIAS_COUNT]; ///< The IOM_AUX_ORI_BIAS_CTRL port config setting.
+ TCSS_IOM_ORI_OVERRIDE IomOverrides;
+ IOM_INTERFACE_CONFIG IomInterface; ///< Config settings are BIOS <-> IOM interface.
+ PMC_INTERFACE_CONFIG PmcInterface; ///< Config settings for BIOS <-> PMC interface
+ UINT8 TcStateLimit; ///< Tcss C-State deep stage
+ UINT8 Reserved[3]; ///< Reserved bytes for future use
+} TCSS_IOM_PEI_CONFIG;
+
+
+#pragma pack (pop)
+
+#endif /* _TCSS_PEI_CONFIG_H_ */
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Vmd/VmdPeiConfig.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Vmd/VmdPeiConfig.h
new file mode 100644
index 0000000000..37e6439abb
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Vmd/VmdPeiConfig.h
@@ -0,0 +1,60 @@
+/** @file
+ VMD PEI policy
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _VMD_PEI_CONFIG_H_
+#define _VMD_PEI_CONFIG_H_
+
+#include <ConfigBlock.h>
+
+#pragma pack (push,1)
+
+#define VMD_MAX_DEVICES 31
+
+typedef struct {
+ UINT8 RpBus;
+ UINT8 RpDevice;
+ UINT8 RpFunction;
+ UINT8 RpEnable;
+} RP_BDF_DATA;
+
+/**
+ This configuration block is to configure VMD related variables used in PostMem PEI.
+ If VMD Device is not supported, all policies can be ignored.
+ <b>Revision 1</b>:
+ - Initial version.
+ <b>Revision 2</b>:
+ - Deprecated VmdPortAEnable, VmdPortBEnable, VmdPortCEnable, VmdPortDEnable.
+ - Added VmdPortEnable[VMD_MAX_DEVICES] and structure to hold Vmd EFI Variable details.
+ (Added B/D/F fields along with Port Enable for up to max 31 devices).
+ <b>Revision 3</b>:
+ Added policy to get the Bar values from platform PCD.
+ <b>Revision 4</b>: Added VmdGlobalMapping to map all the storage devices under VMD
+**/
+
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Block Header
+ UINT8 VmdEnable; ///< Offset 28 This field used to enable VMD controller 1=Enable <b>0=Disable(default)</b>
+ UINT8 VmdPortAEnable; /// Deprecated < Offset 29 This field used to enable VMD portA Support 1=Enable and 0=Disable (default)
+ UINT8 VmdPortBEnable; /// Deprecated < Offset 30 This field used to enable VMD portB Support 1=Enable and 0=Disable (default)
+ UINT8 VmdPortCEnable; /// Deprecated < Offset 31 This field used to enable VMD portC Support 1=Enable and 0=Disable (default)
+ UINT8 VmdPortDEnable; /// Deprecated < Offset 32 This field used to enable VMD portD Support 1=Enable and 0=Disable (default)
+ UINT8 VmdCfgBarSize; ///< Offset 33 This is used to set the VMD Config Bar Size. <b>25(32MB)</b>
+ UINT8 VmdCfgBarAttr; ///< Offset 34 This is used to set VMD Config Bar Attributes 0: VMD_32BIT_NONPREFETCH, 1: VMD_64BIT_PREFETCH, <b>2: VMD_64BIT_NONPREFETCH(Default)</b>
+ UINT8 VmdMemBarSize1; ///< Offset 35 This is used to set the VMD Mem Bar1 size. <b>25 (32MB)</b>.
+ UINT8 VmdMemBar1Attr; ///< Offset 36 This is used to set VMD Mem Bar1 Attributes <b>0: VMD_32BIT_NONPREFETCH(Default) </b> 1: VMD_64BIT_NONPREFETCH, 2: VMD_64BIT_PREFETCH
+ UINT8 VmdMemBarSize2; ///< Offset 37 This is used to set the VMD Mem Bar2 size. <b>20(1MB)</b>.
+ UINT8 VmdMemBar2Attr; ///< Offset 38 This is used to set VMD Mem Bar2 Attributes 0: VMD_32BIT_NONPREFETCH <b>1: VMD_64BIT_NONPREFETCH(Default)</b>, 2: VMD_64BIT_PREFETCH
+ UINT8 VmdGlobalMapping; ///< Offset 39 This field used to enable Global Mapping 1=Enable <b>0=Disable(default)</b>
+ RP_BDF_DATA VmdPortEnable[VMD_MAX_DEVICES]; ///< Offset 40 to 163 This field used to to store b/d/f for each root port along with enable Support 1=Enable <b>0=Disable (default)</b>
+ VOID *VmdVariablePtr; /// This config block will be updated as per the EFI variable.
+ UINT32 VmdCfgBarBase; /// Temp Address VMD CFG BAR Default is <b>0xA0000000</b>
+ UINT32 VmdMemBar1Base; /// Temp Address VMD CFG BAR Default is <b>0xA2000000</b>
+ UINT32 VmdMemBar2Base; /// Temp Address VMD CFG BAR Default is <b>0xA4000000</b>
+} VMD_PEI_CONFIG;
+
+#pragma pack (pop)
+
+#endif /* _VMD_PEI_PREMEM_CONFIG_H_ */
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Wdt/WatchDogConfig.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Wdt/WatchDogConfig.h
new file mode 100644
index 0000000000..ad17488ecc
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Wdt/WatchDogConfig.h
@@ -0,0 +1,30 @@
+/** @file
+ WatchDog policy
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _WATCH_DOG_CONFIG_H_
+#define _WATCH_DOG_CONFIG_H_
+
+extern EFI_GUID gWatchDogPreMemConfigGuid;
+
+#pragma pack (push,1)
+
+/**
+ This policy clears status bits and disable watchdog, then lock the
+ WDT registers.
+ while WDT is designed to be disabled and locked by Policy,
+ bios should not enable WDT by WDT PPI. In such case, bios shows the
+ warning message but not disable and lock WDT register to make sure
+ WDT event trigger correctly.
+**/
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Config Block Header
+ UINT32 DisableAndLock : 1; ///< <b>(Test)</b> Set 1 to clear WDT status, then disable and lock WDT registers. <b>0: Disable</b>; 1: Enable.
+ UINT32 RsvdBits : 31;
+} PCH_WDT_PREMEM_CONFIG;
+
+#pragma pack (pop)
+
+#endif // _WATCH_DOG_CONFIG_H_
--
2.36.1.windows.1
-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#108681): https://edk2.groups.io/g/devel/message/108681
Mute This Topic: https://groups.io/mt/101373949/7686176
Group Owner: devel+owner@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [rebecca@openfw.io]
-=-=-=-=-=-=-=-=-=-=-=-
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [edk2-devel] [PATCH v2 06/10] AlderlakeSiliconPkg/Include: Add Library, Pins, Ppi Includes
2023-09-15 4:45 [edk2-devel] [PATCH v2 01/10] AlderlakeSiliconPkg/IpBlock: Add CpuPcieRp, Espi, Gpio components Saloni Kasbekar
` (3 preceding siblings ...)
2023-09-15 4:45 ` [edk2-devel] [PATCH v2 05/10] AlderlakeSiliconPkg/Include: Add ConfigBlock headers Saloni Kasbekar
@ 2023-09-15 4:45 ` Saloni Kasbekar
2023-09-15 5:43 ` Chaganty, Rangasai V
2023-09-15 23:56 ` Nate DeSimone
2023-09-15 4:45 ` [edk2-devel] [PATCH v2 07/10] AlderlakeSiliconPkg/Include: Add Protocol, Register, Other Includes Saloni Kasbekar
` (6 subsequent siblings)
11 siblings, 2 replies; 41+ messages in thread
From: Saloni Kasbekar @ 2023-09-15 4:45 UTC (permalink / raw)
To: devel; +Cc: Saloni Kasbekar, Sai Chaganty, Nate DeSimone, Rosen Chuang
Adds the following Includes:
- Include/Library
- Include/Pins
- Include/Ppi
Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Rosen Chuang <rosen.chuang@intel.com>
Signed-off-by: Saloni Kasbekar <saloni.kasbekar@intel.com>
---
.../Include/Library/ConfigBlockLib.h | 64 +++
.../Include/Library/EspiLib.h | 34 ++
.../Include/Library/GpioConfig.h | 372 ++++++++++++++++++
.../Include/Library/GpioLib.h | 174 ++++++++
.../Include/Library/GpioNativeLib.h | 135 +++++++
.../Include/Library/GraphicsInfoLib.h | 46 +++
.../Include/Library/MmPciLib.h | 27 ++
.../Include/Library/PchPcieRpLib.h | 41 ++
.../Include/Library/PchPcrLib.h | 221 +++++++++++
.../Library/PeiDxeSmmReserveMmio64SizeLib.h | 21 +
.../Include/Library/PeiSiPolicyUpdateLib.h | 154 ++++++++
.../Include/Library/PmcLib.h | 40 ++
.../Include/Library/ResetSystemLib.h | 68 ++++
.../Include/Library/SecPlatformLib.h | 81 ++++
.../Include/Library/SiConfigBlockLib.h | 56 +++
.../Include/Library/SiPolicyLib.h | 39 ++
.../Include/Library/SpiLib.h | 21 +
.../Include/Pins/GpioPinsVer2Lp.h | 36 ++
.../Include/Ppi/FspmArchConfigPpi.h | 32 ++
.../Include/Ppi/PeiPreMemSiDefaultPolicy.h | 33 ++
.../Include/Ppi/PeiSiDefaultPolicy.h | 33 ++
.../AlderlakeSiliconPkg/Include/Ppi/Spi.h | 29 ++
.../AlderlakeSiliconPkg/Include/Ppi/Wdt.h | 22 ++
23 files changed, 1779 insertions(+)
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Library/ConfigBlockLib.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Library/EspiLib.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Library/GpioConfig.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Library/GpioLib.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Library/GpioNativeLib.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Library/GraphicsInfoLib.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Library/MmPciLib.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Library/PchPcieRpLib.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Library/PchPcrLib.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Library/PeiDxeSmmReserveMmio64SizeLib.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Library/PeiSiPolicyUpdateLib.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Library/PmcLib.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Library/ResetSystemLib.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Library/SecPlatformLib.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Library/SiConfigBlockLib.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Library/SiPolicyLib.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Library/SpiLib.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Pins/GpioPinsVer2Lp.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Ppi/FspmArchConfigPpi.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Ppi/PeiPreMemSiDefaultPolicy.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Ppi/PeiSiDefaultPolicy.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Ppi/Spi.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Ppi/Wdt.h
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/ConfigBlockLib.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/ConfigBlockLib.h
new file mode 100644
index 0000000000..d9966c76e9
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/ConfigBlockLib.h
@@ -0,0 +1,64 @@
+/** @file
+ Header file for Config Block Lib implementation
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _CONFIG_BLOCK_LIB_H_
+#define _CONFIG_BLOCK_LIB_H_
+
+/**
+ Create config block table
+
+ @param[in] TotalSize - Max size to be allocated for the Config Block Table
+ @param[out] ConfigBlockTableAddress - On return, points to a pointer to the beginning of Config Block Table Address
+
+ @retval EFI_INVALID_PARAMETER - Invalid Parameter
+ @retval EFI_OUT_OF_RESOURCES - Out of resources
+ @retval EFI_SUCCESS - Successfully created Config Block Table at ConfigBlockTableAddress
+**/
+EFI_STATUS
+EFIAPI
+CreateConfigBlockTable (
+ IN UINT16 TotalSize,
+ OUT VOID **ConfigBlockTableAddress
+ );
+
+/**
+ Add config block into config block table structure
+
+ @param[in] ConfigBlockTableAddress - A pointer to the beginning of Config Block Table Address
+ @param[out] ConfigBlockAddress - On return, points to a pointer to the beginning of Config Block Address
+
+ @retval EFI_OUT_OF_RESOURCES - Config Block Table is full and cannot add new Config Block or
+ Config Block Offset Table is full and cannot add new Config Block.
+ @retval EFI_SUCCESS - Successfully added Config Block
+**/
+EFI_STATUS
+EFIAPI
+AddConfigBlock (
+ IN VOID *ConfigBlockTableAddress,
+ OUT VOID **ConfigBlockAddress
+ );
+
+/**
+ Retrieve a specific Config Block data by GUID
+
+ @param[in] ConfigBlockTableAddress - A pointer to the beginning of Config Block Table Address
+ @param[in] ConfigBlockGuid - A pointer to the GUID uses to search specific Config Block
+ @param[out] ConfigBlockAddress - On return, points to a pointer to the beginning of Config Block Address
+
+ @retval EFI_NOT_FOUND - Could not find the Config Block
+ @retval EFI_SUCCESS - Config Block found and return
+**/
+EFI_STATUS
+EFIAPI
+GetConfigBlock (
+ IN VOID *ConfigBlockTableAddress,
+ IN EFI_GUID *ConfigBlockGuid,
+ OUT VOID **ConfigBlockAddress
+ );
+
+#endif // _CONFIG_BLOCK_LIB_H_
+
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/EspiLib.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/EspiLib.h
new file mode 100644
index 0000000000..3c37def986
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/EspiLib.h
@@ -0,0 +1,34 @@
+/** @file
+ Header file for PchEspiLib.
+ All function in this library is available for PEI, DXE, and SMM,
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _ESPI_LIB_H_
+#define _ESPI_LIB_H_
+
+/**
+ Checks if there's second device connected under CS#1
+
+ @retval TRUE There's second device
+ @retval FALSE There's no second device
+**/
+BOOLEAN
+IsEspiSecondSlaveSupported (
+ VOID
+ );
+
+/**
+ Is eSPI enabled in strap.
+
+ @retval TRUE Espi is enabled in strap
+ @retval FALSE Espi is disabled in strap
+**/
+BOOLEAN
+IsEspiEnabled (
+ VOID
+ );
+
+#endif // _ESPI_LIB_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/GpioConfig.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/GpioConfig.h
new file mode 100644
index 0000000000..43c0da46d7
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/GpioConfig.h
@@ -0,0 +1,372 @@
+/** @file
+ Header file for GpioConfig structure used by GPIO library.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _GPIO_CONFIG_H_
+#define _GPIO_CONFIG_H_
+
+#pragma pack(push, 1)
+
+///
+/// For any GpioPad usage in code use GPIO_PAD type
+///
+typedef UINT32 GPIO_PAD;
+
+///
+/// GpioPad with additional native function information.
+/// This type is used to represent signal muxing alternatives. Platform will provide such value to
+/// identify muxing selection for given signal on a specific SOC.
+/// Please refer to the board layout
+///
+typedef UINT32 GPIO_NATIVE_PAD;
+
+
+///
+/// For any GpioGroup usage in code use GPIO_GROUP type
+///
+typedef UINT32 GPIO_GROUP;
+
+/**
+ GPIO configuration structure used for pin programming.
+ Structure contains fields that can be used to configure pad.
+**/
+typedef struct {
+ /**
+ Pad Mode
+ Pad can be set as GPIO or one of its native functions.
+ When in native mode setting Direction (except Inversion), OutputState,
+ InterruptConfig, Host Software Pad Ownership and OutputStateLock are unnecessary.
+ Refer to definition of GPIO_PAD_MODE.
+ Refer to EDS for each native mode according to the pad.
+ **/
+ UINT32 PadMode : 5;
+ /**
+ Host Software Pad Ownership
+ Set pad to ACPI mode or GPIO Driver Mode.
+ Refer to definition of GPIO_HOSTSW_OWN.
+ **/
+ UINT32 HostSoftPadOwn : 2;
+ /**
+ GPIO Direction
+ Can choose between In, In with inversion, Out, both In and Out, both In with inversion and out or disabling both.
+ Refer to definition of GPIO_DIRECTION for supported settings.
+ **/
+ UINT32 Direction : 6;
+ /**
+ Output State
+ Set Pad output value.
+ Refer to definition of GPIO_OUTPUT_STATE for supported settings.
+ This setting takes place when output is enabled.
+ **/
+ UINT32 OutputState : 2;
+ /**
+ GPIO Interrupt Configuration
+ Set Pad to cause one of interrupts (IOxAPIC/SCI/SMI/NMI).
+ This setting is applicable only if GPIO is in GpioMode with input enabled.
+ Refer to definition of GPIO_INT_CONFIG for supported settings.
+ **/
+ UINT32 InterruptConfig : 9;
+ /**
+ GPIO Power Configuration.
+ This setting controls Pad Reset Configuration.
+ Refer to definition of GPIO_RESET_CONFIG for supported settings.
+ **/
+ UINT32 PowerConfig : 8;
+ /**
+ GPIO Electrical Configuration
+ This setting controls pads termination.
+ Refer to definition of GPIO_ELECTRICAL_CONFIG for supported settings.
+ **/
+ UINT32 ElectricalConfig : 9;
+ /**
+ GPIO Lock Configuration
+ This setting controls pads lock.
+ Refer to definition of GPIO_LOCK_CONFIG for supported settings.
+ **/
+ UINT32 LockConfig : 4;
+ /**
+ Additional GPIO configuration
+ Refer to definition of GPIO_OTHER_CONFIG for supported settings.
+ **/
+ UINT32 OtherSettings : 9;
+
+ /**
+ Virtual GPIO eSPI Chip Select configuration
+ This setting selects between CS0 and CS1.
+ Refer to definition of VGPIO_CS_CONFIG for supported settings.
+ **/
+ UINT32 VgpioCs : 2;
+
+ UINT32 RsvdBits : 8; ///< Reserved bits for future extension
+} GPIO_CONFIG;
+
+
+typedef enum {
+ GpioHardwareDefault = 0x0 ///< Leave setting unmodified
+} GPIO_HARDWARE_DEFAULT;
+
+/**
+ GPIO Pad Mode
+ Refer to GPIO documentation on native functions available for certain pad.
+ If GPIO is set to one of NativeX modes then following settings are not applicable
+ and can be skipped:
+ - Interrupt related settings
+ - Host Software Ownership
+ - Output/Input enabling/disabling
+ - Output lock
+**/
+typedef enum {
+ GpioPadModeHwDefault = 0x0,
+ GpioPadModeGpio = 0x1,
+ GpioPadModeNative1 = 0x3,
+ GpioPadModeNative2 = 0x5,
+ GpioPadModeNative3 = 0x7,
+ GpioPadModeNative4 = 0x9,
+ GpioPadModeNative5 = 0xB,
+ GpioPadModeNative6 = 0xD,
+ GpioPadModeNative7 = 0xF
+} GPIO_PAD_MODE;
+
+/**
+ Host Software Pad Ownership modes
+ This setting affects GPIO interrupt status registers. Depending on chosen ownership
+ some GPIO Interrupt status register get updated and other masked.
+ Please refer to EDS for HOSTSW_OWN register description.
+**/
+typedef enum {
+ GpioHostOwnDefault = 0x0, ///< Leave ownership value unmodified
+ /**
+ Set HOST ownership to ACPI.
+ Use this setting if pad is not going to be used by GPIO OS driver.
+ If GPIO is configured to generate SCI/SMI/NMI then this setting must be
+ used for interrupts to work
+ **/
+ GpioHostOwnAcpi = 0x1,
+ /**
+ Set HOST ownership to GPIO Driver mode.
+ Use this setting only if GPIO pad should be controlled by GPIO OS Driver.
+ GPIO OS Driver will be able to control the pad if appropriate entry in
+ ACPI exists (refer to ACPI specification for GpioIo and GpioInt descriptors)
+ **/
+ GpioHostOwnGpio = 0x3
+} GPIO_HOSTSW_OWN;
+
+///
+/// GPIO Direction
+///
+typedef enum {
+ GpioDirDefault = 0x0, ///< Leave pad direction setting unmodified
+ GpioDirInOut = (0x1 | (0x1 << 3)), ///< Set pad for both output and input
+ GpioDirInInvOut = (0x1 | (0x3 << 3)), ///< Set pad for both output and input with inversion
+ GpioDirIn = (0x3 | (0x1 << 3)), ///< Set pad for input only
+ GpioDirInInv = (0x3 | (0x3 << 3)), ///< Set pad for input with inversion
+ GpioDirOut = 0x5, ///< Set pad for output only
+ GpioDirNone = 0x7 ///< Disable both output and input
+} GPIO_DIRECTION;
+
+/**
+ GPIO Output State
+ This field is relevant only if output is enabled
+**/
+typedef enum {
+ GpioOutDefault = 0x0, ///< Leave output value unmodified
+ GpioOutLow = 0x1, ///< Set output to low
+ GpioOutHigh = 0x3 ///< Set output to high
+} GPIO_OUTPUT_STATE;
+
+/**
+ GPIO interrupt configuration
+ This setting is applicable only if pad is in GPIO mode and has input enabled.
+ GPIO_INT_CONFIG allows to choose which interrupt is generated (IOxAPIC/SCI/SMI/NMI)
+ and how it is triggered (edge or level). Refer to PADCFG_DW0 register description in
+ EDS for details on this settings.
+ Field from GpioIntNmi to GpioIntApic can be OR'ed with GpioIntLevel to GpioIntBothEdge
+ to describe an interrupt e.g. GpioIntApic | GpioIntLevel
+ If GPIO is set to cause an SCI then also GPI_GPE_EN is enabled for this pad.
+ If GPIO is set to cause an NMI then also GPI_NMI_EN is enabled for this pad.
+ Not all GPIO are capable of generating an SMI or NMI interrupt.
+ When routing GPIO to cause an IOxAPIC interrupt care must be taken, as this
+ interrupt cannot be shared and its IRQn number is not configurable.
+ Refer to EDS for GPIO pads IRQ numbers (PADCFG_DW1.IntSel)
+ If GPIO is under GPIO OS driver control and appropriate ACPI GpioInt descriptor
+ exist then use only trigger type setting (from GpioIntLevel to GpioIntBothEdge).
+ This type of GPIO Driver interrupt doesn't have any additional routing setting
+ required to be set by BIOS. Interrupt is handled by GPIO OS Driver.
+**/
+
+typedef enum {
+ GpioIntDefault = 0x0, ///< Leave value of interrupt routing unmodified
+ GpioIntDis = 0x1, ///< Disable IOxAPIC/SCI/SMI/NMI interrupt generation
+ GpioIntNmi = 0x3, ///< Enable NMI interrupt only
+ GpioIntSmi = 0x5, ///< Enable SMI interrupt only
+ GpioIntSci = 0x9, ///< Enable SCI interrupt only
+ GpioIntApic = 0x11, ///< Enable IOxAPIC interrupt only
+ GpioIntLevel = (0x1 << 5), ///< Set interrupt as level triggered
+ GpioIntEdge = (0x3 << 5), ///< Set interrupt as edge triggered (type of edge depends on input inversion)
+ GpioIntLvlEdgDis = (0x5 << 5), ///< Disable interrupt trigger
+ GpioIntBothEdge = (0x7 << 5) ///< Set interrupt as both edge triggered
+} GPIO_INT_CONFIG;
+
+#define B_GPIO_INT_CONFIG_INT_SOURCE_MASK 0x1F ///< Mask for GPIO_INT_CONFIG for interrupt source
+#define B_GPIO_INT_CONFIG_INT_TYPE_MASK 0xE0 ///< Mask for GPIO_INT_CONFIG for interrupt type
+
+/**
+ GPIO Power Configuration
+ GPIO_RESET_CONFIG allows to set GPIO Reset type (PADCFG_DW0.PadRstCfg) which will
+ be used to reset certain GPIO settings.
+ Refer to EDS for settings that are controllable by PadRstCfg.
+**/
+typedef enum {
+ GpioResetDefault = 0x00, ///< Leave value of pad reset unmodified
+ /**
+ Resume Reset (RSMRST)
+ GPP: PadRstCfg = 00b = "Powergood"
+ GPD: PadRstCfg = 11b = "Resume Reset"
+ Pad setting will reset on:
+ - DeepSx transition
+ - G3
+ Pad settings will not reset on:
+ - S3/S4/S5 transition
+ - Warm/Cold/Global reset
+ **/
+ GpioResumeReset = 0x01,
+ /**
+ Host Deep Reset
+ PadRstCfg = 01b = "Deep GPIO Reset"
+ Pad settings will reset on:
+ - Warm/Cold/Global reset
+ - DeepSx transition
+ - G3
+ Pad settings will not reset on:
+ - S3/S4/S5 transition
+ **/
+ GpioHostDeepReset = 0x03,
+ /**
+ Platform Reset (PLTRST)
+ PadRstCfg = 10b = "GPIO Reset"
+ Pad settings will reset on:
+ - S3/S4/S5 transition
+ - Warm/Cold/Global reset
+ - DeepSx transition
+ - G3
+ **/
+ GpioPlatformReset = 0x05,
+ /**
+ Deep Sleep Well Reset (DSW_PWROK)
+ GPP: not applicable
+ GPD: PadRstCfg = 00b = "Powergood"
+ Pad settings will reset on:
+ - G3
+ Pad settings will not reset on:
+ - S3/S4/S5 transition
+ - Warm/Cold/Global reset
+ - DeepSx transition
+ **/
+ GpioDswReset = 0x07,
+ /**
+ Global reset. Server chipsets only.
+ PadRstCfg = 11b = "Global reset"
+ Pad settings will reset on:
+ - Global reset
+ - G3
+ Pad settings will not reset on:
+ - S3/S4/S5 transition
+ - Warm/Cold reset
+ - DeepSx transition
+ **/
+ GpioGlobalReset = 0x09
+} GPIO_RESET_CONFIG;
+
+/**
+ GPIO Electrical Configuration
+ Configuration options for GPIO termination setting
+**/
+typedef enum {
+ GpioTermDefault = 0x0, ///< Leave termination setting unmodified
+ GpioTermNone = 0x1, ///< none
+ GpioTermWpd5K = 0x5, ///< 5kOhm weak pull-down
+ GpioTermWpd20K = 0x9, ///< 20kOhm weak pull-down
+ GpioTermWpu1K = 0x13, ///< 1kOhm weak pull-up
+ GpioTermWpu2K = 0x17, ///< 2kOhm weak pull-up
+ GpioTermWpu5K = 0x15, ///< 5kOhm weak pull-up
+ GpioTermWpu20K = 0x19, ///< 20kOhm weak pull-up
+ GpioTermWpu1K2K = 0x1B, ///< 1kOhm & 2kOhm weak pull-up
+ /**
+ Native function controls pads termination
+ This setting is applicable only to some native modes.
+ Please check EDS to determine which native functionality
+ can control pads termination
+ **/
+ GpioTermNative = 0x1F
+} GPIO_ELECTRICAL_CONFIG;
+
+#define B_GPIO_ELECTRICAL_CONFIG_TERMINATION_MASK 0x1F ///< Mask for GPIO_ELECTRICAL_CONFIG for termination value
+
+/**
+ GPIO LockConfiguration
+ Set GPIO configuration lock and output state lock.
+ GpioPadConfigUnlock/Lock and GpioOutputStateUnlock can be OR'ed.
+ By default GPIO pads will be locked unless GPIO lib is explicitly
+ informed that certain pad is to be left unlocked.
+ Lock settings reset is in Powergood domain. Care must be taken when using this setting
+ as fields it locks may be reset by a different signal and can be controlled
+ by what is in GPIO_RESET_CONFIG (PADCFG_DW0.PadRstCfg). GPIO library provides
+ functions which allow to unlock a GPIO pad. If possible each GPIO lib function will try to unlock
+ an already locked pad upon request for reconfiguration
+**/
+typedef enum {
+ /**
+ Perform default action
+ - if pad is an GPO, lock configuration but leave output unlocked
+ - if pad is an GPI, lock everything
+ - if pad is in native, lock everything
+**/
+ GpioLockDefault = 0x0,
+ GpioPadConfigUnlock = 0x3, ///< Leave Pad configuration unlocked
+ GpioPadConfigLock = 0x1, ///< Lock Pad configuration
+ GpioOutputStateUnlock = 0xC, ///< Leave Pad output control unlocked
+ GpioPadUnlock = 0xF, ///< Leave both Pad configuration and output control unlocked
+ GpioPadLock = 0x5, ///< Lock both Pad configuration and output control
+ /**
+ Below statuses are used for
+ return from GpioGetPadConfig function
+ **/
+ GpioLockTxLockCfgUnLock = 0x7, ///< Tx State locked, Pad Configuration unlocked
+ GpioLockTxUnLockCfgLock = 0xD ///< Tx State unlocked, Pad Configuration locked
+} GPIO_LOCK_CONFIG;
+
+#define B_GPIO_LOCK_CONFIG_PAD_CONF_LOCK_MASK 0x3 ///< Mask for GPIO_LOCK_CONFIG for Pad Configuration Lock
+#define B_GPIO_LOCK_CONFIG_OUTPUT_LOCK_MASK 0xC ///< Mask for GPIO_LOCK_CONFIG for Pad Output Lock
+
+/**
+ Other GPIO Configuration
+ GPIO_OTHER_CONFIG is used for less often settings and for future extensions
+ Supported settings:
+ - RX raw override to '1' - allows to override input value to '1'
+ This setting is applicable only if in input mode (both in GPIO and native usage).
+ The override takes place at the internal pad state directly from buffer and before the RXINV.
+**/
+typedef enum {
+ GpioRxRaw1Default = 0x0, ///< Use default input override value
+ GpioRxRaw1Dis = 0x1, ///< Don't override input
+ GpioRxRaw1En = 0x3 ///< Override input to '1'
+} GPIO_OTHER_CONFIG;
+
+/**
+ Virtual GPIO eSPI Chip Select configuration
+ This setting selects between CS0 and CS1.
+ Supported settings:
+ - Chipselect CS0 and CS1
+**/
+typedef enum {
+ VgpioCs0 = 0x0, ///< Chipselect CS0
+ VgpioCs1 = 0x1, ///< Chipselect CS1
+} VGPIO_CS_CONFIG;
+
+#define B_GPIO_OTHER_CONFIG_RXRAW_MASK 0x3 ///< Mask for GPIO_OTHER_CONFIG for RxRaw1 setting
+
+#pragma pack(pop)
+
+#endif //_GPIO_CONFIG_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/GpioLib.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/GpioLib.h
new file mode 100644
index 0000000000..d787e13be4
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/GpioLib.h
@@ -0,0 +1,174 @@
+/** @file
+ Header file for GpioLib.
+ All function in this library is available for PEI, DXE, and SMM
+
+ @note: When GPIO pads are owned by ME Firmware, BIOS/host should not
+ attempt to access these GPIO Pads registers, registers value
+ returned in this case will be 0xFF.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _GPIO_LIB_H_
+#define _GPIO_LIB_H_
+
+#include <Library/GpioConfig.h>
+
+typedef struct {
+ GPIO_PAD GpioPad;
+ GPIO_CONFIG GpioConfig;
+} GPIO_INIT_CONFIG;
+
+/**
+ This procedure will initialize multiple GPIO pins. Use GPIO_INIT_CONFIG structure.
+ Structure contains fields that can be used to configure each pad.
+ Pad not configured using GPIO_INIT_CONFIG will be left with hardware default values.
+ Separate fields could be set to hardware default if it does not matter, except
+ GpioPad and PadMode.
+ Function will work in most efficient way if pads which belong to the same group are
+ placed in adjacent records of the table.
+ Although function can enable pads for Native mode, such programming is done
+ by reference code when enabling related silicon feature.
+
+ @param[in] NumberofItem Number of GPIO pads to be updated
+ @param[in] GpioInitTableAddress GPIO initialization table
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid group or pad number
+**/
+EFI_STATUS
+GpioConfigurePads (
+ IN UINT32 NumberOfItems,
+ IN GPIO_INIT_CONFIG *GpioInitTableAddress
+ );
+
+///
+/// Possible values of Pad Ownership
+/// If Pad is not under Host ownership then GPIO registers
+/// are not accessible by host (e.g. BIOS) and reading them
+/// will return 0xFFs.
+///
+typedef enum {
+ GpioPadOwnHost = 0x0,
+ GpioPadOwnCsme = 0x1,
+ GpioPadOwnIsh = 0x2,
+} GPIO_PAD_OWN;
+
+/**
+ This procedure will get Gpio Pad Ownership
+
+ @param[in] GpioPad GPIO pad
+ @param[out] PadOwnVal Value of Pad Ownership
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid GpioPad
+**/
+EFI_STATUS
+GpioGetPadOwnership (
+ IN GPIO_PAD GpioPad,
+ OUT GPIO_PAD_OWN *PadOwnVal
+ );
+
+/**
+ This procedure will check state of Pad Config Lock for pads within one group
+
+ @param[in] Group GPIO group
+ @param[in] DwNum PadCfgLock register number for current group.
+ For group which has less then 32 pads per group DwNum must be 0.
+ @param[out] PadCfgLockRegVal Value of PadCfgLock register
+ Bit position - PadNumber
+ Bit value - 0: NotLocked, 1: Locked
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid group or DwNum parameter number
+**/
+EFI_STATUS
+GpioGetPadCfgLockForGroupDw (
+ IN GPIO_GROUP Group,
+ IN UINT32 DwNum,
+ OUT UINT32 *PadCfgLockRegVal
+ );
+
+/**
+ This procedure will check state of Pad Config Tx Lock for pads within one group
+
+ @param[in] Group GPIO group
+ @param[in] DwNum PadCfgLockTx register number for current group.
+ For group which has less then 32 pads per group DwNum must be 0.
+ @param[out] PadCfgLockTxRegVal Value of PadCfgLockTx register
+ Bit position - PadNumber
+ Bit value - 0: NotLockedTx, 1: LockedTx
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid group or DwNum parameter number
+**/
+EFI_STATUS
+GpioGetPadCfgLockTxForGroupDw (
+ IN GPIO_GROUP Group,
+ IN UINT32 DwNum,
+ OUT UINT32 *PadCfgLockTxRegVal
+ );
+
+/**
+ This procedure will clear PadCfgLock for selected pads within one group.
+ Unlocking a pad will cause an SMI (if enabled)
+
+ @param[in] Group GPIO group
+ @param[in] DwNum PadCfgLock register number for current group.
+ For group which has less then 32 pads per group DwNum must be 0.
+ @param[in] PadsToUnlock Bitmask for pads which are going to be unlocked,
+ Bit position - PadNumber
+ Bit value - 0: DoNotUnlock, 1: Unlock
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid group or pad number
+**/
+EFI_STATUS
+GpioUnlockPadCfgForGroupDw (
+ IN GPIO_GROUP Group,
+ IN UINT32 DwNum,
+ IN UINT32 PadsToUnlock
+ );
+
+/**
+ This procedure will set PadCfgLock for selected pads within one group
+
+ @param[in] Group GPIO group
+ @param[in] DwNum PadCfgLock register number for current group.
+ For group which has less then 32 pads per group DwNum must be 0.
+ @param[in] PadsToLock Bitmask for pads which are going to be locked,
+ Bit position - PadNumber
+ Bit value - 0: DoNotLock, 1: Lock
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid group or DwNum parameter number
+**/
+EFI_STATUS
+GpioLockPadCfgForGroupDw (
+ IN GPIO_GROUP Group,
+ IN UINT32 DwNum,
+ IN UINT32 PadsToLock
+ );
+
+/**
+ This procedure will clear PadCfgLockTx for selected pads within one group.
+ Unlocking a pad will cause an SMI (if enabled)
+
+ @param[in] Group GPIO group
+ @param[in] DwNum PadCfgLockTx register number for current group.
+ For group which has less then 32 pads per group DwNum must be 0.
+ @param[in] PadsToUnlockTx Bitmask for pads which are going to be unlocked,
+ Bit position - PadNumber
+ Bit value - 0: DoNotUnLockTx, 1: LockTx
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid group or pad number
+**/
+EFI_STATUS
+GpioUnlockPadCfgTxForGroupDw (
+ IN GPIO_GROUP Group,
+ IN UINT32 DwNum,
+ IN UINT32 PadsToUnlockTx
+ );
+
+#endif // _GPIO_LIB_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/GpioNativeLib.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/GpioNativeLib.h
new file mode 100644
index 0000000000..971f931442
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/GpioNativeLib.h
@@ -0,0 +1,135 @@
+/** @file
+ Header file for GpioLib for native and Si specific usage.
+ All function in this library is available for PEI, DXE, and SMM,
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _GPIO_NATIVE_LIB_H_
+#define _GPIO_NATIVE_LIB_H_
+
+#include <Library/GpioConfig.h>
+
+/**
+ This procedure will get number of pads for certain GPIO group
+
+ @param[in] Group GPIO group number
+
+ @retval Value Pad number for group
+ If illegal group number then return 0
+**/
+UINT32
+GpioGetPadPerGroup (
+ IN GPIO_GROUP Group
+ );
+
+/**
+ This procedure will get number of groups
+
+ @param[in] none
+
+ @retval Value Group number
+**/
+UINT32
+GpioGetNumberOfGroups (
+ VOID
+ );
+/**
+ This procedure will get lowest group
+
+ @param[in] none
+
+ @retval Value Lowest Group
+**/
+GPIO_GROUP
+GpioGetLowestGroup (
+ VOID
+ );
+
+/**
+ This procedure will get highest group
+
+ @param[in] none
+
+ @retval Value Highest Group
+**/
+GPIO_GROUP
+GpioGetHighestGroup (
+ VOID
+ );
+
+/**
+ This procedure will get group
+
+ @param[in] GpioPad Gpio Pad
+
+ @retval Value Group
+**/
+GPIO_GROUP
+GpioGetGroupFromGpioPad (
+ IN GPIO_PAD GpioPad
+ );
+
+/**
+ This procedure will get group index (0 based) from GpioPad
+
+ @param[in] GpioPad Gpio Pad
+
+ @retval Value Group Index
+**/
+UINT32
+GpioGetGroupIndexFromGpioPad (
+ IN GPIO_PAD GpioPad
+ );
+
+/**
+ This procedure will get group index (0 based) from group
+
+ @param[in] GpioGroup Gpio Group
+
+ @retval Value Group Index
+**/
+UINT32
+GpioGetGroupIndexFromGroup (
+ IN GPIO_GROUP GpioGroup
+ );
+
+/**
+ This procedure will get group from group index (0 based)
+
+ @param[in] GroupIndex Group Index
+
+ @retval GpioGroup Gpio Group
+**/
+GPIO_GROUP
+GpioGetGroupFromGroupIndex (
+ IN UINT32 GroupIndex
+ );
+
+/**
+ This procedure will get pad number (0 based) from Gpio Pad
+
+ @param[in] GpioPad Gpio Pad
+
+ @retval Value Pad Number
+**/
+UINT32
+GpioGetPadNumberFromGpioPad (
+ IN GPIO_PAD GpioPad
+ );
+
+/**
+ This procedure will return GpioPad from Group and PadNumber
+
+ @param[in] Group GPIO group
+ @param[in] PadNumber GPIO PadNumber
+
+ @retval GpioPad GpioPad
+**/
+GPIO_PAD
+GpioGetGpioPadFromGroupAndPadNumber (
+ IN GPIO_GROUP Group,
+ IN UINT32 PadNumber
+ );
+
+#endif // _GPIO_NATIVE_LIB_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/GraphicsInfoLib.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/GraphicsInfoLib.h
new file mode 100644
index 0000000000..bd9a7734b1
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/GraphicsInfoLib.h
@@ -0,0 +1,46 @@
+/** @file
+ Header file for Graphics Private Info Lib implementation.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _GRAPHICS_INFO_LIB_H_
+#define _GRAPHICS_INFO_LIB_H_
+
+#include <Library/BaseLib.h>
+#include <Library/PciSegmentLib.h>
+#include <IndustryStandard/Pci22.h>
+#include <Register/SaRegsHostBridge.h>
+
+/**
+ GetIgdBusNumber: Get IGD Bus Number
+
+ @retval PCI bus number for IGD
+**/
+UINT8
+GetIgdBusNumber (
+ VOID
+ );
+
+/**
+ GetIgdDevNumber: Get IGD Dev Number
+
+ @retval PCI dev number for IGD
+**/
+UINT8
+GetIgdDevNumber (
+ VOID
+ );
+
+/**
+ GetIgdFunNumber: Get IGD Fun Number
+
+ @retval PCI fun number for IGD
+**/
+UINT8
+GetIgdFuncNumber (
+ VOID
+ );
+
+#endif
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/MmPciLib.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/MmPciLib.h
new file mode 100644
index 0000000000..04249eefdf
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/MmPciLib.h
@@ -0,0 +1,27 @@
+/** @file
+ Get Pci Express address library implementation.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _MM_PCI_LIB_H_
+#define _MM_PCI_LIB_H_
+
+/**
+ This procedure will get PCIE address
+
+ @param[in] Bus Pci Bus Number
+ @param[in] Device Pci Device Number
+ @param[in] Function Pci Function Number
+
+ @retval PCIE address
+**/
+UINTN
+EFIAPI
+MmPciBase (
+ IN UINT32 Bus,
+ IN UINT32 Device,
+ IN UINT32 Function
+);
+
+#endif // _PEI_DXE_SMM_MM_PCI_LIB_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/PchPcieRpLib.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/PchPcieRpLib.h
new file mode 100644
index 0000000000..d9ca215d85
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/PchPcieRpLib.h
@@ -0,0 +1,41 @@
+/** @file
+ Header file for PchPcieRpLib.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _PCH_PCIERP_LIB_H_
+#define _PCH_PCIERP_LIB_H_
+
+#include <Uefi.h>
+#include <Library/PchPcrLib.h>
+
+/**
+ Get Pch Pcie Root Port Device and Function Number by Root Port physical Number
+
+ @param[in] RpNumber Root port physical number. (0-based)
+ @param[out] RpDev Return corresponding root port device number.
+ @param[out] RpFun Return corresponding root port function number.
+
+ @retval EFI_SUCCESS
+**/
+EFI_STATUS
+EFIAPI
+GetPchPcieRpDevFun (
+ IN UINTN RpNumber,
+ OUT UINTN *RpDev,
+ OUT UINTN *RpFun
+ );
+
+/**
+ Gets pci segment base address of PCIe root port.
+
+ @param RpIndex Root Port Index (0 based)
+ @return PCIe port base address.
+**/
+UINT64
+PchPcieBase (
+ IN UINT32 RpIndex
+ );
+
+#endif // _PCH_PCIERP_LIB_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/PchPcrLib.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/PchPcrLib.h
new file mode 100644
index 0000000000..19a1a98639
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/PchPcrLib.h
@@ -0,0 +1,221 @@
+/** @file
+ Header file for PchPcrLib.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _PCH_PCR_LIB_H_
+#define _PCH_PCR_LIB_H_
+
+#include <PchReservedResources.h>
+
+/**
+ Definition for PCR address
+ The PCR address is used to the PCR MMIO programming
+
+ SBREG_BAR_20BITADDRESS is configured by SoC
+
+ SBREG_BAR_20BITADDRESS=1, the format has included 16b addressing.
+ +---------------------------------------------------------------------------------------------+
+ | Addr[63:28] | Addr[27:24] | Addr[23:16] | Addr[15:2] | Addr[1:0] |
+ +----------------+-----------------------+-----------------+----------------------------------+
+ | REG_BAR[63:28] | TargetRegister[19:16] | TargetPort[7:0] | TargetRegister[15:2] |
+ +---------------------------------------------------------------------------------------------+
+
+ SBREG_BAR_20BITADDRESS=0
+ +---------------------------------------------------------------------------------------------+
+ | Addr[63:24] | Addr[27:24] | Addr[23:16] | Addr[15:2] | Addr[1:0] |
+ +----------------+-----------------------+-----------------+----------------------------------+
+ | REG_BAR[63:24] | REG_BAR[27:24] | TargetPort[7:0] | TargetRegister[15:2] |
+ +---------------------------------------------------------------------------------------------+
+**/
+#define PCH_PCR_ADDRESS(Pid, Offset) (PCH_PCR_BASE_ADDRESS | (UINT32) (((Offset) & 0x0F0000) << 8) | ((UINT8)(Pid) << 16) | (UINT16) ((Offset) & 0xFFFF))
+
+/**
+ PCH PCR boot script accessing macro
+ Those macros are only available for DXE phase.
+**/
+#define PCH_PCR_BOOT_SCRIPT_WRITE(Width, Pid, Offset, Count, Buffer) \
+ S3BootScriptSaveMemWrite (Width, PCH_PCR_ADDRESS (Pid, Offset), Count, Buffer); \
+
+#define PCH_PCR_BOOT_SCRIPT_READ_WRITE(Width, Pid, Offset, DataOr, DataAnd) \
+ S3BootScriptSaveMemReadWrite (Width, PCH_PCR_ADDRESS (Pid, Offset), DataOr, DataAnd); \
+
+#define PCH_PCR_BOOT_SCRIPT_READ(Width, Pid, Offset, BitMask, BitValue) \
+ S3BootScriptSaveMemPoll (Width, PCH_PCR_ADDRESS (Pid, Offset), BitMask, BitValue, 1, 1);
+
+typedef UINT8 PCH_SBI_PID;
+
+/**
+ Read PCR register.
+ It returns PCR register and size in 4bytes.
+ The Offset should not exceed 0xFFFF and must be aligned with size.
+
+ @param[in] Pid Port ID
+ @param[in] Offset Register offset of this Port ID
+
+ @retval UINT32 PCR register value.
+**/
+UINT32
+PchPcrRead32 (
+ IN PCH_SBI_PID Pid,
+ IN UINT32 Offset
+ );
+
+/**
+ Read PCR register.
+ It returns PCR register and size in 2bytes.
+ The Offset should not exceed 0xFFFF and must be aligned with size.
+
+ @param[in] Pid Port ID
+ @param[in] Offset Register offset of this Port ID
+
+ @retval UINT16 PCR register value.
+**/
+UINT16
+PchPcrRead16 (
+ IN PCH_SBI_PID Pid,
+ IN UINT32 Offset
+ );
+
+/**
+ Read PCR register.
+ It returns PCR register and size in 1bytes.
+ The Offset should not exceed 0xFFFF and must be aligned with size.
+
+ @param[in] Pid Port ID
+ @param[in] Offset Register offset of this Port ID
+
+ @retval UINT8 PCR register value
+**/
+UINT8
+PchPcrRead8 (
+ IN PCH_SBI_PID Pid,
+ IN UINT32 Offset
+ );
+
+/**
+ Write PCR register.
+ It programs PCR register and size in 4bytes.
+ The Offset should not exceed 0xFFFF and must be aligned with size.
+
+ @param[in] Pid Port ID
+ @param[in] Offset Register offset of Port ID.
+ @param[in] Data Input Data. Must be the same size as Size parameter.
+
+ @retval UINT32 Value written to register
+**/
+UINT32
+PchPcrWrite32 (
+ IN PCH_SBI_PID Pid,
+ IN UINT32 Offset,
+ IN UINT32 InData
+ );
+
+/**
+ Write PCR register.
+ It programs PCR register and size in 2bytes.
+ The Offset should not exceed 0xFFFF and must be aligned with size.
+
+ @param[in] Pid Port ID
+ @param[in] Offset Register offset of Port ID.
+ @param[in] Data Input Data. Must be the same size as Size parameter.
+
+ @retval UINT16 Value written to register
+**/
+UINT16
+PchPcrWrite16 (
+ IN PCH_SBI_PID Pid,
+ IN UINT32 Offset,
+ IN UINT16 InData
+ );
+
+/**
+ Write PCR register.
+ It programs PCR register and size in 1bytes.
+ The Offset should not exceed 0xFFFF and must be aligned with size.
+
+ @param[in] Pid Port ID
+ @param[in] Offset Register offset of Port ID.
+ @param[in] Data Input Data. Must be the same size as Size parameter.
+
+ @retval UINT8 Value written to register
+**/
+UINT8
+PchPcrWrite8 (
+ IN PCH_SBI_PID Pid,
+ IN UINT32 Offset,
+ IN UINT8 InData
+ );
+
+/**
+ Write PCR register.
+ It programs PCR register and size in 4bytes.
+ The Offset should not exceed 0xFFFF and must be aligned with size.
+
+ @param[in] Pid Port ID
+ @param[in] Offset Register offset of Port ID.
+ @param[in] AndData AND Data. Must be the same size as Size parameter.
+ @param[in] OrData OR Data. Must be the same size as Size parameter.
+
+ @retval UINT32 Value written to register
+
+**/
+UINT32
+PchPcrAndThenOr32 (
+ IN PCH_SBI_PID Pid,
+ IN UINT32 Offset,
+ IN UINT32 AndData,
+ IN UINT32 OrData
+ );
+
+/**
+ Write PCR register.
+ It programs PCR register and size in 2bytes.
+ The Offset should not exceed 0xFFFF and must be aligned with size.
+
+ @param[in] Pid Port ID
+ @param[in] Offset Register offset of Port ID.
+ @param[in] AndData AND Data. Must be the same size as Size parameter.
+ @param[in] OrData OR Data. Must be the same size as Size parameter.
+
+ @retval UINT16 Value written to register
+
+**/
+UINT16
+PchPcrAndThenOr16 (
+ IN PCH_SBI_PID Pid,
+ IN UINT32 Offset,
+ IN UINT16 AndData,
+ IN UINT16 OrData
+ );
+
+/**
+ Write PCR register.
+ It programs PCR register and size in 1bytes.
+ The Offset should not exceed 0xFFFF and must be aligned with size.
+
+ @param[in] Pid Port ID
+ @param[in] Offset Register offset of Port ID.
+ @param[in] AndData AND Data. Must be the same size as Size parameter.
+ @param[in] OrData OR Data. Must be the same size as Size parameter.
+
+ @retval UINT8 Value written to register
+
+**/
+UINT8
+PchPcrAndThenOr8 (
+ IN PCH_SBI_PID Pid,
+ IN UINT32 Offset,
+ IN UINT8 AndData,
+ IN UINT8 OrData
+ );
+
+
+typedef enum {
+ PchIpDmi = 1,
+ PchIpIclk,
+} PCH_IP_PID_ENUM;
+
+
+#endif // _PCH_PCR_LIB_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/PeiDxeSmmReserveMmio64SizeLib.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/PeiDxeSmmReserveMmio64SizeLib.h
new file mode 100644
index 0000000000..d27f858892
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/PeiDxeSmmReserveMmio64SizeLib.h
@@ -0,0 +1,21 @@
+/** @file
+ PEI/DXE/SMM library for reserved 64-bit MMIO space.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PEI_DXE_SMM_RESERVE_MMIO_64_SIZE_LIB_H_
+#define _PEI_DXE_SMM_RESERVE_MMIO_64_SIZE_LIB_H_
+
+/**
+ The function return the 64 bit MMIO size to reserve.
+
+ @retval The 64-bit MMIO size
+**/
+UINT64
+ReserveMmio64Size (
+ VOID
+ );
+
+#endif // _PEI_DXE_SMM_RESERVE_MMIO_64_SIZE_LIB_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/PeiSiPolicyUpdateLib.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/PeiSiPolicyUpdateLib.h
new file mode 100644
index 0000000000..79e7752e4a
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/PeiSiPolicyUpdateLib.h
@@ -0,0 +1,154 @@
+/** @file
+ Header file for PEI SiPolicyUpdate Library.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PEI_SI_POLICY_UPDATE_LIB_H_
+#define _PEI_SI_POLICY_UPDATE_LIB_H_
+
+#include <Ppi/SiPolicy.h>
+
+/**
+ This function performs CPU PEI Policy initialization in Post-memory.
+
+ @retval EFI_SUCCESS The PPI is installed and initialized.
+ @retval EFI ERRORS The PPI is not successfully installed.
+ @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize the driver
+**/
+EFI_STATUS
+EFIAPI
+UpdatePeiCpuPolicy (
+ VOID
+ );
+
+/**
+ This function performs CPU PEI Policy initialization in PreMem.
+
+ @retval EFI_SUCCESS The PPI is installed and initialized.
+ @retval EFI ERRORS The PPI is not successfully installed.
+ @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize the driver
+**/
+EFI_STATUS
+EFIAPI
+UpdatePeiCpuPolicyPreMem (
+ VOID
+ );
+
+
+/**
+ This function performs SA PEI Policy initialization.
+
+ @retval EFI_SUCCESS The PPI is installed and initialized.
+**/
+EFI_STATUS
+EFIAPI
+UpdatePeiSaPolicy (
+ VOID
+ );
+
+/**
+ This function performs SA PEI Policy initialization for PreMem.
+
+ @retval EFI_SUCCESS Update complete.
+**/
+EFI_STATUS
+EFIAPI
+UpdatePeiSaPolicyPreMem (
+ VOID
+ );
+
+/**
+ This function performs PCH PEI Policy initialization.
+
+ @retval EFI_SUCCESS The PPI is installed and initialized.
+ @retval EFI ERRORS The PPI is not successfully installed.
+ @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize the driver
+**/
+EFI_STATUS
+EFIAPI
+UpdatePeiPchPolicy (
+ VOID
+ );
+
+/**
+ This function performs PCH PEI Policy initialization.
+
+ @retval EFI_SUCCESS The PPI is installed and initialized.
+ @retval EFI ERRORS The PPI is not successfully installed.
+ @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize the driver
+**/
+EFI_STATUS
+EFIAPI
+UpdatePeiPchPolicyPreMem (
+ VOID
+ );
+
+/**
+ Update the ME Policy Library
+
+ @retval EFI_SUCCESS Update complete.
+ @retval Others Update unsuccessful.
+**/
+EFI_STATUS
+EFIAPI
+UpdatePeiMePolicy (
+ VOID
+ );
+
+/**
+ Update the ME Policy Library
+
+ @retval EFI_SUCCESS Update complete.
+**/
+EFI_STATUS
+EFIAPI
+UpdatePeiMePolicyPreMem (
+ VOID
+ );
+
+
+
+/**
+ Update the TBT Policy Library
+
+ @retval EFI_SUCCESS Update complete.
+**/
+EFI_STATUS
+EFIAPI
+UpdatePeiTbtPolicy (
+ VOID
+ );
+
+/**
+ Update the ME Server Policy Ppi (pre mem)
+
+ @param[in, out] SiPreMemPolicyPpi PEI Pre Mem Si Policy
+
+ @retval EFI_SUCCESS Initialization complete.
+ @retval EFI_UNSUPPORTED The chipset is unsupported by this driver.
+ @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize the driver.
+ @retval EFI_DEVICE_ERROR Device error, driver exits abnormally.
+ @retval EFI_INVALID_PARAMETER Wrong pointer passed to the function
+**/
+EFI_STATUS
+UpdatePeiMeServerPreMemPolicy (
+ IN OUT SI_PREMEM_POLICY_PPI *SiPreMemPolicy
+ );
+
+/**
+ Update the ME Server Policy Ppi (post mem)
+
+ @param[in, out] SiPolicyPpi PEI Si Policy
+
+ @retval EFI_SUCCESS Initialization complete.
+ @retval EFI_UNSUPPORTED The chipset is unsupported by this driver.
+ @retval EFI_DEVICE_ERROR Device error, driver exits abnormally.
+ @retval EFI_INVALID_PARAMETER Wrong pointer passed to the function
+**/
+ EFI_STATUS
+UpdatePeiMeServerPolicy (
+ IN OUT SI_POLICY_PPI *SiPolicyPpi
+ );
+#endif
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/PmcLib.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/PmcLib.h
new file mode 100644
index 0000000000..7d49a14164
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/PmcLib.h
@@ -0,0 +1,40 @@
+/** @file
+ Header file for PmcLib.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _PMC_LIB_H_
+#define _PMC_LIB_H_
+
+#include <PmConfig.h>
+
+
+typedef struct {
+ UINT32 Buf0;
+ UINT32 Buf1;
+ UINT32 Buf2;
+ UINT32 Buf3;
+} PMC_IPC_COMMAND_BUFFER;
+
+/**
+ Get PCH ACPI base address.
+
+ @retval Address Address of PWRM base address.
+**/
+UINT16
+PmcGetAcpiBase (
+ VOID
+ );
+
+/**
+ Get PCH PWRM base address.
+
+ @retval Address Address of PWRM base address.
+**/
+UINT32
+PmcGetPwrmBase (
+ VOID
+ );
+
+#endif // _PMC_LIB_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/ResetSystemLib.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/ResetSystemLib.h
new file mode 100644
index 0000000000..6146e8610d
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/ResetSystemLib.h
@@ -0,0 +1,68 @@
+/** @file
+ System reset Library Services. This library class defines a set of
+ methods that reset the whole system.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef __RESET_SYSTEM_LIB_H__
+#define __RESET_SYSTEM_LIB_H__
+
+/**
+ This function causes a system-wide reset (cold reset), in which
+ all circuitry within the system returns to its initial state. This type of reset
+ is asynchronous to system operation and operates without regard to
+ cycle boundaries.
+
+ If this function returns, it means that the system does not support cold reset.
+**/
+VOID
+EFIAPI
+ResetCold (
+ VOID
+ );
+
+/**
+ This function causes a system-wide initialization (warm reset), in which all processors
+ are set to their initial state. Pending cycles are not corrupted.
+
+ If this function returns, it means that the system does not support warm reset.
+**/
+VOID
+EFIAPI
+ResetWarm (
+ VOID
+ );
+
+/**
+ This function causes the system to enter a power state equivalent
+ to the ACPI G2/S5 or G3 states.
+
+ If this function returns, it means that the system does not support shutdown reset.
+**/
+VOID
+EFIAPI
+ResetShutdown (
+ VOID
+ );
+
+/**
+ This function causes a systemwide reset. The exact type of the reset is
+ defined by the EFI_GUID that follows the Null-terminated Unicode string passed
+ into ResetData. If the platform does not recognize the EFI_GUID in ResetData
+ the platform must pick a supported reset type to perform.The platform may
+ optionally log the parameters from any non-normal reset that occurs.
+
+ @param[in] DataSize The size, in bytes, of ResetData.
+ @param[in] ResetData The data buffer starts with a Null-terminated string,
+ followed by the EFI_GUID.
+**/
+VOID
+EFIAPI
+ResetPlatformSpecific (
+ IN UINTN DataSize,
+ IN VOID *ResetData
+ );
+
+#endif
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/SecPlatformLib.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/SecPlatformLib.h
new file mode 100644
index 0000000000..7fa23b1a51
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/SecPlatformLib.h
@@ -0,0 +1,81 @@
+/** @file
+ Prototype of SEC Platform hook library.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _SEC_PLATFORM_LIB_H_
+#define _SEC_PLATFORM_LIB_H_
+
+#include <Ppi/SecPlatformInformation.h>
+#include <Ppi/SecPerformance.h>
+
+/**
+ A developer supplied function to perform platform specific operations.
+
+ It's a developer supplied function to perform any operations appropriate to a
+ given platform. It's invoked just before passing control to PEI core by SEC
+ core. Platform developer may modify the SecCoreData passed to PEI Core.
+ It returns a platform specific PPI list that platform wishes to pass to PEI core.
+ The Generic SEC core module will merge this list to join the final list passed to
+ PEI core.
+
+ @param SecCoreData The same parameter as passing to PEI core. It
+ could be overridden by this function.
+
+ @return The platform specific PPI list to be passed to PEI core or
+ NULL if there is no need of such platform specific PPI list.
+
+**/
+EFI_PEI_PPI_DESCRIPTOR *
+EFIAPI
+SecPlatformMain (
+ IN OUT EFI_SEC_PEI_HAND_OFF *SecCoreData
+ );
+
+
+/**
+ This interface conveys state information out of the Security (SEC) phase into PEI.
+
+ @param PeiServices Pointer to the PEI Services Table.
+ @param StructureSize Pointer to the variable describing size of the input buffer.
+ @param PlatformInformationRecord Pointer to the EFI_SEC_PLATFORM_INFORMATION_RECORD.
+
+ @retval EFI_SUCCESS The data was successfully returned.
+ @retval EFI_BUFFER_TOO_SMALL The buffer was too small.
+
+**/
+EFI_STATUS
+EFIAPI
+SecPlatformInformation (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN OUT UINT64 *StructureSize,
+ OUT EFI_SEC_PLATFORM_INFORMATION_RECORD *PlatformInformationRecord
+ );
+
+/**
+ This interface conveys performance information out of the Security (SEC) phase into PEI.
+
+ This service is published by the SEC phase. The SEC phase handoff has an optional
+ EFI_PEI_PPI_DESCRIPTOR list as its final argument when control is passed from SEC into the
+ PEI Foundation. As such, if the platform supports collecting performance data in SEC,
+ this information is encapsulated into the data structure abstracted by this service.
+ This information is collected for the boot-strap processor (BSP) on IA-32.
+
+ @param[in] PeiServices The pointer to the PEI Services Table.
+ @param[in] This The pointer to this instance of the PEI_SEC_PERFORMANCE_PPI.
+ @param[out] Performance The pointer to performance data collected in SEC phase.
+
+ @retval EFI_SUCCESS The data was successfully returned.
+**/
+EFI_STATUS
+EFIAPI
+SecGetPerformance (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN PEI_SEC_PERFORMANCE_PPI *This,
+ OUT FIRMWARE_SEC_PERFORMANCE *Performance
+ );
+
+#endif
+
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/SiConfigBlockLib.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/SiConfigBlockLib.h
new file mode 100644
index 0000000000..7bb111a932
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/SiConfigBlockLib.h
@@ -0,0 +1,56 @@
+/** @file
+ Prototype of the SiConfigBlockLib library.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _SI_CONFIG_BLOCK_LIB_H_
+#define _SI_CONFIG_BLOCK_LIB_H_
+
+
+typedef
+VOID
+(*LOAD_DEFAULT_FUNCTION) (
+ IN VOID *ConfigBlockPointer
+ );
+
+typedef struct {
+ EFI_GUID *Guid;
+ UINT16 Size;
+ UINT8 Revision;
+ LOAD_DEFAULT_FUNCTION LoadDefault;
+} COMPONENT_BLOCK_ENTRY;
+
+/**
+ GetComponentConfigBlockTotalSize get config block table total size.
+
+ @param[in] ComponentBlocks Component blocks array
+ @param[in] TotalBlockCount Number of blocks
+
+ @retval Size of config block table
+**/
+UINT16
+EFIAPI
+GetComponentConfigBlockTotalSize (
+ IN COMPONENT_BLOCK_ENTRY *ComponentBlocks,
+ IN UINT16 TotalBlockCount
+ );
+
+/**
+ AddComponentConfigBlocks add all config blocks.
+
+ @param[in] ConfigBlockTableAddress The pointer to add config blocks
+ @param[in] ComponentBlocks Config blocks array
+ @param[in] TotalBlockCount Number of blocks
+
+ @retval EFI_SUCCESS The policy default is initialized.
+ @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer
+**/
+EFI_STATUS
+EFIAPI
+AddComponentConfigBlocks (
+ IN VOID *ConfigBlockTableAddress,
+ IN COMPONENT_BLOCK_ENTRY *ComponentBlocks,
+ IN UINT16 TotalBlockCount
+ );
+#endif // _SI_CONFIG_BLOCK_LIB_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/SiPolicyLib.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/SiPolicyLib.h
new file mode 100644
index 0000000000..f821ea2fdf
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/SiPolicyLib.h
@@ -0,0 +1,39 @@
+/** @file
+ Prototype of the SiPolicyLib library.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _SI_POLICY_LIB_H_
+#define _SI_POLICY_LIB_H_
+
+#include <Ppi/SiPolicy.h>
+
+/**
+ SiPreMemInstallPolicyReadyPpi installs SiPreMemPolicyReadyPpi.
+ While installed, RC assumes the Policy is ready and finalized. So please update and override
+ any setting before calling this function.
+
+ @retval EFI_SUCCESS The policy is installed.
+ @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer
+**/
+EFI_STATUS
+EFIAPI
+SiPreMemInstallPolicyReadyPpi (
+ VOID
+ );
+
+/**
+ SiInstallPolicyReadyPpi installs SiPolicyReadyPpi.
+ While installed, RC assumes the Policy is ready and finalized. So please update and override
+ any setting before calling this function.
+
+ @retval EFI_SUCCESS The policy is installed.
+ @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer
+**/
+EFI_STATUS
+EFIAPI
+SiInstallPolicyReadyPpi (
+ VOID
+ );
+#endif // _SI_POLICY_LIB_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/SpiLib.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/SpiLib.h
new file mode 100644
index 0000000000..ca56e74e0f
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/SpiLib.h
@@ -0,0 +1,21 @@
+/** @file
+ Header file for Spi Library.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _SPI_LIB_H_
+#define _SPI_LIB_H_
+
+/**
+ This function Initial SPI services
+
+ @retval EFI_STATUS Results of the installation of the SPI services
+**/
+EFI_STATUS
+EFIAPI
+SpiServiceInit (
+ VOID
+ );
+
+#endif
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Pins/GpioPinsVer2Lp.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Pins/GpioPinsVer2Lp.h
new file mode 100644
index 0000000000..2f58de78f6
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Pins/GpioPinsVer2Lp.h
@@ -0,0 +1,36 @@
+/** @file
+ GPIO pins for TGL-PCH-LP,
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _GPIO_PINS_VER2_LP_H_
+#define _GPIO_PINS_VER2_LP_H_
+///
+/// This header file should be used together with
+/// PCH GPIO lib in C and ASL. All defines used
+/// must match both ASL/C syntax
+///
+
+///
+/// Unique ID used in GpioPad defines
+///
+#define GPIO_VER2_LP_CHIPSET_ID 0x9
+
+///
+/// TGL LP GPIO pins
+/// Use below for functions from PCH GPIO Lib which
+/// require GpioPad as argument. Encoding used here
+/// has all information required by library functions
+///
+#define GPIO_VER2_LP_GPP_H0 0x09070000
+#define GPIO_VER2_LP_GPP_H1 0x09070001
+#define GPIO_VER2_LP_GPP_D16 0x09080010
+#define GPIO_VER2_LP_GPP_C2 0x090B0002
+
+#define GPIO_VER2_LP_GPP_F9 0x090C0009
+#define GPIO_VER2_LP_GPP_F10 0x090C000A
+#define GPIO_VER2_LP_GPP_F20 0x090C0014
+
+#define GPIO_VER2_LP_GPP_E7 0x090E0007
+#endif // _GPIO_PINS_VER2_LP_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Ppi/FspmArchConfigPpi.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Ppi/FspmArchConfigPpi.h
new file mode 100644
index 0000000000..7ed834b9f5
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Ppi/FspmArchConfigPpi.h
@@ -0,0 +1,32 @@
+/** @file
+ Header file for FSP-M Arch Config PPI
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _FSPM_ARCH_CONFIG_PPI_H_
+#define _FSPM_ARCH_CONFIG_PPI_H_
+
+///
+/// Global ID for the FSPM_ARCH_CONFIG_PPI.
+///
+#define FSPM_ARCH_CONFIG_GUID \
+ { \
+ 0x824d5a3a, 0xaf92, 0x4c0c, { 0x9f, 0x19, 0x19, 0x52, 0x6d, 0xca, 0x4a, 0xbb } \
+ }
+
+///
+/// This PPI provides FSP-M Arch Config PPI.
+///
+typedef struct {
+ UINT8 Revision;
+ UINT8 Reserved[3];
+ VOID *NvsBufferPtr;
+ UINT32 BootLoaderTolumSize;
+ UINT8 Reserved1[4];
+} FSPM_ARCH_CONFIG_PPI;
+
+extern EFI_GUID gFspmArchConfigPpiGuid;
+
+#endif // _FSPM_ARCH_CONFIG_PPI_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Ppi/PeiPreMemSiDefaultPolicy.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Ppi/PeiPreMemSiDefaultPolicy.h
new file mode 100644
index 0000000000..0713dbd55b
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Ppi/PeiPreMemSiDefaultPolicy.h
@@ -0,0 +1,33 @@
+/** @file
+ This file defines the function to initialize default silicon policy PPI.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI_H_
+#define _PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI_H_
+
+//
+// Forward declaration for the PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI.
+//
+typedef struct _PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI;
+
+/**
+ Initialize and install default silicon policy PPI
+**/
+typedef
+EFI_STATUS
+(EFIAPI *PEI_PREMEM_POLICY_INIT) (
+ VOID
+ );
+
+///
+/// This PPI provides function to install default silicon policy
+///
+struct _PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI {
+ PEI_PREMEM_POLICY_INIT PeiPreMemPolicyInit; ///< PeiPreMemPolicyInit()
+};
+
+extern EFI_GUID gSiPreMemDefaultPolicyInitPpiGuid;
+
+#endif // _PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Ppi/PeiSiDefaultPolicy.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Ppi/PeiSiDefaultPolicy.h
new file mode 100644
index 0000000000..83bdbe0f6e
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Ppi/PeiSiDefaultPolicy.h
@@ -0,0 +1,33 @@
+/** @file
+ This file defines the function to initialize default silicon policy PPI.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _PEI_SI_DEFAULT_POLICY_INIT_PPI_H_
+#define _PEI_SI_DEFAULT_POLICY_INIT_PPI_H_
+
+//
+// Forward declaration for the PEI_SI_DEFAULT_POLICY_INIT_PPI.
+//
+typedef struct _PEI_SI_DEFAULT_POLICY_INIT_PPI PEI_SI_DEFAULT_POLICY_INIT_PPI;
+
+/**
+ Initialize and install default silicon policy PPI
+**/
+typedef
+EFI_STATUS
+(EFIAPI *PEI_POLICY_INIT) (
+ VOID
+ );
+
+///
+/// This PPI provides function to install default silicon policy
+///
+struct _PEI_SI_DEFAULT_POLICY_INIT_PPI {
+ PEI_POLICY_INIT PeiPolicyInit; ///< PeiPolicyInit()
+};
+
+extern EFI_GUID gSiDefaultPolicyInitPpiGuid;
+
+#endif // _PEI_SI_DEFAULT_POLICY_INIT_PPI_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Ppi/Spi.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Ppi/Spi.h
new file mode 100644
index 0000000000..0faf1e3443
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Ppi/Spi.h
@@ -0,0 +1,29 @@
+/** @file
+ This file defines the PCH SPI PPI which implements the
+ Intel(R) PCH SPI Host Controller Compatibility Interface.
+
+ @note The APIs in this file are designed to be backward compatible with
+ previous versions. Any change in behavior of these APIs will result in
+ newer version of the API.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _PCH_SPI_PPI_H_
+#define _PCH_SPI_PPI_H_
+
+#include <Protocol/Spi.h>
+
+//
+// Extern the GUID for PPI users.
+//
+extern EFI_GUID gPchSpiPpiGuid;
+
+/**
+ Reuse the PCH_SPI_PROTOCOL definitions
+ This is possible becaues the PPI implementation does not rely on a PeiService pointer,
+ as it uses EDKII Glue Lib to do IO accesses
+**/
+typedef PCH_SPI_PROTOCOL PCH_SPI_PPI;
+
+#endif
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Ppi/Wdt.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Ppi/Wdt.h
new file mode 100644
index 0000000000..bd8163fea0
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Ppi/Wdt.h
@@ -0,0 +1,22 @@
+/** @file
+ Watchdog Timer PPI
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _PEI_WDT_H_
+#define _PEI_WDT_H_
+
+#include <Protocol/Wdt.h>
+
+//
+// Extern the GUID for PPI users.
+//
+extern EFI_GUID gWdtPpiGuid;
+
+///
+/// Reuse WDT_PROTOCOL definition
+///
+typedef WDT_PROTOCOL WDT_PPI;
+
+#endif
--
2.36.1.windows.1
-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#108682): https://edk2.groups.io/g/devel/message/108682
Mute This Topic: https://groups.io/mt/101373950/7686176
Group Owner: devel+owner@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [rebecca@openfw.io]
-=-=-=-=-=-=-=-=-=-=-=-
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [edk2-devel] [PATCH v2 07/10] AlderlakeSiliconPkg/Include: Add Protocol, Register, Other Includes
2023-09-15 4:45 [edk2-devel] [PATCH v2 01/10] AlderlakeSiliconPkg/IpBlock: Add CpuPcieRp, Espi, Gpio components Saloni Kasbekar
` (4 preceding siblings ...)
2023-09-15 4:45 ` [edk2-devel] [PATCH v2 06/10] AlderlakeSiliconPkg/Include: Add Library, Pins, Ppi Includes Saloni Kasbekar
@ 2023-09-15 4:45 ` Saloni Kasbekar
2023-09-15 5:43 ` Chaganty, Rangasai V
2023-09-15 23:56 ` Nate DeSimone
2023-09-15 4:45 ` [edk2-devel] [PATCH v2 08/10] AlderlakeSiliconPkg/Fru: Add AdlCpu Fru Saloni Kasbekar
` (5 subsequent siblings)
11 siblings, 2 replies; 41+ messages in thread
From: Saloni Kasbekar @ 2023-09-15 4:45 UTC (permalink / raw)
To: devel; +Cc: Saloni Kasbekar, Sai Chaganty, Nate DeSimone, Rosen Chuang
Adds the following Includes:
- Include/
- Include/Protocol
- Include/Register
Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Rosen Chuang <rosen.chuang@intel.com>
Signed-off-by: Saloni Kasbekar <saloni.kasbekar@intel.com>
---
.../AlderlakeSiliconPkg/Include/ConfigBlock.h | 53 +++
.../AlderlakeSiliconPkg/Include/CpuPcieHob.h | 48 +++
.../Include/Protocol/IgdOpRegion.h | 22 ++
.../Include/Protocol/Spi.h | 346 ++++++++++++++++++
.../Include/Protocol/Wdt.h | 111 ++++++
.../Include/Register/FlashRegs.h | 73 ++++
.../Include/Register/GpioRegs.h | 103 ++++++
.../Include/Register/GpioRegsVer2.h | 211 +++++++++++
.../Include/Register/PchDmi14Regs.h | 49 +++
.../Include/Register/PchDmiRegs.h | 51 +++
.../Include/Register/PchPcieRpRegs.h | 45 +++
.../Include/Register/PchRegsLpc.h | 77 ++++
.../Include/Register/PmcRegs.h | 134 +++++++
.../Include/Register/RtcRegs.h | 44 +++
.../Include/Register/TcoRegs.h | 71 ++++
.../Include/SerialIoDevices.h | 226 ++++++++++++
.../AlderlakeSiliconPkg/Include/SiConfigHob.h | 17 +
.../Include/SiPolicyStruct.h | 64 ++++
18 files changed, 1745 insertions(+)
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/CpuPcieHob.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Protocol/IgdOpRegion.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Protocol/Spi.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Protocol/Wdt.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Register/FlashRegs.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Register/GpioRegs.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Register/GpioRegsVer2.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Register/PchDmi14Regs.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Register/PchDmiRegs.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Register/PchPcieRpRegs.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Register/PchRegsLpc.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Register/PmcRegs.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Register/RtcRegs.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Register/TcoRegs.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/SerialIoDevices.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/SiConfigHob.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/SiPolicyStruct.h
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock.h
new file mode 100644
index 0000000000..2e609bc8d9
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock.h
@@ -0,0 +1,53 @@
+/** @file
+ Header file for Config Block Lib implementation
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _CONFIG_BLOCK_H_
+#define _CONFIG_BLOCK_H_
+
+#include <Uefi/UefiBaseType.h>
+#include <Uefi/UefiMultiPhase.h>
+#include <Pi/PiBootMode.h>
+#include <Pi/PiHob.h>
+
+#pragma pack (push,1)
+
+///
+/// Config Block Header
+///
+typedef struct _CONFIG_BLOCK_HEADER {
+ EFI_HOB_GUID_TYPE GuidHob; ///< Offset 0-23 GUID extension HOB header
+ UINT8 Revision; ///< Offset 24 Revision of this config block
+ UINT8 Attributes; ///< Offset 25 The main revision for config block
+ UINT8 Reserved[2]; ///< Offset 26-27 Reserved for future use
+} CONFIG_BLOCK_HEADER;
+
+///
+/// Config Block
+///
+typedef struct _CONFIG_BLOCK {
+ CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Header of config block
+ //
+ // Config Block Data
+ //
+} CONFIG_BLOCK;
+
+///
+/// Config Block Table Header
+///
+typedef struct _CONFIG_BLOCK_TABLE_STRUCT {
+ CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 GUID number for main entry of config block
+ UINT8 Rsvd0[2]; ///< Offset 28-29 Reserved for future use
+ UINT16 NumberOfBlocks; ///< Offset 30-31 Number of config blocks (N)
+ UINT32 AvailableSize; ///< Offset 32-35 Current config block table size
+///
+/// Individual Config Block Structures are added here in memory as part of AddConfigBlock()
+///
+} CONFIG_BLOCK_TABLE_HEADER;
+#pragma pack (pop)
+
+#endif // _CONFIG_BLOCK_H_
+
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/CpuPcieHob.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/CpuPcieHob.h
new file mode 100644
index 0000000000..dccd6e7d7a
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/CpuPcieHob.h
@@ -0,0 +1,48 @@
+/** @file
+ The GUID definition for CpuPcieHob
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _CPU_PCIE_HOB_H_
+#define _CPU_PCIE_HOB_H_
+
+#include <Base.h>
+#include <CpuPcieInfo.h>
+#include <CpuPcieConfig.h>
+
+extern EFI_GUID gCpuPcieHobGuid;
+#pragma pack (push,1)
+
+
+/**
+ The CPU_PCIE_HOB block describes the expected configuration of the CpuPcie controllers
+**/
+typedef struct {
+ ///
+ /// These members describe the configuration of each CPU PCIe root port.
+ ///
+ EFI_HOB_GUID_TYPE EfiHobGuidType; ///< Offset 0 - 23: GUID Hob type structure for gCpuPcieHobGuid
+ CPU_PCIE_ROOT_PORT_CONFIG RootPort[CPU_PCIE_MAX_ROOT_PORTS];
+ UINT8 L1SubStates[CPU_PCIE_MAX_ROOT_PORTS]; ///< The L1 Substates configuration of the root port
+
+ UINT32 DekelFwVersionMinor; ///< Dekel Firmware Minor Version
+ UINT32 DekelFwVersionMajor; ///< Dekel Firmware Major Version
+ BOOLEAN InitPcieAspmAfterOprom; ///< 1=initialize PCIe ASPM after Oprom; 0=before (This will be set basing on policy)
+ UINT32 RpEnabledMask; ///< Rootport enabled mask based on DEVEN register
+ UINT32 RpEnMaskFromDevEn; ///< Rootport enabled mask based on Device Id
+ UINT8 DisableClkReqMsg[CPU_PCIE_MAX_ROOT_PORTS]; ///< 1=ClkReqMsg disabled, 0=ClkReqMsg enabled
+ UINT8 SlotSelection; ///< 1=M2 slot, 0=CEMx4 slot
+ BOOLEAN ComplianceTest; ///< Compliance Test based on policy
+ UINT32 HsPhyRecipeVersionMajor; ///< HS-Phy Recipe Major Version
+ UINT32 HsPhyRecipeVersionMinor; ///< HS-Phy Recipe Minor Version
+ UINT32 HsPhyFwProdMajor; ///< HS-Phy Firmware Product Major Verison
+ UINT32 HsPhyFwProdMinor; ///< HS-Phy Firmware Product Minor Verison
+ UINT32 HsPhyFwHotFix; ///< HS-Phy Firmware Hot Fix Version
+ UINT32 HsPhyFwBuild; ///< HS-Phy Firmware Build version
+ UINT32 HsPhyFwEvBitProgMajor; ///< HS-Phy Firmware EV Bit Prog Major
+ UINT32 HsPhyFwEvBitProgMinor; ///< HS-Phy Firmware EV Bit Prog Minor
+ UINT32 HsPhyMap; ///< HS-Phy Mapping Based on HS-Py supported ports
+} CPU_PCIE_HOB;
+#pragma pack (pop)
+#endif
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Protocol/IgdOpRegion.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Protocol/IgdOpRegion.h
new file mode 100644
index 0000000000..9f69671f35
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Protocol/IgdOpRegion.h
@@ -0,0 +1,22 @@
+/** @file
+ This file is part of the IGD OpRegion Implementation. The IGD OpRegion is
+ an interface between system BIOS, ASL code, and Graphics drivers.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _IGD_OPREGION_PROTOCOL_H_
+#define _IGD_OPREGION_PROTOCOL_H_
+
+#include <IndustryStandard/IgdOpRegion.h>
+
+extern EFI_GUID gIgdOpRegionProtocolGuid;
+
+///
+/// IGD OpRegion Protocol
+///
+typedef struct {
+ IGD_OPREGION_STRUCTURE *OpRegion; ///< IGD Operation Region Structure
+} IGD_OPREGION_PROTOCOL;
+
+#endif
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Protocol/Spi.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Protocol/Spi.h
new file mode 100644
index 0000000000..cbf2883fa4
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Protocol/Spi.h
@@ -0,0 +1,346 @@
+/** @file
+ This file defines the PCH SPI Protocol which implements the
+ Intel(R) PCH SPI Host Controller Compatibility Interface.
+
+ @note The APIs in this file are designed to be backward compatible with
+ previous versions. Any change in behavior of these APIs will result in
+ newer version of the API.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _PCH_SPI_PROTOCOL_H_
+#define _PCH_SPI_PROTOCOL_H_
+
+//
+// Extern the GUID for protocol users.
+//
+extern EFI_GUID gPchSpiProtocolGuid;
+extern EFI_GUID gPchSmmSpiProtocolGuid;
+
+//
+// Forward reference for ANSI C compatibility
+//
+typedef struct _PCH_SPI_PROTOCOL PCH_SPI_PROTOCOL;
+
+//
+// SPI protocol data structures and definitions
+//
+
+/**
+ Flash Region Type
+**/
+typedef enum {
+ FlashRegionDescriptor,
+ FlashRegionBios,
+ FlashRegionMe,
+ FlashRegionGbE,
+ FlashRegionPlatformData,
+ FlashRegionDer,
+ FlashRegionSecondaryBios,
+ FlashRegionuCodePatch,
+ FlashRegionEC,
+ FlashRegionDeviceExpansion2,
+ FlashRegionIE,
+ FlashRegion10Gbe_A,
+ FlashRegion10Gbe_B,
+ FlashRegion13,
+ FlashRegion14,
+ FlashRegion15,
+ FlashRegionAll,
+ FlashRegionMax
+} FLASH_REGION_TYPE;
+
+//
+// Protocol member functions
+//
+
+/**
+ Read data from the flash part.
+
+ @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
+ @param[in] FlashRegionType The Flash Region type for flash cycle which
+ is listed in the Descriptor.
+ @param[in] Address The Flash Linear Address must fall within a
+ region for which BIOS has access permissions.
+ @param[in] ByteCount Number of bytes in the data portion of the
+ SPI cycle.
+ @param[out] Buffer The Pointer to caller-allocated buffer
+ containing the dada received.
+ It is the caller's responsibility to make
+ sure Buffer is large enough for the total
+ number of bytes read.
+
+ @retval EFI_SUCCESS Command succeed.
+ @retval EFI_INVALID_PARAMETER The parameters specified are not valid.
+ @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *PCH_SPI_FLASH_READ) (
+ IN PCH_SPI_PROTOCOL *This,
+ IN FLASH_REGION_TYPE FlashRegionType,
+ IN UINT32 Address,
+ IN UINT32 ByteCount,
+ OUT UINT8 *Buffer
+ );
+
+/**
+ Write data to the flash part. Remark: Erase may be needed before write to the
+ flash part.
+
+ @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
+ @param[in] FlashRegionType The Flash Region type for flash cycle which
+ is listed in the Descriptor.
+ @param[in] Address The Flash Linear Address must fall within a
+ region for which BIOS has access permissions.
+ @param[in] ByteCount Number of bytes in the data portion of the
+ SPI cycle.
+ @param[in] Buffer Pointer to caller-allocated buffer containing
+ the data sent during the SPI cycle.
+
+ @retval EFI_SUCCESS Command succeed.
+ @retval EFI_INVALID_PARAMETER The parameters specified are not valid.
+ @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *PCH_SPI_FLASH_WRITE) (
+ IN PCH_SPI_PROTOCOL *This,
+ IN FLASH_REGION_TYPE FlashRegionType,
+ IN UINT32 Address,
+ IN UINT32 ByteCount,
+ IN UINT8 *Buffer
+ );
+
+/**
+ Erase area on the flash part.
+
+ @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
+ @param[in] FlashRegionType The Flash Region type for flash cycle which
+ is listed in the Descriptor.
+ @param[in] Address The Flash Linear Address must fall within a
+ region for which BIOS has access permissions.
+ @param[in] ByteCount Number of bytes in the data portion of the
+ SPI cycle.
+
+ @retval EFI_SUCCESS Command succeed.
+ @retval EFI_INVALID_PARAMETER The parameters specified are not valid.
+ @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *PCH_SPI_FLASH_ERASE) (
+ IN PCH_SPI_PROTOCOL *This,
+ IN FLASH_REGION_TYPE FlashRegionType,
+ IN UINT32 Address,
+ IN UINT32 ByteCount
+ );
+
+/**
+ Read SFDP data from the flash part.
+
+ @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
+ @param[in] ComponentNumber The Componen Number for chip select
+ @param[in] Address The starting byte address for SFDP data read.
+ @param[in] ByteCount Number of bytes in SFDP data portion of the
+ SPI cycle
+ @param[out] SfdpData The Pointer to caller-allocated buffer
+ containing the SFDP data received
+ It is the caller's responsibility to make
+ sure Buffer is large enough for the total
+ number of bytes read
+
+ @retval EFI_SUCCESS Command succeed.
+ @retval EFI_INVALID_PARAMETER The parameters specified are not valid.
+ @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *PCH_SPI_FLASH_READ_SFDP) (
+ IN PCH_SPI_PROTOCOL *This,
+ IN UINT8 ComponentNumber,
+ IN UINT32 Address,
+ IN UINT32 ByteCount,
+ OUT UINT8 *SfdpData
+ );
+
+/**
+ Read Jedec Id from the flash part.
+
+ @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
+ @param[in] ComponentNumber The Componen Number for chip select
+ @param[in] ByteCount Number of bytes in JedecId data portion of
+ the SPI cycle, the data size is 3 typically
+ @param[out] JedecId The Pointer to caller-allocated buffer
+ containing JEDEC ID received.
+ It is the caller's responsibility to make
+ sure Buffer is large enough for the total
+ number of bytes read.
+
+ @retval EFI_SUCCESS Command succeed.
+ @retval EFI_INVALID_PARAMETER The parameters specified are not valid.
+ @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *PCH_SPI_FLASH_READ_JEDEC_ID) (
+ IN PCH_SPI_PROTOCOL *This,
+ IN UINT8 ComponentNumber,
+ IN UINT32 ByteCount,
+ OUT UINT8 *JedecId
+ );
+
+/**
+ Write the status register in the flash part.
+
+ @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
+ @param[in] ByteCount Number of bytes in Status data portion of the
+ SPI cycle, the data size is 1 typically
+ @param[in] StatusValue The Pointer to caller-allocated buffer
+ containing the value of Status register writing
+
+ @retval EFI_SUCCESS Command succeed.
+ @retval EFI_INVALID_PARAMETER The parameters specified are not valid.
+ @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *PCH_SPI_FLASH_WRITE_STATUS) (
+ IN PCH_SPI_PROTOCOL *This,
+ IN UINT32 ByteCount,
+ IN UINT8 *StatusValue
+ );
+
+/**
+ Read status register in the flash part.
+
+ @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
+ @param[in] ByteCount Number of bytes in Status data portion of the
+ SPI cycle, the data size is 1 typically
+ @param[out] StatusValue The Pointer to caller-allocated buffer
+ containing the value of Status register received.
+
+ @retval EFI_SUCCESS Command succeed.
+ @retval EFI_INVALID_PARAMETER The parameters specified are not valid.
+ @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *PCH_SPI_FLASH_READ_STATUS) (
+ IN PCH_SPI_PROTOCOL *This,
+ IN UINT32 ByteCount,
+ OUT UINT8 *StatusValue
+ );
+
+/**
+ Get the SPI region base and size, based on the enum type
+
+ @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
+ @param[in] FlashRegionType The Flash Region type for for the base address
+ which is listed in the Descriptor.
+ @param[out] BaseAddress The Flash Linear Address for the Region 'n'
+ Base
+ @param[out] RegionSize The size for the Region 'n'
+
+ @retval EFI_SUCCESS Read success
+ @retval EFI_INVALID_PARAMETER Invalid region type given
+ @retval EFI_DEVICE_ERROR The region is not used
+**/
+typedef
+EFI_STATUS
+(EFIAPI *PCH_SPI_GET_REGION_ADDRESS) (
+ IN PCH_SPI_PROTOCOL *This,
+ IN FLASH_REGION_TYPE FlashRegionType,
+ OUT UINT32 *BaseAddress,
+ OUT UINT32 *RegionSize
+ );
+
+/**
+ Read PCH Soft Strap Values
+
+ @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
+ @param[in] SoftStrapAddr PCH Soft Strap address offset from FPSBA.
+ @param[in] ByteCount Number of bytes in SoftStrap data portion of
+ the SPI cycle
+ @param[out] SoftStrapValue The Pointer to caller-allocated buffer
+ containing PCH Soft Strap Value.
+ If the value of ByteCount is 0, the data type
+ of SoftStrapValue should be UINT16 and
+ SoftStrapValue will be PCH Soft Strap Length.
+ It is the caller's responsibility to make sure
+ Buffer is large enough for the total number of
+ bytes read.
+
+ @retval EFI_SUCCESS Command succeed.
+ @retval EFI_INVALID_PARAMETER The parameters specified are not valid.
+ @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *PCH_SPI_READ_PCH_SOFTSTRAP) (
+ IN PCH_SPI_PROTOCOL *This,
+ IN UINT32 SoftStrapAddr,
+ IN UINT32 ByteCount,
+ OUT VOID *SoftStrapValue
+ );
+
+/**
+ Read CPU Soft Strap Values
+
+ @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
+ @param[in] SoftStrapAddr CPU Soft Strap address offset from FCPUSBA.
+ @param[in] ByteCount Number of bytes in SoftStrap data portion of
+ the SPI cycle.
+ @param[out] SoftStrapValue The Pointer to caller-allocated buffer
+ containing CPU Soft Strap Value.
+ If the value of ByteCount is 0, the data type
+ of SoftStrapValue should be UINT16 and
+ SoftStrapValue will be PCH Soft Strap Length
+ It is the caller's responsibility to make sure
+ Buffer is large enough for the total number
+ of bytes read.
+
+ @retval EFI_SUCCESS Command succeed.
+ @retval EFI_INVALID_PARAMETER The parameters specified are not valid.
+ @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *PCH_SPI_READ_CPU_SOFTSTRAP) (
+ IN PCH_SPI_PROTOCOL *This,
+ IN UINT32 SoftStrapAddr,
+ IN UINT32 ByteCount,
+ OUT VOID *SoftStrapValue
+ );
+
+/**
+ These protocols/PPI allows a platform module to perform SPI operations
+ through the Intel PCH SPI Host Controller Interface.
+**/
+struct _PCH_SPI_PROTOCOL {
+ /**
+ This member specifies the revision of this structure. This field is
+ used to indicate backwards compatible changes to the protocol.
+ **/
+ UINT8 Revision;
+ PCH_SPI_FLASH_READ FlashRead; ///< Read data from the flash part.
+ PCH_SPI_FLASH_WRITE FlashWrite; ///< Write data to the flash part. Remark: Erase may be needed before write to the flash part.
+ PCH_SPI_FLASH_ERASE FlashErase; ///< Erase some area on the flash part.
+ PCH_SPI_FLASH_READ_SFDP FlashReadSfdp; ///< Read SFDP data from the flash part.
+ PCH_SPI_FLASH_READ_JEDEC_ID FlashReadJedecId; ///< Read Jedec Id from the flash part.
+ PCH_SPI_FLASH_WRITE_STATUS FlashWriteStatus; ///< Write the status register in the flash part.
+ PCH_SPI_FLASH_READ_STATUS FlashReadStatus; ///< Read status register in the flash part.
+ PCH_SPI_GET_REGION_ADDRESS GetRegionAddress; ///< Get the SPI region base and size
+ PCH_SPI_READ_PCH_SOFTSTRAP ReadPchSoftStrap; ///< Read PCH Soft Strap Values
+ PCH_SPI_READ_CPU_SOFTSTRAP ReadCpuSoftStrap; ///< Read CPU Soft Strap Values
+};
+
+/**
+ PCH SPI PPI/PROTOCOL revision number
+
+ Revision 1: Initial version
+**/
+#define PCH_SPI_SERVICES_REVISION 1
+
+#endif
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Protocol/Wdt.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Protocol/Wdt.h
new file mode 100644
index 0000000000..a68085fa54
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Protocol/Wdt.h
@@ -0,0 +1,111 @@
+/** @file
+ Watchdog Timer protocol
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _DXE_WDT_H_
+#define _DXE_WDT_H_
+
+//
+// Extern the GUID for protocol users.
+//
+extern EFI_GUID gWdtProtocolGuid;
+//
+// Forward reference for ANSI C compatibility
+//
+typedef struct _WDT_PROTOCOL WDT_PROTOCOL;
+
+/**
+ Reloads WDT with new timeout value and starts it. Also sets Unexpected Reset bit, which
+ causes the next reset to be treated as watchdog expiration - unless AllowKnownReset()
+ function was called too.
+
+ @param[in] TimeoutValue Time in seconds before WDT times out. Supported range = 1 - 1024.
+
+ @retval EFI_SUCCESS if everything's OK
+ @retval EFI_INVALID_PARAMETER if TimeoutValue parameter is wrong
+**/
+typedef
+EFI_STATUS
+(EFIAPI *WDT_RELOAD_AND_START) (
+ UINT32 TimeoutValue
+ );
+
+/**
+ Returns WDT failure status.
+
+ @retval V_PCH_OC_WDT_CTL_STATUS_FAILURE If there was WDT expiration or unexpected reset
+ @retval V_PCH_OC_WDT_CTL_STATUS_OK Otherwise
+**/
+typedef
+UINT8
+(EFIAPI *WDT_CHECK_STATUS) (
+ VOID
+ );
+
+/**
+ Returns information if WDT coverage for the duration of BIOS execution
+ was requested by an OS application.
+
+ @retval TRUE if WDT was requested
+ @retval FALSE if WDT was not requested
+**/
+typedef
+UINT8
+(EFIAPI *IS_WDT_REQUIRED) (
+ VOID
+ );
+
+/**
+ Returns WDT enabled/disabled status.
+
+ @retval TRUE if WDT is enabled
+ @retval FALSE if WDT is disabled
+**/
+typedef
+UINT8
+(EFIAPI *IS_WDT_ENABLED) (
+ VOID
+ );
+
+/**
+ Disables WDT timer.
+**/
+typedef
+VOID
+(EFIAPI *WDT_DISABLE) (
+ VOID
+ );
+
+/**
+ Normally, each reboot performed while watchdog runs is considered a failure.
+ This function allows platform to perform expected reboots with WDT running,
+ without being interpreted as failures.
+ In DXE phase, it is enough to call this function any time before reset.
+ In PEI phase, between calling this function and performing reset, ReloadAndStart()
+ must not be called.
+**/
+typedef
+VOID
+(EFIAPI *WDT_ALLOW_KNOWN_RESET) (
+ VOID
+ );
+
+/**
+ These protocols and PPI allow a platform module to perform watch dog timer operations
+ through the Intel PCH LPC Host Controller Interface. The WDT protocol and WDT PPI
+ implement the Intel (R) Watch Dog timer for DXE, and PEI environments, respectively.
+ WDT_PROTOCOL referenced hereafter represents both WDT_PROTOCOL and WDT_PPI, as they
+ share the identical data structure.
+**/
+struct _WDT_PROTOCOL {
+ WDT_RELOAD_AND_START ReloadAndStart; ///< Reloads WDT with new timeout value and starts it.
+ WDT_CHECK_STATUS CheckStatus; ///< Returns WDT failure status.
+ WDT_DISABLE Disable; ///< Disables WDT timer.
+ WDT_ALLOW_KNOWN_RESET AllowKnownReset; ///< Perform expected reboots with WDT running, without being interpreted as failures.
+ IS_WDT_REQUIRED IsWdtRequired; ///< Returns information if WDT coverage for the duration of BIOS execution was requested by an OS application.
+ IS_WDT_ENABLED IsWdtEnabled; ///< Returns WDT enabled/disabled status.
+};
+
+#endif
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/FlashRegs.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/FlashRegs.h
new file mode 100644
index 0000000000..860f823655
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/FlashRegs.h
@@ -0,0 +1,73 @@
+/** @file
+ Register names for Flash registers
+
+ Conventions:
+
+ - Register definition format:
+ Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_RegisterName
+ - Prefix:
+ Definitions beginning with "R_" are registers
+ Definitions beginning with "B_" are bits within registers
+ Definitions beginning with "V_" are meaningful values within the bits
+ Definitions beginning with "S_" are register size
+ Definitions beginning with "N_" are the bit position
+ - [GenerationName]:
+ Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc.).
+ Register name without GenerationName applies to all generations.
+ - [ComponentName]:
+ This field indicates the component name that the register belongs to (e.g. PCH, SA etc.)
+ Register name without ComponentName applies to all components.
+ Register that is specific to -H denoted by "_PCH_H_" in component name.
+ Register that is specific to -LP denoted by "_PCH_LP_" in component name.
+ - SubsystemName:
+ This field indicates the subsystem name of the component that the register belongs to
+ (e.g. PCIE, USB, SATA, GPIO, PMC etc.).
+ - RegisterSpace:
+ MEM - MMIO space register of subsystem.
+ IO - IO space register of subsystem.
+ PCR - Private configuration register of subsystem.
+ CFG - PCI configuration space register of subsystem.
+ - RegisterName:
+ Full register name.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _FLASH_REGS_H_
+#define _FLASH_REGS_H_
+
+
+//
+// Flash Descriptor Base Address Region (FDBAR) from Flash Region 0
+//
+#define R_FLASH_FDBAR_FLASH_MAP0 0x04
+#define B_FLASH_FDBAR_NC 0x00000300 ///< Number Of Components
+#define N_FLASH_FDBAR_NC 8 ///< Number Of Components
+#define R_FLASH_FDBAR_FLASH_MAP1 0x08
+#define B_FLASH_FDBAR_FPSBA 0x00FF0000 ///< PCH Strap Base Address, [23:16] represents [11:4]
+#define N_FLASH_FDBAR_FPSBA 16 ///< PCH Strap base Address bit position
+#define N_FLASH_FDBAR_FPSBA_REPR 4 ///< PCH Strap base Address bit represents position
+#define B_FLASH_FDBAR_PCHSL 0xFF000000 ///< PCH Strap Length, [31:24] represents number of Dwords
+#define N_FLASH_FDBAR_PCHSL 24 ///< PCH Strap Length bit position
+#define R_FLASH_FDBAR_FLASH_MAP2 0x0C
+#define B_FLASH_FDBAR_FCPUSBA 0x00000FFC ///< CPU Strap Base Address [11:2]
+#define N_FLASH_FDBAR_FCPUSBA 2 ///< CPU Strap Base Address bit position
+#define B_FLASH_FDBAR_CPUSL 0x00FF0000 ///< CPU Strap Length, [23:16] represents number of Dwords
+#define N_FLASH_FDBAR_CPUSL 16 ///< CPU Strap Length bit position
+
+//
+// Flash Component Base Address (FCBA) from Flash Region 0
+//
+#define R_FLASH_FCBA_FLCOMP 0x00 ///< Flash Components Register
+#define B_FLASH_FLCOMP_COMP1_MASK 0xF0 ///< Flash Component 1 Size MASK
+#define N_FLASH_FLCOMP_COMP1 4 ///< Flash Component 1 Size bit position
+#define B_FLASH_FLCOMP_COMP0_MASK 0x0F ///< Flash Component 0 Size MASK
+#define V_FLASH_FLCOMP_COMP_512KB 0x80000
+//
+// Descriptor Upper Map Section from Flash Region 0
+//
+#define R_FLASH_UMAP1 0xEFC ///< Flash Upper Map 1
+#define B_FLASH_UMAP1_MDTBA 0xFF000000 ///< MIP Descriptor Table Base Address
+#define N_FLASH_UMAP1_MDTBA 24 ///< MDTBA bits position
+#define N_FLASH_UMAP1_MDTBA_REPR 4 ///< MDTBA address representation position
+#endif
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/GpioRegs.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/GpioRegs.h
new file mode 100644
index 0000000000..c89dccb7bd
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/GpioRegs.h
@@ -0,0 +1,103 @@
+/** @file
+ Register names for PCH GPIO
+
+Conventions:
+
+ - Register definition format:
+ Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_RegisterName
+ - Prefix:
+ Definitions beginning with "R_" are registers
+ Definitions beginning with "B_" are bits within registers
+ Definitions beginning with "V_" are meaningful values within the bits
+ Definitions beginning with "S_" are register size
+ Definitions beginning with "N_" are the bit position
+ - [GenerationName]:
+ Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc.).
+ Register name without GenerationName applies to all generations.
+ - [ComponentName]:
+ This field indicates the component name that the register belongs to (e.g. PCH, SA etc.)
+ Register name without ComponentName applies to all components.
+ Register that is specific to -H denoted by "_PCH_H_" in component name.
+ Register that is specific to -LP denoted by "_PCH_LP_" in component name.
+ - SubsystemName:
+ This field indicates the subsystem name of the component that the register belongs to
+ (e.g. PCIE, USB, SATA, GPIO, PMC etc.).
+ - RegisterSpace:
+ MEM - MMIO space register of subsystem.
+ IO - IO space register of subsystem.
+ PCR - Private configuration register of subsystem.
+ CFG - PCI configuration space register of subsystem.
+ - RegisterName:
+ Full register name.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _GPIO_REGS_H_
+#define _GPIO_REGS_H_
+
+//
+// PADCFG register is split into multiple DW registers
+// S_GPIO_PCR_PADCFG refers to number of bytes used by all those registers for one pad
+//
+#define S_GPIO_PCR_PADCFG 0x10
+
+//
+// Pad Configuration Register DW0
+//
+
+
+//RX Raw Override to 1
+#define B_GPIO_PCR_RX_RAW1 BIT28
+#define N_GPIO_PCR_RX_RAW1 28
+
+//RX Level/Edge Configuration
+#define B_GPIO_PCR_RX_LVL_EDG (BIT26 | BIT25)
+#define N_GPIO_PCR_RX_LVL_EDG 25
+
+//RX Invert
+#define B_GPIO_PCR_RXINV BIT23
+#define N_GPIO_PCR_RXINV 23
+
+//GPIO Input Route IOxAPIC
+#define B_GPIO_PCR_RX_APIC_ROUTE BIT20
+
+//GPIO Input Route SCI
+#define B_GPIO_PCR_RX_SCI_ROUTE BIT19
+
+//GPIO Input Route SMI
+#define B_GPIO_PCR_RX_SMI_ROUTE BIT18
+
+//GPIO Input Route NMI
+#define B_GPIO_PCR_RX_NMI_ROUTE BIT17
+#define N_GPIO_PCR_RX_NMI_ROUTE 17
+
+//GPIO Pad Mode
+#define B_GPIO_PCR_PAD_MODE (BIT12 | BIT11 | BIT10)
+#define N_GPIO_PCR_PAD_MODE 10
+
+//GPIO RX Disable
+#define B_GPIO_PCR_RXDIS BIT9
+
+//GPIO TX Disable
+#define B_GPIO_PCR_TXDIS BIT8
+#define N_GPIO_PCR_TXDIS 8
+
+//GPIO TX State
+#define B_GPIO_PCR_TX_STATE BIT0
+#define N_GPIO_PCR_TX_STATE 0
+
+//Termination
+#define B_GPIO_PCR_TERM (BIT13 | BIT12 | BIT11 | BIT10)
+#define N_GPIO_PCR_TERM 10
+
+
+///
+/// GPIO SMI data used for EFI_SMM_GPI_DISPATCH2_PROTOCOL
+/// Below defines are to be used internally by PCH SMI dispatcher only
+///
+#define PCH_GPIO_NUM_SUPPORTED_GPIS 512
+#define S_GPIO_PCR_GP_SMI_STS 4
+
+#endif // _GPIO_REGS_H_
+
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/GpioRegsVer2.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/GpioRegsVer2.h
new file mode 100644
index 0000000000..7789236b5e
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/GpioRegsVer2.h
@@ -0,0 +1,211 @@
+/** @file
+ Register names for VER2 GPIO
+
+Conventions:
+
+ - Register definition format:
+ Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_RegisterName
+ - Prefix:
+ Definitions beginning with "R_" are registers
+ Definitions beginning with "B_" are bits within registers
+ Definitions beginning with "V_" are meaningful values within the bits
+ Definitions beginning with "S_" are register size
+ Definitions beginning with "N_" are the bit position
+ - [GenerationName]:
+ Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc.).
+ Register name without GenerationName applies to all generations.
+ - [ComponentName]:
+ This field indicates the component name that the register belongs to (e.g. PCH, SA etc.)
+ Register name without ComponentName applies to all components.
+ Register that is specific to -H denoted by "_PCH_H_" in component name.
+ Register that is specific to -LP denoted by "_PCH_LP_" in component name.
+ - SubsystemName:
+ This field indicates the subsystem name of the component that the register belongs to
+ (e.g. PCIE, USB, SATA, GPIO, PMC etc.).
+ - RegisterSpace:
+ MEM - MMIO space register of subsystem.
+ IO - IO space register of subsystem.
+ PCR - Private configuration register of subsystem.
+ CFG - PCI configuration space register of subsystem.
+ - RegisterName:
+ Full register name.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _GPIO_REGS_VER2_H_
+#define _GPIO_REGS_VER2_H_
+
+#define GPIO_VER2_PCH_LP_GPIO_GPP_B_PAD_MAX 26
+#define GPIO_VER2_PCH_LP_GPIO_GPP_A_PAD_MAX 25
+#define GPIO_VER2_PCH_LP_GPIO_GPP_R_PAD_MAX 8
+#define GPIO_VER2_PCH_LP_GPIO_GPD_PAD_MAX 17
+#define GPIO_VER2_PCH_LP_GPIO_GPP_S_PAD_MAX 8
+#define GPIO_VER2_PCH_LP_GPIO_GPP_H_PAD_MAX 24
+#define GPIO_VER2_PCH_LP_GPIO_GPP_D_PAD_MAX 21
+#define GPIO_VER2_PCH_LP_GPIO_GPP_F_PAD_MAX 25
+#define GPIO_VER2_PCH_LP_GPIO_GPP_C_PAD_MAX 24
+#define GPIO_VER2_PCH_LP_GPIO_GPP_E_PAD_MAX 25
+
+//
+// GPIO Community 0 Private Configuration Registers
+//
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_PAD_OWN 0x20
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_A_PAD_OWN 0x38
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_PADCFGLOCK 0x80
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_PADCFGLOCKTX 0x84
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_A_PADCFGLOCK 0x90
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_A_PADCFGLOCKTX 0x94
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_HOSTSW_OWN 0xB0
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_A_HOSTSW_OWN 0xB8
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_GPI_IS 0x0100
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_A_GPI_IS 0x0108
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_GPI_IE 0x0120
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_A_GPI_IE 0x0128
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_GPI_GPE_STS 0x0140
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_A_GPI_GPE_STS 0x0148
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_GPI_GPE_EN 0x0160
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_A_GPI_GPE_EN 0x0168
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_SMI_STS 0x0180
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_SMI_EN 0x01A0
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_NMI_STS 0x01C0
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_NMI_EN 0x01E0
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_PADCFG_OFFSET 0x700
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_A_PADCFG_OFFSET 0x9A0
+
+//
+// GPIO Community 1 Private Configuration Registers
+//
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_S_PAD_OWN 0x20
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_H_PAD_OWN 0x24
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_PAD_OWN 0x30
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_S_PADCFGLOCK 0x80
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_S_PADCFGLOCKTX 0x84
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_H_PADCFGLOCK 0x88
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_H_PADCFGLOCKTX 0x8C
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_PADCFGLOCK 0x90
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_PADCFGLOCKTX 0x94
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_S_HOSTSW_OWN 0xB0
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_H_HOSTSW_OWN 0xB4
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_HOSTSW_OWN 0xB8
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_S_GPI_IS 0x0100
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_H_GPI_IS 0x0104
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_GPI_IS 0x0108
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_S_GPI_IE 0x0120
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_H_GPI_IE 0x0124
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_GPI_IE 0x0128
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_S_GPI_GPE_STS 0x0140
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_H_GPI_GPE_STS 0x0144
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_GPI_GPE_STS 0x0148
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_S_GPI_GPE_EN 0x0160
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_H_GPI_GPE_EN 0x0164
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_GPI_GPE_EN 0x0168
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_SMI_STS 0x0188
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_SMI_EN 0x01A8
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_NMI_STS 0x01C8
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_NMI_EN 0x01E8
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_S_PADCFG_OFFSET 0x700
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_H_PADCFG_OFFSET 0x780
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_PADCFG_OFFSET 0x900
+//
+// GPIO Community 2 Private Configuration Registers
+//
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPD_PAD_OWN 0x20
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPD_PADCFGLOCK 0x80
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPD_PADCFGLOCKTX 0x84
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPD_HOSTSW_OWN 0xB0
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPD_GPI_IS 0x0100
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPD_GPI_IE 0x0120
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPD_GPI_GPE_STS 0x0140
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPD_GPI_GPE_EN 0x0160
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPD_PADCFG_OFFSET 0x700
+
+//
+// GPIO Community 4 Private Configuration Registers
+//
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_PAD_OWN 0x20
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_F_PAD_OWN 0x2C
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_PAD_OWN 0x40
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_PADCFGLOCK 0x80
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_PADCFGLOCKTX 0x84
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_F_PADCFGLOCK 0x88
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_F_PADCFGLOCKTX 0x8C
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_PADCFGLOCK 0x98
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_PADCFGLOCKTX 0x9C
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_HOSTSW_OWN 0xB0
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_F_HOSTSW_OWN 0xB4
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_HOSTSW_OWN 0xBC
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_GPI_IS 0x0100
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_F_GPI_IS 0x0104
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_GPI_IS 0x010C
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_GPI_IE 0x0120
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_F_GPI_IE 0x0124
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_GPI_IE 0x012C
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_GPI_GPE_STS 0x0140
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_F_GPI_GPE_STS 0x0144
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_GPI_GPE_STS 0x014C
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_GPI_GPE_EN 0x0160
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_F_GPI_GPE_EN 0x0164
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_GPI_GPE_EN 0x016C
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_SMI_STS 0x0180
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_SMI_STS 0x018C
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_SMI_EN 0x01A0
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_SMI_EN 0x01AC
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_NMI_STS 0x01C0
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_NMI_STS 0x01CC
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_NMI_EN 0x01E0
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_NMI_EN 0x01EC
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_PADCFG_OFFSET 0x700
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_F_PADCFG_OFFSET 0x880
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_PADCFG_OFFSET 0xA70
+
+//
+// GPIO Community 5 Private Configuration Registers
+//
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_R_PAD_OWN 0x20
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_R_PADCFGLOCK 0x80
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_R_PADCFGLOCKTX 0x84
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_R_HOSTSW_OWN 0xB0
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_R_GPI_IS 0x0100
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_R_GPI_IE 0x0120
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_R_GPI_GPE_STS 0x0140
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_R_GPI_GPE_EN 0x0160
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_R_PADCFG_OFFSET 0x700
+
+#endif // _GPIO_REGS_VER2_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/PchDmi14Regs.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/PchDmi14Regs.h
new file mode 100644
index 0000000000..f30bf62614
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/PchDmi14Regs.h
@@ -0,0 +1,49 @@
+/** @file
+ Register names for PCH DMI SIP14
+
+Conventions:
+
+ - Register definition format:
+ Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_RegisterName
+ - Prefix:
+ Definitions beginning with "R_" are registers
+ Definitions beginning with "B_" are bits within registers
+ Definitions beginning with "V_" are meaningful values within the bits
+ Definitions beginning with "S_" are register size
+ Definitions beginning with "N_" are the bit position
+ - [GenerationName]:
+ Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc.).
+ Register name without GenerationName applies to all generations.
+ - [ComponentName]:
+ This field indicates the component name that the register belongs to (e.g. PCH, SA etc.)
+ Register name without ComponentName applies to all components.
+ Register that is specific to -H denoted by "_PCH_H_" in component name.
+ Register that is specific to -LP denoted by "_PCH_LP_" in component name.
+ - SubsystemName:
+ This field indicates the subsystem name of the component that the register belongs to
+ (e.g. PCIE, USB, SATA, GPIO, PMC etc.).
+ - RegisterSpace:
+ MEM - MMIO space register of subsystem.
+ IO - IO space register of subsystem.
+ PCR - Private configuration register of subsystem.
+ CFG - PCI configuration space register of subsystem.
+ - RegisterName:
+ Full register name.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _PCH_DMI14_REGS_H_
+#define _PCH_DMI14_REGS_H_
+
+//
+// DMI Chipset Configuration Registers (PID:DMI)
+//
+
+//
+// DMI Control
+//
+#define R_PCH_DMI14_PCR_DMIC 0x2234 ///< DMI Control
+#define B_PCH_DMI14_PCR_DMIC_SRL BIT31 ///< Secured register lock
+
+#endif
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/PchDmiRegs.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/PchDmiRegs.h
new file mode 100644
index 0000000000..649e8dd17b
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/PchDmiRegs.h
@@ -0,0 +1,51 @@
+/** @file
+ Register names for PCH DMI and OP-DMI
+
+Conventions:
+
+ - Register definition format:
+ Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_RegisterName
+ - Prefix:
+ Definitions beginning with "R_" are registers
+ Definitions beginning with "B_" are bits within registers
+ Definitions beginning with "V_" are meaningful values within the bits
+ Definitions beginning with "S_" are register size
+ Definitions beginning with "N_" are the bit position
+ - [GenerationName]:
+ Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc.).
+ Register name without GenerationName applies to all generations.
+ - [ComponentName]:
+ This field indicates the component name that the register belongs to (e.g. PCH, SA etc.)
+ Register name without ComponentName applies to all components.
+ Register that is specific to -H denoted by "_PCH_H_" in component name.
+ Register that is specific to -LP denoted by "_PCH_LP_" in component name.
+ - SubsystemName:
+ This field indicates the subsystem name of the component that the register belongs to
+ (e.g. PCIE, USB, SATA, GPIO, PMC etc.).
+ - RegisterSpace:
+ MEM - MMIO space register of subsystem.
+ IO - IO space register of subsystem.
+ PCR - Private configuration register of subsystem.
+ CFG - PCI configuration space register of subsystem.
+ - RegisterName:
+ Full register name.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _PCH_DMI_REGS_H_
+#define _PCH_DMI_REGS_H_
+
+//
+// PCH DMI Chipset Configuration Registers (PID:DMI)
+//
+
+//
+// PCH DMI Source Decode PCRs (Common)
+//
+#define R_PCH_DMI_PCR_LPCIOD 0x2770 ///< LPC I/O Decode Ranges
+#define R_PCH_DMI_PCR_LPCIOE 0x2774 ///< LPC I/O Enables
+#define R_PCH_DMI_PCR_TCOBASE 0x2778 ///< TCO Base Address
+#define B_PCH_DMI_PCR_TCOBASE_TCOBA 0xFFE0 ///< TCO Base Address Mask
+
+#endif
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/PchPcieRpRegs.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/PchPcieRpRegs.h
new file mode 100644
index 0000000000..17c68cbaaa
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/PchPcieRpRegs.h
@@ -0,0 +1,45 @@
+/** @file
+ Register names for PCH PCI-E root port devices
+
+ Conventions:
+
+ - Register definition format:
+ Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_RegisterName
+ - Prefix:
+ Definitions beginning with "R_" are registers
+ Definitions beginning with "B_" are bits within registers
+ Definitions beginning with "V_" are meaningful values within the bits
+ Definitions beginning with "S_" are register size
+ Definitions beginning with "N_" are the bit position
+ - [GenerationName]:
+ Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc.).
+ Register name without GenerationName applies to all generations.
+ - [ComponentName]:
+ This field indicates the component name that the register belongs to (e.g. PCH, SA etc.)
+ Register name without ComponentName applies to all components.
+ Register that is specific to -H denoted by "_PCH_H_" in component name.
+ Register that is specific to -LP denoted by "_PCH_LP_" in component name.
+ - SubsystemName:
+ This field indicates the subsystem name of the component that the register belongs to
+ (e.g. PCIE, USB, SATA, GPIO, PMC etc.).
+ - RegisterSpace:
+ MEM - MMIO space register of subsystem.
+ IO - IO space register of subsystem.
+ PCR - Private configuration register of subsystem.
+ CFG - PCI configuration space register of subsystem.
+ - RegisterName:
+ Full register name.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _PCH_REGS_PCIE_H_
+#define _PCH_REGS_PCIE_H_
+
+//
+// PCIE PCRs (PID:SPA SPB SPC SPD SPE SPF)
+//
+#define R_SPX_PCR_PCD 0 ///< Port configuration and disable
+#define B_SPX_PCR_PCD_RP1FN (BIT2 | BIT1 | BIT0) ///< Port 1 Function Number
+#define S_SPX_PCR_PCD_RP_FIELD 4 ///< 4 bits for each RP FN
+#endif
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/PchRegsLpc.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/PchRegsLpc.h
new file mode 100644
index 0000000000..326b266352
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/PchRegsLpc.h
@@ -0,0 +1,77 @@
+/** @file
+ Register names for PCH LPC/eSPI device
+
+Conventions:
+
+ - Register definition format:
+ Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_RegisterName
+ - Prefix:
+ Definitions beginning with "R_" are registers
+ Definitions beginning with "B_" are bits within registers
+ Definitions beginning with "V_" are meaningful values within the bits
+ Definitions beginning with "S_" are register size
+ Definitions beginning with "N_" are the bit position
+ - [GenerationName]:
+ Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc.).
+ Register name without GenerationName applies to all generations.
+ - [ComponentName]:
+ This field indicates the component name that the register belongs to (e.g. PCH, SA etc.)
+ Register name without ComponentName applies to all components.
+ Register that is specific to -H denoted by "_PCH_H_" in component name.
+ Register that is specific to -LP denoted by "_PCH_LP_" in component name.
+ - SubsystemName:
+ This field indicates the subsystem name of the component that the register belongs to
+ (e.g. PCIE, USB, SATA, GPIO, PMC etc.).
+ - RegisterSpace:
+ MEM - MMIO space register of subsystem.
+ IO - IO space register of subsystem.
+ PCR - Private configuration register of subsystem.
+ CFG - PCI configuration space register of subsystem.
+ - RegisterName:
+ Full register name.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _PCH_REGS_LPC_H_
+#define _PCH_REGS_LPC_H_
+
+//
+// PCI to LPC Bridge Registers
+//
+
+#define R_LPC_CFG_IOD 0x80
+#define R_LPC_CFG_IOE 0x82
+#define R_ESPI_CFG_CS1IORE 0xA0
+
+#define R_LPC_CFG_ULKMC 0x94
+#define B_LPC_CFG_ULKMC_A20PASSEN BIT5
+#define B_LPC_CFG_ULKMC_64WEN BIT3
+#define B_LPC_CFG_ULKMC_64REN BIT2
+#define B_LPC_CFG_ULKMC_60WEN BIT1
+#define B_LPC_CFG_ULKMC_60REN BIT0
+
+//
+// APM Registers
+//
+#define R_PCH_IO_APM_CNT 0xB2
+#define R_PCH_IO_APM_STS 0xB3
+#define R_LPC_CFG_BC 0xDC ///< Bios Control
+#define S_LPC_CFG_BC 1
+#define N_LPC_CFG_BC_LE 1
+
+//
+// Reset Generator I/O Port
+//
+#define R_PCH_IO_RST_CNT 0xCF9
+#define V_PCH_IO_RST_CNT_FULLRESET 0x0E
+#define V_PCH_IO_RST_CNT_HARDRESET 0x06
+//
+// eSPI PCR Registers
+//
+#define R_ESPI_PCR_CFG_VAL 0xC00C ///< ESPI Enabled Strap
+#define B_ESPI_PCR_CFG_VAL_ESPI_EN BIT0 ///< ESPI Enabled Strap bit position
+#define R_ESPI_PCR_SOFTSTRAPS 0xC210 ///< eSPI Sofstraps Register 0
+#define B_ESPI_PCR_SOFTSTRAPS_CS1_EN BIT12 ///< CS1# Enable
+
+#endif
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/PmcRegs.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/PmcRegs.h
new file mode 100644
index 0000000000..f7153b931c
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/PmcRegs.h
@@ -0,0 +1,134 @@
+/** @file
+ Register names for PCH PMC device
+
+ Conventions:
+
+ - Register definition format:
+ Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_RegisterName
+ - Prefix:
+ Definitions beginning with "R_" are registers
+ Definitions beginning with "B_" are bits within registers
+ Definitions beginning with "V_" are meaningful values within the bits
+ Definitions beginning with "S_" are register size
+ Definitions beginning with "N_" are the bit position
+ - [GenerationName]:
+ Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc.).
+ Register name without GenerationName applies to all generations.
+ - [ComponentName]:
+ This field indicates the component name that the register belongs to (e.g. PCH, SA etc.)
+ Register name without ComponentName applies to all components.
+ Register that is specific to -H denoted by "_PCH_H_" in component name.
+ Register that is specific to -LP denoted by "_PCH_LP_" in component name.
+ - SubsystemName:
+ This field indicates the subsystem name of the component that the register belongs to
+ (e.g. PCIE, USB, SATA, GPIO, PMC etc.).
+ - RegisterSpace:
+ MEM - MMIO space register of subsystem.
+ IO - IO space register of subsystem.
+ PCR - Private configuration register of subsystem.
+ CFG - PCI configuration space register of subsystem.
+ - RegisterName:
+ Full register name.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _PCH_REGS_PMC_H_
+#define _PCH_REGS_PMC_H_
+
+//
+// ACPI and legacy I/O register offsets from ACPIBASE
+//
+#define R_ACPI_IO_PM1_STS 0x00
+#define S_ACPI_IO_PM1_STS 2
+#define B_ACPI_IO_PM1_STS_PRBTNOR BIT11
+#define B_ACPI_IO_PM1_STS_PWRBTN BIT8
+#define N_ACPI_IO_PM1_STS_RTC 10
+#define N_ACPI_IO_PM1_STS_PWRBTN 8
+#define N_ACPI_IO_PM1_STS_TMROF 0
+
+#define R_ACPI_IO_PM1_EN 0x02
+#define S_ACPI_IO_PM1_EN 2
+#define B_ACPI_IO_PM1_EN_PWRBTN BIT8
+#define N_ACPI_IO_PM1_EN_RTC 10
+#define N_ACPI_IO_PM1_EN_PWRBTN 8
+#define N_ACPI_IO_PM1_EN_TMROF 0
+
+#define R_ACPI_IO_PM1_CNT 0x04 ///< Power Management 1 Control
+#define B_ACPI_IO_PM1_CNT_SLP_EN BIT13 ///< Sleep Enable
+#define B_ACPI_IO_PM1_CNT_SLP_TYP (BIT12 | BIT11 | BIT10) ///< Sleep Type
+#define V_ACPI_IO_PM1_CNT_S0 0
+#define V_ACPI_IO_PM1_CNT_S1 BIT10
+#define V_ACPI_IO_PM1_CNT_S3 (BIT12 | BIT10)
+#define V_ACPI_IO_PM1_CNT_S4 (BIT12 | BIT11)
+#define V_ACPI_IO_PM1_CNT_S5 (BIT12 | BIT11 | BIT10)
+#define B_ACPI_IO_PM1_CNT_SCI_EN BIT0 ///< SCI Enable
+
+#define R_ACPI_IO_PM1_TMR 0x08 ///< Power Management 1 Timer
+#define B_ACPI_IO_PM1_TMR_TMR_VAL 0xFFFFFF ///< Timer Value
+#define V_ACPI_IO_PM1_TMR_MAX_VAL 0x1000000 ///< The timer is 24 bit overflow
+
+#define R_ACPI_IO_SMI_EN 0x30 ///< SMI Control and Enable
+#define S_ACPI_IO_SMI_EN 4
+#define B_ACPI_IO_SMI_EN_LEGACY_USB2 BIT17
+#define B_ACPI_IO_SMI_EN_TCO BIT13
+#define B_ACPI_IO_SMI_EN_SWSMI_TMR BIT6
+#define B_ACPI_IO_SMI_EN_APMC BIT5
+#define B_ACPI_IO_SMI_EN_LEGACY_USB BIT3
+#define B_ACPI_IO_SMI_EN_EOS BIT1 ///< End of SMI
+#define B_ACPI_IO_SMI_EN_GBL_SMI BIT0
+#define N_ACPI_IO_SMI_EN_LEGACY_USB3 31
+#define N_ACPI_IO_SMI_EN_PERIODIC 14
+#define N_ACPI_IO_SMI_EN_TCO 13
+#define N_ACPI_IO_SMI_EN_MCSMI 11
+#define N_ACPI_IO_SMI_EN_SWSMI_TMR 6
+#define N_ACPI_IO_SMI_EN_APMC 5
+#define N_ACPI_IO_SMI_EN_ON_SLP_EN 4
+#define N_ACPI_IO_SMI_EN_LEGACY_USB 3
+
+#define R_ACPI_IO_SMI_STS 0x34 ///< SMI Status Register
+#define S_ACPI_IO_SMI_STS 4
+#define B_ACPI_IO_SMI_STS_GPIO_UNLOCK BIT27
+#define B_ACPI_IO_SMI_STS_TCO BIT13
+#define B_ACPI_IO_SMI_STS_APM BIT5
+#define N_ACPI_IO_SMI_STS_LEGACY_USB3 31
+#define N_ACPI_IO_SMI_STS_SPI 26
+#define N_ACPI_IO_SMI_STS_SMBUS 16
+#define N_ACPI_IO_SMI_STS_SERIRQ 15
+#define N_ACPI_IO_SMI_STS_PERIODIC 14
+#define N_ACPI_IO_SMI_STS_TCO 13
+#define N_ACPI_IO_SMI_STS_MCSMI 11
+#define N_ACPI_IO_SMI_STS_GPIO_SMI 10
+#define N_ACPI_IO_SMI_STS_GPE0 9
+#define N_ACPI_IO_SMI_STS_PM1_STS_REG 8
+#define N_ACPI_IO_SMI_STS_SWSMI_TMR 6
+#define N_ACPI_IO_SMI_STS_APM 5
+#define N_ACPI_IO_SMI_STS_ON_SLP_EN 4
+#define N_ACPI_IO_SMI_STS_LEGACY_USB 3
+
+#define R_ACPI_IO_GPE0_STS_127_96 0x6C ///< General Purpose Event 0 Status [127:96]
+#define S_ACPI_IO_GPE0_STS_127_96 4
+#define B_ACPI_IO_GPE0_STS_127_96_WADT BIT18
+#define N_ACPI_IO_GPE0_STS_127_96_PME_B0 13
+#define N_ACPI_IO_GPE0_STS_127_96_PME 11
+#define R_ACPI_IO_GPE0_EN_127_96 0x7C ///< General Purpose Event 0 Enable [127:96]
+#define S_ACPI_IO_GPE0_EN_127_96 4
+#define B_ACPI_IO_GPE0_EN_127_96_WADT BIT18
+#define N_ACPI_IO_GPE0_EN_127_96_PME_B0 13
+#define N_ACPI_IO_GPE0_EN_127_96_PME 11
+
+//
+// PWRM Registers
+//
+#define R_PMC_PWRM_GEN_PMCON_A 0x1020 ///< General PM Configuration A
+#define B_PMC_PWRM_GEN_PMCON_A_SWSMI_RTSL 0xC0
+#define V_PMC_PWRM_GEN_PMCON_A_SWSMI_RTSL_64MS 0xC0
+#define V_PMC_PWRM_GEN_PMCON_A_SWSMI_RTSL_32MS 0x80
+#define V_PMC_PWRM_GEN_PMCON_A_SWSMI_RTSL_16MS 0x40
+#define V_PMC_PWRM_GEN_PMCON_A_SWSMI_RTSL_1_5MS 0x00
+#define B_PMC_PWRM_GEN_PMCON_A_PER_SMI_SEL (BIT2|BIT1) ///< Period SMI Select
+#define V_PMC_PWRM_GEN_PMCON_A_PER_SMI_64S 0x0000
+#define V_PMC_PWRM_GEN_PMCON_A_PER_SMI_32S 0x0002
+#define V_PMC_PWRM_GEN_PMCON_A_PER_SMI_16S 0x0004
+#define V_PMC_PWRM_GEN_PMCON_A_PER_SMI_8S 0x0006
+#endif
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/RtcRegs.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/RtcRegs.h
new file mode 100644
index 0000000000..8424ef5897
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/RtcRegs.h
@@ -0,0 +1,44 @@
+/** @file
+ Register names for RTC device
+
+Conventions:
+
+ - Register definition format:
+ Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_RegisterName
+ - Prefix:
+ Definitions beginning with "R_" are registers
+ Definitions beginning with "B_" are bits within registers
+ Definitions beginning with "V_" are meaningful values within the bits
+ Definitions beginning with "S_" are register size
+ Definitions beginning with "N_" are the bit position
+ - [GenerationName]:
+ Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc.).
+ Register name without GenerationName applies to all generations.
+ - [ComponentName]:
+ This field indicates the component name that the register belongs to (e.g. PCH, SA etc.)
+ Register name without ComponentName applies to all components.
+ Register that is specific to -H denoted by "_PCH_H_" in component name.
+ Register that is specific to -LP denoted by "_PCH_LP_" in component name.
+ - SubsystemName:
+ This field indicates the subsystem name of the component that the register belongs to
+ (e.g. PCIE, USB, SATA, GPIO, PMC etc.).
+ - RegisterSpace:
+ MEM - MMIO space register of subsystem.
+ IO - IO space register of subsystem.
+ PCR - Private configuration register of subsystem.
+ CFG - PCI configuration space register of subsystem.
+ - RegisterName:
+ Full register name.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _REGS_RTC_H_
+#define _REGS_RTC_H_
+
+#define R_RTC_IO_INDEX_ALT 0x74
+#define R_RTC_IO_TARGET_ALT 0x75
+#define R_RTC_IO_EXT_INDEX_ALT 0x76
+#define R_RTC_IO_REGD 0x0D
+
+#endif
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/TcoRegs.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/TcoRegs.h
new file mode 100644
index 0000000000..c3afcd5079
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/TcoRegs.h
@@ -0,0 +1,71 @@
+/** @file
+ Register names for PCH TCO device
+
+ Conventions:
+
+ - Register definition format:
+ Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_RegisterName
+ - Prefix:
+ Definitions beginning with "R_" are registers
+ Definitions beginning with "B_" are bits within registers
+ Definitions beginning with "V_" are meaningful values within the bits
+ Definitions beginning with "S_" are register size
+ Definitions beginning with "N_" are the bit position
+ - [GenerationName]:
+ Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc.).
+ Register name without GenerationName applies to all generations.
+ - [ComponentName]:
+ This field indicates the component name that the register belongs to (e.g. PCH, SA etc.)
+ Register name without ComponentName applies to all components.
+ Register that is specific to -H denoted by "_PCH_H_" in component name.
+ Register that is specific to -LP denoted by "_PCH_LP_" in component name.
+ - SubsystemName:
+ This field indicates the subsystem name of the component that the register belongs to
+ (e.g. PCIE, USB, SATA, GPIO, PMC etc.).
+ - RegisterSpace:
+ MEM - MMIO space register of subsystem.
+ IO - IO space register of subsystem.
+ PCR - Private configuration register of subsystem.
+ CFG - PCI configuration space register of subsystem.
+ - RegisterName:
+ Full register name.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _TCO_REGS_H_
+#define _TCO_REGS_H_
+
+//
+// TCO register I/O map
+//
+#define R_TCO_IO_TCO1_STS 0x04
+#define S_TCO_IO_TCO1_STS 2
+#define B_TCO_IO_TCO1_STS_DMISERR BIT12
+#define B_TCO_IO_TCO1_STS_DMISMI BIT10
+#define B_TCO_IO_TCO1_STS_DMISCI BIT9
+#define B_TCO_IO_TCO1_STS_BIOSWR BIT8
+#define B_TCO_IO_TCO1_STS_NEWCENTURY BIT7
+#define B_TCO_IO_TCO1_STS_TIMEOUT BIT3
+#define B_TCO_IO_TCO1_STS_TCO_INT BIT2
+#define B_TCO_IO_TCO1_STS_SW_TCO_SMI BIT1
+#define N_TCO_IO_TCO1_STS_DMISMI 10
+#define N_TCO_IO_TCO1_STS_BIOSWR 8
+#define N_TCO_IO_TCO1_STS_NEWCENTURY 7
+#define N_TCO_IO_TCO1_STS_TIMEOUT 3
+#define N_TCO_IO_TCO1_STS_SW_TCO_SMI 1
+#define N_TCO_IO_TCO1_STS_NMI2SMI 0
+
+#define R_TCO_IO_TCO2_STS 0x06
+#define S_TCO_IO_TCO2_STS 2
+#define N_TCO_IO_TCO2_STS_INTRD_DET 0
+
+#define R_TCO_IO_TCO1_CNT 0x08
+#define S_TCO_IO_TCO1_CNT 2
+#define N_TCO_IO_TCO1_CNT_NMI2SMI_EN 9
+
+#define R_TCO_IO_TCO2_CNT 0x0A
+#define S_TCO_IO_TCO2_CNT 2
+#define N_TCO_IO_TCO2_CNT_INTRD_SEL 2
+
+#endif
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/SerialIoDevices.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/SerialIoDevices.h
new file mode 100644
index 0000000000..1829fb90ff
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/SerialIoDevices.h
@@ -0,0 +1,226 @@
+/** @file
+ Serial IO policy
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _SERIAL_IO_DEVICES_H_
+#define _SERIAL_IO_DEVICES_H_
+
+#include <Protocol/SerialIo.h>
+#include <PchLimits.h>
+
+#pragma pack (push,1)
+
+/**
+ Available working modes for SerialIo SPI Host Controller
+
+ 0: SerialIoSpiDisabled;
+ - Device is placed in D3
+ - Gpio configuration is skipped
+ - PSF:
+ !important! If given device is Function 0 and other higher functions on given device
+ are enabled, PSF disabling is skipped. PSF default will remain and device PCI CFG Space will still be visible.
+ This is needed to allow PCI enumerator access functions above 0 in a multifunction device.
+ <b>1: SerialIoSpiPci;</b>
+ - Gpio pin configuration in native mode for each assigned pin
+ - Device will be enabled in PSF
+ - Only BAR0 will be enabled
+ 2: SerialIoSpiHidden;
+ - Gpio pin configuration in native mode for each assigned pin
+ - Device disabled in the PSF
+ - Both BARs are enabled, BAR1 becomes devices Pci Config Space
+ - BAR0 assigned from the global PCH reserved memory range, reported as motherboard resource by SIRC
+ @note
+ If this controller is located at function 0 and it's mode is set to hidden it will not be visible in the PCI space.
+**/
+typedef enum {
+ SerialIoSpiDisabled,
+ SerialIoSpiPci,
+ SerialIoSpiHidden
+} SERIAL_IO_SPI_MODE;
+
+/**
+ Used to set Inactive/Idle polarity of Spi Chip Select
+**/
+typedef enum {
+ SerialIoSpiCsActiveLow = 0,
+ SerialIoSpiCsActiveHigh = 1
+} SERIAL_IO_CS_POLARITY;
+
+/**
+ SPI signals pin muxing settings. If signal can be enable only on a single pin
+ then this parameter is ignored by RC. Refer to GPIO_*_MUXING_SERIALIO_SPIx_* in GpioPins*.h
+ for supported settings on a given platform
+**/
+typedef struct {
+ UINT32 Cs[PCH_MAX_SERIALIO_SPI_CHIP_SELECTS]; ///< CS Pin mux configuration. Refer to GPIO_*_MUXING_SERIALIO_SPIx_CS_*
+ UINT32 Clk; ///< CLK Pin mux configuration. Refer to GPIO_*_MUXING_SERIALIO_SPIx_CLK_*
+ UINT32 Miso; ///< MISO Pin mux configuration. Refer to GPIO_*_MUXING_SERIALIO_SPIx_MISO_*
+ UINT32 Mosi; ///< MOSI Pin mux configuration. Refer to GPIO_*_MUXING_SERIALIO_SPIx_MOSI_*
+} SPI_PIN_MUX;
+
+/**
+ The SERIAL_IO_SPI_CONFIG provides the configurations to set the Serial IO SPI controller
+**/
+typedef struct {
+ UINT8 Mode; ///< <b>SerialIoSpiPci </b> see SERIAL_IO_SPI_MODE
+ UINT8 DefaultCsOutput; ///< <b>0 = CS0</b> CS1, CS2, CS3. Default CS used by the SPI HC
+ UINT8 CsPolarity[PCH_MAX_SERIALIO_SPI_CHIP_SELECTS]; ///< Selects SPI ChipSelect signal polarity, 0 = low <b>1 = High</b>
+ UINT8 CsEnable[PCH_MAX_SERIALIO_SPI_CHIP_SELECTS]; ///< <b>0 = Enable</b> 1 = Disable. Based on this setting GPIO for given SPIx CSx will be configured in Native mode
+ UINT8 CsMode; ///< <b>0 = HW Control</b> 1 = SW Control. Sets Chip Select Control mode Hardware or Software.
+ UINT8 CsState; ///< <b>0 = CS is set to low</b> 1 = CS is set to high
+ SPI_PIN_MUX PinMux; ///< SPI Pinmux configuration
+} SERIAL_IO_SPI_CONFIG;
+
+/**
+ Available working modes for SerialIo UART Host Controller
+
+ 0: SerialIoUartDisabled;
+ - Device is placed in D3
+ - Gpio configuration is skipped
+ - PSF:
+ !important! If given device is Function 0 and other higher functions on given device
+ are enabled, PSF disabling is skipped. PSF default will remain and device PCI CFG Space will still be visible.
+ This is needed to allow PCI enumerator access functions above 0 in a multifunction device.
+ <b>1: SerialIoUartPci;</b>
+ - Designated for Serial IO UART OS driver usage
+ - Gpio pin configuration in native mode for each assigned pin
+ - Device will be enabled in PSF
+ - Only BAR0 will be enabled
+ 2: SerialIoUartHidden;
+ - Designated for BIOS and/or DBG2 OS kernel debug
+ - Gpio pin configuration in native mode for each assigned pin
+ - Device disabled in the PSF
+ - Both BARs are enabled, BAR1 becomes devices Pci Config Space
+ - BAR0 assigned from the global PCH reserved memory range, reported as motherboard resource by SIRC
+ @note
+ If this controller is located at function 0 and it's mode is set to hidden it will not be visible in the PCI space.
+ 3: SerialIoUartCom;
+ - Designated for 16550/PNP0501 compatible COM device
+ - Gpio pin configuration in native mode for each assigned pin
+ - Device disabled in the PSF
+ - Both BARs are enabled, BAR1 becomes devices Pci Config Space
+ - BAR0 assigned from the global PCH reserved memory range, reported as motherboard resource by SIRC
+ 4: SerialIoUartSkipInit;
+ - Gpio configuration is skipped
+ - PSF configuration is skipped
+ - BAR assignemnt is skipped
+ - D-satate setting is skipped
+
+**/
+typedef enum {
+ SerialIoUartDisabled,
+ SerialIoUartPci,
+ SerialIoUartHidden,
+ SerialIoUartCom,
+ SerialIoUartSkipInit
+} SERIAL_IO_UART_MODE;
+
+/**
+ UART Settings
+**/
+typedef struct {
+ UINT32 BaudRate; ///< <b> 115200 </b> Max 6000000 MdePkg.dec PcdUartDefaultBaudRate
+ UINT8 Parity; ///< <b> 1 - No Parity</b> see EFI_PARITY_TYPE MdePkg.dec PcdUartDefaultParity
+ UINT8 DataBits; ///< <b>8</b> MdePkg.dec PcdUartDefaultDataBits
+ UINT8 StopBits; ///< <b>1 - One Stop Bit</b> see EFI_STOP_BITS_TYPE MdePkg.dec PcdUartDefaultStopBits
+ UINT8 AutoFlow; ///< <b>FALSE</b> IntelFrameworkModulePkg.dsc PcdIsaBusSerialUseHalfHandshake
+} SERIAL_IO_UART_ATTRIBUTES;
+
+/**
+ UART signals pin muxing settings. If signal can be enable only on a single pin
+ then this parameter is ignored by RC. Refer to GPIO_*_MUXING_SERIALIO_UARTx_* in GpioPins*.h
+ for supported settings on a given platform
+**/
+typedef struct {
+ UINT32 Rx; ///< RXD Pin mux configuration. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RXD_*
+ UINT32 Tx; ///< TXD Pin mux configuration. Refer to GPIO_*_MUXING_SERIALIO_UARTx_TXD_*
+ UINT32 Rts; ///< RTS Pin mux configuration. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RTS_*
+ UINT32 Cts; ///< CTS Pin mux configuration. Refer to GPIO_*_MUXING_SERIALIO_UARTx_CTS_*
+} UART_PIN_MUX;
+
+/**
+ Serial IO UART Controller Configuration
+**/
+typedef struct {
+ SERIAL_IO_UART_ATTRIBUTES Attributes; ///< see SERIAL_IO_UART_ATTRIBUTES
+ UART_PIN_MUX PinMux; ///< UART pin mux configuration
+ UINT8 Mode; ///< <b> SerialIoUartPci </b> see SERIAL_IO_UART_MODE
+ UINT8 DBG2; ///< <b> FALSE </b> If TRUE adds UART to DBG2 table and overrides UartPg to SerialIoUartPgDisabled
+ UINT8 PowerGating; ///< <b> SerialIoUartPgAuto </b> Applies to Hidden/COM/SkipInit see SERIAL_IO_UART_PG
+ UINT8 DmaEnable; ///< <b> TRUE </b> Applies to SerialIoUartPci only. Informs OS driver to use DMA, if false it will run in PIO mode
+} SERIAL_IO_UART_CONFIG;
+
+typedef enum {
+ SerialIoUartPgDisabled, ///< No _PS0/_PS3 support, device left in D0, after initialization
+/**
+ In mode: SerialIoUartCom;
+ _PS0/_PS3 that supports getting device out of reset
+ In mode: SerialIoUartPci
+ Keeps UART in D0 and assigns Fixed MMIO for SEC/PEI usage only
+**/
+ SerialIoUartPgEnabled,
+ SerialIoUartPgAuto ///< _PS0 and _PS3, detection through ACPI if device was initialized prior to first PG. If it was used (DBG2) PG is disabled,
+} SERIAL_IO_UART_PG;
+
+/**
+ Available working modes for SerialIo I2C Host Controller
+
+ 0: SerialIoI2cDisabled;
+ - Device is placed in D3
+ - Gpio configuration is skipped
+ - PSF:
+ !important! If given device is Function 0 and other higher functions on given device
+ are enabled, PSF disabling is skipped. PSF default will remain and device PCI CFG Space will still be visible.
+ This is needed to allow PCI enumerator access functions above 0 in a multifunction device.
+ <b>1: SerialIoI2cPci;</b>
+ - Gpio pin configuration in native mode for each assigned pin
+ - Device will be enabled in PSF
+ - Only BAR0 will be enabled
+ 2: SerialIoI2cHidden;
+ - Gpio pin configuration in native mode for each assigned pin
+ - Device disabled in the PSF
+ - Both BARs are enabled, BAR1 becomes devices Pci Config Space
+ - BAR0 assigned from the global PCH reserved memory range, reported as motherboard resource by SIRC
+ @note
+ If this controller is located at function 0 and it's mode is set to hidden it will not be visible in the PCI space.
+**/
+typedef enum {
+ SerialIoI2cDisabled,
+ SerialIoI2cPci,
+ SerialIoI2cHidden
+} SERIAL_IO_I2C_MODE;
+
+/**
+ I2C signals pin muxing settings. If signal can be enable only on a single pin
+ then this parameter is ignored by RC. Refer to GPIO_*_MUXING_SERIALIO_I2Cx_* in GpioPins*.h
+ for supported settings on a given platform
+**/
+typedef struct {
+ UINT32 Sda; ///< SDA Pin mux configuration. Refer to GPIO_*_MUXING_SERIALIO_I2Cx_SDA_*
+ UINT32 Scl; ///< SCL Pin mux configuration. Refer to GPIO_*_MUXING_SERIALIO_I2Cx_SCL_*
+} I2C_PIN_MUX;
+
+/**
+ Serial IO I2C Controller Configuration
+**/
+typedef struct {
+ UINT8 Mode; /// <b>SerialIoI2cPci <b> see SERIAL_IO_I2C_MODE
+ /**
+ I2C Pads Internal Termination.
+ For more information please see Platform Design Guide.
+ Supported values (check GPIO_ELECTRICAL_CONFIG for reference):
+ <b>GpioTermNone: No termination</b>,
+ GpioTermWpu1K: 1kOhm weak pull-up,
+ GpioTermWpu5K: 5kOhm weak pull-up,
+ GpioTermWpu20K: 20kOhm weak pull-up
+ **/
+ UINT8 PadTermination;
+ UINT8 Reserved[2];
+ I2C_PIN_MUX PinMux; ///< I2C pin mux configuration
+} SERIAL_IO_I2C_CONFIG;
+
+#pragma pack (pop)
+
+#endif // _SERIAL_IO_DEVICES_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/SiConfigHob.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/SiConfigHob.h
new file mode 100644
index 0000000000..089141d143
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/SiConfigHob.h
@@ -0,0 +1,17 @@
+/** @file
+ Silicon Config HOB is used for gathering platform
+ related Intel silicon information and config setting.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _SI_CONFIG_HOB_H_
+#define _SI_CONFIG_HOB_H_
+
+#include <SiPolicyStruct.h>
+
+extern EFI_GUID gSiConfigHobGuid;
+
+// Rename SI_CONFIG_HOB into SI_CONFIG_HOB_DATA for it does not follow HOB structure.
+typedef CONST SI_CONFIG SI_CONFIG_HOB_DATA;
+#endif
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/SiPolicyStruct.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/SiPolicyStruct.h
new file mode 100644
index 0000000000..4dacba242e
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/SiPolicyStruct.h
@@ -0,0 +1,64 @@
+/** @file
+ Intel reference code configuration policies.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _SI_POLICY_STRUCT_H_
+#define _SI_POLICY_STRUCT_H_
+
+#include <ConfigBlock.h>
+#include <ConfigBlock/SiPreMemConfig.h>
+#include <ConfigBlock/SiConfig.h>
+
+/**
+ Silicon Policy revision number
+ Any change to this structure will result in an update in the revision number
+
+ This member specifies the revision of the Silicon Policy. This field is used to indicate change
+ to the policy structure.
+
+ <b>Revision 1</b>:
+ - Initial version.
+**/
+#define SI_POLICY_REVISION 1
+
+/**
+ Silicon pre-memory Policy revision number
+ Any change to this structure will result in an update in the revision number
+
+ <b>Revision 1</b>:
+ - Initial version.
+**/
+#define SI_PREMEM_POLICY_REVISION 1
+
+
+/**
+ SI Policy PPI in Pre-Mem\n
+ All SI config block change history will be listed here\n\n
+
+ - <b>Revision 1</b>:
+ - Initial version.\n
+**/
+struct _SI_PREMEM_POLICY_STRUCT {
+ CONFIG_BLOCK_TABLE_HEADER TableHeader; ///< Config Block Table Header
+/*
+ Individual Config Block Structures are added here in memory as part of AddConfigBlock()
+*/
+};
+
+/**
+ SI Policy PPI\n
+ All SI config block change history will be listed here\n\n
+
+ - <b>Revision 1</b>:
+ - Initial version.\n
+**/
+struct _SI_POLICY_STRUCT {
+ CONFIG_BLOCK_TABLE_HEADER TableHeader; ///< Config Block Table Header
+/*
+ Individual Config Block Structures are added here in memory as part of AddConfigBlock()
+*/
+};
+
+#endif
--
2.36.1.windows.1
-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#108683): https://edk2.groups.io/g/devel/message/108683
Mute This Topic: https://groups.io/mt/101373951/7686176
Group Owner: devel+owner@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [rebecca@openfw.io]
-=-=-=-=-=-=-=-=-=-=-=-
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [edk2-devel] [PATCH v2 08/10] AlderlakeSiliconPkg/Fru: Add AdlCpu Fru
2023-09-15 4:45 [edk2-devel] [PATCH v2 01/10] AlderlakeSiliconPkg/IpBlock: Add CpuPcieRp, Espi, Gpio components Saloni Kasbekar
` (5 preceding siblings ...)
2023-09-15 4:45 ` [edk2-devel] [PATCH v2 07/10] AlderlakeSiliconPkg/Include: Add Protocol, Register, Other Includes Saloni Kasbekar
@ 2023-09-15 4:45 ` Saloni Kasbekar
2023-09-15 5:43 ` Chaganty, Rangasai V
2023-09-15 23:56 ` Nate DeSimone
2023-09-15 4:45 ` [edk2-devel] [PATCH v2 09/10] AlderlakeSiliconPkg: Add AdlPch Fru and IncludePrivate modules Saloni Kasbekar
` (4 subsequent siblings)
11 siblings, 2 replies; 41+ messages in thread
From: Saloni Kasbekar @ 2023-09-15 4:45 UTC (permalink / raw)
To: devel; +Cc: Saloni Kasbekar, Sai Chaganty, Nate DeSimone, Rosen Chuang
Adds the following modules:
- AdlCpu/CpuPcieRp
- AdlCpu/Include
- AdlCpu/IncludePrivate
- AdlCpu/LibraryPrivate
- AdlCpu/PeiReportCpuHob
- AdlCpu DSCs
Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Rosen Chuang <rosen.chuang@intel.com>
Signed-off-by: Saloni Kasbekar <saloni.kasbekar@intel.com>
---
.../Fru/AdlCpu/CommonLib.dsc | 9 +
.../CpuPcieInfoFruLib.c | 87 ++++++++++
.../PeiDxeSmmCpuPcieInfoFruLib.inf | 39 +++++
.../AlderlakeSiliconPkg/Fru/AdlCpu/DxeLib.dsc | 8 +
.../Fru/AdlCpu/Include/CpuGenInfo.h | 42 +++++
.../Include/Library/CpuPcieInfoFruLib.h | 45 +++++
.../Include/Register/SaRegsHostBridge.h | 64 +++++++
.../AdlCpu/IncludePrivate/CpuGenInfoFruLib.h | 44 +++++
.../AdlCpu/IncludePrivate/Register/IgdRegs.h | 34 ++++
.../BaseCpuInfoFruLib/BaseCpuInfoFruLib.c | 164 ++++++++++++++++++
.../BaseCpuInfoFruLib/BaseCpuInfoFruLib.inf | 29 ++++
.../PeiReportCpuHobLib/PeiReportCpuHobLib.c | 22 +++
.../PeiReportCpuHobLib/PeiReportCpuHobLib.inf | 26 +++
13 files changed, 613 insertions(+)
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/CommonLib.dsc
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/CpuPcieRp/Library/PeiDxeSmmCpuPcieInfoFruLib/CpuPcieInfoFruLib.c
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/CpuPcieRp/Library/PeiDxeSmmCpuPcieInfoFruLib/PeiDxeSmmCpuPcieInfoFruLib.inf
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/DxeLib.dsc
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/Include/CpuGenInfo.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/Include/Library/CpuPcieInfoFruLib.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/Include/Register/SaRegsHostBridge.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/IncludePrivate/CpuGenInfoFruLib.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/IncludePrivate/Register/IgdRegs.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/LibraryPrivate/BaseCpuInfoFruLib/BaseCpuInfoFruLib.c
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/LibraryPrivate/BaseCpuInfoFruLib/BaseCpuInfoFruLib.inf
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/PeiReportCpuHob/Library/PeiReportCpuHobLib/PeiReportCpuHobLib.c
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/PeiReportCpuHob/Library/PeiReportCpuHobLib/PeiReportCpuHobLib.inf
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/CommonLib.dsc b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/CommonLib.dsc
new file mode 100644
index 0000000000..35a3cce916
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/CommonLib.dsc
@@ -0,0 +1,9 @@
+## @file
+# Component description file for the AlderLake CPU Common FRU libraries.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+CpuPcieInfoFruLib|$(PLATFORM_SI_PACKAGE)/Fru/AdlCpu/CpuPcieRp/Library/PeiDxeSmmCpuPcieInfoFruLib/PeiDxeSmmCpuPcieInfoFruLib.inf
+CpuInfoFruLib|$(PLATFORM_SI_PACKAGE)/Fru/AdlCpu/LibraryPrivate/BaseCpuInfoFruLib/BaseCpuInfoFruLib.inf
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/CpuPcieRp/Library/PeiDxeSmmCpuPcieInfoFruLib/CpuPcieInfoFruLib.c b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/CpuPcieRp/Library/PeiDxeSmmCpuPcieInfoFruLib/CpuPcieInfoFruLib.c
new file mode 100644
index 0000000000..277b73fe67
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/CpuPcieRp/Library/PeiDxeSmmCpuPcieInfoFruLib/CpuPcieInfoFruLib.c
@@ -0,0 +1,87 @@
+/** @file
+ CPU PCIe information library.
+
+ All function in this library is available for PEI, DXE, and SMM,
+ But do not support UEFI RUNTIME environment call.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#include <Uefi/UefiBaseType.h>
+#include <Library/CpuPlatformLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseLib.h>
+#include <Library/PciSegmentLib.h>
+#include <Register/SaRegsHostBridge.h>
+#include <Library/CpuPcieInfoFruLib.h>
+#include <CpuPcieInfo.h>
+
+/**
+ Get Maximum CPU Pcie Root Port Number
+
+ @retval Maximum CPU Pcie Root Port Number
+**/
+UINT8
+GetMaxCpuPciePortNum (
+ VOID
+ )
+{
+ switch (GetCpuSku ()) {
+ case EnumCpuUlt:
+ return CPU_PCIE_ULT_MAX_ROOT_PORT;
+ case EnumCpuUlx:
+ return CPU_PCIE_ULX_MAX_ROOT_PORT;
+ default:
+ return CPU_PCIE_ULT_MAX_ROOT_PORT;
+ }
+}
+
+/**
+ Get CPU Pcie Root Port Device and Function Number by Root Port physical Number
+
+ @param[in] RpNumber Root port physical number. (0-based)
+ @param[out] RpDev Return corresponding root port device number.
+ @param[out] RpFun Return corresponding root port function number.
+
+ @retval EFI_SUCCESS Root port device and function is retrieved
+ @retval EFI_INVALID_PARAMETER RpNumber is invalid
+**/
+EFI_STATUS
+EFIAPI
+GetCpuPcieRpDevFun (
+ IN UINTN RpNumber,
+ OUT UINTN *RpDev,
+ OUT UINTN *RpFun
+ )
+{
+ if (RpNumber > GetMaxCpuPciePortNum ()) {
+ DEBUG ((DEBUG_ERROR, "GetCpuPcieRpDevFun invalid RpNumber %x", RpNumber));
+ ASSERT (FALSE);
+ return EFI_INVALID_PARAMETER;
+ }
+
+ switch (RpNumber) {
+ case 0:
+ *RpDev = 6;
+ *RpFun = 0;
+ break;
+ case 1:
+ *RpDev = 1;
+ *RpFun = 0;
+ break;
+ case 2:
+ if (GetCpuSku () == EnumCpuTrad) {
+ *RpDev = 1;
+ *RpFun = 1;
+ } else {
+ *RpDev = 6;
+ *RpFun = 2;
+ }
+ break;
+ default:
+ *RpDev = 6;
+ *RpFun = 0;
+ break;
+ }
+ return EFI_SUCCESS;
+}
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/CpuPcieRp/Library/PeiDxeSmmCpuPcieInfoFruLib/PeiDxeSmmCpuPcieInfoFruLib.inf b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/CpuPcieRp/Library/PeiDxeSmmCpuPcieInfoFruLib/PeiDxeSmmCpuPcieInfoFruLib.inf
new file mode 100644
index 0000000000..f850f1a5f1
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/CpuPcieRp/Library/PeiDxeSmmCpuPcieInfoFruLib/PeiDxeSmmCpuPcieInfoFruLib.inf
@@ -0,0 +1,39 @@
+## @file
+# CPU PCIe information library for TigerLake PCH.
+#
+# All function in this library is available for PEI, DXE, and SMM,
+# But do not support UEFI RUNTIME environment call.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+
+[Defines]
+INF_VERSION = 0x00010017
+BASE_NAME = PeiDxeSmmCpuPcieInfoFruLib
+FILE_GUID = 59CA5352-ED46-4449-BF1C-0D0074C4D5B1
+VERSION_STRING = 1.0
+MODULE_TYPE = BASE
+LIBRARY_CLASS = CpuPcieInfoFruLib
+
+
+[LibraryClasses]
+IoLib
+BaseLib
+DebugLib
+PrintLib
+PciSegmentLib
+PchPcrLib
+PmcPrivateLib
+PcdLib
+ConfigBlockLib
+CpuPlatformLib
+
+[Packages]
+MdePkg/MdePkg.dec
+AlderlakeSiliconPkg/SiPkg.dec
+
+[Sources]
+CpuPcieInfoFruLib.c
+
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/DxeLib.dsc b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/DxeLib.dsc
new file mode 100644
index 0000000000..644230484e
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/DxeLib.dsc
@@ -0,0 +1,8 @@
+# @file
+# Component description file for the AlderLake CPU DXE FRU libraries.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+DxeGraphicsPolicyLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Graphics/LibraryPrivate/DxeGraphicsPolicyLib/DxeGraphicsPolicyLib.inf
+DxeIgdOpRegionInitLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Graphics/LibraryPrivate/DxeIgdOpRegionInitLib/DxeIgdOpRegionInitLib.inf
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/Include/CpuGenInfo.h b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/Include/CpuGenInfo.h
new file mode 100644
index 0000000000..482316829d
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/Include/CpuGenInfo.h
@@ -0,0 +1,42 @@
+/** @file
+ Header file for Cpu Information
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _CPU_GEN_INFO_H_
+#define _CPU_GEN_INFO_H_
+
+#include <CpuRegs.h>
+
+//
+// Processor Definitions
+//
+#define CPUID_FULL_FAMILY_MODEL_ALDERLAKE_MOBILE 0x000906A0
+
+///
+/// Enums for CPU Stepping IDs
+///
+typedef enum {
+
+ ///
+ /// AlderLake Mobile Steppings(ULT)
+ ///
+ EnumAdlJ0 = 0,
+ EnumAdlK0 = 2,
+ EnumAdlL0 = 3,
+
+ ///
+ /// AlderLake Mobile Steppings(ULX)
+ ///
+ EnumAdlQ0 = 1,
+ EnumAdlR0 = 4,
+ EnumAdlS0 = 5,
+
+
+ ///
+ /// Max Stepping
+ ///
+ EnumCpuSteppingMax = CPUID_FULL_STEPPING
+} CPU_STEPPING;
+#endif
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/Include/Library/CpuPcieInfoFruLib.h b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/Include/Library/CpuPcieInfoFruLib.h
new file mode 100644
index 0000000000..9dafa98631
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/Include/Library/CpuPcieInfoFruLib.h
@@ -0,0 +1,45 @@
+/** @file
+ Header file for CpuPcieInfoFruLib.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _CPU_PCIE_INFO_FRU_LIB_H_
+#define _CPU_PCIE_INFO_FRU_LIB_H_
+
+#include <CpuPcieInfo.h>
+
+#define CPU_PCIE_MAX_ROOT_PORTS 4
+#define CPU_PCIE_MAX_CONTROLLERS 3
+
+#define CPU_PCIE_ULT_MAX_ROOT_PORT 3
+#define CPU_PCIE_ULX_MAX_ROOT_PORT 1
+
+/**
+ Get CPU Maximum Pcie Root Port Number
+
+ @retval PcieMaxRootPort Pch Maximum Pcie Root Port Number
+**/
+UINT8
+GetMaxCpuPciePortNum (
+ VOID
+ );
+
+/**
+ Get CPU Pcie Root Port Device and Function Number by Root Port physical Number
+
+ @param[in] RpNumber Root port physical number. (0-based)
+ @param[out] RpDev Return corresponding root port device number.
+ @param[out] RpFun Return corresponding root port function number.
+
+ @retval EFI_SUCCESS Root port device and function is retrieved
+ @retval EFI_INVALID_PARAMETER RpNumber is invalid
+**/
+EFI_STATUS
+EFIAPI
+GetCpuPcieRpDevFun (
+ IN UINTN RpNumber,
+ OUT UINTN *RpDev,
+ OUT UINTN *RpFun
+ );
+#endif // _CPU_PCIE_INFO_FRU_LIB_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/Include/Register/SaRegsHostBridge.h b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/Include/Register/SaRegsHostBridge.h
new file mode 100644
index 0000000000..be4bba3283
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/Include/Register/SaRegsHostBridge.h
@@ -0,0 +1,64 @@
+/** @file
+ Register names for Host Bridge block
+ <b>Conventions</b>:
+ - Prefixes:
+ - Definitions beginning with "R_" are registers
+ - Definitions beginning with "B_" are bits within registers
+ - Definitions beginning with "V_" are meaningful values of bits within the registers
+ - Definitions beginning with "S_" are register sizes
+ - Definitions beginning with "N_" are the bit position
+ - In general, SA registers are denoted by "_SA_" in register names
+ - Registers / bits that are different between SA generations are denoted by
+ "_SA_[generation_name]_" in register/bit names. e.g., "_SA_HSW_"
+ - Registers / bits that are different between SKUs are denoted by "_[SKU_name]"
+ at the end of the register/bit names
+ - Registers / bits of new devices introduced in a SA generation will be just named
+ as "_SA_" without [generation_name] inserted.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _SA_REGS_HOST_BRIDGE_H_
+#define _SA_REGS_HOST_BRIDGE_H_
+
+#define SA_SEG_NUM 0x00
+//
+// DEVICE 0 (Memory Controller Hub)
+//
+#define SA_MC_BUS 0x00
+#define SA_MC_DEV 0x00
+#define SA_MC_FUN 0x00
+#define R_SA_MC_DEVICE_ID 0x02
+
+//
+// AlderLake CPU Mobile SA Device IDs B0:D0:F0
+//
+#define V_SA_DEVICE_ID_MB_ULT_1 0x4641 ///< AlderLake P (6+8+GT) SA DID
+#define V_SA_DEVICE_ID_MB_ULT_2 0x4649 ///< AlderLake P (6+4(f)+GT) SA DID
+#define V_SA_DEVICE_ID_MB_ULT_3 0x4621 ///< AlderLake P (4(f)+8+GT) SA DID
+#define V_SA_DEVICE_ID_MB_ULT_4 0x4609 ///< AlderLake P (2(f)+4(f)+GT) SA DID
+#define V_SA_DEVICE_ID_MB_ULT_5 0x4601 ///< AlderLake P (2+8+GT) SA DID
+#define V_SA_DEVICE_ID_MB_ULT_6 0x4661 ///< AlderLake P (6+8+2) SA DID
+#define V_SA_DEVICE_ID_MB_ULT_7 0x4629 ///< AlderLake P (4+4+1) SA DID
+#define V_SA_DEVICE_ID_MB_ULT_8 0x4619 ///< AlderLake P (1+4+GT) SA DID
+#define V_SA_DEVICE_ID_MB_ULT_9 0x4659 ///< AlderLake P (1+8+GT) SA DID
+#define V_SA_DEVICE_ID_MB_ULT_10 0x4645 ///< AlderLake P (6+6+GT) SA DID
+///
+/// Description:
+/// The SMRAMC register controls how accesses to Compatible SMRAM spaces are treated. The Open, Close and Lock bits function only when G_SMRAME bit is set to 1. Also, the Open bit must be reset before the Lock bit is set.
+///
+#define R_SA_SMRAMC (0x88)
+
+///
+/// Description:
+/// This register contains the Top of low memory address.
+///
+#define R_SA_TOLUD (0xbc)
+///
+/// Description of TOLUD (20:31)
+/// This register contains bits 31 to 20 of an address one byte above the maximum DRAM memory below 4G that is usable by the operating system. Address bits 31 down to 20 programmed to 01h implies a minimum memory size of 1MB. Configuration software must set this value to the smaller of the following 2 choices: maximum amount memory in the system minus ME stolen memory plus one byte or the minimum address allocated for PCI memory. Address bits 19:0 are assumed to be 0_0000h for the purposes of address comparison. The Host interface positively decodes an address towards DRAM if the incoming address is less than the value programmed in this register.
+/// The Top of Low Usable DRAM is the lowest address above both Graphics Stolen memory and Tseg. BIOS determines the base of Graphics Stolen Memory by subtracting the Graphics Stolen Memory Size from TOLUD and further decrements by Tseg size to determine base of Tseg. All the Bits in this register are locked in LT mode.
+/// This register must be 1MB aligned when reclaim is enabled.
+///
+#define B_SA_TOLUD_TOLUD_MASK (0xfff00000)
+#endif
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/IncludePrivate/CpuGenInfoFruLib.h b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/IncludePrivate/CpuGenInfoFruLib.h
new file mode 100644
index 0000000000..5ad7bf4982
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/IncludePrivate/CpuGenInfoFruLib.h
@@ -0,0 +1,44 @@
+ /** @file
+ This file contains Cpu Information for specific generation.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _CPU_GEN_INFO_FRU_LIB_H_
+#define _CPU_GEN_INFO_FRU_LIB_H_
+#include <CpuRegs.h>
+#include <CpuGenInfo.h>
+#include <Register/CommonMsr.h>
+
+///
+/// Used to identify the CPU used for programming with the VR override table
+///
+typedef enum {
+ EnumUnknownCpuId = 0,
+ EnumMinCpuId = 1,
+
+ ///
+ /// ADL P
+ ///
+ EnumAdlP15Watt282fCpuId = 0x30,
+ EnumAdlP28Watt482fCpuId = 0x31,
+ EnumAdlP28Watt682fCpuId = 0x32,
+ EnumAdlP45Watt682fCpuId = 0x35,
+ EnumAdlP15Watt142fCpuId = 0x36,
+ EnumAdlP15Watt242fCpuId = 0x37,
+ EnumAdlP45Watt482fCpuId = 0x38,
+ EnumAdlP45Watt442fCpuId = 0x39,
+ EnumAdlP28Watt442fCpuId = 0x3A,
+ EnumAdlP28Watt282fCpuId = 0x3B,
+ EnumAdlP28Watt242fCpuId = 0x3C,
+ EnumAdlP28Watt142fCpuId = 0x3D,
+ EnumAdlP45Watt242fCpuId = 0x3E,
+ EnumAdlP28Watt182fCpuId = 0x3F,
+ EnumAdlP28Watt662fCpuId = 0x40,
+ EnumAdlP28Watt642fCpuId = 0x41,
+ EnumAdlP45Watt642fCpuId = 0x42,
+ EnumAdlPMaxCpuId = EnumAdlP45Watt642fCpuId,
+
+} CPU_IDENTIFIER;
+
+#endif // _CPU_GEN_INFO_FRU_LIB_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/IncludePrivate/Register/IgdRegs.h b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/IncludePrivate/Register/IgdRegs.h
new file mode 100644
index 0000000000..289b293b32
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/IncludePrivate/Register/IgdRegs.h
@@ -0,0 +1,34 @@
+/** @file
+ Register names for IGD block
+ <b>Conventions</b>:
+ - Prefixes:
+ - Definitions beginning with "R_" are registers
+ - Definitions beginning with "B_" are bits within registers
+ - Definitions beginning with "V_" are meaningful values of bits within the registers
+ - Definitions beginning with "S_" are register sizes
+ - Definitions beginning with "N_" are the bit position
+ - In general, SA registers are denoted by "_SA_" in register names
+ - Registers / bits that are different between SA generations are denoted by
+ "_SA_[generation_name]_" in register/bit names. e.g., "_SA_HSW_"
+ - Registers / bits that are different between SKUs are denoted by "_[SKU_name]"
+ at the end of the register/bit names
+ - Registers / bits of new devices introduced in a SA generation will be just named
+ as "_SA_" without [generation_name] inserted.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _IGD_REGS_H_
+#define _IGD_REGS_H_
+
+///
+/// Device 2 Register Equates
+///
+//
+// The following equates must be reviewed and revised when the specification is ready.
+//
+#define IGD_BUS_NUM 0x00
+#define IGD_DEV_NUM 0x02
+#define IGD_FUN_NUM 0x00
+
+#endif
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/LibraryPrivate/BaseCpuInfoFruLib/BaseCpuInfoFruLib.c b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/LibraryPrivate/BaseCpuInfoFruLib/BaseCpuInfoFruLib.c
new file mode 100644
index 0000000000..d93048eb6e
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/LibraryPrivate/BaseCpuInfoFruLib/BaseCpuInfoFruLib.c
@@ -0,0 +1,164 @@
+/** @file
+ This file contains the Cpu Information for specific generation.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#include <CpuGenInfoFruLib.h>
+#include <Library/BaseLib.h>
+#include <Library/DebugLib.h>
+#include <Register/Cpuid.h>
+#include <Library/CpuPlatformLib.h>
+#include <Library/CpuInfoFruLib.h>
+#include <Register/ArchitecturalMsr.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Register/CommonMsr.h>
+#include <IndustryStandard/SmBios.h>
+#include <Library/PcdLib.h>
+#include <Library/PchInfoLib.h>
+#include <IndustryStandard/Pci22.h>
+#include <Register/IgdRegs.h>
+
+
+STATIC CONST CHAR8 mAdlCpuFamilyString[] = "AlderLake";
+typedef struct {
+ UINT32 CPUID;
+ UINT8 CpuSku;
+ CHAR8 *String;
+} CPU_REV;
+
+typedef struct {
+ CPU_IDENTIFIER CpuIdentifier;
+ UINT8 SupportedCores;
+ UINT8 SupportedAtomCores;
+} CPU_CORE_COUNT;
+
+GLOBAL_REMOVE_IF_UNREFERENCED CONST CPU_REV mProcessorRevisionTable[] = {
+ {CPUID_FULL_FAMILY_MODEL_ALDERLAKE_MOBILE + EnumAdlJ0, EnumCpuUlt, "J0"},
+ {CPUID_FULL_FAMILY_MODEL_ALDERLAKE_MOBILE + EnumAdlK0, EnumCpuUlt, "K0"},
+ {CPUID_FULL_FAMILY_MODEL_ALDERLAKE_MOBILE + EnumAdlL0, EnumCpuUlt, "L0"},
+ {CPUID_FULL_FAMILY_MODEL_ALDERLAKE_MOBILE + EnumAdlQ0, EnumCpuUlt, "Q0"},
+ {CPUID_FULL_FAMILY_MODEL_ALDERLAKE_MOBILE + EnumAdlR0, EnumCpuUlt, "R0"},
+ {CPUID_FULL_FAMILY_MODEL_ALDERLAKE_MOBILE + EnumAdlQ0, EnumCpuUlx, "Q0"},
+ {CPUID_FULL_FAMILY_MODEL_ALDERLAKE_MOBILE + EnumAdlR0, EnumCpuUlx, "R0"},
+ {CPUID_FULL_FAMILY_MODEL_ALDERLAKE_MOBILE + EnumAdlS0, EnumCpuUlx, "S0"}
+};
+
+///
+/// PowerLimits Override table for all SKUs. Non-cTDP parts would have '0' data for TDP level information.
+///
+GLOBAL_REMOVE_IF_UNREFERENCED PPM_OVERRIDE_TABLE mPowerLimitsOverrideTable[] = {
+///
+/// CpuIdentifier TDP MSR PL1 MSR PL2 TdpUp TdpUp TdpNominal TdpNominal TdpDown TdpDown MSR MSR Disablefvm
+/// PL1 PL2 PL1 PL2 PL1 PL2 PL1 PL2 PL4 PL4
+ {EnumAdlP15Watt282fCpuId, 1500, 1500, 5500, 0, 5500, 0, 5500, 0, 5500, 12300, 0}, /// 15W 282 ADL-P
+ {EnumAdlP15Watt142fCpuId, 1500, 1500, 5500, 0, 5500, 0, 5500, 0, 5500, 12300, 0}, /// 15W 142 ADL-P
+ {EnumAdlP15Watt242fCpuId, 1500, 1500, 5500, 0, 5500, 0, 5500, 0, 5500, 12300, 0}, /// 15W 242 ADL-P
+ {EnumAdlP28Watt282fCpuId, 2800, 2800, 6400, 0, 6400, 0, 6400, 0, 6400, 9000, 0}, /// 28W 282 ADL-P
+ {EnumAdlP28Watt482fCpuId, 2800, 2800, 6400, 0, 6400, 0, 6400, 0, 6400, 9000, 0}, /// 28W 482 ADL-P
+ {EnumAdlP28Watt682fCpuId, 2800, 2800, 6400, 0, 6400, 0, 6400, 0, 6400, 14000, 0}, /// 26W 682 ADL-P
+ {EnumAdlP28Watt142fCpuId, 2800, 2800, 6400, 0, 6400, 0, 6400, 0, 6400, 9000, 0}, /// 28W 142 ADL-P
+ {EnumAdlP28Watt242fCpuId, 2800, 2800, 6400, 0, 6400, 0, 6400, 0, 6400, 9000, 0}, /// 28W 242 ADL-P
+ {EnumAdlP28Watt442fCpuId, 2800, 2800, 6400, 0, 6400, 0, 6400, 0, 6400, 9000, 0}, /// 28W 442 ADL-P
+ {EnumAdlP28Watt182fCpuId, 2800, 2800, 6400, 0, 6400, 0, 6400, 0, 6400, 9000, 0}, /// 28W 182 ADL-P
+ {EnumAdlP28Watt642fCpuId, 2800, 2800, 6400, 0, 6400, 0, 6400, 0, 6400, 14000, 0}, /// 26W 682 ADL-P
+ {EnumAdlP28Watt662fCpuId, 2800, 2800, 6400, 0, 6400, 0, 6400, 0, 6400, 14000, 0}, /// 26W 682 ADL-P
+ {EnumAdlP45Watt682fCpuId, 4500, 4500, 11500, 0, 11500, 0, 11500, 0, 11500, 21500, 0}, /// 45W 682 ADL-P
+ {EnumAdlP45Watt242fCpuId, 4500, 4500, 9500, 0, 9500, 0, 9500, 0, 9500, 12500, 0}, /// 45W 242 ADL-P
+ {EnumAdlP45Watt482fCpuId, 4500, 4500, 9500, 0, 9500, 0, 9500, 0, 9500, 12500, 0}, /// 45W 482 ADL-P
+ {EnumAdlP45Watt442fCpuId, 4500, 4500, 9500, 0, 9500, 0, 9500, 0, 9500, 12500, 0}, /// 45W 442 ADL-P
+ {EnumAdlP45Watt642fCpuId, 4500, 4500, 11500, 0, 11500, 0, 11500, 0, 11500, 21500, 0}, /// 45W 642 ADL-P
+};
+
+GLOBAL_REMOVE_IF_UNREFERENCED CONST CPU_CORE_COUNT mCpuCoreCountMappingTable[] = {
+ { EnumAdlP15Watt282fCpuId, 2, 8},
+ { EnumAdlP28Watt282fCpuId, 2, 8},
+ { EnumAdlP28Watt482fCpuId, 4, 8},
+ { EnumAdlP28Watt682fCpuId, 6, 8},
+ { EnumAdlP45Watt682fCpuId, 6, 8},
+ { EnumAdlP45Watt482fCpuId, 4, 8},
+ { EnumAdlP45Watt442fCpuId, 4, 4},
+ { EnumAdlP28Watt442fCpuId, 4, 4},
+ { EnumAdlP15Watt142fCpuId, 1, 4},
+ { EnumAdlP28Watt142fCpuId, 1, 4},
+ { EnumAdlP15Watt242fCpuId, 2, 4},
+ { EnumAdlP28Watt242fCpuId, 2, 4},
+ { EnumAdlP45Watt242fCpuId, 2, 4},
+ { EnumAdlP45Watt642fCpuId, 6, 4},
+ { EnumAdlP28Watt182fCpuId, 1, 8},
+ { EnumAdlP28Watt642fCpuId, 6, 4},
+ { EnumAdlP28Watt662fCpuId, 6, 6},
+};
+
+/**
+ Return CPU Sku
+
+ @param[in] UINT32 CpuFamilyModel
+ @param[in] UINT16 CpuDid
+
+ @retval UINT8 CPU Sku
+**/
+UINT8
+GetCpuSkuInfo (
+ IN UINT32 CpuFamilyModel,
+ IN UINT16 CpuDid
+ )
+{
+ UINT8 CpuType;
+ BOOLEAN SkuFound;
+
+ SkuFound = TRUE;
+ CpuType = EnumCpuUnknown;
+
+ switch (CpuFamilyModel) {
+ case CPUID_FULL_FAMILY_MODEL_ALDERLAKE_MOBILE:
+ switch (CpuDid) {
+ case V_SA_DEVICE_ID_MB_ULT_1: // AlderLake P (6+8+GT)
+ case V_SA_DEVICE_ID_MB_ULT_2: // AlderLake P (6+4(f)+GT)
+ case V_SA_DEVICE_ID_MB_ULT_3: // AlderLake P (4(f)+8+GT)
+ case V_SA_DEVICE_ID_MB_ULT_4: // AlderLake P (2(f)+4(f)+GT)
+ case V_SA_DEVICE_ID_MB_ULT_5: // AlderLake P (2+8+GT)
+ case V_SA_DEVICE_ID_MB_ULT_6: // AlderLake P (2+4(f)+GT)
+ case V_SA_DEVICE_ID_MB_ULT_7: // AlderLake P (4+4(f)+GT)
+ case V_SA_DEVICE_ID_MB_ULT_8: // AlderLake P (1+4+GT) SA DID
+ case V_SA_DEVICE_ID_MB_ULT_9: // AlderLake P (1+8+GT) SA DID
+ case V_SA_DEVICE_ID_MB_ULT_10: // AlderLake P (6+6+GT) SA DID
+ CpuType = EnumCpuUlt;
+ break;
+ default:
+ SkuFound = FALSE;
+ break;
+ }
+ break;
+ default:
+ SkuFound = FALSE;
+ break;
+ }
+
+ if (!SkuFound) {
+ DEBUG ((DEBUG_ERROR, "Unsupported CPU SKU, Device ID: 0x%02X, CPUID: 0x%08X!\n", CpuDid, CpuFamilyModel));
+ ASSERT (FALSE);
+ }
+
+ return CpuType;
+}
+
+
+/**
+ This function returns the supported Physical Address Size
+
+ @retval returns the supported Physical Address Size.
+**/
+UINT8
+GetMaxPhysicalAddressSizeFru (
+ VOID
+ )
+{
+ //
+ // Even though CPUID Leaf CPUID_VIR_PHY_ADDRESS_SIZE (0x80000008) MAX_PA will report 46.
+ // For ADL BIOS will return Memory expansion 39 bit (0 - 38) + MKTME (Bits 39-41 must be zero - 3 bit hole in the middle) 42-45 bit is MKTME Keys.
+ //
+ return 39;
+}
+
+
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/LibraryPrivate/BaseCpuInfoFruLib/BaseCpuInfoFruLib.inf b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/LibraryPrivate/BaseCpuInfoFruLib/BaseCpuInfoFruLib.inf
new file mode 100644
index 0000000000..22bcbdf43c
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/LibraryPrivate/BaseCpuInfoFruLib/BaseCpuInfoFruLib.inf
@@ -0,0 +1,29 @@
+## @file
+# This file contains the Cpu Information for specific generation.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+
+[Defines]
+INF_VERSION = 0x00010017
+BASE_NAME = BaseCpuInfoFruLib
+FILE_GUID = 72E44627-C719-4B2D-8C5D-963E167E5AAC
+VERSION_STRING = 1.0
+MODULE_TYPE = BASE
+LIBRARY_CLASS = CpuInfoFruLib
+
+[LibraryClasses]
+BaseLib
+DebugLib
+PchInfoLib
+
+[Packages]
+MdePkg/MdePkg.dec
+UefiCpuPkg/UefiCpuPkg.dec
+AlderlakeSiliconPkg/SiPkg.dec
+
+[Sources]
+BaseCpuInfoFruLib.c
+
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/PeiReportCpuHob/Library/PeiReportCpuHobLib/PeiReportCpuHobLib.c b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/PeiReportCpuHob/Library/PeiReportCpuHobLib/PeiReportCpuHobLib.c
new file mode 100644
index 0000000000..7ea605a05b
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/PeiReportCpuHob/Library/PeiReportCpuHobLib/PeiReportCpuHobLib.c
@@ -0,0 +1,22 @@
+/** @file
+
+ Source code file for Report CPU HOB library.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <Base.h>
+#include <Library/HobLib.h>
+#include <Library/CpuPlatformLib.h>
+
+VOID
+ReportCpuHob (
+ VOID
+ )
+{
+ ///
+ /// Create a CPU hand-off information
+ ///
+ BuildCpuHob (GetMaxPhysicalAddressSize (), 16);
+}
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/PeiReportCpuHob/Library/PeiReportCpuHobLib/PeiReportCpuHobLib.inf b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/PeiReportCpuHob/Library/PeiReportCpuHobLib/PeiReportCpuHobLib.inf
new file mode 100644
index 0000000000..0ba4744eea
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/PeiReportCpuHob/Library/PeiReportCpuHobLib/PeiReportCpuHobLib.inf
@@ -0,0 +1,26 @@
+### @file
+# Component information file for the Report CPU HOB library.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+[Defines]
+ INF_VERSION = 0x00010017
+ BASE_NAME = PeiReportCpuHobLib
+ FILE_GUID = F19AA754-CE24-448D-B755-1F939B00C23D
+ VERSION_STRING = 1.0
+ MODULE_TYPE = PEIM
+ LIBRARY_CLASS = ReportCpuHobLib
+
+[LibraryClasses]
+ BaseLib
+ HobLib
+ CpuPlatformLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ AlderlakeSiliconPkg/SiPkg.dec
+
+[Sources]
+ PeiReportCpuHobLib.c
--
2.36.1.windows.1
-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#108684): https://edk2.groups.io/g/devel/message/108684
Mute This Topic: https://groups.io/mt/101373952/7686176
Group Owner: devel+owner@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [rebecca@openfw.io]
-=-=-=-=-=-=-=-=-=-=-=-
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [edk2-devel] [PATCH v2 09/10] AlderlakeSiliconPkg: Add AdlPch Fru and IncludePrivate modules
2023-09-15 4:45 [edk2-devel] [PATCH v2 01/10] AlderlakeSiliconPkg/IpBlock: Add CpuPcieRp, Espi, Gpio components Saloni Kasbekar
` (6 preceding siblings ...)
2023-09-15 4:45 ` [edk2-devel] [PATCH v2 08/10] AlderlakeSiliconPkg/Fru: Add AdlCpu Fru Saloni Kasbekar
@ 2023-09-15 4:45 ` Saloni Kasbekar
2023-09-15 5:43 ` Chaganty, Rangasai V
2023-09-15 23:57 ` Nate DeSimone
2023-09-15 4:45 ` [edk2-devel] [PATCH v2 10/10] AlderlakeSiliconPkg: Add Alderlake Product and SiPkg.dec Saloni Kasbekar
` (3 subsequent siblings)
11 siblings, 2 replies; 41+ messages in thread
From: Saloni Kasbekar @ 2023-09-15 4:45 UTC (permalink / raw)
To: devel; +Cc: Saloni Kasbekar, Sai Chaganty, Nate DeSimone, Rosen Chuang
Adds the following modules:
- AdlPch/Include
- AdlPch/IncludePrivate
- AdlPch/Library
- AdlPch DSCs
- IncludePrivate
Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Rosen Chuang <rosen.chuang@intel.com>
Signed-off-by: Saloni Kasbekar <saloni.kasbekar@intel.com>
---
.../Fru/AdlPch/CommonLib.dsc | 29 ++
.../AlderlakeSiliconPkg/Fru/AdlPch/Dxe.dsc | 10 +
.../AlderlakeSiliconPkg/Fru/AdlPch/DxeLib.dsc | 7 +
.../Fru/AdlPch/Include/PchBdfAssignment.h | 81 +++++
.../Fru/AdlPch/Include/PchLimits.h | 47 +++
.../Fru/AdlPch/Include/PchPcieRpInfo.h | 17 ++
.../Fru/AdlPch/Include/PchReservedResources.h | 13 +
.../AdlPch/Include/PchReservedResourcesAdpP.h | 36 +++
.../IncludePrivate/Register/PchPcrRegs.h | 59 ++++
.../IncludePrivate/Register/PchRegsLpcAdl.h | 30 ++
.../PeiDxeSmmPchInfoLib/PchInfoLibAdl.c | 223 ++++++++++++++
.../PeiDxeSmmPchInfoLib/PchInfoLibPrivate.h | 44 +++
.../PeiDxeSmmPchInfoLibAdl.inf | 37 +++
.../AlderlakeSiliconPkg/Fru/AdlPch/Pei.dsc | 7 +
.../AlderlakeSiliconPkg/Fru/AdlPch/PeiLib.dsc | 12 +
.../IncludePrivate/RegisterAccess.h | 288 ++++++++++++++++++
16 files changed, 940 insertions(+)
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/CommonLib.dsc
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Dxe.dsc
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/DxeLib.dsc
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Include/PchBdfAssignment.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Include/PchLimits.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Include/PchPcieRpInfo.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Include/PchReservedResources.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Include/PchReservedResourcesAdpP.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/IncludePrivate/Register/PchPcrRegs.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/IncludePrivate/Register/PchRegsLpcAdl.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Library/PeiDxeSmmPchInfoLib/PchInfoLibAdl.c
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Library/PeiDxeSmmPchInfoLib/PchInfoLibPrivate.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Library/PeiDxeSmmPchInfoLib/PeiDxeSmmPchInfoLibAdl.inf
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Pei.dsc
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/PeiLib.dsc
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IncludePrivate/RegisterAccess.h
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/CommonLib.dsc b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/CommonLib.dsc
new file mode 100644
index 0000000000..3f508f83a1
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/CommonLib.dsc
@@ -0,0 +1,29 @@
+## @file
+# Component description file for the AlderLake PCH Common FRU libraries.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+ PchPcrLib|$(PLATFORM_SI_PACKAGE)/IpBlock/P2sb/Library/PeiDxeSmmPchPcrLib/PeiDxeSmmPchPcrLib.inf
+ PchSbiAccessLib|$(PLATFORM_SI_PACKAGE)/IpBlock/P2sb/LibraryPrivate/PeiDxeSmmPchSbiAccessLib/PeiDxeSmmPchSbiAccessLib.inf
+ P2SbSidebandAccessLib|$(PLATFORM_SI_PACKAGE)/IpBlock/P2sb/LibraryPrivate/PeiDxeSmmP2SbSidebandAccessLib/PeiDxeSmmP2SbSidebandAccessLib.inf
+
+ EspiLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Espi/Library/PeiDxeSmmEspiLib/PeiDxeSmmEspiLib.inf
+
+
+ PmcLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Pmc/Library/PeiDxeSmmPmcLib/PeiDxeSmmPmcLib.inf
+ PmcPrivateLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Pmc/LibraryPrivate/PeiDxeSmmPmcPrivateLib/PeiDxeSmmPmcPrivateLib.inf
+ SpiCommonLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Spi/LibraryPrivate/BaseSpiCommonLib/BaseSpiCommonLib.inf
+ GpioLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Gpio/Library/PeiDxeSmmGpioLib/PeiDxeSmmGpioLib.inf
+ PchDmiLib|$(PLATFORM_SI_PACKAGE)/IpBlock/PchDmi/LibraryPrivate/PeiDxeSmmPchDmiLib/PeiDxeSmmPchDmiLib.inf
+
+ GpioPrivateLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Gpio/LibraryPrivate/PeiDxeSmmGpioPrivateLib/PeiDxeSmmGpioPrivateLibVer2.inf
+ PchPcieRpLib|$(PLATFORM_SI_PACKAGE)/IpBlock/PcieRp/Library/PeiDxeSmmPchPcieRpLib/PeiDxeSmmPchPcieRpLibVer2.inf
+
+
+ #
+ # Common FRU Libraries
+ #
+ PchInfoLib|$(PLATFORM_SI_PACKAGE)/Fru/AdlPch/Library/PeiDxeSmmPchInfoLib/PeiDxeSmmPchInfoLibAdl.inf
+
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Dxe.dsc b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Dxe.dsc
new file mode 100644
index 0000000000..b443611d9a
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Dxe.dsc
@@ -0,0 +1,10 @@
+## @file
+# Component description file for the AlderLake PCH DXE FRU drivers.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+ $(PLATFORM_SI_PACKAGE)/IpBlock/Spi/Smm/SpiSmm.inf
+
+
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/DxeLib.dsc b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/DxeLib.dsc
new file mode 100644
index 0000000000..e350b8e643
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/DxeLib.dsc
@@ -0,0 +1,7 @@
+# @file
+# Component description file for the AlderLake PCH DXE FRU libraries.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+ GpioHelpersLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Gpio/LibraryPrivate/BaseGpioHelpersLibNull/BaseGpioHelpersLibNull.inf
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Include/PchBdfAssignment.h b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Include/PchBdfAssignment.h
new file mode 100644
index 0000000000..b8af6d7624
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Include/PchBdfAssignment.h
@@ -0,0 +1,81 @@
+/** @file
+ Header file for AlderLake PCH devices PCI Bus Device Function map.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _PCH_BDF_ASSIGNMENT_H_
+#define _PCH_BDF_ASSIGNMENT_H_
+
+#define NOT_PRESENT 0xFF
+
+//
+// PCH PCIe Controllers
+//
+#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_1 28
+#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_2 28
+#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_3 28
+#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_4 28
+#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_5 28
+#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_6 28
+#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_7 28
+#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_8 28
+#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_9 29
+#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_10 29
+#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_11 29
+#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_12 29
+#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_13 29
+#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_14 29
+#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_15 29
+#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_16 29
+#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_17 27
+#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_18 27
+#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_19 27
+#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_20 27
+#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_21 27
+#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_22 27
+#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_23 27
+#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_24 27
+#ifdef PCH_ADPP
+#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_25 NOT_PRESENT
+#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_26 NOT_PRESENT
+#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_27 NOT_PRESENT
+#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_28 NOT_PRESENT
+#else
+#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_25 26
+#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_26 26
+#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_27 26
+#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_28 26
+#endif
+
+//
+// USB3 (XHCI) Controller PCI config
+//
+#define PCI_DEVICE_NUMBER_PCH_XHCI 20
+#define PCI_FUNCTION_NUMBER_PCH_XHCI 0
+
+
+
+
+//
+// LPC Controller (D31:F0)
+//
+#define PCI_DEVICE_NUMBER_PCH_LPC 31
+#define PCI_FUNCTION_NUMBER_PCH_LPC 0
+
+//
+// Primary to Sideband (P2SB) Bridge (D31:F1)
+//
+#define PCI_DEVICE_NUMBER_PCH_P2SB 31
+#define PCI_FUNCTION_NUMBER_PCH_P2SB 1
+
+
+
+//
+// SPI Controller (D31:F5)
+//
+#define PCI_DEVICE_NUMBER_PCH_SPI 31
+#define PCI_FUNCTION_NUMBER_PCH_SPI 5
+
+
+#endif // _PCH_BDF_ASSIGNMENT_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Include/PchLimits.h b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Include/PchLimits.h
new file mode 100644
index 0000000000..dad3a9a073
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Include/PchLimits.h
@@ -0,0 +1,47 @@
+/** @file
+ Build time limits of PCH resources.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _PCH_LIMITS_H_
+#define _PCH_LIMITS_H_
+/*
+ * Defines povided in this file are indended to be used only where static value
+ * is needed. They are set to values which allow to accomodate multiple projects
+ * needs. Where runtime usage is possible please used dedicated functions from
+ * PchInfoLib to retrieve accurate values
+ */
+
+
+
+//
+// PCIe limits
+//
+#define PCH_MAX_PCIE_ROOT_PORTS 28
+#define PCH_MAX_PCIE_CONTROLLERS 7
+
+//
+// PCIe clocks limits
+//
+#define PCH_MAX_PCIE_CLOCKS 18
+
+//
+// DMI lanes
+//
+#define PCH_MAX_DMI_LANES 8
+
+//
+// SerialIo limits
+//
+#define PCH_MAX_SERIALIO_I2C_CONTROLLERS 8
+#define PCH_MAX_SERIALIO_SPI_CONTROLLERS 7
+#define PCH_MAX_SERIALIO_SPI_CHIP_SELECTS 2
+#define PCH_MAX_SERIALIO_UART_CONTROLLERS 7
+
+//
+// Number of eSPI slaves
+//
+#define PCH_MAX_ESPI_SLAVES 2
+
+#endif // _PCH_LIMITS_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Include/PchPcieRpInfo.h b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Include/PchPcieRpInfo.h
new file mode 100644
index 0000000000..9276b61e1f
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Include/PchPcieRpInfo.h
@@ -0,0 +1,17 @@
+/** @file
+ Pcie Root Port info header
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PCH_PCIERP_INFO_H_
+#define _PCH_PCIERP_INFO_H_
+
+//
+// Number of PCIe ports per PCIe controller
+//
+#define PCH_PCIE_CONTROLLER_PORTS 4u
+
+
+#endif
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Include/PchReservedResources.h b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Include/PchReservedResources.h
new file mode 100644
index 0000000000..f4adfab74f
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Include/PchReservedResources.h
@@ -0,0 +1,13 @@
+/** @file
+ PCH preserved MMIO resource definitions.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PCH_PRESERVED_RESOURCES_H_
+#define _PCH_PRESERVED_RESOURCES_H_
+#include "PchReservedResourcesAdpP.h"
+
+#endif // _PCH_PRESERVED_RESOURCES_H_
+
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Include/PchReservedResourcesAdpP.h b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Include/PchReservedResourcesAdpP.h
new file mode 100644
index 0000000000..69aac29cea
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Include/PchReservedResourcesAdpP.h
@@ -0,0 +1,36 @@
+/** @file
+ PCH preserved MMIO resource definitions.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _PCH_PRESERVED_RESOURCES_ADP_P_H_
+#define _PCH_PRESERVED_RESOURCES_ADP_P_H_
+
+/**
+ Detailed recommended static allocation
+ +-------------------------------------------------------------------------+
+ | PCH preserved MMIO range, 32 MB, from 0xFC800000 to 0xFE7FFFFF |
+ +-------------------------------------------------------------------------+
+ | Size | Start | End | Usage |
+ | 8 MB | 0xFC800000 | 0xFCFFFFFF | TraceHub SW BAR |
+ | 16 MB | 0xFD000000 | 0xFDFFFFFF | SBREG |
+ | 64 KB | 0xFE000000 | 0xFE00FFFF | PMC MBAR |
+ | 4 KB | 0xFE010000 | 0xFE010FFF | SPI BAR0 |
+ | 176 KB | 0xFE020000 | 0xFE04BFFF | SerialIo BAR in ACPI mode |
+ | 400 KB | 0xFE04C000 | 0xFE0AFFFF | Unused |
+ | 64 KB | 0xFE0B0000 | 0xFE0BFFFF | eSPI LGMR BAR |
+ | 64 KB | 0xFE0C0000 | 0xFE0CFFFF | eSPI2 SEGMR BAR |
+ | 192 KB | 0xFE0D0000 | 0xFE0FFFFF | Unused |
+ | 1 MB | 0xFE100000 | 0xFE1FFFFF | TraceHub MTB BAR |
+ | 2 MB | 0xFE200000 | 0xFE3FFFFF | TraceHub FW BAR |
+ | 2 MB | 0xFE400000 | 0xFE5FFFFF | Unused |
+ | 2 MB | 0xFE600000 | 0xFE7FFFFF | Temp address |
+ +-------------------------------------------------------------------------+
+**/
+#define PCH_PCR_BASE_ADDRESS 0xFD000000 ///< SBREG MMIO base address
+#define PCH_PWRM_BASE_ADDRESS 0xFE000000 ///< PMC MBAR MMIO base address
+#define PCH_SPI_BASE_ADDRESS 0xFE010000 ///< SPI BAR0 MMIO base address
+
+#endif // _PCH_PRESERVED_RESOURCES_ADP_P_H_
+
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/IncludePrivate/Register/PchPcrRegs.h b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/IncludePrivate/Register/PchPcrRegs.h
new file mode 100644
index 0000000000..fe548dae4b
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/IncludePrivate/Register/PchPcrRegs.h
@@ -0,0 +1,59 @@
+/** @file
+ Register names for PCH private chipset register
+
+Conventions:
+
+ - Register definition format:
+ Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_RegisterName
+ - Prefix:
+ Definitions beginning with "R_" are registers
+ Definitions beginning with "B_" are bits within registers
+ Definitions beginning with "V_" are meaningful values within the bits
+ Definitions beginning with "S_" are register size
+ Definitions beginning with "N_" are the bit position
+ - [GenerationName]:
+ Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc.).
+ Register name without GenerationName applies to all generations.
+ - [ComponentName]:
+ This field indicates the component name that the register belongs to (e.g. PCH, SA etc.)
+ Register name without ComponentName applies to all components.
+ Register that is specific to -H denoted by "_PCH_H_" in component name.
+ Register that is specific to -LP denoted by "_PCH_LP_" in component name.
+ - SubsystemName:
+ This field indicates the subsystem name of the component that the register belongs to
+ (e.g. PCIE, USB, SATA, GPIO, PMC etc.).
+ - RegisterSpace:
+ MEM - MMIO space register of subsystem.
+ IO - IO space register of subsystem.
+ PCR - Private configuration register of subsystem.
+ CFG - PCI configuration space register of subsystem.
+ - RegisterName:
+ Full register name.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PCH_REGS_PCR_H_
+#define _PCH_REGS_PCR_H_
+
+
+/**
+ Definition for SBI PID
+ The PCH_SBI_PID defines the PID for PCR MMIO programming and PCH SBI programming as well.
+**/
+#define PID_DMI 0x88
+#define PID_ESPISPI 0x72
+#define PID_SPF 0x85
+#define PID_SPE 0x84
+#define PID_SPD 0x83
+#define PID_SPC 0x82
+#define PID_SPB 0x81
+#define PID_SPA 0x80
+#define PID_GPIOCOM0 0x6E
+#define PID_GPIOCOM1 0x6D
+#define PID_GPIOCOM2 0x6C
+#define PID_GPIOCOM4 0x6A
+#define PID_GPIOCOM5 0x69
+
+#endif
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/IncludePrivate/Register/PchRegsLpcAdl.h b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/IncludePrivate/Register/PchRegsLpcAdl.h
new file mode 100644
index 0000000000..8b1a01036e
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/IncludePrivate/Register/PchRegsLpcAdl.h
@@ -0,0 +1,30 @@
+/** @file
+ Register names for ADL PCH LPC/eSPI device
+
+ Conventions:
+
+ - Prefixes:
+ Definitions beginning with "R_" are registers
+ Definitions beginning with "B_" are bits within registers
+ Definitions beginning with "V_" are meaningful values within the bits
+ Definitions beginning with "S_" are register sizes
+ Definitions beginning with "N_" are the bit position
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _PCH_REGS_LPC_ADL_H_
+#define _PCH_REGS_LPC_ADL_H_
+
+//
+// ADL PCH-P/M LPC Device IDs
+//
+#define V_ADL_PCH_P_LPC_CFG_DEVICE_ID_MB_0 0x5180 ///< LPC/eSPI Controller
+#define V_ADL_PCH_P_LPC_CFG_DEVICE_ID_MB_1 0x5181 ///< LPC/eSPI Controller P SuperSKU
+#define V_ADL_PCH_P_LPC_CFG_DEVICE_ID_MB_2 0x5182 ///< LPC/eSPI Controller P Premium
+#define V_ADL_PCH_P_LPC_CFG_DEVICE_ID_MB_3 0x5183 ///< LPC/eSPI Controller Placeholder
+#define V_ADL_PCH_P_LPC_CFG_DEVICE_ID_MB_4 0x5184 ///< LPC/eSPI Controller
+#define V_ADL_PCH_P_LPC_CFG_DEVICE_ID_MB_5 0x5185 ///< LPC/eSPI Controller
+
+
+#endif
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Library/PeiDxeSmmPchInfoLib/PchInfoLibAdl.c b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Library/PeiDxeSmmPchInfoLib/PchInfoLibAdl.c
new file mode 100644
index 0000000000..c74d665533
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Library/PeiDxeSmmPchInfoLib/PchInfoLibAdl.c
@@ -0,0 +1,223 @@
+/** @file
+ Pch information library for ADL.
+
+ All function in this library is available for PEI, DXE, and SMM,
+ But do not support UEFI RUNTIME environment call.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#include <Base.h>
+#include <PchPcieRpInfo.h>
+#include <Uefi/UefiBaseType.h>
+#include <Library/PchInfoLib.h>
+#include <Library/PmcPrivateLib.h>
+#include <Library/PrintLib.h>
+#include <Library/IoLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseLib.h>
+#include <Library/PciSegmentLib.h>
+#include <Library/PcdLib.h>
+#include <Library/PchPciBdfLib.h>
+#include <Register/PchRegsLpcAdl.h>
+#include <Register/PchRegs.h>
+#include <Register/PchRegsLpc.h>
+#include <IndustryStandard/Pci30.h>
+#include "PchInfoLibPrivate.h"
+
+
+/**
+ Return LPC Device Id
+
+ @retval PCH_LPC_DEVICE_ID PCH Lpc Device ID
+**/
+UINT16
+PchGetLpcDid (
+ VOID
+ )
+{
+ UINT64 LpcBaseAddress;
+
+ LpcBaseAddress = LpcPciCfgBase ();
+
+ return PciSegmentRead16 (LpcBaseAddress + PCI_DEVICE_ID_OFFSET);
+}
+
+/**
+ Return Pch Series
+
+ @retval PCH_SERIES Pch Series
+**/
+PCH_SERIES
+PchSeries (
+ VOID
+ )
+{
+ PCH_SERIES PchSer;
+ static PCH_SERIES PchSeries = PCH_UNKNOWN_SERIES;
+
+ if (PchSeries != PCH_UNKNOWN_SERIES) {
+ return PchSeries;
+ }
+
+ PchSer = PchSeriesFromLpcDid (PchGetLpcDid ());
+
+ PchSeries = PchSer;
+
+ return PchSer;
+}
+
+/**
+ Return Pch stepping type
+
+ @retval PCH_STEPPING Pch stepping type
+**/
+PCH_STEPPING
+PchStepping (
+ VOID
+ )
+{
+ UINT8 RevId;
+ UINT64 LpcBaseAddress;
+ static PCH_STEPPING PchStepping = PCH_STEPPING_MAX;
+
+ if (PchStepping != PCH_STEPPING_MAX) {
+ return PchStepping;
+ }
+
+ LpcBaseAddress = LpcPciCfgBase ();
+ RevId = PciSegmentRead8 (LpcBaseAddress + PCI_REVISION_ID_OFFSET);
+
+ RevId = PchSteppingFromRevId (RevId);
+
+ PchStepping = RevId;
+
+ return RevId;
+}
+
+/**
+ Check if this is PCH P series
+
+ @retval TRUE It's PCH P series
+ @retval FALSE It's not PCH P series
+**/
+BOOLEAN
+IsPchP (
+ VOID
+ )
+{
+ return (PchSeries () == PCH_P);
+}
+
+/**
+ return support status for P2SB PCR 20-bit addressing
+
+ @retval TRUE
+ @retval FALSE
+**/
+BOOLEAN
+IsP2sb20bPcrSupported (
+ VOID
+ )
+{
+ return FALSE;
+}
+
+/**
+ Determine Pch Series based on Device Id
+
+ @param[in] LpcDeviceId Lpc Device Id
+
+ @retval PCH_SERIES Pch Series
+**/
+PCH_SERIES
+PchSeriesFromLpcDid (
+ IN UINT16 LpcDeviceId
+ )
+{
+ return PCH_P;
+}
+
+/**
+ Determine Pch Stepping based on Revision ID
+
+ @param[in] RevId Pch Revision Id
+
+ @retval PCH_STEPPING Pch Stepping
+**/
+PCH_STEPPING
+PchSteppingFromRevId (
+ IN UINT8 RevId
+ )
+{
+ return RevId;
+}
+
+
+/**
+ Check if this is PCH LP series
+
+ @retval TRUE It's PCH LP series
+ @retval FALSE It's not PCH LP series
+**/
+BOOLEAN
+IsPchLp (
+ VOID
+ )
+{
+ return (PchSeries () == PCH_LP || PchSeries () == PCH_P || PchSeries () == PCH_M || PchSeries () == PCH_N );
+}
+/**
+ Get RST mode supported by the silicon
+
+ @retval RST_MODE RST mode supported by silicon
+**/
+
+GLOBAL_REMOVE_IF_UNREFERENCED
+struct PCH_SKU_STRING mSkuStrs[] = {
+ //
+ // ADL PCH LPC Device IDs
+ //
+ {V_ADL_PCH_P_LPC_CFG_DEVICE_ID_MB_0, "ADL SKU 0"},
+ {V_ADL_PCH_P_LPC_CFG_DEVICE_ID_MB_1, "P Super SKU (SSKU)"},
+ {V_ADL_PCH_P_LPC_CFG_DEVICE_ID_MB_2, "P Premium"},
+ {V_ADL_PCH_P_LPC_CFG_DEVICE_ID_MB_3, "ADL No UFS"},
+ {V_ADL_PCH_P_LPC_CFG_DEVICE_ID_MB_4, "ADL SKU 4"},
+ {V_ADL_PCH_P_LPC_CFG_DEVICE_ID_MB_5, "ADL SKU 5"},
+
+ {0xFFFF, NULL}
+};
+
+/**
+ Get Pch Maximum Pcie Root Port Number
+
+ @retval Pch Maximum Pcie Root Port Number
+**/
+UINT8
+GetPchMaxPciePortNum (
+ VOID
+ )
+{
+ switch (PchSeries ()) {
+ case PCH_P:
+ case PCH_N:
+ return 12;
+ case PCH_S:
+ return 28;
+ default:
+ return 0;
+ }
+}
+
+/**
+ Get Pch Maximum Serial IO I2C controllers number
+
+ @retval Pch Maximum Serial IO I2C controllers number
+**/
+UINT8
+GetPchMaxSerialIoI2cControllersNum (
+ VOID
+ )
+{
+ return 8;
+}
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Library/PeiDxeSmmPchInfoLib/PchInfoLibPrivate.h b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Library/PeiDxeSmmPchInfoLib/PchInfoLibPrivate.h
new file mode 100644
index 0000000000..a4bd4d5aa7
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Library/PeiDxeSmmPchInfoLib/PchInfoLibPrivate.h
@@ -0,0 +1,44 @@
+/** @file
+ Private header for PCH Info Lib.
+
+ All function in this library is available for PEI, DXE, and SMM,
+ But do not support UEFI RUNTIME environment call.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+/**
+ Structure for PCH SKU string mapping
+**/
+struct PCH_SKU_STRING {
+ UINT16 Id;
+ CHAR8 *String;
+};
+
+extern struct PCH_SKU_STRING mSkuStrs[];
+
+/**
+ Determine Pch Series based on Device Id
+
+ @param[in] LpcDeviceId Lpc Device Id
+
+ @retval PCH_SERIES Pch Series
+**/
+PCH_SERIES
+PchSeriesFromLpcDid (
+ IN UINT16 LpcDeviceId
+ );
+
+/**
+ Determine Pch Stepping based on Revision ID
+
+ @param[in] RevId Pch Revision Id
+
+ @retval PCH_STEPPING Pch Stepping
+**/
+PCH_STEPPING
+PchSteppingFromRevId (
+ IN UINT8 RevId
+ );
+
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Library/PeiDxeSmmPchInfoLib/PeiDxeSmmPchInfoLibAdl.inf b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Library/PeiDxeSmmPchInfoLib/PeiDxeSmmPchInfoLibAdl.inf
new file mode 100644
index 0000000000..28a6863aed
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Library/PeiDxeSmmPchInfoLib/PeiDxeSmmPchInfoLibAdl.inf
@@ -0,0 +1,37 @@
+## @file
+# PCH information library for Alderlake PCH.
+#
+# All function in this library is available for PEI, DXE, and SMM,
+# But do not support UEFI RUNTIME environment call.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+
+[Defines]
+INF_VERSION = 0x00010017
+BASE_NAME = PeiDxeSmmPchInfoLibAdl
+FILE_GUID = F5B0CBB7-4AFC-4535-A5EC-D9ECEDA24DC5
+VERSION_STRING = 1.0
+MODULE_TYPE = BASE
+LIBRARY_CLASS = PchInfoLib
+
+
+[LibraryClasses]
+BaseLib
+IoLib
+DebugLib
+PrintLib
+PciSegmentLib
+PmcPrivateLib
+PcdLib
+
+
+[Packages]
+MdePkg/MdePkg.dec
+AlderlakeSiliconPkg/SiPkg.dec
+
+
+[Sources]
+PchInfoLibAdl.c
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Pei.dsc b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Pei.dsc
new file mode 100644
index 0000000000..8a923554dd
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Pei.dsc
@@ -0,0 +1,7 @@
+## @file
+# Component description file for the AlderLake PCH PEI FRU drivers.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/PeiLib.dsc b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/PeiLib.dsc
new file mode 100644
index 0000000000..ebe2bbfda0
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/PeiLib.dsc
@@ -0,0 +1,12 @@
+## @file
+# Component description file for the AlderLake PCH PEI FRU libraries.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+ SpiLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Spi/Library/PeiSpiLib/PeiSpiLib.inf
+
+ GpioHelpersLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Gpio/LibraryPrivate/PeiGpioHelpersLib/PeiGpioHelpersLib.inf
+
+
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IncludePrivate/RegisterAccess.h b/Silicon/Intel/AlderlakeSiliconPkg/IncludePrivate/RegisterAccess.h
new file mode 100644
index 0000000000..25a0ba49d2
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IncludePrivate/RegisterAccess.h
@@ -0,0 +1,288 @@
+/** @file
+ Header file for register access.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _REGISTER_ACCESS_H_
+#define _REGISTER_ACCESS_H_
+
+typedef struct _REGISTER_ACCESS REGISTER_ACCESS;
+
+/**
+ Reads an 8-bit register
+
+ @param[in] This Pointer to REGISTER_ACCESS
+ @param[in] Offset Offset of the register in the register bank
+
+ @return The 8-bit register value specified by Offset
+**/
+typedef
+UINT8
+(*REG_READ8) (
+ IN REGISTER_ACCESS *This,
+ IN UINT32 Offset
+ );
+
+/**
+ Writes an 8-bit register
+
+ @param[in] This Pointer to REGISTER_ACCESS
+ @param[in] Offset Offset of the register in the register bank
+ @param[in] Value Value to write to register
+
+ @return The 8-bit register value written to register
+**/
+typedef
+UINT8
+(*REG_WRITE8) (
+ IN REGISTER_ACCESS *This,
+ IN UINT32 Offset,
+ IN UINT8 Value
+ );
+
+/**
+ Performs an 8-bit or on the register
+
+ @param[in] This Pointer to REGISTER_ACCESS
+ @param[in] Offset Offset of the register in the register bank
+ @param[in] OrData Data with which register should be OR-ed
+
+ @return The 8-bit register value written to register
+**/
+typedef
+UINT8
+(*REG_OR8) (
+ IN REGISTER_ACCESS *This,
+ IN UINT32 Offset,
+ IN UINT8 OrData
+ );
+
+/**
+ Performs an 8-bit and on the register
+
+ @param[in] This Pointer to REGISTER_ACCESS
+ @param[in] Offset Offset of the register in the register bank
+ @param[in] AndData Data with which register should be AND-ed
+
+ @return The 8-bit register value written to register
+**/
+typedef
+UINT8
+(*REG_AND8) (
+ IN REGISTER_ACCESS *This,
+ IN UINT32 Offset,
+ IN UINT8 AndData
+ );
+
+/**
+ Performs an 8-bit and then or on the register
+
+ @param[in] This Pointer to REGISTER_ACCESS
+ @param[in] Offset Offset of the register in the register bank
+ @param[in] AndData Data with which register should be AND-ed
+ @param[in] OrData Data with which register should be OR-ed
+
+ @return The 8-bit register value written to register
+**/
+typedef
+UINT8
+(*REG_AND_THEN_OR8) (
+ IN REGISTER_ACCESS *This,
+ IN UINT32 Offset,
+ IN UINT8 AndData,
+ IN UINT8 OrData
+ );
+
+/**
+ Reads a 16-bit register
+
+ @param[in] This Pointer to REGISTER_ACCESS
+ @param[in] Offset Offset of the register in the register bank
+
+ @return The 16-bit register value specified by Offset
+**/
+typedef
+UINT16
+(*REG_READ16) (
+ IN REGISTER_ACCESS *This,
+ IN UINT32 Offset
+ );
+
+/**
+ Writes a 16-bit register
+
+ @param[in] This Pointer to REGISTER_ACCESS
+ @param[in] Offset Offset of the register in the register bank
+ @param[in] Value Value to write to register
+
+ @return The 16-bit register value written to register
+**/
+typedef
+UINT16
+(*REG_WRITE16) (
+ IN REGISTER_ACCESS *This,
+ IN UINT32 Offset,
+ IN UINT16 Value
+ );
+
+/**
+ Performs a 16-bit or on the register
+
+ @param[in] This Pointer to REGISTER_ACCESS
+ @param[in] Offset Offset of the register in the register bank
+ @param[in] OrData Data with which register should be OR-ed
+
+ @return The 16-bit register value written to register
+**/
+typedef
+UINT16
+(*REG_OR16) (
+ IN REGISTER_ACCESS *This,
+ IN UINT32 Offset,
+ IN UINT16 OrData
+ );
+
+/**
+ Performs a 16-bit and on the register
+
+ @param[in] This Pointer to REGISTER_ACCESS
+ @param[in] Offset Offset of the register in the register bank
+ @param[in] AndData Data with which register should be AND-ed
+
+ @return The 16-bit register value written to register
+**/
+typedef
+UINT16
+(*REG_AND16) (
+ IN REGISTER_ACCESS *This,
+ IN UINT32 Offset,
+ IN UINT16 AndData
+ );
+
+/**
+ Performs a 16-bit and then or on the register
+
+ @param[in] This Pointer to REGISTER_ACCESS
+ @param[in] Offset Offset of the register in the register bank
+ @param[in] AndData Data with which register should be AND-ed
+ @param[in] OrData Data with which register should be OR-ed
+
+ @return The 16-bit register value written to register
+**/
+typedef
+UINT16
+(*REG_AND_THEN_OR16) (
+ IN REGISTER_ACCESS *This,
+ IN UINT32 Offset,
+ IN UINT16 AndData,
+ IN UINT16 OrData
+ );
+
+/**
+ Reads a 32-bit register
+
+ @param[in] This Pointer to REGISTER_ACCESS
+ @param[in] Offset Offset of the register in the register bank
+
+ @return The 32-bit register value specified by Offset
+**/
+typedef
+UINT32
+(*REG_READ32) (
+ IN REGISTER_ACCESS *This,
+ IN UINT32 Offset
+ );
+
+/**
+ Writes a 32-bit register
+
+ @param[in] This Pointer to REGISTER_ACCESS
+ @param[in] Offset Offset of the register in the register bank
+ @param[in] Value Value to write to register
+
+ @return The 32-bit register value written to register
+**/
+typedef
+UINT32
+(*REG_WRITE32) (
+ IN REGISTER_ACCESS *This,
+ IN UINT32 Offset,
+ IN UINT32 Value
+ );
+
+/**
+ Performs a 32-bit or on the register
+
+ @param[in] This Pointer to REGISTER_ACCESS
+ @param[in] Offset Offset of the register in the register bank
+ @param[in] OrData Data with which register should be OR-ed
+
+ @return The 32-bit register value written to register
+**/
+typedef
+UINT32
+(*REG_OR32) (
+ IN REGISTER_ACCESS *This,
+ IN UINT32 Offset,
+ IN UINT32 OrData
+ );
+
+/**
+ Performs a 32-bit and on the register
+
+ @param[in] This Pointer to REGISTER_ACCESS
+ @param[in] Offset Offset of the register in the register bank
+ @param[in] AndData Data with which register should be AND-ed
+
+ @return The 32-bit register value written to register
+**/
+typedef
+UINT32
+(*REG_AND32) (
+ IN REGISTER_ACCESS *This,
+ IN UINT32 Offset,
+ IN UINT32 AndData
+ );
+
+/**
+ Performs a 32-bit and then or on the register
+
+ @param[in] This Pointer to REGISTER_ACCESS
+ @param[in] Offset Offset of the register in the register bank
+ @param[in] AndData Data with which register should be AND-ed
+ @param[in] OrData Data with which register should be OR-ed
+
+ @return The 32-bit register value written to register
+**/
+typedef
+UINT32
+(*REG_AND_THEN_OR32) (
+ IN REGISTER_ACCESS *This,
+ IN UINT32 Offset,
+ IN UINT32 AndData,
+ IN UINT32 OrData
+ );
+
+struct _REGISTER_ACCESS {
+ REG_READ8 Read8;
+ REG_WRITE8 Write8;
+ REG_OR8 Or8;
+ REG_AND8 And8;
+ REG_AND_THEN_OR8 AndThenOr8;
+
+ REG_READ16 Read16;
+ REG_WRITE16 Write16;
+ REG_OR16 Or16;
+ REG_AND16 And16;
+ REG_AND_THEN_OR16 AndThenOr16;
+
+ REG_READ32 Read32;
+ REG_WRITE32 Write32;
+ REG_OR32 Or32;
+ REG_AND32 And32;
+ REG_AND_THEN_OR32 AndThenOr32;
+};
+
+#endif
--
2.36.1.windows.1
-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#108685): https://edk2.groups.io/g/devel/message/108685
Mute This Topic: https://groups.io/mt/101373953/7686176
Group Owner: devel+owner@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [rebecca@openfw.io]
-=-=-=-=-=-=-=-=-=-=-=-
^ permalink raw reply related [flat|nested] 41+ messages in thread
* [edk2-devel] [PATCH v2 10/10] AlderlakeSiliconPkg: Add Alderlake Product and SiPkg.dec
2023-09-15 4:45 [edk2-devel] [PATCH v2 01/10] AlderlakeSiliconPkg/IpBlock: Add CpuPcieRp, Espi, Gpio components Saloni Kasbekar
` (7 preceding siblings ...)
2023-09-15 4:45 ` [edk2-devel] [PATCH v2 09/10] AlderlakeSiliconPkg: Add AdlPch Fru and IncludePrivate modules Saloni Kasbekar
@ 2023-09-15 4:45 ` Saloni Kasbekar
2023-09-15 5:43 ` Chaganty, Rangasai V
2023-09-15 23:57 ` Nate DeSimone
2023-09-15 5:42 ` [edk2-devel] [PATCH v2 01/10] AlderlakeSiliconPkg/IpBlock: Add CpuPcieRp, Espi, Gpio components Chaganty, Rangasai V
` (2 subsequent siblings)
11 siblings, 2 replies; 41+ messages in thread
From: Saloni Kasbekar @ 2023-09-15 4:45 UTC (permalink / raw)
To: devel; +Cc: Saloni Kasbekar, Sai Chaganty, Nate DeSimone, Rosen Chuang
Adds the following modules:
- Product/Alderlake/Include
- Product/Alderlake/Library
- Product/Alderlake DSCs
- SiPkg.dec
Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Rosen Chuang <rosen.chuang@intel.com>
Signed-off-by: Saloni Kasbekar <saloni.kasbekar@intel.com>
---
.../Product/Alderlake/Include/Ppi/SiPolicy.h | 55 ++
.../Library/PeiSiPolicyLib/PeiSiPolicyLib.c | 47 ++
.../Library/PeiSiPolicyLib/PeiSiPolicyLib.inf | 47 ++
.../PeiSiPolicyLib/PeiSiPolicyLibPreMem.c | 47 ++
.../PeiSiPolicyLib/PeiSiPolicyLibrary.h | 21 +
.../Product/Alderlake/SiPkgBuildOption.dsc | 122 ++++
.../Product/Alderlake/SiPkgCommonLib.dsc | 36 +
.../Product/Alderlake/SiPkgDxe.dsc | 32 +
.../Product/Alderlake/SiPkgDxeLib.dsc | 23 +
.../Product/Alderlake/SiPkgPeiLib.dsc | 19 +
Silicon/Intel/AlderlakeSiliconPkg/SiPkg.dec | 625 ++++++++++++++++++
11 files changed, 1074 insertions(+)
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/Include/Ppi/SiPolicy.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/Library/PeiSiPolicyLib/PeiSiPolicyLib.c
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/Library/PeiSiPolicyLib/PeiSiPolicyLib.inf
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/Library/PeiSiPolicyLib/PeiSiPolicyLibPreMem.c
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/Library/PeiSiPolicyLib/PeiSiPolicyLibrary.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/SiPkgBuildOption.dsc
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/SiPkgCommonLib.dsc
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/SiPkgDxe.dsc
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/SiPkgDxeLib.dsc
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/SiPkgPeiLib.dsc
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/SiPkg.dec
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/Include/Ppi/SiPolicy.h b/Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/Include/Ppi/SiPolicy.h
new file mode 100644
index 0000000000..703f0221bd
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/Include/Ppi/SiPolicy.h
@@ -0,0 +1,55 @@
+/** @file
+ Silicon Policy PPI is used for specifying platform
+ related Intel silicon information and policy setting.
+ This PPI is consumed by the silicon PEI modules and carried
+ over to silicon DXE modules.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _SI_POLICY_PPI_H_
+#define _SI_POLICY_PPI_H_
+
+#include <SiPolicyStruct.h>
+#include <PchPolicyCommon.h>
+#include <PchPreMemPolicyCommon.h>
+#include <Uefi.h>
+#include <ConfigBlock/CpuConfig.h>
+#include <ConfigBlock/CpuConfigLibPreMemConfig.h>
+#include <ConfigBlock/CpuSecurityPreMemConfig.h>
+
+#ifndef DISABLED
+#define DISABLED 0
+#endif
+#ifndef ENABLED
+#define ENABLED 1
+#endif
+
+extern EFI_GUID gSiPreMemPolicyPpiGuid;
+extern EFI_GUID gSiPolicyPpiGuid;
+
+
+#include <GraphicsConfig.h>
+
+
+#include <CpuPcieConfigGen3.h>
+#include <CpuPcieConfig.h>
+extern EFI_GUID gCpuPciePeiPreMemConfigGuid;
+extern EFI_GUID gCpuPcieRpConfigGuid;
+
+#include <MemoryConfig.h>
+extern EFI_GUID gMemoryConfigGuid;
+extern EFI_GUID gMemoryConfigNoCrcGuid;
+
+#include <ConfigBlock/SaMiscPeiPreMemConfig.h>
+extern EFI_GUID gSaMiscPeiPreMemConfigGuid;
+
+#include <HostBridgeConfig.h>
+extern EFI_GUID gHostBridgePeiPreMemConfigGuid;
+extern EFI_GUID gHostBridgePeiConfigGuid;
+
+typedef struct _SI_PREMEM_POLICY_STRUCT SI_PREMEM_POLICY_PPI;
+typedef struct _SI_POLICY_STRUCT SI_POLICY_PPI;
+
+#endif // _SI_POLICY_PPI_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/Library/PeiSiPolicyLib/PeiSiPolicyLib.c b/Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/Library/PeiSiPolicyLib/PeiSiPolicyLib.c
new file mode 100644
index 0000000000..886415bdaa
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/Library/PeiSiPolicyLib/PeiSiPolicyLib.c
@@ -0,0 +1,47 @@
+/** @file
+ This file is PeiSiPolicyLib library creates default settings of RC
+ Policy and installs RC Policy PPI.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#include "PeiSiPolicyLibrary.h"
+#include <Library/PcdLib.h>
+#include <Library/PchInfoLib.h>
+
+
+/**
+ SiInstallPolicyReadyPpi installs SiPolicyReadyPpi.
+ While installed, RC assumes the Policy is ready and finalized. So please update and override
+ any setting before calling this function.
+
+ @retval EFI_SUCCESS The policy is installed.
+ @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer
+**/
+EFI_STATUS
+EFIAPI
+SiInstallPolicyReadyPpi (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+ EFI_PEI_PPI_DESCRIPTOR *SiPolicyReadyPpiDesc;
+
+ SiPolicyReadyPpiDesc = (EFI_PEI_PPI_DESCRIPTOR *) AllocateZeroPool (sizeof (EFI_PEI_PPI_DESCRIPTOR));
+ if (SiPolicyReadyPpiDesc == NULL) {
+ ASSERT (FALSE);
+ return EFI_OUT_OF_RESOURCES;
+ }
+
+ SiPolicyReadyPpiDesc->Flags = EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST;
+ SiPolicyReadyPpiDesc->Guid = &gSiPolicyReadyPpiGuid;
+ SiPolicyReadyPpiDesc->Ppi = NULL;
+
+ //
+ // Install Silicon Policy Ready PPI
+ //
+ Status = PeiServicesInstallPpi (SiPolicyReadyPpiDesc);
+ ASSERT_EFI_ERROR (Status);
+ return Status;
+}
+
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/Library/PeiSiPolicyLib/PeiSiPolicyLib.inf b/Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/Library/PeiSiPolicyLib/PeiSiPolicyLib.inf
new file mode 100644
index 0000000000..7dab1ff510
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/Library/PeiSiPolicyLib/PeiSiPolicyLib.inf
@@ -0,0 +1,47 @@
+## @file
+# Component description file for the PeiSiPolicyLib library.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+
+[Defines]
+INF_VERSION = 0x00010017
+BASE_NAME = PeiSiPolicyLib
+FILE_GUID = 97584FAE-9299-4202-9889-2D339E4BFA5B
+VERSION_STRING = 1.0
+MODULE_TYPE = PEIM
+LIBRARY_CLASS = SiPolicyLib
+
+
+[LibraryClasses]
+DebugLib
+IoLib
+PeiServicesLib
+BaseMemoryLib
+MemoryAllocationLib
+ConfigBlockLib
+PcdLib
+CpuPlatformLib
+
+[Packages]
+MdePkg/MdePkg.dec
+AlderlakeSiliconPkg/SiPkg.dec
+
+[Sources]
+PeiSiPolicyLib.c
+PeiSiPolicyLibrary.h
+PeiSiPolicyLibPreMem.c
+
+
+[Guids]
+gSiConfigGuid ## CONSUMES
+gSiPreMemConfigGuid ## CONSUMES
+gPciePreMemConfigGuid ## CONSUMES
+
+[Ppis]
+gSiPolicyPpiGuid ## PRODUCES
+gSiPreMemPolicyPpiGuid ## PRODUCES
+gSiPolicyReadyPpiGuid ## CONSUMES
+gSiPreMemPolicyReadyPpiGuid ## CONSUMES
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/Library/PeiSiPolicyLib/PeiSiPolicyLibPreMem.c b/Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/Library/PeiSiPolicyLib/PeiSiPolicyLibPreMem.c
new file mode 100644
index 0000000000..93bffac2b0
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/Library/PeiSiPolicyLib/PeiSiPolicyLibPreMem.c
@@ -0,0 +1,47 @@
+/** @file
+ This file is PeiSiPolicyLib library creates default settings of RC
+ Policy and installs RC Policy PPI.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#include "PeiSiPolicyLibrary.h"
+#include <Base.h>
+#include <PciePreMemConfig.h>
+#include <Library/PchInfoLib.h>
+#include <Library/CpuPlatformLib.h>
+
+/**
+ SiPreMemInstallPolicyReadyPpi installs SiPreMemPolicyReadyPpi.
+ While installed, RC assumes the Policy is ready and finalized. So please update and override
+ any setting before calling this function.
+
+ @retval EFI_SUCCESS The policy is installed.
+ @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer
+**/
+EFI_STATUS
+EFIAPI
+SiPreMemInstallPolicyReadyPpi (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+ EFI_PEI_PPI_DESCRIPTOR *SiPolicyReadyPreMemPpiDesc;
+
+ SiPolicyReadyPreMemPpiDesc = (EFI_PEI_PPI_DESCRIPTOR *) AllocateZeroPool (sizeof (EFI_PEI_PPI_DESCRIPTOR));
+ if (SiPolicyReadyPreMemPpiDesc == NULL) {
+ ASSERT (FALSE);
+ return EFI_OUT_OF_RESOURCES;
+ }
+
+ SiPolicyReadyPreMemPpiDesc->Flags = EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST;
+ SiPolicyReadyPreMemPpiDesc->Guid = &gSiPreMemPolicyReadyPpiGuid;
+ SiPolicyReadyPreMemPpiDesc->Ppi = NULL;
+
+ //
+ // Install PreMem Silicon Policy Ready PPI
+ //
+ Status = PeiServicesInstallPpi (SiPolicyReadyPreMemPpiDesc);
+ ASSERT_EFI_ERROR (Status);
+ return Status;
+}
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/Library/PeiSiPolicyLib/PeiSiPolicyLibrary.h b/Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/Library/PeiSiPolicyLib/PeiSiPolicyLibrary.h
new file mode 100644
index 0000000000..aac24cf187
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/Library/PeiSiPolicyLib/PeiSiPolicyLibrary.h
@@ -0,0 +1,21 @@
+/** @file
+ Header file for the PeiSiPolicyLib library.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _PEI_SI_POLICY_LIBRARY_H_
+#define _PEI_SI_POLICY_LIBRARY_H_
+
+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/PeiServicesLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/ConfigBlockLib.h>
+#include <Ppi/SiPolicy.h>
+#include <Library/SiPolicyLib.h>
+
+
+
+#endif // _PEI_SI_POLICY_LIBRARY_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/SiPkgBuildOption.dsc b/Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/SiPkgBuildOption.dsc
new file mode 100644
index 0000000000..290d6eb885
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/SiPkgBuildOption.dsc
@@ -0,0 +1,122 @@
+## @file
+# Silicon build option configuration file.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+[BuildOptions]
+# Define Build Options both for EDK and EDKII drivers.
+
+# SA
+!if gSiPkgTokenSpaceGuid.PcdAdlLpSupport == TRUE
+DEFINE PCH_BUILD_OPTIONS = -DPCH_ADPP
+!else
+DEFINE PCH_BUILD_OPTIONS = -DPCH_ADL
+!endif
+#
+# SA
+#
+!if gSiPkgTokenSpaceGuid.PcdBdatEnable == TRUE
+ DEFINE BDAT_BUILD_OPTION = -DBDAT_SUPPORT=1
+!else
+ DEFINE BDAT_BUILD_OPTION =
+!endif
+
+ DEFINE SLE_BUILD_OPTIONS =
+!if $(TARGET) == RELEASE
+!if gSiPkgTokenSpaceGuid.PcdSiCatalogDebugEnable == TRUE
+ DEFINE DEBUG_BUILD_OPTIONS =
+!else
+ # MDEPKG_NDEBUG is introduced for the intention
+ # of size reduction when compiler optimization is disabled. If MDEPKG_NDEBUG is
+ # defined, then debug and assert related macros wrapped by it are the NULL implementations.
+ DEFINE DEBUG_BUILD_OPTIONS = -DMDEPKG_NDEBUG
+!endif
+!else
+ DEFINE DEBUG_BUILD_OPTIONS =
+!endif
+
+!if ($(TARGET) == RELEASE) AND (gSiPkgTokenSpaceGuid.PcdSiCatalogDebugEnable == TRUE)
+ DEFINE RELEASE_CATALOG_BUILD_OPTIONS = -DRELEASE_CATALOG
+!else
+ DEFINE RELEASE_CATALOG_BUILD_OPTIONS =
+!endif
+
+!if gSiPkgTokenSpaceGuid.PcdOptimizeCompilerEnable == FALSE
+ DEFINE OPTIMIZE_DISABLE_OPTIONS = -Od -GL-
+!else
+ DEFINE OPTIMIZE_DISABLE_OPTIONS =
+!endif
+
+ DEFINE HSLE_BUILD_OPTIONS =
+
+
+DEFINE CPU_FLAGS = -DCPU_ADL
+
+
+DEFINE DSC_SIPKG_FEATURE_BUILD_OPTIONS = $(BDAT_BUILD_OPTION) $(DEBUG_BUILD_OPTIONS)
+DEFINE DSC_SIPKG_FEATURE_BUILD_OPTIONS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) $(PCH_BUILD_OPTIONS) $(CPU_FLAGS) $(HSLE_BUILD_OPTIONS)
+
+!if gSiPkgTokenSpaceGuid.PcdSourceDebugEnable == TRUE
+ *_*_X64_GENFW_FLAGS = --keepexceptiontable
+!endif
+
+[BuildOptions.Common.EDKII]
+
+#
+# For IA32 Global Build Flag
+#
+ *_*_IA32_CC_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) -D PI_SPECIFICATION_VERSION=0x00010015 -DASF_PEI
+ *_*_IA32_VFRPP_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS)
+ *_*_IA32_APP_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS)
+ *_*_IA32_ASLPP_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS)
+ *_*_IA32_ASLCC_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS)
+
+#
+# For IA32 Specific Build Flag
+#
+CLANGPDB:*_*_IA32_CC_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) -D PI_SPECIFICATION_VERSION=0x00010015 -DASF_PEI -Wno-enum-conversion -Wno-incompatible-pointer-types-discards-qualifiers -Wno-sometimes-uninitialized -Wno-braced-scalar-init -Wno-nonportable-include-path -Wno-misleading-indentation
+GCC: *_*_IA32_PP_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS)
+MSFT: *_*_IA32_ASM_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS)
+MSFT: *_*_IA32_CC_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) $(OPTIMIZE_DISABLE_OPTIONS) -D PI_SPECIFICATION_VERSION=0x00010015 -DASF_PEI /w34668
+MSFT: *_*_IA32_VFRPP_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) $(OPTIMIZE_DISABLE_OPTIONS)
+MSFT: *_*_IA32_APP_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) $(OPTIMIZE_DISABLE_OPTIONS)
+MSFT: *_*_IA32_ASLPP_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) $(OPTIMIZE_DISABLE_OPTIONS)
+MSFT: *_*_IA32_ASLCC_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) $(OPTIMIZE_DISABLE_OPTIONS)
+
+#
+# For X64 Global Build Flag
+#
+ *_*_X64_CC_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) -D PI_SPECIFICATION_VERSION=0x00010015
+ *_*_X64_VFRPP_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS)
+ *_*_X64_APP_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS)
+ *_*_X64_ASLPP_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS)
+ *_*_X64_ASLCC_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS)
+
+#
+# For X64 Specific Build Flag
+#
+CLANGPDB:*_*_X64_CC_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) -D PI_SPECIFICATION_VERSION=0x00010015 -Wno-enum-conversion -Wno-main-return-type -Wno-incompatible-pointer-types -Wno-implicit-function-declaration -Wno-unused-variable -Wno-incompatible-pointer-types-discards-qualifiers -Wno-ignored-pragma-optimize -Wno-bitwise-op-parentheses -Wno-sometimes-uninitialized -Wno-unused-function -Wno-misleading-indentation
+GCC: *_*_X64_PP_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS)
+MSFT: *_*_X64_ASM_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS)
+MSFT: *_*_X64_CC_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) $(OPTIMIZE_DISABLE_OPTIONS) -D PI_SPECIFICATION_VERSION=0x00010015 /w34668
+MSFT: *_*_X64_VFRPP_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) $(OPTIMIZE_DISABLE_OPTIONS)
+MSFT: *_*_X64_APP_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) $(OPTIMIZE_DISABLE_OPTIONS)
+MSFT: *_*_X64_ASLPP_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS)
+MSFT: *_*_X64_ASLCC_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS)
+
+#
+# For Xcode Specific Build Flag
+#
+# Override assembly code build order
+*_XCODE5_*_*_BUILDRULEORDER = nasm S s
+# Align 47bfbd7f8069e523798ef973c8eb0abd5c6b0746 to fix the usage of VA_START in undefined way
+*_XCODE5_*_CC_FLAGS = -Wno-varargs
+
+# Force PE/COFF sections to be aligned at 4KB boundaries to support page level protection of runtime modules
+[BuildOptions.common.EDKII.DXE_RUNTIME_DRIVER]
+ MSFT: *_*_*_DLINK_FLAGS = /ALIGN:4096
+ GCC: *_GCC*_*_DLINK_FLAGS = -z common-page-size=0x1000
+
+
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/SiPkgCommonLib.dsc b/Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/SiPkgCommonLib.dsc
new file mode 100644
index 0000000000..69eca2ecc1
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/SiPkgCommonLib.dsc
@@ -0,0 +1,36 @@
+## @file
+# Component description file for the AlderLake SiPkg both Pei and Dxe libraries DSC file.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+#
+#
+# FRUs
+#
+!include $(PLATFORM_SI_PACKAGE)/Fru/AdlCpu/CommonLib.dsc
+!include $(PLATFORM_SI_PACKAGE)/Fru/AdlPch/CommonLib.dsc
+#
+# Common
+#
+ PciSegmentLib|$(PLATFORM_SI_PACKAGE)/Library/BasePciSegmentMultiSegLibPci/BasePciSegmentMultiSegLibPci.inf
+
+#
+# Cpu
+#
+ CpuPlatformLib|$(PLATFORM_SI_PACKAGE)/Cpu/Library/PeiDxeSmmCpuPlatformLib/PeiDxeSmmCpuPlatformLib.inf
+
+#
+# Pch
+#
+ PchCycleDecodingLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/PeiDxeSmmPchCycleDecodingLib/PeiDxeSmmPchCycleDecodingLib.inf
+
+ ResetSystemLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/BaseResetSystemLib/BaseResetSystemLib.inf
+#private
+ GpioPrivateLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Gpio/LibraryPrivate/PeiDxeSmmGpioPrivateLib/PeiDxeSmmGpioPrivateLibVer2.inf
+ PchPciBdfLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/BasePchPciBdfLib/BasePchPciBdfLib.inf
+
+#
+# SA
+#
+ GraphicsInfoLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Graphics/Library/PeiDxeSmmGraphicsInfoLib/GraphicsInfoLibVer1.inf
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/SiPkgDxe.dsc b/Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/SiPkgDxe.dsc
new file mode 100644
index 0000000000..97e63dcc96
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/SiPkgDxe.dsc
@@ -0,0 +1,32 @@
+## @file
+# Component description file for the AlderLake SiPkg DXE drivers.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+#
+# FRUs
+#
+!include $(PLATFORM_SI_PACKAGE)/Fru/AdlPch/Dxe.dsc
+#
+# Common
+#
+
+#
+# Pch
+#
+ $(PLATFORM_SI_PACKAGE)/Pch/SmmControl/RuntimeDxe/SmmControl.inf
+
+ $(PLATFORM_SI_PACKAGE)/Pch/PchSmiDispatcher/Smm/PchSmiDispatcher.inf{
+ <LibraryClasses>
+ SmiHandlerProfileLib|MdePkg/Library/SmiHandlerProfileLibNull/SmiHandlerProfileLibNull.inf
+ }
+
+#
+# SystemAgent
+#
+ $(PLATFORM_SI_PACKAGE)/SystemAgent/SaInit/Dxe/SaInitDxe.inf
+
+
+
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/SiPkgDxeLib.dsc b/Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/SiPkgDxeLib.dsc
new file mode 100644
index 0000000000..37876cbfc4
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/SiPkgDxeLib.dsc
@@ -0,0 +1,23 @@
+# @file
+# Component description file for the AlderLake SiPkg DXE libraries.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+#
+# FRUs
+#
+!include $(PLATFORM_SI_PACKAGE)/Fru/AdlCpu/DxeLib.dsc
+!include $(PLATFORM_SI_PACKAGE)/Fru/AdlPch/DxeLib.dsc
+
+#
+# Common
+#
+ AslUpdateLib|IntelSiliconPkg/Library/DxeAslUpdateLib/DxeAslUpdateLib.inf
+ SiConfigBlockLib|$(PLATFORM_SI_PACKAGE)/Library/BaseSiConfigBlockLib/BaseSiConfigBlockLib.inf
+
+#
+# SystemAgent
+#
+ DxeSaPolicyLib|$(PLATFORM_SI_PACKAGE)/SystemAgent/Library/DxeSaPolicyLib/DxeSaPolicyLib.inf
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/SiPkgPeiLib.dsc b/Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/SiPkgPeiLib.dsc
new file mode 100644
index 0000000000..21e6ff3851
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/SiPkgPeiLib.dsc
@@ -0,0 +1,19 @@
+## @file
+# Component description file for the AlderLake SiPkg PEI libraries.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+#
+# FRUs
+#
+!include $(PLATFORM_SI_PACKAGE)/Fru/AdlPch/PeiLib.dsc
+
+
+ SiPolicyLib|$(PLATFORM_SI_PACKAGE)/Product/Alderlake/Library/PeiSiPolicyLib/PeiSiPolicyLib.inf
+ SiConfigBlockLib|$(PLATFORM_SI_PACKAGE)/Library/BaseSiConfigBlockLib/BaseSiConfigBlockLib.inf
+
+
+
+
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/SiPkg.dec b/Silicon/Intel/AlderlakeSiliconPkg/SiPkg.dec
new file mode 100644
index 0000000000..ce9cfe599a
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/SiPkg.dec
@@ -0,0 +1,625 @@
+## @file
+# Component description file for the Silicon Reference Code.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+
+[Defines]
+DEC_SPECIFICATION = 0x00010017
+PACKAGE_NAME = SiPkg
+PACKAGE_VERSION = 0.1
+PACKAGE_GUID = F245E276-44A0-46b3-AEB5-9898BBCF008D
+
+[Includes.Common.Private]
+
+#
+# AlderLake Fru
+#
+Fru/AdlCpu/IncludePrivate
+Fru/AdlPch/IncludePrivate
+
+##
+# IpBlock IncludePrivate
+#
+IpBlock/Pmc/IncludePrivate
+IpBlock/Graphics/IncludePrivate
+IpBlock/PchDmi/IncludePrivate
+IpBlock/P2sb/IncludePrivate
+IpBlock/Spi/IncludePrivate
+IpBlock/Gpio/IncludePrivate
+IpBlock/HostBridge/IncludePrivate
+
+# Cpu
+Cpu/IncludePrivate
+
+IncludePrivate
+
+[Includes]
+Product/Alderlake/Include
+#
+# AlderLake
+#
+Fru/AdlCpu/Include
+Fru/AdlPch/Include
+
+
+# CPU PCIe
+IpBlock/CpuPcieRp/Include
+
+#
+# - Memory
+Include/ConfigBlock/Memory/Ver2
+#
+# - Graphics
+Include/ConfigBlock/Graphics/Gen12
+IpBlock/Graphics/Include
+
+#
+# - CPU PCIe
+Include/ConfigBlock/CpuPcieRp/Gen4
+
+#
+# HostBridge
+#
+Include/ConfigBlock/HostBridge/Ver1
+
+Include
+#
+# SystemAgent
+#
+SystemAgent/Include
+Include/ConfigBlock/PcieRp
+Include/ConfigBlock/Vmd
+Include/ConfigBlock/CpuPcieRp/Gen4
+Include/ConfigBlock/CpuPcieRp/Gen3
+
+#
+# Cpu
+#
+Cpu/Include
+
+
+#
+# Pch
+#
+Pch/Include
+Include/ConfigBlock/Espi
+Include/ConfigBlock/Smbus
+Include/ConfigBlock/Pmc
+Include/ConfigBlock/PchDmi
+Include/ConfigBlock/Wdt
+Include/ConfigBlock/PcieRp/PchPcieRp
+Include/ConfigBlock/PcieRp
+Include/ConfigBlock/SerialIo
+
+[Guids.common.Private]
+#
+# PCH
+#
+gGpioLibUnlockHobGuid = { 0xA7892E49, 0x0F9F, 0x4166, { 0xB8, 0xD6, 0x8A, 0x9B, 0xD9, 0x8B, 0x17, 0x38 }}
+
+[Guids]
+gSmbiosProcessorInfoHobGuid = {0xe6d73d92, 0xff56, 0x4146, {0xaf, 0xac, 0x1c, 0x18, 0x81, 0x7d, 0x68, 0x71}}
+gSmbiosCacheInfoHobGuid = {0xd805b74e, 0x1460, 0x4755, {0xbb, 0x36, 0x1e, 0x8c, 0x8a, 0xd6, 0x78, 0xd7}}
+
+##
+## MdeModulePkg
+##
+gEfiMemoryTypeInformationGuid = {0x4c19049f, 0x4137, 0x4dd3, {0x9c, 0x10, 0x8b, 0x97, 0xa8, 0x3f, 0xfd, 0xfa}}
+gEfiCapsuleVendorGuid = {0x711c703f, 0xc285, 0x4b10, {0xa3, 0xb0, 0x36, 0xec, 0xbd, 0x3c, 0x8b, 0xe2}}
+gEfiConsoleOutDeviceGuid = { 0xd3b36f2c, 0xd551, 0x11d4, { 0x9a, 0x46, 0x0, 0x90, 0x27, 0x3f, 0xc1, 0x4d}}
+##
+## Common
+##
+## Include/ConfigBlock/SiConfig.h
+gSiConfigGuid = {0x4ed6d282, 0x22f3, 0x4fe1, {0xa6, 0x61, 0x6, 0x1a, 0x97, 0x38, 0x59, 0xd8}}
+##
+gSiPreMemConfigGuid = {0xb94c004c, 0xa0ab, 0x40f0, {0x9b, 0x61, 0x0b, 0x25, 0x88, 0xbe, 0xfd, 0xc6}}
+##
+##
+gPciePreMemConfigGuid = {0xd0f9c2a9, 0x7332, 0x4733, {0x8d, 0xb1, 0x98, 0x79, 0x27, 0x60, 0xda, 0xe6}}
+##
+gSiPkgTokenSpaceGuid = {0x977c97c1, 0x47e1, 0x4b6b, {0x96, 0x69, 0x43, 0x66, 0x99, 0xcb, 0xe4, 0x5b}}
+
+gSiConfigHobGuid = {0xb3903068, 0x7482, 0x4424, {0xba, 0x4b, 0x40, 0x5f, 0x8f, 0xd7, 0x65, 0x4e}}
+
+##
+##
+## SystemAgent
+##
+gSaDataHobGuid = {0xe07d0bda, 0xbf90, 0x46a9, { 0xb0, 0x0e, 0xb2, 0xc4, 0x4a, 0x0e, 0xd6, 0xd0}}
+gSaConfigHobGuid = {0x762fa2e6, 0xea3b, 0x41c8, { 0x8c, 0x52, 0x63, 0x76, 0x6d, 0x70, 0x39, 0xe0}}
+gSaMiscPeiPreMemConfigGuid = {0x4a525577, 0x3469, 0x4f11, { 0x99, 0xcf, 0xfb, 0xcd, 0x5e, 0xf1, 0x84, 0xe4}}
+gCpuPciePeiPreMemConfigGuid = { 0x81baf3c9, 0xf295, 0x4572, { 0x8b, 0x21, 0x79, 0x3f, 0xa3, 0x1b, 0xa5, 0xdb}}
+gVmdPeiConfigGuid = { 0x79b52c74, 0xb9ba, 0x4f36, {0xa2, 0x40, 0xf2, 0x41, 0x0d, 0x20, 0x84, 0x8a}}
+gVmdInfoHobGuid = { 0xccd0306e, 0x7fa1, 0x4df5, {0x99, 0x99, 0xc1, 0xf8, 0x9a, 0x1d, 0x1b, 0xa9}}
+gMemoryConfigGuid = { 0x26cf084c, 0xc9db, 0x41bb, { 0x92, 0xc6, 0xd1, 0x97, 0xb8, 0xa1, 0xe4, 0xbf}}
+gMemoryConfigNoCrcGuid = { 0xc56c73d0, 0x1cdb, 0x4c0c, { 0xa9, 0x57, 0xea, 0x62, 0xa9, 0xe6, 0xf5, 0x0c}}
+gMemoryDxeConfigGuid = {0xa5c7dda8, 0x686b, 0x404f, {0x86, 0x40, 0xf8, 0x2, 0xd, 0x84, 0x4c, 0x94}}
+gCpuPcieRpPrememConfigGuid = { 0x41aef892, 0xc800, 0x4ac0, {0xa9, 0x30, 0x84, 0xac, 0x47, 0xca, 0xca, 0x7e}}
+gCpuPcieRpConfigGuid = { 0x9749a5fb, 0x9130, 0x44f0, {0x8f, 0x61, 0xdb, 0xff, 0x8e, 0xf2, 0xca, 0xc7}}
+## IntelFsp2Pkg/IntelFsp2Pkg.dec gSiMemoryS3DataGuid is the same as gFspNonVolatileStorageHobGuid
+gSiMemoryS3DataGuid = { 0x721acf02, 0x4d77, 0x4c2a, { 0xb3, 0xdc, 0x27, 0x0b, 0x7b, 0xa9, 0xe4, 0xb0 } }
+gSiMemoryInfoDataGuid = { 0x9b2071d4, 0xb054, 0x4e0c, { 0x8d, 0x09, 0x11, 0xcf, 0x8b, 0x9f, 0x03, 0x23 } }
+gSiMemoryPlatformDataGuid = { 0x6210d62f, 0x418d, 0x4999, { 0xa2, 0x45, 0x22, 0x10, 0x0a, 0x5d, 0xea, 0x44 } }
+gSaPciePeiConfigGuid = { 0xdaa929a9, 0x5ec9, 0x486a, { 0xb0, 0xf7, 0x82, 0x3a, 0x55, 0xc7, 0xb5, 0xb3}}
+gSaPciePeiPreMemConfigGuid = { 0xfc5e01a3, 0x69f6, 0x4e35, { 0x9f, 0xcf, 0x6, 0x68, 0x7b, 0xab, 0x31, 0xd7}}
+
+#
+# Host Bridge
+#
+gHostBridgePeiPreMemConfigGuid = {0xbdef6805, 0x2080, 0x44ad, { 0x93, 0x2e, 0x00, 0x04, 0xf5, 0x2c, 0xb7, 0xa1}}
+gHostBridgePeiConfigGuid = {0x3b6d998e, 0x8b6e, 0x4f53, { 0xbe, 0x41, 0x7, 0x41, 0x95, 0x53, 0x8a, 0xaf}}
+gHostBridgeDataHobGuid = {0x3b682d57, 0xd402, 0x40a6, { 0xb1, 0x34, 0xa0, 0xc4, 0xf6, 0x31, 0x1d, 0x9}}
+
+#
+# Graphics
+#
+gGraphicsPeiConfigGuid = {0x04249ac0, 0x0088, 0x439f, { 0xa7, 0x4e, 0xa7, 0x04, 0x2a, 0x06, 0x2f, 0x5d}}
+gGraphicsDxeConfigGuid = {0x34d93161, 0xf78e, 0x4915, {0xad, 0xc4, 0xdb, 0x67, 0x16, 0x42, 0x39, 0x24}}
+
+## Include/SsaCommonConfig.h
+gSsaPostcodeHookGuid = {0xADF0A27B, 0x61A6, 0x4F18, {0x9E, 0xAC, 0x46, 0x87, 0xE7, 0x9E, 0x6F, 0xBB}}
+gSsaBiosVariablesGuid = {0x43eeffe8, 0xa978, 0x41dc, {0x9d, 0xb6, 0x54, 0xc4, 0x27, 0xf2, 0x7e, 0x2a}}
+gSsaBiosResultsGuid = {0x8f4e928, 0xf5f, 0x46d4, {0x84, 0x10, 0x47, 0x9f, 0xda, 0x27, 0x9d, 0xb6}}
+gHobUsageDataGuid = {0xc764a821, 0xec41, 0x450d, { 0x9c, 0x99, 0x27, 0x20, 0xfc, 0x7c, 0xe1, 0xf6 }}
+
+##
+## Cpu
+##
+gCpuAcpiTableStorageGuid = {0xc38fb0e2, 0x0c43, 0x49c9, {0xb5, 0x44, 0x9b, 0x17, 0xaa, 0x4d, 0xcb, 0xa3}}
+gCpuSecurityPreMemConfigGuid = {0xfd5c346, 0x8260, 0x4067, {0x94, 0x69, 0xcf, 0x91, 0x68, 0xa3, 0x42, 0x90}}
+gCpuConfigLibPreMemConfigGuid = {0xfc1c0ec2, 0xc6b4, 0x4f05, {0xbb, 0x85, 0xc8, 0x0, 0x8d, 0x5b, 0x4a, 0xb7}}
+gCpuConfigGuid = {0x48c3aac9, 0xd66c, 0x42e4, {0x9b, 0x1d, 0x39, 0x4, 0x5f, 0x46, 0x53, 0x41}}
+gCpuDataHobGuid = {0x1eec629f, 0xf3cf, 0x4b02, { 0xa9, 0xa5, 0x27, 0xa2, 0x33, 0x20, 0xbe, 0x5d}}
+##
+## Me
+##
+gPciImrHobGuid = {0x49b1eac3, 0x0cd6, 0x451e, {0x96, 0x30, 0x92, 0x4b, 0xc2, 0x69, 0x35, 0x86}}
+gTpm2AcpiTableStorageGuid = {0x7d279373, 0xeecc, 0x4d4f, {0xae, 0x2f, 0xce, 0xc4, 0xb7, 0x06, 0xb0, 0x6a}}
+gEdkiiTouchPanelGuid = {0x91b1d27b, 0xe126, 0x48d1, {0x82, 0x34, 0xd2, 0x8b, 0x81, 0xc8, 0x83, 0x62}}
+gMeDidSentHobGuid = {0x4c3d3af1, 0x1720, 0x4c3f, {0xab, 0x7c, 0x36, 0x50, 0xbb, 0x5b, 0x85, 0x7e}}
+
+##
+## PCH
+##
+gPchGlobalResetGuid = { 0x9db31b4c, 0xf5ef, 0x48bb, { 0x94, 0x2b, 0x18, 0x1f, 0x7e, 0x3a, 0x3e, 0x40 }}
+
+gPchGeneralPreMemConfigGuid = {0xC65F62FA, 0x52B9, 0x4837, {0x86, 0xEB, 0x1A, 0xFB, 0xD4, 0xAD, 0xBB, 0x3E}}
+gWatchDogPreMemConfigGuid = {0xFBCE08CC, 0x60F2, 0x4BDF, {0xB7, 0x88, 0x09, 0xBB, 0x81, 0x65, 0x52, 0x2B}}
+gPcieRpPreMemConfigGuid = {0x8377AB38, 0xF8B0, 0x476A, { 0x9C, 0xA1, 0x68, 0xEA, 0x78, 0x57, 0xD8, 0x2A}}
+gSmbusPreMemConfigGuid = {0x77A6E62C, 0x716B, 0x4386, {0x9E, 0x9C, 0x23, 0xA0, 0x2E, 0x13, 0x7B, 0x3A}}
+gLpcPreMemConfigGuid = {0xA6E6032F, 0x1E58, 0x407E, {0x9A, 0xB8, 0xC6, 0x30, 0xC6, 0xC4, 0x11, 0x8E}}
+gPchDmiPreMemConfigGuid = {0x4DA4AA22, 0xB54A, 0x43D7, {0x87, 0xC8, 0xA3, 0xCF, 0x53, 0xE6, 0xC1, 0x8A}}
+
+gPchGeneralConfigGuid = {0x6ED94C8C, 0x25F7, 0x4686, {0xB2, 0x46, 0xCA, 0x4D, 0xE2, 0x95, 0x4B, 0x5D}}
+gPchPcieConfigGuid = {0x0A53B507, 0x988B, 0x475C, {0xBF, 0x76, 0x33, 0xDE, 0x10, 0x6D, 0x94, 0x84}}
+gPchPcieRpDxeConfigGuid = {0x475530EA, 0xBD72, 0x416F, {0x98, 0x9F,0x48, 0x70, 0x5F, 0x14, 0x4E, 0xD9}}
+gIoApicConfigGuid = {0x2873D0F1, 0x00F6, 0x40AB, {0xAC, 0x36, 0x9A, 0x68, 0xBA, 0x87, 0x3E, 0x6C}}
+gPchDmiConfigGuid = {0xB3A61210, 0x1CD3, 0x4797, {0x8E, 0xE6, 0xD3, 0x42, 0x9C, 0x4F, 0x17, 0xBD}}
+gSerialIoConfigGuid = {0x6CC06EBF, 0x0D34, 0x4340, {0xBC, 0x16, 0xDA, 0x09, 0xE5, 0x78, 0x3A, 0xDB}}
+
+##
+## SecurityPkg
+##
+## GUID used to "Tcg2PhysicalPresence" variable and "Tcg2PhysicalPresenceFlags" variable for TPM2 request and response.
+# Include/Guid/Tcg2PhysicalPresenceData.h
+gEfiTcg2PhysicalPresenceGuid = { 0xaeb9c5c1, 0x94f1, 0x4d02, { 0xbf, 0xd9, 0x46, 0x2, 0xdb, 0x2d, 0x3c, 0x54 }}
+
+##
+## FSP
+##
+gFspSiliconFvGuid = { 0x1b5c27fe, 0xf01c, 0x4fbc, { 0xae, 0xae, 0x34, 0x1b, 0x2e, 0x99, 0x2a, 0x17 }}
+gFspTscFrequencyGuid = { 0x0e3b622a, 0xedbb, 0x4e30, { 0x93, 0x60, 0x69, 0x5c, 0xd4, 0xb3, 0x20, 0xc9 }}
+gFspInfoGuid = { 0x067e0f25, 0x374f, 0x47c2, { 0x17, 0x92, 0x86, 0xdc, 0xdb, 0xc4, 0x8a, 0xc9 }}
+
+[Protocols]
+##
+## MdeModulePkg
+##
+gEdkiiSmmExitBootServicesProtocolGuid = { 0x296eb418, 0xc4c8, 0x4e05, { 0xab, 0x59, 0x39, 0xe8, 0xaf, 0x56, 0xf0, 0xa } }
+
+##
+## SystemAgent
+##
+gIgdOpRegionProtocolGuid = {0x9e67aecf, 0x4fbb, 0x4c84, {0x99, 0xa5, 0x10, 0x73, 0x40, 0x7, 0x6d, 0xb4}}
+gSaPolicyProtocolGuid = {0xc6aa1f27, 0x5597, 0x4802, {0x9f, 0x63, 0xd6, 0x28, 0x36, 0x59, 0x86, 0x35}}
+gGopPolicyProtocolGuid = {0xec2e931b, 0x3281, 0x48a5, {0x81, 0x07, 0xdf, 0x8a, 0x8b, 0xed, 0x3c, 0x5d}}
+
+##
+## PCH
+##
+gPchSpiProtocolGuid = { 0xc7d289, 0x1347, 0x4de0, {0xbf, 0x42, 0xe, 0x26, 0x9d, 0xe, 0xf3, 0x4a}}
+gWdtProtocolGuid = {0xb42b8d12, 0x2acb, 0x499a, {0xa9, 0x20, 0xdd, 0x5b, 0xe6, 0xcf, 0x09, 0xb1}}
+gEfiSmmSmbusProtocolGuid = {0x72e40094, 0x2ee1, 0x497a, {0x8f, 0x33, 0x4c, 0x93, 0x4a, 0x9e, 0x9c, 0x0c}}
+gPchSmmSpiProtocolGuid = {0x56521f06, 0xa62, 0x4822, {0x99, 0x63, 0xdf, 0x1, 0x9d, 0x72, 0xc7, 0xe1}}
+gPchSmmIoTrapControlGuid = {0x514d2afd, 0x2096, 0x4283, {0x9d, 0xa6, 0x70, 0x0c, 0xd2, 0x7d, 0xc7, 0xa5}}
+gPchTcoSmiDispatchProtocolGuid = {0x9e71d609, 0x6d24, 0x47fd, {0xb5, 0x72, 0x61, 0x40, 0xf8, 0xd9, 0xc2, 0xa4}}
+gPchPcieSmiDispatchProtocolGuid = {0x3e7d2b56, 0x3f47, 0x42aa, {0x8f, 0x6b, 0x22, 0xf5, 0x19, 0x81, 0x8d, 0xab}}
+gPchAcpiSmiDispatchProtocolGuid = {0xd52bb262, 0xf022, 0x49ec, {0x86, 0xd2, 0x7a, 0x29, 0x3a, 0x7a, 0x05, 0x4b}}
+gPchSmiDispatchProtocolGuid = {0xE6A81BBF, 0x873D, 0x47FD, {0xB6, 0xBE, 0x61, 0xB3, 0xE5, 0x72, 0x09, 0x93}}
+gPchEspiSmiDispatchProtocolGuid = {0xB3C14FF3, 0xBAE8, 0x456C, {0x86, 0x31, 0x27, 0xFE, 0x0C, 0xEB, 0x34, 0x0C}}
+gPchSmmPeriodicTimerControlGuid = {0x6906E93B, 0x603B, 0x4A0F, {0x86, 0x92, 0x83, 0x20, 0x04, 0xAA, 0xF2, 0xDB}}
+##
+## Silicon Policy
+##
+## Include/Protocol/SiPolicyProtocol.h
+gDxeSiPolicyProtocolGuid = { 0xeca27516, 0x306c, 0x4e28, { 0x8c, 0x94, 0x4e, 0x52, 0x10, 0x96, 0x69, 0x5e }}
+
+[Ppis.common.Private]
+
+[Ppis]
+##
+## MdeModulePkg
+##
+gEdkiiPlatformSpecificResetFilterPpiGuid = { 0x8c9f4de3, 0x7b90, 0x47ef, { 0x93, 0x8, 0x28, 0x7c, 0xec, 0xd6, 0x6d, 0xe8 } }
+
+##
+## SecurityPkg
+##
+gPeiTpmInitializationDonePpiGuid = {0xa030d115, 0x54dd, 0x447b, { 0x90, 0x64, 0xf2, 0x6, 0x88, 0x3d, 0x7c, 0xcc}}
+##
+## Common
+##
+## Include/Ppi/SiPolicy.h
+gSiPolicyPpiGuid = {0xaebffa01, 0x7edc, 0x49ff, {0x8d, 0x88, 0xcb, 0x84, 0x8c, 0x5e, 0x86, 0x70}}
+## Include/Ppi/SiPolicy.h
+gSiPreMemPolicyPpiGuid = {0xc133fe57, 0x17c7, 0x4b09, {0x8b, 0x3c, 0x97, 0xc1, 0x89, 0xd0, 0xab, 0x8d}}
+## Silicon Initialization PPI is used to export End of Silicon init.
+gEndOfSiInitPpiGuid = {0xE2E3D5D1, 0x8356, 0x4F96, {0x9C, 0x9E, 0x2E, 0xC3, 0x48, 0x1D, 0xEA, 0x88}}
+gEfiEndOfPeiSignal2PpiGuid = {0x22918381, 0xd018, 0x4d7c, {0x9d, 0x62, 0xf5, 0xa5, 0x70, 0x1c, 0x66, 0x80}}
+gFspTempRamExitPpiGuid = {0xbc1cfbdb, 0x7e50, 0x42be, {0xb4, 0x87, 0x22, 0xe0, 0xa9, 0x0c, 0xb0, 0x52}}
+gFspmArchConfigPpiGuid = {0x824d5a3a, 0xaf92, 0x4c0c, {0x9f, 0x19, 0x19, 0x52, 0x6d, 0xca, 0x4a, 0xbb}}
+gSiPreMemDefaultPolicyInitPpiGuid = {0xfec36242, 0xf8d8, 0x4b43, {0x87, 0x94, 0x4f, 0x1f, 0x9f, 0x63, 0x8d, 0xdc}}
+gSiPreMemPolicyReadyPpiGuid = {0x85270bef, 0x6984, 0x4375, {0xa6, 0xea, 0xb5, 0xaa, 0x90, 0x6e, 0xdd, 0x4a}}
+gSiDefaultPolicyInitPpiGuid = {0xf69abf86, 0x4048, 0x44ef, { 0xa8, 0xef, 0x6c, 0x7f, 0x20, 0x4a, 0xc8, 0xda}}
+gSiPolicyReadyPpiGuid = {0xd570de8c, 0xb9c4, 0x4ffa, {0xad, 0xee, 0xa5, 0x82, 0x7c, 0xe3, 0x17, 0x79}}
+gPeiBeforeGraphicsDetectionPpiGuid = {0xa494060d, 0x98c5, 0x4948, {0x84, 0x57, 0x74, 0xd7, 0x1a, 0x3d, 0x0e, 0x85}}
+
+##
+## UEFI Variable Support (Override Until BP1.5)
+##
+gEdkiiVariableStoragePpiGuid = { 0x90d915c5, 0xe4c1, 0x4da8, {0xa7, 0x6f, 0x9, 0xe5, 0x78, 0x91, 0x65, 0x48}}
+gEdkiiVariableStorageSelectorPpiGuid = { 0x782546d1, 0x03ab, 0x41e4, {0xa0, 0x1d, 0x7a, 0x9b, 0x22, 0xba, 0x2e, 0x1e}}
+gReadOnlyVariablePreMemoryDescriptorPpiGuid = { 0xbe136fc9, 0xc277, 0x4dd1, {0xbe, 0x42, 0xce, 0xf0, 0x9f, 0xf4, 0x3f, 0x55}}
+gEfiReadyToInstallEndOfPei2PpiGuid = {0xeef72924, 0x2db2, 0x4569, { 0x86, 0x3f, 0xd4, 0x86, 0xae, 0x7a, 0xe4, 0x12}}
+
+##
+## SystemAgent
+##
+gEnablePeiGraphicsPpiGuid = {0x8e3bb474, 0x545, 0x4902, {0x86, 0xb0, 0x6c, 0xb5, 0xe2, 0x64, 0xb4, 0xa5}}
+gPeiGraphicsFramebufferReadyPpiGuid = {0x590ad868, 0xb0b1, 0x4d20, {0x91, 0xff, 0xc2, 0xa9, 0xd6, 0x88, 0x81, 0x94}}
+gPeiGraphicsPlatformPpiGuid = {0x4eabcd09, 0x43d3, 0x4b4d, {0xb7, 0x3d, 0x43, 0xc8, 0xd9, 0x89, 0x99, 0x05}}
+## X Compatibility support PPI
+gCompatibleMemoryInitPpiGuid = {0xca311f82, 0xf490, 0x4b12, {0x9e, 0xe1, 0x2b, 0x66, 0xa3, 0x6c, 0x3e, 0xa}}
+gVmdInitDonePpiGuid = {0x42a187c8, 0xca0a, 0x4750, {0x82, 0xfd, 0xc9, 0xa0, 0xd5, 0x9, 0xfe, 0xd1}}
+
+##
+## Cpu
+##
+gPeiCachePpiGuid = {0xC153205A, 0xE898, 0x4C24, {0x86, 0x89, 0xA4, 0xB4, 0xBC, 0xC5, 0xC8, 0xA2}}
+gPeiTxtMemoryUnlockedPpiGuid = {0x38cdd10b, 0x767d, 0x4f6e, {0xa7, 0x44, 0x67, 0xee, 0x1d, 0xfe, 0x2f, 0xa5}}
+gPeiTxtReadyToRunMemoryInitPpiGuid = {0x9ecafd30, 0x29e2, 0x42f6, {0xba, 0xf3, 0x8b, 0x7d, 0xb8, 0xfe, 0x1f, 0x22}}
+gPeiReadyToInstallMpPpiGuid = { 0x1a266768, 0xfd43, 0x4e18, { 0xa8, 0x8a, 0x35, 0xc7, 0x94, 0xc3, 0x91, 0x0e }}
+
+##
+## PCH
+##
+gWdtPpiGuid = {0xf38d1338, 0xaf7a, 0x4fb6, {0x91, 0xdb, 0x1a, 0x9c, 0x21, 0x83, 0x57, 0x0d}}
+gPchSpiPpiGuid = {0xdade7ce3, 0x6971, 0x4b75, {0x82, 0x5e, 0xe, 0xe0, 0xeb, 0x17, 0x72, 0x2d}}
+gPeiSmbusPolicyPpiGuid = {0x63b6e435, 0x32bc, 0x49c6, {0x81, 0xbd, 0xb7, 0xa1, 0xa0, 0xfe, 0x1a, 0x6c}}
+gPchIoExpanderInfoPpiGuid = { 0xf4a29776, 0x0ff9, 0x4b5c, { 0xb6, 0x9d, 0x88, 0x45, 0x09, 0x9b, 0x8d, 0xa5 }}
+
+##
+## TCSS
+##
+gTcssPeiInitDonePpiGuid = {0x5ad291b8, 0xace4, 0x416a, {0xb7, 0x50, 0x7, 0x63, 0x59, 0xfc, 0xc1, 0x5b}}
+
+##
+## ExtendedBiosDecodeReady PPI
+##
+gExtendedBiosDecodeReadyPpiGuid = {0x54b522bc, 0xbef2, 0x419b, {0xa9, 0x66, 0x7e, 0xc4, 0xf0, 0x15, 0xe8, 0x21}}
+
+##
+## FSP##
+gFsptUpdLocationPpiGuid = { 0xfc4dd4f2, 0x179e, 0x41f8, { 0x9d, 0x6d, 0xfa, 0xd6, 0xf9, 0xd7, 0xb8, 0xb9 }}
+
+[LibraryClasses]
+## @libraryclass
+## Common
+##
+SiPolicyLib|Include/Library/SiPolicyLib.h
+PeiPolicyUpdateLib|Include/Library/PeiSiPolicyUpdateLib.h
+ProcessorTraceMemoryAllocationLib|Include/Library/ProcessorTraceMemoryAllocationLib.h
+PlatformSecLib|Include/Library/SecPlatformLib.h
+SiAssertErrorHandlerLib|Include/Library/SiAssertErrorHandlerLib.h
+SiConfigBlockLib|Include/Library/SiConfigBlockLib.h
+## @libraryclass
+## SampleCode
+##
+## CPU
+##
+CpuPlatformLib|Cpu/Include/Library/CpuPlatformLib.h
+
+
+## @libraryclass
+## Pch
+##
+GpioLib|Include/Library/GpioLib.h
+GpioLib|Include/Library/GpioNativeLib.h
+PchCycleDecodingLib|Pch/Include/Library/PchCycleDecodingLib.h
+EspiLib|Include/Library/EspiLib.h
+PchInfoLib|Pch/Include/Library/PchInfoLib.h
+PchPcieRpLib|Include/Library/PchPcieRpLib.h
+PchPcrLib|Include/Library/PchPcrLib.h
+PchSbiAccessLib|IpBlock/P2sb/IncludePrivate/Library/PchSbiAccessLib.h
+PchPciBdfLib|Pch/Include/Library/PchPciBdfLib.h
+PchRasLib|Pch/Include/Library/PchRasLib.h
+PchRtcLib|Pch/Include/Library/PchRtcLib.h
+ResetSystemLib|Include/Library/ResetSystemLib.h
+## @libraryclass
+## Sa
+##
+DxeSaPolicyLib|SystemAgent/Include/Library/DxeSaPolicyLib.h
+## @libraryclass
+## Fru
+##
+CpuInfoFruLib|Cpu/IncludePrivate/Library/CpuInfoFruLib.h
+## @libraryclass
+## IpBlock
+##
+PmcPrivateLib|IpBlock/Pmc/IncludePrivate/Library/PmcPrivateLib.h
+IehInitLib|IpBlock/Ieh/IncludePrivate/Library/PeiIehInitLib.h
+PeiIehPolicyLib|IpBlock/Ieh/IncludePrivate/Library/PeiIehPolicyLib.h
+DxeGraphicsPolicyLib|IpBlock/Graphics/IncludePrivate/Library/DxeGraphicsPolicyLib.h
+DxeIgdOpRegionInitLib|IpBlock/Graphics/IncludePrivate/Library/DxeIgdOpRegionInitLib.h
+PchDmiLib|IpBlock/PchDmi/IncludePrivate/Library/PchDmiLib.h
+P2SbSidebandAccessLib|IpBlock/P2sb/IncludePrivate/Library/P2SbSidebandAccessLib.h
+SpiCommonLib|IpBlock/Spi/IncludePrivate/Library/SpiCommonLib.h
+GpioHelpersLib|IpBlock/Gpio/IncludePrivate/Library/GpioHelpersLib.h
+GpioPrivateLib|IpBlock/Gpio/IncludePrivate/Library/GpioPrivateLib.h
+PeiDmiSipInitLib|IpBlock/PcieRp/IncludePrivate/Library/PeiDmiSipInitLib.h
+PeiEnterprisePcieRpInitLib|IpBlock/PcieRp/IncludePrivate/Library/PeiEnterprisePcieRpInitLib.h
+PeiDpInInitLib|IpBlock/Tcss/IncludePrivate/Library/PeiDpInInitLib.h
+CpuPcieRpLib|IpBlock/CpuPcieRp/Include/Library/CpuPcieRpLib.h
+GpioGsxLib|Include/Library/GpioGsxLib.h
+GraphicsInfoLib|Include/Library/GraphicsInfoLib.h
+HeciCommonLib|Include/Library/HeciCommonLib.h
+HeciConfigureLib|Include/Library/HeciConfigureLib.h
+HeciTraceLib|Include/Library/HeciTraceLib.h
+HeciTransportCoreLib|Include/Library/HeciTransportCoreLib.h
+OcPlatformLib|Include/Library/OcPlatformLib.h
+PeiSpsPreMemPolicyLib|Include/Library/PeiSpsPreMemPolicyLib.h
+PmcLib|Include/Library/PmcLib.h
+PmcSsramLib|Include/Library/PmcSsramLib.h
+SpiLib|Include/Library/SpiLib.h
+SpsDxeLib|Include/Library/SpsDxeLib.h
+SpsGetDxeConfigBlockLib|Include/Library/SpsGetDxeConfigBlock.h
+MeGetPeiConfigBlock|Include/Library/MeGetConfigBlock.h
+## @libraryclass
+## Fsp
+##
+FspHelperLib|Fsp/Include/Library/FspHelperLib.h
+FspInfoLib|Fsp/Include/Library/FspInfoLib.h
+FspSerialIoUartDebugHelperLib|Fsp/Include/Library/FspSerialIoUartDebugHelperLib.h
+
+
+CpuPcieInfoFruLib|Fru/AdlCpu/Include/Library/CpuPcieInfoFruLib.h
+
+[PcdsFixedAtBuild]
+## From MdeModulePkg.dec
+## Progress Code for S3 Suspend start.
+## PROGRESS_CODE_S3_SUSPEND_START = (EFI_SOFTWARE_SMM_DRIVER | (EFI_OEM_SPECIFIC | 0x00000000)) = 0x03078000
+gSiPkgTokenSpaceGuid.PcdProgressCodeS3SuspendStart|0x03078000|UINT32|0x30001032
+## Progress Code for S3 Suspend end.
+## PROGRESS_CODE_S3_SUSPEND_END = (EFI_SOFTWARE_SMM_DRIVER | (EFI_OEM_SPECIFIC | 0x00000001)) = 0x03078001
+gSiPkgTokenSpaceGuid.PcdProgressCodeS3SuspendEnd|0x03078001|UINT32|0x30001033
+##
+## PcdNemCodeCacheBase is usally the same as PEI FV Base address,
+## FLASH_BASE+FLASH_REGION_FV_RECOVERY_OFFSET from PlatformPkg.fdf.
+##
+## Restriction:
+## 1) PcdNemCodeCacheBase - (PcdTemporaryRamBase + PcdTemporaryRamSize) >= 4K
+## 2) PcdTemporaryRamBase >= 4G - 64M
+##
+gSiPkgTokenSpaceGuid.PcdNemCodeCacheBase|0xFFF80000|UINT32|0x20000009
+##
+## NemCodeCacheSize is usally the same as PEI FV Size,
+## FLASH_REGION_FV_RECOVERY_SIZE from PlatformPkg.fdf.
+##
+## Restriction:
+## 1) PcdNemTotalCacheSize = NemCodeCacheSize + PcdTemporaryRamSize
+## <= Maximun CPU NEM total size (Code + Data)
+## = LLC size - 0.5M
+## 2) PcdTemporaryRamSize <= Maximum CPU NEM data size
+## = MLC size
+## NOTE: The size restriction may be changed in next generation processor.
+## Please refer to Processor BWG for detail.
+##
+gSiPkgTokenSpaceGuid.PcdBiosAreaBaseAddress|0xFF800000|UINT32|0x10000001
+gSiPkgTokenSpaceGuid.PcdBiosSize|0x00800000|UINT32|0x10000002
+gSiPkgTokenSpaceGuid.PcdTemporaryRamBase|0xfef00000|UINT32|0x00010028
+gSiPkgTokenSpaceGuid.PcdTemporaryRamSize|0x2000|UINT32|0x00010029
+gSiPkgTokenSpaceGuid.PcdTopMemoryCacheSize|0x0|UINT32|0x0001002A
+gSiPkgTokenSpaceGuid.PcdFlashMicrocodeOffset|0x00000060|UINT32|0x30000013
+
+gSiPkgTokenSpaceGuid.PcdFspWrapperEnable |FALSE|BOOLEAN|0x3000000F
+
+
+#
+# PCD is using for SOC core boot
+#
+
+#
+# PCD is using for AlderLakeL P/M/S
+# True: ADL-P/M
+# False: ADL-S
+#
+gSiPkgTokenSpaceGuid.PcdAdlLpSupport|TRUE|BOOLEAN|0x30000014
+
+#
+# PCD is using for AlderLakeL S
+#
+gSiPkgTokenSpaceGuid.PcdAdlSSupport|FALSE|BOOLEAN|0x30000015
+
+##
+## PcdEfiGcdAllocateType is using for EFI_GCD_ALLOCATE_TYPE selection
+## value of the struct
+## 0x00 EfiGcdAllocateAnySearchBottomUp
+## 0x01 EfiGcdAllocateMaxAddressSearchBottomUp
+## 0x03 EfiGcdAllocateAnySearchTopDown
+## 0x04 EfiGcdAllocateMaxAddressSearchTopDown
+##
+## below value should not using in this situation
+## 0x05 EfiGcdMaxAllocateType : design for max value of struct
+## 0x02 EfiGcdAllocateAddress : design for speccification address allocate
+##
+gSiPkgTokenSpaceGuid.PcdEfiGcdAllocateType|0x01|UINT8|0x40000000
+
+
+##
+## Those PCDs are used to control build process.
+##
+gSiPkgTokenSpaceGuid.PcdSmmVariableEnable |TRUE |BOOLEAN|0xF0000002
+gSiPkgTokenSpaceGuid.PcdAcpiEnable |TRUE |BOOLEAN|0xF0000009
+gSiPkgTokenSpaceGuid.PcdSourceDebugEnable |FALSE|BOOLEAN|0xF000000B
+gSiPkgTokenSpaceGuid.PcdTxtEnable |FALSE|BOOLEAN|0xF000000D
+
+gSiPkgTokenSpaceGuid.PcdSmbiosEnable |TRUE |BOOLEAN|0xF0000014
+gSiPkgTokenSpaceGuid.PcdIgdEnable |TRUE |BOOLEAN|0xF000001A
+gSiPkgTokenSpaceGuid.PcdSaDmiEnable |TRUE |BOOLEAN|0xF000001C
+gSiPkgTokenSpaceGuid.PcdBdatEnable |TRUE |BOOLEAN|0xF0000023
+gSiPkgTokenSpaceGuid.PcdOptimizeCompilerEnable |TRUE |BOOLEAN|0xF0000024
+gSiPkgTokenSpaceGuid.PcdPeiDisplayEnable |TRUE |BOOLEAN|0xF0000025
+gSiPkgTokenSpaceGuid.PcdSerialIoUartEnable |TRUE |BOOLEAN|0xF0000033
+gSiPkgTokenSpaceGuid.PcdSiCatalogDebugEnable |FALSE|BOOLEAN|0xF0000037
+
+gSiPkgTokenSpaceGuid.PcdCpuPcieEnable |TRUE |BOOLEAN|0xF0000043
+gSiPkgTokenSpaceGuid.PcdMrcTraceMessageSupported |TRUE |BOOLEAN|0xF0000045
+
+[PcdsDynamic, PcdsPatchableInModule]
+## Default OEM Table ID for ACPI table creation, it is "EDK2 ".
+gSiPkgTokenSpaceGuid.PcdAcpiDefaultOemTableId|0x20202020324B4445|UINT64|0x30001035
+
+[PcdsFixedAtBuild, PcdsPatchableInModule]
+## This value is used to set the base address of PCH devices
+gSiPkgTokenSpaceGuid.PcdSmbusBaseAddress|0x0000EFA0|UINT16|0x00010031
+gSiPkgTokenSpaceGuid.PcdTcoBaseAddress|0x0400|UINT16|0x00010033
+gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress|0x1800|UINT16|0x00010035
+
+##
+## FSP
+##
+## The PCD value here are either dummy or generic for all platforms
+## Some of them are expected to have different value in platform FSP package DSC.
+##
+## Examples:
+## PcdFspImageIdString, PcdFspVersionRevision, PcdFspVersionBuild, PcdFspVersionMinor
+##
+gSiPkgTokenSpaceGuid.PcdFspImageIdString |0x0|UINT64|0x0001005A
+gSiPkgTokenSpaceGuid.PcdFspVersionRevision |0x00|UINT8|0x0001005C
+gSiPkgTokenSpaceGuid.PcdFspVersionBuild |0x00|UINT8|0x0001005D
+gSiPkgTokenSpaceGuid.PcdFspVersionMinor |0x00|UINT8|0x0001005E
+
+
+## This value is used to set the base address of MCH
+gSiPkgTokenSpaceGuid.PcdMchBaseAddress|0xFEDC0000|UINT64|0x00010030
+
+##
+## Allocate 56 KB [0x2000..0xFFFF] of I/O space for Pci Devices
+## If PcdPciReservedMemLimit =0 Pci Reserved default MMIO Limit is 0xE0000000 else use PcdPciReservedMemLimit .
+##
+gSiPkgTokenSpaceGuid.PcdPciReservedMemLimit |0x0000 |UINT32|0x00010043
+
+##
+## Default 8MB TSEG for Release build BIOS when IED disabled (Also a default)
+##
+gSiPkgTokenSpaceGuid.PcdTsegSize|0x00800000|UINT32|0x00010046
+
+##
+## Silicon Reference Code versions
+##
+gSiPkgTokenSpaceGuid.PcdSiliconInitVersionMajor |0x0C|UINT8|0x00010049
+
+##Minor:the program that supported by same core generation.
+gSiPkgTokenSpaceGuid.PcdSiliconInitVersionMinor |0x00|UINT8|0x00010050
+
+##Revision:Weekly build number
+gSiPkgTokenSpaceGuid.PcdSiliconInitVersionRevision|0x82|UINT8|0x00010051
+
+##Build[7:4]:Daily build number.
+##Build[3:0]:Patch build number.
+
+gSiPkgTokenSpaceGuid.PcdSiliconInitVersionBuild |0x30|UINT8|0x00010052
+
+
+
+##
+## This PCD specifies the base address of the HPET timer.
+## The acceptable values are 0xFED00000, 0xFED01000, 0xFED02000, and 0xFED03000
+##
+gSiPkgTokenSpaceGuid.PcdSiHpetBaseAddress |0xFED00000|UINT32|0x00010057
+##
+## This PCD specifies the base address of the IO APIC.
+## The acceptable values are 0xFECxx000.
+##
+gSiPkgTokenSpaceGuid.PcdSiIoApicBaseAddress |0xFEC00000|UINT32|0x00010058
+
+[PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx]
+##
+## SerialIo Uart Configuration
+##
+gSiPkgTokenSpaceGuid.PcdSerialIoUartDebugEnable |0 |UINT8 |0x00210001 # 0:Disable, 1:Enable and Initialize, 2:Enable without Initializing
+gSiPkgTokenSpaceGuid.PcdSerialIoUartNumber |2 |UINT8 |0x00210002
+gSiPkgTokenSpaceGuid.PcdSerialIoUartMode |2 |UINT8 |0x00210003 # 0:Disabled, 1:Enabled, 2:Hidden, 3:COM, 4:SkipInit
+gSiPkgTokenSpaceGuid.PcdSerialIoUartBaudRate |115200 |UINT32|0x00210004 # 0:Default, Max:6000000
+gSiPkgTokenSpaceGuid.PcdSerialIoUartParity |1 |UINT8 |0x00210008 # 0:DefaultParity, 1:NoParity, 2:EvenParity, 3:OddParity
+gSiPkgTokenSpaceGuid.PcdSerialIoUartDataBits |8 |UINT8 |0x00210009 # 0:Default, 5,6,7,8
+gSiPkgTokenSpaceGuid.PcdSerialIoUartStopBits |1 |UINT8 |0x0021000A # 0:DefaultStopBits, 1:OneStopBit, 2:OneFiveStopBits, 3:TwoStopBits
+gSiPkgTokenSpaceGuid.PcdSerialIoUartAutoFlow |0 |UINT8 |0x0021000B # 0:No HW flow control, Only RX/TX Enabled; 1:HW Flow Control On, Rts/Cts lines enabled;
+gSiPkgTokenSpaceGuid.PcdSerialIoUartRxPinMux |0x0 |UINT32|0x0021000C # Pin muxing config for UART Rx pin
+gSiPkgTokenSpaceGuid.PcdSerialIoUartTxPinMux |0x0 |UINT32|0x00210010 # Pin muxing config for UART Tx pin
+gSiPkgTokenSpaceGuid.PcdSerialIoUartRtsPinMux |0x0 |UINT32|0x00210014 # Pin muxing config for UART Rts pin
+gSiPkgTokenSpaceGuid.PcdSerialIoUartCtsPinMux |0x0 |UINT32|0x00210018 # Pin muxing config for UART Cts pin
+gSiPkgTokenSpaceGuid.PcdSerialIoUartDebugMmioBase |0xFE036000 |UINT32|0x0021001C # PcdSerialIoUartMode = Enabled, need to assign MMIO Resource in SEC/PEI Phase
+
+gSiPkgTokenSpaceGuid.PcdLpcUartDebugEnable |0x1 |UINT8 |0x00210026 # 0:Disable, 1:Enable
+gSiPkgTokenSpaceGuid.PcdDebugInterfaceFlags |0x12 |UINT8 |0x00210027 # BIT0-RAM, BIT1-UART, BIT3-USB3, BIT4-Serial IO, BIT5-TraceHub, BIT2 - Not used.
+gSiPkgTokenSpaceGuid.PcdSerialDebugLevel |0x3 |UINT8 |0x00210028 # {0:Disable, 1:Error Only, 2:Error and Warnings, 3:Load Error Warnings and Info, 4:Load Error Warnings and Info, 5:Load Error Warnings Info and Verbose
+gSiPkgTokenSpaceGuid.PcdIsaSerialUartBase |0x0 |UINT8 |0x00210029 # 0:0x3F8, 1:0x2F8
+
+
+##
+## SerialIo 2nd Uart Configuration
+##
+gSiPkgTokenSpaceGuid.PcdSerialIo2ndUartEnable |0 |UINT8 |0x0021002A # 0:Disable, 1:Enable and Initialize, 2:Enable without Initializing
+gSiPkgTokenSpaceGuid.PcdSerialIo2ndUartNumber |2 |UINT8 |0x0021002B
+gSiPkgTokenSpaceGuid.PcdSerialIo2ndUartMode |2 |UINT8 |0x0021002C # 0:Disabled, 1:Enabled, 2:Hidden, 3:COM, 4:SkipInit
+gSiPkgTokenSpaceGuid.PcdSerialIo2ndUartBaudRate |115200 |UINT32|0x0021002D # 0:Default, Max:6000000
+gSiPkgTokenSpaceGuid.PcdSerialIo2ndUartParity |1 |UINT8 |0x00210031 # 0:DefaultParity, 1:NoParity, 2:EvenParity, 3:OddParity
+gSiPkgTokenSpaceGuid.PcdSerialIo2ndUartDataBits |8 |UINT8 |0x00210032 # 0:Default, 5,6,7,8
+gSiPkgTokenSpaceGuid.PcdSerialIo2ndUartStopBits |1 |UINT8 |0x00210033 # 0:DefaultStopBits, 1:OneStopBit, 2:OneFiveStopBits, 3:TwoStopBits
+gSiPkgTokenSpaceGuid.PcdSerialIo2ndUartAutoFlow |0 |UINT8 |0x00210034 # 0:No HW flow control, Only RX/TX Enabled; 1:HW Flow Control On, Rts/Cts lines enabled;
+gSiPkgTokenSpaceGuid.PcdSerialIo2ndUartRxPinMux |0x0 |UINT32|0x00210035 # Pin muxing config for UART Rx pin
+gSiPkgTokenSpaceGuid.PcdSerialIo2ndUartTxPinMux |0x0 |UINT32|0x00210039 # Pin muxing config for UART Tx pin
+gSiPkgTokenSpaceGuid.PcdSerialIo2ndUartRtsPinMux |0x0 |UINT32|0x0021003D # Pin muxing config for UART Rts pin
+gSiPkgTokenSpaceGuid.PcdSerialIo2ndUartCtsPinMux |0x0 |UINT32|0x00210041 # Pin muxing config for UART Cts pin
+gSiPkgTokenSpaceGuid.PcdSerialIo2ndUartMmioBase |0xFE034000 |UINT32|0x00210045 # PcdSerialIoUartMode = Enabled, need to assign MMIO Resource in SEC/PEI Phase
+
+##
+## PCI Express MMIO region length
+## Valid settings: 0x20000000/512MB, 0x10000000/256MB, 0x8000000/128MB, 0x4000000/64MB
+##
+gSiPkgTokenSpaceGuid.PcdPciExpressRegionLength|0x10000000|UINT32|0x00200001
+##
+## Typically this should be the same with gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress.
+## This PCD is added for supporting different PCD type in different phases.
+##
+gSiPkgTokenSpaceGuid.PcdSiPciExpressBaseAddress |0xC0000000|UINT64|0x00200002
+##
+## PCI Express MMIO temporary region length in SEC phase.
+## Valid settings: 0x20000000/512MB, 0x10000000/256MB, 0x8000000/128MB, 0x4000000/64MB
+##
+gSiPkgTokenSpaceGuid.PcdTemporaryPciExpressRegionLength|0x10000000|UINT32|0x00200005
--
2.36.1.windows.1
-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#108686): https://edk2.groups.io/g/devel/message/108686
Mute This Topic: https://groups.io/mt/101373955/7686176
Group Owner: devel+owner@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [rebecca@openfw.io]
-=-=-=-=-=-=-=-=-=-=-=-
^ permalink raw reply related [flat|nested] 41+ messages in thread
* Re: [edk2-devel] [PATCH v2 01/10] AlderlakeSiliconPkg/IpBlock: Add CpuPcieRp, Espi, Gpio components
2023-09-15 4:45 [edk2-devel] [PATCH v2 01/10] AlderlakeSiliconPkg/IpBlock: Add CpuPcieRp, Espi, Gpio components Saloni Kasbekar
` (8 preceding siblings ...)
2023-09-15 4:45 ` [edk2-devel] [PATCH v2 10/10] AlderlakeSiliconPkg: Add Alderlake Product and SiPkg.dec Saloni Kasbekar
@ 2023-09-15 5:42 ` Chaganty, Rangasai V
2023-09-15 13:27 ` Chuang, Rosen
2023-09-15 23:56 ` Nate DeSimone
2023-09-16 0:26 ` Nate DeSimone
11 siblings, 1 reply; 41+ messages in thread
From: Chaganty, Rangasai V @ 2023-09-15 5:42 UTC (permalink / raw)
To: Kasbekar, Saloni, devel@edk2.groups.io
Cc: Desimone, Nathaniel L, Chuang, Rosen
Reviewed-by: Sai Chaganty <rangasai.v.chaganty@intel.com>
-----Original Message-----
From: Kasbekar, Saloni <saloni.kasbekar@intel.com>
Sent: Thursday, September 14, 2023 9:46 PM
To: devel@edk2.groups.io
Cc: Kasbekar, Saloni <saloni.kasbekar@intel.com>; Chaganty, Rangasai V <rangasai.v.chaganty@intel.com>; Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>; Chuang, Rosen <rosen.chuang@intel.com>
Subject: [PATCH v2 01/10] AlderlakeSiliconPkg/IpBlock: Add CpuPcieRp, Espi, Gpio components
Adds the following modules:
- IpBlock/CpuPcieRp/Include
- IpBlock/Espi/Library
- IpBlock/Gpio/IncludePrivate
- IpBlock/Gpio/Library
- IpBlock/Gpio/LibraryPrivate
Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Rosen Chuang <rosen.chuang@intel.com>
Signed-off-by: Saloni Kasbekar <saloni.kasbekar@intel.com>
---
.../IpBlock/CpuPcieRp/Include/CpuPcieInfo.h | 25 +
.../Espi/Library/PeiDxeSmmEspiLib/EspiLib.c | 58 ++
.../PeiDxeSmmEspiLib/PeiDxeSmmEspiLib.inf | 38 ++
.../IncludePrivate/Library/GpioHelpersLib.h | 50 ++
.../IncludePrivate/Library/GpioNativePads.h | 245 ++++++++
.../IncludePrivate/Library/GpioPrivateLib.h | 350 +++++++++++
.../Gpio/Library/PeiDxeSmmGpioLib/GpioInit.c | 546 ++++++++++++++++++
.../Gpio/Library/PeiDxeSmmGpioLib/GpioLib.c | 522 +++++++++++++++++
.../Library/PeiDxeSmmGpioLib/GpioLibrary.h | 29 +
.../Library/PeiDxeSmmGpioLib/GpioNativeLib.c | 177 ++++++
.../PeiDxeSmmGpioLib/PeiDxeSmmGpioLib.inf | 44 ++
.../BaseGpioHelpersLibNull.c | 51 ++
.../BaseGpioHelpersLibNull.inf | 25 +
.../GpioNativePrivateLibInternal.h | 48 ++
.../PeiDxeSmmGpioPrivateLib/GpioPrivateLib.c | 267 +++++++++
.../GpioPrivateLibPch.c | 172 ++++++
.../GpioPrivateLibVer2.c | 81 +++
.../PeiDxeSmmGpioPrivateLibVer2.inf | 40 ++
.../PeiGpioHelpersLib/PeiGpioHelpersLib.c | 218 +++++++
.../PeiGpioHelpersLib/PeiGpioHelpersLib.inf | 46 ++
20 files changed, 3032 insertions(+)
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/CpuPcieRp/Include/CpuPcieInfo.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Espi/Library/PeiDxeSmmEspiLib/EspiLib.c
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Espi/Library/PeiDxeSmmEspiLib/PeiDxeSmmEspiLib.inf
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/IncludePrivate/Library/GpioHelpersLib.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/IncludePrivate/Library/GpioNativePads.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/IncludePrivate/Library/GpioPrivateLib.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/Library/PeiDxeSmmGpioLib/GpioInit.c
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/Library/PeiDxeSmmGpioLib/GpioLib.c
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/Library/PeiDxeSmmGpioLib/GpioLibrary.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/Library/PeiDxeSmmGpioLib/GpioNativeLib.c
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/Library/PeiDxeSmmGpioLib/PeiDxeSmmGpioLib.inf
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/BaseGpioHelpersLibNull/BaseGpioHelpersLibNull.c
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/BaseGpioHelpersLibNull/BaseGpioHelpersLibNull.inf
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiDxeSmmGpioPrivateLib/GpioNativePrivateLibInternal.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiDxeSmmGpioPrivateLib/GpioPrivateLib.c
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiDxeSmmGpioPrivateLib/GpioPrivateLibPch.c
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiDxeSmmGpioPrivateLib/GpioPrivateLibVer2.c
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiDxeSmmGpioPrivateLib/PeiDxeSmmGpioPrivateLibVer2.inf
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiGpioHelpersLib/PeiGpioHelpersLib.c
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiGpioHelpersLib/PeiGpioHelpersLib.inf
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/CpuPcieRp/Include/CpuPcieInfo.h b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/CpuPcieRp/Include/CpuPcieInfo.h
new file mode 100644
index 0000000000..a6f8b16d10
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/CpuPcieRp/Include/CpuPcieInfo.h
@@ -0,0 +1,25 @@
+/** @file
+ This file contains definitions of PCIe controller information
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _CPU_PCIE_INFO_H_
+#define _CPU_PCIE_INFO_H_
+
+#define PCIE_HWEQ_COEFFS_MAX 5
+
+
+//
+// SA PCI Express* Port configuration
+//
+
+#define CPU_PCIE_MAX_ROOT_PORTS 4
+#define CPU_PCIE_MAX_CONTROLLERS 3
+
+#define SA_PEG_MAX_FUN 0x04
+#define SA_PEG_MAX_LANE 0x14
+
+
+
+#endif
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Espi/Library/PeiDxeSmmEspiLib/EspiLib.c b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Espi/Library/PeiDxeSmmEspiLib/EspiLib.c
new file mode 100644
index 0000000000..2e4d1375ca
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Espi/Library/PeiDxeSmmEspiLib/EspiLib.c
@@ -0,0 +1,58 @@
+/** @file
+ This file contains routines for eSPI
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#include <Base.h>
+#include <Uefi/UefiBaseType.h>
+#include <Library/IoLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/EspiLib.h>
+#include <Library/PchPcrLib.h>
+#include <Library/PchInfoLib.h>
+#include <Library/TimerLib.h>
+#include <PchLimits.h>
+#include <Register/PchPcrRegs.h>
+#include <Register/PchRegsLpc.h>
+
+
+/**
+ Checks if second device capability is enabled
+
+ @retval TRUE There's second device
+ @retval FALSE There's no second device
+**/
+BOOLEAN
+IsEspiSecondSlaveSupported (
+ VOID
+ )
+{
+ return ((PchPcrRead32 (PID_ESPISPI, R_ESPI_PCR_SOFTSTRAPS) & B_ESPI_PCR_SOFTSTRAPS_CS1_EN) != 0);
+}
+
+
+/**
+ Is eSPI enabled in strap.
+
+ @retval TRUE Espi is enabled in strap
+ @retval FALSE Espi is disabled in strap
+**/
+BOOLEAN
+IsEspiEnabled (
+ VOID
+ )
+{
+ return (PchPcrRead32 (PID_ESPISPI, R_ESPI_PCR_CFG_VAL) & B_ESPI_PCR_CFG_VAL_ESPI_EN) != 0;
+}
+
+typedef enum {
+ EspiSlaveOperationConfigRead,
+ EspiSlaveOperationConfigWrite,
+ EspiSlaveOperationStatusRead,
+ EspiSlaveOperationInBandReset
+} ESPI_SLAVE_OPERATION;
+
+
+
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Espi/Library/PeiDxeSmmEspiLib/PeiDxeSmmEspiLib.inf b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Espi/Library/PeiDxeSmmEspiLib/PeiDxeSmmEspiLib.inf
new file mode 100644
index 0000000000..e8db1e4e8d
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Espi/Library/PeiDxeSmmEspiLib/PeiDxeSmmEspiLib.inf
@@ -0,0 +1,38 @@
+## @file
+# Component description file for the PeiDxeSmmPchEspiLib
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+
+[Defines]
+INF_VERSION = 0x00010017
+BASE_NAME = PeiDxeSmmEspiLib
+FILE_GUID = 7F25F990-7989-4413-B414-1EDE557E9389
+VERSION_STRING = 1.0
+MODULE_TYPE = BASE
+LIBRARY_CLASS = EspiLib
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = IA32 X64 IPF EBC
+#
+
+
+
+[LibraryClasses]
+BaseLib
+IoLib
+DebugLib
+PchPcrLib
+TimerLib
+
+
+[Packages]
+MdePkg/MdePkg.dec
+AlderlakeSiliconPkg/SiPkg.dec
+
+
+[Sources]
+EspiLib.c
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/IncludePrivate/Library/GpioHelpersLib.h b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/IncludePrivate/Library/GpioHelpersLib.h
new file mode 100644
index 0000000000..cf67c81ed0
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/IncludePrivate/Library/GpioHelpersLib.h
@@ -0,0 +1,50 @@
+/** @file
+ Header file for GPIO Helpers Lib implementation.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _GPIO_HELPERS_LIB_H_
+#define _GPIO_HELPERS_LIB_H_
+
+#include <Library/GpioConfig.h>
+
+/**
+ This procedure stores GPIO group data about pads which PadConfig needs to be unlocked.
+
+ @param[in] GroupIndex GPIO group index
+ @param[in] DwNum DWORD index for a group.
+ For group which has less then 32 pads per group DwNum must be 0.
+ @param[in] PadsToLock DWORD bitmask for pads which are going to be left unlocked
+ Bit position - PadNumber
+ Bit value - 0: Skip, 1: Leave unlocked
+
+ @retval Status
+**/
+EFI_STATUS
+GpioStoreGroupDwUnlockPadConfigData (
+ IN UINT32 GroupIndex,
+ IN UINT32 DwNum,
+ IN UINT32 UnlockedPads
+ );
+
+/**
+ This procedure stores GPIO group data about pads which Output state needs to be unlocked.
+
+ @param[in] GroupIndex GPIO group index
+ @param[in] DwNum DWORD index for a group.
+ For group which has less then 32 pads per group DwNum must be 0.
+ @param[in] PadsToLock DWORD bitmask for pads which are going to be left unlocked
+ Bit position - PadNumber
+ Bit value - 0: Skip, 1: Leave unlocked
+
+ @retval Status
+**/
+EFI_STATUS
+GpioStoreGroupDwUnlockOutputData (
+ IN UINT32 GroupIndex,
+ IN UINT32 DwNum,
+ IN UINT32 UnlockedPads
+ );
+
+#endif // _GPIO_HELPERS_LIB_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/IncludePrivate/Library/GpioNativePads.h b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/IncludePrivate/Library/GpioNativePads.h
new file mode 100644
index 0000000000..dbd13963fa
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/IncludePrivate/Library/GpioNativePads.h
@@ -0,0 +1,245 @@
+/** @file
+ Header file for GPIO Native pads support
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _GPIO_NATIVE_PADS_H_
+#define _GPIO_NATIVE_PADS_H_
+
+//
+// GpioPad can contain additional information used to provide data on
+// native functions. Please refer to description of GPIO_NATIVE_PAD
+//
+// FFFF CCCC TTTG GGGG TTTT TTTP PPPP PPPP
+//
+// F - 2^4 = 16, native function number
+// C - 2^4 = 16, chipset ID
+// T - 2^10 = 1024 , abstract type representing native mode of a pad (e.g. SERIALIO_UART2_TX)
+// G - 2^5 = 32, group
+// P - 2^9 = 512, pad number
+//
+// F & T contain additional optional settings used for native pads
+//
+#define GPIO_NATIVE_PAD_DEF(GpioNativePad, NativeMode, NativeFunction) \
+ (GpioNativePad | (NativeMode << 28) | ((NativeFunction & 0x7F) << 9) | ((NativeFunction & 0x380) << 14))
+
+#define GPIO_NATIVE_GET_FUNCTION(GpioNativePad) ((((GpioNativePad) & 0xFE00) >> 9) | (((GpioNativePad) & 0xE00000) >> 14))
+#define GPIO_NATIVE_GET_PAD_FN(GpioNativePad) (((GpioNativePad) >> 28) & 0xF)
+#define GPIO_NATIVE_GET_PAD_MODE(GpioNativePad) ((GPIO_NATIVE_GET_PAD_FN(GpioNativePad) << 1) | 1)
+#define GPIO_NATIVE_TO_GPIO_PAD(GpioNativePad) (GpioNativePad & 0xF1F01FF)
+
+//
+// Below defines and macros are used to build abstract type
+// to help encode native pin information in GPIO_PAD
+//
+
+//
+// Macro used to define GPIO native function.
+// <Min,Max> defines range that can be used to encode given native signal.
+// Numbering must be unique and cannot overlap.
+// If there are many instances of similar signal (e.g. per controller) the lower
+// word will store value for a given instance in the form: Min + Instance
+// Upper word (Max) is left untouched and later used for verification
+//
+#define GPIO_NATIVE_FUNCTION_DEF(Min, Max) (((Max) << 16) + (Min))
+#define GPIO_NATIVE_FUNCTION_GET_MAX(NativeFunction) (((NativeFunction) >> 16) & 0xFFFF)
+#define GPIO_NATIVE_FUNCTION_GET_VALUE(NativeFunction) ((NativeFunction) & 0xFFFF)
+
+//
+// Macro GPIO_NATIVE_FUNCTION_GET_SIGNAL is created as synonym to macro GPIO_NATIVE_FUNCTION_GET_MAX
+// GPIO_NATIVE_FUNCTION_GET_SIGNAL used with below defines is more descriptive and easier to read
+// ex.
+// - GPIO_NATIVE_FUNCTION_GET_SIGNAL(GPIO_SERIAL_IO_UART_RX)
+// - GPIO_NATIVE_FUNCTION_GET_SIGNAL(GPIO_ISH_GP)
+// - ...
+//
+#define GPIO_NATIVE_FUNCTION_GET_SIGNAL(NativeFunction) (GPIO_NATIVE_FUNCTION_GET_MAX(NativeFunction))
+
+//
+// GPIO native modes
+// Those defines are internal to this header.
+// GPIO_FUNCTION_<IP>_<signal>(index) defines should be used by other modules instead.
+//
+#define GPIO_SERIAL_IO_UART_RX GPIO_NATIVE_FUNCTION_DEF(1,8)
+#define GPIO_SERIAL_IO_UART_TX GPIO_NATIVE_FUNCTION_DEF(9,16)
+#define GPIO_SERIAL_IO_UART_RTS GPIO_NATIVE_FUNCTION_DEF(17,24)
+#define GPIO_SERIAL_IO_UART_CTS GPIO_NATIVE_FUNCTION_DEF(25,31)
+#define GPIO_SERIAL_IO_SPI_MOSI GPIO_NATIVE_FUNCTION_DEF(32,39)
+#define GPIO_SERIAL_IO_SPI_MISO GPIO_NATIVE_FUNCTION_DEF(40,47)
+#define GPIO_SERIAL_IO_SPI_CLK GPIO_NATIVE_FUNCTION_DEF(48,55)
+#define GPIO_SERIAL_IO_SPI_CS GPIO_NATIVE_FUNCTION_DEF(56,71)
+#define GPIO_ISH_GP GPIO_NATIVE_FUNCTION_DEF(80,143)
+#define GPIO_ISH_UART_RX GPIO_NATIVE_FUNCTION_DEF(144,151)
+#define GPIO_ISH_UART_TX GPIO_NATIVE_FUNCTION_DEF(152,159)
+#define GPIO_ISH_UART_RTS GPIO_NATIVE_FUNCTION_DEF(160,167)
+#define GPIO_ISH_UART_CTS GPIO_NATIVE_FUNCTION_DEF(168,175)
+#define GPIO_ISH_SPI_MOSI GPIO_NATIVE_FUNCTION_DEF(184,191)
+#define GPIO_ISH_SPI_MISO GPIO_NATIVE_FUNCTION_DEF(192,199)
+#define GPIO_ISH_SPI_CLK GPIO_NATIVE_FUNCTION_DEF(200,207)
+#define GPIO_ISH_SPI_CS GPIO_NATIVE_FUNCTION_DEF(208,223)
+#define GPIO_ISH_I2C_SCL GPIO_NATIVE_FUNCTION_DEF(232,239)
+#define GPIO_ISH_I2C_SDA GPIO_NATIVE_FUNCTION_DEF(240,247)
+#define GPIO_THC_SPI_INT GPIO_NATIVE_FUNCTION_DEF(248,251)
+#define GPIO_DMIC_DATA GPIO_NATIVE_FUNCTION_DEF(258,261)
+#define GPIO_DMIC_CLKA GPIO_NATIVE_FUNCTION_DEF(262,265)
+#define GPIO_DMIC_CLKB GPIO_NATIVE_FUNCTION_DEF(266,269)
+#define GPIO_DDSP_HPD0 GPIO_NATIVE_FUNCTION_DEF(270,285)
+#define GPIO_PANEL_AVDD_EN GPIO_NATIVE_FUNCTION_DEF(286,289)
+#define GPIO_PANEL_BKLTEN GPIO_NATIVE_FUNCTION_DEF(290,293)
+#define GPIO_PANEL_BKLTCTL GPIO_NATIVE_FUNCTION_DEF(294,297)
+#define GPIO_PANEL_RESET GPIO_NATIVE_FUNCTION_DEF(298,301)
+#define GPIO_PANEL_AVEE_EN GPIO_NATIVE_FUNCTION_DEF(302,305)
+#define GPIO_PANEL_VIO_EN GPIO_NATIVE_FUNCTION_DEF(306,309)
+#define GPIO_PANEL_HPD GPIO_NATIVE_FUNCTION_DEF(310,313)
+#define GPIO_PANEL_TE_EN GPIO_NATIVE_FUNCTION_DEF(314,317)
+#define GPIO_HDMI_GMBUS_SCL GPIO_NATIVE_FUNCTION_DEF(318,325)
+#define GPIO_HDMI_GMBUS_SDA GPIO_NATIVE_FUNCTION_DEF(326,333)
+#define GPIO_SERIAL_IO_I2C_SCL GPIO_NATIVE_FUNCTION_DEF(338,353)
+#define GPIO_SERIAL_IO_I2C_SDA GPIO_NATIVE_FUNCTION_DEF(354,369)
+#define GPIO_SD_DATA GPIO_NATIVE_FUNCTION_DEF(374,377)
+#define GPIO_EMMC_DATA GPIO_NATIVE_FUNCTION_DEF(384,391)
+#define GPIO_THC_CLK_LOOPBACK GPIO_NATIVE_FUNCTION_DEF(395,396)
+#define GPIO_MIPI_PANEL_RESET GPIO_NATIVE_FUNCTION_DEF(401,404)
+#define GPIO_MIPI_SEC_POW_EN_AVEE GPIO_NATIVE_FUNCTION_DEF(405,408)
+#define GPIO_MIPI_SEC_POW_EN_AVDD GPIO_NATIVE_FUNCTION_DEF(409,412)
+#define GPIO_THC_WOT GPIO_NATIVE_FUNCTION_DEF(413,414)
+#define GPIO_SATA_DEVSLP GPIO_NATIVE_FUNCTION_DEF(415,446)
+#define GPIO_PCIE_CLKREQ GPIO_NATIVE_FUNCTION_DEF(447,478)
+
+//
+// Serial IO UART
+//
+
+#define GPIO_FUNCTION_SERIAL_IO_UART_RX(UartDev) (GPIO_SERIAL_IO_UART_RX + ((UINT32)UartDev))
+#define GPIO_FUNCTION_SERIAL_IO_UART_TX(UartDev) (GPIO_SERIAL_IO_UART_TX + ((UINT32)UartDev))
+#define GPIO_FUNCTION_SERIAL_IO_UART_RTS(UartDev) (GPIO_SERIAL_IO_UART_RTS + ((UINT32)UartDev))
+#define GPIO_FUNCTION_SERIAL_IO_UART_CTS(UartDev) (GPIO_SERIAL_IO_UART_CTS + ((UINT32)UartDev))
+
+//
+// Serial IO SPI
+//
+#define GPIO_SERIAL_IO_SPI_RANGE 8 // Number of SerialIo SPIx controllers supported in GPIO_NATIVE_PAD encoding
+
+#define GPIO_FUNCTION_SERIAL_IO_SPI_MOSI(SpiDev) (GPIO_SERIAL_IO_SPI_MOSI + ((UINT32)SpiDev))
+#define GPIO_FUNCTION_SERIAL_IO_SPI_MISO(SpiDev) (GPIO_SERIAL_IO_SPI_MISO + ((UINT32)SpiDev))
+#define GPIO_FUNCTION_SERIAL_IO_SPI_CLK(SpiDev) (GPIO_SERIAL_IO_SPI_CLK + ((UINT32)SpiDev))
+#define GPIO_FUNCTION_SERIAL_IO_SPI_CS(SpiDev, CsNum) (GPIO_SERIAL_IO_SPI_CS + ((UINT32)SpiDev) + ((UINT32)CsNum) * GPIO_SERIAL_IO_SPI_RANGE)
+
+//
+// Serial IO I2C
+//
+
+#define GPIO_FUNCTION_SERIAL_IO_I2C_SCL(I2cDev) (GPIO_SERIAL_IO_I2C_SCL + ((UINT32)I2cDev))
+#define GPIO_FUNCTION_SERIAL_IO_I2C_SDA(I2cDev) (GPIO_SERIAL_IO_I2C_SDA + ((UINT32)I2cDev))
+
+//
+// ISH GP
+//
+
+#define GPIO_FUNCTION_ISH_GP(GpNum) (GPIO_ISH_GP + ((UINT32)GpNum))
+
+//
+// ISH UART
+//
+
+#define GPIO_FUNCTION_ISH_UART_RX(UartDev) (GPIO_ISH_UART_RX + ((UINT32)UartDev))
+#define GPIO_FUNCTION_ISH_UART_TX(UartDev) (GPIO_ISH_UART_TX + ((UINT32)UartDev))
+#define GPIO_FUNCTION_ISH_UART_RTS(UartDev) (GPIO_ISH_UART_RTS + ((UINT32)UartDev))
+#define GPIO_FUNCTION_ISH_UART_CTS(UartDev) (GPIO_ISH_UART_CTS + ((UINT32)UartDev))
+
+//
+// ISH SPI
+//
+#define GPIO_ISH_SPI_RANGE 8 // Number of ISH SPI controllers supported in GPIO_NATIVE_PAD encoding
+
+#define GPIO_FUNCTION_ISH_SPI_MOSI(SpiDev) (GPIO_ISH_SPI_MOSI + ((UINT32)SpiDev))
+#define GPIO_FUNCTION_ISH_SPI_MISO(SpiDev) (GPIO_ISH_SPI_MISO + ((UINT32)SpiDev))
+#define GPIO_FUNCTION_ISH_SPI_CLK(SpiDev) (GPIO_ISH_SPI_CLK + ((UINT32)SpiDev))
+#define GPIO_FUNCTION_ISH_SPI_CS(SpiDev, CsNum) (GPIO_ISH_SPI_CS + ((UINT32)SpiDev) + ((UINT32)CsNum) * GPIO_ISH_SPI_RANGE)
+
+//
+// ISH I2C
+//
+
+#define GPIO_FUNCTION_ISH_I2C_SCL(I2cDev) (GPIO_ISH_I2C_SCL + ((UINT32)I2cDev))
+#define GPIO_FUNCTION_ISH_I2C_SDA(I2cDev) (GPIO_ISH_I2C_SDA + ((UINT32)I2cDev))
+
+//
+// SD Card
+//
+#define GPIO_FUNCTION_SD_DATA(Index) (GPIO_SD_DATA + ((UINT32)Index))
+
+//
+// EMMC
+//
+#define GPIO_FUNCTION_EMMC_DATA(Index) (GPIO_EMMC_DATA + ((UINT32)Index))
+
+//
+// THC SPI
+//
+
+#define GPIO_FUNCTION_THC_SPI_INT(SpiDev) (GPIO_THC_SPI_INT + ((UINT32)SpiDev))
+#define GPIO_FUNCTION_THC_CLK_LOOPBACK(SpiDev) (GPIO_THC_CLK_LOOPBACK + ((UINT32)SpiDev))
+#define GPIO_FUNCTION_THC_WOT(SpiDev) (GPIO_THC_WOT + ((UINT32)SpiDev))
+
+
+//
+// DMIC
+//
+
+#define GPIO_FUNCTION_DMIC_DATA(DmicDev) (GPIO_DMIC_DATA + ((UINT32)DmicDev))
+#define GPIO_FUNCTION_DMIC_CLKA(DmicDev) (GPIO_DMIC_CLKA + ((UINT32)DmicDev))
+#define GPIO_FUNCTION_DMIC_CLKB(DmicDev) (GPIO_DMIC_CLKB + ((UINT32)DmicDev))
+#define GPIO_FUNCTION_DMIC_CLK(DmicDev) (GPIO_DMIC_CLKA + ((UINT32)DmicDev)) // If there is no split between channel A/B use A range for such Clocks
+
+
+//
+// DDSP HPD
+//
+
+#define GPIO_FUNCTION_DDSP_HPD(HpdIndex) \
+ (HpdIndex > 7) ? GPIO_DDSP_HPD0 + 8 + (HpdIndex) - 'A' : GPIO_DDSP_HPD0 + HpdIndex
+
+//
+// HDMI_GMBUS
+//
+
+#define GPIO_FUNCTION_HDMI_SCL(DdiPort) (GPIO_HDMI_GMBUS_SCL + ((UINT32)DdiPort))
+#define GPIO_FUNCTION_HDMI_SDA(DdiPort) (GPIO_HDMI_GMBUS_SDA + ((UINT32)DdiPort))
+
+//
+// Panel
+//
+
+#define GPIO_FUNCTION_PANEL_AVDD_EN(PanelDev) (GPIO_PANEL_AVDD_EN + ((UINT32)PanelDev))
+#define GPIO_FUNCTION_PANEL_BKLTEN(PanelDev) (GPIO_PANEL_BKLTEN + ((UINT32)PanelDev))
+#define GPIO_FUNCTION_PANEL_BKLTCTL(PanelDev) (GPIO_PANEL_BKLTCTL + ((UINT32)PanelDev))
+#define GPIO_FUNCTION_PANEL_RESET(PanelDev) (GPIO_PANEL_RESET + ((UINT32)PanelDev))
+#define GPIO_FUNCTION_PANEL_AVEE_EN(PanelDev) (GPIO_PANEL_AVEE_EN + ((UINT32)PanelDev))
+#define GPIO_FUNCTION_PANEL_VIO_EN(PanelDev) (GPIO_PANEL_VIO_EN + ((UINT32)PanelDev))
+#define GPIO_FUNCTION_PANEL_HPD(PanelDev) (GPIO_PANEL_HPD + ((UINT32)PanelDev))
+#define GPIO_FUNCTION_PANEL_TE_EN(PanelDev) (GPIO_PANEL_TE_EN + ((UINT32)PanelDev))
+
+//
+// MIPI
+//
+#define GPIO_FUNCTION_MIPI_PANEL_RESET(PanelDev) (GPIO_MIPI_PANEL_RESET + ((UINT32)PanelDev))
+#define GPIO_FUNCTION_MIPI_SEC_POW_EN_AVEE(PanelDev) (GPIO_MIPI_SEC_POW_EN_AVEE + ((UINT32)PanelDev))
+#define GPIO_FUNCTION_MIPI_SEC_POW_EN_AVDD(PanelDev) (GPIO_MIPI_SEC_POW_EN_AVDD + ((UINT32)PanelDev))
+
+
+//
+// SATA DevSlp
+//
+#define GPIO_SATA_DEVSLP_RANGE 32 // Number of SATA DevSlp instances per controller supported in GPIO_NATIVE_PAD encoding
+
+#define GPIO_FUNCTION_SATA_DEVSLP(CsNum, SataDevSlpIndex) (GPIO_SATA_DEVSLP + ((UINT32)SataDevSlpIndex) + ((UINT32)CsNum) * GPIO_SATA_DEVSLP_RANGE)
+
+//
+// SRC CLKREQ
+//
+
+#define GPIO_FUNCTION_PCIE_CLKREQ(ClkReqIndex) (GPIO_PCIE_CLKREQ + ((UINT32)ClkReqIndex))
+
+#endif // _GPIO_NATIVE_PADS_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/IncludePrivate/Library/GpioPrivateLib.h b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/IncludePrivate/Library/GpioPrivateLib.h
new file mode 100644
index 0000000000..a757a4b057
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/IncludePrivate/Library/GpioPrivateLib.h
@@ -0,0 +1,350 @@
+/** @file
+ Header file for GpioPrivateLib.
+ All function in this library is available for PEI, DXE, and SMM,
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _GPIO_PRIVATE_LIB_H_
+#define _GPIO_PRIVATE_LIB_H_
+
+#include <Uefi/UefiBaseType.h>
+#include <Library/GpioConfig.h>
+#include <Library/PchPcrLib.h>
+
+/**
+ GPIO Standby State configuration
+ Standby State options for GPIO Pads
+**/
+typedef enum {
+ GpioIosStateDefault = 0x0,
+ GpioIosStateLatchLastValue = (0x0 << 1) | 0x01, ///< Latch last value driven on TX, TX Enable and RX Enable
+ GpioIosStateTx0Rx0RxDis = (0x1 << 1) | 0x01, ///< TX: 0, RX: 0 (internally), RX disabled
+ GpioIosStateTx0Rx1RxDis = (0x2 << 1) | 0x01, ///< TX: 0, RX: 1 (internally), RX disabled
+ GpioIosStateTx1Rx0RxDis = (0x3 << 1) | 0x01, ///< TX: 1, RX: 0 (internally), RX disabled
+ GpioIosStateTx1Rx1RxDis = (0x4 << 1) | 0x01, ///< TX: 1, RX: 1 (internally), RX disabled
+ GpioIosStateTx0RxEn = (0x5 << 1) | 0x01, ///< TX: 0, RX enabled
+ GpioIosStateTx1RxEn = (0x6 << 1) | 0x01, ///< TX: 1, RX enabled
+ GpioIosStateHizRx0 = (0x7 << 1) | 0x01, ///< Hi-Z, RX: 0 (internally)
+ GpioIosStateHizRx1 = (0x8 << 1) | 0x01, ///< Hi-Z, RX: 1 (internally)
+ GpioIosStateTxDisRxEn = (0x9 << 1) | 0x01, ///< TX Disabled and RX Enabled (i.e. wake or interrupt)
+ GpioIosStateMasked = (0xF << 1) | 0x01 ///< IO Standby signal is masked for this pad. In this mode, a pad operates as if IOStandby has not been asserted.
+} GPIO_IOSTANDBY_STATE;
+
+/**
+ GPIO Standby Term configuration
+ Standby Termination options for GPIO Pads
+**/
+typedef enum {
+ GpioIosTermDefault = 0x00,
+ GpioIosTermSame = (0x00 << 1) | 0x01, ///< Same as state specified in Term
+ GpioIosTermPuDisPdDis = (0x01 << 1) | 0x01, ///< Disable Pullup and Pulldown
+ GpioIosTermPuDisPdEn = (0x02 << 1) | 0x01, ///< Enable Pulldown
+ GpioIosTermPuEnPdDis = (0x03 << 1) | 0x01 ///< Enable Pullup
+} GPIO_IOSTANDBY_TERM;
+
+//
+// Structure for native pin data
+//
+typedef struct {
+ GPIO_PAD Pad;
+ GPIO_PAD_MODE Mode;
+ GPIO_IOSTANDBY_STATE IosState;
+ GPIO_IOSTANDBY_TERM IosTerm;
+} GPIO_PAD_NATIVE_FUNCTION;
+
+//
+// Structure for Serial GPIO pin definition
+//
+typedef struct {
+ GPIO_PAD_NATIVE_FUNCTION Sclock;
+ GPIO_PAD_NATIVE_FUNCTION Sload;
+ GPIO_PAD_NATIVE_FUNCTION Sdataout;
+} SGPIO_PINS;
+
+//
+// Structure for USB Virtual Wire OverCurrent Pad Mode group
+//
+typedef struct {
+ GPIO_PAD OcRxPad;
+ GPIO_PAD OcTxPad;
+} GPIO_VWOC_FUNCTION;
+
+//
+// Below defines are based on GPIO_CONFIG structure fields
+//
+#define B_GPIO_PAD_MODE_MASK 0xF
+#define N_GPIO_PAD_MODE_BIT_POS 0
+#define B_GPIO_DIRECTION_DIR_MASK 0x7
+#define N_GPIO_DIRECTION_DIR_BIT_POS 0
+#define B_GPIO_DIRECTION_INV_MASK 0x18
+#define N_GPIO_DIRECTION_INV_BIT_POS 3
+#define B_GPIO_OUTPUT_MASK 0x3
+#define N_GPIO_OUTPUT_BIT_POS 0
+#define N_GPIO_INT_CONFIG_INT_SOURCE_BIT_POS 0
+#define N_GPIO_INT_CONFIG_INT_TYPE_BIT_POS 5
+#define N_GPIO_ELECTRICAL_CONFIG_TERMINATION_BIT_POS 0
+#define N_GPIO_OTHER_CONFIG_RXRAW_BIT_POS 0
+
+//
+// Structure for storing information about registers offset, community,
+// maximal pad number for available groups
+//
+typedef struct {
+ PCH_SBI_PID Community;
+ UINT16 PadOwnOffset;
+ UINT16 HostOwnOffset;
+ UINT16 GpiIsOffset;
+ UINT16 GpiIeOffset;
+ UINT16 GpiGpeStsOffset;
+ UINT16 GpiGpeEnOffset;
+ UINT16 SmiStsOffset;
+ UINT16 SmiEnOffset;
+ UINT16 NmiStsOffset;
+ UINT16 NmiEnOffset;
+ UINT16 PadCfgLockOffset;
+ UINT16 PadCfgLockTxOffset;
+ UINT16 PadCfgOffset;
+ UINT16 PadPerGroup;
+} GPIO_GROUP_INFO;
+
+//
+// If in GPIO_GROUP_INFO structure certain register doesn't exist
+// it will have value equal to NO_REGISTER_FOR_PROPERTY
+//
+#define NO_REGISTER_FOR_PROPERTY 0xFFFF
+
+#define GPIO_PAD_DEF(Group,Pad) (UINT32)(((Group) << 16) + (Pad))
+#define GPIO_GROUP_DEF(GroupIndex,ChipsetId) ((GroupIndex) | ((ChipsetId) << 8))
+#define GPIO_GET_GROUP_INDEX(Group) ((Group) & 0x1F)
+#define GPIO_GET_GROUP_FROM_PAD(GpioPad) (((GpioPad) & 0x0F1F0000) >> 16)
+#define GPIO_GET_GROUP_INDEX_FROM_PAD(GpioPad) GPIO_GET_GROUP_INDEX (GPIO_GET_GROUP_FROM_PAD(GpioPad))
+#define GPIO_GET_PAD_NUMBER(GpioPad) ((GpioPad) & 0x1FF)
+#define GPIO_GET_CHIPSET_ID(GpioPad) (((GpioPad) >> 24) & 0xF)
+
+#define GPIO_GET_PAD_POSITION(PadNumber) ((PadNumber) % 32)
+#define GPIO_GET_DW_NUM(PadNumber) ((PadNumber) / 32u)
+
+/**
+ This procedure will retrieve address and length of GPIO info table
+
+ @param[out] GpioGroupInfoTableLength Length of GPIO group table
+
+ @retval Pointer to GPIO group table
+**/
+CONST GPIO_GROUP_INFO*
+GpioGetGroupInfoTable (
+ OUT UINT32 *GpioGroupInfoTableLength
+ );
+
+typedef struct {
+ CONST CHAR8* GpioGroupPrefix;
+ CONST GPIO_PAD FirstUniqueGpio;
+ CONST CHAR8** GroupUniqueNames;
+ CONST UINT32 UniqueNamesTableSize;
+} GPIO_GROUP_NAME_INFO;
+
+//
+// Helper macros for initializing GPIO_GROUP_NAME_INFO structures
+//
+#define GPIO_GROUP_NAME(GroupName,FirstUniqueGpio,GroupUniqueNamesTable) \
+ {GroupName, FirstUniqueGpio, GroupUniqueNamesTable, ARRAY_SIZE (GroupUniqueNamesTable)}
+
+#define GPIO_GROUP_NAME_BASIC(GroupName) \
+ {GroupName, 0, NULL, 0}
+
+/**
+ Get GPIO Chipset ID specific to PCH generation and series
+**/
+UINT32
+GpioGetThisChipsetId (
+ VOID
+ );
+
+/**
+ This procedure is used to check if GpioPad is valid for certain chipset
+
+ @param[in] GpioPad GPIO pad
+
+ @retval TRUE This pin is valid on this chipset
+ FALSE Incorrect pin
+**/
+BOOLEAN
+GpioIsCorrectPadForThisChipset (
+ IN GPIO_PAD GpioPad
+ );
+
+
+/**
+ This procedure is used by PchSmiDispatcher and will return information
+ needed to register GPI SMI.
+
+ @param[in] Index GPI SMI number
+ @param[out] GpioPin GPIO pin
+ @param[out] GpiSmiBitOffset GPI SMI bit position within GpiSmi Registers
+ @param[out] GpiHostSwOwnRegAddress Address of HOSTSW_OWN register
+ @param[out] GpiSmiStsRegAddress Address of GPI SMI status register
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid group or pad number
+**/
+EFI_STATUS
+GpioGetPadAndSmiRegs (
+ IN UINT32 Index,
+ OUT GPIO_PAD *GpioPin,
+ OUT UINT8 *GpiSmiBitOffset,
+ OUT UINT32 *GpiHostSwOwnRegAddress,
+ OUT UINT32 *GpiSmiStsRegAddress
+ );
+
+/**
+ This procedure calculates Pad Configuration Register DW offset
+
+ @param[in] GpioPad GPIO pad
+ @param[in] DwReg Index of the configuration register
+
+ @retval DW Register offset
+**/
+UINT32
+GpioGetGpioPadCfgAddressFromGpioPad (
+ IN GPIO_PAD GpioPad,
+ IN UINT32 DwReg
+ );
+
+
+/**
+ This procedure will check if GpioPad argument is valid.
+ Function will check below conditions:
+ - GpioPad represents a pad for current PCH
+ - GpioPad belongs to valid GpioGroup
+ - GPIO PadNumber is not greater than number of pads for this group
+
+ @param[in] GpioPad GPIO pad
+
+ @retval TRUE GPIO pad is valid and can be used with GPIO lib API
+ @retval FALSE GPIO pad is invalid and cannot be used with GPIO lib API
+**/
+BOOLEAN
+GpioIsPadValid (
+ IN GPIO_PAD GpioPad
+ );
+
+/**
+ This procedure will read GPIO Pad Configuration register
+
+ @param[in] GpioPad GPIO pad
+ @param[in] DwReg Choose PADCFG register: 0:DW0, 1:DW1
+
+ @retval PadCfgRegValue PADCFG_DWx value
+**/
+UINT32
+GpioReadPadCfgReg (
+ IN GPIO_PAD GpioPad,
+ IN UINT8 DwReg
+ );
+
+/**
+ Check if 0x13 opcode supported for writing to GPIO lock unlock register
+
+ @retval TRUE It's supported
+ @retval FALSE It's not supported
+**/
+BOOLEAN
+IsGpioLockOpcodeSupported (
+ VOID
+ );
+
+/**
+ Gpio Minimum Set
+
+ Set of Gpio Minimum function to use in Pre Mem phase.
+ To optimise execution and reduce memory footprint thse minimum version
+ of 'full' functions are stripped from:
+ - GpioPad PCH validation
+ - GpioPad Group belonging validation
+ - GpioPad Host ownership validation
+ - IoStandbyState configuration
+ The use of below functions has to be careful and with full
+ understanding of all pros and cons. Please refer to GpioPrivateLib.c
+ to familiarize with details of implementation.
+**/
+
+/**
+ This procedure reads GPIO register
+
+ @param[in] GpioGroupInfo Pointer to GPIO group table info
+ @param[in] Register Register offset
+
+ @retval Register value or "F"s in case of errors
+**/
+UINT32
+GpioRegisterAccessRead32 (
+ IN CONST GPIO_GROUP_INFO *GpioGroupInfo,
+ IN UINT32 Register
+ );
+
+/**
+ This procedure writes GPIO register
+
+ @param[in] GpioGroupInfo Pointer to GPIO group table info
+ @param[in] Register Register offset
+ @param[in] AndValue And value
+ @param[in] OrValue Or value
+
+ @retval EFI_DEVICE_ERROR vGPIO BAR not programmed
+ EFI_SUCCESS Operation completed successfully
+**/
+EFI_STATUS
+GpioRegisterAccessAndThenOr32 (
+ IN CONST GPIO_GROUP_INFO *GpioGroupInfo,
+ IN UINT32 Register,
+ IN UINT32 AndValue,
+ IN UINT32 OrValue
+ );
+
+/**
+ This procedure will calculate PADCFG register value based on GpioConfig data
+ The procedure can be various depending on chipset generation.
+ Available configuration options and corresponding registers fields
+ can distributed in different way in configuration registers.
+
+ @param[in] GpioPad GPIO Pad
+ @param[in] GpioConfig GPIO Configuration data
+ @param[out] PadCfgDwReg PADCFG DWx register value
+ @param[out] PadCfgDwRegMask Mask with PADCFG DWx register bits to be modified
+
+ @retval Status
+**/
+EFI_STATUS
+GpioPadCfgRegValueFromGpioConfig (
+ IN GPIO_PAD GpioPad,
+ IN CONST GPIO_CONFIG *GpioConfig,
+ OUT UINT32 *PadCfgDwReg,
+ OUT UINT32 *PadCfgDwRegMask
+ );
+
+/**
+ This procedure will write GPIO Lock/LockTx register
+ - For PCH SBI message is used.
+ - For IBL MMIO access is used.
+
+ @param[in] RegValue GPIO register (Lock or LockTx) value
+ @param[in] RegOffset GPIO register (Lock or LockTx) base offset
+ @param[in] DwNum Register number for current group.
+ For group which has less then 32 pads per group DwNum must be 0.
+ @param[in] GpioGroupInfo Pointer to GPIO group table info
+ @param[in] GroupIndex GPIO group index in the GpioGroupInfo table
+
+ @retval EFI_SUCCESS The function completed successfully
+ EFI_UNSUPPORTED Feature is not supported for this group or pad
+**/
+EFI_STATUS
+GpioInternalWriteLockRegister (
+ IN UINT32 RegValue,
+ IN UINT32 RegOffset,
+ IN UINT32 DwNum,
+ IN CONST GPIO_GROUP_INFO *GpioGroupInfo,
+ IN UINT32 GroupIndex
+ );
+
+#endif // _GPIO_PRIVATE_LIB_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/Library/PeiDxeSmmGpioLib/GpioInit.c b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/Library/PeiDxeSmmGpioLib/GpioInit.c
new file mode 100644
index 0000000000..cf6f92a50d
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/Library/PeiDxeSmmGpioLib/GpioInit.c
@@ -0,0 +1,546 @@
+/** @file
+ This file contains routines for GPIO initialization
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#include "GpioLibrary.h"
+
+//
+// GPIO_GROUP_DW_DATA structure is used by GpioConfigurePch function
+// to cache values which will be programmed into respective GPIO registers
+// after all GpioPads are processed. This way MMIO accesses are decreased
+// and instead of doing one programming for one GpioPad there is only
+// one access for whole register.
+//
+typedef struct {
+ UINT32 HostSoftOwnReg;
+ UINT32 HostSoftOwnRegMask;
+ UINT32 GpiGpeEnReg;
+ UINT32 GpiGpeEnRegMask;
+ UINT32 GpiNmiEnReg;
+ UINT32 GpiNmiEnRegMask;
+ UINT32 GpiSmiEnReg;
+ UINT32 GpiSmiEnRegMask;
+ UINT32 ConfigUnlockMask;
+ UINT32 OutputUnlockMask;
+} GPIO_GROUP_DW_DATA;
+
+//
+// GPIO_GROUP_DW_NUMBER contains number of DWords required to
+// store Pad data for all groups. Each pad uses one bit.
+//
+// For Cannonlake only vGPIO group has >32 pads but those pads
+// will not be accessed by this function so GPIO_GROUP_DW_NUMBER can be 1
+//
+#define GPIO_GROUP_DW_NUMBER 1
+
+/**
+ Get GPIO DW Register values (HOSTSW_OWN, GPE_EN, NMI_EN, Lock).
+
+ @param[in] PadNumber GPIO pad number
+ @param[in] GpioConfig GPIO Config data
+ @param[in out] DwRegsValues Values for GPIO DW Registers
+
+ @retval None
+**/
+STATIC
+VOID
+GpioDwRegValueFromGpioConfig (
+ IN UINT32 PadNumber,
+ IN CONST GPIO_CONFIG *GpioConfig,
+ IN OUT GPIO_GROUP_DW_DATA *GroupDwData
+ )
+{
+ UINT32 PadBitPosition;
+ UINT32 DwNum;
+
+ PadBitPosition = GPIO_GET_PAD_POSITION (PadNumber);
+ DwNum = GPIO_GET_DW_NUM (PadNumber);
+
+ if (DwNum >= GPIO_GROUP_DW_NUMBER) {
+ ASSERT (FALSE);
+ return;
+ }
+ //
+ // Update value to be programmed in HOSTSW_OWN register
+ //
+ GroupDwData[DwNum].HostSoftOwnRegMask |= (GpioConfig->HostSoftPadOwn & 0x1) << PadBitPosition;
+ GroupDwData[DwNum].HostSoftOwnReg |= (GpioConfig->HostSoftPadOwn >> 0x1) << PadBitPosition;
+
+ //
+ // Update value to be programmed in GPI_GPE_EN register
+ //
+ GroupDwData[DwNum].GpiGpeEnRegMask |= (GpioConfig->InterruptConfig & 0x1) << PadBitPosition;
+ GroupDwData[DwNum].GpiGpeEnReg |= ((GpioConfig->InterruptConfig & GpioIntSci) >> 3) << PadBitPosition;
+
+ //
+ // Update value to be programmed in GPI_NMI_EN register
+ //
+ GroupDwData[DwNum].GpiNmiEnRegMask |= (GpioConfig->InterruptConfig & 0x1) << PadBitPosition;
+ GroupDwData[DwNum].GpiNmiEnReg |= ((GpioConfig->InterruptConfig & GpioIntNmi) >> 1) << PadBitPosition;
+
+ //
+ // Update value to be programmed in GPI_SMI_EN register
+ GroupDwData[DwNum].GpiSmiEnRegMask |= (GpioConfig->InterruptConfig & 0x1) << PadBitPosition;
+ GroupDwData[DwNum].GpiSmiEnReg |= ((GpioConfig->InterruptConfig & GpioIntSmi) >> 2) << PadBitPosition;
+ if ((GpioConfig->InterruptConfig & GpioIntSmi) == GpioIntSmi) {
+ GroupDwData[DwNum].HostSoftOwnRegMask |= 1 << PadBitPosition;
+ GroupDwData[DwNum].HostSoftOwnReg |= 1 << PadBitPosition;
+ }
+
+ //
+ // Update information on Pad Configuration Lock
+ //
+ GroupDwData[DwNum].ConfigUnlockMask |= ((GpioConfig->LockConfig >> 1) & 0x1) << PadBitPosition;
+
+ //
+ // Update information on Pad Configuration Lock Tx
+ //
+ GroupDwData[DwNum].OutputUnlockMask |= ((GpioConfig->LockConfig >> 3) & 0x1) << PadBitPosition;
+
+ //
+ // if pad in GpioMode is an output default action should be to leave output unlocked
+ //
+ if ((GpioConfig->PadMode == GpioPadModeGpio) &&
+ (GpioConfig->Direction == GpioDirOut) &&
+ ((GpioConfig->LockConfig & B_GPIO_LOCK_CONFIG_OUTPUT_LOCK_MASK) == GpioLockDefault)) {
+ GroupDwData[DwNum].OutputUnlockMask |= 0x1 << PadBitPosition;
+ }
+}
+
+/**
+ This internal procedure will scan GPIO initialization table and unlock
+ all pads present in it
+
+ @param[in] NumberOfItem Number of GPIO pad records in table
+ @param[in] GpioInitTableAddress GPIO initialization table
+ @param[in] Index Index of GPIO Initialization table record
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid group or pad number
+**/
+STATIC
+EFI_STATUS
+GpioUnlockPadsForAGroup (
+ IN UINT32 NumberOfItems,
+ IN GPIO_INIT_CONFIG *GpioInitTableAddress,
+ IN UINT32 Index
+ )
+{
+ UINT32 PadsToUnlock[GPIO_GROUP_DW_NUMBER];
+ UINT32 DwNum;
+ UINT32 PadBitPosition;
+ CONST GPIO_GROUP_INFO *GpioGroupInfo;
+ UINT32 GpioGroupInfoLength;
+ CONST GPIO_INIT_CONFIG *GpioData;
+ GPIO_GROUP Group;
+ UINT32 GroupIndex;
+ UINT32 PadNumber;
+
+ GpioGroupInfo = GpioGetGroupInfoTable (&GpioGroupInfoLength);
+
+ GpioData = &GpioInitTableAddress[Index];
+ Group = GpioGetGroupFromGpioPad (GpioData->GpioPad);
+ GroupIndex = GpioGetGroupIndexFromGpioPad (GpioData->GpioPad);
+
+ ZeroMem (PadsToUnlock, sizeof (PadsToUnlock));
+ //
+ // Loop through pads for one group. If pad belongs to a different group then
+ // break and move to register programming.
+ //
+ while (Index < NumberOfItems) {
+
+ GpioData = &GpioInitTableAddress[Index];
+ if (GroupIndex != GpioGetGroupIndexFromGpioPad (GpioData->GpioPad)) {
+ //if next pad is from different group then break loop
+ break;
+ }
+
+ PadNumber = GpioGetPadNumberFromGpioPad (GpioData->GpioPad);
+ //
+ // Check if legal pin number
+ //
+ if (PadNumber >= GpioGroupInfo[GroupIndex].PadPerGroup) {
+ DEBUG ((DEBUG_ERROR, "GPIO ERROR: Pin number (%d) exceeds possible range for group %d\n", PadNumber, GroupIndex));
+ return EFI_INVALID_PARAMETER;
+ }
+
+ PadBitPosition = GPIO_GET_PAD_POSITION (PadNumber);
+ DwNum = GPIO_GET_DW_NUM (PadNumber);
+
+ if (DwNum >= GPIO_GROUP_DW_NUMBER) {
+ ASSERT (FALSE);
+ return EFI_UNSUPPORTED;
+ }
+ //
+ // Update pads which need to be unlocked
+ //
+ PadsToUnlock[DwNum] |= 0x1 << PadBitPosition;
+
+ //Move to next item
+ Index++;
+ }
+
+ for (DwNum = 0; DwNum <= GPIO_GET_DW_NUM (GpioGroupInfo[GroupIndex].PadPerGroup - 1); DwNum++) {
+ //
+ // Unlock pads
+ //
+ if (PadsToUnlock[DwNum] != 0) {
+ GpioUnlockPadCfgForGroupDw (Group, DwNum, PadsToUnlock[DwNum]);
+ GpioUnlockPadCfgTxForGroupDw (Group, DwNum, PadsToUnlock[DwNum]);
+ }
+ }
+
+ return EFI_SUCCESS;
+}
+
+/**
+ This procedure will initialize multiple PCH GPIO pins
+
+ @param[in] NumberofItem Number of GPIO pads to be updated
+ @param[in] GpioInitTableAddress GPIO initialization table
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid group or pad number
+**/
+STATIC
+EFI_STATUS
+GpioConfigurePch (
+ IN UINT32 NumberOfItems,
+ IN GPIO_INIT_CONFIG *GpioInitTableAddress
+ )
+{
+ UINT32 Index;
+ UINT32 PadCfgDwReg[GPIO_PADCFG_DW_REG_NUMBER];
+ UINT32 PadCfgDwRegMask[GPIO_PADCFG_DW_REG_NUMBER];
+ UINT32 PadCfgReg;
+ GPIO_GROUP_DW_DATA GroupDwData[GPIO_GROUP_DW_NUMBER];
+ UINT32 DwNum;
+ CONST GPIO_GROUP_INFO *GpioGroupInfo;
+ UINT32 GpioGroupInfoLength;
+ GPIO_PAD_OWN PadOwnVal;
+ CONST GPIO_INIT_CONFIG *GpioData;
+ UINT32 GroupIndex;
+ UINT32 PadNumber;
+ UINT32 DwRegIndex;
+
+ PadOwnVal = GpioPadOwnHost;
+
+ GpioGroupInfo = GpioGetGroupInfoTable (&GpioGroupInfoLength);
+
+ Index = 0;
+ while (Index < NumberOfItems) {
+
+ GpioData = &GpioInitTableAddress[Index];
+ GroupIndex = GpioGetGroupIndexFromGpioPad (GpioData->GpioPad);
+
+ DEBUG_CODE_BEGIN();
+ if (!GpioIsCorrectPadForThisChipset (GpioData->GpioPad)) {
+ DEBUG ((DEBUG_ERROR, "GPIO ERROR: Incorrect GpioPad (0x%08x) used on this chipset!\n", GpioData->GpioPad));
+ ASSERT (FALSE);
+ return EFI_UNSUPPORTED;
+ }
+ DEBUG_CODE_END ();
+
+ //
+ // Unlock pads for a given group which are going to be reconfigured
+ //
+ //
+ // Because PADCFGLOCK/LOCKTX register reset domain is Powergood, lock settings
+ // will get back to default only after G3 or DeepSx transition. On the other hand GpioPads
+ // configuration is controlled by a configurable type of reset - PadRstCfg. This means that if
+ // PadRstCfg != Powergood GpioPad will have its configuration locked despite it being not the
+ // one desired by BIOS. Before reconfiguring all pads they will get unlocked.
+ //
+ GpioUnlockPadsForAGroup (NumberOfItems, GpioInitTableAddress, Index);
+
+ ZeroMem (GroupDwData, sizeof (GroupDwData));
+ //
+ // Loop through pads for one group. If pad belongs to a different group then
+ // break and move to register programming.
+ //
+ while (Index < NumberOfItems) {
+
+ GpioData = &GpioInitTableAddress[Index];
+ if (GroupIndex != GpioGetGroupIndexFromGpioPad (GpioData->GpioPad)) {
+ //if next pad is from different group then break loop
+ break;
+ }
+
+ PadNumber = GpioGetPadNumberFromGpioPad (GpioData->GpioPad);
+
+ DEBUG_CODE_BEGIN ();
+ //
+ // Check if legal pin number
+ //
+ if (PadNumber >= GpioGroupInfo[GroupIndex].PadPerGroup) {
+ DEBUG ((DEBUG_ERROR, "GPIO ERROR: Pin number (%d) exceeds possible range for group %d\n", PadNumber, GroupIndex));
+ return EFI_INVALID_PARAMETER;
+ }
+
+ //
+ // Check if selected GPIO Pad is not owned by CSME/ISH
+ //
+ GpioGetPadOwnership (GpioData->GpioPad, &PadOwnVal);
+
+ if (PadOwnVal != GpioPadOwnHost) {
+ DEBUG ((DEBUG_ERROR, "GPIO ERROR: Accessing pad not owned by host (Group=%d, Pad=%d)!\n", GroupIndex, PadNumber));
+ DEBUG ((DEBUG_ERROR, "** Please make sure the GPIO usage in sync between CSME and BIOS configuration. \n"));
+ DEBUG ((DEBUG_ERROR, "** All the GPIO occupied by CSME should not do any configuration by BIOS.\n"));
+ //Move to next item
+ goto move_to_next_index;
+ }
+
+ //
+ // Check if Pad enabled for SCI is to be in unlocked state
+ //
+ if (((GpioData->GpioConfig.InterruptConfig & GpioIntSci) == GpioIntSci) &&
+ ((GpioData->GpioConfig.LockConfig & B_GPIO_LOCK_CONFIG_PAD_CONF_LOCK_MASK) != GpioPadConfigUnlock)){
+ DEBUG ((DEBUG_ERROR, "GPIO ERROR: GPIO used for SCI is not unlocked!\n"));
+ ASSERT (FALSE);
+ return EFI_INVALID_PARAMETER;
+ }
+ DEBUG_CODE_END ();
+
+ ZeroMem (PadCfgDwReg, sizeof (PadCfgDwReg));
+ ZeroMem (PadCfgDwRegMask, sizeof (PadCfgDwRegMask));
+ //
+ // Get GPIO PADCFG register value from GPIO config data
+ //
+ GpioPadCfgRegValueFromGpioConfig (
+ GpioData->GpioPad,
+ &GpioData->GpioConfig,
+ PadCfgDwReg,
+ PadCfgDwRegMask
+ );
+
+ //
+ // Write PADCFG DW0, DW1, DW2 registers
+ //
+ for (DwRegIndex = 0; DwRegIndex <= 2; DwRegIndex++) {
+ PadCfgReg = GpioGetGpioPadCfgAddressFromGpioPad (GpioData->GpioPad, DwRegIndex);
+ if (PadCfgReg != 0) {
+ GpioRegisterAccessAndThenOr32 (&GpioGroupInfo[GroupIndex], PadCfgReg, ~PadCfgDwRegMask[DwRegIndex], PadCfgDwReg[DwRegIndex]);
+ }
+ }
+
+ //
+ // Get GPIO DW register values from GPIO config data
+ //
+ GpioDwRegValueFromGpioConfig (
+ PadNumber,
+ &GpioData->GpioConfig,
+ GroupDwData
+ );
+
+ move_to_next_index:
+ //Move to next item
+ Index++;
+ }
+
+ for (DwNum = 0; DwNum <= GPIO_GET_DW_NUM (GpioGroupInfo[GroupIndex].PadPerGroup); DwNum++) {
+ //
+ // Write HOSTSW_OWN registers
+ //
+ if (GpioGroupInfo[GroupIndex].HostOwnOffset != NO_REGISTER_FOR_PROPERTY) {
+ GpioRegisterAccessAndThenOr32 (
+ &GpioGroupInfo[GroupIndex],
+ GpioGroupInfo[GroupIndex].HostOwnOffset + DwNum * 0x4,
+ ~GroupDwData[DwNum].HostSoftOwnRegMask,
+ GroupDwData[DwNum].HostSoftOwnReg
+ );
+ }
+
+ //
+ // Write GPI_GPE_EN registers
+ //
+ if (GpioGroupInfo[GroupIndex].GpiGpeEnOffset != NO_REGISTER_FOR_PROPERTY) {
+ GpioRegisterAccessAndThenOr32 (
+ &GpioGroupInfo[GroupIndex],
+ GpioGroupInfo[GroupIndex].GpiGpeEnOffset + DwNum * 0x4,
+ ~GroupDwData[DwNum].GpiGpeEnRegMask,
+ GroupDwData[DwNum].GpiGpeEnReg
+ );
+ }
+
+ //
+ // Write GPI_NMI_EN registers
+ //
+ if (GpioGroupInfo[GroupIndex].NmiEnOffset != NO_REGISTER_FOR_PROPERTY) {
+ GpioRegisterAccessAndThenOr32 (
+ &GpioGroupInfo[GroupIndex],
+ GpioGroupInfo[GroupIndex].NmiEnOffset + DwNum * 0x4,
+ ~GroupDwData[DwNum].GpiNmiEnRegMask,
+ GroupDwData[DwNum].GpiNmiEnReg
+ );
+ } else if (GroupDwData[DwNum].GpiNmiEnReg != 0x0) {
+ DEBUG ((DEBUG_ERROR, "GPIO ERROR: Group %d has no pads supporting NMI\n", GroupIndex));
+ ASSERT_EFI_ERROR (EFI_UNSUPPORTED);
+ }
+
+ //
+ // Write GPI_SMI_EN registers
+ //
+ if (GpioGroupInfo[GroupIndex].SmiEnOffset != NO_REGISTER_FOR_PROPERTY) {
+ GpioRegisterAccessAndThenOr32 (
+ &GpioGroupInfo[GroupIndex],
+ GpioGroupInfo[GroupIndex].SmiEnOffset + DwNum * 0x4,
+ ~GroupDwData[DwNum].GpiSmiEnRegMask,
+ GroupDwData[DwNum].GpiSmiEnReg
+ );
+ } else if (GroupDwData[DwNum].GpiSmiEnReg != 0x0) {
+ DEBUG ((DEBUG_ERROR, "GPIO ERROR: Group %d has no pads supporting SMI\n", GroupIndex));
+ ASSERT_EFI_ERROR (EFI_UNSUPPORTED);
+ }
+
+ //
+ // Update Pad Configuration unlock data
+ //
+ if (GroupDwData[DwNum].ConfigUnlockMask) {
+ GpioStoreGroupDwUnlockPadConfigData (GroupIndex, DwNum, GroupDwData[DwNum].ConfigUnlockMask);
+ }
+
+ //
+ // Update Pad Output unlock data
+ //
+ if (GroupDwData[DwNum].OutputUnlockMask) {
+ GpioStoreGroupDwUnlockOutputData (GroupIndex, DwNum, GroupDwData[DwNum].OutputUnlockMask);
+ }
+ }
+ }
+
+ return EFI_SUCCESS;
+}
+
+/**
+ This procedure will clear all status bits of any GPIO interrupts.
+
+ @param[in] none
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid group or pad number
+**/
+STATIC
+EFI_STATUS
+GpioClearAllGpioInterrupts (
+ VOID
+ )
+{
+ GPIO_GROUP Group;
+ CONST GPIO_GROUP_INFO *GpioGroupInfo;
+ GPIO_GROUP GpioGroupLowest;
+ GPIO_GROUP GpioGroupHighest;
+ UINT32 GroupIndex;
+ UINT32 GpioGroupInfoLength;
+ UINT32 DwNum;
+
+ GpioGroupInfo = GpioGetGroupInfoTable (&GpioGroupInfoLength);
+
+ GpioGroupLowest = GpioGetLowestGroup ();
+ GpioGroupHighest = GpioGetHighestGroup ();
+
+ for (Group = GpioGroupLowest; Group <= GpioGroupHighest; Group++) {
+ GroupIndex = GpioGetGroupIndexFromGroup (Group);
+ //
+ // Check if group has GPI IS register
+ //
+ if (GpioGroupInfo[GroupIndex].GpiIsOffset != NO_REGISTER_FOR_PROPERTY) {
+ //
+ // Clear all GPI_IS Status bits by writing '1'
+ //
+ for (DwNum = 0; DwNum <= GPIO_GET_DW_NUM (GpioGroupInfo[GroupIndex].PadPerGroup); DwNum++) {
+ GpioRegisterAccessAndThenOr32 (
+ &GpioGroupInfo[GroupIndex],
+ GpioGroupInfo[GroupIndex].GpiIsOffset + DwNum * 0x4,
+ ~(UINT32)0,
+ 0xFFFFFFFF
+ );
+ }
+ }
+
+ //
+ // Check if group has GPI_GPE_STS register
+ //
+ if (GpioGroupInfo[GroupIndex].GpiGpeStsOffset != NO_REGISTER_FOR_PROPERTY) {
+ //
+ // Clear all GPI_GPE_STS Status bits by writing '1'
+ //
+ for (DwNum = 0; DwNum <= GPIO_GET_DW_NUM (GpioGroupInfo[GroupIndex].PadPerGroup); DwNum++) {
+ GpioRegisterAccessAndThenOr32 (
+ &GpioGroupInfo[GroupIndex],
+ GpioGroupInfo[GroupIndex].GpiGpeStsOffset + DwNum * 0x4,
+ ~(UINT32)0,
+ 0xFFFFFFFF
+ );
+ }
+ }
+
+ //
+ // Check if group has SMI_STS register
+ //
+ if (GpioGroupInfo[GroupIndex].SmiStsOffset != NO_REGISTER_FOR_PROPERTY) {
+ //
+ // Clear all SMI_STS Status bits by writing '1'
+ //
+ for (DwNum = 0; DwNum <= GPIO_GET_DW_NUM (GpioGroupInfo[GroupIndex].PadPerGroup); DwNum++) {
+ GpioRegisterAccessAndThenOr32 (
+ &GpioGroupInfo[GroupIndex],
+ GpioGroupInfo[GroupIndex].SmiStsOffset + DwNum * 4,
+ ~(UINT32)0,
+ 0xFFFFFFFF
+ );
+ }
+ }
+
+ //
+ // Check if group has NMI_STS register
+ //
+ if (GpioGroupInfo[GroupIndex].NmiStsOffset != NO_REGISTER_FOR_PROPERTY) {
+ //
+ // Clear all NMI_STS Status bits by writing '1'
+ //
+ for (DwNum = 0; DwNum <= GPIO_GET_DW_NUM (GpioGroupInfo[GroupIndex].PadPerGroup); DwNum++) {
+ GpioRegisterAccessAndThenOr32 (
+ &GpioGroupInfo[GroupIndex],
+ GpioGroupInfo[GroupIndex].NmiStsOffset + DwNum * 4,
+ ~(UINT32)0,
+ 0xFFFFFFFF
+ );
+ }
+ }
+
+ }
+ return EFI_SUCCESS;
+}
+
+/**
+ This procedure will initialize multiple GPIO pins. Use GPIO_INIT_CONFIG structure.
+ Structure contains fields that can be used to configure each pad.
+ Pad not configured using GPIO_INIT_CONFIG will be left with hardware default values.
+ Separate fields could be set to hardware default if it does not matter, except
+ GpioPad and PadMode.
+ Function will work in most efficient way if pads which belong to the same group are
+ placed in adjacent records of the table.
+ Although function can enable pads for Native mode, such programming is done
+ by reference code when enabling related silicon feature.
+
+ @param[in] NumberofItem Number of GPIO pads to be updated
+ @param[in] GpioInitTableAddress GPIO initialization table
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid group or pad number
+**/
+EFI_STATUS
+GpioConfigurePads (
+ IN UINT32 NumberOfItems,
+ IN GPIO_INIT_CONFIG *GpioInitTableAddress
+ )
+{
+ EFI_STATUS Status;
+
+ Status = GpioConfigurePch (NumberOfItems, GpioInitTableAddress);
+
+ GpioClearAllGpioInterrupts ();
+ return Status;
+}
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/Library/PeiDxeSmmGpioLib/GpioLib.c b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/Library/PeiDxeSmmGpioLib/GpioLib.c
new file mode 100644
index 0000000000..19daed97c0
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/Library/PeiDxeSmmGpioLib/GpioLib.c
@@ -0,0 +1,522 @@
+/** @file
+ This file contains routines for GPIO
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#include "GpioLibrary.h"
+#include <Register/PchPcrRegs.h>
+
+/**
+ This procedure will check if GpioGroup argument is correct and
+ supplied DW reg number can be used for this group to access DW registers.
+ Function will check below conditions:
+ - Valid GpioGroup
+ - DwNum is has valid value for this group
+
+ @param[in] Group GPIO group
+ @param[in] DwNum Register number for current group (parameter applicable in accessing whole register).
+ For group which has less then 32 pads per group DwNum must be 0.
+
+ @retval TRUE DW Reg number and GpioGroup is valid
+ @retval FALSE DW Reg number and GpioGroup is invalid
+**/
+STATIC
+BOOLEAN
+GpioIsGroupAndDwNumValid (
+ IN GPIO_GROUP Group,
+ IN UINT32 DwNum
+ )
+{
+ UINT32 GroupIndex;
+ CONST GPIO_GROUP_INFO *GpioGroupInfo;
+ UINT32 GpioGroupInfoLength;
+
+ GpioGroupInfo = GpioGetGroupInfoTable (&GpioGroupInfoLength);
+
+ GroupIndex = GpioGetGroupIndexFromGroup (Group);
+
+ if ((Group < GpioGetLowestGroup ()) || (Group > GpioGetHighestGroup ()) || (GroupIndex >= GpioGroupInfoLength)) {
+ DEBUG ((DEBUG_ERROR, "GPIO ERROR: Group argument (%d) is not within range of possible groups for this PCH\n", GroupIndex));
+ goto Error;
+ }
+
+ //
+ // Check if DwNum argument does not exceed number of DWord registers
+ // resulting from available pads for certain group
+ //
+ if (DwNum > GPIO_GET_DW_NUM (GpioGroupInfo[GroupIndex].PadPerGroup - 1)){
+ goto Error;
+ }
+
+ return TRUE;
+Error:
+ ASSERT (FALSE);
+ return FALSE;
+}
+
+//
+// Possible registers to be accessed using GpioReadReg()/GpioWriteReg() functions
+//
+typedef enum {
+ GpioHostOwnershipRegister = 0,
+ GpioGpeEnableRegister,
+ GpioGpeStatusRegister,
+ GpioSmiEnableRegister,
+ GpioSmiStatusRegister,
+ GpioNmiEnableRegister,
+ GpioPadConfigLockRegister,
+ GpioPadLockOutputRegister
+} GPIO_REG;
+
+/**
+ This procedure will read GPIO register
+
+ @param[in] RegType GPIO register type
+ @param[in] Group GPIO group
+ @param[in] DwNum Register number for current group (parameter applicable in accessing whole register).
+ For group which has less then 32 pads per group DwNum must be 0.
+ @param[out] ReadVal Read data
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_UNSUPPORTED Feature is not supported for this group or pad
+**/
+STATIC
+EFI_STATUS
+GpioReadReg (
+ IN GPIO_REG RegType,
+ IN GPIO_GROUP Group,
+ IN UINT32 DwNum,
+ OUT UINT32 *ReadVal
+ )
+{
+ UINT32 RegOffset;
+ UINT32 GroupIndex;
+ CONST GPIO_GROUP_INFO *GpioGroupInfo;
+ UINT32 GpioGroupInfoLength;
+
+ RegOffset = NO_REGISTER_FOR_PROPERTY;
+ GroupIndex = GpioGetGroupIndexFromGroup (Group);
+
+ GpioGroupInfo = GpioGetGroupInfoTable (&GpioGroupInfoLength);
+
+ switch (RegType) {
+ case GpioHostOwnershipRegister:
+ RegOffset = GpioGroupInfo[GroupIndex].HostOwnOffset;
+ break;
+ case GpioGpeEnableRegister:
+ RegOffset = GpioGroupInfo[GroupIndex].GpiGpeEnOffset;
+ break;
+ case GpioGpeStatusRegister:
+ RegOffset = GpioGroupInfo[GroupIndex].GpiGpeStsOffset;
+ break;
+ case GpioSmiEnableRegister:
+ RegOffset = GpioGroupInfo[GroupIndex].SmiEnOffset;
+ break;
+ case GpioSmiStatusRegister:
+ RegOffset = GpioGroupInfo[GroupIndex].SmiStsOffset;
+ break;
+ case GpioNmiEnableRegister:
+ RegOffset = GpioGroupInfo[GroupIndex].NmiEnOffset;
+ break;
+ case GpioPadConfigLockRegister:
+ RegOffset = GpioGroupInfo[GroupIndex].PadCfgLockOffset;
+ break;
+ case GpioPadLockOutputRegister:
+ RegOffset = GpioGroupInfo[GroupIndex].PadCfgLockTxOffset;
+ break;
+ default:
+ break;
+ }
+
+ //
+ // Check if selected register exists
+ //
+ if (RegOffset == NO_REGISTER_FOR_PROPERTY) {
+ return EFI_UNSUPPORTED;
+ }
+
+ //
+ // If there are more then 32 pads per group then certain
+ // group information would be split into more then one DWord register.
+ //
+ if ((RegType == GpioPadConfigLockRegister) || (RegType == GpioPadLockOutputRegister)) {
+ //
+ // PadConfigLock and OutputLock registers when used for group containing more than 32 pads
+ // are not placed in a continuous way, e.g:
+ // 0x0 - PadConfigLock_DW0
+ // 0x4 - OutputLock_DW0
+ // 0x8 - PadConfigLock_DW1
+ // 0xC - OutputLock_DW1
+ //
+ RegOffset += DwNum * 0x8;
+ } else {
+ RegOffset += DwNum * 0x4;
+ }
+
+ *ReadVal = GpioRegisterAccessRead32 (&GpioGroupInfo[GroupIndex], RegOffset);
+
+ return EFI_SUCCESS;
+}
+
+/**
+ This procedure will write GPIO register
+
+ @param[in] RegType GPIO register type
+ @param[in] Group GPIO group
+ @param[in] DwNum Register number for current group (parameter applicable in accessing whole register).
+ For group which has less then 32 pads per group DwNum must be 0.
+ @param[in] RegAndMask Mask which will be AND'ed with register value
+ @param[in] RegOrMask Mask which will be OR'ed with register value
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_UNSUPPORTED Feature is not supported for this group or pad
+**/
+STATIC
+EFI_STATUS
+GpioWriteReg (
+ IN GPIO_REG RegType,
+ IN GPIO_GROUP Group,
+ IN UINT32 DwNum,
+ IN UINT32 RegAndMask,
+ IN UINT32 RegOrMask
+ )
+{
+ UINT32 RegOffset;
+ UINT32 GroupIndex;
+ CONST GPIO_GROUP_INFO *GpioGroupInfo;
+ UINT32 GpioGroupInfoLength;
+ UINT32 PadCfgLock;
+ BOOLEAN Lockable;
+
+ Lockable = FALSE;
+ PadCfgLock = 0;
+ RegOffset = NO_REGISTER_FOR_PROPERTY;
+ GroupIndex = GpioGetGroupIndexFromGroup (Group);
+
+ GpioGroupInfo = GpioGetGroupInfoTable (&GpioGroupInfoLength);
+
+ switch (RegType) {
+ case GpioHostOwnershipRegister:
+ RegOffset = GpioGroupInfo[GroupIndex].HostOwnOffset;
+ break;
+ case GpioGpeEnableRegister:
+ RegOffset = GpioGroupInfo[GroupIndex].GpiGpeEnOffset;
+ Lockable = TRUE;
+ break;
+ case GpioGpeStatusRegister:
+ RegOffset = GpioGroupInfo[GroupIndex].GpiGpeStsOffset;
+ break;
+ case GpioSmiEnableRegister:
+ RegOffset = GpioGroupInfo[GroupIndex].SmiEnOffset;
+ Lockable = TRUE;
+ break;
+ case GpioSmiStatusRegister:
+ RegOffset = GpioGroupInfo[GroupIndex].SmiStsOffset;
+ break;
+ case GpioNmiEnableRegister:
+ RegOffset = GpioGroupInfo[GroupIndex].NmiEnOffset;
+ Lockable = TRUE;
+ break;
+ case GpioPadConfigLockRegister:
+ case GpioPadLockOutputRegister:
+ default:
+ break;
+ }
+
+ //
+ // Check if selected register exists
+ //
+ if (RegOffset == NO_REGISTER_FOR_PROPERTY) {
+ return EFI_UNSUPPORTED;
+ }
+
+ if (Lockable) {
+ GpioGetPadCfgLockForGroupDw (Group, DwNum, &PadCfgLock);
+ if (PadCfgLock) {
+ //
+ // Check if for pads which are going to be reconfigured lock is set.
+ //
+ if ((~RegAndMask | RegOrMask) & PadCfgLock) {
+ //
+ // Unlock all pads for this Group DW reg for simplicity
+ // even if not all of those pads will have their settings reprogrammed
+ //
+ GpioUnlockPadCfgForGroupDw (Group, DwNum, PadCfgLock);
+ } else {
+ //
+ // No need to perform an unlock as pads which are going to be reconfigured
+ // are not in locked state
+ //
+ PadCfgLock = 0;
+ }
+ }
+ }
+
+ //
+ // If there are more then 32 pads per group then certain
+ // group information would be split into more then one DWord register.
+ //
+ RegOffset += DwNum * 0x4;
+
+ GpioRegisterAccessAndThenOr32 (&GpioGroupInfo[GroupIndex], RegOffset, RegAndMask,RegOrMask);
+
+ if (Lockable && PadCfgLock) {
+ //
+ // Lock previously unlocked pads
+ //
+ GpioLockPadCfgForGroupDw (Group, DwNum, PadCfgLock);
+ }
+
+ return EFI_SUCCESS;
+}
+
+/**
+ This procedure will write GPIO Lock/LockTx register using SBI.
+
+ @param[in] RegType GPIO register (Lock or LockTx)
+ @param[in] Group GPIO group number
+ @param[in] DwNum Register number for current group.
+ For group which has less then 32 pads per group DwNum must be 0.
+ @param[in] LockRegAndMask Mask which will be AND'ed with Lock register value
+ @param[in] LockRegOrMask Mask which will be Or'ed with Lock register value
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_UNSUPPORTED Feature is not supported for this group or pad
+**/
+STATIC
+EFI_STATUS
+GpioWriteLockReg (
+ IN GPIO_REG RegType,
+ IN GPIO_GROUP Group,
+ IN UINT32 DwNum,
+ IN UINT32 LockRegAndMask,
+ IN UINT32 LockRegOrMask
+ )
+{
+ CONST GPIO_GROUP_INFO *GpioGroupInfo;
+ UINT32 GpioGroupInfoLength;
+ UINT32 RegOffset;
+ UINT32 OldLockVal;
+ UINT32 NewLockVal;
+ UINT32 GroupIndex;
+
+ OldLockVal = 0;
+ NewLockVal = 0;
+
+ RegOffset = NO_REGISTER_FOR_PROPERTY;
+ GroupIndex = GpioGetGroupIndexFromGroup (Group);
+
+ GpioGroupInfo = GpioGetGroupInfoTable (&GpioGroupInfoLength);
+
+ switch (RegType) {
+ case GpioPadConfigLockRegister:
+ RegOffset = GpioGroupInfo[GroupIndex].PadCfgLockOffset;
+ GpioGetPadCfgLockForGroupDw (Group, DwNum, &OldLockVal);
+ break;
+ case GpioPadLockOutputRegister:
+ RegOffset = GpioGroupInfo[GroupIndex].PadCfgLockTxOffset;
+ GpioGetPadCfgLockTxForGroupDw (Group, DwNum, &OldLockVal);
+ break;
+ default:
+ break;
+ }
+
+ //
+ // Check if selected register exists
+ //
+ if (RegOffset == NO_REGISTER_FOR_PROPERTY) {
+ return EFI_UNSUPPORTED;
+ }
+
+ NewLockVal = (OldLockVal & LockRegAndMask) | LockRegOrMask;
+
+ return GpioInternalWriteLockRegister (NewLockVal, RegOffset, DwNum, GpioGroupInfo, GroupIndex);
+}
+
+/**
+ This procedure will get Gpio Pad Ownership
+
+ @param[in] GpioPad GPIO pad
+ @param[out] PadOwnVal Value of Pad Ownership
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid group or pad number
+**/
+EFI_STATUS
+GpioGetPadOwnership (
+ IN GPIO_PAD GpioPad,
+ OUT GPIO_PAD_OWN *PadOwnVal
+ )
+{
+ UINT32 Mask;
+ UINT32 RegOffset;
+ UINT32 GroupIndex;
+ UINT32 PadNumber;
+ CONST GPIO_GROUP_INFO *GpioGroupInfo;
+ UINT32 GpioGroupInfoLength;
+ UINT32 PadOwnRegValue;
+
+ if (!GpioIsPadValid (GpioPad)) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ GroupIndex = GpioGetGroupIndexFromGpioPad (GpioPad);
+ PadNumber = GpioGetPadNumberFromGpioPad (GpioPad);
+
+ GpioGroupInfo = GpioGetGroupInfoTable (&GpioGroupInfoLength);
+
+ //
+ // Check if selected register exists
+ //
+ if (GpioGroupInfo[GroupIndex].PadOwnOffset == NO_REGISTER_FOR_PROPERTY) {
+ *PadOwnVal = GpioPadOwnHost;
+ return EFI_UNSUPPORTED;
+ }
+ //
+ // Calculate RegOffset using Pad Ownership offset and GPIO Pad number.
+ // One DWord register contains information for 8 pads.
+ //
+ RegOffset = GpioGroupInfo[GroupIndex].PadOwnOffset + (PadNumber >> 3) * 0x4;
+
+ //
+ // Calculate pad bit position within DWord register
+ //
+ PadNumber %= 8;
+ Mask = (BIT1 | BIT0) << (PadNumber * 4);
+
+ PadOwnRegValue = GpioRegisterAccessRead32 (&GpioGroupInfo[GroupIndex], RegOffset);
+
+ *PadOwnVal = (GPIO_PAD_OWN) ((PadOwnRegValue & Mask) >> (PadNumber * 4));
+
+ return EFI_SUCCESS;
+}
+
+/**
+ This procedure will check state of Pad Config Lock for pads within one group
+
+ @param[in] Group GPIO group
+ @param[in] DwNum PadCfgLock register number for current group.
+ For group which has less then 32 pads per group DwNum must be 0.
+ @param[out] PadCfgLockRegVal Value of PadCfgLock register
+ Bit position - PadNumber
+ Bit value - 0: NotLocked, 1: Locked
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid group or DwNum parameter number
+**/
+EFI_STATUS
+GpioGetPadCfgLockForGroupDw (
+ IN GPIO_GROUP Group,
+ IN UINT32 DwNum,
+ OUT UINT32 *PadCfgLockRegVal
+ )
+{
+ if (!GpioIsGroupAndDwNumValid (Group, DwNum)) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ return GpioReadReg (
+ GpioPadConfigLockRegister,
+ Group,
+ DwNum,
+ PadCfgLockRegVal
+ );
+}
+/**
+ This procedure will check state of Pad Config Tx Lock for pads within one group
+
+ @param[in] Group GPIO group
+ @param[in] DwNum PadCfgLockTx register number for current group.
+ For group which has less then 32 pads per group DwNum must be 0.
+ @param[out] PadCfgLockTxRegVal Value of PadCfgLockTx register
+ Bit position - PadNumber
+ Bit value - 0: NotLockedTx, 1: LockedTx
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid group or DwNum parameter number
+**/
+EFI_STATUS
+GpioGetPadCfgLockTxForGroupDw (
+ IN GPIO_GROUP Group,
+ IN UINT32 DwNum,
+ OUT UINT32 *PadCfgLockTxRegVal
+ )
+{
+ if (!GpioIsGroupAndDwNumValid (Group, DwNum)) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ return GpioReadReg (
+ GpioPadLockOutputRegister,
+ Group,
+ DwNum,
+ PadCfgLockTxRegVal
+ );
+}
+/**
+ This procedure will clear PadCfgLock for selected pads within one group.
+ This function should be used only inside SMI.
+
+ @param[in] Group GPIO group
+ @param[in] DwNum PadCfgLock register number for current group.
+ For group which has less then 32 pads per group DwNum must be 0.
+ @param[in] PadsToUnlock Bitmask for pads which are going to be unlocked,
+ Bit position - PadNumber
+ Bit value - 0: DoNotUnlock, 1: Unlock
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid group or pad number
+**/
+EFI_STATUS
+GpioUnlockPadCfgForGroupDw (
+ IN GPIO_GROUP Group,
+ IN UINT32 DwNum,
+ IN UINT32 PadsToUnlock
+ )
+{
+ if (!GpioIsGroupAndDwNumValid (Group, DwNum)) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ return GpioWriteLockReg (
+ GpioPadConfigLockRegister,
+ Group,
+ DwNum,
+ ~PadsToUnlock,
+ 0
+ );
+}
+/**
+ This procedure will clear PadCfgLockTx for selected pads within one group.
+ This function should be used only inside SMI.
+
+ @param[in] Group GPIO group
+ @param[in] DwNum PadCfgLockTx register number for current group.
+ For group which has less then 32 pads per group DwNum must be 0.
+ @param[in] PadsToUnlockTx Bitmask for pads which are going to be unlocked,
+ Bit position - PadNumber
+ Bit value - 0: DoNotUnLockTx, 1: LockTx
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid group or pad number
+**/
+EFI_STATUS
+GpioUnlockPadCfgTxForGroupDw (
+ IN GPIO_GROUP Group,
+ IN UINT32 DwNum,
+ IN UINT32 PadsToUnlockTx
+ )
+{
+ if (!GpioIsGroupAndDwNumValid (Group, DwNum)) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ return GpioWriteLockReg (
+ GpioPadLockOutputRegister,
+ Group,
+ DwNum,
+ ~PadsToUnlockTx,
+ 0
+ );
+}
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/Library/PeiDxeSmmGpioLib/GpioLibrary.h b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/Library/PeiDxeSmmGpioLib/GpioLibrary.h
new file mode 100644
index 0000000000..2c2b4ee75c
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/Library/PeiDxeSmmGpioLib/GpioLibrary.h
@@ -0,0 +1,29 @@
+/** @file
+ Header file for GPIO Lib implementation.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _GPIO_LIBRARY_H_
+#define _GPIO_LIBRARY_H_
+
+#include <Base.h>
+#include <Uefi/UefiBaseType.h>
+#include <Library/IoLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/GpioLib.h>
+#include <Library/GpioNativeLib.h>
+#include <Library/GpioPrivateLib.h>
+#include <Library/PchInfoLib.h>
+#include <Library/PchCycleDecodingLib.h>
+#include <Library/PmcPrivateLib.h>
+#include <Library/GpioHelpersLib.h>
+#include <Register/GpioRegs.h>
+
+//
+// Number of PADCFG_DW registers
+//
+#define GPIO_PADCFG_DW_REG_NUMBER 4
+
+#endif // _GPIO_LIBRARY_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/Library/PeiDxeSmmGpioLib/GpioNativeLib.c b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/Library/PeiDxeSmmGpioLib/GpioNativeLib.c
new file mode 100644
index 0000000000..4e4c53e588
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/Library/PeiDxeSmmGpioLib/GpioNativeLib.c
@@ -0,0 +1,177 @@
+/** @file
+ This file contains routines for GPIO native and chipset specific usage
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#include "GpioLibrary.h"
+
+/**
+ This procedure will get number of pads for certain GPIO group
+
+ @param[in] Group GPIO group number
+
+ @retval Value Pad number for group
+ If illegal group number then return 0
+**/
+UINT32
+GpioGetPadPerGroup (
+ IN GPIO_GROUP Group
+ )
+{
+ CONST GPIO_GROUP_INFO *GpioGroupInfo;
+ UINT32 GpioGroupInfoLength;
+ UINT32 GroupIndex;
+ //
+ // Check if group argument exceeds GPIO GROUP INFO array
+ //
+ GpioGroupInfo = GpioGetGroupInfoTable (&GpioGroupInfoLength);
+ GroupIndex = GpioGetGroupIndexFromGroup (Group);
+
+ if ((UINTN) GroupIndex >= GpioGroupInfoLength) {
+ return 0;
+ } else {
+ return GpioGroupInfo[GroupIndex].PadPerGroup;
+ }
+}
+
+/**
+ This procedure will get number of groups
+
+ @param[in] none
+
+ @retval Value Group number
+**/
+UINT32
+GpioGetNumberOfGroups (
+ VOID
+ )
+{
+ UINT32 GpioGroupInfoLength;
+
+ GpioGetGroupInfoTable (&GpioGroupInfoLength);
+ return GpioGroupInfoLength;
+}
+/**
+ This procedure will get lowest group
+
+ @param[in] none
+
+ @retval Value Lowest Group
+**/
+GPIO_GROUP
+GpioGetLowestGroup (
+ VOID
+ )
+{
+ return GpioGetGroupFromGroupIndex (0);
+}
+/**
+ This procedure will get highest group
+
+ @param[in] none
+
+ @retval Value Highest Group
+**/
+GPIO_GROUP
+GpioGetHighestGroup (
+ VOID
+ )
+{
+ return GpioGetGroupFromGroupIndex (GpioGetNumberOfGroups () - 1);
+}
+
+/**
+ This procedure will get group number
+
+ @param[in] GpioPad Gpio Pad
+
+ @retval Value Group number
+**/
+GPIO_GROUP
+GpioGetGroupFromGpioPad (
+ IN GPIO_PAD GpioPad
+ )
+{
+ return GPIO_GET_GROUP_FROM_PAD (GpioPad);
+}
+
+/**
+ This procedure will get group index (0 based)
+
+ @param[in] GpioPad Gpio Pad
+
+ @retval Value Group Index
+**/
+UINT32
+GpioGetGroupIndexFromGpioPad (
+ IN GPIO_PAD GpioPad
+ )
+{
+ return (UINT32) GPIO_GET_GROUP_INDEX_FROM_PAD (GpioPad);
+}
+
+/**
+ This procedure will get group index (0 based) from group
+
+ @param[in] GpioGroup Gpio Group
+
+ @retval Value Group Index
+**/
+UINT32
+GpioGetGroupIndexFromGroup (
+ IN GPIO_GROUP GpioGroup
+ )
+{
+ return (UINT32) GPIO_GET_GROUP_INDEX (GpioGroup);
+}
+
+/**
+ This procedure will get group from group index (0 based)
+
+ @param[in] GroupIndex Group Index
+
+ @retval GpioGroup Gpio Group
+**/
+GPIO_GROUP
+GpioGetGroupFromGroupIndex (
+ IN UINT32 GroupIndex
+ )
+{
+ return GPIO_GROUP_DEF (GroupIndex, GpioGetThisChipsetId ());
+}
+
+/**
+ This procedure will get pad number (0 based) from Gpio Pad
+
+ @param[in] GpioPad Gpio Pad
+
+ @retval Value Pad Number
+**/
+UINT32
+GpioGetPadNumberFromGpioPad (
+ IN GPIO_PAD GpioPad
+ )
+{
+ return (UINT32) GPIO_GET_PAD_NUMBER (GpioPad);
+}
+/**
+ This procedure will return GpioPad from Group and PadNumber
+
+ @param[in] Group GPIO group
+ @param[in] PadNumber GPIO PadNumber
+
+ @retval GpioPad GpioPad
+**/
+GPIO_PAD
+GpioGetGpioPadFromGroupAndPadNumber (
+ IN GPIO_GROUP Group,
+ IN UINT32 PadNumber
+ )
+{
+ if (IsPchLp ()) {
+ return GPIO_PAD_DEF (Group,PadNumber);
+ } else {
+ return GPIO_PAD_DEF (Group,PadNumber);
+ }
+}
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/Library/PeiDxeSmmGpioLib/PeiDxeSmmGpioLib.inf b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/Library/PeiDxeSmmGpioLib/PeiDxeSmmGpioLib.inf
new file mode 100644
index 0000000000..21fb4417c1
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/Library/PeiDxeSmmGpioLib/PeiDxeSmmGpioLib.inf
@@ -0,0 +1,44 @@
+## @file
+# Component description file for the PeiDxeSmmGpioLib
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+
+[Defines]
+INF_VERSION = 0x00010017
+BASE_NAME = PeiDxeSmmGpioLib
+FILE_GUID = 16EC5CA8-8195-4847-B6CB-662BD7B763F2
+VERSION_STRING = 1.0
+MODULE_TYPE = BASE
+LIBRARY_CLASS = GpioLib
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = IA32 X64 IPF EBC
+#
+
+
+
+[LibraryClasses]
+BaseLib
+IoLib
+DebugLib
+PrintLib
+PchCycleDecodingLib
+PchSbiAccessLib
+PmcPrivateLib
+GpioPrivateLib
+GpioHelpersLib
+
+[Packages]
+MdePkg/MdePkg.dec
+AlderlakeSiliconPkg/SiPkg.dec
+
+
+[Sources]
+GpioLib.c
+GpioNativeLib.c
+GpioInit.c
+GpioLibrary.h
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/BaseGpioHelpersLibNull/BaseGpioHelpersLibNull.c b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/BaseGpioHelpersLibNull/BaseGpioHelpersLibNull.c
new file mode 100644
index 0000000000..b4b6c14329
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/BaseGpioHelpersLibNull/BaseGpioHelpersLibNull.c
@@ -0,0 +1,51 @@
+/** @file
+ This file contains NULL implementation for GPIO Helpers Lib
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#include <Uefi/UefiBaseType.h>
+#include <Library/GpioConfig.h>
+
+/**
+ This procedure stores GPIO group data about pads which PadConfig needs to be unlocked.
+
+ @param[in] GroupIndex GPIO group index
+ @param[in] DwNum DWORD index for a group.
+ For group which has less then 32 pads per group DwNum must be 0.
+ @param[in] UnlockedPads DWORD bitmask for pads which are going to be left unlocked
+ Bit position - PadNumber
+ Bit value - 0: Skip, 1: Leave unlocked
+
+ @retval Status
+**/
+EFI_STATUS
+GpioStoreGroupDwUnlockPadConfigData (
+ IN UINT32 GroupIndex,
+ IN UINT32 DwNum,
+ IN UINT32 UnlockedPads
+ )
+{
+ return EFI_SUCCESS;
+}
+
+/**
+ This procedure stores GPIO group data about pads which Output state needs to be unlocked.
+
+ @param[in] GroupIndex GPIO group index
+ @param[in] DwNum DWORD index for a group.
+ For group which has less then 32 pads per group DwNum must be 0.
+ @param[in] UnlockedPads DWORD bitmask for pads which are going to be left unlocked
+ Bit position - PadNumber
+ Bit value - 0: Skip, 1: Leave unlocked
+ @retval Status
+**/
+EFI_STATUS
+GpioStoreGroupDwUnlockOutputData (
+ IN UINT32 GroupIndex,
+ IN UINT32 DwNum,
+ IN UINT32 UnlockedPads
+ )
+{
+ return EFI_SUCCESS;
+}
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/BaseGpioHelpersLibNull/BaseGpioHelpersLibNull.inf b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/BaseGpioHelpersLibNull/BaseGpioHelpersLibNull.inf
new file mode 100644
index 0000000000..91d81af4b9
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/BaseGpioHelpersLibNull/BaseGpioHelpersLibNull.inf
@@ -0,0 +1,25 @@
+## @file
+# Component description file for the NULL GpioHelpersLib
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+
+[Defines]
+INF_VERSION = 0x00010017
+BASE_NAME = BaseGpioHelpersLib
+FILE_GUID = AB282608-2A50-4AE3-9242-64064ECF40D4
+VERSION_STRING = 1.0
+MODULE_TYPE = BASE
+LIBRARY_CLASS = GpioHelpersLib
+
+
+[Packages]
+MdePkg/MdePkg.dec
+AlderlakeSiliconPkg/SiPkg.dec
+
+
+[Sources]
+BaseGpioHelpersLibNull.c
+
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiDxeSmmGpioPrivateLib/GpioNativePrivateLibInternal.h b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiDxeSmmGpioPrivateLib/GpioNativePrivateLibInternal.h
new file mode 100644
index 0000000000..480990cb62
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiDxeSmmGpioPrivateLib/GpioNativePrivateLibInternal.h
@@ -0,0 +1,48 @@
+/** @file
+ Header file for GPIO Private Lib Internal functions.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _GPIO_NATIVE_PRIVATE_LIB_INTERNAL_H_
+#define _GPIO_NATIVE_PRIVATE_LIB_INTERNAL_H_
+
+#include <Library/GpioPrivateLib.h>
+
+
+/**
+ This function provides recommended GPIO IO Standby configuration for a given native function
+
+ @param[in] PadFunction PadFunction for a specific native signal. Please refer to GpioNativePads.h
+ @param[out] StandbyState IO Standby State for specified native function
+ @param[out] StandbyTerm IO Standby Termination for specified native function
+
+ @retval Status
+**/
+EFI_STATUS
+GpioGetFunctionIoStandbyConfig (
+ IN UINT32 PadFunction,
+ OUT GPIO_IOSTANDBY_STATE *StandbyState,
+ OUT GPIO_IOSTANDBY_TERM *StandbyTerm
+ );
+
+/**
+ This procedure will calculate PADCFG register value based on GpioConfig data
+ For physical/local/hard (not virtual) GPIO pads
+
+ @param[in] GpioPad GPIO Pad
+ @param[in] GpioConfig GPIO Configuration data
+ @param[out] PadCfgDwReg PADCFG DWx register value
+ @param[out] PadCfgDwRegMask Mask with PADCFG DWx register bits to be modified
+
+ @retval Status
+**/
+EFI_STATUS
+GpioPadCfgRegValueFromGpioConfigHardGpio (
+ IN GPIO_PAD GpioPad,
+ IN CONST GPIO_CONFIG *GpioConfig,
+ OUT UINT32 *PadCfgDwReg,
+ OUT UINT32 *PadCfgDwRegMask
+ );
+
+#endif // _GPIO_NATIVE_PRIVATE_LIB_INTERNAL_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiDxeSmmGpioPrivateLib/GpioPrivateLib.c b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiDxeSmmGpioPrivateLib/GpioPrivateLib.c
new file mode 100644
index 0000000000..7d5fa9fafd
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiDxeSmmGpioPrivateLib/GpioPrivateLib.c
@@ -0,0 +1,267 @@
+/** @file
+ This file contains GPIO routines for RC usage
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#include <Base.h>
+#include <Uefi/UefiBaseType.h>
+#include <Library/IoLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/GpioLib.h>
+#include <Library/GpioNativeLib.h>
+#include <Library/GpioPrivateLib.h>
+#include <Library/GpioNativePads.h>
+#include <Register/GpioRegs.h>
+#include "GpioNativePrivateLibInternal.h"
+
+/**
+ This procedure is used to check if GpioPad is valid for certain chipset
+
+ @param[in] GpioPad GPIO pad
+
+ @retval TRUE This pin is valid on this chipset
+ FALSE Incorrect pin
+**/
+BOOLEAN
+GpioIsCorrectPadForThisChipset (
+ IN GPIO_PAD GpioPad
+ )
+{
+ return ((GPIO_GET_CHIPSET_ID (GpioPad) == GpioGetThisChipsetId ()) &&
+ (GpioGetGroupIndexFromGpioPad (GpioPad) < GpioGetNumberOfGroups ()));
+}
+
+/**
+ This procedure is used by PchSmiDispatcher and will return information
+ needed to register GPI SMI.
+
+ @param[in] Index GPI SMI number
+ @param[out] GpioPin GPIO pin
+ @param[out] GpiSmiBitOffset GPI SMI bit position within GpiSmi Registers
+ @param[out] GpiHostSwOwnRegAddress Address of HOSTSW_OWN register
+ @param[out] GpiSmiStsRegAddress Address of GPI SMI status register
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid group or pad number
+**/
+EFI_STATUS
+GpioGetPadAndSmiRegs (
+ IN UINT32 Index,
+ OUT GPIO_PAD *GpioPin,
+ OUT UINT8 *GpiSmiBitOffset,
+ OUT UINT32 *GpiHostSwOwnRegAddress,
+ OUT UINT32 *GpiSmiStsRegAddress
+ )
+{
+ UINT32 GroupIndex;
+ UINT32 PadNumber;
+ CONST GPIO_GROUP_INFO *GpioGroupInfo;
+ GPIO_GROUP GpioGroup;
+ UINT32 GpioGroupInfoLength;
+ UINT32 SmiStsRegOffset;
+ UINT32 HostSwOwnRegOffset;
+ GPIO_PAD_OWN PadOwnVal;
+
+ GpioGroupInfo = GpioGetGroupInfoTable (&GpioGroupInfoLength);
+
+ PadNumber = 0;
+ GroupIndex = 0;
+ for (GroupIndex = 0; GroupIndex < GpioGroupInfoLength; GroupIndex++) {
+ PadNumber = Index;
+ if (PadNumber < GpioGroupInfo[GroupIndex].PadPerGroup) {
+ //
+ // Found group and pad number
+ //
+ break;
+ }
+ Index = Index - GpioGroupInfo[GroupIndex].PadPerGroup;
+ }
+
+ //
+ // Check if legal pad number
+ //
+ if (PadNumber >= GpioGroupInfo[GroupIndex].PadPerGroup){
+ return EFI_INVALID_PARAMETER;
+ }
+
+ //
+ // Check if selected group has GPI SMI Enable and Status registers
+ //
+ if (GpioGroupInfo[GroupIndex].SmiEnOffset == NO_REGISTER_FOR_PROPERTY) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ GpioGroup = GpioGetGroupFromGroupIndex (GroupIndex);
+ *GpioPin = GpioGetGpioPadFromGroupAndPadNumber (GpioGroup, PadNumber);
+
+ DEBUG_CODE_BEGIN ();
+ //
+ // Check if selected GPIO Pad is not owned by CSME/ISH/IE
+ //
+ GpioGetPadOwnership (*GpioPin, &PadOwnVal);
+ if (PadOwnVal != GpioPadOwnHost) {
+ DEBUG ((DEBUG_ERROR, "GPIO ERROR: GPIO not owned by host!\n"));
+ return EFI_INVALID_PARAMETER;
+ }
+ DEBUG_CODE_END ();
+
+ *GpiSmiBitOffset = (UINT8)(PadNumber % 32);
+
+ HostSwOwnRegOffset = GpioGroupInfo[GroupIndex].HostOwnOffset + (PadNumber / 32) * 0x4;
+ *GpiHostSwOwnRegAddress = PCH_PCR_ADDRESS (GpioGroupInfo[GroupIndex].Community, HostSwOwnRegOffset);
+
+ SmiStsRegOffset = GpioGroupInfo[GroupIndex].SmiStsOffset + (PadNumber / 32) * 0x4;
+ *GpiSmiStsRegAddress = PCH_PCR_ADDRESS (GpioGroupInfo[GroupIndex].Community, SmiStsRegOffset);
+
+ return EFI_SUCCESS;
+}
+
+/**
+ This procedure will check if GpioPad argument is valid.
+ Function will check below conditions:
+ - GpioPad represents a pad for current PCH
+ - GpioPad belongs to valid GpioGroup
+ - GPIO PadNumber is not greater than number of pads for this group
+
+ @param[in] GpioPad GPIO pad
+
+ @retval TRUE GPIO pad is valid and can be used with GPIO lib API
+ @retval FALSE GPIO pad is invalid and cannot be used with GPIO lib API
+**/
+BOOLEAN
+GpioIsPadValid (
+ IN GPIO_PAD GpioPad
+ )
+{
+ CONST GPIO_GROUP_INFO *GpioGroupInfo;
+ UINT32 GpioGroupInfoLength;
+ UINT32 PadNumber;
+ UINT32 GroupIndex;
+
+ if (!GpioIsCorrectPadForThisChipset (GpioPad)) {
+ DEBUG ((DEBUG_ERROR, "GPIO ERROR: Incorrect GpioPad (0x%08x) used on this chipset!\n", GpioPad));
+ goto Error;
+ }
+
+ GpioGroupInfo = GpioGetGroupInfoTable (&GpioGroupInfoLength);
+
+ //
+ // Check if legal pin number
+ //
+ GroupIndex = GpioGetGroupIndexFromGpioPad (GpioPad);
+ PadNumber = GpioGetPadNumberFromGpioPad (GpioPad);
+ if (PadNumber >= GpioGroupInfo[GroupIndex].PadPerGroup) {
+ DEBUG ((DEBUG_ERROR, "GPIO ERROR: Pin number (%d) exceeds range of group (max: %d)\n",
+ PadNumber,
+ GpioGroupInfo[GroupIndex].PadPerGroup));
+ goto Error;
+ }
+
+ return TRUE;
+Error:
+ ASSERT (FALSE);
+ return FALSE;
+}
+
+/**
+ This procedure will read GPIO Pad Configuration register
+
+ @param[in] GpioPad GPIO pad
+ @param[in] DwReg Choose PADCFG register: 0:DW0, 1:DW1
+
+ @retval PadCfgRegValue PADCFG_DWx value
+**/
+UINT32
+GpioReadPadCfgReg (
+ IN GPIO_PAD GpioPad,
+ IN UINT8 DwReg
+ )
+{
+ UINT32 PadCfgReg;
+ CONST GPIO_GROUP_INFO *GpioGroupInfo;
+ UINT32 GpioGroupInfoLength;
+ UINT32 GroupIndex;
+
+ GroupIndex = GpioGetGroupIndexFromGpioPad (GpioPad);
+ GpioGroupInfo = GpioGetGroupInfoTable (&GpioGroupInfoLength);
+
+ //
+ // Create Pad Configuration register offset
+ //
+ PadCfgReg = GpioGetGpioPadCfgAddressFromGpioPad (GpioPad, DwReg);
+ return GpioRegisterAccessRead32 (&GpioGroupInfo[GroupIndex], PadCfgReg);
+}
+
+
+/**
+ This procedure will calculate PADCFG register value based on GpioConfig data
+ For physical/local/hard (not virtual) GPIO pads
+
+ @param[in] GpioPad GPIO Pad
+ @param[in] GpioConfig GPIO Configuration data
+ @param[out] PadCfgDwReg PADCFG DWx register value
+ @param[out] PadCfgDwRegMask Mask with PADCFG DWx register bits to be modified
+
+ @retval Status
+**/
+EFI_STATUS
+GpioPadCfgRegValueFromGpioConfigHardGpio (
+ IN GPIO_PAD GpioPad,
+ IN CONST GPIO_CONFIG *GpioConfig,
+ OUT UINT32 *PadCfgDwReg,
+ OUT UINT32 *PadCfgDwRegMask
+ )
+{
+ //
+ // Configure how interrupt is triggered (RxEvCfg)
+ //
+ PadCfgDwRegMask[0] |= ((((GpioConfig->InterruptConfig & B_GPIO_INT_CONFIG_INT_TYPE_MASK) >> N_GPIO_INT_CONFIG_INT_TYPE_BIT_POS) == GpioHardwareDefault) ? 0x0 : B_GPIO_PCR_RX_LVL_EDG);
+ PadCfgDwReg[0] |= (((GpioConfig->InterruptConfig & B_GPIO_INT_CONFIG_INT_TYPE_MASK) >> (N_GPIO_INT_CONFIG_INT_TYPE_BIT_POS + 1)) << N_GPIO_PCR_RX_LVL_EDG);
+
+ //
+ // Configure interrupt generation (GPIRoutIOxAPIC/SCI/SMI/NMI)
+ //
+ PadCfgDwRegMask[0] |= ((((GpioConfig->InterruptConfig & B_GPIO_INT_CONFIG_INT_SOURCE_MASK) >> N_GPIO_INT_CONFIG_INT_SOURCE_BIT_POS) == GpioHardwareDefault) ? 0x0 : (B_GPIO_PCR_RX_NMI_ROUTE | B_GPIO_PCR_RX_SCI_ROUTE | B_GPIO_PCR_RX_SMI_ROUTE | B_GPIO_PCR_RX_APIC_ROUTE));
+ PadCfgDwReg[0] |= (((GpioConfig->InterruptConfig & B_GPIO_INT_CONFIG_INT_SOURCE_MASK) >> (N_GPIO_INT_CONFIG_INT_SOURCE_BIT_POS + 1)) << N_GPIO_PCR_RX_NMI_ROUTE);
+
+ //
+ // Configure GPIO direction (GPIORxDis and GPIOTxDis)
+ //
+ PadCfgDwRegMask[0] |= ((((GpioConfig->Direction & B_GPIO_DIRECTION_DIR_MASK) >> N_GPIO_DIRECTION_DIR_BIT_POS) == GpioHardwareDefault) ? 0x0 : (B_GPIO_PCR_RXDIS | B_GPIO_PCR_TXDIS));
+ PadCfgDwReg[0] |= (((GpioConfig->Direction & B_GPIO_DIRECTION_DIR_MASK) >> (N_GPIO_DIRECTION_DIR_BIT_POS + 1)) << N_GPIO_PCR_TXDIS);
+
+ //
+ // Configure GPIO input inversion (RXINV)
+ //
+ PadCfgDwRegMask[0] |= ((((GpioConfig->Direction & B_GPIO_DIRECTION_INV_MASK) >> N_GPIO_DIRECTION_INV_BIT_POS) == GpioHardwareDefault) ? 0x0 : B_GPIO_PCR_RXINV);
+ PadCfgDwReg[0] |= (((GpioConfig->Direction & B_GPIO_DIRECTION_INV_MASK) >> (N_GPIO_DIRECTION_INV_BIT_POS + 1)) << N_GPIO_PCR_RXINV);
+
+ //
+ // Configure GPIO output state (GPIOTxState)
+ //
+ PadCfgDwRegMask[0] |= ((((GpioConfig->OutputState & B_GPIO_OUTPUT_MASK) >> N_GPIO_OUTPUT_BIT_POS) == GpioHardwareDefault) ? 0x0 : B_GPIO_PCR_TX_STATE);
+ PadCfgDwReg[0] |= (((GpioConfig->OutputState & B_GPIO_OUTPUT_MASK) >> (N_GPIO_OUTPUT_BIT_POS + 1)) << N_GPIO_PCR_TX_STATE);
+
+ //
+ // Configure GPIO RX raw override to '1' (RXRAW1)
+ //
+ PadCfgDwRegMask[0] |= ((((GpioConfig->OtherSettings & B_GPIO_OTHER_CONFIG_RXRAW_MASK) >> N_GPIO_OTHER_CONFIG_RXRAW_BIT_POS) == GpioHardwareDefault) ? 0x0 : B_GPIO_PCR_RX_RAW1);
+ PadCfgDwReg[0] |= (((GpioConfig->OtherSettings & B_GPIO_OTHER_CONFIG_RXRAW_MASK) >> (N_GPIO_OTHER_CONFIG_RXRAW_BIT_POS + 1)) << N_GPIO_PCR_RX_RAW1);
+
+ //
+ // Configure GPIO Pad Mode (PMode)
+ //
+ PadCfgDwRegMask[0] |= ((((GpioConfig->PadMode & B_GPIO_PAD_MODE_MASK) >> N_GPIO_PAD_MODE_BIT_POS) == GpioHardwareDefault) ? 0x0 : B_GPIO_PCR_PAD_MODE);
+ PadCfgDwReg[0] |= (((GpioConfig->PadMode & B_GPIO_PAD_MODE_MASK) >> (N_GPIO_PAD_MODE_BIT_POS + 1)) << N_GPIO_PCR_PAD_MODE);
+
+ //
+ // Configure GPIO termination (Term)
+ //
+ PadCfgDwRegMask[1] |= ((((GpioConfig->ElectricalConfig & B_GPIO_ELECTRICAL_CONFIG_TERMINATION_MASK) >> N_GPIO_ELECTRICAL_CONFIG_TERMINATION_BIT_POS) == GpioHardwareDefault) ? 0x0 : B_GPIO_PCR_TERM);
+ PadCfgDwReg[1] |= (((GpioConfig->ElectricalConfig & B_GPIO_ELECTRICAL_CONFIG_TERMINATION_MASK) >> (N_GPIO_ELECTRICAL_CONFIG_TERMINATION_BIT_POS + 1)) << N_GPIO_PCR_TERM);
+
+ return EFI_SUCCESS;
+}
+
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiDxeSmmGpioPrivateLib/GpioPrivateLibPch.c b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiDxeSmmGpioPrivateLib/GpioPrivateLibPch.c
new file mode 100644
index 0000000000..3d16fd2acd
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiDxeSmmGpioPrivateLib/GpioPrivateLibPch.c
@@ -0,0 +1,172 @@
+/** @file
+ This file contains hard/physical/local (not virtual) GPIO information
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#include <Uefi/UefiBaseType.h>
+#include <Library/GpioLib.h>
+#include <Library/GpioPrivateLib.h>
+#include <Library/GpioNativeLib.h>
+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+#include <Library/PchSbiAccessLib.h>
+#include <Register/GpioRegs.h>
+#include "GpioNativePrivateLibInternal.h"
+
+/**
+ This procedure calculates Pad Configuration Register DW offset
+
+ @param[in] GpioPad GPIO pad
+ @param[in] DwReg Index of the configuration register
+
+ @retval DW Register offset
+**/
+UINT32
+GpioGetGpioPadCfgAddressFromGpioPad (
+ IN GPIO_PAD GpioPad,
+ IN UINT32 DwReg
+ )
+{
+ UINT32 PadCfgRegAddress;
+ CONST GPIO_GROUP_INFO *GpioGroupInfo;
+ UINT32 GpioGroupInfoLength;
+ UINT32 GroupIndex;
+ UINT32 PadNumber;
+
+ GroupIndex = GpioGetGroupIndexFromGpioPad (GpioPad);
+ PadNumber = GpioGetPadNumberFromGpioPad (GpioPad);
+
+ GpioGroupInfo = GpioGetGroupInfoTable (&GpioGroupInfoLength);
+
+ //
+ // Create Pad Configuration register offset
+ //
+ PadCfgRegAddress = GpioGroupInfo[GroupIndex].PadCfgOffset + DwReg * 4 + S_GPIO_PCR_PADCFG * PadNumber;
+
+ return PadCfgRegAddress;
+}
+
+/**
+ This procedure reads GPIO register
+
+ @param[in] GpioGroupInfo Pointer to GPIO group table info
+ @param[in] Register Register offset
+
+ @retval Register value or "F"s in case of errors
+**/
+UINT32
+GpioRegisterAccessRead32 (
+ IN CONST GPIO_GROUP_INFO *GpioGroupInfo,
+ IN UINT32 Register
+ )
+{
+ return MmioRead32 (PCH_PCR_ADDRESS (GpioGroupInfo->Community, Register));
+}
+
+/**
+ This procedure writes GPIO register
+
+ @param[in] GpioGroupInfo Pointer to GPIO group table info
+ @param[in] Register Register offset
+ @param[in] AndValue And value
+ @param[in] OrValue Or value
+
+ @retval EFI_SUCCESS Operation completed successfully
+**/
+EFI_STATUS
+GpioRegisterAccessAndThenOr32 (
+ IN CONST GPIO_GROUP_INFO *GpioGroupInfo,
+ IN UINT32 Register,
+ IN UINT32 AndValue,
+ IN UINT32 OrValue
+ )
+{
+ MmioAndThenOr32 (
+ PCH_PCR_ADDRESS (GpioGroupInfo->Community, Register),
+ AndValue,
+ OrValue
+ );
+ return EFI_SUCCESS;
+}
+
+/**
+ This procedure will calculate PADCFG register value based on GpioConfig data
+
+ @param[in] GpioPad GPIO Pad
+ @param[in] GpioConfig GPIO Configuration data
+ @param[out] PadCfgDwReg PADCFG DWx register value
+ @param[out] PadCfgDwRegMask Mask with PADCFG DWx register bits to be modified
+
+ @retval Status
+**/
+EFI_STATUS
+GpioPadCfgRegValueFromGpioConfig (
+ IN GPIO_PAD GpioPad,
+ IN CONST GPIO_CONFIG *GpioConfig,
+ OUT UINT32 *PadCfgDwReg,
+ OUT UINT32 *PadCfgDwRegMask
+ )
+{
+ return GpioPadCfgRegValueFromGpioConfigHardGpio (GpioPad, GpioConfig, PadCfgDwReg, PadCfgDwRegMask);
+}
+
+/**
+ This procedure will write GPIO Lock/LockTx register
+ - For PCH SBI message is used.
+
+ @param[in] RegValue GPIO register (Lock or LockTx) value
+ @param[in] RegOffset GPIO register (Lock or LockTx) base offset
+ @param[in] DwNum Register number for current group.
+ For group which has less then 32 pads per group DwNum must be 0.
+ @param[in] GpioGroupInfo Pointer to GPIO group table info
+ @param[in] GroupIndex GPIO group index in the GpioGroupInfo table
+
+ @retval EFI_SUCCESS The function completed successfully
+ EFI_UNSUPPORTED Feature is not supported for this group or pad
+**/
+EFI_STATUS
+GpioInternalWriteLockRegister (
+ IN UINT32 RegValue,
+ IN UINT32 RegOffset,
+ IN UINT32 DwNum,
+ IN CONST GPIO_GROUP_INFO *GpioGroupInfo,
+ IN UINT32 GroupIndex
+ )
+{
+ EFI_STATUS Status;
+ PCH_SBI_OPCODE Opcode;
+ UINT8 Response;
+
+ //
+ // If there are more then 32 pads per group then certain
+ // group information would be split into more then one DWord register.
+ // PadConfigLock and OutputLock registers when used for group containing more than 32 pads
+ // are not placed in a continuous way, e.g:
+ // 0x0 - PadConfigLock_DW0
+ // 0x4 - OutputLock_DW0
+ // 0x8 - PadConfigLock_DW1
+ // 0xC - OutputLock_DW1
+ //
+ RegOffset += DwNum * 0x8;
+
+ if (IsGpioLockOpcodeSupported ()) {
+ Opcode = GpioLockUnlock;
+ } else {
+ Opcode = PrivateControlWrite;
+ }
+
+ Status = PchSbiExecutionEx (
+ GpioGroupInfo[GroupIndex].Community,
+ RegOffset,
+ Opcode,
+ FALSE,
+ 0x000F,
+ 0x0000,
+ 0x0000,
+ &RegValue,
+ &Response
+ );
+ ASSERT_EFI_ERROR (Status);
+ return Status;
+}
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiDxeSmmGpioPrivateLib/GpioPrivateLibVer2.c b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiDxeSmmGpioPrivateLib/GpioPrivateLibVer2.c
new file mode 100644
index 0000000000..1348643553
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiDxeSmmGpioPrivateLib/GpioPrivateLibVer2.c
@@ -0,0 +1,81 @@
+/** @file
+ This file contains VER2 specific GPIO information
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#include <Uefi/UefiBaseType.h>
+#include <Library/DebugLib.h>
+#include <Library/PchInfoLib.h>
+#include <Library/GpioLib.h>
+#include <Library/GpioNativeLib.h>
+#include <Library/GpioNativePads.h>
+#include <Library/GpioPrivateLib.h>
+#include <Library/GpioHelpersLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/IoLib.h>
+#include <Register/GpioRegsVer2.h>
+#include <Register/PchPcrRegs.h>
+#include <Register/GpioRegs.h>
+#include <Pins/GpioPinsVer2Lp.h>
+#include <GpioNativePrivateLibInternal.h>
+#include <Library/PcdLib.h>
+GLOBAL_REMOVE_IF_UNREFERENCED GPIO_GROUP_INFO mPchLpGpioGroupInfo[] = {
+ {PID_GPIOCOM0, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_PAD_OWN, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_HOSTSW_OWN, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_GPI_IS, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_GPI_IE, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_GPI_GPE_STS, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_GPI_GPE_EN, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_SMI_STS, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_SMI_EN, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_NMI_STS, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_NMI_EN, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_PADCFGLOCK, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_PADCFGLOCKTX, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_PADCFG_OFFSET, GPIO_VER2_PCH_LP_GPIO_GPP_B_PAD_MAX}, //TGL PCH-LP GPP_B
+ {PID_GPIOCOM0, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, 0},
+ {PID_GPIOCOM0, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_A_PAD_OWN, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_A_HOSTSW_OWN, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_A_GPI_IS, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_A_GPI_IE, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_A_GPI_GPE_STS, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_A_GPI_GPE_EN, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_A_PADCFGLOCK, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_A_PADCFGLOCKTX, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_A_PADCFG_OFFSET, GPIO_VER2_PCH_LP_GPIO_GPP_A_PAD_MAX}, //TGL PCH-LP GPP_A
+ {PID_GPIOCOM5, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_R_PAD_OWN, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_R_HOSTSW_OWN, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_R_GPI_IS, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_R_GPI_IE, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_R_GPI_GPE_STS, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_R_GPI_GPE_EN, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_R_PADCFGLOCK, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_R_PADCFGLOCKTX, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_R_PADCFG_OFFSET, GPIO_VER2_PCH_LP_GPIO_GPP_R_PAD_MAX}, //TGL PCH-LP GPP_R
+ {PID_GPIOCOM5, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, 0},
+ {PID_GPIOCOM2, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPD_PAD_OWN, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPD_HOSTSW_OWN, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPD_GPI_IS, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPD_GPI_IE, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPD_GPI_GPE_STS, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPD_GPI_GPE_EN, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPD_PADCFGLOCK, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPD_PADCFGLOCKTX, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPD_PADCFG_OFFSET, GPIO_VER2_PCH_LP_GPIO_GPD_PAD_MAX}, //TGL PCH-LP GPD
+ {PID_GPIOCOM1, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_S_PAD_OWN, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_S_HOSTSW_OWN, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_S_GPI_IS, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_S_GPI_IE, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_S_GPI_GPE_STS, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_S_GPI_GPE_EN, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_S_PADCFGLOCK, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_S_PADCFGLOCKTX, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_S_PADCFG_OFFSET, GPIO_VER2_PCH_LP_GPIO_GPP_S_PAD_MAX}, //TGL PCH-LP GPP_S
+ {PID_GPIOCOM1, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_H_PAD_OWN, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_H_HOSTSW_OWN, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_H_GPI_IS, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_H_GPI_IE, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_H_GPI_GPE_STS, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_H_GPI_GPE_EN, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_H_PADCFGLOCK, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_H_PADCFGLOCKTX, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_H_PADCFG_OFFSET, GPIO_VER2_PCH_LP_GPIO_GPP_H_PAD_MAX}, //TGL PCH-LP GPP_H
+ {PID_GPIOCOM1, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_PAD_OWN, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_HOSTSW_OWN, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_GPI_IS, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_GPI_IE, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_GPI_GPE_STS, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_GPI_GPE_EN, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_SMI_STS, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_SMI_EN, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_NMI_STS, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_NMI_EN, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_PADCFGLOCK, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_PADCFGLOCKTX, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_PADCFG_OFFSET, GPIO_VER2_PCH_LP_GPIO_GPP_D_PAD_MAX}, //TGL PCH-LP GPP_D
+ {PID_GPIOCOM1, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, 0},
+ {PID_GPIOCOM1, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, 0},
+ {PID_GPIOCOM4, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_PAD_OWN, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_HOSTSW_OWN, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_GPI_IS, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_GPI_IE, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_GPI_GPE_STS, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_GPI_GPE_EN, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_SMI_STS, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_SMI_EN, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_NMI_STS, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_NMI_EN, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_PADCFGLOCK, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_PADCFGLOCKTX, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_PADCFG_OFFSET, GPIO_VER2_PCH_LP_GPIO_GPP_C_PAD_MAX}, //TGL PCH-LP GPP_C
+ {PID_GPIOCOM4, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_F_PAD_OWN, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_F_HOSTSW_OWN, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_F_GPI_IS, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_F_GPI_IE, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_F_GPI_GPE_STS, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_F_GPI_GPE_EN, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_F_PADCFGLOCK, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_F_PADCFGLOCKTX, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_F_PADCFG_OFFSET, GPIO_VER2_PCH_LP_GPIO_GPP_F_PAD_MAX}, //TGL PCH-LP GPP_F
+ {PID_GPIOCOM4, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, 0},
+ {PID_GPIOCOM4, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_PAD_OWN, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_HOSTSW_OWN, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_GPI_IS, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_GPI_IE, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_GPI_GPE_STS, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_GPI_GPE_EN, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_SMI_STS, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_SMI_EN, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_NMI_STS, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_NMI_EN, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_PADCFGLOCK, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_PADCFGLOCKTX, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_PADCFG_OFFSET, GPIO_VER2_PCH_LP_GPIO_GPP_E_PAD_MAX}, //TGL PCH-LP GPP_E
+};
+
+/**
+ This procedure will retrieve address and length of GPIO info table
+
+ @param[out] GpioGroupInfoTableLength Length of GPIO group table
+
+ @retval Pointer to GPIO group table
+
+**/
+CONST GPIO_GROUP_INFO*
+GpioGetGroupInfoTable (
+ OUT UINT32 *GpioGroupInfoTableLength
+ )
+{
+ *GpioGroupInfoTableLength = ARRAY_SIZE (mPchLpGpioGroupInfo);
+ return mPchLpGpioGroupInfo;
+}
+
+/**
+ Get GPIO Chipset ID specific to PCH generation and series
+**/
+UINT32
+GpioGetThisChipsetId (
+ VOID
+ )
+{
+ return GPIO_VER2_LP_CHIPSET_ID;
+}
+
+/**
+ Check if 0x13 opcode supported for writing to GPIO lock unlock register
+
+ @retval TRUE It's supported
+ @retval FALSE It's not supported
+**/
+BOOLEAN
+IsGpioLockOpcodeSupported (
+ VOID
+ )
+{
+ return TRUE;
+}
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiDxeSmmGpioPrivateLib/PeiDxeSmmGpioPrivateLibVer2.inf b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiDxeSmmGpioPrivateLib/PeiDxeSmmGpioPrivateLibVer2.inf
new file mode 100644
index 0000000000..2e9a6b7336
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiDxeSmmGpioPrivateLib/PeiDxeSmmGpioPrivateLibVer2.inf
@@ -0,0 +1,40 @@
+## @file
+# Component description file for the PeiDxeSmmGpioPrivateLib
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+[Defines]
+INF_VERSION = 0x00010017
+BASE_NAME = PeiDxeSmmGpioPrivateLibVer2
+FILE_GUID = 680A81B0-A087-4687-B5B4-146DA30042D6
+VERSION_STRING = 1.0
+MODULE_TYPE = BASE
+LIBRARY_CLASS = GpioPrivateLib
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = IA32 X64 IPF EBC
+#
+
+
+[LibraryClasses]
+ BaseLib
+ IoLib
+ DebugLib
+ PmcLib
+ PchInfoLib
+ GpioLib
+ GpioHelpersLib
+
+
+[Packages]
+ MdePkg/MdePkg.dec
+ AlderlakeSiliconPkg/SiPkg.dec
+
+
+[Sources]
+ GpioPrivateLib.c
+ GpioPrivateLibVer2.c
+ GpioPrivateLibPch.c
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiGpioHelpersLib/PeiGpioHelpersLib.c b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiGpioHelpersLib/PeiGpioHelpersLib.c
new file mode 100644
index 0000000000..9d47e6bfd5
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiGpioHelpersLib/PeiGpioHelpersLib.c
@@ -0,0 +1,218 @@
+/** @file
+ This file contains routines for PEI GPIO Helpers Lib
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#include <Library/HobLib.h>
+#include <Base.h>
+#include <Uefi/UefiBaseType.h>
+#include <Library/IoLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/GpioNativeLib.h>
+#include <Library/GpioPrivateLib.h>
+#include <Library/GpioHelpersLib.h>
+#include <Library/PeiServicesLib.h>
+#include <Library/ConfigBlockLib.h>
+#include <Ppi/SiPolicy.h>
+
+extern EFI_GUID gGpioLibUnlockHobGuid;
+
+//
+// GPIO Lock HOB
+// Stores information on GPIO pads that should be left unlocked
+//
+typedef struct {
+ //
+ // GPIO PadConfig unlock data
+ //
+ UINT32 PadConfig;
+ //
+ // GPIO Output unlock data
+ //
+ UINT32 OutputState;
+} GPIO_UNLOCK_HOB_DATA;
+
+/**
+ This procedure will get index of GPIO Unlock HOB structure for selected GroupIndex and DwNum.
+
+ @param[in] GroupIndex GPIO group index
+ @param[in] DwNum DWORD index for a group.
+ For group which has less then 32 pads per group DwNum must be 0.
+
+ @retval GpioUnlockHobIndex
+**/
+STATIC
+UINT32
+GpioUnlockDataIndex (
+ IN UINT32 GroupIndex,
+ IN UINT32 DwNum
+ )
+{
+ UINT32 GpioUnlockDataIndex;
+ UINT32 Index;
+
+ GpioUnlockDataIndex = 0;
+
+ for (Index = 0; Index < GroupIndex; Index++) {
+ GpioUnlockDataIndex += GPIO_GET_DW_NUM (GpioGetPadPerGroup (GpioGetGroupFromGroupIndex (Index))) + 1;
+ }
+
+ GpioUnlockDataIndex += DwNum;
+ return GpioUnlockDataIndex;
+}
+
+/**
+ This procedure will create GPIO HOB for storing unlock data
+
+ @retval Pointer to GPIO Unlock data structure
+**/
+STATIC
+GPIO_UNLOCK_HOB_DATA*
+GpioCreateUnlockData (
+ VOID
+ )
+{
+ VOID *HobData;
+ GPIO_GROUP Group;
+ GPIO_GROUP GroupMin;
+ GPIO_GROUP GroupMax;
+ UINT32 GpioUnlockDataRecords;
+
+ GroupMin = GpioGetLowestGroup ();
+ GroupMax = GpioGetHighestGroup ();
+ GpioUnlockDataRecords = 0;
+
+ for (Group = GroupMin; Group <= GroupMax; Group++) {
+ GpioUnlockDataRecords += GPIO_GET_DW_NUM (GpioGetPadPerGroup (Group)) + 1;
+ }
+
+ HobData = BuildGuidHob (&gGpioLibUnlockHobGuid, GpioUnlockDataRecords * sizeof (GPIO_UNLOCK_HOB_DATA));
+ if (HobData == NULL) {
+ return NULL;
+ }
+
+ ZeroMem (HobData, GpioUnlockDataRecords * sizeof (GPIO_UNLOCK_HOB_DATA));
+
+ return (GPIO_UNLOCK_HOB_DATA*)HobData;
+}
+
+/**
+ This procedure will Get GPIO Unlock data structure for storing unlock data.
+ If HOB doesn't exist it will be created.
+
+ @param[out] GpioUnlockData pointer to GPIO Unlock data structure
+
+ @retval Length number of GPIO unlock data records
+**/
+STATIC
+UINT32
+GpioGetUnlockData (
+ GPIO_UNLOCK_HOB_DATA **GpioUnlockData
+ )
+{
+ VOID *Hob;
+
+ Hob = GetFirstGuidHob (&gGpioLibUnlockHobGuid);
+ if (Hob == NULL) {
+ //
+ // It is the first time this function is used so create the HOB
+ //
+ *GpioUnlockData = GpioCreateUnlockData ();
+ if (*GpioUnlockData == NULL) {
+ return 0;
+ }
+ Hob = GetFirstGuidHob (&gGpioLibUnlockHobGuid);
+ } else {
+ *GpioUnlockData = (GPIO_UNLOCK_HOB_DATA*) GET_GUID_HOB_DATA (Hob);
+ }
+ return GET_GUID_HOB_DATA_SIZE (Hob) / sizeof (GPIO_UNLOCK_HOB_DATA);
+}
+
+/**
+ This procedure stores GPIO group data about pads which PadConfig needs to be unlocked.
+
+ @param[in] GroupIndex GPIO group index
+ @param[in] DwNum DWORD index for a group.
+ For group which has less then 32 pads per group DwNum must be 0.
+ @param[in] UnlockedPads DWORD bitmask for pads which are going to be left unlocked
+ Bit position - PadNumber
+ Bit value - 0: Skip, 1: Leave unlocked
+
+ @retval Status
+**/
+EFI_STATUS
+GpioStoreGroupDwUnlockPadConfigData (
+ IN UINT32 GroupIndex,
+ IN UINT32 DwNum,
+ IN UINT32 UnlockedPads
+ )
+{
+ GPIO_UNLOCK_HOB_DATA *GpioUnlockData;
+ UINT32 Length;
+ UINT32 Index;
+
+ if (UnlockedPads == 0) {
+ //
+ // No pads to be left unlocked
+ //
+ return EFI_SUCCESS;
+ }
+
+ Length = GpioGetUnlockData (&GpioUnlockData);
+ if (Length == 0) {
+ return EFI_NOT_FOUND;
+ }
+
+ Index = GpioUnlockDataIndex (GroupIndex, DwNum);
+ if (Index >= Length) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ GpioUnlockData[Index].PadConfig |= UnlockedPads;
+ return EFI_SUCCESS;
+}
+
+/**
+ This procedure stores GPIO group data about pads which Output state needs to be unlocked.
+
+ @param[in] GroupIndex GPIO group index
+ @param[in] DwNum DWORD index for a group.
+ For group which has less then 32 pads per group DwNum must be 0.
+ @param[in] UnlockedPads DWORD bitmask for pads which are going to be left unlocked
+ Bit position - PadNumber
+ Bit value - 0: Skip, 1: Leave unlocked
+ @retval Status
+**/
+EFI_STATUS
+GpioStoreGroupDwUnlockOutputData (
+ IN UINT32 GroupIndex,
+ IN UINT32 DwNum,
+ IN UINT32 UnlockedPads
+ )
+{
+ GPIO_UNLOCK_HOB_DATA *GpioUnlockData;
+ UINT32 Length;
+ UINT32 Index;
+
+ if (UnlockedPads == 0) {
+ //
+ // No pads to be left unlocked
+ //
+ return EFI_SUCCESS;
+ }
+
+ Length = GpioGetUnlockData (&GpioUnlockData);
+ if (Length == 0) {
+ return EFI_NOT_FOUND;
+ }
+
+ Index = GpioUnlockDataIndex (GroupIndex, DwNum);
+ if (Index >= Length) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ GpioUnlockData[Index].OutputState |= UnlockedPads;
+ return EFI_SUCCESS;
+}
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiGpioHelpersLib/PeiGpioHelpersLib.inf b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiGpioHelpersLib/PeiGpioHelpersLib.inf
new file mode 100644
index 0000000000..c1886b22f9
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiGpioHelpersLib/PeiGpioHelpersLib.inf
@@ -0,0 +1,46 @@
+## @file
+# Component description file for the PeiGpioHelpersLib
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+
+[Defines]
+INF_VERSION = 0x00010017
+BASE_NAME = PeiGpioHelpersLib
+FILE_GUID = 1838E1E7-3CC4-4A74-90D9-B421EF2A579F
+VERSION_STRING = 1.0
+MODULE_TYPE = PEIM
+LIBRARY_CLASS = GpioHelpersLib
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = IA32 X64 IPF EBC
+#
+
+
+[LibraryClasses]
+BaseLib
+IoLib
+DebugLib
+HobLib
+GpioLib
+ConfigBlockLib
+PeiServicesLib
+
+
+[Packages]
+MdePkg/MdePkg.dec
+AlderlakeSiliconPkg/SiPkg.dec
+
+
+[Sources]
+PeiGpioHelpersLib.c
+
+
+[Guids]
+gGpioLibUnlockHobGuid
+
+[Ppis]
+gSiPreMemPolicyPpiGuid
--
2.36.1.windows.1
-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#108688): https://edk2.groups.io/g/devel/message/108688
Mute This Topic: https://groups.io/mt/101373944/7686176
Group Owner: devel+owner@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [rebecca@openfw.io]
-=-=-=-=-=-=-=-=-=-=-=-
^ permalink raw reply related [flat|nested] 41+ messages in thread
* Re: [edk2-devel] [PATCH v2 02/10] AlderlakeSiliconPkg/IpBlock: Add Graphics, HostBridge, PcieRp components
2023-09-15 4:45 ` [edk2-devel] [PATCH v2 02/10] AlderlakeSiliconPkg/IpBlock: Add Graphics, HostBridge, PcieRp components Saloni Kasbekar
@ 2023-09-15 5:42 ` Chaganty, Rangasai V
2023-09-15 13:27 ` Chuang, Rosen
2023-09-15 23:56 ` Nate DeSimone
1 sibling, 1 reply; 41+ messages in thread
From: Chaganty, Rangasai V @ 2023-09-15 5:42 UTC (permalink / raw)
To: Kasbekar, Saloni, devel@edk2.groups.io
Cc: Desimone, Nathaniel L, Chuang, Rosen
Reviewed-by: Sai Chaganty <rangasai.v.chaganty@intel.com>
-----Original Message-----
From: Kasbekar, Saloni <saloni.kasbekar@intel.com>
Sent: Thursday, September 14, 2023 9:46 PM
To: devel@edk2.groups.io
Cc: Kasbekar, Saloni <saloni.kasbekar@intel.com>; Chaganty, Rangasai V <rangasai.v.chaganty@intel.com>; Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>; Chuang, Rosen <rosen.chuang@intel.com>
Subject: [PATCH v2 02/10] AlderlakeSiliconPkg/IpBlock: Add Graphics, HostBridge, PcieRp components
Adds the following modules:
- IpBlock/Graphics/Include
- IpBlock/Graphics/IncludePrivate
- IpBlock/Graphics/Library
- IpBlock/Graphics/LibraryPrivate
- IpBlock/HostBridge/IncludePrivate
- IpBlock/PcieRp/Library
Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Rosen Chuang <rosen.chuang@intel.com>
Signed-off-by: Saloni Kasbekar <saloni.kasbekar@intel.com>
---
.../Include/Ppi/GraphicsPlatformPolicyPpi.h | 76 +++++++++++
.../Library/DxeGraphicsPolicyLib.h | 71 +++++++++++
.../Library/DxeIgdOpRegionInitLib.h | 115 +++++++++++++++++
.../GraphicsInfoLibVer1.c | 52 ++++++++
.../GraphicsInfoLibVer1.inf | 33 +++++
.../DxeGraphicsPolicyLib.c | 116 +++++++++++++++++
.../DxeGraphicsPolicyLib.inf | 36 ++++++
.../DxeIgdOpRegionInit.c | 119 ++++++++++++++++++
.../DxeIgdOpRegionInitLib.inf | 47 +++++++
.../IncludePrivate/HostBridgeDataHob.h | 25 ++++
.../PchPcieRpLibInternal.h | 20 +++
.../PeiDxeSmmPchPcieRpLib/PchPcieRpLibVer2.c | 71 +++++++++++
.../PeiDxeSmmPchPcieRpLibVer2.inf | 37 ++++++
13 files changed, 818 insertions(+)
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/Include/Ppi/GraphicsPlatformPolicyPpi.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/IncludePrivate/Library/DxeGraphicsPolicyLib.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/IncludePrivate/Library/DxeIgdOpRegionInitLib.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/Library/PeiDxeSmmGraphicsInfoLib/GraphicsInfoLibVer1.c
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/Library/PeiDxeSmmGraphicsInfoLib/GraphicsInfoLibVer1.inf
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/LibraryPrivate/DxeGraphicsPolicyLib/DxeGraphicsPolicyLib.c
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/LibraryPrivate/DxeGraphicsPolicyLib/DxeGraphicsPolicyLib.inf
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/LibraryPrivate/DxeIgdOpRegionInitLib/DxeIgdOpRegionInit.c
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/LibraryPrivate/DxeIgdOpRegionInitLib/DxeIgdOpRegionInitLib.inf
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/HostBridge/IncludePrivate/HostBridgeDataHob.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PcieRp/Library/PeiDxeSmmPchPcieRpLib/PchPcieRpLibInternal.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PcieRp/Library/PeiDxeSmmPchPcieRpLib/PchPcieRpLibVer2.c
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PcieRp/Library/PeiDxeSmmPchPcieRpLib/PeiDxeSmmPchPcieRpLibVer2.inf
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/Include/Ppi/GraphicsPlatformPolicyPpi.h b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/Include/Ppi/GraphicsPlatformPolicyPpi.h
new file mode 100644
index 0000000000..a8f67061a5
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/Include/Ppi/Gra
+++ phicsPlatformPolicyPpi.h
@@ -0,0 +1,76 @@
+/** @file
+ The PEI_GRAPHICS_PLATFORM_POLICY_PPI provides platform information to PEI Graphics PEIM.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/
+
+#ifndef _PEI_GRAPHICS_PLATFORM_POLICY_PPI_H_
+#define _PEI_GRAPHICS_PLATFORM_POLICY_PPI_H_
+
+/**
+ Globally unique identifier for PEI platform policy PPI.
+**/
+#define PEI_GRAPHICS_PLATFORM_POLICY_PPI_GUID \ { \
+ 0x4eabcd09, 0x43d3, 0x4b4d, { 0xb7, 0x3d, 0x43, 0xc8, 0xd9, 0x89,
+0x99, 0x5 } \ }
+
+#define PEI_GRAPHICS_PLATFORM_POLICY_REVISION 1
+
+/**
+Pre-declaration of PEI graphics platform policy PPI.
+**/
+typedef struct _PEI_GRAPHICS_PLATFORM_POLICY_PPI
+PEI_GRAPHICS_PLATFORM_POLICY_PPI;
+
+/**
+ Enum defining the different lid status values **/ typedef enum {
+ LidClosed,
+ LidOpen,
+ LidStatusMax
+} LID_STATUS;
+
+/**
+ This function gets the platform lid status for LFP displays.
+
+ @param[out] CurrentLidStatus Output variable to store the lid status.
+
+ @retval EFI_SUCCESS Correct lid status is returned.
+ @retval EFI_UNSUPPORTED Platform does not support lid.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *GET_PLATFORM_LID_STATUS) (
+ OUT LID_STATUS *CurrentLidStatus
+ );
+
+/**
+ This function gets the base address of loaded VBT.
+
+ @param[out] VbtAddress Starting address of the VBT is returned in this parameter.
+ @param[out] VbtSize Size of the VBT is returned in this parameter.
+
+ @retval EFI_SUCCESS If the VBT is loaded and parameters contain valid values.
+ @return Other error codes meaning VBT is not loaded and parameters contain invalid values.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *GET_VBT_DATA) (
+ OUT EFI_PHYSICAL_ADDRESS *VbtAddress,
+ OUT UINT32 *VbtSize
+ );
+
+/**
+ This defines the PEI Graphics Platform Policy PPI structure.
+**/
+struct _PEI_GRAPHICS_PLATFORM_POLICY_PPI {
+ UINT32 Revision; ///< Revision of current implementation.
+ GET_PLATFORM_LID_STATUS GetPlatformLidStatus; ///< Function Pointer for get platform lid status.
+ GET_VBT_DATA GetVbtData; ///< Function pointer for get vbt data.
+};
+
+extern EFI_GUID gPeiGraphicsPlatformPpiGuid;
+
+#endif
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/IncludePrivate/Library/DxeGraphicsPolicyLib.h b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/IncludePrivate/Library/DxeGraphicsPolicyLib.h
new file mode 100644
index 0000000000..0347d4c94c
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/IncludePrivate/
+++ Library/DxeGraphicsPolicyLib.h
@@ -0,0 +1,71 @@
+/** @file
+ Header file for the DXE Graphics Policy Init library.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/ #ifndef
+_DXE_GRAPHICS_POLICY_LIB_H_ #define _DXE_GRAPHICS_POLICY_LIB_H_
+
+#include <Uefi.h>
+#include <Library/DebugLib.h>
+#include <Library/UefiLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/MemoryAllocationLib.h> #include <Protocol/SaPolicy.h>
+#include <ConfigBlock.h> #include <GraphicsConfig.h> #include
+<Library/SiConfigBlockLib.h>
+
+#define WORD_FIELD_VALID_BIT BIT15
+
+extern EFI_GUID gGraphicsDxeConfigGuid;
+
+/**
+ This function prints the Graphics DXE phase policy.
+
+ @param[in] SaPolicy - SA DXE Policy protocol **/ VOID
+GraphicsDxePolicyPrint (
+ IN SA_POLICY_PROTOCOL *SaPolicy
+ );
+
+/**
+ This function Load default Graphics DXE policy.
+
+ @param[in] ConfigBlockPointer The pointer to add Graphics config block
+**/
+VOID
+LoadIgdDxeDefault (
+ IN VOID *ConfigBlockPointer
+ );
+
+
+/**
+ Get DXE Graphics config block table total size.
+
+ @retval Size of DXE Graphics config block table
+**/
+UINT16
+EFIAPI
+GraphicsGetConfigBlockTotalSizeDxe (
+ VOID
+ );
+
+/**
+ GraphicsAddConfigBlocksDxe add all DXE Graphics config block.
+
+ @param[in] ConfigBlockTableAddress The pointer to add SA config blocks
+
+ @retval EFI_SUCCESS The policy default is initialized.
+ @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer
+**/
+EFI_STATUS
+EFIAPI
+GraphicsAddConfigBlocksDxe (
+ IN VOID *ConfigBlockTableAddress
+ );
+
+#endif // _DXE_GRAPHICs_POLICY_LIBRARY_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/IncludePrivate/Library/DxeIgdOpRegionInitLib.h b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/IncludePrivate/Library/DxeIgdOpRegionInitLib.h
new file mode 100644
index 0000000000..02e4988b2b
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/IncludePrivate/
+++ Library/DxeIgdOpRegionInitLib.h
@@ -0,0 +1,115 @@
+/** @file
+ This is part of the implementation of an Intel Graphics drivers
+OpRegion /
+ Software SCI interface between system BIOS, ASL code, and Graphics drivers.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/ #ifndef
+_DXE_IGD_OPREGION_INIT_LIB_H_ #define _DXE_IGD_OPREGION_INIT_LIB_H_
+
+///
+/// Statements that include other header files.
+///
+#include <Uefi.h>
+#include <Uefi/UefiBaseType.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <IndustryStandard/Pci.h>
+#include <Library/ConfigBlockLib.h>
+#include <Library/PciSegmentLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/MemoryAllocationLib.h> #include <Library/IoLib.h>
+#include <Library/DebugLib.h> #include <Library/HobLib.h> #include
+<Library/UefiLib.h> #include <Library/S3BootScriptLib.h> #include
+<Register/IgdRegs.h> #include <SiConfigHob.h> #include
+<Register/SaRegsHostBridge.h> /// /// Driver Consumed Protocol
+Prototypes /// #include <Protocol/PciIo.h> #include
+<Protocol/PciRootBridgeIo.h> #include <Protocol/SaPolicy.h> /// ///
+Driver Produced Protocol Prototypes /// #include
+<Protocol/IgdOpRegion.h>
+
+#pragma pack(push, 1)
+///
+///
+/// OpRegion (Miscellaneous) defines.
+///
+/// OpRegion Header defines.
+///
+typedef UINT16 STRING_REF;
+///
+/// Typedef stuctures
+///
+typedef struct {
+ UINT16 Signature; /// 0xAA55
+ UINT8 Size512;
+ UINT8 Reserved[21];
+ UINT16 PcirOffset;
+ UINT16 VbtOffset;
+} INTEL_VBIOS_OPTION_ROM_HEADER;
+
+typedef struct {
+ UINT32 Signature; /// "PCIR"
+ UINT16 VendorId; /// 0x8086
+ UINT16 DeviceId;
+ UINT16 Reserved0;
+ UINT16 Length;
+ UINT8 Revision;
+ UINT8 ClassCode[3];
+ UINT16 ImageLength;
+ UINT16 CodeRevision;
+ UINT8 CodeType;
+ UINT8 Indicator;
+ UINT16 Reserved1;
+} INTEL_VBIOS_PCIR_STRUCTURE;
+
+typedef struct {
+ UINT8 HeaderSignature[20];
+ UINT16 HeaderVersion;
+ UINT16 HeaderSize;
+ UINT16 HeaderVbtSize;
+ UINT8 HeaderVbtCheckSum;
+ UINT8 HeaderReserved;
+ UINT32 HeaderOffsetVbtDataBlock;
+ UINT32 HeaderOffsetAim1;
+ UINT32 HeaderOffsetAim2;
+ UINT32 HeaderOffsetAim3;
+ UINT32 HeaderOffsetAim4;
+ UINT8 DataHeaderSignature[16];
+ UINT16 DataHeaderVersion;
+ UINT16 DataHeaderSize;
+ UINT16 DataHeaderDataBlockSize;
+ UINT8 CoreBlockId;
+ UINT16 CoreBlockSize;
+ UINT16 CoreBlockBiosSize;
+ UINT8 CoreBlockBiosType;
+ UINT8 CoreBlockReleaseStatus;
+ UINT8 CoreBlockHWSupported;
+ UINT8 CoreBlockIntegratedHW;
+ UINT8 CoreBlockBiosBuild[4];
+ UINT8 CoreBlockBiosSignOn[155];
+} VBIOS_VBT_STRUCTURE;
+#pragma pack(pop)
+///
+/// Driver Private Function definitions ///
+
+/**
+ Update Graphics OpRegion after PCI enumeration.
+
+ @retval EFI_SUCCESS - The function completed successfully.
+**/
+EFI_STATUS
+UpdateIgdOpRegionEndOfDxe (
+ VOID
+ );
+#endif
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/Library/PeiDxeSmmGraphicsInfoLib/GraphicsInfoLibVer1.c b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/Library/PeiDxeSmmGraphicsInfoLib/GraphicsInfoLibVer1.c
new file mode 100644
index 0000000000..9dd9b33a49
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/Library/PeiDxeS
+++ mmGraphicsInfoLib/GraphicsInfoLibVer1.c
@@ -0,0 +1,52 @@
+/** @file
+ Source file for common Graphics Info Lib.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/ #include
+<Library/GraphicsInfoLib.h> #include <Register/IgdRegs.h> #include
+<Library/TimerLib.h> #include <Base.h>
+
+/**
+ GetIgdBusNumber: Get IGD Bus Number
+
+ @retval PCI bus number for IGD
+**/
+UINT8
+GetIgdBusNumber (
+ VOID
+ )
+{
+ return (UINT8) IGD_BUS_NUM;
+}
+
+/**
+ GetIgdDevNumber: Get IGD Dev Number
+
+ @retval PCI dev number for IGD
+**/
+UINT8
+GetIgdDevNumber (
+ VOID
+ )
+{
+ return (UINT8) IGD_DEV_NUM;
+}
+
+/**
+ GetIgdFunNumber: Get IGD Fun Number
+
+ @retval PCI fun number for IGD
+**/
+UINT8
+GetIgdFuncNumber (
+ VOID
+ )
+{
+ return (UINT8) IGD_FUN_NUM;
+}
+
+
+
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/Library/PeiDxeSmmGraphicsInfoLib/GraphicsInfoLibVer1.inf b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/Library/PeiDxeSmmGraphicsInfoLib/GraphicsInfoLibVer1.inf
new file mode 100644
index 0000000000..ca363ce105
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/Library/PeiDxeS
+++ mmGraphicsInfoLib/GraphicsInfoLibVer1.inf
@@ -0,0 +1,33 @@
+## @file
+# Graphics information library.
+#
+# All function in this library is available for PEI, DXE, and SMM, #
+But do not support UEFI RUNTIME environment call.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+
+[Defines]
+INF_VERSION = 0x00010017
+BASE_NAME = PeiDxeSmmGraphicsInfoLib
+FILE_GUID = AE4D5DE8-F092-4B2A-8003-F1A4CCBDC3E4
+VERSION_STRING = 1.0
+MODULE_TYPE = BASE
+LIBRARY_CLASS = GraphicsInfoLib
+
+[LibraryClasses]
+BaseLib
+IoLib
+DebugLib
+BaseMemoryLib
+PciSegmentLib
+TimerLib
+
+[Packages]
+MdePkg/MdePkg.dec
+AlderlakeSiliconPkg/SiPkg.dec
+
+[Sources]
+GraphicsInfoLibVer1.c
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/LibraryPrivate/DxeGraphicsPolicyLib/DxeGraphicsPolicyLib.c b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/LibraryPrivate/DxeGraphicsPolicyLib/DxeGraphicsPolicyLib.c
new file mode 100644
index 0000000000..a9344b424d
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/LibraryPrivate/
+++ DxeGraphicsPolicyLib/DxeGraphicsPolicyLib.c
@@ -0,0 +1,116 @@
+/** @file
+ This file provide services for DXE phase Graphics policy default initialization.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/
+
+#include <Library/DxeGraphicsPolicyLib.h>
+
+/**
+ This function prints the Graphics DXE phase policy.
+
+ @param[in] SaPolicy - SA DXE Policy protocol **/ VOID
+GraphicsDxePolicyPrint (
+ IN SA_POLICY_PROTOCOL *SaPolicy
+ )
+{
+ EFI_STATUS Status;
+ GRAPHICS_DXE_CONFIG *GraphicsDxeConfig;
+
+ //
+ // Get requisite IP Config Blocks which needs to be used here //
+ Status = GetConfigBlock ((VOID *) SaPolicy, &gGraphicsDxeConfigGuid,
+ (VOID *)&GraphicsDxeConfig); ASSERT_EFI_ERROR (Status);
+
+
+ DEBUG_CODE_BEGIN ();
+ DEBUG ((DEBUG_INFO, "\n------------------------ Graphics Policy (DXE)
+ print BEGIN -----------------\n")); DEBUG ((DEBUG_INFO, " Revision :
+ %d\n", GraphicsDxeConfig->Header.Revision));
+ ASSERT (GraphicsDxeConfig->Header.Revision ==
+ GRAPHICS_DXE_CONFIG_REVISION); DEBUG ((DEBUG_INFO,
+ "\n------------------------ Graphics Policy (DXE) print END
+ -----------------\n")); DEBUG_CODE_END ();
+
+ return;
+}
+
+
+/**
+ This function Load default Graphics DXE policy.
+
+ @param[in] ConfigBlockPointer The pointer to add Graphics config block
+**/
+VOID
+LoadIgdDxeDefault (
+ IN VOID *ConfigBlockPointer
+ )
+{
+ GRAPHICS_DXE_CONFIG *GraphicsDxeConfig;
+
+ GraphicsDxeConfig = ConfigBlockPointer;
+
+ ///
+ /// Initialize the Graphics configuration
+ ///
+ GraphicsDxeConfig->PlatformConfig = 1;
+ GraphicsDxeConfig->AlsEnable = 2;
+ GraphicsDxeConfig->BacklightControlSupport = 2;
+ GraphicsDxeConfig->IgdBlcConfig = 2;
+ GraphicsDxeConfig->GfxTurboIMON = 31;
+ ///
+ /// <EXAMPLE> Create a static Backlight Brightness Level Duty cycle
+Mapping Table
+ /// Possible 20 entries (example used 11), each 16 bits as follows:
+ /// [15] = Field Valid bit, [14:08] = Level in Percentage (0-64h), [07:00] = Desired duty cycle (0 - FFh).
+ ///
+ GraphicsDxeConfig->BCLM[0] = (0x0000 + WORD_FIELD_VALID_BIT); ///<
+0%
+ GraphicsDxeConfig->BCLM[1] = (0x0A19 + WORD_FIELD_VALID_BIT); ///<
+10%
+ GraphicsDxeConfig->BCLM[2] = (0x1433 + WORD_FIELD_VALID_BIT); ///<
+20%
+ GraphicsDxeConfig->BCLM[3] = (0x1E4C + WORD_FIELD_VALID_BIT); ///<
+30%
+ GraphicsDxeConfig->BCLM[4] = (0x2866 + WORD_FIELD_VALID_BIT); ///<
+40%
+ GraphicsDxeConfig->BCLM[5] = (0x327F + WORD_FIELD_VALID_BIT); ///<
+50%
+ GraphicsDxeConfig->BCLM[6] = (0x3C99 + WORD_FIELD_VALID_BIT); ///<
+60%
+ GraphicsDxeConfig->BCLM[7] = (0x46B2 + WORD_FIELD_VALID_BIT); ///<
+70%
+ GraphicsDxeConfig->BCLM[8] = (0x50CC + WORD_FIELD_VALID_BIT); ///<
+80%
+ GraphicsDxeConfig->BCLM[9] = (0x5AE5 + WORD_FIELD_VALID_BIT); ///<
+90%
+ GraphicsDxeConfig->BCLM[10] = (0x64FF + WORD_FIELD_VALID_BIT); ///<
+100% }
+
+static COMPONENT_BLOCK_ENTRY mGraphicsDxeIpBlocks = {
+ &gGraphicsDxeConfigGuid, sizeof (GRAPHICS_DXE_CONFIG),
+GRAPHICS_DXE_CONFIG_REVISION, LoadIgdDxeDefault};
+
+
+/**
+ Get DXE Graphics config block table total size.
+
+ @retval Size of DXE Graphics config block table
+**/
+UINT16
+EFIAPI
+GraphicsGetConfigBlockTotalSizeDxe (
+ VOID
+ )
+{
+ return mGraphicsDxeIpBlocks.Size;
+}
+
+/**
+ GraphicsAddConfigBlocksDxe add all DXE Graphics config block.
+
+ @param[in] ConfigBlockTableAddress The pointer to add SA config blocks
+
+ @retval EFI_SUCCESS The policy default is initialized.
+ @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer
+**/
+EFI_STATUS
+EFIAPI
+GraphicsAddConfigBlocksDxe (
+ IN VOID *ConfigBlockTableAddress
+ )
+{
+ EFI_STATUS Status;
+ Status = AddComponentConfigBlocks (ConfigBlockTableAddress,
+&mGraphicsDxeIpBlocks, 1);
+ return Status;
+}
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/LibraryPrivate/DxeGraphicsPolicyLib/DxeGraphicsPolicyLib.inf b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/LibraryPrivate/DxeGraphicsPolicyLib/DxeGraphicsPolicyLib.inf
new file mode 100644
index 0000000000..0fd6aba0bb
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/LibraryPrivate/
+++ DxeGraphicsPolicyLib/DxeGraphicsPolicyLib.inf
@@ -0,0 +1,36 @@
+## @file
+# Component description file for the DXE Graphics Policy Init library.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+[Defines]
+INF_VERSION = 0x00010017
+BASE_NAME = DxeGraphicsPolicyLib
+FILE_GUID = C6190599-287E-40F9-9B46-EE112A322EBF
+VERSION_STRING = 1.0
+MODULE_TYPE = BASE
+LIBRARY_CLASS = DxeGraphicsPolicyLib
+
+[LibraryClasses]
+BaseMemoryLib
+UefiRuntimeServicesTableLib
+UefiBootServicesTableLib
+DebugLib
+PostCodeLib
+ConfigBlockLib
+HobLib
+SiConfigBlockLib
+
+[Packages]
+MdePkg/MdePkg.dec
+AlderlakeSiliconPkg/SiPkg.dec
+
+[Sources]
+DxeGraphicsPolicyLib.c
+
+[Guids]
+gGraphicsDxeConfigGuid
+
+[Pcd]
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/LibraryPrivate/DxeIgdOpRegionInitLib/DxeIgdOpRegionInit.c b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/LibraryPrivate/DxeIgdOpRegionInitLib/DxeIgdOpRegionInit.c
new file mode 100644
index 0000000000..b3c9d28078
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/LibraryPrivate/
+++ DxeIgdOpRegionInitLib/DxeIgdOpRegionInit.c
@@ -0,0 +1,119 @@
+/** @file
+ This is part of the implementation of an Intel Graphics drivers
+OpRegion /
+ Software SCI interface between system BIOS, ASL code, and Graphics drivers.
+ The code in this file will load the driver and initialize the
+interface
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/
+
+#include <Library/DxeIgdOpRegionInitLib.h>
+
+
+
+GLOBAL_REMOVE_IF_UNREFERENCED IGD_OPREGION_PROTOCOL mIgdOpRegion;
+
+
+/**
+ Update Graphics OpRegion after PCI enumeration.
+
+ @param[in] void - None
+ @retval EFI_SUCCESS - The function completed successfully.
+**/
+EFI_STATUS
+UpdateIgdOpRegionEndOfDxe (
+ VOID
+)
+{
+ EFI_STATUS Status;
+ UINTN HandleCount;
+ EFI_HANDLE *HandleBuffer;
+ UINTN Index;
+ EFI_PCI_IO_PROTOCOL *PciIo;
+ PCI_TYPE00 Pci;
+ UINTN Segment;
+ UINTN Bus;
+ UINTN Device;
+ UINTN Function;
+
+ Bus = 0;
+ Device = 0;
+ Function = 0;
+
+ DEBUG ((DEBUG_INFO, "UpdateIgdOpRegionEndOfDxe\n"));
+
+ mIgdOpRegion.OpRegion->Header.PCON |= BIT8; //Set External Gfx
+ Adapter field is valid mIgdOpRegion.OpRegion->Header.PCON &= (UINT32)
+ (~BIT7); //Assume No External Gfx Adapter
+
+ ///
+ /// Get all PCI IO protocols handles
+ ///
+ Status = gBS->LocateHandleBuffer (
+ ByProtocol,
+ &gEfiPciIoProtocolGuid,
+ NULL,
+ &HandleCount,
+ &HandleBuffer
+ );
+
+ if (!EFI_ERROR (Status)) {
+ for (Index = 0; Index < HandleCount; Index++) {
+ ///
+ /// Get the PCI IO Protocol Interface corresponding to each handle
+ ///
+ Status = gBS->HandleProtocol (
+ HandleBuffer[Index],
+ &gEfiPciIoProtocolGuid,
+ (VOID **) &PciIo
+ );
+
+ if (!EFI_ERROR (Status)) {
+ ///
+ /// Read the PCI configuration space
+ ///
+ Status = PciIo->Pci.Read (
+ PciIo,
+ EfiPciIoWidthUint32,
+ 0,
+ sizeof (Pci) / sizeof (UINT32),
+ &Pci
+ );
+
+ ///
+ /// Find the display controllers devices
+ ///
+ if (!EFI_ERROR (Status) && IS_PCI_DISPLAY (&Pci)) {
+ Status = PciIo->GetLocation (
+ PciIo,
+ &Segment,
+ &Bus,
+ &Device,
+ &Function
+ );
+
+ //
+ // Assumption: Onboard devices will be sits on Bus no 0, while external devices will be sits on Bus no > 0
+ //
+ if (!EFI_ERROR (Status) && (Bus > 0)) {
+ //External Gfx Adapter Detected and Available
+ DEBUG ((DEBUG_INFO, "PCON - External Gfx Adapter Detected and Available\n"));
+ mIgdOpRegion.OpRegion->Header.PCON |= BIT7;
+ break;
+ }
+ }
+ }
+ }
+ }
+
+ ///
+ /// Free any allocated buffers
+ ///
+ if (HandleBuffer != NULL) {
+ FreePool (HandleBuffer);
+ }
+
+ ///
+ /// Return final status
+ ///
+ return Status;
+}
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/LibraryPrivate/DxeIgdOpRegionInitLib/DxeIgdOpRegionInitLib.inf b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/LibraryPrivate/DxeIgdOpRegionInitLib/DxeIgdOpRegionInitLib.inf
new file mode 100644
index 0000000000..e3a56d5563
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/LibraryPrivate/
+++ DxeIgdOpRegionInitLib/DxeIgdOpRegionInitLib.inf
@@ -0,0 +1,47 @@
+## @file
+# Component description file for the Dxe IGD OpRegion library.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+[Defines]
+INF_VERSION = 0x00010017
+BASE_NAME = DxeIgdOpRegionInitLib
+FILE_GUID = 18D47D72-555E-475B-A4E4-AD20C3BD8B15
+VERSION_STRING = 1.0
+MODULE_TYPE = DXE_DRIVER
+UEFI_SPECIFICATION_VERSION = 2.00
+LIBRARY_CLASS = DxeIgdOpRegionInitLib
+
+[LibraryClasses]
+UefiLib
+UefiRuntimeServicesTableLib
+UefiBootServicesTableLib
+DebugLib
+PostCodeLib
+ConfigBlockLib
+PciSegmentLib
+BaseMemoryLib
+MemoryAllocationLib
+IoLib
+S3BootScriptLib
+
+[Packages]
+MdePkg/MdePkg.dec
+AlderlakeSiliconPkg/SiPkg.dec
+IntelSiliconPkg/IntelSiliconPkg.dec
+
+[Pcd]
+gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress
+
+[Sources]
+DxeIgdOpRegionInit.c
+
+[Guids]
+gGraphicsDxeConfigGuid ## CONSUMES
+
+[Protocols]
+gIgdOpRegionProtocolGuid ## PRODUCES
+gSaPolicyProtocolGuid ## CONSUMES
+gEfiPciIoProtocolGuid ## CONSUMES
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/HostBridge/IncludePrivate/HostBridgeDataHob.h b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/HostBridge/IncludePrivate/HostBridgeDataHob.h
new file mode 100644
index 0000000000..671e821342
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/HostBridge/IncludePrivat
+++ e/HostBridgeDataHob.h
@@ -0,0 +1,25 @@
+/** @file
+ The GUID definition for Host Bridge Data Hob
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/ #ifndef
+_HOST_BRIDGE_DATA_HOB_H_ #define _HOST_BRIDGE_DATA_HOB_H_
+
+#include <Base.h>
+
+extern EFI_GUID gHostBridgeDataHobGuid; #pragma pack (push,1)
+
+///
+/// Host Bridge Data Hob
+///
+typedef struct {
+ EFI_HOB_GUID_TYPE EfiHobGuidType; ///< GUID Hob type structure for gSaDataHobGuid
+ UINT8 EnableAbove4GBMmio; ///< 0=Disable above 4GB MMIO resource support, 1=Enable above 4GB MMIO resource support
+ BOOLEAN SkipPamLock; ///< 0=All PAM registers will be locked in System Agent code, 1=Do not lock PAM registers in System Agent code.
+ UINT8 Rsvd1[2]; ///< Reserved for future use
+} HOST_BRIDGE_DATA_HOB;
+#pragma pack (pop)
+#endif
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PcieRp/Library/PeiDxeSmmPchPcieRpLib/PchPcieRpLibInternal.h b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PcieRp/Library/PeiDxeSmmPchPcieRpLib/PchPcieRpLibInternal.h
new file mode 100644
index 0000000000..e2be00fae7
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PcieRp/Library/PeiDxeSmm
+++ PchPcieRpLib/PchPcieRpLibInternal.h
@@ -0,0 +1,20 @@
+/** @file
+ PCIE root port library.
+ All function in this library is available for PEI, DXE, and SMM,
+ But do not support UEFI RUNTIME environment call.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/
+
+#ifndef _PCH_PCIE_RP_LIB_INTERNAL_H_
+#define _PCH_PCIE_RP_LIB_INTERNAL_H_
+
+typedef struct {
+ UINT8 DevNum;
+ UINT8 Pid;
+ UINT8 RpNumBase;
+} PCH_PCIE_CONTROLLER_INFO;
+
+#endif
+
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PcieRp/Library/PeiDxeSmmPchPcieRpLib/PchPcieRpLibVer2.c b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PcieRp/Library/PeiDxeSmmPchPcieRpLib/PchPcieRpLibVer2.c
new file mode 100644
index 0000000000..0702792597
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PcieRp/Library/PeiDxeSmm
+++ PchPcieRpLib/PchPcieRpLibVer2.c
@@ -0,0 +1,71 @@
+/** @file
+ PCIE root port library.
+ All function in this library is available for PEI, DXE, and SMM,
+ But do not support UEFI RUNTIME environment call.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/
+
+#include <Base.h>
+#include <Uefi/UefiBaseType.h>
+#include <Library/IoLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseLib.h>
+#include <Library/PciSegmentLib.h>
+#include <Library/PchInfoLib.h>
+#include <Library/PchPcrLib.h>
+#include <Library/PchPcieRpLib.h>
+#include <Register/PchRegs.h>
+#include <PchBdfAssignment.h>
+#include <PchPcieRpInfo.h>
+#include <Register/PchPcieRpRegs.h>
+#include <Register/PchPcrRegs.h>
+
+#include "PchPcieRpLibInternal.h"
+
+GLOBAL_REMOVE_IF_UNREFERENCED PCH_PCIE_CONTROLLER_INFO
+mPchPcieControllerInfo[] = {
+ { PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_1, PID_SPA, 0 },
+ { PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_5, PID_SPB, 4 },
+ { PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_9, PID_SPC, 8 },
+ { PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_13, PID_SPD, 12 },
+ { PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_17, PID_SPE, 16 }, // PCH-H
+only
+ { PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_21, PID_SPF, 20 } // PCH-H
+only };
+
+/**
+ Get Pch Pcie Root Port Device and Function Number by Root Port
+physical Number
+
+ @param[in] RpNumber Root port physical number. (0-based)
+ @param[out] RpDev Return corresponding root port device number.
+ @param[out] RpFun Return corresponding root port function number.
+
+ @retval EFI_SUCCESS Root port device and function is retrieved
+ @retval EFI_INVALID_PARAMETER RpNumber is invalid
+**/
+EFI_STATUS
+EFIAPI
+GetPchPcieRpDevFun (
+ IN UINTN RpNumber,
+ OUT UINTN *RpDev,
+ OUT UINTN *RpFun
+ )
+{
+ UINTN Index;
+ UINTN FuncIndex;
+ UINT32 PciePcd;
+
+ if (RpNumber >= GetPchMaxPciePortNum ()) {
+ DEBUG ((DEBUG_ERROR, "GetPchPcieRpDevFun invalid RpNumber %x", RpNumber));
+ ASSERT (FALSE);
+ return EFI_INVALID_PARAMETER;
+ }
+
+ Index = RpNumber / PCH_PCIE_CONTROLLER_PORTS; FuncIndex = RpNumber -
+ mPchPcieControllerInfo[Index].RpNumBase;
+ *RpDev = mPchPcieControllerInfo[Index].DevNum;
+ PciePcd = PchPcrRead32 (mPchPcieControllerInfo[Index].Pid,
+ R_SPX_PCR_PCD); *RpFun = (PciePcd >> (FuncIndex *
+ S_SPX_PCR_PCD_RP_FIELD)) & B_SPX_PCR_PCD_RP1FN;
+
+ return EFI_SUCCESS;
+}
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PcieRp/Library/PeiDxeSmmPchPcieRpLib/PeiDxeSmmPchPcieRpLibVer2.inf b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PcieRp/Library/PeiDxeSmmPchPcieRpLib/PeiDxeSmmPchPcieRpLibVer2.inf
new file mode 100644
index 0000000000..0acafbfc43
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PcieRp/Library/PeiDxeSmm
+++ PchPcieRpLib/PeiDxeSmmPchPcieRpLibVer2.inf
@@ -0,0 +1,37 @@
+## @file
+# PCIE root port Library.
+#
+# All function in this library is available for PEI, DXE, and SMM, #
+But do not support UEFI RUNTIME environment call.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+
+[Defines]
+INF_VERSION = 0x00010017
+BASE_NAME = PeiDxeSmmPchPcieRpLib
+FILE_GUID = B522981C-E0C5-4E04-A82A-C61D4F0B2C75
+VERSION_STRING = 1.0
+MODULE_TYPE = BASE
+LIBRARY_CLASS = PchPcieRpLib
+
+
+[LibraryClasses]
+BaseLib
+IoLib
+DebugLib
+PciSegmentLib
+PchInfoLib
+PchPcrLib
+
+
+[Packages]
+MdePkg/MdePkg.dec
+AlderlakeSiliconPkg/SiPkg.dec
+
+
+[Sources]
+PchPcieRpLibVer2.c
+
--
2.36.1.windows.1
-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#108687): https://edk2.groups.io/g/devel/message/108687
Mute This Topic: https://groups.io/mt/101373945/7686176
Group Owner: devel+owner@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [rebecca@openfw.io]
-=-=-=-=-=-=-=-=-=-=-=-
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [edk2-devel] [PATCH v2 03/10] AlderlakeSiliconPkg/IpBlock: Add P2sb, PchDmi components
2023-09-15 4:45 ` [edk2-devel] [PATCH v2 03/10] AlderlakeSiliconPkg/IpBlock: Add P2sb, PchDmi components Saloni Kasbekar
@ 2023-09-15 5:42 ` Chaganty, Rangasai V
2023-09-15 13:28 ` Chuang, Rosen
2023-09-15 23:56 ` Nate DeSimone
1 sibling, 1 reply; 41+ messages in thread
From: Chaganty, Rangasai V @ 2023-09-15 5:42 UTC (permalink / raw)
To: Kasbekar, Saloni, devel@edk2.groups.io
Cc: Desimone, Nathaniel L, Chuang, Rosen
Reviewed-by: Sai Chaganty <rangasai.v.chaganty@intel.com>
-----Original Message-----
From: Kasbekar, Saloni <saloni.kasbekar@intel.com>
Sent: Thursday, September 14, 2023 9:46 PM
To: devel@edk2.groups.io
Cc: Kasbekar, Saloni <saloni.kasbekar@intel.com>; Chaganty, Rangasai V <rangasai.v.chaganty@intel.com>; Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>; Chuang, Rosen <rosen.chuang@intel.com>
Subject: [PATCH v2 03/10] AlderlakeSiliconPkg/IpBlock: Add P2sb, PchDmi components
Adds the following modules:
- IpBlock/P2sb/IncludePrivate
- IpBlock/P2sb/Library
- IpBlock/P2sb/LibraryPrivate
- IpBlock/PchDmi/IncludePrivate
- IpBlock/PchDmi/LibraryPrivate
Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Rosen Chuang <rosen.chuang@intel.com>
Signed-off-by: Saloni Kasbekar <saloni.kasbekar@intel.com>
---
.../Library/P2SbSidebandAccessLib.h | 105 +++++++
.../IncludePrivate/Library/PchSbiAccessLib.h | 58 ++++
.../P2sb/IncludePrivate/P2SbController.h | 32 +++
.../P2sb/IncludePrivate/Register/P2sbRegs.h | 53 ++++
.../Library/PeiDxeSmmPchPcrLib/PchPcrLib.c | 266 ++++++++++++++++++
.../PeiDxeSmmPchPcrLib/PeiDxeSmmPchPcrLib.inf | 35 +++
.../PeiDxeSmmP2SbSidebandAccessLib.c | 208 ++++++++++++++
.../PeiDxeSmmP2SbSidebandAccessLib.inf | 30 ++
.../PchSbiAccessLib.c | 72 +++++
.../PeiDxeSmmPchSbiAccessLib.inf | 35 +++
.../PchDmi/IncludePrivate/Library/PchDmiLib.h | 60 ++++
.../PeiDxeSmmPchDmiLib/PchDmi14.c | 34 +++
.../PeiDxeSmmPchDmiLib/PchDmi14.h | 22 ++
.../PeiDxeSmmPchDmiLib/PchDmiLib.c | 110 ++++++++
.../PeiDxeSmmPchDmiLib/PeiDxeSmmPchDmiLib.inf | 43 +++
15 files changed, 1163 insertions(+)
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/IncludePrivate/Library/P2SbSidebandAccessLib.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/IncludePrivate/Library/PchSbiAccessLib.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/IncludePrivate/P2SbController.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/IncludePrivate/Register/P2sbRegs.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/Library/PeiDxeSmmPchPcrLib/PchPcrLib.c
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/Library/PeiDxeSmmPchPcrLib/PeiDxeSmmPchPcrLib.inf
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/LibraryPrivate/PeiDxeSmmP2SbSidebandAccessLib/PeiDxeSmmP2SbSidebandAccessLib.c
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/LibraryPrivate/PeiDxeSmmP2SbSidebandAccessLib/PeiDxeSmmP2SbSidebandAccessLib.inf
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/LibraryPrivate/PeiDxeSmmPchSbiAccessLib/PchSbiAccessLib.c
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/LibraryPrivate/PeiDxeSmmPchSbiAccessLib/PeiDxeSmmPchSbiAccessLib.inf
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PchDmi/IncludePrivate/Library/PchDmiLib.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivate/PeiDxeSmmPchDmiLib/PchDmi14.c
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivate/PeiDxeSmmPchDmiLib/PchDmi14.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivate/PeiDxeSmmPchDmiLib/PchDmiLib.c
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivate/PeiDxeSmmPchDmiLib/PeiDxeSmmPchDmiLib.inf
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/IncludePrivate/Library/P2SbSidebandAccessLib.h b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/IncludePrivate/Library/P2SbSidebandAccessLib.h
new file mode 100644
index 0000000000..e364508eb4
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/IncludePrivate/Libr
+++ ary/P2SbSidebandAccessLib.h
@@ -0,0 +1,105 @@
+/** @file
+ Header for P2SbSidebandAccessLib
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/
+
+#ifndef _P2SB_SIDEBAND_ACCESS_LIB_H_
+#define _P2SB_SIDEBAND_ACCESS_LIB_H_
+
+#include <RegisterAccess.h>
+#include <P2SbController.h>
+#include <Library/PchPcrLib.h> // For PCH_SBI_PID definition
+
+typedef PCH_SBI_PID P2SB_PID;
+
+typedef enum {
+ P2SbMemory = 0,
+ P2SbPciConfig,
+ P2SbPrivateConfig
+} P2SB_REGISTER_SPACE;
+
+typedef enum {
+ MemoryRead = 0x0,
+ MemoryWrite = 0x1,
+ PciConfigRead = 0x4,
+ PciConfigWrite = 0x5,
+ PrivateControlRead = 0x6,
+ PrivateControlWrite = 0x7,
+ GpioLockUnlock = 0x13
+} P2SB_SBI_OPCODE;
+
+typedef enum {
+ SBI_SUCCESSFUL = 0,
+ SBI_UNSUCCESSFUL = 1,
+ SBI_POWERDOWN = 2,
+ SBI_MIXED = 3,
+ SBI_INVALID_RESPONSE
+} P2SB_SBI_RESPONSE;
+
+typedef enum {
+ P2SbMmioAccess = 0,
+ P2SbMsgAccess
+} P2SB_SIDEBAND_ACCESS_METHOD;
+
+/**
+ REGISTER_ACCESS for P2SB device to support access to sideband registers.
+ Be sure to keep first member of this structure as REGISTER_ACCESS to
+allow
+ for correct casting between caller who sees this structure as
+REGISTER_ACCESS
+ and calle who will cast it to P2SB_SIDEBAND_REGISTER_ACCESS.
+**/
+typedef struct {
+ REGISTER_ACCESS Access;
+ P2SB_SIDEBAND_ACCESS_METHOD AccessMethod;
+ P2SB_PID P2SbPid;
+ UINT16 Fid;
+ P2SB_REGISTER_SPACE RegisterSpace;
+ BOOLEAN PostedWrites;
+ P2SB_CONTROLLER *P2SbCtrl;
+} P2SB_SIDEBAND_REGISTER_ACCESS;
+
+/**
+ Full function for executing P2SB SBI message
+ Take care of that there is no lock protection when using SBI programming in both POST time and SMI.
+ It will clash with POST time SBI programming when SMI happen.
+ Programmer MUST do the save and restore opration while using the
+PchSbiExecution inside SMI
+ to prevent from racing condition.
+ This function will reveal P2SB and hide P2SB if it's originally
+hidden. If more than one SBI access
+ needed, it's better to unhide the P2SB before calling and hide it back after done.
+
+ When the return value is "EFI_SUCCESS", the "Response" do not need to
+ be checked as it would have been SBI_SUCCESS. If the return value is
+ "EFI_DEVICE_ERROR", then this would provide additional information when needed.
+
+ @param[in] P2sbBase P2SB PCI config base
+ @param[in] Pid Port ID of the SBI message
+ @param[in] Offset Offset of the SBI message
+ @param[in] Opcode Opcode
+ @param[in] Posted Posted message
+ @param[in] Fbe First byte enable
+ @param[in] Bar Bar
+ @param[in] Fid Function ID
+ @param[in, out] Data32 Read/Write data
+ @param[out] Response Response
+
+ @retval EFI_SUCCESS Successfully completed.
+ @retval EFI_DEVICE_ERROR Transaction fail
+ @retval EFI_INVALID_PARAMETER Invalid parameter
+ @retval EFI_TIMEOUT Timeout while waiting for response
+**/
+EFI_STATUS
+P2SbSbiExecutionEx (
+ IN UINT64 P2sbBase,
+ IN P2SB_PID Pid,
+ IN UINT64 Offset,
+ IN P2SB_SBI_OPCODE Opcode,
+ IN BOOLEAN Posted,
+ IN UINT16 Fbe,
+ IN UINT16 Bar,
+ IN UINT16 Fid,
+ IN OUT UINT32 *Data32,
+ OUT UINT8 *Response
+ );
+
+#endif
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/IncludePrivate/Library/PchSbiAccessLib.h b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/IncludePrivate/Library/PchSbiAccessLib.h
new file mode 100644
index 0000000000..a46d8fb649
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/IncludePrivate/Libr
+++ ary/PchSbiAccessLib.h
@@ -0,0 +1,58 @@
+/** @file
+ Header file for PchSbiAccessLib.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/ #ifndef
+_PCH_SBI_ACCESS_LIB_H_ #define _PCH_SBI_ACCESS_LIB_H_
+
+#include <Library/PchPcrLib.h>
+#include <Library/P2SbSidebandAccessLib.h>
+
+typedef P2SB_SBI_OPCODE PCH_SBI_OPCODE ;
+
+typedef P2SB_SBI_RESPONSE PCH_SBI_RESPONSE;
+
+/**
+ Full function for executing PCH SBI message
+ Take care of that there is no lock protection when using SBI programming in both POST time and SMI.
+ It will clash with POST time SBI programming when SMI happen.
+ Programmer MUST do the save and restore opration while using the
+PchSbiExecution inside SMI
+ to prevent from racing condition.
+ This function will reveal P2SB and hide P2SB if it's originally
+hidden. If more than one SBI access
+ needed, it's better to unhide the P2SB before calling and hide it back after done.
+
+ When the return value is "EFI_SUCCESS", the "Response" do not need to
+ be checked as it would have been SBI_SUCCESS. If the return value is
+ "EFI_DEVICE_ERROR", then this would provide additional information when needed.
+
+ @param[in] Pid Port ID of the SBI message
+ @param[in] Offset Offset of the SBI message
+ @param[in] Opcode Opcode
+ @param[in] Posted Posted message
+ @param[in] Fbe First byte enable
+ @param[in] Bar Bar
+ @param[in] Fid Function ID
+ @param[in, out] Data32 Read/Write data
+ @param[out] Response Response
+
+ @retval EFI_SUCCESS Successfully completed.
+ @retval EFI_DEVICE_ERROR Transaction fail
+ @retval EFI_INVALID_PARAMETER Invalid parameter
+ @retval EFI_TIMEOUT Timeout while waiting for response
+**/
+EFI_STATUS
+PchSbiExecutionEx (
+ IN PCH_SBI_PID Pid,
+ IN UINT64 Offset,
+ IN PCH_SBI_OPCODE Opcode,
+ IN BOOLEAN Posted,
+ IN UINT16 Fbe,
+ IN UINT16 Bar,
+ IN UINT16 Fid,
+ IN OUT UINT32 *Data32,
+ OUT UINT8 *Response
+ );
+
+#endif // _PCH_SBI_ACCESS_LIB_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/IncludePrivate/P2SbController.h b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/IncludePrivate/P2SbController.h
new file mode 100644
index 0000000000..51c67d4624
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/IncludePrivate/P2Sb
+++ Controller.h
@@ -0,0 +1,32 @@
+/** @file
+ P2SB controller
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/ #ifndef
+_P2SB_CONTROLLER_H_ #define _P2SB_CONTROLLER_H_
+
+/**
+ P2SB structure
+ Stores information required to access to registers
+ like base address, S:B:D:F etc.
+ and definitions specific to P2SB.
+**/
+typedef struct {
+ /**
+ P2SB controller PCI config space address
+ in PCI Segment Library representation.
+ **/
+ UINT64 PciCfgBaseAddr;
+ /**
+ P2SB controller MMIO base address
+ **/
+ UINT64 Mmio;
+ /**
+ HPET MMIO base address
+ **/
+ UINT64 HpetMmio;
+} P2SB_CONTROLLER;
+
+#endif // _P2SB_CONTROLLER_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/IncludePrivate/Register/P2sbRegs.h b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/IncludePrivate/Register/P2sbRegs.h
new file mode 100644
index 0000000000..ffe35411f7
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/IncludePrivate/Regi
+++ ster/P2sbRegs.h
@@ -0,0 +1,53 @@
+/** @file
+ Register names for PCH P2SB device
+
+ Conventions:
+
+ - Register definition format:
+
+ Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_Re
+ gisterName
+ - Prefix:
+ Definitions beginning with "R_" are registers
+ Definitions beginning with "B_" are bits within registers
+ Definitions beginning with "V_" are meaningful values within the bits
+ Definitions beginning with "S_" are register size
+ Definitions beginning with "N_" are the bit position
+ - [GenerationName]:
+ Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc.).
+ Register name without GenerationName applies to all generations.
+ - [ComponentName]:
+ This field indicates the component name that the register belongs to (e.g. PCH, SA etc.)
+ Register name without ComponentName applies to all components.
+ Register that is specific to -H denoted by "_PCH_H_" in component name.
+ Register that is specific to -LP denoted by "_PCH_LP_" in component name.
+ - SubsystemName:
+ This field indicates the subsystem name of the component that the register belongs to
+ (e.g. PCIE, USB, SATA, GPIO, PMC etc.).
+ - RegisterSpace:
+ MEM - MMIO space register of subsystem.
+ IO - IO space register of subsystem.
+ PCR - Private configuration register of subsystem.
+ CFG - PCI configuration space register of subsystem.
+ - RegisterName:
+ Full register name.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/ #ifndef
+_P2SB_REGS_H_ #define _P2SB_REGS_H_
+
+//
+// Definition for SBI
+//
+#define R_P2SB_CFG_SBIADDR 0xD0
+#define R_P2SB_CFG_SBIDATA 0xD4
+#define R_P2SB_CFG_SBISTAT 0xD8
+#define B_P2SB_CFG_SBISTAT_OPCODE 0xFF00
+#define B_P2SB_CFG_SBISTAT_POSTED BIT7
+#define B_P2SB_CFG_SBISTAT_RESPONSE 0x0006
+#define N_P2SB_CFG_SBISTAT_RESPONSE 1
+#define B_P2SB_CFG_SBISTAT_INITRDY BIT0
+#define R_P2SB_CFG_SBIRID 0xDA
+#define R_P2SB_CFG_SBIEXTADDR 0xDC
+
+#endif
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/Library/PeiDxeSmmPchPcrLib/PchPcrLib.c b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/Library/PeiDxeSmmPchPcrLib/PchPcrLib.c
new file mode 100644
index 0000000000..a5b18613bc
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/Library/PeiDxeSmmPc
+++ hPcrLib/PchPcrLib.c
@@ -0,0 +1,266 @@
+/** @file
+ PCH PCR library.
+ All function in this library is available for PEI, DXE, and SMM,
+ But do not support UEFI RUNTIME environment call.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/
+
+#include <Base.h>
+#include <Uefi/UefiBaseType.h>
+#include <Library/IoLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseLib.h>
+#include <Library/PchInfoLib.h>
+#include <Library/PchPcrLib.h>
+#include <Library/PchSbiAccessLib.h>
+#include <Library/PciSegmentLib.h>
+#include <Register/PchPcrRegs.h>
+
+#ifndef MDEPKG_NDEBUG
+/**
+ Checks if the offset is valid for a given memory access width. Offset must align to width size.
+
+ @param[in] Offset Offset of a register
+ @param[in] Size Size of memory access in bytes
+
+ @retval FALSE Offset is not valid for a given memory access
+ @retval TRUE Offset is valid
+**/
+STATIC
+BOOLEAN
+PchIsPcrOffsetValid (
+ IN UINT32 Offset,
+ IN UINTN Size
+ )
+{
+ if (!IsP2sb20bPcrSupported ()) {
+ if (((Offset & (Size - 1)) != 0) || (Offset > 0xFFFF)) {
+ DEBUG ((DEBUG_ERROR, "PCR offset error. Invalid Offset: %x Size: %x", Offset, Size));
+ return FALSE;
+ } else {
+ return TRUE;
+ }
+ } else {
+ if (((Offset & (Size - 1)) != 0) || (Offset > 0xFFFFF)) {
+ DEBUG ((DEBUG_ERROR, "PCR offset error. Invalid Offset: %x Size: %x", Offset, Size));
+ return FALSE;
+ } else {
+ return TRUE;
+ }
+ }
+}
+#endif
+
+/**
+ Read PCR register.
+ It returns PCR register and size in 4bytes.
+ The Offset should not exceed 0xFFFF and must be aligned with size.
+
+ @param[in] Pid Port ID
+ @param[in] Offset Register offset of this Port ID
+
+ @retval UINT32 PCR register value.
+**/
+UINT32
+PchPcrRead32 (
+ IN PCH_SBI_PID Pid,
+ IN UINT32 Offset
+ )
+{
+#ifndef MDEPKG_NDEBUG
+ ASSERT (PchIsPcrOffsetValid (Offset, 4)); #endif
+ return MmioRead32 (PCH_PCR_ADDRESS (Pid, Offset)); }
+
+/**
+ Read PCR register.
+ It returns PCR register and size in 2bytes.
+ The Offset should not exceed 0xFFFF and must be aligned with size.
+
+ @param[in] Pid Port ID
+ @param[in] Offset Register offset of this Port ID
+
+ @retval UINT16 PCR register value.
+**/
+UINT16
+PchPcrRead16 (
+ IN PCH_SBI_PID Pid,
+ IN UINT32 Offset
+ )
+{
+#ifndef MDEPKG_NDEBUG
+ ASSERT (PchIsPcrOffsetValid (Offset, 2)); #endif
+ return MmioRead16 (PCH_PCR_ADDRESS (Pid, Offset)); }
+
+/**
+ Read PCR register.
+ It returns PCR register and size in 1bytes.
+ The Offset should not exceed 0xFFFF and must be aligned with size.
+
+ @param[in] Pid Port ID
+ @param[in] Offset Register offset of this Port ID
+
+ @retval UINT8 PCR register value
+**/
+UINT8
+PchPcrRead8 (
+ IN PCH_SBI_PID Pid,
+ IN UINT32 Offset
+ )
+{
+ return MmioRead8 (PCH_PCR_ADDRESS (Pid, Offset)); }
+
+/**
+ Write PCR register.
+ It programs PCR register and size in 4bytes.
+ The Offset should not exceed 0xFFFF and must be aligned with size.
+
+ @param[in] Pid Port ID
+ @param[in] Offset Register offset of Port ID.
+ @param[in] Data Input Data. Must be the same size as Size parameter.
+
+ @retval UINT32 Value written to register
+**/
+UINT32
+PchPcrWrite32 (
+ IN PCH_SBI_PID Pid,
+ IN UINT32 Offset,
+ IN UINT32 Data
+ )
+{
+#ifndef MDEPKG_NDEBUG
+ ASSERT (PchIsPcrOffsetValid (Offset, 4)); #endif
+ MmioWrite32 (PCH_PCR_ADDRESS (Pid, Offset), Data);
+
+ return Data;
+
+}
+
+/**
+ Write PCR register.
+ It programs PCR register and size in 2bytes.
+ The Offset should not exceed 0xFFFF and must be aligned with size.
+
+ @param[in] Pid Port ID
+ @param[in] Offset Register offset of Port ID.
+ @param[in] Data Input Data. Must be the same size as Size parameter.
+
+ @retval UINT16 Value written to register
+**/
+UINT16
+PchPcrWrite16 (
+ IN PCH_SBI_PID Pid,
+ IN UINT32 Offset,
+ IN UINT16 Data
+ )
+{
+#ifndef MDEPKG_NDEBUG
+ ASSERT (PchIsPcrOffsetValid (Offset, 2)); #endif
+ MmioWrite16 (PCH_PCR_ADDRESS (Pid, Offset), Data);
+
+ return Data;
+}
+
+/**
+ Write PCR register.
+ It programs PCR register and size in 1bytes.
+ The Offset should not exceed 0xFFFF and must be aligned with size.
+
+ @param[in] Pid Port ID
+ @param[in] Offset Register offset of Port ID.
+ @param[in] Data Input Data. Must be the same size as Size parameter.
+
+ @retval UINT8 Value written to register
+**/
+UINT8
+PchPcrWrite8 (
+ IN PCH_SBI_PID Pid,
+ IN UINT32 Offset,
+ IN UINT8 Data
+ )
+{
+
+ MmioWrite8 (PCH_PCR_ADDRESS (Pid, Offset), Data);
+
+ return Data;
+}
+
+/**
+ Write PCR register.
+ It programs PCR register and size in 4bytes.
+ The Offset should not exceed 0xFFFF and must be aligned with size.
+
+ @param[in] Pid Port ID
+ @param[in] Offset Register offset of Port ID.
+ @param[in] AndData AND Data. Must be the same size as Size parameter.
+ @param[in] OrData OR Data. Must be the same size as Size parameter.
+
+ @retval UINT32 Value written to register
+
+**/
+UINT32
+PchPcrAndThenOr32 (
+ IN PCH_SBI_PID Pid,
+ IN UINT32 Offset,
+ IN UINT32 AndData,
+ IN UINT32 OrData
+ )
+{
+ return PchPcrWrite32 (Pid, Offset, (PchPcrRead32 (Pid, Offset) &
+AndData) | OrData); }
+
+/**
+ Write PCR register.
+ It programs PCR register and size in 2bytes.
+ The Offset should not exceed 0xFFFF and must be aligned with size.
+
+ @param[in] Pid Port ID
+ @param[in] Offset Register offset of Port ID.
+ @param[in] AndData AND Data. Must be the same size as Size parameter.
+ @param[in] OrData OR Data. Must be the same size as Size parameter.
+
+ @retval UINT16 Value written to register
+
+**/
+UINT16
+PchPcrAndThenOr16 (
+ IN PCH_SBI_PID Pid,
+ IN UINT32 Offset,
+ IN UINT16 AndData,
+ IN UINT16 OrData
+ )
+{
+ return PchPcrWrite16 (Pid, Offset, (PchPcrRead16 (Pid, Offset) &
+AndData) | OrData); }
+
+/**
+ Write PCR register.
+ It programs PCR register and size in 1bytes.
+ The Offset should not exceed 0xFFFF and must be aligned with size.
+
+ @param[in] Pid Port ID
+ @param[in] Offset Register offset of Port ID.
+ @param[in] AndData AND Data. Must be the same size as Size parameter.
+ @param[in] OrData OR Data. Must be the same size as Size parameter.
+
+ @retval UINT8 Value written to register
+
+**/
+UINT8
+PchPcrAndThenOr8 (
+ IN PCH_SBI_PID Pid,
+ IN UINT32 Offset,
+ IN UINT8 AndData,
+ IN UINT8 OrData
+ )
+{
+ return PchPcrWrite8 (Pid, Offset, (PchPcrRead8 (Pid, Offset) &
+AndData) | OrData); }
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/Library/PeiDxeSmmPchPcrLib/PeiDxeSmmPchPcrLib.inf b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/Library/PeiDxeSmmPchPcrLib/PeiDxeSmmPchPcrLib.inf
new file mode 100644
index 0000000000..5e1b4914d8
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/Library/PeiDxeSmmPc
+++ hPcrLib/PeiDxeSmmPchPcrLib.inf
@@ -0,0 +1,35 @@
+## @file
+# PCH PCR Library.
+#
+# All function in this library is available for PEI, DXE, and SMM, #
+But do not support UEFI RUNTIME environment call.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+
+[Defines]
+INF_VERSION = 0x00010017
+BASE_NAME = PeiDxeSmmPchPcrLib
+FILE_GUID = 117C8D19-445B-46BF-B624-109F63709375
+VERSION_STRING = 1.0
+MODULE_TYPE = BASE
+LIBRARY_CLASS = PchPcrLib
+
+
+[LibraryClasses]
+BaseLib
+IoLib
+DebugLib
+PchInfoLib
+PchSbiAccessLib
+PciSegmentLib
+
+[Packages]
+MdePkg/MdePkg.dec
+AlderlakeSiliconPkg/SiPkg.dec
+
+
+[Sources]
+PchPcrLib.c
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/LibraryPrivate/PeiDxeSmmP2SbSidebandAccessLib/PeiDxeSmmP2SbSidebandAccessLib.c b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/LibraryPrivate/PeiDxeSmmP2SbSidebandAccessLib/PeiDxeSmmP2SbSidebandAccessLib.c
new file mode 100644
index 0000000000..52ec8fd9e1
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/LibraryPrivate/PeiD
+++ xeSmmP2SbSidebandAccessLib/PeiDxeSmmP2SbSidebandAccessLib.c
@@ -0,0 +1,208 @@
+/** @file
+ P2SB sideband access lib
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/
+
+#include <Base.h>
+#include <Uefi/UefiBaseType.h>
+#include <Library/IoLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseLib.h>
+#include <Library/PchInfoLib.h>
+#include <Library/P2SbSidebandAccessLib.h> #include
+<Library/PciSegmentLib.h> #include <Library/PchSbiAccessLib.h> #include
+<Register/P2sbRegs.h> #include <IndustryStandard/Pci30.h>
+
+#define P2SB_PCR_ADDRESS(MmioBase, Pid, Offset) ((UINTN) MmioBase |
+(UINT32) (((Offset) & 0x0F0000) << 8) | ((UINT8)(Pid) << 16) | (UINT16)
+((Offset) & 0xFFFF))
+
+/**
+ Full function for executing P2SB SBI message
+ Take care of that there is no lock protection when using SBI programming in both POST time and SMI.
+ It will clash with POST time SBI programming when SMI happen.
+ Programmer MUST do the save and restore opration while using the
+PchSbiExecution inside SMI
+ to prevent from racing condition.
+ This function will reveal P2SB and hide P2SB if it's originally
+hidden. If more than one SBI access
+ needed, it's better to unhide the P2SB before calling and hide it back after done.
+
+ When the return value is "EFI_SUCCESS", the "Response" do not need to
+ be checked as it would have been SBI_SUCCESS. If the return value is
+ "EFI_DEVICE_ERROR", then this would provide additional information when needed.
+
+ @param[in] P2sbBase P2SB PCI config base
+ @param[in] Pid Port ID of the SBI message
+ @param[in] Offset Offset of the SBI message
+ @param[in] Opcode Opcode
+ @param[in] Posted Posted message
+ @param[in] Fbe First byte enable
+ @param[in] Bar Bar
+ @param[in] Fid Function ID
+ @param[in, out] Data32 Read/Write data
+ @param[out] Response Response
+
+ @retval EFI_SUCCESS Successfully completed.
+ @retval EFI_DEVICE_ERROR Transaction fail
+ @retval EFI_INVALID_PARAMETER Invalid parameter
+ @retval EFI_TIMEOUT Timeout while waiting for response
+**/
+EFI_STATUS
+P2SbSbiExecutionEx (
+ IN UINT64 P2sbBase,
+ IN P2SB_PID Pid,
+ IN UINT64 Offset,
+ IN P2SB_SBI_OPCODE Opcode,
+ IN BOOLEAN Posted,
+ IN UINT16 Fbe,
+ IN UINT16 Bar,
+ IN UINT16 Fid,
+ IN OUT UINT32 *Data32,
+ OUT UINT8 *Response
+ )
+{
+ INT32 Timeout;
+ UINT16 SbiStat;
+
+ //
+ // Check opcode valid
+ //
+ switch (Opcode) {
+ case MemoryRead:
+ case MemoryWrite:
+ case PciConfigRead:
+ case PciConfigWrite:
+ case PrivateControlRead:
+ case PrivateControlWrite:
+ case GpioLockUnlock:
+ break;
+ default:
+ return EFI_INVALID_PARAMETER;
+ break;
+ }
+
+ if (PciSegmentRead16 (P2sbBase + PCI_VENDOR_ID_OFFSET) == 0xFFFF) {
+ ASSERT (FALSE);
+ return EFI_DEVICE_ERROR;
+ }
+ ///
+ /// BWG Section 2.2.1
+ /// 1. Poll P2SB PCI offset D8h[0] = 0b /// Make sure the previous
+ opeartion is completed.
+ ///
+ Timeout = 0xFFFFFFF;
+ while (Timeout > 0) {
+ SbiStat = PciSegmentRead16 (P2sbBase + R_P2SB_CFG_SBISTAT);
+ if ((SbiStat & B_P2SB_CFG_SBISTAT_INITRDY) == 0) {
+ break;
+ }
+ Timeout--;
+ }
+ if (Timeout == 0) {
+ return EFI_TIMEOUT;
+ }
+ //
+ // Initial Response status
+ //
+ *Response = SBI_INVALID_RESPONSE;
+ SbiStat = 0;
+ ///
+ /// 2. Write P2SB PCI offset D0h[31:0] with Address and Destination
+ Port ID ///
+ PciSegmentWrite32 (P2sbBase + R_P2SB_CFG_SBIADDR, (UINT32) ((Pid <<
+ 24) | (UINT16) Offset)); /// /// 3. Write P2SB PCI offset DCh[31:0]
+ with extended address, which is expected to be 0 in CNL PCH.
+ ///
+ PciSegmentWrite32 (P2sbBase + R_P2SB_CFG_SBIEXTADDR, (UINT32)
+ RShiftU64 (Offset, 16)); /// /// 5. Set P2SB PCI offset D8h[15:8] =
+ 00000110b for read
+ /// Set P2SB PCI offset D8h[15:8] = 00000111b for write
+ //
+ // Set SBISTAT[15:8] to the opcode passed in // Set SBISTAT[7] to
+ the posted passed in //
+ PciSegmentAndThenOr16 (
+ (P2sbBase + R_P2SB_CFG_SBISTAT),
+ (UINT16) ~(B_P2SB_CFG_SBISTAT_OPCODE | B_P2SB_CFG_SBISTAT_POSTED),
+ (UINT16) ((Opcode << 8) | (Posted << 7))
+ );
+ ///
+ /// 6. Write P2SB PCI offset DAh[15:0] = F000h /// // // Set
+ RID[15:0] = Fbe << 12 | Bar << 8 | Fid //
+ PciSegmentWrite16 (
+ (P2sbBase + R_P2SB_CFG_SBIRID),
+ (((Fbe & 0x000F) << 12) | ((Bar & 0x0007) << 8) | (Fid & 0x00FF))
+ );
+
+ switch (Opcode) {
+ case MemoryWrite:
+ case PciConfigWrite:
+ case PrivateControlWrite:
+ case GpioLockUnlock:
+ ///
+ /// 4. Write P2SB PCI offset D4h[31:0] with the intended data accordingly
+ ///
+ PciSegmentWrite32 ((P2sbBase + R_P2SB_CFG_SBIDATA), *Data32);
+ break;
+ default:
+ ///
+ /// 4. Write P2SB PCI offset D4h[31:0] with dummy data such as 0,
+ /// because all D0-DFh register range must be touched in CNL PCH
+ /// for a successful SBI transaction.
+ ///
+ PciSegmentWrite32 ((P2sbBase + R_P2SB_CFG_SBIDATA), 0);
+ break;
+ }
+ ///
+ /// 7. Set P2SB PCI offset D8h[0] = 1b, Poll P2SB PCI offset D8h[0] =
+0b
+ ///
+ //
+ // Set SBISTAT[0] = 1b, trigger the SBI operation
+ //
+ PciSegmentOr16 (P2sbBase + R_P2SB_CFG_SBISTAT, (UINT16)
+B_P2SB_CFG_SBISTAT_INITRDY);
+ //
+ // Poll SBISTAT[0] = 0b, Polling for Busy bit
+ //
+ Timeout = 0xFFFFFFF;
+ while (Timeout > 0) {
+ SbiStat = PciSegmentRead16 (P2sbBase + R_P2SB_CFG_SBISTAT);
+ if ((SbiStat & B_P2SB_CFG_SBISTAT_INITRDY) == 0) {
+ break;
+ }
+ Timeout--;
+ }
+ if (Timeout == 0) {
+ //
+ // If timeout, it's fatal error.
+ //
+ return EFI_TIMEOUT;
+ } else {
+ ///
+ /// 8. Check if P2SB PCI offset D8h[2:1] = 00b for successful transaction
+ ///
+ *Response = (UINT8) ((SbiStat & B_P2SB_CFG_SBISTAT_RESPONSE) >> N_P2SB_CFG_SBISTAT_RESPONSE);
+ if (*Response == SBI_SUCCESSFUL) {
+ switch (Opcode) {
+ case MemoryRead:
+ case PciConfigRead:
+ case PrivateControlRead:
+ ///
+ /// 9. Read P2SB PCI offset D4h[31:0] for SBI data
+ ///
+ *Data32 = PciSegmentRead32 (P2sbBase + R_P2SB_CFG_SBIDATA);
+ break;
+ default:
+ break;
+ }
+ return EFI_SUCCESS;
+ } else if (*Response == SBI_POWERDOWN) {
+ return EFI_NO_RESPONSE;
+ } else {
+ return EFI_DEVICE_ERROR;
+ }
+ }
+}
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/LibraryPrivate/PeiDxeSmmP2SbSidebandAccessLib/PeiDxeSmmP2SbSidebandAccessLib.inf b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/LibraryPrivate/PeiDxeSmmP2SbSidebandAccessLib/PeiDxeSmmP2SbSidebandAccessLib.inf
new file mode 100644
index 0000000000..9530e56940
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/LibraryPrivate/PeiD
+++ xeSmmP2SbSidebandAccessLib/PeiDxeSmmP2SbSidebandAccessLib.inf
@@ -0,0 +1,30 @@
+## @file
+# Library for accessing sideband register banks via the P2SB router.
+#
+# All function in this library is available for PEI, DXE, and SMM, #
+But do not support UEFI RUNTIME environment call.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+
+[Defines]
+INF_VERSION = 0x00010017
+BASE_NAME = PeiDxeSmmP2SbSidebandAccessLib FILE_GUID =
+425C479D-A489-4382-8C28-59A3521A24FF
+VERSION_STRING = 1.0
+MODULE_TYPE = BASE
+LIBRARY_CLASS = P2SbSidebandAccessLib
+
+[LibraryClasses]
+BaseLib
+IoLib
+DebugLib
+
+[Packages]
+MdePkg/MdePkg.dec
+AlderlakeSiliconPkg/SiPkg.dec
+
+[Sources]
+PeiDxeSmmP2SbSidebandAccessLib.c
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/LibraryPrivate/PeiDxeSmmPchSbiAccessLib/PchSbiAccessLib.c b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/LibraryPrivate/PeiDxeSmmPchSbiAccessLib/PchSbiAccessLib.c
new file mode 100644
index 0000000000..1f7bb82692
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/LibraryPrivate/PeiD
+++ xeSmmPchSbiAccessLib/PchSbiAccessLib.c
@@ -0,0 +1,72 @@
+/** @file
+ PCH SBI access library.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/
+
+#include <Base.h>
+#include <Uefi/UefiBaseType.h>
+#include <Library/IoLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseLib.h>
+#include <Library/PchSbiAccessLib.h>
+#include <Library/P2SbSidebandAccessLib.h> #include
+<Library/PchPciBdfLib.h> #include <Register/PchRegs.h> #include
+<Register/P2sbRegs.h>
+
+/**
+ Full function for executing PCH SBI message
+ Take care of that there is no lock protection when using SBI programming in both POST time and SMI.
+ It will clash with POST time SBI programming when SMI happen.
+ Programmer MUST do the save and restore opration while using the
+PchSbiExecution inside SMI
+ to prevent from racing condition.
+ This function will reveal P2SB and hide P2SB if it's originally
+hidden. If more than one SBI access
+ needed, it's better to unhide the P2SB before calling and hide it back after done.
+
+ When the return value is "EFI_SUCCESS", the "Response" do not need to
+ be checked as it would have been SBI_SUCCESS. If the return value is
+ "EFI_DEVICE_ERROR", then this would provide additional information when needed.
+
+ @param[in] Pid Port ID of the SBI message
+ @param[in] Offset Offset of the SBI message
+ @param[in] Opcode Opcode
+ @param[in] Posted Posted message
+ @param[in] Fbe First byte enable
+ @param[in] Bar Bar
+ @param[in] Fid Function ID
+ @param[in, out] Data32 Read/Write data
+ @param[out] Response Response
+
+ @retval EFI_SUCCESS Successfully completed.
+ @retval EFI_DEVICE_ERROR Transaction fail
+ @retval EFI_INVALID_PARAMETER Invalid parameter
+ @retval EFI_TIMEOUT Timeout while waiting for response
+**/
+EFI_STATUS
+PchSbiExecutionEx (
+ IN PCH_SBI_PID Pid,
+ IN UINT64 Offset,
+ IN PCH_SBI_OPCODE Opcode,
+ IN BOOLEAN Posted,
+ IN UINT16 Fbe,
+ IN UINT16 Bar,
+ IN UINT16 Fid,
+ IN OUT UINT32 *Data32,
+ OUT UINT8 *Response
+ )
+{
+ return P2SbSbiExecutionEx (
+ P2sbPciCfgBase (),
+ Pid,
+ Offset,
+ Opcode,
+ Posted,
+ Fbe,
+ Bar,
+ Fid,
+ Data32,
+ Response
+ );
+}
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/LibraryPrivate/PeiDxeSmmPchSbiAccessLib/PeiDxeSmmPchSbiAccessLib.inf b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/LibraryPrivate/PeiDxeSmmPchSbiAccessLib/PeiDxeSmmPchSbiAccessLib.inf
new file mode 100644
index 0000000000..a28a90c74b
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/LibraryPrivate/PeiD
+++ xeSmmPchSbiAccessLib/PeiDxeSmmPchSbiAccessLib.inf
@@ -0,0 +1,35 @@
+## @file
+# PCH SBI access library.
+#
+# All function in this library is available for PEI, DXE, and SMM, #
+But do not support UEFI RUNTIME environment call.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+
+[Defines]
+INF_VERSION = 0x00010017
+BASE_NAME = PeiDxeSmmPchSbiAccessLib
+FILE_GUID = 96ECB0FB-A975-4DC8-B88A-D90C3378CE87
+VERSION_STRING = 1.0
+MODULE_TYPE = BASE
+LIBRARY_CLASS = PchSbiAccessLib
+
+
+[LibraryClasses]
+BaseLib
+IoLib
+DebugLib
+PchPciBdfLib
+P2SbSidebandAccessLib
+
+
+[Packages]
+MdePkg/MdePkg.dec
+AlderlakeSiliconPkg/SiPkg.dec
+
+
+[Sources]
+PchSbiAccessLib.c
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PchDmi/IncludePrivate/Library/PchDmiLib.h b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PchDmi/IncludePrivate/Library/PchDmiLib.h
new file mode 100644
index 0000000000..efbb76f6be
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PchDmi/IncludePrivate/Li
+++ brary/PchDmiLib.h
@@ -0,0 +1,60 @@
+/** @file
+ Header file for PchDmiLib.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/ #ifndef
+_PCH_DMI_LIB_H_ #define _PCH_DMI_LIB_H_
+
+/**
+ This function checks if DMI Secured Register Lock (SRL) is set
+
+ @retval SRL state
+**/
+BOOLEAN
+IsPchDmiLocked (
+ VOID
+ );
+
+/**
+ Get PCH TCO base address.
+
+ @retval Address Address of TCO base address.
+**/
+UINT16
+PchDmiGetTcoBase (
+ VOID
+ );
+
+/**
+ Set PCH LPC/eSPI IO decode ranges in DMI
+ Please check EDS for detail of LPC/eSPI IO decode ranges bit definition.
+ Bit 12: FDD range
+ Bit 9:8: LPT range
+ Bit 6:4: ComB range
+ Bit 2:0: ComA range
+
+ @param[in] LpcIoDecodeRanges LPC/eSPI IO decode ranges bit settings.
+
+ @retval EFI_SUCCESS Successfully completed.
+ @retval EFI_UNSUPPORTED DMIC.SRL is set.
+**/
+EFI_STATUS
+PchDmiSetLpcIoDecodeRanges (
+ IN UINT16 LpcIoDecodeRanges
+ );
+
+/**
+ Set PCH LPC/eSPI IO enable decoding in DMI
+
+ @param[in] LpcIoEnableDecoding LPC/eSPI IO enable decoding bit settings.
+
+ @retval EFI_SUCCESS Successfully completed.
+ @retval EFI_UNSUPPORTED DMIC.SRL is set.
+**/
+EFI_STATUS
+PchDmiSetLpcIoEnable (
+ IN UINT16 LpcIoEnableDecoding
+ );
+#endif // _PCH_DMI_LIB_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivate/PeiDxeSmmPchDmiLib/PchDmi14.c b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivate/PeiDxeSmmPchDmiLib/PchDmi14.c
new file mode 100644
index 0000000000..9f49790372
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivate/Pe
+++ iDxeSmmPchDmiLib/PchDmi14.c
@@ -0,0 +1,34 @@
+/** @file
+ This file contains functions for PCH DMI SIP14
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/
+
+#include <Base.h>
+#include <Uefi/UefiBaseType.h>
+#include <Library/IoLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseLib.h>
+#include <Library/PchInfoLib.h>
+#include <Library/PchPcrLib.h>
+#include <Library/PchDmiLib.h>
+#include <Library/PchCycleDecodingLib.h> #include <Library/PchPcrLib.h>
+#include <Library/PchInfoLib.h> #include <Register/PchDmiRegs.h>
+#include <Register/PchDmi14Regs.h> #include <Register/PchPcrRegs.h>
+
+/**
+ This function checks if DMI SIP14 Secured Register Lock (SRL) is set
+
+ @retval SRL state
+**/
+BOOLEAN
+IsPchDmi14Locked (
+ VOID
+ )
+{
+ return ((PchPcrRead32 (PID_DMI, R_PCH_DMI14_PCR_DMIC) &
+B_PCH_DMI14_PCR_DMIC_SRL) != 0); }
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivate/PeiDxeSmmPchDmiLib/PchDmi14.h b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivate/PeiDxeSmmPchDmiLib/PchDmi14.h
new file mode 100644
index 0000000000..494caebb4a
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivate/Pe
+++ iDxeSmmPchDmiLib/PchDmi14.h
@@ -0,0 +1,22 @@
+/** @file
+ Internal header file for PCH DMI library for SIP14
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/ #ifndef
+__PCH_DMI_14_H__ #define __PCH_DMI_14_H__
+
+#include <Library/PchDmiLib.h>
+
+/**
+ This function checks if DMI SIP14 Secured Register Lock (SRL) is set
+
+ @retval SRL state
+**/
+BOOLEAN
+IsPchDmi14Locked (
+ VOID
+ );
+
+#endif
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivate/PeiDxeSmmPchDmiLib/PchDmiLib.c b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivate/PeiDxeSmmPchDmiLib/PchDmiLib.c
new file mode 100644
index 0000000000..3d5436f1a3
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivate/Pe
+++ iDxeSmmPchDmiLib/PchDmiLib.c
@@ -0,0 +1,110 @@
+/** @file
+ PCH DMI library.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/ #include <Base.h>
+#include <Uefi/UefiBaseType.h> #include <Library/IoLib.h> #include
+<Library/DebugLib.h> #include <Library/BaseLib.h> #include
+<Library/PchInfoLib.h> #include <Library/PchPcrLib.h> #include
+<Library/PchDmiLib.h> #include <Library/PchCycleDecodingLib.h> #include
+<Register/PchPcrRegs.h> #include <Register/PchDmiRegs.h> #include
+<Register/PchRegsLpc.h>
+
+#include "PchDmi14.h"
+
+/**
+ This function checks if DMI Secured Register Lock (SRL) is set
+
+ @retval SRL state
+**/
+BOOLEAN
+IsPchDmiLocked (
+ VOID
+ )
+{
+ return IsPchDmi14Locked ();
+}
+
+/**
+ Get PCH TCO base address.
+
+ @retval Address Address of TCO base address.
+**/
+UINT16
+PchDmiGetTcoBase (
+ VOID
+ )
+{
+ //
+ // Read "TCO Base Address" PCR[DMI] + 2778h[15:5]
+ //
+ return (PchPcrRead16 (PID_DMI, R_PCH_DMI_PCR_TCOBASE) &
+B_PCH_DMI_PCR_TCOBASE_TCOBA); }
+
+/**
+ Set PCH LPC/eSPI IO decode ranges in DMI
+ Please check EDS for detail of LPC/eSPI IO decode ranges bit definition.
+ Bit 12: FDD range
+ Bit 9:8: LPT range
+ Bit 6:4: ComB range
+ Bit 2:0: ComA range
+
+ @param[in] LpcIoDecodeRanges LPC/eSPI IO decode ranges bit settings.
+
+ @retval EFI_SUCCESS Successfully completed.
+ @retval EFI_UNSUPPORTED DMIC.SRL is set.
+**/
+EFI_STATUS
+PchDmiSetLpcIoDecodeRanges (
+ IN UINT16 LpcIoDecodeRanges
+ )
+{
+ //
+ // This cycle decoding is only allowed to set when DMI is not locked.
+ //
+ if (IsPchDmiLocked ()) {
+ ASSERT (FALSE);
+ return EFI_UNSUPPORTED;
+ }
+
+ //
+ // program LPC I/O Decode Ranges, PCR[DMI] + 2770h[15:0] to the same value programmed in LPC/eSPI PCI offset 80h.
+ //
+ PchPcrWrite16 (PID_DMI, R_PCH_DMI_PCR_LPCIOD, LpcIoDecodeRanges);
+ return EFI_SUCCESS;
+}
+
+/**
+ Set PCH LPC/eSPI IO enable decoding in DMI
+
+ @param[in] LpcIoEnableDecoding LPC/eSPI IO enable decoding bit settings.
+
+ @retval EFI_SUCCESS Successfully completed.
+ @retval EFI_UNSUPPORTED DMIC.SRL is set.
+**/
+EFI_STATUS
+PchDmiSetLpcIoEnable (
+ IN UINT16 LpcIoEnableDecoding
+ )
+{
+ //
+ // This cycle decoding is only allowed to set when DMI is not locked.
+ //
+ if (IsPchDmiLocked ()) {
+ ASSERT (FALSE);
+ return EFI_UNSUPPORTED;
+ }
+
+ //
+ // program LPC I/O Decode Ranges, PCR[DMI] + 2774h[15:0] to the same value programmed in LPC/eSPI PCI offset 82h.
+ //
+ PchPcrWrite16 (PID_DMI, R_PCH_DMI_PCR_LPCIOE, LpcIoEnableDecoding);
+ return EFI_SUCCESS;
+}
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivate/PeiDxeSmmPchDmiLib/PeiDxeSmmPchDmiLib.inf b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivate/PeiDxeSmmPchDmiLib/PeiDxeSmmPchDmiLib.inf
new file mode 100644
index 0000000000..4e92117be3
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivate/Pe
+++ iDxeSmmPchDmiLib/PeiDxeSmmPchDmiLib.inf
@@ -0,0 +1,43 @@
+## @file
+# Component description file for the PeiDxeSmmPchDmiLib #
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+[Defines]
+INF_VERSION = 0x00010017
+BASE_NAME = PeiDxeSmmPchDmiLib
+FILE_GUID = 067DC1C4-2668-4F06-9921-307514B66B34
+VERSION_STRING = 1.0
+MODULE_TYPE = BASE
+LIBRARY_CLASS = PchDmiLib
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = IA32 X64
+#
+
+[LibraryClasses]
+ BaseLib
+ IoLib
+ DebugLib
+ PchInfoLib
+ PchPcrLib
+
+
+[Packages]
+ MdePkg/MdePkg.dec
+ AlderlakeSiliconPkg/SiPkg.dec
+
+
+[Sources]
+ PchDmiLib.c
+ PchDmi14.c
+ PchDmi14.h
+
+[Guids]
+ gPchDmiConfigGuid ## CONSUMES
+ gPchDmiPreMemConfigGuid ## CONSUMES
+
+[Pcd]
--
2.36.1.windows.1
-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#108689): https://edk2.groups.io/g/devel/message/108689
Mute This Topic: https://groups.io/mt/101373946/7686176
Group Owner: devel+owner@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [rebecca@openfw.io]
-=-=-=-=-=-=-=-=-=-=-=-
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [edk2-devel] [PATCH v2 04/10] AlderlakeSiliconPkg/IpBlock: Add Pmc, Spi components
2023-09-15 4:45 ` [edk2-devel] [PATCH v2 04/10] AlderlakeSiliconPkg/IpBlock: Add Pmc, Spi components Saloni Kasbekar
@ 2023-09-15 5:42 ` Chaganty, Rangasai V
2023-09-15 13:28 ` Chuang, Rosen
2023-09-15 23:56 ` Nate DeSimone
1 sibling, 1 reply; 41+ messages in thread
From: Chaganty, Rangasai V @ 2023-09-15 5:42 UTC (permalink / raw)
To: Kasbekar, Saloni, devel@edk2.groups.io
Cc: Desimone, Nathaniel L, Chuang, Rosen
Reviewed-by: Sai Chaganty <rangasai.v.chaganty@intel.com>
-----Original Message-----
From: Kasbekar, Saloni <saloni.kasbekar@intel.com>
Sent: Thursday, September 14, 2023 9:46 PM
To: devel@edk2.groups.io
Cc: Kasbekar, Saloni <saloni.kasbekar@intel.com>; Chaganty, Rangasai V <rangasai.v.chaganty@intel.com>; Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>; Chuang, Rosen <rosen.chuang@intel.com>
Subject: [PATCH v2 04/10] AlderlakeSiliconPkg/IpBlock: Add Pmc, Spi components
Adds the following modules:
- IpBlock/Pmc/IncludePrivate
- IpBlock/Pmc/Library
- IpBlock/Pmc/LibraryPrivate
- IpBlock/Spi/IncludePrivate
- IpBlock/Spi/Library
- IpBlock/Spi/LibraryPrivate
- IpBlock/Spi/Smm
Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Rosen Chuang <rosen.chuang@intel.com>
Signed-off-by: Saloni Kasbekar <saloni.kasbekar@intel.com>
---
.../IncludePrivate/Library/PmcPrivateLib.h | 47 +
.../IpBlock/Pmc/IncludePrivate/PmcSocConfig.h | 67 +
.../PeiDxeSmmPmcLib/PeiDxeSmmPmcLib.inf | 38 +
.../Pmc/Library/PeiDxeSmmPmcLib/PmcLib.c | 50 +
.../PeiDxeSmmPmcPrivateLib.inf | 43 +
.../PeiDxeSmmPmcPrivateLib/PmcPrivateLib.c | 86 ++
.../Spi/IncludePrivate/Library/SpiCommonLib.h | 376 ++++++
.../Spi/IncludePrivate/Register/SpiRegs.h | 116 ++
.../IpBlock/Spi/Library/PeiSpiLib/PchSpi.c | 209 +++
.../Spi/Library/PeiSpiLib/PeiSpiLib.inf | 41 +
.../BaseSpiCommonLib/BaseSpiCommonLib.inf | 29 +
.../BaseSpiCommonLib/SpiCommon.c | 1127 +++++++++++++++++
.../AlderlakeSiliconPkg/IpBlock/Spi/Smm/Spi.c | 387 ++++++
.../IpBlock/Spi/Smm/SpiSmm.inf | 46 +
14 files changed, 2662 insertions(+)
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Pmc/IncludePrivate/Library/PmcPrivateLib.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Pmc/IncludePrivate/PmcSocConfig.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Pmc/Library/PeiDxeSmmPmcLib/PeiDxeSmmPmcLib.inf
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Pmc/Library/PeiDxeSmmPmcLib/PmcLib.c
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Pmc/LibraryPrivate/PeiDxeSmmPmcPrivateLib/PeiDxeSmmPmcPrivateLib.inf
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Pmc/LibraryPrivate/PeiDxeSmmPmcPrivateLib/PmcPrivateLib.c
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/IncludePrivate/Library/SpiCommonLib.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/IncludePrivate/Register/SpiRegs.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/Library/PeiSpiLib/PchSpi.c
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/Library/PeiSpiLib/PeiSpiLib.inf
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/LibraryPrivate/BaseSpiCommonLib/BaseSpiCommonLib.inf
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/LibraryPrivate/BaseSpiCommonLib/SpiCommon.c
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/Smm/Spi.c
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/Smm/SpiSmm.inf
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Pmc/IncludePrivate/Library/PmcPrivateLib.h b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Pmc/IncludePrivate/Library/PmcPrivateLib.h
new file mode 100644
index 0000000000..6ec244b127
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Pmc/IncludePrivate/Library/PmcPrivateLib.h
@@ -0,0 +1,47 @@
+/** @file
+ Header file for private PmcLib.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _PMC_PRIVATE_LIB_H_
+#define _PMC_PRIVATE_LIB_H_
+
+#include <Library/PmcLib.h>
+#include "Register/PmcRegs.h"
+
+typedef enum {
+ PmcSwSmiRate1p5ms = 0,
+ PmcSwSmiRate16ms,
+ PmcSwSmiRate32ms,
+ PmcSwSmiRate64ms
+} PMC_SWSMI_RATE;
+
+/**
+ This function sets SW SMI Rate.
+
+ @param[in] SwSmiRate Refer to PMC_SWSMI_RATE for possible values
+**/
+VOID
+PmcSetSwSmiRate (
+ IN PMC_SWSMI_RATE SwSmiRate
+ );
+
+typedef enum {
+ PmcPeriodicSmiRate8s = 0,
+ PmcPeriodicSmiRate16s,
+ PmcPeriodicSmiRate32s,
+ PmcPeriodicSmiRate64s
+} PMC_PERIODIC_SMI_RATE;
+
+/**
+ This function sets Periodic SMI Rate.
+
+ @param[in] PeriodicSmiRate Refer to PMC_PERIODIC_SMI_RATE for possible values
+**/
+VOID
+PmcSetPeriodicSmiRate (
+ IN PMC_PERIODIC_SMI_RATE PeriodicSmiRate
+ );
+
+#endif // _PMC_PRIVATE_LIB_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Pmc/IncludePrivate/PmcSocConfig.h b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Pmc/IncludePrivate/PmcSocConfig.h
new file mode 100644
index 0000000000..523a84a180
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Pmc/IncludePrivate/PmcSocConfig.h
@@ -0,0 +1,67 @@
+/** @file
+ PMC SoC configuration
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PMC_SOC_CONFIGURATION_H_
+#define _PMC_SOC_CONFIGURATION_H_
+
+typedef enum {
+ AdrSinglePhase = 0,
+ AdrDualPhase
+} ADR_PHASE_TYPE;
+
+typedef enum {
+ AdrGpioB = 0,
+ AdrGpioC
+} ADR_GPIO;
+
+typedef enum {
+ AdrOverPmSync = 0,
+ AdrOverDmi
+} ADR_MSG_INTERFACE;
+
+typedef struct {
+ BOOLEAN Supported;
+ ADR_PHASE_TYPE AdrPhaseType;
+ ADR_GPIO AdrGpio;
+ ADR_MSG_INTERFACE AdrMsgInterface;
+ //
+ // On some designs ADR_GEN_CFG has been moved in the HW.
+ // Set this to if ADR_GEN_CFG is located at 0x1908
+ //
+ BOOLEAN AdrGenCfgMoved;
+} PMC_ADR_SOC_CONFIG;
+
+typedef struct {
+ BOOLEAN CppmCgInterfaceVersion;
+ BOOLEAN LpmSupported;
+ UINT8 LpmInterfaceVersion;
+ BOOLEAN OsIdleSupported;
+ BOOLEAN TimedGpioSupported;
+ UINT32 CpuIovrRampTime;
+ BOOLEAN PsOnSupported;
+ BOOLEAN ModPhySusPgSupported;
+ UINT8 SciIrq;
+ BOOLEAN FabricPowerGatingCppmQualificationEnable;
+ BOOLEAN EspiBoot;
+ BOOLEAN UsbDbcConnected;
+ UINT32 Usb3LanesConnectedBitmask;
+ BOOLEAN DisableIosfSbClockGating;
+ BOOLEAN SkipModPhyGatingPolicy;
+ PMC_ADR_SOC_CONFIG AdrSocConfig;
+ BOOLEAN AllSbrIdleQualifierEnable;
+ UINT32 LpmPriVal; ///< Low Power Mode Priority
+
+} PMC_SOC_CONFIG;
+
+typedef struct {
+ BOOLEAN OverrideFetRampTime;
+ UINT8 FetRampTime;
+ UINT8 IsFetRampTime;
+ UINT16 FuseDownloadDelayUs;
+} PMC_FIVR_SOC_CONFIG;
+
+#endif
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Pmc/Library/PeiDxeSmmPmcLib/PeiDxeSmmPmcLib.inf b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Pmc/Library/PeiDxeSmmPmcLib/PeiDxeSmmPmcLib.inf
new file mode 100644
index 0000000000..e9784ceb9c
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Pmc/Library/PeiDxeSmmPmcLib/PeiDxeSmmPmcLib.inf
@@ -0,0 +1,38 @@
+## @file
+# PEI/DXE/SMM PCH PMC Lib.
+#
+# All function in this library is available for PEI, DXE, and SMM,
+# But do not support UEFI RUNTIME environment call.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+[Defines]
+ INF_VERSION = 0x00010017
+ BASE_NAME = PeiDxeSmmPmcLib
+ FILE_GUID = 9D60C364-5086-41E3-BC9D-C62AB7233DBF
+ VERSION_STRING = 1.0
+ MODULE_TYPE = BASE
+ LIBRARY_CLASS = PmcLib
+
+[LibraryClasses]
+ BaseLib
+ IoLib
+ DebugLib
+ PciSegmentLib
+ PchCycleDecodingLib
+ PchPcrLib
+ PchInfoLib
+ PmcPrivateLib
+ BaseMemoryLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ AlderlakeSiliconPkg/SiPkg.dec
+
+[Pcd]
+ gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress
+
+[Sources]
+ PmcLib.c
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Pmc/Library/PeiDxeSmmPmcLib/PmcLib.c b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Pmc/Library/PeiDxeSmmPmcLib/PmcLib.c
new file mode 100644
index 0000000000..91e741a294
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Pmc/Library/PeiDxeSmmPmcLib/PmcLib.c
@@ -0,0 +1,50 @@
+/** @file
+ PCH PMC Library.
+ All function in this library is available for PEI, DXE, and SMM,
+ But do not support UEFI RUNTIME environment call.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <Base.h>
+#include <Uefi/UefiBaseType.h>
+#include <Library/IoLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/PciSegmentLib.h>
+#include <Library/PchCycleDecodingLib.h>
+#include <Library/PmcLib.h>
+#include <Library/PchPcrLib.h>
+#include <Library/PchInfoLib.h>
+#include <Library/PmcPrivateLib.h>
+#include <PchReservedResources.h>
+#include <Register/PmcRegs.h>
+#include <Register/PchRegs.h>
+
+/**
+ Get PCH ACPI base address.
+
+ @retval Address Address of PWRM base address.
+**/
+UINT16
+PmcGetAcpiBase (
+ VOID
+ )
+{
+ return PcdGet16 (PcdAcpiBaseAddress);
+}
+
+/**
+ Get PCH PWRM base address.
+
+ @retval Address Address of PWRM base address.
+**/
+UINT32
+PmcGetPwrmBase (
+ VOID
+ )
+{
+ return PCH_PWRM_BASE_ADDRESS;
+}
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Pmc/LibraryPrivate/PeiDxeSmmPmcPrivateLib/PeiDxeSmmPmcPrivateLib.inf b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Pmc/LibraryPrivate/PeiDxeSmmPmcPrivateLib/PeiDxeSmmPmcPrivateLib.inf
new file mode 100644
index 0000000000..e6693f767d
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Pmc/LibraryPrivate/PeiDxeSmmPmcPrivateLib/PeiDxeSmmPmcPrivateLib.inf
@@ -0,0 +1,43 @@
+## @file
+# PEI/DXE/SMM PCH PMC Private Lib.
+#
+# All function in this library is available for PEI, DXE, and SMM,
+# But do not support UEFI RUNTIME environment call.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+
+[Defines]
+INF_VERSION = 0x00010017
+BASE_NAME = PeiDxeSmmPmcPrivateLib
+FILE_GUID = EB69B12B-6D4C-4B12-BB31-66CBCC4C1DC7
+VERSION_STRING = 1.0
+MODULE_TYPE = BASE
+LIBRARY_CLASS = PmcPrivateLib
+
+
+[LibraryClasses]
+BaseLib
+IoLib
+DebugLib
+TimerLib
+PciSegmentLib
+PmcLib
+BaseMemoryLib
+PchPciBdfLib
+
+[Packages]
+MdePkg/MdePkg.dec
+AlderlakeSiliconPkg/SiPkg.dec
+
+
+[Pcd]
+gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress
+
+[FixedPcd]
+
+[Sources]
+PmcPrivateLib.c
+
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Pmc/LibraryPrivate/PeiDxeSmmPmcPrivateLib/PmcPrivateLib.c b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Pmc/LibraryPrivate/PeiDxeSmmPmcPrivateLib/PmcPrivateLib.c
new file mode 100644
index 0000000000..b720305d15
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Pmc/LibraryPrivate/PeiDxeSmmPmcPrivateLib/PmcPrivateLib.c
@@ -0,0 +1,86 @@
+/** @file
+ PCH private PMC Library for all PCH generations.
+ All function in this library is available for PEI, DXE, and SMM,
+ But do not support UEFI RUNTIME environment call.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <Base.h>
+#include <Uefi/UefiBaseType.h>
+#include <Library/IoLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/PmcLib.h>
+#include <Library/PciSegmentLib.h>
+#include <Library/TimerLib.h>
+#include <Library/PmcPrivateLib.h>
+#include <PchReservedResources.h>
+#include <Register/PchRegs.h>
+#include <Register/PmcRegs.h>
+#include <IndustryStandard/Pci30.h>
+#include <Library/PchPciBdfLib.h>
+
+
+/**
+ This function sets SW SMI Rate.
+
+ @param[in] SwSmiRate Refer to PMC_SWSMI_RATE for possible values
+**/
+VOID
+PmcSetSwSmiRate (
+ IN PMC_SWSMI_RATE SwSmiRate
+ )
+{
+ UINT32 PchPwrmBase;
+ STATIC UINT8 SwSmiRateRegVal[4] = {
+ V_PMC_PWRM_GEN_PMCON_A_SWSMI_RTSL_1_5MS,
+ V_PMC_PWRM_GEN_PMCON_A_SWSMI_RTSL_16MS,
+ V_PMC_PWRM_GEN_PMCON_A_SWSMI_RTSL_32MS,
+ V_PMC_PWRM_GEN_PMCON_A_SWSMI_RTSL_64MS
+ };
+
+ ASSERT (SwSmiRate <= PmcSwSmiRate64ms);
+
+ PchPwrmBase = PmcGetPwrmBase ();
+
+ //
+ // SWSMI_RATE_SEL BIT (PWRMBASE offset 1020h[7:6]) bits are in RTC well
+ //
+ MmioAndThenOr8 (
+ PchPwrmBase + R_PMC_PWRM_GEN_PMCON_A,
+ (UINT8)~B_PMC_PWRM_GEN_PMCON_A_SWSMI_RTSL,
+ SwSmiRateRegVal[SwSmiRate]
+ );
+}
+
+/**
+ This function sets Periodic SMI Rate.
+
+ @param[in] PeriodicSmiRate Refer to PMC_PERIODIC_SMI_RATE for possible values
+**/
+VOID
+PmcSetPeriodicSmiRate (
+ IN PMC_PERIODIC_SMI_RATE PeriodicSmiRate
+ )
+{
+ UINT32 PchPwrmBase;
+ STATIC UINT8 PeriodicSmiRateRegVal[4] = {
+ V_PMC_PWRM_GEN_PMCON_A_PER_SMI_8S,
+ V_PMC_PWRM_GEN_PMCON_A_PER_SMI_16S,
+ V_PMC_PWRM_GEN_PMCON_A_PER_SMI_32S,
+ V_PMC_PWRM_GEN_PMCON_A_PER_SMI_64S
+ };
+
+ ASSERT (PeriodicSmiRate <= PmcPeriodicSmiRate64s);
+
+ PchPwrmBase = PmcGetPwrmBase ();
+
+ MmioAndThenOr8 (
+ PchPwrmBase + R_PMC_PWRM_GEN_PMCON_A,
+ (UINT8)~B_PMC_PWRM_GEN_PMCON_A_PER_SMI_SEL,
+ PeriodicSmiRateRegVal[PeriodicSmiRate]
+ );
+}
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/IncludePrivate/Library/SpiCommonLib.h b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/IncludePrivate/Library/SpiCommonLib.h
new file mode 100644
index 0000000000..e13718c9e9
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/IncludePrivate/Library/SpiCommonLib.h
@@ -0,0 +1,376 @@
+/** @file
+ Header file for the PCH SPI Common Driver.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _SPI_COMMON_LIB_H_
+#define _SPI_COMMON_LIB_H_
+
+#include <Protocol/Spi.h>
+
+//
+// Maximum time allowed while waiting the SPI cycle to complete
+// Wait Time = 6 seconds = 6000000 microseconds
+// Wait Period = 10 microseconds
+//
+#define SPI_WAIT_TIME 6000000 ///< Wait Time = 6 seconds = 6000000 microseconds
+
+#define SPI_WAIT_PERIOD 10 ///< Wait Period = 10 microseconds
+
+///
+/// Flash cycle Type
+///
+typedef enum {
+ FlashCycleRead,
+ FlashCycleWrite,
+ FlashCycleErase,
+ FlashCycleReadSfdp,
+ FlashCycleReadJedecId,
+ FlashCycleWriteStatus,
+ FlashCycleReadStatus,
+ FlashCycleMax
+} FLASH_CYCLE_TYPE;
+
+///
+/// Flash Component Number
+///
+typedef enum {
+ FlashComponent0,
+ FlashComponent1,
+ FlashComponentMax
+} FLASH_COMPONENT_NUM;
+
+///
+/// Private data structure definitions for the driver
+///
+#define PCH_SPI_PRIVATE_DATA_SIGNATURE SIGNATURE_32 ('P', 'S', 'P', 'I')
+
+typedef struct {
+ UINT32 Signature;
+ EFI_HANDLE Handle;
+ PCH_SPI_PROTOCOL SpiProtocol;
+ UINT16 PchAcpiBase;
+ UINT64 PchSpiBase;
+ UINT8 ReadPermission;
+ UINT8 WritePermission;
+ UINT32 SfdpVscc0Value;
+ UINT32 SfdpVscc1Value;
+ UINT16 PchStrapBaseAddr;
+ UINT16 PchStrapSize;
+ UINT16 CpuStrapBaseAddr;
+ UINT16 CpuStrapSize;
+ UINT8 NumberOfComponents;
+ UINT32 Component1StartAddr;
+ UINT32 TotalFlashSize;
+} SPI_INSTANCE;
+
+#define SPI_INSTANCE_FROM_SPIPROTOCOL(a) CR (a, SPI_INSTANCE, SpiProtocol, PCH_SPI_PRIVATE_DATA_SIGNATURE)
+
+//
+// Function prototypes used by the SPI protocol.
+//
+
+/**
+ Initialize an SPI protocol instance.
+
+ @param[in] SpiInstance Pointer to SpiInstance to initialize
+
+ @retval EFI_SUCCESS The protocol instance was properly initialized
+ @exception EFI_UNSUPPORTED The PCH is not supported by this module
+**/
+EFI_STATUS
+SpiProtocolConstructor (
+ IN SPI_INSTANCE *SpiInstance
+ );
+
+/**
+ This function is a hook for Spi to disable BIOS Write Protect
+
+ @retval EFI_SUCCESS The protocol instance was properly initialized
+ @retval EFI_ACCESS_DENIED The BIOS Region can only be updated in SMM phase
+
+**/
+EFI_STATUS
+EFIAPI
+DisableBiosWriteProtect (
+ VOID
+ );
+
+/**
+ This function is a hook for Spi to enable BIOS Write Protect
+
+
+**/
+VOID
+EFIAPI
+EnableBiosWriteProtect (
+ VOID
+ );
+
+/**
+ Acquire pch spi mmio address.
+
+ @param[in] SpiInstance Pointer to SpiInstance to initialize
+
+ @retval PchSpiBar0 return SPI MMIO address
+**/
+UINTN
+AcquireSpiBar0 (
+ IN SPI_INSTANCE *SpiInstance
+ );
+
+/**
+ Release pch spi mmio address.
+
+ @param[in] SpiInstance Pointer to SpiInstance to initialize
+
+ @retval None
+**/
+VOID
+ReleaseSpiBar0 (
+ IN SPI_INSTANCE *SpiInstance
+ );
+
+/**
+ Check if it's granted to do flash write.
+
+ @retval TRUE It's secure to do flash write.
+ @retval FALSE It's not secure to do flash write.
+**/
+BOOLEAN
+IsSpiFlashWriteGranted (
+ VOID
+ );
+
+/**
+ Check if a save and restore of the SPI controller state is necessary
+
+ @retval TRUE It's necessary to save and restore SPI controller state
+ @retval FALSE It's not necessary to save and restore SPI controller state
+**/
+BOOLEAN
+IsSpiControllerSaveRestoreEnabled (
+ VOID
+ );
+
+/**
+ Read data from the flash part.
+
+ @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
+ @param[in] FlashRegionType The Flash Region type for flash cycle which is listed in the Descriptor.
+ @param[in] Address The Flash Linear Address must fall within a region for which BIOS has access permissions.
+ @param[in] ByteCount Number of bytes in the data portion of the SPI cycle.
+ @param[out] Buffer The Pointer to caller-allocated buffer containing the dada received.
+ It is the caller's responsibility to make sure Buffer is large enough for the total number of bytes read.
+
+ @retval EFI_SUCCESS Command succeed.
+ @retval EFI_INVALID_PARAMETER The parameters specified are not valid.
+ @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
+**/
+EFI_STATUS
+EFIAPI
+SpiProtocolFlashRead (
+ IN PCH_SPI_PROTOCOL *This,
+ IN FLASH_REGION_TYPE FlashRegionType,
+ IN UINT32 Address,
+ IN UINT32 ByteCount,
+ OUT UINT8 *Buffer
+ );
+
+/**
+ Write data to the flash part.
+
+ @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
+ @param[in] FlashRegionType The Flash Region type for flash cycle which is listed in the Descriptor.
+ @param[in] Address The Flash Linear Address must fall within a region for which BIOS has access permissions.
+ @param[in] ByteCount Number of bytes in the data portion of the SPI cycle.
+ @param[in] Buffer Pointer to caller-allocated buffer containing the data sent during the SPI cycle.
+
+ @retval EFI_SUCCESS Command succeed.
+ @retval EFI_INVALID_PARAMETER The parameters specified are not valid.
+ @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
+**/
+EFI_STATUS
+EFIAPI
+SpiProtocolFlashWrite (
+ IN PCH_SPI_PROTOCOL *This,
+ IN FLASH_REGION_TYPE FlashRegionType,
+ IN UINT32 Address,
+ IN UINT32 ByteCount,
+ IN UINT8 *Buffer
+ );
+
+/**
+ Erase some area on the flash part.
+
+ @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
+ @param[in] FlashRegionType The Flash Region type for flash cycle which is listed in the Descriptor.
+ @param[in] Address The Flash Linear Address must fall within a region for which BIOS has access permissions.
+ @param[in] ByteCount Number of bytes in the data portion of the SPI cycle.
+
+ @retval EFI_SUCCESS Command succeed.
+ @retval EFI_INVALID_PARAMETER The parameters specified are not valid.
+ @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
+**/
+EFI_STATUS
+EFIAPI
+SpiProtocolFlashErase (
+ IN PCH_SPI_PROTOCOL *This,
+ IN FLASH_REGION_TYPE FlashRegionType,
+ IN UINT32 Address,
+ IN UINT32 ByteCount
+ );
+
+/**
+ Read SFDP data from the flash part.
+
+ @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
+ @param[in] ComponentNumber The Componen Number for chip select
+ @param[in] Address The starting byte address for SFDP data read.
+ @param[in] ByteCount Number of bytes in SFDP data portion of the SPI cycle
+ @param[out] SfdpData The Pointer to caller-allocated buffer containing the SFDP data received
+ It is the caller's responsibility to make sure Buffer is large enough for the total number of bytes read
+
+ @retval EFI_SUCCESS Command succeed.
+ @retval EFI_INVALID_PARAMETER The parameters specified are not valid.
+ @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
+**/
+EFI_STATUS
+EFIAPI
+SpiProtocolFlashReadSfdp (
+ IN PCH_SPI_PROTOCOL *This,
+ IN UINT8 ComponentNumber,
+ IN UINT32 Address,
+ IN UINT32 ByteCount,
+ OUT UINT8 *SfdpData
+ );
+
+/**
+ Read Jedec Id from the flash part.
+
+ @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
+ @param[in] ComponentNumber The Componen Number for chip select
+ @param[in] ByteCount Number of bytes in JedecId data portion of the SPI cycle, the data size is 3 typically
+ @param[out] JedecId The Pointer to caller-allocated buffer containing JEDEC ID received
+ It is the caller's responsibility to make sure Buffer is large enough for the total number of bytes read.
+
+ @retval EFI_SUCCESS Command succeed.
+ @retval EFI_INVALID_PARAMETER The parameters specified are not valid.
+ @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
+**/
+EFI_STATUS
+EFIAPI
+SpiProtocolFlashReadJedecId (
+ IN PCH_SPI_PROTOCOL *This,
+ IN UINT8 ComponentNumber,
+ IN UINT32 ByteCount,
+ OUT UINT8 *JedecId
+ );
+
+/**
+ Write the status register in the flash part.
+
+ @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
+ @param[in] ByteCount Number of bytes in Status data portion of the SPI cycle, the data size is 1 typically
+ @param[in] StatusValue The Pointer to caller-allocated buffer containing the value of Status register writing
+
+ @retval EFI_SUCCESS Command succeed.
+ @retval EFI_INVALID_PARAMETER The parameters specified are not valid.
+ @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
+**/
+EFI_STATUS
+EFIAPI
+SpiProtocolFlashWriteStatus (
+ IN PCH_SPI_PROTOCOL *This,
+ IN UINT32 ByteCount,
+ IN UINT8 *StatusValue
+ );
+
+/**
+ Read status register in the flash part.
+
+ @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
+ @param[in] ByteCount Number of bytes in Status data portion of the SPI cycle, the data size is 1 typically
+ @param[out] StatusValue The Pointer to caller-allocated buffer containing the value of Status register received.
+
+ @retval EFI_SUCCESS Command succeed.
+ @retval EFI_INVALID_PARAMETER The parameters specified are not valid.
+ @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
+**/
+EFI_STATUS
+EFIAPI
+SpiProtocolFlashReadStatus (
+ IN PCH_SPI_PROTOCOL *This,
+ IN UINT32 ByteCount,
+ OUT UINT8 *StatusValue
+ );
+
+/**
+ Get the SPI region base and size, based on the enum type
+
+ @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
+ @param[in] FlashRegionType The Flash Region type for for the base address which is listed in the Descriptor.
+ @param[out] BaseAddress The Flash Linear Address for the Region 'n' Base
+ @param[out] RegionSize The size for the Region 'n'
+
+ @retval EFI_SUCCESS Read success
+ @retval EFI_INVALID_PARAMETER Invalid region type given
+ @retval EFI_DEVICE_ERROR The region is not used
+**/
+EFI_STATUS
+EFIAPI
+SpiProtocolGetRegionAddress (
+ IN PCH_SPI_PROTOCOL *This,
+ IN FLASH_REGION_TYPE FlashRegionType,
+ OUT UINT32 *BaseAddress,
+ OUT UINT32 *RegionSize
+ );
+
+/**
+ Read PCH Soft Strap Values
+
+ @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
+ @param[in] SoftStrapAddr PCH Soft Strap address offset from FPSBA.
+ @param[in] ByteCount Number of bytes in SoftStrap data portion of the SPI cycle
+ @param[out] SoftStrapValue The Pointer to caller-allocated buffer containing PCH Soft Strap Value.
+ If the value of ByteCount is 0, the data type of SoftStrapValue should be UINT16 and SoftStrapValue will be PCH Soft Strap Length
+ It is the caller's responsibility to make sure Buffer is large enough for the total number of bytes read.
+
+ @retval EFI_SUCCESS Command succeed.
+ @retval EFI_INVALID_PARAMETER The parameters specified are not valid.
+ @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
+**/
+EFI_STATUS
+EFIAPI
+SpiProtocolReadPchSoftStrap (
+ IN PCH_SPI_PROTOCOL *This,
+ IN UINT32 SoftStrapAddr,
+ IN UINT32 ByteCount,
+ OUT VOID *SoftStrapValue
+ );
+
+/**
+ Read CPU Soft Strap Values
+
+ @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
+ @param[in] SoftStrapAddr CPU Soft Strap address offset from FCPUSBA.
+ @param[in] ByteCount Number of bytes in SoftStrap data portion of the SPI cycle.
+ @param[out] SoftStrapValue The Pointer to caller-allocated buffer containing CPU Soft Strap Value.
+ If the value of ByteCount is 0, the data type of SoftStrapValue should be UINT16 and SoftStrapValue will be PCH Soft Strap Length
+ It is the caller's responsibility to make sure Buffer is large enough for the total number of bytes read.
+
+ @retval EFI_SUCCESS Command succeed.
+ @retval EFI_INVALID_PARAMETER The parameters specified are not valid.
+ @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
+**/
+EFI_STATUS
+EFIAPI
+SpiProtocolReadCpuSoftStrap (
+ IN PCH_SPI_PROTOCOL *This,
+ IN UINT32 SoftStrapAddr,
+ IN UINT32 ByteCount,
+ OUT VOID *SoftStrapValue
+ );
+
+#endif
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/IncludePrivate/Register/SpiRegs.h b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/IncludePrivate/Register/SpiRegs.h
new file mode 100644
index 0000000000..5cb4791142
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/IncludePrivate/Register/SpiRegs.h
@@ -0,0 +1,116 @@
+/** @file
+ Register names for PCH SPI device.
+
+ Conventions:
+
+ - Register definition format:
+ Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_RegisterName
+ - Prefix:
+ Definitions beginning with "R_" are registers
+ Definitions beginning with "B_" are bits within registers
+ Definitions beginning with "V_" are meaningful values within the bits
+ Definitions beginning with "S_" are register size
+ Definitions beginning with "N_" are the bit position
+ - [GenerationName]:
+ Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc.).
+ Register name without GenerationName applies to all generations.
+ - [ComponentName]:
+ This field indicates the component name that the register belongs to (e.g. PCH, SA etc.)
+ Register name without ComponentName applies to all components.
+ Register that is specific to -H denoted by "_PCH_H_" in component name.
+ Register that is specific to -LP denoted by "_PCH_LP_" in component name.
+ - SubsystemName:
+ This field indicates the subsystem name of the component that the register belongs to
+ (e.g. PCIE, USB, SATA, GPIO, PMC etc.).
+ - RegisterSpace:
+ MEM - MMIO space register of subsystem.
+ IO - IO space register of subsystem.
+ PCR - Private configuration register of subsystem.
+ CFG - PCI configuration space register of subsystem.
+ - RegisterName:
+ Full register name.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _SPI_REGS_H_
+#define _SPI_REGS_H_
+
+//
+// SPI Registers
+//
+#define R_SPI_CFG_BAR0 0x10
+#define B_SPI_CFG_BAR0_MASK 0x0FFF
+
+
+#define R_SPI_CFG_BC 0xDC
+#define S_SPI_CFG_BC 4
+#define N_SPI_CFG_BC_ASE_BWP 11
+#define B_SPI_CFG_BC_ASE_BWP BIT11
+#define N_SPI_CFG_BC_ASYNC_SS 10
+#define B_SPI_CFG_BC_ASYNC_SS BIT10
+#define N_SPI_CFG_BC_SYNC_SS 8
+#define B_SPI_CFG_BC_SYNC_SS BIT8
+#define B_SPI_CFG_BC_BILD BIT7
+#define B_SPI_CFG_BC_EISS BIT5 ///< Enable InSMM.STS
+#define B_SPI_CFG_BC_SRC (BIT3 | BIT2)
+#define N_SPI_CFG_BC_SRC 2
+#define V_SPI_CFG_BC_SRC_PREF_DIS_CACHE_DIS 0x01 ///< No prefetching and no caching
+#define N_SPI_CFG_BC_BLE 1
+#define B_SPI_CFG_BC_WPD BIT0 ///< Write Protect Disable
+
+//
+// BIOS Flash Program Registers (based on SPI_BAR0)
+//
+#define R_SPI_MEM_HSFSC 0x04 ///< Hardware Sequencing Flash Status and Control Register(32bits)
+#define B_SPI_MEM_HSFSC_FDBC_MASK 0x3F000000 ///< Flash Data Byte Count ( <= 64), Count = (Value in this field) + 1.
+#define N_SPI_MEM_HSFSC_FDBC 24
+#define B_SPI_MEM_HSFSC_CYCLE_MASK 0x001E0000 ///< Flash Cycle.
+#define N_SPI_MEM_HSFSC_CYCLE 17
+#define V_SPI_MEM_HSFSC_CYCLE_READ 0 ///< Flash Cycle Read
+#define V_SPI_MEM_HSFSC_CYCLE_WRITE 2 ///< Flash Cycle Write
+#define V_SPI_MEM_HSFSC_CYCLE_4K_ERASE 3 ///< Flash Cycle 4K Block Erase
+#define V_SPI_MEM_HSFSC_CYCLE_64K_ERASE 4 ///< Flash Cycle 64K Sector Erase
+#define V_SPI_MEM_HSFSC_CYCLE_READ_SFDP 5 ///< Flash Cycle Read SFDP
+#define V_SPI_MEM_HSFSC_CYCLE_READ_JEDEC_ID 6 ///< Flash Cycle Read JEDEC ID
+#define V_SPI_MEM_HSFSC_CYCLE_WRITE_STATUS 7 ///< Flash Cycle Write Status
+#define V_SPI_MEM_HSFSC_CYCLE_READ_STATUS 8 ///< Flash Cycle Read Status
+#define B_SPI_MEM_HSFSC_CYCLE_FGO BIT16 ///< Flash Cycle Go.
+#define B_SPI_MEM_HSFSC_FDV BIT14 ///< Flash Descriptor Valid, once valid software can use hareware sequencing regs
+#define B_SPI_MEM_HSFSC_WRSDIS BIT11 ///< Write Status Disable
+#define B_SPI_MEM_HSFSC_SAF_CE BIT8 ///< SAF ctype error
+#define B_SPI_MEM_HSFSC_SAF_LE BIT6 ///< SAF link error
+#define B_SPI_MEM_HSFSC_SCIP BIT5 ///< SPI cycle in progress
+#define B_SPI_MEM_HSFSC_SAF_DLE BIT4 ///< SAF Data length error
+#define B_SPI_MEM_HSFSC_SAF_ERROR BIT3 ///< SAF Error
+#define B_SPI_MEM_HSFSC_AEL BIT2 ///< Access Error Log
+#define B_SPI_MEM_HSFSC_FCERR BIT1 ///< Flash Cycle Error
+#define B_SPI_MEM_HSFSC_FDONE BIT0 ///< Flash Cycle Done
+#define R_SPI_MEM_FADDR 0x08 ///< SPI Flash Address
+#define B_SPI_MEM_FADDR_MASK 0x07FFFFFF ///< SPI Flash Address Mask (0~26bit)
+#define R_SPI_MEM_FDATA00 0x10 ///< SPI Data 00 (32 bits)
+#define R_SPI_MEM_FRAP 0x50 ///< Flash Region Access Permissions Register
+#define B_SPI_MEM_FRAP_BRWA_MASK 0x0000FF00 ///< BIOS Region Write Access MASK, Region0~7 - 0: Flash Descriptor; 1: BIOS; 2: ME; 3: GbE; 4: PlatformData
+#define N_SPI_MEM_FRAP_BRWA 8 ///< BIOS Region Write Access bit position
+#define B_SPI_MEM_FRAP_BRRA_MASK 0x000000FF ///< BIOS Region Read Access MASK, Region0~7 - 0: Flash Descriptor; 1: BIOS; 2: ME; 3: GbE; 4: PlatformData
+#define R_SPI_MEM_FREG0_FLASHD 0x54 ///< Flash Region 0(Flash Descriptor)(32bits)
+#define S_SPI_MEM_FREGX 4 ///< Size of Flash Region register
+#define B_SPI_MEM_FREGX_LIMIT_MASK 0x7FFF0000 ///< Flash Region Limit [30:16] represents [26:12], [11:0] are assumed to be FFFh
+#define N_SPI_MEM_FREGX_LIMIT 16 ///< Region limit bit position
+#define N_SPI_MEM_FREGX_LIMIT_REPR 12 ///< Region limit bit represents position
+#define B_SPI_MEM_FREGX_BASE_MASK 0x00007FFF ///< Flash Region Base, [14:0] represents [26:12]
+#define N_SPI_MEM_FREGX_BASE 0 ///< Region base bit position
+#define N_SPI_MEM_FREGX_BASE_REPR 12 ///< Region base bit represents position
+#define R_SPI_MEM_FDOC 0xB4 ///< Flash Descriptor Observability Control Register(32 bits)
+#define B_SPI_MEM_FDOC_FDSS_MASK (BIT14 | BIT13 | BIT12) ///< Flash Descritor Section Select
+#define V_SPI_MEM_FDOC_FDSS_FSDM 0x0000 ///< Flash Signature and Descriptor Map
+#define V_SPI_MEM_FDOC_FDSS_COMP 0x1000 ///< Component
+
+#define B_SPI_MEM_FDOC_FDSI_MASK 0x0FFC ///< Flash Descriptor Section Index
+#define R_SPI_MEM_FDOD 0xB8 ///< Flash Descriptor Observability Data Register(32 bits)
+#define R_SPI_MEM_SFDP0_VSCC0 0xC4 ///< Vendor Specific Component Capabilities Register(32 bits)
+
+#define B_SPI_MEM_SFDPX_VSCCX_EO_64K BIT29 ///< 64k Erase valid (EO_64k_valid)
+#define R_SPI_MEM_SFDP1_VSCC1 0xC8 ///< Vendor Specific Component Capabilities Register(32 bits)
+
+#endif
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/Library/PeiSpiLib/PchSpi.c b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/Library/PeiSpiLib/PchSpi.c
new file mode 100644
index 0000000000..aaf4e1790f
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/Library/PeiSpiLib/PchSpi.c
@@ -0,0 +1,209 @@
+/** @file
+ PCH SPI PEI Library implements the SPI Host Controller Compatibility Interface.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#include <Library/IoLib.h>
+#include <Library/DebugLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/PeiServicesLib.h>
+#include <Library/PciSegmentLib.h>
+#include <Ppi/Spi.h>
+#include <Library/SpiCommonLib.h>
+#include <PchReservedResources.h>
+#include <IndustryStandard/Pci30.h>
+#include <Register/PchRegs.h>
+#include <Register/PchRegsLpc.h>
+#include <Register/SpiRegs.h>
+#include <Library/PchPciBdfLib.h>
+
+typedef struct {
+ EFI_PEI_PPI_DESCRIPTOR PpiDescriptor;
+ SPI_INSTANCE SpiInstance;
+} PEI_SPI_INSTANCE;
+
+/**
+ PCI Enumeratuion is not done till later in DXE
+ Initlialize SPI BAR0 to a default value till enumeration is done
+ also enable memory space decoding for SPI
+
+**/
+VOID
+InitSpiBar0 (
+ VOID
+ )
+{
+ UINT64 PchSpiBase;
+ PchSpiBase = SpiPciCfgBase ();
+ PciSegmentWrite32 (PchSpiBase + R_SPI_CFG_BAR0, PCH_SPI_BASE_ADDRESS);
+ PciSegmentOr32 (PchSpiBase + PCI_COMMAND_OFFSET, EFI_PCI_COMMAND_MEMORY_SPACE);
+}
+
+/**
+ This function Initial SPI services
+
+ @retval EFI_STATUS Results of the installation of the SPI services
+**/
+EFI_STATUS
+EFIAPI
+SpiServiceInit (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+ PEI_SPI_INSTANCE *PeiSpiInstance;
+ SPI_INSTANCE *SpiInstance;
+ PCH_SPI_PPI *SpiPpi;
+
+ Status = PeiServicesLocatePpi (
+ &gPchSpiPpiGuid,
+ 0,
+ NULL,
+ (VOID **)&SpiPpi
+ );
+
+ if (Status != EFI_SUCCESS) {
+ DEBUG ((DEBUG_INFO, "SpiServiceInit() Start\n"));
+
+ //
+ // PCI Enumeratuion is not done till later in DXE
+ // Initlialize SPI BAR0 to a default value till enumeration is done
+ // also enable memory space decoding for SPI
+ //
+ InitSpiBar0 ();
+
+ PeiSpiInstance = (PEI_SPI_INSTANCE *) AllocateZeroPool (sizeof (PEI_SPI_INSTANCE));
+ if (NULL == PeiSpiInstance) {
+ return EFI_OUT_OF_RESOURCES;
+ }
+
+ SpiInstance = &(PeiSpiInstance->SpiInstance);
+ SpiProtocolConstructor (SpiInstance);
+
+ PeiSpiInstance->PpiDescriptor.Flags = EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST;
+ PeiSpiInstance->PpiDescriptor.Guid = &gPchSpiPpiGuid;
+ PeiSpiInstance->PpiDescriptor.Ppi = &(SpiInstance->SpiProtocol);
+
+ ///
+ /// Install the SPI PPI
+ ///
+ DEBUG ((DEBUG_INFO, "SPI PPI Installed\n"));
+ Status = PeiServicesInstallPpi (&PeiSpiInstance->PpiDescriptor);
+ ASSERT_EFI_ERROR (Status);
+
+ DEBUG ((DEBUG_INFO, "SpiServiceInit() End\n"));
+ }
+ else {
+ DEBUG ((DEBUG_INFO, "SPI PPI already installed\n"));
+ }
+ return Status;
+}
+
+/**
+ Acquire pch spi mmio address.
+
+ @param[in] SpiInstance Pointer to SpiInstance to initialize
+
+ @retval PchSpiBar0 return SPI MMIO address
+**/
+UINTN
+AcquireSpiBar0 (
+ IN SPI_INSTANCE *SpiInstance
+ )
+{
+ return PciSegmentRead32 (SpiInstance->PchSpiBase + R_SPI_CFG_BAR0) & ~(B_SPI_CFG_BAR0_MASK);
+}
+
+/**
+ Release pch spi mmio address. Do nothing.
+
+ @param[in] SpiInstance Pointer to SpiInstance to initialize
+
+ @retval None
+**/
+VOID
+ReleaseSpiBar0 (
+ IN SPI_INSTANCE *SpiInstance
+ )
+{
+}
+
+/**
+ This function is a hook for Spi to disable BIOS Write Protect
+
+ @retval EFI_SUCCESS The protocol instance was properly initialized
+ @retval EFI_ACCESS_DENIED The BIOS Region can only be updated in SMM phase
+
+**/
+EFI_STATUS
+EFIAPI
+DisableBiosWriteProtect (
+ VOID
+ )
+{
+ UINT64 SpiBaseAddress;
+
+ SpiBaseAddress = SpiPciCfgBase ();
+ if ((PciSegmentRead8 (SpiBaseAddress + R_SPI_CFG_BC) & B_SPI_CFG_BC_EISS) != 0) {
+ return EFI_ACCESS_DENIED;
+ }
+ ///
+ /// Enable the access to the BIOS space for both read and write cycles
+ ///
+ PciSegmentOr8 (
+ SpiBaseAddress + R_SPI_CFG_BC,
+ B_SPI_CFG_BC_WPD
+ );
+
+ return EFI_SUCCESS;
+}
+
+/**
+ This function is a hook for Spi to enable BIOS Write Protect
+**/
+VOID
+EFIAPI
+EnableBiosWriteProtect (
+ VOID
+ )
+{
+ UINT64 SpiBaseAddress;
+
+ SpiBaseAddress = SpiPciCfgBase ();
+ ///
+ /// Disable the access to the BIOS space for write cycles
+ ///
+ PciSegmentAnd8 (
+ SpiBaseAddress + R_SPI_CFG_BC,
+ (UINT8) (~B_SPI_CFG_BC_WPD)
+ );
+}
+
+/**
+ Check if it's granted to do flash write.
+
+ @retval TRUE It's secure to do flash write.
+ @retval FALSE It's not secure to do flash write.
+**/
+BOOLEAN
+IsSpiFlashWriteGranted (
+ VOID
+ )
+{
+ return TRUE;
+}
+
+/**
+ Check if a save and restore of the SPI controller state is necessary
+
+ @retval TRUE It's necessary to save and restore SPI controller state
+ @retval FALSE It's not necessary to save and restore SPI controller state
+**/
+BOOLEAN
+IsSpiControllerSaveRestoreEnabled (
+ VOID
+ )
+{
+ return FALSE;
+}
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/Library/PeiSpiLib/PeiSpiLib.inf b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/Library/PeiSpiLib/PeiSpiLib.inf
new file mode 100644
index 0000000000..c3bf6d02a1
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/Library/PeiSpiLib/PeiSpiLib.inf
@@ -0,0 +1,41 @@
+## @file
+# Component description file for PCH Reset Lib Pei Phase
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+[Defines]
+INF_VERSION = 0x00010017
+BASE_NAME = PeiSpiLib
+FILE_GUID = 4998447D-7948-448F-AB75-96E24E18FF23
+VERSION_STRING = 1.0
+MODULE_TYPE = PEIM
+LIBRARY_CLASS = SpiLib
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = IA32 X64 IPF
+#
+
+[LibraryClasses]
+DebugLib
+PeiServicesLib
+PeiServicesTablePointerLib
+MemoryAllocationLib
+PciSegmentLib
+SpiCommonLib
+PchPciBdfLib
+
+[Packages]
+MdePkg/MdePkg.dec
+AlderlakeSiliconPkg/SiPkg.dec
+
+
+[Sources]
+PchSpi.c
+
+
+[Ppis]
+gPchSpiPpiGuid ## PRODUCES
+
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/LibraryPrivate/BaseSpiCommonLib/BaseSpiCommonLib.inf b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/LibraryPrivate/BaseSpiCommonLib/BaseSpiCommonLib.inf
new file mode 100644
index 0000000000..25ab91940c
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/LibraryPrivate/BaseSpiCommonLib/BaseSpiCommonLib.inf
@@ -0,0 +1,29 @@
+## @file
+# Component description file for the PchSpiCommonLib
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = BaseSpiCommonLib
+ FILE_GUID = A37CB67E-7D85-45B3-B07E-BF65BDB603E8
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = SpiCommonLib
+
+[Sources]
+ SpiCommon.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ AlderlakeSiliconPkg/SiPkg.dec
+
+[LibraryClasses]
+ IoLib
+ DebugLib
+ PmcLib
+ PchPciBdfLib
+
+[Pcd]
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/LibraryPrivate/BaseSpiCommonLib/SpiCommon.c b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/LibraryPrivate/BaseSpiCommonLib/SpiCommon.c
new file mode 100644
index 0000000000..ab51521f14
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/LibraryPrivate/BaseSpiCommonLib/SpiCommon.c
@@ -0,0 +1,1127 @@
+/** @file
+ PCH SPI Common Driver implements the SPI Host Controller Compatibility Interface.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#include <Uefi/UefiBaseType.h>
+#include <Library/BaseLib.h>
+#include <Library/IoLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <IndustryStandard/Pci30.h>
+#include <Library/PmcLib.h>
+#include <Library/PciSegmentLib.h>
+#include <Protocol/Spi.h>
+#include <Library/SpiCommonLib.h>
+#include <Register/PchRegs.h>
+#include <Register/SpiRegs.h>
+#include <Register/FlashRegs.h>
+#include <Register/PmcRegs.h>
+#include <Library/PchPciBdfLib.h>
+
+#define DEFAULT_CPU_STRAP_BASE_OFFSET 0x300 // Default CPU Straps base offset
+#define B_SPI_MEM_HSFSC_SAVE_MASK (B_SPI_MEM_HSFSC_FDBC_MASK | B_SPI_MEM_HSFSC_CYCLE_MASK)
+
+/**
+ Initialize an SPI protocol instance.
+
+ @param[in] SpiInstance Pointer to SpiInstance to initialize
+
+ @retval EFI_SUCCESS The protocol instance was properly initialized
+ @exception EFI_UNSUPPORTED The PCH is not supported by this module
+**/
+EFI_STATUS
+SpiProtocolConstructor (
+ IN SPI_INSTANCE *SpiInstance
+ )
+{
+ UINTN PchSpiBar0;
+ UINT32 Data32;
+ UINT16 Mdtba;
+ EFI_STATUS Status;
+
+ //
+ // Initialize the SPI protocol instance
+ //
+ SpiInstance->Signature = PCH_SPI_PRIVATE_DATA_SIGNATURE;
+ SpiInstance->Handle = NULL;
+ SpiInstance->SpiProtocol.Revision = PCH_SPI_SERVICES_REVISION;
+ SpiInstance->SpiProtocol.FlashRead = SpiProtocolFlashRead;
+ SpiInstance->SpiProtocol.FlashWrite = SpiProtocolFlashWrite;
+ SpiInstance->SpiProtocol.FlashErase = SpiProtocolFlashErase;
+ SpiInstance->SpiProtocol.FlashReadSfdp = SpiProtocolFlashReadSfdp;
+ SpiInstance->SpiProtocol.FlashReadJedecId = SpiProtocolFlashReadJedecId;
+ SpiInstance->SpiProtocol.FlashWriteStatus = SpiProtocolFlashWriteStatus;
+ SpiInstance->SpiProtocol.FlashReadStatus = SpiProtocolFlashReadStatus;
+ SpiInstance->SpiProtocol.GetRegionAddress = SpiProtocolGetRegionAddress;
+ SpiInstance->SpiProtocol.ReadPchSoftStrap = SpiProtocolReadPchSoftStrap;
+ SpiInstance->SpiProtocol.ReadCpuSoftStrap = SpiProtocolReadCpuSoftStrap;
+
+ SpiInstance->PchSpiBase = SpiPciCfgBase ();
+
+ SpiInstance->PchAcpiBase = PmcGetAcpiBase ();
+ ASSERT (SpiInstance->PchAcpiBase != 0);
+
+ PchSpiBar0 = PciSegmentRead32 (SpiInstance->PchSpiBase + R_SPI_CFG_BAR0) & ~(B_SPI_CFG_BAR0_MASK);
+ if (PchSpiBar0 == 0) {
+ DEBUG ((DEBUG_ERROR, "ERROR : PchSpiBar0 is invalid!\n"));
+ ASSERT (FALSE);
+ }
+
+ if ((MmioRead32 (PchSpiBar0 + R_SPI_MEM_HSFSC) & B_SPI_MEM_HSFSC_FDV) == 0) {
+ DEBUG ((DEBUG_ERROR, "ERROR : SPI Flash Signature invalid, cannot use the Hardware Sequencing registers!\n"));
+ ASSERT (FALSE);
+ }
+
+ //
+ // Get Region 0 - 7 read Permission bits, region 8 and above are not permitted.
+ //
+ SpiInstance->ReadPermission = MmioRead8 (PchSpiBar0 + R_SPI_MEM_FRAP) & B_SPI_MEM_FRAP_BRRA_MASK;
+ DEBUG ((DEBUG_INFO, "Flash Region read Permission : %0x\n", SpiInstance->ReadPermission));
+ //
+ // Get Region 0 - 7 write Permission bits, region 8 and above are not permitted.
+ //
+ SpiInstance->WritePermission = (UINT8) ((MmioRead16 (PchSpiBar0 + R_SPI_MEM_FRAP) &
+ B_SPI_MEM_FRAP_BRWA_MASK) >> N_SPI_MEM_FRAP_BRWA);
+ DEBUG ((DEBUG_INFO, "Flash Region write Permission : %0x\n", SpiInstance->WritePermission));
+
+ SpiInstance->SfdpVscc0Value = MmioRead32 (PchSpiBar0 + R_SPI_MEM_SFDP0_VSCC0);
+ DEBUG ((DEBUG_INFO, "Component 0 SFDP VSCC value : %0x\n", SpiInstance->SfdpVscc0Value));
+ SpiInstance->SfdpVscc1Value = MmioRead32 (PchSpiBar0 + R_SPI_MEM_SFDP1_VSCC1);
+ DEBUG ((DEBUG_INFO, "Component 1 SFDP VSCC value : %0x\n", SpiInstance->SfdpVscc1Value));
+
+ //
+ // Select to Flash Map 0 Register to get the number of flash Component
+ //
+ MmioAndThenOr32 (
+ PchSpiBar0 + R_SPI_MEM_FDOC,
+ (UINT32) (~(B_SPI_MEM_FDOC_FDSS_MASK | B_SPI_MEM_FDOC_FDSI_MASK)),
+ (UINT32) (V_SPI_MEM_FDOC_FDSS_FSDM | R_FLASH_FDBAR_FLASH_MAP0)
+ );
+
+ //
+ // Copy Zero based Number Of Components
+ //
+ SpiInstance->NumberOfComponents = (UINT8) ((MmioRead16 (PchSpiBar0 + R_SPI_MEM_FDOD) & B_FLASH_FDBAR_NC) >> N_FLASH_FDBAR_NC);
+ DEBUG ((DEBUG_INFO, "Component Number : %0x\n", SpiInstance->NumberOfComponents + 1));
+
+ MmioAndThenOr32 (
+ PchSpiBar0 + R_SPI_MEM_FDOC,
+ (UINT32) (~(B_SPI_MEM_FDOC_FDSS_MASK | B_SPI_MEM_FDOC_FDSI_MASK)),
+ (UINT32) (V_SPI_MEM_FDOC_FDSS_COMP | R_FLASH_FCBA_FLCOMP)
+ );
+
+ //
+ // Copy Component 0 Density
+ //
+ Data32 = MmioRead32 (PchSpiBar0 + R_SPI_MEM_FDOD);
+ if (SpiInstance->NumberOfComponents > 0) {
+ SpiInstance->Component1StartAddr = V_FLASH_FLCOMP_COMP_512KB <<
+ (Data32 & B_FLASH_FLCOMP_COMP0_MASK);
+ DEBUG ((DEBUG_INFO, "Component 1 StartAddr : %0x\n", SpiInstance->Component1StartAddr));
+ SpiInstance->TotalFlashSize = SpiInstance->Component1StartAddr +
+ (V_FLASH_FLCOMP_COMP_512KB <<
+ ((Data32 & B_FLASH_FLCOMP_COMP1_MASK) >>
+ N_FLASH_FLCOMP_COMP1));
+ } else {
+ SpiInstance->TotalFlashSize = V_FLASH_FLCOMP_COMP_512KB <<
+ (Data32 & B_FLASH_FLCOMP_COMP0_MASK);
+ }
+ DEBUG ((DEBUG_INFO, "Total Flash Size : %0x\n", SpiInstance->TotalFlashSize));
+
+ //
+ // Select FLASH_MAP1 to get Flash PCH Strap Base Address
+ //
+ MmioAndThenOr32 (
+ (PchSpiBar0 + R_SPI_MEM_FDOC),
+ (UINT32) (~(B_SPI_MEM_FDOC_FDSS_MASK | B_SPI_MEM_FDOC_FDSI_MASK)),
+ (UINT32) (V_SPI_MEM_FDOC_FDSS_FSDM | R_FLASH_FDBAR_FLASH_MAP1)
+ );
+ //
+ // Align FPSBA with address bits for the PCH Strap portion of flash descriptor
+ //
+ Data32 = MmioRead32 (PchSpiBar0 + R_SPI_MEM_FDOD);
+ SpiInstance->PchStrapBaseAddr = (UINT16) (((Data32 & B_FLASH_FDBAR_FPSBA)
+ >> N_FLASH_FDBAR_FPSBA)
+ << N_FLASH_FDBAR_FPSBA_REPR);
+ DEBUG ((DEBUG_INFO, "PchStrapBaseAddr : %0x\n", SpiInstance->PchStrapBaseAddr));
+ ASSERT (SpiInstance->PchStrapBaseAddr != 0);
+ //
+ // PCH Strap Length, [31:24] represents number of Dwords
+ //
+ SpiInstance->PchStrapSize = (UINT16) (((Data32 & B_FLASH_FDBAR_PCHSL)
+ >> N_FLASH_FDBAR_PCHSL)
+ * sizeof (UINT32));
+ DEBUG ((DEBUG_INFO, "PchStrapSize : %0x\n", SpiInstance->PchStrapSize));
+
+ //
+ // Select FLASH_MAP2 to get Flash CPU Strap Base Address
+ //
+ MmioAndThenOr32 (
+ (PchSpiBar0 + R_SPI_MEM_FDOC),
+ (UINT32) (~(B_SPI_MEM_FDOC_FDSS_MASK | B_SPI_MEM_FDOC_FDSI_MASK)),
+ (UINT32) (V_SPI_MEM_FDOC_FDSS_FSDM | R_FLASH_FDBAR_FLASH_MAP2)
+ );
+ //
+ // Align FPSBA with address bits for the CPU Strap portion of flash descriptor
+ //
+ Data32 = MmioRead32 (PchSpiBar0 + R_SPI_MEM_FDOD);
+ //
+ // CPU Strap Length, [23:16] represents number of Dwords
+ //
+ SpiInstance->CpuStrapSize = (UINT16) (((Data32 & B_FLASH_FDBAR_CPUSL)
+ >> N_FLASH_FDBAR_CPUSL)
+ * sizeof (UINT32));
+
+ //
+ // CPU Strap Address [11:2] represent offset from MDTBA
+ //
+ SpiInstance->CpuStrapBaseAddr = (UINT16) ((Data32 & B_FLASH_FDBAR_FCPUSBA) >> N_FLASH_FDBAR_FCPUSBA);
+ ASSERT (SpiInstance->CpuStrapBaseAddr != 0);
+
+ //
+ // If CPU Strap base address is different than 0x300 need to add MDTBA value for final location
+ //
+ if (SpiInstance->CpuStrapBaseAddr != DEFAULT_CPU_STRAP_BASE_OFFSET) {
+ Status = SpiProtocolFlashRead (&(SpiInstance->SpiProtocol), FlashRegionAll, R_FLASH_UMAP1, sizeof (Data32), (UINT8 *) (&Data32));
+ ASSERT_EFI_ERROR (Status);
+ Mdtba = (UINT16)(((Data32 & B_FLASH_UMAP1_MDTBA) >> N_FLASH_UMAP1_MDTBA) << N_FLASH_UMAP1_MDTBA_REPR);
+ DEBUG ((DEBUG_INFO, "Mdtba : %0x\n", Mdtba));
+ // Add MDTBA offset for final address of CPU Straps
+ SpiInstance->CpuStrapBaseAddr += Mdtba;
+ }
+
+ DEBUG ((DEBUG_INFO, "CpuStrapBaseAddr : %0x\n", SpiInstance->CpuStrapBaseAddr));
+ DEBUG ((DEBUG_INFO, "CpuStrapSize : %0x\n", SpiInstance->CpuStrapSize));
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Delay for at least the request number of microseconds for Runtime usage.
+
+ @param[in] ABase Acpi base address
+ @param[in] Microseconds Number of microseconds to delay.
+
+**/
+VOID
+EFIAPI
+PchPmTimerStallRuntimeSafe (
+ IN UINT16 ABase,
+ IN UINTN Microseconds
+ )
+{
+ UINTN Ticks;
+ UINTN Counts;
+ UINTN CurrentTick;
+ UINTN OriginalTick;
+ UINTN RemainingTick;
+
+ if (Microseconds == 0) {
+ return;
+ }
+
+ OriginalTick = IoRead32 ((UINTN) (ABase + R_ACPI_IO_PM1_TMR)) & B_ACPI_IO_PM1_TMR_TMR_VAL;
+ CurrentTick = OriginalTick;
+
+ //
+ // The timer frequency is 3.579545 MHz, so 1 ms corresponds 3.58 clocks
+ //
+ Ticks = Microseconds * 358 / 100 + OriginalTick + 1;
+
+ //
+ // The loops needed by timer overflow
+ //
+ Counts = Ticks / V_ACPI_IO_PM1_TMR_MAX_VAL;
+
+ //
+ // Remaining clocks within one loop
+ //
+ RemainingTick = Ticks % V_ACPI_IO_PM1_TMR_MAX_VAL;
+
+ //
+ // not intend to use TMROF_STS bit of register PM1_STS, because this adds extra
+ // one I/O operation, and maybe generate SMI
+ //
+ while ((Counts != 0) || (RemainingTick > CurrentTick)) {
+ CurrentTick = IoRead32 ((UINTN) (ABase + R_ACPI_IO_PM1_TMR)) & B_ACPI_IO_PM1_TMR_TMR_VAL;
+ //
+ // Check if timer overflow
+ //
+ if ((CurrentTick < OriginalTick)) {
+ if (Counts != 0) {
+ Counts--;
+ } else {
+ //
+ // If timer overflow and Counts equ to 0, that means we already stalled more than
+ // RemainingTick, break the loop here
+ //
+ break;
+ }
+ }
+
+ OriginalTick = CurrentTick;
+ }
+}
+
+/**
+ Wait execution cycle to complete on the SPI interface.
+
+ @param[in] This The SPI protocol instance
+ @param[in] PchSpiBar0 Spi MMIO base address
+ @param[in] ErrorCheck TRUE if the SpiCycle needs to do the error check
+
+ @retval TRUE SPI cycle completed on the interface.
+ @retval FALSE Time out while waiting the SPI cycle to complete.
+ It's not safe to program the next command on the SPI interface.
+**/
+STATIC
+BOOLEAN
+WaitForSpiCycleComplete (
+ IN PCH_SPI_PROTOCOL *This,
+ IN UINTN PchSpiBar0,
+ IN BOOLEAN ErrorCheck
+ )
+{
+ UINT64 WaitTicks;
+ UINT64 WaitCount;
+ UINT32 Data32;
+ SPI_INSTANCE *SpiInstance;
+
+ SpiInstance = SPI_INSTANCE_FROM_SPIPROTOCOL (This);
+
+ //
+ // Convert the wait period allowed into to tick count
+ //
+ WaitCount = SPI_WAIT_TIME / SPI_WAIT_PERIOD;
+ //
+ // Wait for the SPI cycle to complete.
+ //
+ for (WaitTicks = 0; WaitTicks < WaitCount; WaitTicks++) {
+ Data32 = MmioRead32 (PchSpiBar0 + R_SPI_MEM_HSFSC);
+ if ((Data32 & B_SPI_MEM_HSFSC_SCIP) == 0) {
+ MmioWrite8 (PchSpiBar0 + R_SPI_MEM_HSFSC, B_SPI_MEM_HSFSC_FCERR | B_SPI_MEM_HSFSC_FDONE);
+ if (((Data32 & B_SPI_MEM_HSFSC_FCERR) != 0) && (ErrorCheck == TRUE)) {
+ return FALSE;
+ } else {
+ return TRUE;
+ }
+ }
+ PchPmTimerStallRuntimeSafe (SpiInstance->PchAcpiBase, SPI_WAIT_PERIOD);
+ }
+ return FALSE;
+}
+
+/**
+ This function waits for a pending SPI transaction to complete without clearing
+ status fields
+
+ @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
+ @param[in] PchSpiBar0 SPI MMIO address
+
+ @retval TRUE SPI cycle completed on the interface.
+ @retval FALSE Time out while waiting the SPI cycle to complete.
+ It's not safe to program the next command on the SPI interface.
+**/
+BOOLEAN
+STATIC
+WaitForScipNoClear (
+ IN PCH_SPI_PROTOCOL *This,
+ IN UINTN PchSpiBar0
+ )
+{
+ UINT64 WaitTicks;
+ UINT64 WaitCount;
+ SPI_INSTANCE *SpiInstance;
+ UINT32 Data32;
+
+ SpiInstance = SPI_INSTANCE_FROM_SPIPROTOCOL (This);
+
+ //
+ // Wait for the SPI cycle to complete.
+ //
+ WaitCount = SPI_WAIT_TIME / SPI_WAIT_PERIOD;
+ for (WaitTicks = 0; WaitTicks < WaitCount; WaitTicks++) {
+ Data32 = MmioRead32 (PchSpiBar0 + R_SPI_MEM_HSFSC);
+ if ((Data32 & B_SPI_MEM_HSFSC_SCIP) == 0) {
+ return TRUE;
+ }
+ PchPmTimerStallRuntimeSafe (SpiInstance->PchAcpiBase, SPI_WAIT_PERIOD);
+ }
+ return FALSE;
+}
+
+/**
+ This function sets the FDONE and optionally FCERR bits in the HSFS_CTL register
+
+ @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
+ @param[in] PchSpiBar0 SPI MMIO address
+ @param[in] SetErrorBit Set to TRUE to set the FCERR bit
+
+**/
+VOID
+STATIC
+SetHsfscFdone (
+ IN PCH_SPI_PROTOCOL *This,
+ IN UINTN PchSpiBar0,
+ IN BOOLEAN SetFcErrorBit
+ )
+{
+ EFI_STATUS Status;
+ UINT32 HardwareSpiAddr;
+ UINT32 FlashRegionSize;
+ UINT32 Index;
+ UINT8 DataCount;
+
+ Status = SpiProtocolGetRegionAddress (This, FlashRegionBios, &HardwareSpiAddr, &FlashRegionSize);
+ if (EFI_ERROR (Status)) {
+ return;
+ }
+
+ //
+ // Clear FDONE and FCERR
+ //
+ MmioWrite8 (PchSpiBar0 + R_SPI_MEM_HSFSC, B_SPI_MEM_HSFSC_FCERR | B_SPI_MEM_HSFSC_FDONE);
+
+ //
+ // Fill data buffer
+ //
+ if (SetFcErrorBit) {
+ for (Index = 0; Index < 64; Index += sizeof (UINT32)) {
+ MmioWrite32 (PchSpiBar0 + R_SPI_MEM_FDATA00 + Index, 0xFFFFFFFF);
+ }
+ }
+
+ //
+ // Set the Flash Address
+ //
+ MmioWrite32 (
+ (PchSpiBar0 + R_SPI_MEM_FADDR),
+ (UINT32) (HardwareSpiAddr & B_SPI_MEM_FADDR_MASK)
+ );
+ //
+ // Set Data count, Flash cycle, and Set Go bit to start a cycle
+ //
+ if (SetFcErrorBit) {
+ DataCount = 0x3F;
+ } else {
+ DataCount = 0;
+ }
+ MmioAndThenOr32 (
+ PchSpiBar0 + R_SPI_MEM_HSFSC,
+ (UINT32) (~(B_SPI_MEM_HSFSC_FDBC_MASK | B_SPI_MEM_HSFSC_CYCLE_MASK)),
+ (UINT32) (((DataCount << N_SPI_MEM_HSFSC_FDBC) & B_SPI_MEM_HSFSC_FDBC_MASK) |
+ (V_SPI_MEM_HSFSC_CYCLE_READ << N_SPI_MEM_HSFSC_CYCLE) |
+ B_SPI_MEM_HSFSC_CYCLE_FGO)
+ );
+
+ if (SetFcErrorBit) {
+ //
+ // Intentionally write to FDATA while a cycle is in progress to generate an error
+ //
+ for (Index = 0; Index < 64; Index += sizeof (UINT32)) {
+ MmioWrite32 (PchSpiBar0 + R_SPI_MEM_FDATA00 + Index, 0x0);
+ }
+ }
+
+ WaitForScipNoClear (This, PchSpiBar0);
+}
+
+/**
+ This function sends the programmed SPI command to the device.
+
+ @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
+ @param[in] SpiRegionType The SPI Region type for flash cycle which is listed in the Descriptor
+ @param[in] FlashCycleType The Flash SPI cycle type list in HSFC (Hardware Sequencing Flash Control Register) register
+ @param[in] Address The Flash Linear Address must fall within a region for which BIOS has access permissions.
+ @param[in] ByteCount Number of bytes in the data portion of the SPI cycle.
+ @param[in,out] Buffer Pointer to caller-allocated buffer containing the dada received or sent during the SPI cycle.
+
+ @retval EFI_SUCCESS SPI command completes successfully.
+ @retval EFI_DEVICE_ERROR Device error, the command aborts abnormally.
+ @retval EFI_ACCESS_DENIED Some unrecognized or blocked command encountered in hardware sequencing mode
+ @retval EFI_INVALID_PARAMETER The parameters specified are not valid.
+**/
+STATIC
+EFI_STATUS
+SendSpiCmd (
+ IN PCH_SPI_PROTOCOL *This,
+ IN FLASH_REGION_TYPE FlashRegionType,
+ IN FLASH_CYCLE_TYPE FlashCycleType,
+ IN UINT32 Address,
+ IN UINT32 ByteCount,
+ IN OUT UINT8 *Buffer
+ )
+{
+ UINT32 FdataSave[16];
+ EFI_STATUS Status;
+ UINT32 Index;
+ SPI_INSTANCE *SpiInstance;
+ UINT64 SpiBaseAddress;
+ UINTN PchSpiBar0;
+ UINT32 HardwareSpiAddr;
+ UINT32 FlashRegionSize;
+ UINT32 SpiDataCount;
+ UINT32 FlashCycle;
+ UINT8 BiosCtlSave;
+ UINT32 SmiEnSave;
+ UINT16 ABase;
+ UINT32 HsfstsCtl;
+ UINT32 FaddrSave;
+ UINT32 HsfscSave;
+ BOOLEAN HsfscFdoneSave;
+ BOOLEAN HsfscFcerrSave;
+ BOOLEAN RestoreState;
+
+ //
+ // For flash write, there is a requirement that all CPU threads are in SMM
+ // before the flash protection is disabled.
+ //
+ if ((FlashCycleType == FlashCycleWrite) || (FlashCycleType == FlashCycleErase)) {
+ if (!IsSpiFlashWriteGranted ()) {
+ return EFI_ACCESS_DENIED;
+ }
+ }
+
+ Status = EFI_SUCCESS;
+ SpiInstance = SPI_INSTANCE_FROM_SPIPROTOCOL (This);
+ SpiBaseAddress = SpiInstance->PchSpiBase;
+ ABase = SpiInstance->PchAcpiBase;
+ RestoreState = FALSE;
+
+ //
+ // Disable SMIs to make sure normal mode flash access is not interrupted by an SMI
+ // whose SMI handler accesses flash (e.g. for error logging)
+ //
+ // *** NOTE: if the SMI_LOCK bit is set (i.e., PMC PCI Offset A0h [4]='1'),
+ // clearing B_GBL_SMI_EN will not have effect. In this situation, some other
+ // synchronization methods must be applied here or in the consumer of the
+ // SendSpiCmd. An example method is disabling the specific SMI sources
+ // whose SMI handlers access flash before flash cycle and re-enabling the SMI
+ // sources after the flash cycle .
+ //
+ SmiEnSave = IoRead32 ((UINTN) (ABase + R_ACPI_IO_SMI_EN));
+ IoWrite32 ((UINTN) (ABase + R_ACPI_IO_SMI_EN), SmiEnSave & (UINT32) (~B_ACPI_IO_SMI_EN_GBL_SMI));
+ BiosCtlSave = PciSegmentRead8 (SpiBaseAddress + R_SPI_CFG_BC) & B_SPI_CFG_BC_SRC;
+
+ //
+ // Acquire SPI BAR0
+ //
+ PchSpiBar0 = AcquireSpiBar0 (SpiInstance);
+
+ //
+ // If it's write cycle, disable Prefetching, Caching and disable BIOS Write Protect
+ //
+ if ((FlashCycleType == FlashCycleWrite) ||
+ (FlashCycleType == FlashCycleErase)) {
+ Status = DisableBiosWriteProtect ();
+ if (EFI_ERROR (Status)) {
+ goto SendSpiCmdEnd;
+ }
+ PciSegmentAndThenOr8 (
+ SpiBaseAddress + R_SPI_CFG_BC,
+ (UINT8) (~B_SPI_CFG_BC_SRC),
+ (UINT8) (V_SPI_CFG_BC_SRC_PREF_DIS_CACHE_DIS << N_SPI_CFG_BC_SRC)
+ );
+ }
+
+ //
+ // Save current SPI controller state
+ //
+ if (IsSpiControllerSaveRestoreEnabled ()) {
+ if (!WaitForScipNoClear (This, PchSpiBar0)) {
+ Status = EFI_DEVICE_ERROR;
+ goto SendSpiCmdEnd;
+ }
+ HsfscSave = MmioRead32 (PchSpiBar0 + R_SPI_MEM_HSFSC);
+ HsfscFdoneSave = ((HsfscSave & B_SPI_MEM_HSFSC_FDONE) != 0) ? TRUE : FALSE;
+ HsfscFcerrSave = ((HsfscSave & B_SPI_MEM_HSFSC_FCERR) != 0) ? TRUE : FALSE;
+ HsfscSave &= B_SPI_MEM_HSFSC_SAVE_MASK;
+ FaddrSave = MmioRead32 (PchSpiBar0 + R_SPI_MEM_FADDR);
+ for (Index = 0; Index < 64; Index += sizeof (UINT32)) {
+ FdataSave[Index >> 2] = MmioRead32 (PchSpiBar0 + R_SPI_MEM_FDATA00 + Index);
+ }
+ RestoreState = TRUE;
+ }
+
+ //
+ // Make sure it's safe to program the command.
+ //
+ if (!WaitForSpiCycleComplete (This, PchSpiBar0, FALSE)) {
+ Status = EFI_DEVICE_ERROR;
+ goto SendSpiCmdEnd;
+ }
+
+ //
+ // Check if Write Status isn't disabled in HW Sequencing
+ //
+ if (FlashCycleType == FlashCycleWriteStatus) {
+ HsfstsCtl = MmioRead32 (PchSpiBar0 + R_SPI_MEM_HSFSC);
+ if ((HsfstsCtl & B_SPI_MEM_HSFSC_WRSDIS) != 0) {
+ Status = EFI_ACCESS_DENIED;
+ goto SendSpiCmdEnd;
+ }
+ }
+
+ Status = SpiProtocolGetRegionAddress (This, FlashRegionType, &HardwareSpiAddr, &FlashRegionSize);
+ if (EFI_ERROR (Status)) {
+ goto SendSpiCmdEnd;
+ }
+ HardwareSpiAddr += Address;
+ if ((Address + ByteCount) > FlashRegionSize) {
+ Status = EFI_INVALID_PARAMETER;
+ goto SendSpiCmdEnd;
+ }
+
+ //
+ // Check for PCH SPI hardware sequencing required commands
+ //
+ FlashCycle = 0;
+ switch (FlashCycleType) {
+ case FlashCycleRead:
+ FlashCycle = (UINT32) (V_SPI_MEM_HSFSC_CYCLE_READ << N_SPI_MEM_HSFSC_CYCLE);
+ break;
+ case FlashCycleWrite:
+ FlashCycle = (UINT32) (V_SPI_MEM_HSFSC_CYCLE_WRITE << N_SPI_MEM_HSFSC_CYCLE);
+ break;
+ case FlashCycleErase:
+ if (((ByteCount % SIZE_4KB) != 0) ||
+ ((HardwareSpiAddr % SIZE_4KB) != 0)) {
+ ASSERT (FALSE);
+ Status = EFI_INVALID_PARAMETER;
+ goto SendSpiCmdEnd;
+ }
+ break;
+ case FlashCycleReadSfdp:
+ FlashCycle = (UINT32) (V_SPI_MEM_HSFSC_CYCLE_READ_SFDP << N_SPI_MEM_HSFSC_CYCLE);
+ break;
+ case FlashCycleReadJedecId:
+ FlashCycle = (UINT32) (V_SPI_MEM_HSFSC_CYCLE_READ_JEDEC_ID << N_SPI_MEM_HSFSC_CYCLE);
+ break;
+ case FlashCycleWriteStatus:
+ FlashCycle = (UINT32) (V_SPI_MEM_HSFSC_CYCLE_WRITE_STATUS << N_SPI_MEM_HSFSC_CYCLE);
+ break;
+ case FlashCycleReadStatus:
+ FlashCycle = (UINT32) (V_SPI_MEM_HSFSC_CYCLE_READ_STATUS << N_SPI_MEM_HSFSC_CYCLE);
+ break;
+ default:
+ //
+ // Unrecognized Operation
+ //
+ ASSERT (FALSE);
+ Status = EFI_INVALID_PARAMETER;
+ goto SendSpiCmdEnd;
+ break;
+ }
+
+ do {
+ SpiDataCount = ByteCount;
+ if ((FlashCycleType == FlashCycleRead) ||
+ (FlashCycleType == FlashCycleWrite) ||
+ (FlashCycleType == FlashCycleReadSfdp)) {
+ //
+ // Trim at 256 byte boundary per operation,
+ // - PCH SPI controller requires trimming at 4KB boundary
+ // - Some SPI chips require trimming at 256 byte boundary for write operation
+ // - Trimming has limited performance impact as we can read / write at most 64 bytes
+ // per operation
+ //
+ if (HardwareSpiAddr + ByteCount > ((HardwareSpiAddr + BIT8) &~(BIT8 - 1))) {
+ SpiDataCount = (((UINT32) (HardwareSpiAddr) + BIT8) &~(BIT8 - 1)) - (UINT32) (HardwareSpiAddr);
+ }
+ //
+ // Calculate the number of bytes to shift in/out during the SPI data cycle.
+ // Valid settings for the number of bytes during each data portion of the
+ // PCH SPI cycles are: 0, 1, 2, 3, 4, 5, 6, 7, 8, 16, 24, 32, 40, 48, 56, 64
+ //
+ if (SpiDataCount >= 64) {
+ SpiDataCount = 64;
+ } else if ((SpiDataCount &~0x07) != 0) {
+ SpiDataCount = SpiDataCount &~0x07;
+ }
+ }
+ if (FlashCycleType == FlashCycleErase) {
+ if (((ByteCount / SIZE_64KB) != 0) &&
+ ((ByteCount % SIZE_64KB) == 0) &&
+ ((HardwareSpiAddr % SIZE_64KB) == 0)) {
+ if ((SpiInstance->NumberOfComponents == 0) ||
+ (HardwareSpiAddr < SpiInstance->Component1StartAddr)) {
+ //
+ // Check whether Component0 support 64k Erase
+ //
+ if ((SpiInstance->SfdpVscc0Value & B_SPI_MEM_SFDPX_VSCCX_EO_64K) != 0) {
+ SpiDataCount = SIZE_64KB;
+ } else {
+ SpiDataCount = SIZE_4KB;
+ }
+ } else {
+ //
+ // Check whether Component1 support 64k Erase
+ //
+ if ((SpiInstance->SfdpVscc1Value & B_SPI_MEM_SFDPX_VSCCX_EO_64K) != 0) {
+ SpiDataCount = SIZE_64KB;
+ } else {
+ SpiDataCount = SIZE_4KB;
+ }
+ }
+ } else {
+ SpiDataCount = SIZE_4KB;
+ }
+ if (SpiDataCount == SIZE_4KB) {
+ FlashCycle = (UINT32) (V_SPI_MEM_HSFSC_CYCLE_4K_ERASE << N_SPI_MEM_HSFSC_CYCLE);
+ } else {
+ FlashCycle = (UINT32) (V_SPI_MEM_HSFSC_CYCLE_64K_ERASE << N_SPI_MEM_HSFSC_CYCLE);
+ }
+ }
+ //
+ // If it's write cycle, load data into the SPI data buffer.
+ //
+ if ((FlashCycleType == FlashCycleWrite) || (FlashCycleType == FlashCycleWriteStatus)) {
+ if ((SpiDataCount & 0x07) != 0) {
+ //
+ // Use Byte write if Data Count is 0, 1, 2, 3, 4, 5, 6, 7
+ //
+ for (Index = 0; Index < SpiDataCount; Index++) {
+ MmioWrite8 (PchSpiBar0 + R_SPI_MEM_FDATA00 + Index, Buffer[Index]);
+ }
+ } else {
+ //
+ // Use Dword write if Data Count is 8, 16, 24, 32, 40, 48, 56, 64
+ //
+ for (Index = 0; Index < SpiDataCount; Index += sizeof (UINT32)) {
+ MmioWrite32 (PchSpiBar0 + R_SPI_MEM_FDATA00 + Index, *(UINT32 *) (Buffer + Index));
+ }
+ }
+ }
+
+ //
+ // Set the Flash Address
+ //
+ MmioWrite32 (
+ (PchSpiBar0 + R_SPI_MEM_FADDR),
+ (UINT32) (HardwareSpiAddr & B_SPI_MEM_FADDR_MASK)
+ );
+
+ //
+ // Set Data count, Flash cycle, and Set Go bit to start a cycle
+ //
+ MmioAndThenOr32 (
+ PchSpiBar0 + R_SPI_MEM_HSFSC,
+ (UINT32) (~(B_SPI_MEM_HSFSC_FDBC_MASK | B_SPI_MEM_HSFSC_CYCLE_MASK)),
+ (UINT32) ((((SpiDataCount - 1) << N_SPI_MEM_HSFSC_FDBC) & B_SPI_MEM_HSFSC_FDBC_MASK) | FlashCycle | B_SPI_MEM_HSFSC_CYCLE_FGO)
+ );
+ //
+ // end of command execution
+ //
+ // Wait the SPI cycle to complete.
+ //
+ if (!WaitForSpiCycleComplete (This, PchSpiBar0, TRUE)) {
+ ASSERT (FALSE);
+ Status = EFI_DEVICE_ERROR;
+ goto SendSpiCmdEnd;
+ }
+ //
+ // If it's read cycle, load data into the call's buffer.
+ //
+ if ((FlashCycleType == FlashCycleRead) ||
+ (FlashCycleType == FlashCycleReadSfdp) ||
+ (FlashCycleType == FlashCycleReadJedecId) ||
+ (FlashCycleType == FlashCycleReadStatus)) {
+ if ((SpiDataCount & 0x07) != 0) {
+ //
+ // Use Byte read if Data Count is 0, 1, 2, 3, 4, 5, 6, 7
+ //
+ for (Index = 0; Index < SpiDataCount; Index++) {
+ Buffer[Index] = MmioRead8 (PchSpiBar0 + R_SPI_MEM_FDATA00 + Index);
+ }
+ } else {
+ //
+ // Use Dword read if Data Count is 8, 16, 24, 32, 40, 48, 56, 64
+ //
+ for (Index = 0; Index < SpiDataCount; Index += sizeof (UINT32)) {
+ *(UINT32 *) (Buffer + Index) = MmioRead32 (PchSpiBar0 + R_SPI_MEM_FDATA00 + Index);
+ }
+ }
+ }
+
+ HardwareSpiAddr += SpiDataCount;
+ Buffer += SpiDataCount;
+ ByteCount -= SpiDataCount;
+ } while (ByteCount > 0);
+
+SendSpiCmdEnd:
+ //
+ // Restore SPI controller state
+ //
+ if (RestoreState) {
+ if (HsfscFdoneSave) {
+ SetHsfscFdone (This, PchSpiBar0, HsfscFcerrSave);
+ }
+ MmioAndThenOr32 (
+ PchSpiBar0 + R_SPI_MEM_HSFSC,
+ (UINT32) ~(B_SPI_MEM_HSFSC_SAVE_MASK |
+ B_SPI_MEM_HSFSC_SAF_CE | // This bit clears when set to 1, ensure 0 is written
+ B_SPI_MEM_HSFSC_SAF_LE | // This bit clears when set to 1, ensure 0 is written
+ B_SPI_MEM_HSFSC_SAF_DLE | // This bit clears when set to 1, ensure 0 is written
+ B_SPI_MEM_HSFSC_SAF_ERROR | // This bit clears when set to 1, ensure 0 is written
+ B_SPI_MEM_HSFSC_AEL | // This bit clears when set to 1, ensure 0 is written
+ B_SPI_MEM_HSFSC_FCERR | // This bit clears when set to 1, ensure 0 is written
+ B_SPI_MEM_HSFSC_FDONE), // This bit clears when set to 1, ensure 0 is written
+ HsfscSave
+ );
+ MmioWrite32 (PchSpiBar0 + R_SPI_MEM_FADDR, FaddrSave);
+ for (Index = 0; Index < 64; Index += sizeof (UINT32)) {
+ MmioWrite32 (PchSpiBar0 + R_SPI_MEM_FDATA00 + Index, FdataSave[Index >> 2]);
+ }
+ }
+
+ //
+ // Restore the settings for SPI Prefetching and Caching and enable BIOS Write Protect
+ //
+ if ((FlashCycleType == FlashCycleWrite) ||
+ (FlashCycleType == FlashCycleErase)) {
+ EnableBiosWriteProtect ();
+ PciSegmentAndThenOr8 (
+ SpiBaseAddress + R_SPI_CFG_BC,
+ (UINT8) ~B_SPI_CFG_BC_SRC,
+ BiosCtlSave
+ );
+ }
+ ReleaseSpiBar0 (SpiInstance);
+
+ //
+ // Restore SMIs.
+ //
+ IoWrite32 ((UINTN) (ABase + R_ACPI_IO_SMI_EN), SmiEnSave);
+
+ return Status;
+}
+
+/**
+ Read data from the flash part.
+
+ @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
+ @param[in] FlashRegionType The Flash Region type for flash cycle which is listed in the Descriptor.
+ @param[in] Address The Flash Linear Address must fall within a region for which BIOS has access permissions.
+ @param[in] ByteCount Number of bytes in the data portion of the SPI cycle.
+ @param[out] Buffer The Pointer to caller-allocated buffer containing the dada received.
+ It is the caller's responsibility to make sure Buffer is large enough for the total number of bytes read.
+
+ @retval EFI_SUCCESS Command succeed.
+ @retval EFI_INVALID_PARAMETER The parameters specified are not valid.
+ @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
+**/
+EFI_STATUS
+EFIAPI
+SpiProtocolFlashRead (
+ IN PCH_SPI_PROTOCOL *This,
+ IN FLASH_REGION_TYPE FlashRegionType,
+ IN UINT32 Address,
+ IN UINT32 ByteCount,
+ OUT UINT8 *Buffer
+ )
+{
+ EFI_STATUS Status;
+
+ //
+ // Sends the command to the SPI interface to execute.
+ //
+ Status = SendSpiCmd (
+ This,
+ FlashRegionType,
+ FlashCycleRead,
+ Address,
+ ByteCount,
+ Buffer
+ );
+ return Status;
+}
+
+/**
+ Write data to the flash part.
+
+ @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
+ @param[in] FlashRegionType The Flash Region type for flash cycle which is listed in the Descriptor.
+ @param[in] Address The Flash Linear Address must fall within a region for which BIOS has access permissions.
+ @param[in] ByteCount Number of bytes in the data portion of the SPI cycle.
+ @param[in] Buffer Pointer to caller-allocated buffer containing the data sent during the SPI cycle.
+
+ @retval EFI_SUCCESS Command succeed.
+ @retval EFI_INVALID_PARAMETER The parameters specified are not valid.
+ @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
+**/
+EFI_STATUS
+EFIAPI
+SpiProtocolFlashWrite (
+ IN PCH_SPI_PROTOCOL *This,
+ IN FLASH_REGION_TYPE FlashRegionType,
+ IN UINT32 Address,
+ IN UINT32 ByteCount,
+ IN UINT8 *Buffer
+ )
+{
+ EFI_STATUS Status;
+
+ //
+ // Sends the command to the SPI interface to execute.
+ //
+ Status = SendSpiCmd (
+ This,
+ FlashRegionType,
+ FlashCycleWrite,
+ Address,
+ ByteCount,
+ Buffer
+ );
+ return Status;
+}
+
+/**
+ Erase some area on the flash part.
+
+ @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
+ @param[in] FlashRegionType The Flash Region type for flash cycle which is listed in the Descriptor.
+ @param[in] Address The Flash Linear Address must fall within a region for which BIOS has access permissions.
+ @param[in] ByteCount Number of bytes in the data portion of the SPI cycle.
+
+ @retval EFI_SUCCESS Command succeed.
+ @retval EFI_INVALID_PARAMETER The parameters specified are not valid.
+ @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
+**/
+EFI_STATUS
+EFIAPI
+SpiProtocolFlashErase (
+ IN PCH_SPI_PROTOCOL *This,
+ IN FLASH_REGION_TYPE FlashRegionType,
+ IN UINT32 Address,
+ IN UINT32 ByteCount
+ )
+{
+ EFI_STATUS Status;
+
+ //
+ // Sends the command to the SPI interface to execute.
+ //
+ Status = SendSpiCmd (
+ This,
+ FlashRegionType,
+ FlashCycleErase,
+ Address,
+ ByteCount,
+ NULL
+ );
+ return Status;
+}
+
+/**
+ Read SFDP data from the flash part.
+
+ @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
+ @param[in] ComponentNumber The Componen Number for chip select
+ @param[in] Address The starting byte address for SFDP data read.
+ @param[in] ByteCount Number of bytes in SFDP data portion of the SPI cycle
+ @param[out] SfdpData The Pointer to caller-allocated buffer containing the SFDP data received
+ It is the caller's responsibility to make sure Buffer is large enough for the total number of bytes read
+
+ @retval EFI_SUCCESS Command succeed.
+ @retval EFI_INVALID_PARAMETER The parameters specified are not valid.
+ @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
+ @retval EFI_UNSUPPORTED Unsupported operation with SAF Mode enabled
+**/
+EFI_STATUS
+EFIAPI
+SpiProtocolFlashReadSfdp (
+ IN PCH_SPI_PROTOCOL *This,
+ IN UINT8 ComponentNumber,
+ IN UINT32 Address,
+ IN UINT32 ByteCount,
+ OUT UINT8 *SfdpData
+ )
+{
+ return EFI_SUCCESS;
+}
+
+/**
+ Read Jedec Id from the flash part.
+
+ @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
+ @param[in] ComponentNumber The Componen Number for chip select
+ @param[in] ByteCount Number of bytes in JedecId data portion of the SPI cycle, the data size is 3 typically
+ @param[out] JedecId The Pointer to caller-allocated buffer containing JEDEC ID received
+ It is the caller's responsibility to make sure Buffer is large enough for the total number of bytes read.
+
+ @retval EFI_SUCCESS Command succeed.
+ @retval EFI_INVALID_PARAMETER The parameters specified are not valid.
+ @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
+ @retval EFI_UNSUPPORTED Unsupported operation with SAF Mode enabled
+**/
+EFI_STATUS
+EFIAPI
+SpiProtocolFlashReadJedecId (
+ IN PCH_SPI_PROTOCOL *This,
+ IN UINT8 ComponentNumber,
+ IN UINT32 ByteCount,
+ OUT UINT8 *JedecId
+ )
+{
+ return EFI_SUCCESS;
+}
+
+/**
+ Write the status register in the flash part.
+
+ @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
+ @param[in] ByteCount Number of bytes in Status data portion of the SPI cycle, the data size is 1 typically
+ @param[in] StatusValue The Pointer to caller-allocated buffer containing the value of Status register writing
+
+ @retval EFI_SUCCESS Command succeed.
+ @retval EFI_INVALID_PARAMETER The parameters specified are not valid.
+ @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
+ @retval EFI_UNSUPPORTED Unsupported operation with SAF Mode enabled
+**/
+EFI_STATUS
+EFIAPI
+SpiProtocolFlashWriteStatus (
+ IN PCH_SPI_PROTOCOL *This,
+ IN UINT32 ByteCount,
+ IN UINT8 *StatusValue
+ )
+{
+ return EFI_SUCCESS;
+}
+
+/**
+ Read status register in the flash part.
+
+ @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
+ @param[in] ByteCount Number of bytes in Status data portion of the SPI cycle, the data size is 1 typically
+ @param[out] StatusValue The Pointer to caller-allocated buffer containing the value of Status register received.
+
+ @retval EFI_SUCCESS Command succeed.
+ @retval EFI_INVALID_PARAMETER The parameters specified are not valid.
+ @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
+ @retval EFI_UNSUPPORTED Unsupported operation with SAF Mode enabled
+**/
+EFI_STATUS
+EFIAPI
+SpiProtocolFlashReadStatus (
+ IN PCH_SPI_PROTOCOL *This,
+ IN UINT32 ByteCount,
+ OUT UINT8 *StatusValue
+ )
+{
+ return EFI_SUCCESS;
+}
+
+/**
+ Get the SPI region base and size, based on the enum type
+
+ @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
+ @param[in] FlashRegionType The Flash Region type for for the base address which is listed in the Descriptor.
+ @param[out] BaseAddress The Flash Linear Address for the Region 'n' Base
+ @param[out] RegionSize The size for the Region 'n'
+
+ @retval EFI_SUCCESS Read success
+ @retval EFI_INVALID_PARAMETER Invalid region type given
+ @retval EFI_DEVICE_ERROR The region is not used
+**/
+EFI_STATUS
+EFIAPI
+SpiProtocolGetRegionAddress (
+ IN PCH_SPI_PROTOCOL *This,
+ IN FLASH_REGION_TYPE FlashRegionType,
+ OUT UINT32 *BaseAddress,
+ OUT UINT32 *RegionSize
+ )
+{
+ SPI_INSTANCE *SpiInstance;
+ UINTN PchSpiBar0;
+ UINT32 ReadValue;
+
+ SpiInstance = SPI_INSTANCE_FROM_SPIPROTOCOL (This);
+
+ if (FlashRegionType >= FlashRegionMax) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ if (FlashRegionType == FlashRegionAll) {
+ *BaseAddress = 0;
+ *RegionSize = SpiInstance->TotalFlashSize;
+ return EFI_SUCCESS;
+ }
+
+ PchSpiBar0 = AcquireSpiBar0 (SpiInstance);
+
+ ReadValue = MmioRead32 (PchSpiBar0 + (R_SPI_MEM_FREG0_FLASHD + (S_SPI_MEM_FREGX * ((UINT32) FlashRegionType))));
+
+ ReleaseSpiBar0 (SpiInstance);
+
+ //
+ // If the region is not used, the Region Base is 7FFFh and Region Limit is 0000h
+ //
+ if (ReadValue == B_SPI_MEM_FREGX_BASE_MASK) {
+ return EFI_DEVICE_ERROR;
+ }
+ *BaseAddress = ((ReadValue & B_SPI_MEM_FREGX_BASE_MASK) >> N_SPI_MEM_FREGX_BASE) <<
+ N_SPI_MEM_FREGX_BASE_REPR;
+ //
+ // Region limit address Bits[11:0] are assumed to be FFFh
+ //
+ *RegionSize = ((((ReadValue & B_SPI_MEM_FREGX_LIMIT_MASK) >> N_SPI_MEM_FREGX_LIMIT) + 1) <<
+ N_SPI_MEM_FREGX_LIMIT_REPR) - *BaseAddress;
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Read PCH Soft Strap Values
+
+ @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
+ @param[in] SoftStrapAddr PCH Soft Strap address offset from FPSBA.
+ @param[in] ByteCount Number of bytes in SoftStrap data portion of the SPI cycle
+ @param[out] SoftStrapValue The Pointer to caller-allocated buffer containing PCH Soft Strap Value.
+ If the value of ByteCount is 0, the data type of SoftStrapValue should be UINT16 and SoftStrapValue will be PCH Soft Strap Length
+ It is the caller's responsibility to make sure Buffer is large enough for the total number of bytes read.
+
+ @retval EFI_SUCCESS Command succeed.
+ @retval EFI_INVALID_PARAMETER The parameters specified are not valid.
+ @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
+**/
+EFI_STATUS
+EFIAPI
+SpiProtocolReadPchSoftStrap (
+ IN PCH_SPI_PROTOCOL *This,
+ IN UINT32 SoftStrapAddr,
+ IN UINT32 ByteCount,
+ OUT VOID *SoftStrapValue
+ )
+{
+ return EFI_SUCCESS;
+}
+
+/**
+ Read CPU Soft Strap Values
+
+ @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
+ @param[in] SoftStrapAddr CPU Soft Strap address offset from FCPUSBA.
+ @param[in] ByteCount Number of bytes in SoftStrap data portion of the SPI cycle.
+ @param[out] SoftStrapValue The Pointer to caller-allocated buffer containing CPU Soft Strap Value.
+ If the value of ByteCount is 0, the data type of SoftStrapValue should be UINT16 and SoftStrapValue will be PCH Soft Strap Length
+ It is the caller's responsibility to make sure Buffer is large enough for the total number of bytes read.
+
+ @retval EFI_SUCCESS Command succeed.
+ @retval EFI_INVALID_PARAMETER The parameters specified are not valid.
+ @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
+**/
+EFI_STATUS
+EFIAPI
+SpiProtocolReadCpuSoftStrap (
+ IN PCH_SPI_PROTOCOL *This,
+ IN UINT32 SoftStrapAddr,
+ IN UINT32 ByteCount,
+ OUT VOID *SoftStrapValue
+ )
+{
+ return EFI_SUCCESS;
+}
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/Smm/Spi.c b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/Smm/Spi.c
new file mode 100644
index 0000000000..2dd80eba7c
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/Smm/Spi.c
@@ -0,0 +1,387 @@
+/** @file
+ PCH SPI SMM Driver implements the SPI Host Controller Compatibility Interface.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <Library/IoLib.h>
+#include <Library/DebugLib.h>
+#include <Library/UefiDriverEntryPoint.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/BaseLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/SmmServicesTableLib.h>
+#include <Library/PciSegmentLib.h>
+#include <Protocol/Spi.h>
+#include <Protocol/SmmCpu.h>
+#include <Library/SpiCommonLib.h>
+#include <PchReservedResources.h>
+#include <Library/PchPciBdfLib.h>
+#include <IndustryStandard/Pci30.h>
+#include <Register/PchRegs.h>
+#include <Register/SpiRegs.h>
+
+//
+// Global variables
+//
+GLOBAL_REMOVE_IF_UNREFERENCED SPI_INSTANCE *mSpiInstance;
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_SMM_CPU_PROTOCOL *mSmmCpuProtocol;
+//
+// mPchSpiResvMmioAddr keeps the reserved MMIO range assigned to SPI.
+// In SMM it always set back the reserved MMIO address to SPI BAR0 to ensure the MMIO range
+// won't overlap with SMRAM range, and trusted.
+//
+GLOBAL_REMOVE_IF_UNREFERENCED UINT32 mSpiResvMmioAddr;
+//
+// mPchSpiSavedMmioAddr keeps the MMIO range assigned to SPI by PCI enumeration.
+// In SMM this is used to restore the original value for SPI BAR0 after finishing
+// commands to the SPI controller.
+//
+GLOBAL_REMOVE_IF_UNREFERENCED UINT32 mSpiSavedMmioAddr;
+//
+// mPchSpiBar0RefCount stores the reference count for SPI BAR0.
+//
+GLOBAL_REMOVE_IF_UNREFERENCED UINT32 mPchSpiBar0RefCount;
+//
+// mPchSpiSavedPciCmdReg stores the PCI command register state at the start of the
+// SPI transaction. This is used to restore the original PCI command register
+// state after finishing commands to the SPI controller.
+//
+GLOBAL_REMOVE_IF_UNREFERENCED UINT8 mPchSpiSavedPciCmdReg;
+GLOBAL_REMOVE_IF_UNREFERENCED BOOLEAN mBootServiceExited;
+
+/**
+ This function is invoked at ExitBootServices()
+
+ @param[in] Protocol Protocol unique ID.
+ @param[in] Interface Interface instance.
+ @param[in] Handle The handle on which the interface is installed..
+
+ @retval Status.
+**/
+EFI_STATUS
+EFIAPI
+SpiExitBootServicesCallback (
+ IN CONST EFI_GUID *Protocol,
+ IN VOID *Interface,
+ IN EFI_HANDLE Handle
+ )
+{
+ mBootServiceExited = TRUE;
+ return EFI_SUCCESS;
+}
+
+/**
+ <b>SPI Runtime SMM Module Entry Point</b>\n
+ - <b>Introduction</b>\n
+ The SPI SMM module provide a standard way for other modules to use the PCH SPI Interface in SMM.
+
+ - @pre
+ - EFI_SMM_BASE2_PROTOCOL
+ - Documented in System Management Mode Core Interface Specification .
+
+ - @result
+ The SPI SMM driver produces @link _PCH_SPI_PROTOCOL PCH_SPI_PROTOCOL @endlink with GUID
+ gPchSmmSpiProtocolGuid which is different from SPI RUNTIME driver.
+
+ - <b>Integration Check List</b>\n
+ - This driver supports Descriptor Mode only.
+ - This driver supports Hardware Sequence only.
+ - When using SMM SPI Protocol to perform flash access in an SMI handler,
+ and the SMI occurrence is asynchronous to normal mode code execution,
+ proper synchronization mechanism must be applied, e.g. disable SMI before
+ the normal mode SendSpiCmd() starts and re-enable SMI after
+ the normal mode SendSpiCmd() completes.
+ @note The implementation of SendSpiCmd() uses GBL_SMI_EN in
+ SMI_EN register (ABase + 30h) to disable and enable SMIs. But this may
+ not be effective as platform may well set the SMI_LOCK bit (i.e., PMC PCI Offset A0h [4]).
+ So the synchronization at caller level is likely needed.
+
+ @param[in] ImageHandle Image handle of this driver.
+ @param[in] SystemTable Global system service table.
+
+ @retval EFI_SUCCESS Initialization complete.
+ @exception EFI_UNSUPPORTED The chipset is unsupported by this driver.
+ @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize the driver.
+ @retval EFI_DEVICE_ERROR Device error, driver exits abnormally.
+**/
+EFI_STATUS
+EFIAPI
+InstallPchSpi (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUS Status;
+ VOID *Registration;
+
+ //
+ // Init PCH spi reserved MMIO address.
+ //
+ mSpiResvMmioAddr = PCH_SPI_BASE_ADDRESS;
+ mSpiSavedMmioAddr = 0;
+ mPchSpiBar0RefCount = 0;
+ mPchSpiSavedPciCmdReg = 0;
+ mBootServiceExited = FALSE;
+
+ ///
+ /// Allocate pool for SPI protocol instance
+ ///
+ Status = gSmst->SmmAllocatePool (
+ EfiRuntimeServicesData, /// MemoryType don't care
+ sizeof (SPI_INSTANCE),
+ (VOID **) &mSpiInstance
+ );
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ if (mSpiInstance == NULL) {
+ return EFI_OUT_OF_RESOURCES;
+ }
+
+ ZeroMem ((VOID *) mSpiInstance, sizeof (SPI_INSTANCE));
+ ///
+ /// Initialize the SPI protocol instance
+ ///
+ Status = SpiProtocolConstructor (mSpiInstance);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ //
+ // Register ExitBootServices callback
+ //
+ Status = gSmst->SmmRegisterProtocolNotify (
+ &gEdkiiSmmExitBootServicesProtocolGuid,
+ SpiExitBootServicesCallback,
+ &Registration
+ );
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ //
+ // Install the SMM PCH_SPI_PROTOCOL interface
+ //
+ Status = gSmst->SmmInstallProtocolInterface (
+ &(mSpiInstance->Handle),
+ &gPchSmmSpiProtocolGuid,
+ EFI_NATIVE_INTERFACE,
+ &(mSpiInstance->SpiProtocol)
+ );
+ if (EFI_ERROR (Status)) {
+ gSmst->SmmFreePool (mSpiInstance);
+ return EFI_DEVICE_ERROR;
+ }
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Acquire PCH SPI MMIO address.
+ It is not expected for this BAR0 to change because the SPI device is usually
+ hidden from the OS. But if it is ever different from the preallocated address,
+ reassign it back. In SMM, BAR0 will always be overwritten and the reserved
+ MMIO range for SPI will be returned.
+
+ @param[in] SpiInstance Pointer to SpiInstance to initialize
+
+ @retval PchSpiBar0 return SPI MMIO address
+**/
+UINTN
+AcquireSpiBar0 (
+ IN SPI_INSTANCE *SpiInstance
+ )
+{
+ UINT32 SpiBar0;
+ UINT8 PciCmdReg;
+
+ //
+ // Save original SPI physical MMIO address
+ //
+ SpiBar0 = PciSegmentRead32 (SpiInstance->PchSpiBase + R_SPI_CFG_BAR0) & ~(B_SPI_CFG_BAR0_MASK);
+ PciCmdReg = PciSegmentRead8 (SpiInstance->PchSpiBase + PCI_COMMAND_OFFSET);
+
+ if ((SpiBar0 != mSpiResvMmioAddr) || ((PciCmdReg & EFI_PCI_COMMAND_MEMORY_SPACE) == 0)) {
+ //
+ // Save PCI command register state and BAR value assigned by PCI enumeration
+ //
+ mPchSpiSavedPciCmdReg = PciCmdReg;
+ mSpiSavedMmioAddr = SpiBar0;
+
+ //
+ // Temporary disable MSE, and override with SPI reserved MMIO address, then enable MSE.
+ //
+ PciSegmentAnd8 (SpiInstance->PchSpiBase + PCI_COMMAND_OFFSET, (UINT8) ~EFI_PCI_COMMAND_MEMORY_SPACE);
+ PciSegmentWrite32 (SpiInstance->PchSpiBase + R_SPI_CFG_BAR0, mSpiResvMmioAddr);
+ PciSegmentOr8 (SpiInstance->PchSpiBase + PCI_COMMAND_OFFSET, EFI_PCI_COMMAND_MEMORY_SPACE);
+ } else if (mPchSpiBar0RefCount == 0) {
+ mSpiSavedMmioAddr = 0;
+ mPchSpiSavedPciCmdReg = 0;
+ }
+ mPchSpiBar0RefCount++;
+
+ //
+ // SPIBAR0 will be different before and after PCI enum so need to get it from SPI BAR0 reg.
+ //
+ return mSpiResvMmioAddr;
+}
+
+/**
+ Release PCH SPI MMIO address. If AcquireSpiBar0() previously overwrote the
+ value of BAR0, this function will restore the original value assigned by PCI
+ enumeration
+
+ @param[in] SpiInstance Pointer to SpiInstance to initialize
+
+ @retval None
+**/
+VOID
+ReleaseSpiBar0 (
+ IN SPI_INSTANCE *SpiInstance
+ )
+{
+ //
+ // Reference counting is used here because multiple nested calls to
+ // AcquireSpiBar0()/ReleaseSpiBar0() will cause SpiBar0 to be reprogrammed
+ // back to the original value before access to the SPI controller is done.
+ // Reference counting ensures that the BAR is not restored until after access
+ // is complete.
+ //
+ if (mPchSpiBar0RefCount <= 1) {
+ mPchSpiBar0RefCount = 0;
+ if (mSpiSavedMmioAddr != 0) {
+ //
+ // Temporary disable MSE, restore the original SPI MMIO address, then
+ // restore PCI command register state
+ //
+ PciSegmentAnd8 (SpiInstance->PchSpiBase + PCI_COMMAND_OFFSET, (UINT8)~EFI_PCI_COMMAND_MEMORY_SPACE);
+ PciSegmentWrite32 (SpiInstance->PchSpiBase + R_SPI_CFG_BAR0, mSpiSavedMmioAddr);
+ PciSegmentWrite8 (SpiInstance->PchSpiBase + PCI_COMMAND_OFFSET, mPchSpiSavedPciCmdReg);
+
+ //
+ // Clear saved state
+ //
+ mSpiSavedMmioAddr = 0;
+ mPchSpiSavedPciCmdReg = 0;
+ }
+ } else {
+ mPchSpiBar0RefCount--;
+ }
+}
+
+/**
+ This function is a hook for Spi to disable BIOS Write Protect
+
+ @retval EFI_SUCCESS The protocol instance was properly initialized
+ @retval EFI_ACCESS_DENIED The BIOS Region can only be updated in SMM phase
+
+**/
+EFI_STATUS
+EFIAPI
+DisableBiosWriteProtect (
+ VOID
+ )
+{
+ UINT64 SpiBaseAddress;
+
+ SpiBaseAddress = SpiPciCfgBase ();
+ // Write clear BC_SYNC_SS prior to change WPD from 0 to 1.
+ //
+ PciSegmentOr8 (
+ SpiBaseAddress + R_SPI_CFG_BC + 1,
+ (B_SPI_CFG_BC_SYNC_SS >> 8)
+ );
+ ///
+ /// Set BIOSWE bit (SPI PCI Offset DCh [0]) = 1b
+ /// Enable the access to the BIOS space for both read and write cycles
+ ///
+ PciSegmentOr8 (
+ SpiBaseAddress + R_SPI_CFG_BC,
+ B_SPI_CFG_BC_WPD
+ );
+
+ return EFI_SUCCESS;
+}
+
+/**
+ This function is a hook for Spi to enable BIOS Write Protect
+**/
+VOID
+EFIAPI
+EnableBiosWriteProtect (
+ VOID
+ )
+{
+ UINT64 SpiBaseAddress;
+
+ SpiBaseAddress = SpiPciCfgBase ();
+ ///
+ /// Clear BIOSWE bit (SPI PCI Offset DCh [0]) = 0b
+ /// Disable the access to the BIOS space for write cycles
+ ///
+ PciSegmentAnd8 (
+ SpiBaseAddress + R_SPI_CFG_BC,
+ (UINT8) (~B_SPI_CFG_BC_WPD)
+ );
+
+}
+
+/**
+ Check if it's granted to do flash write.
+
+ @retval TRUE It's secure to do flash write.
+ @retval FALSE It's not secure to do flash write.
+**/
+BOOLEAN
+IsSpiFlashWriteGranted (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+ UINT32 CpuIndex;
+ UINT64 ProcessorId;
+
+ if (mSmmCpuProtocol == NULL) {
+ Status = gSmst->SmmLocateProtocol (&gEfiSmmCpuProtocolGuid, NULL, (VOID **)&mSmmCpuProtocol);
+ ASSERT_EFI_ERROR (Status);
+ if (mSmmCpuProtocol == NULL) {
+ return TRUE;
+ }
+ }
+
+ for (CpuIndex = 0; CpuIndex < gSmst->NumberOfCpus; CpuIndex++) {
+ Status = mSmmCpuProtocol->ReadSaveState (
+ mSmmCpuProtocol,
+ sizeof (ProcessorId),
+ EFI_SMM_SAVE_STATE_REGISTER_PROCESSOR_ID,
+ CpuIndex,
+ &ProcessorId
+ );
+ //
+ // If the processor is in SMM at the time the SMI occurred,
+ // it will return success. Otherwise, EFI_NOT_FOUND is returned.
+ //
+ if (EFI_ERROR (Status)) {
+ return FALSE;
+ }
+ }
+
+ return TRUE;
+}
+
+/**
+ Check if a save and restore of the SPI controller state is necessary
+
+ @retval TRUE It's necessary to save and restore SPI controller state
+ @retval FALSE It's not necessary to save and restore SPI controller state
+**/
+BOOLEAN
+IsSpiControllerSaveRestoreEnabled (
+ VOID
+ )
+{
+ return mBootServiceExited;
+}
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/Smm/SpiSmm.inf b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/Smm/SpiSmm.inf
new file mode 100644
index 0000000000..78913423fb
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/Smm/SpiSmm.inf
@@ -0,0 +1,46 @@
+## @file
+# Component description file for the SPI SMM driver.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+
+[Defines]
+INF_VERSION = 0x00010017
+BASE_NAME = SpiSmm
+FILE_GUID = 27F4917B-A707-4aad-9676-26DF168CBF0D
+VERSION_STRING = 1.0
+MODULE_TYPE = DXE_SMM_DRIVER
+PI_SPECIFICATION_VERSION = 1.10
+ENTRY_POINT = InstallPchSpi
+
+
+[LibraryClasses]
+DebugLib
+IoLib
+UefiDriverEntryPoint
+UefiBootServicesTableLib
+BaseLib
+SmmServicesTableLib
+SpiCommonLib
+PchPciBdfLib
+
+[Packages]
+MdePkg/MdePkg.dec
+AlderlakeSiliconPkg/SiPkg.dec
+
+
+[Sources]
+Spi.c
+
+
+[Protocols]
+gPchSmmSpiProtocolGuid ## PRODUCES
+gEfiSmmCpuProtocolGuid ## CONSUMES
+gEdkiiSmmExitBootServicesProtocolGuid ## CONSUMES
+
+
+[Depex]
+gEfiSmmBase2ProtocolGuid AND # This is for SmmServicesTableLib
+gEfiSmmCpuProtocolGuid
--
2.36.1.windows.1
-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#108690): https://edk2.groups.io/g/devel/message/108690
Mute This Topic: https://groups.io/mt/101373948/7686176
Group Owner: devel+owner@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [rebecca@openfw.io]
-=-=-=-=-=-=-=-=-=-=-=-
^ permalink raw reply related [flat|nested] 41+ messages in thread
* Re: [edk2-devel] [PATCH v2 05/10] AlderlakeSiliconPkg/Include: Add ConfigBlock headers
2023-09-15 4:45 ` [edk2-devel] [PATCH v2 05/10] AlderlakeSiliconPkg/Include: Add ConfigBlock headers Saloni Kasbekar
@ 2023-09-15 5:42 ` Chaganty, Rangasai V
2023-09-15 13:28 ` Chuang, Rosen
2023-09-15 23:56 ` Nate DeSimone
1 sibling, 1 reply; 41+ messages in thread
From: Chaganty, Rangasai V @ 2023-09-15 5:42 UTC (permalink / raw)
To: Kasbekar, Saloni, devel@edk2.groups.io
Cc: Desimone, Nathaniel L, Chuang, Rosen
Reviewed-by: Sai Chaganty <rangasai.v.chaganty@intel.com>
-----Original Message-----
From: Kasbekar, Saloni <saloni.kasbekar@intel.com>
Sent: Thursday, September 14, 2023 9:46 PM
To: devel@edk2.groups.io
Cc: Kasbekar, Saloni <saloni.kasbekar@intel.com>; Chaganty, Rangasai V <rangasai.v.chaganty@intel.com>; Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>; Chuang, Rosen <rosen.chuang@intel.com>
Subject: [PATCH v2 05/10] AlderlakeSiliconPkg/Include: Add ConfigBlock headers
Adds the header includes for the ConfigBlocks
Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Rosen Chuang <rosen.chuang@intel.com>
Signed-off-by: Saloni Kasbekar <saloni.kasbekar@intel.com>
---
.../CpuPcieRp/Gen3/CpuPcieConfigGen3.h | 48 ++
.../CpuPcieRp/Gen4/CpuPcieConfig.h | 240 ++++++++
.../Include/ConfigBlock/Espi/LpcConfig.h | 38 ++
.../Include/ConfigBlock/Fivr/FivrConfig.h | 183 ++++++
.../Include/ConfigBlock/Gpio/GpioDevConfig.h | 37 ++
.../Graphics/Gen12/GraphicsConfig.h | 212 +++++++
.../HostBridge/Ver1/HostBridgeConfig.h | 58 ++
.../ConfigBlock/Itss/InterruptConfig.h | 38 ++
.../ConfigBlock/Memory/Ver2/MemoryConfig.h | 551 ++++++++++++++++++
.../Include/ConfigBlock/PchDmi/PchDmiConfig.h | 65 +++
.../PcieRp/PchPcieRp/PchPcieRpConfig.h | 180 ++++++
.../Include/ConfigBlock/PcieRp/PcieConfig.h | 408 +++++++++++++
.../ConfigBlock/PcieRp/PciePreMemConfig.h | 36 ++
.../Include/ConfigBlock/Pmc/AdrConfig.h | 76 +++
.../Include/ConfigBlock/Pmc/PmConfig.h | 86 +++
.../Include/ConfigBlock/Rtc/RtcConfig.h | 37 ++
.../ConfigBlock/SerialIo/SerialIoConfig.h | 33 ++
.../Include/ConfigBlock/SiConfig.h | 105 ++++
.../Include/ConfigBlock/SiPreMemConfig.h | 63 ++
.../Include/ConfigBlock/Smbus/SmbusConfig.h | 49 ++
.../ConfigBlock/Spi/FlashProtectionConfig.h | 54 ++
.../Include/ConfigBlock/Tcss/TcssPeiConfig.h | 71 +++
.../Include/ConfigBlock/Vmd/VmdPeiConfig.h | 60 ++
.../Include/ConfigBlock/Wdt/WatchDogConfig.h | 30 +
24 files changed, 2758 insertions(+)
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/CpuPcieRp/Gen3/CpuPcieConfigGen3.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/CpuPcieRp/Gen4/CpuPcieConfig.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Espi/LpcConfig.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Fivr/FivrConfig.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Gpio/GpioDevConfig.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Graphics/Gen12/GraphicsConfig.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/HostBridge/Ver1/HostBridgeConfig.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Itss/InterruptConfig.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Memory/Ver2/MemoryConfig.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/PchDmi/PchDmiConfig.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/PcieRp/PchPcieRp/PchPcieRpConfig.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/PcieRp/PcieConfig.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/PcieRp/PciePreMemConfig.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Pmc/AdrConfig.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Pmc/PmConfig.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Rtc/RtcConfig.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/SerialIo/SerialIoConfig.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/SiConfig.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/SiPreMemConfig.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Smbus/SmbusConfig.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Spi/FlashProtectionConfig.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Tcss/TcssPeiConfig.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Vmd/VmdPeiConfig.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Wdt/WatchDogConfig.h
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/CpuPcieRp/Gen3/CpuPcieConfigGen3.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/CpuPcieRp/Gen3/CpuPcieConfigGen3.h
new file mode 100644
index 0000000000..5b437c8311
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/CpuPcieRp/Gen3/CpuPcieConfigGen3.h
@@ -0,0 +1,48 @@
+/** @file
+Pcie root port policy
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _CPU_PCIE_CONFIG_GEN3_H_
+#define _CPU_PCIE_CONFIG_GEN3_H_
+
+#include <Library/GpioLib.h>
+#include <Library/CpuPcieInfoFruLib.h>
+#include <PcieConfig.h>
+#include <ConfigBlock.h>
+#include <Register/SaRegsHostBridge.h>
+
+#pragma pack(push, 1)
+
+
+#define L0_SET BIT0
+#define L1_SET BIT1
+
+
+///
+/// SA GPIO Data Structure
+///
+typedef struct {
+ GPIO_PAD GpioPad; ///< Offset 0: GPIO Pad
+ UINT8 Value; ///< Offset 4: GPIO Value
+ UINT8 Rsvd0[3]; ///< Offset 5: Reserved for 4 bytes alignment
+ UINT32 Active : 1; ///< Offset 8: 0=Active Low; 1=Active High
+ UINT32 RsvdBits0 : 31;
+} SA_GPIO_INFO_PCIE;
+
+///
+/// SA Board PEG GPIO Info
+///
+typedef struct {
+ SA_GPIO_INFO_PCIE SaPeg0ResetGpio; ///< Offset 0: PEG0 PERST# GPIO assigned, must be a PCH GPIO pin
+ SA_GPIO_INFO_PCIE SaPeg3ResetGpio; ///< Offset 12: PEG3 PERST# GPIO assigned, must be a PCH GPIO pin
+ BOOLEAN GpioSupport; ///< Offset 24: 1=Supported; 0=Not Supported
+ UINT8 Rsvd0[3]; ///< Offset 25: Reserved for 4 bytes alignment
+} PEG_GPIO_DATA;
+
+
+#pragma pack (pop)
+
+#endif // _CPU_PCIE_CONFIG_GEN3_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/CpuPcieRp/Gen4/CpuPcieConfig.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/CpuPcieRp/Gen4/CpuPcieConfig.h
new file mode 100644
index 0000000000..999748d711
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/CpuPcieRp/Gen4/CpuPcieConfig.h
@@ -0,0 +1,240 @@
+/** @file
+ Pcie root port policy
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _CPU_PCIE_CONFIG_H_
+#define _CPU_PCIE_CONFIG_H_
+
+#include <Library/GpioLib.h>
+#include <Library/CpuPcieInfoFruLib.h>
+#include <PcieConfig.h>
+#include <ConfigBlock.h>
+#include <Register/SaRegsHostBridge.h>
+
+#pragma pack(push, 1)
+
+#define CPU_PCIE_RP_PREMEM_CONFIG_REVISION 1
+
+/**
+ Making any setup structure change after code frozen
+ will need to maintain backward compatibility, bump up
+ structure revision and update below history table\n
+ <b>Revision 1</b>: - Initial version.
+**/
+
+#define CPU_PCIE_CONFIG_REVISION 10
+
+#define L0_SET BIT0
+#define L1_SET BIT1
+
+/**
+ CPU PCIe Root Port Pre-Memory Configuration
+ Contains Root Port settings and capabilities
+ <b>Revision 1</b>: - Initial version.
+ <b>Revision 2</b>: - Adding Dekel Suqelch Workaround Setup Variable
+ <b>Revision 3</b>: - Deprecate Dekel Suqelch Workaround Setup Variable
+ <b>Revision 4</b>: - Adding New FOM Setup Variable
+ <b>Revision 5</b>: - Add CdrRelock Policy to CPU_PCIE_RP_PREMEM_CONFIG.
+**/
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Config Block Header
+ /**
+ Root Port enabling mask.
+ Bit0 presents RP1, Bit1 presents RP2, and so on.
+ 0: Disable; <b>1: Enable</b>.
+ **/
+ UINT32 RpEnabledMask;
+ /**
+ Assertion on Link Down GPIOs
+ - <b>Disabled</b> (0x0) : Disable assertion on Link Down GPIOs(Default)
+ - Enabled (0x1) : Enable assertion on Link Down GPIOs
+ **/
+ UINT8 LinkDownGpios;
+ /**
+ Enable ClockReq Messaging
+ - <b>Disabled</> (0x0) : Disable ClockReq Messaging(Default)
+ - Enabled (0x1) : Enable ClockReq Messaging
+ **/
+ UINT8 ClkReqMsgEnable;
+ /**
+ Dekel Recipe Workaround
+ <b>2</b>
+ 1=Minimal, 9=Maximum,
+ **/
+ UINT8 DekelSquelchWa; // Deprecated variable
+ UINT8 Rsvd0[1];
+ /**
+ Determines each PCIE Port speed capability.
+ <b>0: Auto</b>; 1: Gen1; 2: Gen2; 3: Gen3; 4: Gen4 (see: CPU_PCIE_SPEED)
+ **/
+ UINT8 PcieSpeed[CPU_PCIE_MAX_ROOT_PORTS];
+
+ /**
+ Enable ClockReq Messaging Policy is for all Rootports
+ - <b>Disabled</> (0x0) : Disable ClockReq Messaging(Default)
+ - Enabled (0x1) : Enable ClockReq Messaging
+ **/
+ UINT8 ClkReqMsgEnableRp[CPU_PCIE_MAX_ROOT_PORTS];
+ /**
+ To Enable/Disable New FOM
+ <b>0: Disable</b>; 1: Enable
+ **/
+ UINT8 NewFom[CPU_PCIE_MAX_ROOT_PORTS];
+ /**
+ To Enable/Disable CDR Relock
+ <b>0: Disable</b>; 1: Enable
+ **/
+ UINT8 CdrRelock[CPU_PCIE_MAX_ROOT_PORTS];
+} CPU_PCIE_RP_PREMEM_CONFIG;
+
+/**
+ Represent lane specific PCIe Gen3 equalization parameters.
+**/
+typedef struct {
+ UINT8 Cm; ///< Coefficient C-1
+ UINT8 Cp; ///< Coefficient C+1
+ UINT8 PegGen3RootPortPreset; ///< <b>(Test)</b> Used for programming PEG Gen3 preset values per lane. Range: 0-9, 8 is default for each lane
+ UINT8 PegGen3EndPointPreset; ///< <b>(Test)</b> Used for programming PEG Gen3 preset values per lane. Range: 0-9, 7 is default for each lane
+ UINT8 PegGen3EndPointHint; ///< <b>(Test)</b> Hint value per lane for the PEG Gen3 End Point. Range: 0-6, 2 is default for each lane
+ UINT8 PegGen4RootPortPreset; ///< <b>(Test)</b> Used for programming PEG Gen4 preset values per lane. Range: 0-9, 8 is default for each lane
+ UINT8 PegGen4EndPointPreset; ///< <b>(Test)</b> Used for programming PEG Gen4 preset values per lane. Range: 0-9, 7 is default for each lane
+ UINT8 PegGen4EndPointHint; ///< <b>(Test)</b> Hint value per lane for the PEG Gen4 End Point. Range: 0-6, 2 is default for each lane
+} CPU_PCIE_EQ_LANE_PARAM;
+
+/**
+ The CPU_PCI_ROOT_PORT_CONFIG describe the feature and capability of each CPU PCIe root port.
+**/
+typedef struct {
+
+ UINT32 ExtSync : 1; ///< Indicate whether the extended synch is enabled. <b>0: Disable</b>; 1: Enable.
+ UINT32 MultiVcEnabled : 1; ///< Multiple Virtual Channel. 0: Disable; <b>1: Enable</b>
+ UINT32 RsvdBits0 : 30; ///< Reserved bits
+ /**
+ PCIe Gen4 Equalization Method
+ - HwEq (0x1) : Hardware Equalization (Default)
+ - StaticEq (0x2) : Static Equalization
+ **/
+ UINT8 Gen4EqPh3Method;
+ UINT8 FomsCp; ///< FOM Score Board Control Policy
+ UINT8 RsvdBytes0[2]; ///< Reserved bytes
+
+ //
+ // Gen3 Equalization settings
+ //
+ UINT32 Gen3Uptp : 4; ///< <b>(Test)</b> Upstream Port Transmitter Preset used during Gen3 Link Equalization. Used for all lanes. Default is <b>7</b>.
+ UINT32 Gen3Dptp : 4; ///< <b>(Test)</b> Downstream Port Transmiter Preset used during Gen3 Link Equalization. Used for all lanes. Default is <b>7</b>.
+ //
+ // Gen4 Equalization settings
+ //
+ UINT32 Gen4Uptp : 4; ///< <b>(Test)</b> Upstream Port Transmitter Preset used during Gen4 Link Equalization. Used for all lanes. Default is <b>7</b>.
+ UINT32 Gen4Dptp : 4; ///< <b>(Test)</b> Downstream Port Transmiter Preset used during Gen4 Link Equalization. Used for all lanes. Default is <b>7</b>.
+ //
+ // Gen5 Equalization settings
+ //
+ UINT32 Gen5Uptp : 4; ///< <b>(Test)</b> Upstream Port Transmitter Preset used during Gen5 Link Equalization. Used for all lanes. Default is <b>5</b>.
+ UINT32 Gen5Dptp : 4; ///< <b>(Test)</b> Downstream Port Transmiter Preset used during Gen5 Link Equalization. Used for all lanes. Default is <b>7</b>.
+ UINT32 RsvdBits1 : 8; ///< Reserved Bits
+
+ PCIE_ROOT_PORT_COMMON_CONFIG PcieRpCommonConfig; ///< <b>(Test)</b> Includes policies which are common to both SA and PCH RootPort
+
+} CPU_PCIE_ROOT_PORT_CONFIG;
+
+typedef struct {
+ UINT8 PcieGen3PresetCoeffSelection; ///<Gen3 Preset or Coefficient Selection
+ UINT8 PcieGen4PresetCoeffSelection; ///<Gen4 Preset or Coefficient Selection
+ UINT8 PcieGen5PresetCoeffSelection; ///<Gen5 Preset or Coefficient Selection
+ UINT8 Func0LinkDisable; ///< Disable Func0 Port
+} CPU_PCIE_ROOT_PORT_CONFIG2;
+
+/**
+ The CPU_PCIE_CONFIG block describes the expected configuration of the CPU PCI Express controllers
+ <b>Revision 1< / b>:
+ -Initial version.
+ <b>Revision 2</b>:
+ - SlotSelection policy added
+ <b>Revision 3</b>
+ - Deprecate PegGen3ProgramStaticEq and PegGen4ProgramStaticEq
+ <b>Revision 4</b>:
+ - Deprecating SetSecuredRegisterLock
+ <b>Revision 5</b>:
+ - Moved ClockGating policy to PCIE_ROOT_PORT_COMMON_CONFIG
+ - Moved PowerGating policy to PCIE_ROOT_PORT_COMMON_CONFIG
+ - Deprecate VcEnabled policy
+ <b>Revision 7</b>:
+ - Deprecating Gen3PresetCoeffSelection and Gen4PresetCoeffSelection
+ <b>Revision 8</b>:
+ - Added Serl policy
+ <b>Revision 9</b>:
+ - Align revision with CPU_PCIE_CONFIG_REVISION value
+ <b>Revision 10</b>:
+ - Deprecate EqPh3LaneParam.Cm and EqPh3LaneParam.Cp
+**/
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Config Block Header
+ ///
+ /// These members describe the configuration of each SA PCIe root port.
+ ///
+ CPU_PCIE_ROOT_PORT_CONFIG RootPort[CPU_PCIE_MAX_ROOT_PORTS];
+ ///
+ /// Gen3 Equalization settings for physical PCIe lane, index 0 represents PCIe lane 1, etc.
+ /// Corresponding entries are used when root port EqPh3Method is PchPcieEqStaticCoeff (default).
+ ///
+ CPU_PCIE_EQ_LANE_PARAM EqPh3LaneParam[SA_PEG_MAX_LANE]; //@ Deprecated Policy
+ ///
+ /// List of coefficients used during equalization (applicable to both software and hardware EQ)
+ ///
+ PCIE_EQ_PARAM HwEqGen4CoeffList[PCIE_HWEQ_COEFFS_MAX]; //@ Deprecated Policy
+
+ PCIE_COMMON_CONFIG PcieCommonConfig; /// < <b>(Test)</b> Includes policies which are common to both SA and PCH PCIe
+
+ UINT32 FiaProgramming : 1; /// < Skip Fia Configuration and lock if enable
+ // Deprecated Policy
+ /**
+ <b>(Test)</b> Program PEG Gen3 EQ Phase1 Static Presets
+ - Disabled (0x0) : Disable EQ Phase1 Static Presets Programming
+ - <b>Enabled</b> (0x1) : Enable EQ Phase1 Static Presets Programming (Default)
+ **/
+ UINT32 PegGen3ProgramStaticEq : 1;
+
+ // Deprecated Policy
+ /**
+ <b>(Test)</b> Program PEG Gen4 EQ Phase1 Static Presets
+ - Disabled (0x0) : Disable EQ Phase1 Static Presets Programming
+ - <b>Enabled</b> (0x1) : Enable EQ Phase1 Static Presets Programming (Default)
+ **/
+ UINT32 PegGen4ProgramStaticEq : 1;
+ /**
+ <b>(Test)</b> Cpu Pcie Secure Register Lock
+ - Disabled (0x0)
+ - <b>Enabled</b> (0x1)
+ **/
+ UINT32 SetSecuredRegisterLock : 1; // Deprecated Policy
+ ///
+ /// This member allows to select between the PCI Express M2 or CEMx4 slot <b>1: PCIe M2</b>; 0: CEMx4 slot.
+ ///
+ UINT32 SlotSelection : 1;
+
+ UINT32 Serl : 1;
+
+ UINT32 RsvdBits0 : 26;
+
+ /**
+ PCIe device override table
+ The PCIe device table is being used to override PCIe device ASPM settings.
+ This is a pointer points to a 32bit address. And it's only used in PostMem phase.
+ Please refer to PCIE_DEVICE_OVERRIDE structure for the table.
+ Last entry VendorId must be 0.
+ The prototype of this policy is:
+ PCIE_DEVICE_OVERRIDE *PcieDeviceOverrideTablePtr;
+ **/
+ UINT32 PcieDeviceOverrideTablePtr;
+ CPU_PCIE_ROOT_PORT_CONFIG2 RootPort2[CPU_PCIE_MAX_ROOT_PORTS];
+ PCIE_COMMON_CONFIG2 PcieCommonConfig2;
+ } CPU_PCIE_CONFIG;
+
+#pragma pack (pop)
+
+#endif // _CPU_PCIE_CONFIG_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Espi/LpcConfig.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Espi/LpcConfig.h
new file mode 100644
index 0000000000..324facde78
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Espi/LpcConfig.h
@@ -0,0 +1,38 @@
+/** @file
+ Lpc policy
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _LPC_CONFIG_H_
+#define _LPC_CONFIG_H_
+
+#define PCH_LPC_PREMEM_CONFIG_REVISION 1
+extern EFI_GUID gLpcPreMemConfigGuid;
+
+#pragma pack (push,1)
+
+/**
+ This structure contains the policies which are related to LPC.
+**/
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Config Block Header
+ /**
+ Enhance the port 8xh decoding.
+ Original LPC only decodes one byte of port 80h, with this enhancement LPC can decode word or dword of port 80h-83h.
+ @note: this will occupy one LPC generic IO range register. While this is enabled, read from port 80h always return 0x00.
+ 0: Disable, <b>1: Enable</b>
+ **/
+ UINT32 EnhancePort8xhDecoding : 1;
+ /**
+ Hardware Autonomous Enable.
+ When enabled, LPC will automatically engage power gating when it has reached its idle condition.
+ 0: Disable, <b>1: Enable</b>
+ **/
+ UINT32 LpcPmHAE : 1;
+ UINT32 RsvdBits : 30; ///< Reserved bits
+} PCH_LPC_PREMEM_CONFIG;
+
+#pragma pack (pop)
+
+#endif // _LPC_CONFIG_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Fivr/FivrConfig.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Fivr/FivrConfig.h
new file mode 100644
index 0000000000..501e00c0e1
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Fivr/FivrConfig.h
@@ -0,0 +1,183 @@
+/** @file
+ PCH FIVR policy
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _FIVR_CONFIG_H_
+#define _FIVR_CONFIG_H_
+
+/**
+ <b>Revision 1</b>: - Initial version.
+**/
+#define PCH_FIVR_CONFIG_REVISION 1
+extern EFI_GUID gFivrConfigGuid;
+
+#pragma pack (push,1)
+
+/**
+ Rail support in S0ix and Sx
+ Settings other than FivrRailDisabled can be OR'ed
+**/
+typedef enum {
+ FivrRailDisabled = 0,
+ FivrRailInS0i1S0i2 = BIT0,
+ FivrRailInS0i3 = BIT1,
+ FivrRailInS3 = BIT2,
+ FivrRailInS4 = BIT3,
+ FivrRailInS5 = BIT4,
+ FivrRailInS0ix = FivrRailInS0i1S0i2 | FivrRailInS0i3,
+ FivrRailInSx = FivrRailInS3 | FivrRailInS4 | FivrRailInS5,
+ FivrRailAlwaysOn = FivrRailInS0ix | FivrRailInSx
+} FIVR_RAIL_SX_STATE;
+
+typedef enum {
+ FivrRetentionActive = BIT0,
+ FivrNormActive = BIT1,
+ FivrMinActive = BIT2,
+ FivrMinRetention = BIT3
+} FIVR_RAIL_SUPPORTED_VOLTAGE;
+
+/**
+ Structure for V1p05/Vnn VR rail configuration
+**/
+typedef struct {
+ /**
+ Mask to enable the usage of external VR rail in specific S0ix or Sx states
+ Use values from FIVR_RAIL_SX_STATE
+ The default is <b>FivrRailDisabled</b>.
+ **/
+ UINT32 EnabledStates : 6;
+
+ /**
+ VR rail voltage value that will be used in S0i2/S0i3 states.
+ This value is given in 2.5mV increments (0=0mV, 1=2.5mV, 2=5mV...)
+ The default for Vnn is set to <b>420 - 1050 mV</b>.
+ **/
+ UINT32 Voltage : 11;
+ /**
+ @deprecated
+ THIS POLICY IS DEPRECATED, PLEASE USE IccMaximum INSTEAD
+ VR rail Icc Max Value
+ Granularity of this setting is 1mA and maximal possible value is 500mA
+ The default is <b> 0mA </b>.
+ **/
+ UINT32 IccMax : 8;
+ /**
+ UINT32 Alignement
+ **/
+ UINT32 RsvdBits1 : 7;
+ /**
+ This register holds the control hold off values to be used when
+ changing the rail control for external bypass value in us
+ **/
+ UINT32 CtrlRampTmr : 8;
+
+ /**
+ Mask to set the supported configuration in VR rail.
+ Use values from FIVR_RAIL_SUPPORTED_VOLTAGE
+ **/
+ UINT32 SupportedVoltageStates : 4;
+
+ /**
+ VR rail Icc Maximum Value
+ Granularity of this setting is 1mA and maximal possible value is 500mA
+ The default is <b> 0mA </b>.
+ **/
+ UINT32 IccMaximum : 16;
+ /**
+ UINT32 Alignment
+ **/
+ UINT32 RsvdBits2 : 4;
+
+} FIVR_EXT_RAIL_CONFIG;
+
+
+/**
+ Structure for VCCIN_AUX voltage rail configuration
+**/
+typedef struct {
+ /**
+ Transition time in microseconds from Low Current Mode Voltage to High Current Mode Voltage.
+ Voltage transition time required by motherboard voltage regulator when PCH changes
+ the VCCIN_AUX regulator set point from the low current mode voltage and high current mode voltage.
+ This field has 1us resolution.
+ When value is 0 PCH will not transition VCCIN_AUX to low current mode voltage.
+ The default is <b> 0xC </b>.
+ **/
+ UINT8 LowToHighCurModeVolTranTime;
+
+ /**
+ Transition time in microseconds from Retention Mode Voltage to High Current Mode Voltage.
+ Voltage transition time required by motherboard voltage regulator when PCH changes
+ the VCCIN_AUX regulator set point from the retention mode voltage to high current mode voltage.
+ This field has 1us resolution.
+ When value is 0 PCH will not transition VCCIN_AUX to retention voltage.
+ The default is <b> 0x36 </b>.
+ **/
+ UINT8 RetToHighCurModeVolTranTime;
+
+ /**
+ Transition time in microseconds from Retention Mode Voltage to Low Current Mode Voltage.
+ Voltage transition time required by motherboard voltage regulator when PCH changes
+ the VCCIN_AUX regulator set point from the retention mode voltage to low current mode voltage.
+ This field has 1us resolution.
+ When value is 0 PCH will not transition VCCIN_AUX to retention voltage.
+ The default is <b> 0x2B </b>.
+ **/
+ UINT8 RetToLowCurModeVolTranTime;
+ UINT8 RsvdByte1;
+ /**
+ Transition time in microseconds from Off (0V) to High Current Mode Voltage.
+ Voltage transition time required by motherboard voltage regulator when PCH changes
+ the VCCIN_AUX regulator set point from 0V to the high current mode voltage.
+ This field has 1us resolution.
+ 0 = Transition to 0V is disabled
+ Setting this field to 0 sets VCCIN_AUX as a fixed rail that stays on
+ in all S0 & Sx power states after initial start up on G3 exit
+ The default is <b> 0x96 </b>.
+ **/
+ UINT32 OffToHighCurModeVolTranTime : 11;
+ UINT32 RsvdBits1 : 21;
+} FIVR_VCCIN_AUX_CONFIG;
+
+/**
+ The PCH_FIVR_CONFIG block describes FIVR settings.
+**/
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Config Block Header
+ /**
+ External V1P05 VR rail configuration.
+ **/
+ FIVR_EXT_RAIL_CONFIG ExtV1p05Rail;
+ /**
+ External Vnn VR rail configuration.
+ **/
+ FIVR_EXT_RAIL_CONFIG ExtVnnRail;
+ /**
+ Additional External Vnn VR rail configuration that will get applied
+ in Sx entry SMI callback. Required only if External Vnn VR
+ needs different settings for Sx than those specified in ExtVnnRail.
+ **/
+ FIVR_EXT_RAIL_CONFIG ExtVnnRailSx;
+ /**
+ VCCIN_AUX voltage rail configuration.
+ **/
+ FIVR_VCCIN_AUX_CONFIG VccinAux;
+
+ /**
+ Enable/Disable FIVR Dynamic Power Management
+ Default is <b> 1 </b>.
+ **/
+ UINT32 FivrDynPm : 1;
+ /**
+ Enable/Disable Bypass of FIVR configuration
+ Default is <b> 0 </b>.
+ **/
+ UINT32 BypassFivrConfig : 1;
+ UINT32 RsvdBits2 : 30;
+} PCH_FIVR_CONFIG;
+
+#pragma pack (pop)
+
+#endif // _FIVR_CONFIG_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Gpio/GpioDevConfig.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Gpio/GpioDevConfig.h
new file mode 100644
index 0000000000..5652df0259
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Gpio/GpioDevConfig.h
@@ -0,0 +1,37 @@
+/** @file
+ GPIO device policy
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _GPIO_DEV_CONFIG_H_
+#define _GPIO_DEV_CONFIG_H_
+
+extern EFI_GUID gGpioDxeConfigGuid;
+
+#define GPIO_DXE_CONFIG_REVISION 1
+
+#pragma pack (push,1)
+
+/**
+ This structure contains the DXE policies which are related to GPIO device.
+
+ <b>Revision 1:</b>
+ - Inital version.
+**/
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Config Block Header
+ /**
+ If GPIO ACPI device is not used by OS it can be hidden. In such case
+ no other device exposed to the system can reference GPIO device in one
+ of its resources through GpioIo(..) or GpioInt(..) ACPI descriptors.
+ <b>0: Disable</b>; 1: Enable
+ **/
+ UINT32 HideGpioAcpiDevice : 1;
+ UINT32 RsvdBits : 31; ///< Reserved bits
+
+} GPIO_DXE_CONFIG;
+
+#pragma pack (pop)
+
+#endif // _GPIO_DEV_CONFIG_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Graphics/Gen12/GraphicsConfig.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Graphics/Gen12/GraphicsConfig.h
new file mode 100644
index 0000000000..c6a2f36612
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Graphics/Gen12/GraphicsConfig.h
@@ -0,0 +1,212 @@
+/** @file
+ Policy definition for Internal Graphics Config Block.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _GRAPHICS_CONFIG_H_
+#define _GRAPHICS_CONFIG_H_
+#pragma pack(push, 1)
+
+#define GRAPHICS_DXE_CONFIG_REVISION 2
+
+#define MAX_BCLM_ENTRIES 20
+
+
+//
+// DDI defines
+//
+typedef enum {
+ DdiDisable = 0x00,
+ DdiDdcEnable = 0x01,
+} DDI_DDC_TBT_VAL;
+
+typedef enum {
+ DdiHpdDisable = 0x00,
+ DdiHpdEnable = 0x01,
+} DDI_HPD_VAL;
+
+typedef enum {
+ DdiPortDisabled = 0x00,
+ DdiPortEdp = 0x01,
+ DdiPortMipiDsi = 0x02,
+} DDI_PORT_SETTINGS;
+
+/**
+ This structure configures the Native GPIOs for DDI port per VBT settings.
+**/
+typedef struct {
+ UINT8 DdiPortAConfig; /// The Configuration of DDI port A, this settings must match VBT's settings. DdiPortDisabled - No LFP is connected on DdiPortA, <b>DdiPortEdp - Set DdiPortA to eDP</b>, DdiPortMipiDsi - Set DdiPortA to MIPI DSI
+ UINT8 DdiPortBConfig; /// The Configuration of DDI port B, this settings must match VBT's settings. DdiPortDisabled - No LFP is connected on DdiPortB, <b>DdiPortEdp - Set DdiPortB to eDP</b>, DdiPortMipiDsi - Set DdiPortB to MIPI DSI
+ UINT8 DdiPortAHpd; /// The HPD setting of DDI Port A, this settings must match VBT's settings. <b>DdiHpdDisable - Disable HPD</b>, DdiHpdEnable - Enable HPD
+ UINT8 DdiPortBHpd; /// The HPD setting of DDI Port B, this settings must match VBT's settings. DdiHpdDisable - Disable HPD, <b>DdiHpdEnable - Enable HPD</b>
+ UINT8 DdiPortCHpd; /// The HPD setting of DDI Port C, this settings must match VBT's settings. <b>DdiHpdDisable - Disable HPD</b>, DdiHpdEnable - Enable HPD
+ UINT8 DdiPort1Hpd; /// The HPD setting of DDI Port 1, this settings must match VBT's settings. <b>DdiHpdDisable - Disable HPD</b>, DdiHpdEnable - Enable HPD
+ UINT8 DdiPort2Hpd; /// The HPD setting of DDI Port 2, this settings must match VBT's settings. <b>DdiHpdDisable - Disable HPD</b>, DdiHpdEnable - Enable HPD
+ UINT8 DdiPort3Hpd; /// The HPD setting of DDI Port 3, this settings must match VBT's settings. <b>DdiHpdDisable - Disable HPD</b>, DdiHpdEnable - Enable HPD
+ UINT8 DdiPort4Hpd; /// The HPD setting of DDI Port 4, this settings must match VBT's settings. <b>DdiHpdDisable - Disable HPD</b>, DdiHpdEnable - Enable HPD
+ UINT8 DdiPortADdc; /// The DDC setting of DDI Port A, this settings must match VBT's settings. <b>DdiDisable - Disable DDC</b>, DdiDdcEnable - Enable DDC
+ UINT8 DdiPortBDdc; /// The DDC setting of DDI Port B, this settings must match VBT's settings. DdiDisable - Disable DDC, <b>DdiDdcEnable - Enable DDC </b>
+ UINT8 DdiPortCDdc; /// The DDC setting of DDI Port C, this settings must match VBT's settings. <b>DdiDisable - Disable DDC</b>, DdiDdcEnable - Enable DDC
+ UINT8 DdiPort1Ddc; /// The DDC setting of DDI Port 1, this settings must match VBT's settings. <b>DdiDisable - Disable DDC</b>, DdiDdcEnable - Enable DDC
+ UINT8 DdiPort2Ddc; /// The DDC setting of DDI Port 2, this settings must match VBT's settings. <b>DdiDisable - Disable DDC</b>, DdiDdcEnable - Enable DDC
+ UINT8 DdiPort3Ddc; /// The DDC setting of DDI Port 3, this settings must match VBT's settings. <b>DdiDisable - Disable DDC</b>, DdiDdcEnable - Enable DDC
+ UINT8 DdiPort4Ddc; /// The DDC setting of DDI Port 4, this settings must match VBT's settings. <b>DdiDisable - Disable DDC</b>, DdiDdcEnable - Enable DDC
+} DDI_CONFIGURATION;
+
+/**
+ This Configuration block is to configure GT related PreMem data/variables.\n
+ <b>Revision 1</b>:
+ - Initial version.
+**/
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Block Header
+ /**
+ Offset 28
+ Selection of the primary display device: 0=iGFX, 1=PEG, 2=PCIe Graphics on PCH, <b>3=AUTO</b>, 4=Switchable Graphics\n
+ When AUTO mode selected, the priority of display devices is: PCIe Graphics on PCH > PEG > iGFX
+ **/
+ UINT8 PrimaryDisplay;
+ /**
+ Offset 29
+ Intel Gfx Support. It controls enabling/disabling iGfx device.
+ When AUTO mode selected, iGFX will be turned off when external graphics detected.
+ If FALSE, all other polices can be ignored.
+ <b>2 = AUTO</b>;
+ 0 = FALSE;
+ 1 = TRUE.
+ **/
+ UINT8 InternalGraphics;
+ /**
+ Offset 30
+ Pre-allocated memory for iGFX\n
+ 0 = 0MB,1 or 247 = 32MB,\n
+ 2 = 64MB,\n
+ 240 = 4MB, 241 = 8MB,\n
+ 242 = 12MB, 243 = 16MB,\n
+ 244 = 20MB, 245 = 24MB,\n
+ 246 = 28MB, 248 = 36MB,\n
+ 249 = 40MB, 250 = 44MB,\n
+ 251 = 48MB, 252 = 52MB,\n
+ 253 = 56MB,<b> 254 = 60MB</b>,\n
+ <b>Note: enlarging pre-allocated memory for iGFX may need to reduce MmioSize because of 4GB boundary limitation</b>
+ **/
+ UINT16 IgdDvmt50PreAlloc;
+ UINT8 PanelPowerEnable; ///< Offset 32 :<b>(Test)</b> Control for enabling/disabling VDD force bit (Required only for early enabling of eDP panel): 0=FALSE, <b>1=TRUE</b>
+ UINT8 ApertureSize; ///< Offset 33 :Graphics aperture size (256MB is the recommended size as per BWG) : 0=128MB, <b>1=256MB</b>, 3=512MB, 7=1024MB, 15=2048MB.
+ UINT8 GtPsmiSupport; ///< Offset 34 :PSMI support On/Off: <b>0=FALSE</b>, 1=TRUE
+ UINT8 PsmiRegionSize; ///< Offset 35 :Psmi region size: <b>0=32MB</b>, 1=288MB, 2=544MB, 3=800MB, 4=1056MB
+ UINT8 DismSize; ///< Offset 36 :DiSM Size for 2LM Sku: <b>0=0GB</b>, 1=1GB, 2=2GB, 3=3GB, 4=4GB, 5=5GB, 6=6GB, 7=7GB
+ UINT8 DfdRestoreEnable; ///< Offset 37 :(Deprecated) Display memory map programming for DFD Restore <b>0- Disable</b>, 1- Enable
+ UINT16 GttSize; ///< Offset 38 :Selection of iGFX GTT Memory size: 1=2MB, 2=4MB, <b>3=8MB</b>
+ /**
+ Offset 40
+ Temp Address of System Agent GTTMMADR: Default is <b>0xAF000000</b>
+ **/
+ UINT32 GttMmAdr;
+ UINT32 GmAdr; ///< Offset 44 Obsolete not to be used, use GmAdr64
+ DDI_CONFIGURATION DdiConfiguration; ///< Offset 48 DDI configuration, need to match with VBT settings.
+
+ UINT8 GtClosEnable; ///< Offset 50 Gt ClOS
+ UINT8 Rsvd0[7]; ///< Offset 51 Reserved for 4 bytes of alignment
+ /**
+ Offset 58
+ Temp Address of System Agent GMADR: Default is <b>0xB0000000</b>
+ **/
+ UINT64 GmAdr64;
+ UINT16 DeltaT12PowerCycleDelay; ///< Offset 66 Power Cycle Delay required for eDP as per VESA standard.0 - 0 ms, <b>0xFFFF - Auto calculate to max 500 ms<\b>
+ UINT8 DisplayAudioLink; ///< Offset 68 Enable/Disable Display Audio Links in Pre-OS.<b>0- Disable</b>, 1- Enable
+ UINT8 OemT12DelayOverride; ///< Offset 69 :Oem T12 Delay Override <b> Disable<\b>,Enable-Enable T12 Time.
+ UINT8 Rsvd2[4]; ///< Offset 70 Reserved for 4 bytes of alignment
+} GRAPHICS_PEI_PREMEM_CONFIG;
+
+/**
+ This configuration block is to configure IGD related variables used in PostMem PEI.
+ If Intel Gfx Device is not supported, all policies can be ignored.
+ <b>Revision 1</b>:
+ - Initial version.
+ <b>Revision 2</b>:
+ - Removed DfdRestoreEnable.
+ <b>Revision 3</b>:
+ - Removed DdiConfiguration.
+ <b>Revision 4</b>:
+ - Added new CdClock frequency
+ <b>Revision 5</b>:
+ - Added GT Chicket bits
+ <b>Revision 6</b>:
+ - Added LogoPixelHeight and LogoPixelWidth
+ <b>Revision 7</b>:
+ - Added SkipFspGop
+ <b>Revision 8</b>:
+ - Added VerticalResolution and HorizontalResolution
+
+**/
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Block Header
+ UINT8 RenderStandby; ///< Offset 28 :<b>(Test)</b> This field is used to enable or disable RC6 (Render Standby): 0=FALSE, <b>1=TRUE</b>
+ UINT8 PmSupport; ///< Offset 29 :<b>(Test)</b> Configure GT to use along with PM Support TRUE/FALSE: 0=FALSE, <b>1=TRUE</b>
+ /**
+ Offset 30
+ CdClock Frequency select\n
+ <b>0xFF = Auto. Max CdClock freq based on Reference Clk</b> \n
+ 0: 192 Mhz, 1: 307.2 Mhz, 2: 312 Mhz, 3: 324 Mhz, 4: 326.4 Mhz, 5: 552 Mhz, 6: 556.8 Mhz, 7: 648 Mhz, 8: 652.8 Mhz
+
+ **/
+ UINT16 CdClock;
+ UINT8 PeiGraphicsPeimInit; ///< Offset 32 : This policy is used to enable/disable Intel Gfx PEIM.<b>0- Disable</b>, 1- Enable
+ UINT8 CdynmaxClampEnable; ///< Offset 33 : This policy is used to enable/disable CDynmax Clamping Feature (CCF) <b>1- Enable</b>, 0- Disable
+ UINT16 GtFreqMax; ///< Offset 34 : <b>(Test)</b> Max GT frequency limited by user in multiples of 50MHz: Default value which indicates normal frequency is <b>0xFF</b>
+ UINT8 DisableTurboGt; ///< Offset 36 : This policy is used to enable/disable DisableTurboGt <b>0- Disable</b>, 1- Enable
+ UINT8 SkipCdClockInit; ///< Offset 37 : SKip full CD clock initialization. <b>0- Disable</b>, 1- Enable
+ UINT8 RC1pFreqEnable; ///< Offset 38 : This policy is used to enable/disable RC1p Frequency. <b>0- Disable</b>, 1- Enable
+ UINT8 PavpEnable; ///< Offset 39 :IGD PAVP TRUE/FALSE: 0=FALSE, <b>1=TRUE</b>
+ VOID* LogoPtr; ///< Offset 40 Address of Intel Gfx PEIM Logo to be displayed
+ UINT32 LogoSize; ///< Offset 44 Intel Gfx PEIM Logo Size
+ VOID* GraphicsConfigPtr; ///< Offset 48 Address of the Graphics Configuration Table
+ VOID* BltBufferAddress; ///< Offset 52 Address of Blt buffer for PEIM Logo use
+ UINT32 BltBufferSize; ///< Offset 56 The size for Blt Buffer, calculating by PixelWidth * PixelHeight * 4 bytes (the size of EFI_GRAPHICS_OUTPUT_BLT_PIXEL)
+ UINT8 ProgramGtChickenBits; ///< Offset 60 Program GT Chicket bits in GTTMMADR + 0xD00 BITS [3:1].
+ UINT8 SkipFspGop; ///< Offset 61 This policy is used to skip PEIM GOP in FSP.<b>0- Use FSP provided GOP driver</b>, 1- Skip FSP provided GOP driver
+ UINT8 Rsvd1[2]; ///< Offset 62 Reserved for 4 bytes alignment
+ UINT32 LogoPixelHeight; ///< Offset 64 Address of LogoPixelHeight for PEIM Logo use
+ UINT32 LogoPixelWidth; ///< Offset 68 Address of LogoPixelWidth for PEIM Logo use
+ UINT32 VerticalResolution; ///< Offset 72 Address of VerticalResolution for PEIM Logo use
+ UINT32 HorizontalResolution; ///< Offset 76 Address of HorizontalResolution for PEIM Logo use
+} GRAPHICS_PEI_CONFIG;
+
+/**
+ This configuration block is to configure IGD related variables used in DXE.
+ If Intel Gfx Device is not supported or disabled, all policies will be ignored.
+ The data elements should be initialized by a Platform Module.\n
+ <b>Revision 1</b>:
+ - Initial version.
+ <b>Revision 2</b>:
+ - Removed IgdDvmtMemSize.
+**/
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Offset 0-27: Config Block Header
+ UINT32 Size; ///< Offset 28 - 31: This field gives the size of the GOP VBT Data buffer
+ EFI_PHYSICAL_ADDRESS VbtAddress; ///< Offset 32 - 39: This field points to the GOP VBT data buffer
+ UINT8 PlatformConfig; ///< Offset 40: This field gives the Platform Configuration Information (0=Platform is S0ix Capable for ULT SKUs only, <b>1=Platform is not S0ix Capable</b>, 2=Force Platform is S0ix Capable for All SKUs)
+ UINT8 AlsEnable; ///< Offset 41: Ambient Light Sensor Enable: <b>0=Disable</b>, 2=Enable
+ UINT8 BacklightControlSupport; ///< Offset 42: Backlight Control Support: 0=PWM Inverted, <b>2=PWM Normal</b>
+ UINT8 IgdBootType; ///< Offset 43: IGD Boot Type CMOS option: <b>0=Default</b>, 0x01=CRT, 0x04=EFP, 0x08=LFP, 0x20=EFP3, 0x40=EFP2, 0x80=LFP2
+ UINT32 IuerStatusVal; ///< Offset 44 - 47: Offset 16 This field holds the current status of all the supported Ultrabook events (Intel(R) Ultrabook Event Status bits)
+ CHAR16 GopVersion[0x10]; ///< Offset 48 - 79:This field holds the GOP Driver Version. It is an Output Protocol and updated by the Silicon code
+ /**
+ Offset 80: IGD Panel Type CMOS option\n
+ <b>0=Default</b>, 1=640X480LVDS, 2=800X600LVDS, 3=1024X768LVDS, 4=1280X1024LVDS, 5=1400X1050LVDS1\n
+ 6=1400X1050LVDS2, 7=1600X1200LVDS, 8=1280X768LVDS, 9=1680X1050LVDS, 10=1920X1200LVDS, 13=1600X900LVDS\n
+ 14=1280X800LVDS, 15=1280X600LVDS, 16=2048X1536LVDS, 17=1366X768LVDS
+ **/
+ UINT8 IgdPanelType;
+ UINT8 IgdPanelScaling; ///< Offset 81: IGD Panel Scaling: <b>0=AUTO</b>, 1=OFF, 6=Force scaling
+ UINT8 IgdBlcConfig; ///< Offset 82: Backlight Control Support: 0=PWM Inverted, <b>2=PWM Normal</b>
+ UINT8 IgdDvmtMemSize; ///< Offset 83: @deprecated IGD DVMT Memory Size: 1=128MB, <b>2=256MB</b>, 3=MAX
+ UINT8 GfxTurboIMON; ///< Offset 84: IMON Current Value: 14=Minimal, <b>31=Maximum</b>
+ UINT8 Reserved[3]; ///< Offset 85: Reserved for DWORD alignment.
+ UINT16 BCLM[MAX_BCLM_ENTRIES]; ///< Offset 88: IGD Backlight Brightness Level Duty cycle Mapping Table.
+} GRAPHICS_DXE_CONFIG;
+#pragma pack(pop)
+
+#endif // _GRAPHICS_CONFIG_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/HostBridge/Ver1/HostBridgeConfig.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/HostBridge/Ver1/HostBridgeConfig.h
new file mode 100644
index 0000000000..11ef7b119c
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/HostBridge/Ver1/HostBridgeConfig.h
@@ -0,0 +1,58 @@
+/** @file
+ Configurations for HostBridge
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _HOST_BRIDGE_CONFIG_H_
+#define _HOST_BRIDGE_CONFIG_H_
+
+#include <ConfigBlock.h>
+
+
+extern EFI_GUID gHostBridgePeiPreMemConfigGuid;
+extern EFI_GUID gHostBridgePeiConfigGuid;
+
+#pragma pack (push,1)
+
+/**
+ This configuration block describes HostBridge settings in PreMem.\n
+ <b>Revision 1</b>:
+ - Initial version.
+**/
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Block Header
+ UINT32 MchBar; ///< Offset 28 Address of System Agent MCHBAR: <b>0xFEDC0000(TGL)/0xFEA80000(JSL)<b>
+ UINT32 DmiBar; ///< Offset 32 Address of System Agent DMIBAR: <b>0xFEDA0000</b>
+ UINT32 EpBar; ///< Offset 36 Address of System Agent EPBAR: <b>0xFEDA1000</b>
+ UINT32 GdxcBar; ///< Offset 40 Address of System Agent GDXCBAR: <b>0xFED84000</b>
+ UINT32 RegBar; ///< Offset 44 Address of System Agent REGBAR: <b>0xFB000000</b>
+ UINT32 EdramBar; ///< Offset 48 Address of System Agent EDRAMBAR: <b>0xFED80000</b>
+ /**
+ Offset 52 :
+ Size of reserved MMIO space for PCI devices\n
+ <b>0=AUTO</b>, 512=512MB, 768=768MB, 1024=1024MB, 1280=1280MB, 1536=1536MB, 1792=1792MB,
+ 2048=2048MB, 2304=2304MB, 2560=2560MB, 2816=2816MB, 3072=3072MB\n
+ When AUTO mode selected, the MMIO size will be calculated by required MMIO size from PCIe devices detected.
+ **/
+ UINT32 MmioSize;
+ UINT32 MmioSizeAdjustment; ///< Offset 56 Increase (given positive value) or Decrease (given negative value) the Reserved MMIO size when Dynamic Tolud/AUTO mode enabled (in MBs): <b>0=no adjustment</b>
+ UINT8 EnableAbove4GBMmio; ///< Offset 60 Enable/disable above 4GB MMIO resource support: 0=Disable, <b>1=Enable</b>
+ UINT8 Reserved[3]; ///< Offset 61 Reserved for future use.
+} HOST_BRIDGE_PREMEM_CONFIG;
+
+
+/**
+ This configuration block describes HostBridge settings in Post-Mem.\n
+ <b>Revision 1</b>:
+ - Initial version.
+**/
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Block Header
+ UINT8 SkipPamLock; ///< Offset 28 :To skip PAM register locking. @note It is still recommended to set PCI Config space B0: D0: F0: Offset 80h[0]=1 in platform code even Silicon code skipped this.\n <b>0=All PAM registers will be locked in Silicon code</b>, 1=Skip lock PAM registers in Silicon code.
+ UINT8 Reserved[3]; ///< Offset 29 Reserved for future use.
+} HOST_BRIDGE_PEI_CONFIG;
+
+#pragma pack (pop)
+
+#endif
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Itss/InterruptConfig.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Itss/InterruptConfig.h
new file mode 100644
index 0000000000..926c7ab6ab
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Itss/InterruptConfig.h
@@ -0,0 +1,38 @@
+/** @file
+ Interrupt policy
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _INTERRUPT_CONFIG_H_
+#define _INTERRUPT_CONFIG_H_
+
+extern EFI_GUID gInterruptConfigGuid;
+
+#pragma pack (push,1)
+
+//
+// --------------------- Interrupts Config ------------------------------
+//
+typedef enum {
+ PchNoInt, ///< No Interrupt Pin
+ PchIntA,
+ PchIntB,
+ PchIntC,
+ PchIntD
+} PCH_INT_PIN;
+
+///
+/// The PCH_DEVICE_INTERRUPT_CONFIG block describes interrupt pin, IRQ and interrupt mode for PCH device.
+///
+typedef struct {
+ UINT8 Device; ///< Device number
+ UINT8 Function; ///< Device function
+ UINT8 IntX; ///< Interrupt pin: INTA-INTD (see PCH_INT_PIN)
+ UINT8 Irq; ///< IRQ to be set for device.
+} PCH_DEVICE_INTERRUPT_CONFIG;
+
+
+#pragma pack (pop)
+
+#endif // _INTERRUPT_CONFIG_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Memory/Ver2/MemoryConfig.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Memory/Ver2/MemoryConfig.h
new file mode 100644
index 0000000000..2be85da5a8
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Memory/Ver2/MemoryConfig.h
@@ -0,0 +1,551 @@
+/** @file
+ Policy definition of Memory Config Block
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _MEMORY_CONFIG_H_
+#define _MEMORY_CONFIG_H_
+
+
+#pragma pack(push, 1)
+
+// MEMORY_CONFIGURATION_REVISION:
+// 3 - Adds DDR5 PDA Enumeration training
+// 4 - Adds LPDDR4 Command Mirroring
+// 5 - Adds PprEnableType
+// 6 - Removed IbeccParity
+// 7 - Adds MarginLimitCheck training within MEMORY_CONFIGURATION
+// 8 - Adds LpddrRttCa, LpddrRttWr
+// 9 - Adds VddqVoltage, VppVoltage
+// 10 - Changes PprEnableType to PprEnable
+// 11 - Changes DisableDimmChannel to DisableChannel
+// 12 - Added DIMMDFE
+// 13 - Added ExtendedBankHashing
+// 14 - Added IBECC Error Injection knobs: IbeccErrInjControl, IbeccErrInjAddress, IbeccErrInjMask, IbeccErrInjCount
+// 15 - Added DynamicMemoryBoost
+// 16 - Added ReuseAdlDdr5Board
+// 17 - Added RefreshWm; Deprecated RefreshPanicWm and RefreshHpWm
+// 18 - Added DebugValue
+// 19 - Added McRefreshRate; Deprecated McRefresh2X
+// 20 - Added RealtimeMemoryFrequency
+// 21 - Added PeriodicDcc and LpMode
+// 22 - Added Tx Dqs Dcc Training
+// 23 - Added tRFCpb, tRFC2, tRFC4, tRRD_L, tRRD_S, tWTR_L, tCCD_L, tWTR_S
+// 24 - Added EccErrInjAddress, EccErrInjMask, EccErrInjCount
+// 25 - Added FreqLimitMixedConfig, FirstDimmBitMask, UserBd
+// 26 - Added SagvSwitchFactorIA/GT/IO/Stall, SagvHeuristicsDownControl, SagvHeuristicsUpControl
+// 27 - Added DRAMDCA
+// 28 - Added FreqLimitMixedConfig_1R1R_8GB, FreqLimitMixedConfig_1R1R_16GB, FreqLimitMixedConfig_1R1R_8GB_16GB, FreqLimitMixedConfig_2R2R
+// 29 - Added LctCmdEyeWidth
+// 30 - Added FirstDimmBitMaskEcc
+// 31 - Added Lp5BankMode
+// 32 - Added WRDS
+// 33 - Added EARLYDIMMDFE for Early DIMM DFE Training
+// 34 - Added OverloadSAM
+#define MEMORY_CONFIGURATION_REVISION 34
+
+// MEMORY_CONFIG_NO_CRC_REVISION:
+// 3 - adds DDR5 SetMemoryPmicVoltage in SA_FUNCTION_CALLS
+#define MEMORY_CONFIG_NO_CRC_REVISION 3
+
+///
+/// MEMORY_CONFIGURATION interface definitions
+///
+#define MRC_MAX_RCOMP_TARGETS 5
+///
+/// Memory SubSystem Definitions
+///
+#define MEM_CFG_MAX_CONTROLLERS 2
+#define MEM_CFG_MAX_CHANNELS 4
+#define MEM_CFG_MAX_DIMMS 2
+#define MEM_CFG_NUM_BYTES_MAPPED 2
+#define MEM_CFG_MAX_SPD_SIZE 1024
+#define MEM_CFG_MAX_SOCKETS (MEM_CFG_MAX_CONTROLLERS * MEM_CFG_MAX_CHANNELS * MEM_CFG_MAX_DIMMS)
+#ifndef MEM_MAX_SAGV_POINTS
+#define MEM_MAX_SAGV_POINTS 4
+#endif
+#define MEM_MAX_IBECC_REGIONS 8
+
+///
+/// SA SPD profile selections.
+///
+typedef enum {
+ DEFAULT_SPD, ///< Standard DIMM profile select.
+ CUSTOM_PROFILE, ///< XMP enthusiast settings: User specifies various override values
+ XMP_PROFILE_1, ///< XMP enthusiast settings: XMP profile #1
+ XMP_PROFILE_2, ///< XMP enthusiast settings: XMP profile #2
+ XMP_PROFILE_3, ///< XMP enthusiast settings: XMP profile #3
+ XMP_USER_PROFILE_4, ///< XMP enthusiast settings: XMP user profile #4
+ XMP_USER_PROFILE_5, ///< XMP enthusiast settings: XMP user profile #5
+ SPDProfileMax = 0xFF ///< Ensures SA_SPD is UINT8
+} SA_SPD;
+
+///
+/// Define the boot modes used by the SPD read function.
+///
+typedef enum {
+ SpdCold, ///< Cold boot
+ SpdWarm, ///< Warm boot
+ SpdS3, ///< S3 resume
+ SpdFast, ///< Fast boot
+ SpdBootModeMax ///< Delimiter
+} SPD_BOOT_MODE;
+
+/**
+ SPD Data Buffer
+**/
+typedef struct {
+ UINT8 SpdData[MEM_CFG_MAX_CONTROLLERS][MEM_CFG_MAX_CHANNELS][MEM_CFG_MAX_DIMMS][MEM_CFG_MAX_SPD_SIZE]; ///< SpdData
+//Next Field Offset 2048
+} SPD_DATA_BUFFER;
+
+/**
+ DqDqs Mapping
+**/
+typedef struct {
+ UINT8 DqsMapCpu2Dram[MEM_CFG_MAX_CONTROLLERS][MEM_CFG_MAX_CHANNELS][MEM_CFG_NUM_BYTES_MAPPED]; ///< DqsMapCpu2Dram
+ UINT8 DqMapCpu2Dram[MEM_CFG_MAX_CONTROLLERS][MEM_CFG_MAX_CHANNELS][MEM_CFG_NUM_BYTES_MAPPED][8]; ///< DqMapCpu2Dram
+//Next Field Offset 16
+} SA_MEMORY_DQDQS_MAPPING;
+
+/**
+ Rcomp Policies
+**/
+typedef struct {
+ UINT16 RcompResistor; ///< Offset 0: Reference RCOMP resistors on motherboard ~ 100 ohms
+ UINT16 RcompTarget[MRC_MAX_RCOMP_TARGETS]; ///< Offset 1: RCOMP target values for DqOdt, DqDrv, CmdDrv, CtlDrv, ClkDrv
+//Next Field Offset 16
+} SA_MEMORY_RCOMP;
+
+/**
+ SPD Offset Table
+**/
+typedef struct {
+ UINT16 Start; ///< Offset 0
+ UINT16 End; ///< Offset 2
+ UINT8 BootMode; ///< Offset 4
+ UINT8 Reserved3[3]; ///< Offset 5 Reserved for future use
+} SPD_OFFSET_TABLE;
+
+///
+/// SA memory address decode.
+///
+typedef struct
+{
+ UINT8 Controller; ///< Offset 0 Zero based Controller number
+ UINT8 Channel; ///< Offset 1 Zero based Channel number
+ UINT8 Dimm; ///< Offset 2 Zero based DIMM number
+ UINT8 Rank; ///< Offset 3 Zero based Rank number
+ UINT8 BankGroup; ///< Offset 4 Zero based Bank Group number
+ UINT8 Bank; ///< Offset 5 Zero based Bank number
+ UINT16 Cas; ///< Offset 6 Zero based CAS number
+ UINT32 Ras; ///< Offset 8 Zero based RAS number
+} SA_ADDRESS_DECODE;
+
+typedef UINT8 (EFIAPI * SA_IO_READ_8) (UINTN IoAddress); ///< CPU I/O port 8-bit read.
+typedef UINT16 (EFIAPI * SA_IO_READ_16) (UINTN IoAddress); ///< CPU I/O port 16-bit read.
+typedef UINT32 (EFIAPI * SA_IO_READ_32) (UINTN IoAddress); ///< CPU I/O port 32-bit read.
+typedef UINT8 (EFIAPI * SA_IO_WRITE_8) (UINTN IoAddress, UINT8 Value); ///< CPU I/O port 8-bit write.
+typedef UINT16 (EFIAPI * SA_IO_WRITE_16) (UINTN IoAddress, UINT16 Value); ///< CPU I/O port 16-bit write.
+typedef UINT32 (EFIAPI * SA_IO_WRITE_32) (UINTN IoAddress, UINT32 Value); ///< CPU I/O port 32-bit write.
+typedef UINT8 (EFIAPI * SA_MMIO_READ_8) (UINTN Address); ///< Memory Mapped I/O port 8-bit read.
+typedef UINT16 (EFIAPI * SA_MMIO_READ_16) (UINTN Address); ///< Memory Mapped I/O port 16-bit read.
+typedef UINT32 (EFIAPI * SA_MMIO_READ_32) (UINTN Address); ///< Memory Mapped I/O port 32-bit read.
+typedef UINT64 (EFIAPI * SA_MMIO_READ_64) (UINTN Address); ///< Memory Mapped I/O port 64-bit read.
+typedef UINT8 (EFIAPI * SA_MMIO_WRITE_8) (UINTN Address, UINT8 Value); ///< Memory Mapped I/O port 8-bit write.
+typedef UINT16 (EFIAPI * SA_MMIO_WRITE_16) (UINTN Address, UINT16 Value); ///< Memory Mapped I/O port 16-bit write.
+typedef UINT32 (EFIAPI * SA_MMIO_WRITE_32) (UINTN Address, UINT32 Value); ///< Memory Mapped I/O port 32-bit write.
+typedef UINT64 (EFIAPI * SA_MMIO_WRITE_64) (UINTN Address, UINT64 Value); ///< Memory Mapped I/O port 64-bit write.
+typedef UINT8 (EFIAPI * SA_SMBUS_READ_8) (UINTN Address, RETURN_STATUS *Status); ///< Smbus 8-bit read.
+typedef UINT16 (EFIAPI * SA_SMBUS_READ_16) (UINTN Address, RETURN_STATUS *Status); ///< Smbus 16-bit read.
+typedef UINT8 (EFIAPI * SA_SMBUS_WRITE_8) (UINTN Address, UINT8 Value, RETURN_STATUS *Status); ///< Smbus 8-bit write.
+typedef UINT16 (EFIAPI * SA_SMBUS_WRITE_16) (UINTN Address, UINT16 Value, RETURN_STATUS *Status); ///< Smbus 16-bit write.
+typedef UINT32 (EFIAPI * SA_GET_PCI_DEVICE_ADDRESS) (UINT8 Bus, UINT8 Device, UINT8 Function, UINT8 Offset); ///< Get PCI device address.
+typedef UINT32 (EFIAPI * SA_GET_PCIE_DEVICE_ADDRESS) (UINT8 Bus, UINT8 Device, UINT8 Function, UINT8 Offset); ///< Get PCI express device address.
+typedef VOID (EFIAPI * SA_GET_RTC_TIME) (UINT8 *Second, UINT8 *Minute, UINT8 *Hour, UINT8 *Day, UINT8 *Month, UINT16 *Year); ///< Get the current time value.
+typedef UINT64 (EFIAPI * SA_GET_CPU_TIME) (VOID); ///< The current CPU time in milliseconds.
+typedef VOID * (EFIAPI * SA_MEMORY_COPY) (VOID *Destination, CONST VOID *Source, UINTN NumBytes); ///< Perform byte copy operation.
+typedef VOID * (EFIAPI * SA_MEMORY_SET_BYTE) (VOID *Buffer, UINTN NumBytes, UINT8 Value); ///< Perform byte initialization operation.
+typedef VOID * (EFIAPI * SA_MEMORY_SET_WORD) (VOID *Buffer, UINTN NumWords, UINT16 Value); ///< Perform word initialization operation.
+typedef VOID * (EFIAPI * SA_MEMORY_SET_DWORD) (VOID *Buffer, UINTN NumDwords, UINT32 Value); ///< Perform dword initialization operation.
+typedef UINT64 (EFIAPI * SA_LEFT_SHIFT_64) (UINT64 Data, UINTN NumBits); ///< Left shift the 64-bit data value by specified number of bits.
+typedef UINT64 (EFIAPI * SA_RIGHT_SHIFT_64) (UINT64 Data, UINTN NumBits); ///< Right shift the 64-bit data value by specified number of bits.
+typedef UINT64 (EFIAPI * SA_MULT_U64_U32) (UINT64 Multiplicand, UINT32 Multiplier); ///< Multiply a 64-bit data value by a 32-bit data value.
+typedef UINT64 (EFIAPI * SA_DIV_U64_U64) (UINT64 Dividend, UINT64 Divisor, UINT64 *Remainder); ///< Divide a 64-bit data value by a 64-bit data value.
+typedef BOOLEAN (EFIAPI * SA_GET_SPD_DATA) (SPD_BOOT_MODE BootMode, UINT8 SpdAddress, UINT8 *Buffer, UINT8 *Ddr3Table, UINT32 Ddr3TableSize, UINT8 *Ddr4Table, UINT32 Ddr4TableSize, UINT8 *LpddrTable, UINT32 LpddrTableSize); ///< Read the SPD data over the SMBus, at the given SmBus SPD address and copy the data to the data structure.
+typedef UINT8 (EFIAPI * SA_GET_MC_ADDRESS_DECODE) (UINT64 Address, SA_ADDRESS_DECODE *DramAddress);
+typedef UINT8 (EFIAPI * SA_GET_MC_ADDRESS_ENCODE) (SA_ADDRESS_DECODE *DramAddress, UINT64 Address);
+typedef BOOLEAN (EFIAPI * SA_GET_RANDOM_NUMBER) (UINT32 *Rand); ///< Get the next random 32-bit number.
+typedef EFI_STATUS (EFIAPI * SA_CPU_MAILBOX_READ) (UINT32 Type, UINT32 Command, UINT32 *Value, UINT32 *Status); ///< Perform a CPU mailbox read.
+typedef EFI_STATUS (EFIAPI * SA_CPU_MAILBOX_WRITE) (UINT32 Type, UINT32 Command, UINT32 Value, UINT32 *Status); ///< Perform a CPU mailbox write.
+typedef UINT32 (EFIAPI * SA_GET_MEMORY_VDD) (VOID *GlobalData, UINT32 DefaultVdd); ///< Get the current memory voltage (VDD).
+typedef UINT32 (EFIAPI * SA_SET_MEMORY_VDD) (VOID *GlobalData, UINT32 DefaultVdd, UINT32 Value); ///< Set the memory voltage (VDD) to the given value.
+typedef UINT32 (EFIAPI * SA_SET_MEMORY_PMIC_VOLTAGE) (VOID *GlobalData, UINT8 SpdAddress, UINT32 Vdd, UINT32 Vddq, UINT32 Vpp); ///< Set DDR5 memory voltages (VDD, VDDQ, VPP) to the given values.
+typedef UINT32 (EFIAPI * SA_CHECKPOINT) (VOID *GlobalData, UINT32 CheckPoint, VOID *Scratch); ///< Check point that is called at various points in the MRC.
+typedef VOID (EFIAPI * SA_DEBUG_HOOK) (VOID *GlobalData, UINT16 DisplayDebugNumber); ///< Typically used to display to the I/O port 80h.
+typedef UINT8 (EFIAPI * SA_CHANNEL_EXIST) (VOID *Outputs, UINT8 Channel); ///< Returns whether Channel is or is not present.
+typedef INT32 (EFIAPI * SA_PRINTF) (VOID *Debug, UINT32 Level, char *Format, ...); ///< Print to output stream/device.
+typedef VOID (EFIAPI * SA_DEBUG_PRINT) (VOID *String); ///< Output a string to the debug stream/device.
+typedef UINT32 (EFIAPI * SA_CHANGE_MARGIN) (VOID *GlobalData, UINT8 Param, INT32 Value0, INT32 Value1, UINT8 EnMultiCast, UINT8 Channel, UINT8 RankIn, UINT8 Byte, UINT8 BitIn, UINT8 UpdateMrcData, UINT8 SkipWait, UINT32 RegFileParam); ///< Change the margin.
+typedef UINT8 (EFIAPI * SA_SIGN_EXTEND) (UINT8 Value, UINT8 OldMsb, UINT8 NewMsb); ///< Sign extends OldMSB to NewMSB Bits (Eg: Bit 6 to Bit 7).
+typedef VOID (EFIAPI * SA_SHIFT_PI_COMMAND_TRAIN) (VOID *GlobalData, UINT8 Channel, UINT8 Iteration, UINT8 RankMask, UINT8 GroupMask, INT32 NewValue, UINT8 UpdateHost); ///< Move CMD/CTL/CLK/CKE PIs during training.
+typedef VOID (EFIAPI * SA_UPDATE_VREF) (VOID *GlobalData, UINT8 Channel, UINT8 RankMask, UINT16 DeviceMask, UINT8 VrefType, INT32 Offset, BOOLEAN UpdateMrcData, BOOLEAN PDAmode, BOOLEAN SkipWait); ///< Update the Vref value and wait until it is stable.
+typedef UINT8 (EFIAPI * SA_GET_RTC_CMOS) (UINT8 Location); ///< Get the current value of the specified RTC CMOS location.
+typedef UINT64 (EFIAPI * SA_MSR_READ_64) (UINT32 Location); ///< Get the current value of the specified MSR location.
+typedef UINT64 (EFIAPI * SA_MSR_WRITE_64) (UINT32 Location, UINT64 Data); ///< Set the current value of the specified MSR location.
+typedef VOID (EFIAPI * SA_MRC_RETURN_FROM_SMC) (VOID *GlobalData, UINT32 MrcStatus); ///< Hook function after returning from MrcStartMemoryConfiguration()
+typedef VOID (EFIAPI * SA_MRC_DRAM_RESET) (UINT32 PciEBaseAddress, UINT32 ResetValue); ///< Assert or deassert DRAM_RESET# pin; this is used in JEDEC Reset.
+typedef VOID (EFIAPI * SA_DELAY_NS) (VOID *GlobalData, UINT32 DelayNs); ///< Delay (stall) for the given amount of nanoseconds.
+typedef VOID (EFIAPI * SA_SET_LOCK_PRMRR) (UINT64 PrmrrBaseAddress, UINT32 PrmrrSize);
+
+
+///
+/// Function calls into the SA.
+///
+typedef struct {
+ SA_IO_READ_8 IoRead8; ///< Offset 0: - CPU I/O port 8-bit read.
+ SA_IO_READ_16 IoRead16; ///< Offset 4: - CPU I/O port 16-bit read.
+ SA_IO_READ_32 IoRead32; ///< Offset 8: - CPU I/O port 32-bit read.
+ SA_IO_WRITE_8 IoWrite8; ///< Offset 12: - CPU I/O port 8-bit write.
+ SA_IO_WRITE_16 IoWrite16; ///< Offset 16: - CPU I/O port 16-bit write.
+ SA_IO_WRITE_32 IoWrite32; ///< Offset 20: - CPU I/O port 32-bit write.
+ SA_MMIO_READ_8 MmioRead8; ///< Offset 24: - Memory Mapped I/O port 8-bit read.
+ SA_MMIO_READ_16 MmioRead16; ///< Offset 28: - Memory Mapped I/O port 16-bit read.
+ SA_MMIO_READ_32 MmioRead32; ///< Offset 32: - Memory Mapped I/O port 32-bit read.
+ SA_MMIO_READ_64 MmioRead64; ///< Offset 36: - Memory Mapped I/O port 64-bit read.
+ SA_MMIO_WRITE_8 MmioWrite8; ///< Offset 40: - Memory Mapped I/O port 8-bit write.
+ SA_MMIO_WRITE_16 MmioWrite16; ///< Offset 44: - Memory Mapped I/O port 16-bit write.
+ SA_MMIO_WRITE_32 MmioWrite32; ///< Offset 48: - Memory Mapped I/O port 32-bit write.
+ SA_MMIO_WRITE_64 MmioWrite64; ///< Offset 52: - Memory Mapped I/O port 64-bit write.
+ SA_SMBUS_READ_8 SmbusRead8; ///< Offset 56: - Smbus 8-bit read.
+ SA_SMBUS_READ_16 SmbusRead16; ///< Offset 60: - Smbus 16-bit read.
+ SA_SMBUS_WRITE_8 SmbusWrite8; ///< Offset 64: - Smbus 8-bit write.
+ SA_SMBUS_WRITE_16 SmbusWrite16; ///< Offset 68: - Smbus 16-bit write.
+ SA_GET_PCI_DEVICE_ADDRESS GetPciDeviceAddress; ///< Offset 72: - Get PCI device address.
+ SA_GET_PCIE_DEVICE_ADDRESS GetPcieDeviceAddress; ///< Offset 76: - Get PCI express device address.
+ SA_GET_RTC_TIME GetRtcTime; ///< Offset 80: - Get the current time value.
+ SA_GET_CPU_TIME GetCpuTime; ///< Offset 84: - The current CPU time in milliseconds.
+ SA_MEMORY_COPY CopyMem; ///< Offset 88: - Perform byte copy operation.
+ SA_MEMORY_SET_BYTE SetMem; ///< Offset 92: - Perform byte initialization operation.
+ SA_MEMORY_SET_WORD SetMemWord; ///< Offset 96: - Perform word initialization operation.
+ SA_MEMORY_SET_DWORD SetMemDword; ///< Offset 100: - Perform dword initialization operation.
+ SA_LEFT_SHIFT_64 LeftShift64; ///< Offset 104: - Left shift the 64-bit data value by specified number of bits.
+ SA_RIGHT_SHIFT_64 RightShift64; ///< Offset 108: - Right shift the 64-bit data value by specified number of bits.
+ SA_MULT_U64_U32 MultU64x32; ///< Offset 112: - Multiply a 64-bit data value by a 32-bit data value.
+ SA_DIV_U64_U64 DivU64x64; ///< Offset 116: - Divide a 64-bit data value by a 64-bit data value.
+ SA_GET_SPD_DATA GetSpdData; ///< Offset 120: - Read the SPD data over the SMBus, at the given SmBus SPD address and copy the data to the data structure.
+ SA_GET_RANDOM_NUMBER GetRandomNumber; ///< Offset 124: - Get the next random 32-bit number.
+ SA_CPU_MAILBOX_READ CpuMailboxRead; ///< Offset 128: - Perform a CPU mailbox read.
+ SA_CPU_MAILBOX_WRITE CpuMailboxWrite; ///< Offset 132: - Perform a CPU mailbox write.
+ SA_GET_MEMORY_VDD GetMemoryVdd; ///< Offset 136: - Get the current memory voltage (VDD).
+ SA_SET_MEMORY_VDD SetMemoryVdd; ///< Offset 140: - Set the memory voltage (VDD) to the given value.
+ SA_CHECKPOINT CheckPoint; ///< Offset 144: - Check point that is called at various points in the MRC.
+ SA_DEBUG_HOOK DebugHook; ///< Offset 148: - Typically used to display to the I/O port 80h.
+ SA_DEBUG_PRINT DebugPrint; ///< Offset 152: - Output a string to the debug stream/device.
+ SA_GET_RTC_CMOS GetRtcCmos; ///< Offset 156: - Get the current value of the specified RTC CMOS location.
+ SA_MSR_READ_64 ReadMsr64; ///< Offset 160: - Get the current value of the specified MSR location.
+ SA_MSR_WRITE_64 WriteMsr64; ///< Offset 164 - Set the current value of the specified MSR location.
+ SA_MRC_RETURN_FROM_SMC MrcReturnFromSmc; ///< Offset 168 - Hook function after returning from MrcStartMemoryConfiguration()
+ SA_MRC_DRAM_RESET MrcDramReset; ///< Offset 172 - Assert or deassert DRAM_RESET# pin; this is used in JEDEC Reset.
+ SA_DELAY_NS MrcDelayNs; ///< Offset 176 - Delay (stall) for the given amount of nanoseconds.
+ SA_SET_MEMORY_PMIC_VOLTAGE SetMemoryPmicVoltage; ///< Offset 180: - Set the memory voltage (VDD/VDDQ/VPP) by PMIC for DDR5.
+} SA_FUNCTION_CALLS;
+
+///
+/// Function calls into the MRC.
+///
+typedef struct {
+ SA_CHANNEL_EXIST MrcChannelExist; ///< Offset 0: - Returns whether Channel is or is not present.
+ SA_PRINTF MrcPrintf; ///< Offset 4: - Print to output stream/device.
+ SA_CHANGE_MARGIN MrcChangeMargin; ///< Offset 8: - Change the margin.
+ SA_SIGN_EXTEND MrcSignExtend; ///< Offset 12: - Sign extends OldMSB to NewMSB Bits (Eg: Bit 6 to Bit 7).
+ SA_SHIFT_PI_COMMAND_TRAIN ShiftPiCommandTrain; ///< Offset 16: - Move CMD/CTL/CLK/CKE PIs during training.
+ SA_UPDATE_VREF MrcUpdateVref; ///< Offset 20: - Update the Vref value and wait until it is stable.
+} SA_MEMORY_FUNCTIONS;
+
+/**
+ Memory Configuration
+ The contents of this structure are CRC'd by the MRC for option change detection.
+ This structure is copied en mass to the MrcInput structure. If you add fields here, you must update the MrcInput structure.
+ Revision history is at the top of this file
+**/
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Block Header
+ UINT16 Size; ///< Offset 28 The size of this structure, in bytes. Must be the first entry in this structure.
+ UINT8 HobBufferSize; ///< Offset 30 Size of HOB buffer for MRC
+
+ UINT8 SpdProfileSelected; ///< Offset 31 SPD XMP profile selection - for XMP supported DIMM: <b>0=Default DIMM profile</b>, 1=Custom Profile, 2=XMP Profile 1, 3=XMP Profile 2, 4=XMP Profile 3, 5=XMP User Profile 4, 6=XMP User Profile 5
+
+ // The following parameters are used only when SpdProfileSelected is User Defined (CUSTOM_PROFILE)
+ UINT16 tCL; ///< Offset 32 User defined Memory Timing tCL value, valid when SpdProfileSelected is CUSTOM_PROFILE: <b>0=AUTO</b>, 31=Maximum.
+ UINT16 tRCDtRP; ///< Offset 34 User defined Memory Timing tRCD value (same as tRP), valid when SpdProfileSelected is CUSTOM_PROFILE: <b>0=AUTO</b>, 63=Maximum
+ UINT16 tRAS; ///< Offset 36 User defined Memory Timing tRAS value, valid when SpdProfileSelected is CUSTOM_PROFILE: <b>0=AUTO</b>, 64=Maximum.
+ UINT16 tWR; ///< Offset 38 User defined Memory Timing tWR value, valid when SpdProfileSelected is CUSTOM_PROFILE: <b>0=AUTO</b>, legal values: 5, 6, 7, 8, 10, 12, 14, 16, 18, 20, 24.
+ UINT16 tRFC; ///< Offset 40 User defined Memory Timing tRFC value, valid when SpdProfileSelected is CUSTOM_PROFILE: <b>0=AUTO</b>, 1023=Maximum.
+ UINT16 tRRD; ///< Offset 42 User defined Memory Timing tRRD value, valid when SpdProfileSelected is CUSTOM_PROFILE: <b>0=AUTO</b>, 15=Maximum.
+ UINT16 tWTR; ///< Offset 44 User defined Memory Timing tWTR value, valid when SpdProfileSelected is CUSTOM_PROFILE: <b>0=AUTO</b>, 28=Maximum.
+ UINT16 tRTP; ///< Offset 46 User defined Memory Timing tRTP value, valid when SpdProfileSelected is CUSTOM_PROFILE: <b>0=AUTO</b>, 15=Maximum. DDR4 legal values: 5, 6, 7, 8, 9, 10, 12
+ UINT16 tFAW; ///< Offset 48 User defined Memory Timing tFAW value, valid when SpdProfileSelected is CUSTOM_PROFILE: <b>0=AUTO</b>, 63=Maximum.
+ UINT16 tCWL; ///< Offset 50 User defined Memory Timing tCWL value, valid when SpdProfileSelected is CUSTOM_PROFILE: <b>0=AUTO</b>, 20=Maximum.
+ UINT16 tREFI; ///< Offset 52 User defined Memory Timing tREFI value, valid when SpdProfileSelected is CUSTOM_PROFILE: <b>0=AUTO</b>, 65535=Maximum.
+ UINT16 PciIndex; ///< Offset 54 Pci index register address: <b>0xCF8=Default</b>
+ UINT16 PciData; ///< Offset 56 Pci data register address: <b>0xCFC=Default</b>
+ UINT16 VddVoltage; ///< Offset 58 DRAM voltage (Vdd) in millivolts: <b>0=Platform Default (no override)</b>, 1200=1.2V, 1350=1.35V etc.
+ UINT16 Idd3n; ///< Offset 60 EPG Active standby current (Idd3N) in milliamps from DIMM datasheet.
+ UINT16 Idd3p; ///< Offset 62 EPG Active power-down current (Idd3P) in milliamps from DIMM datasheet.
+
+ UINT32 EccSupport:1; ///< Offset 64 Bit 0 - DIMM Ecc Support option - for Desktop only: 0=Disable, <b>1=Enable</b>
+ UINT32 MrcSafeConfig:1; ///< Bit 1 - MRC Safe Mode: <b>0=Disable</b>, 1=Enable
+ UINT32 RemapEnable:1; ///< Bit 2 - This option is used to control whether to enable/disable memory remap above 4GB: 0=Disable, <b>1=Enable</b>.
+ UINT32 ScramblerSupport:1; ///< Bit 3 - Memory scrambler support: 0=Disable, <b>1=Enable</b>
+ UINT32 Vc1ReadMeter:1; ///< Bit 4 - VC1 Read Metering Enable: 0=Disable, <b>1=Enable</b>
+ UINT32 ForceSingleSubchannel:1; ///< Bit 5 - TRUE means use SubChannel0 only (for LPDDR4): <b>0=Disable</b>, 1=Enable
+ UINT32 SimicsFlag:1; ///< Bit 6 - Option to Enable SIMICS: 0=Disable, <b>1=Enable</b>
+ UINT32 Ddr4DdpSharedClock:1; ///< Bit 7 - Select if CLK0 is shared between Rank0 and Rank1 in DDR4 DDP package. <b>0=Not shared</b>, 1=Shared
+ UINT32 SharedZqPin:1; ///< Bit 8 - Select if the ZQ resistor is shared between Ranks in DDR4/LPDDR4 DRAM Packages <b>0=Not Shared</b>, 1=Shared
+ UINT32 LpDqsOscEn:1; ///< Bit 9 - LPDDR Write DQ/DQS Retraining: 0=Disable, <b>1=Enable</b>
+ UINT32 RmtPerTask:1; ///< Bit 10 - Rank Margin Tool Per Task. <b>0 = Disabled</b>, 1 = Enabled
+ UINT32 TrainTrace:1; ///< Bit 11 - Trained state tracing debug. <b>0 = Disabled</b>, 1 = Enabled
+ UINT32 SafeMode:1; ///< Bit 12 - Define if safe mode is enabled for MC/IO
+ UINT32 MsHashEnable:1; ///< Bit 13 - Controller Hash Enable: 0=Disable, <b>1=Enable</b>
+ UINT32 DisPgCloseIdleTimeout:1; ///< Bit 14 - Disable Page Close Idle Timeout: 0=Enable, <b>1=Disable</b>
+ UINT32 Ibecc:1; ///< Bit 15 - In-band ECC: <b>0=Disable</b>, 1=Enable
+ UINT32 IbeccOperationMode:2; ///< Bits 16:17 - In-band ECC Operation Mode: 0=Functional Mode protects requests based on the address range, 1=Makes all requests non protected and ignore range checks, <b>2=Makes all requests protected and ignore range checks</b>
+ UINT32 ChHashOverride:1; ///< Bit 18 - Select if Channel Hash setting values will be taken from input parameters or automatically taken from POR values depending on DRAM type detected.
+ UINT32 EccDftEn:1; ///< Bit 19 - ECC DFT support option
+ UINT32 Write0:1; ///< Bit 20 - Write0 feature (LP5/DDR5): 0=Disable, <b>1=Enable</b>
+ UINT32 ReuseAdlSDdr5Board:1; ///< Bit 21 - Indicate whether adl ddr5 board is reused.
+ UINT32 PeriodicDcc:1; ///< Bit 22 - Periodic DCC: <b>0=Disable</b>, 1=Enable
+ UINT32 LpMode:2; ///< Bit 23:24 - LPMode: <b>0=Auto</b>, 1=Enabled, 2=Disabled, 3=Reserved
+ UINT32 RsvdO64B25to31:7; ///< Bits 25:31 reserved
+ UINT8 DisableChannel[MEM_CFG_MAX_CONTROLLERS][MEM_CFG_MAX_CHANNELS]; ///< Offset 68-75
+ UINT8 Ratio; ///< Offset 76 DDR Frequency ratio, to multiply by 133 or 100 MHz depending on RefClk. <b>0 = Auto</b>
+ UINT8 ProbelessTrace; ///< Offset 77 Probeless Trace: <b>0=Disabled</b>, <b>1=Enabled</b>
+ /**
+ Channel Hash Enable.\n
+ NOTE: BIT7 will interleave the channels at a 2 cache-line granularity, BIT8 at 4 and BIT9 at 8\n
+ 0=BIT6, <B>1=BIT7</B>, 2=BIT8, 3=BIT9
+ **/
+ UINT8 ChHashInterleaveBit; ///< Offset 78 Option to select interleave Address bit. Valid values are 0 - 3 for BITS 6 - 9 (Valid values for BDW are 0-7 for BITS 6 - 13)
+ UINT8 SmramMask; ///< Offset 79 Reserved memory ranges for SMRAM
+ UINT32 BClkFrequency; ///< Offset 80 Base reference clock value, in Hertz: <b>100000000 = 100Hz</b>, 125000000=125Hz, 167000000=167Hz, 250000000=250Hz
+
+ /// Training Algorithms 1 Offset 84
+ UINT32 ECT:1; ///< Bit 0 - Enable/Disable Early Command Training. Note it is not recommended to change this setting from the default value: <b>0=Disable</b>, 1=Enable.
+ UINT32 SOT:1; ///< Bit 1 - Enable/Disable Sense Amp Offset Training. Note it is not recommended to change this setting from the default value: 0=Disable, <b>1=Enable</b>.
+ UINT32 ERDMPRTC2D:1; ///< Bit 2 - Enable/Disable Early ReadMPR Timing Centering 2D. Note it is not recommended to change this setting from the default value: 0=Disable, <b>1=Enable</b>.
+ UINT32 RDMPRT:1; ///< Bit 3 - Enable/Disable Read MPR Training. Note it is not recommended to change this setting from the default value: 0=Disable, <b>1=Enable</b>.
+ UINT32 RCVET:1; ///< Bit 4 - Enable/Disable Receive Enable Training. Note it is not recommended to change this setting from the default value: 0=Disable, <b>1=Enable</b>.
+ UINT32 JWRL:1; ///< Bit 5 - Enable/Disable JEDEC Write Leveling Training. Note it is not recommended to change this setting from the default value: 0=Disable, <b>1=Enable</b>.
+ UINT32 EWRTC2D:1; ///< Bit 6 - Enable/Disable Early Write Time Centering 2D Training. Note it is not recommended to change this setting from the default value: 0=Disable, <b>1=Enable</b>.
+ UINT32 ERDTC2D:1; ///< Bit 7 - Enable/Disable Early Read Time Centering 2D Training. Note it is not recommended to change this setting from the default value: 0=Disable, <b>1=Enable</b>.
+ UINT32 WRTC1D:1; ///< Bit 8 - Enable/Disable 1D Write Timing Centering Training. Note it is not recommended to change this setting from the default value: 0=Disable, <b>1=Enable</b>.
+ UINT32 WRVC1D:1; ///< Bit 9 - Enable/Disable 1D Write Voltage Centering Training. Note it is not recommended to change this setting from the default value: 0=Disable, <b>1=Enable</b>.
+ UINT32 RDTC1D:1; ///< Bit 10 - Enable/Disable 1D Read Timing Centering Training. Note it is not recommended to change this setting from the default value: 0=Disable, <b>1=Enable</b>.
+ UINT32 DIMMODTT:1; ///< Bit 11 - Enable/Disable DIMM ODT Training. Note it is not recommended to change this setting from the default value: <b>0=Disable</b>, 1=Enable.
+ UINT32 DIMMRONT:1; ///< Bit 12 - Enable/Disable DIMM RON training. Note it is not recommended to change this setting from the default value: 0=Disable, <b>1=Enable</b>.
+ UINT32 WRDSEQT:1; ///< Bit 13 - Enable/Disable Write Drive Strength / Equalization Training 2D. Note it is not recommended to change this setting from the default value: <b>0=Disable</b>, 1=Enable.
+ UINT32 WRSRT:1; ///< Bit 14 - Enable/Disable Write Slew Rate traning. Note it is not recommended to change this setting from the default value: 0=Disable, <b>1=Enable.</b>
+ UINT32 RDODTT:1; ///< Bit 15 - Enable/Disable Read ODT Training. Note it is not recommended to change this setting from the default value: <b>0=Disable</b>, 1=Enable.
+ UINT32 RDEQT:1; ///< Bit 16 - Enable/Disable Read Equalization Training. Note it is not recommended to change this setting from the default value: <b>0=Disable</b>, 1=Enable.
+ UINT32 RDAPT:1; ///< Bit 17 - Enable/Disable Read Amplifier Power Training. Note it is not recommended to change this setting from the default value: <b>0=Disable</b>, 1=Enable.
+ UINT32 WRTC2D:1; ///< Bit 18 - Enable/Disable 2D Write Timing Centering Training. Note it is not recommended to change this setting from the default value: 0=Disable, <b>1=Enable</b>.
+ UINT32 RDTC2D:1; ///< Bit 19 - Enable/Disable 2D Read Timing Centering Training. Note it is not recommended to change this setting from the default value: 0=Disable, <b>1=Enable</b>.
+ UINT32 WRVC2D:1; ///< Bit 20 - Enable/Disable 2D Write Voltage Centering Training. Note it is not recommended to change this setting from the default value: 0=Disable, <b>1=Enable</b>.
+ UINT32 RDVC2D:1; ///< Bit 21 - Enable/Disable 2D Read Voltage Centering Training. Note it is not recommended to change this setting from the default value: 0=Disable, <b>1=Enable</b>.
+ UINT32 CMDVC:1; ///< Bit 22 - Enable/Disable Command Vref Centering Training. Note it is not recommended to change this setting from the default value 0=Disable, <b>1=Enable</b>.
+ UINT32 LCT:1; ///< Bit 23 - Enable/Disable Late Command Training. Note it is not recommended to change this setting from the default value: 0=Disable, <b>1=Enable</b>.
+ UINT32 RTL:1; ///< Bit 24 - Enable/Disable Round Trip Latency function. Note it is not recommended to change this setting from the default value: 0=Disable, <b>1=Enable</b>.
+ UINT32 TAT:1; ///< Bit 25 - Enable/Disable Turn Around Time function. Note it is not recommended to change this setting from the default value: <b>0=Disable</b>, 1=Enable.
+ UINT32 RMT:1; ///< Bit 26 - Enable/Disable Rank Margin Tool function: <b>0=Disable</b>, 1=Enable.
+ UINT32 MEMTST:1; ///< Bit 27 - Enable/Disable Memory Test function: <b>0=Disable</b>, 1=Enable.
+ UINT32 ALIASCHK:1; ///< Bit 28 - Enable/Disable DIMM SPD Alias Check: 0=Disable, <b>1=Enable</b>
+ UINT32 RCVENC1D:1; ///< Bit 29 - Enable/Disable Receive Enable Centering Training (LPDDR Only). Note it is not recommended to change this setting from the default value: <b>0=Disable</b>, 1=Enable
+ UINT32 RMC:1; ///< Bit 30 - Enable/Disable Retrain Margin Check. Note it is not recommended to change this setting from the default value: <b>0=Disable</b>, 1=Enable
+ UINT32 WRDSUDT:1; ///< Bit 31 - Enable/Disable Write Drive Strength Up/Dn independently. Note it is not recommended to change this setting from the default value: <b>0=Disable</b>, 1=Enable
+ /// Training Algorithms 2 Offset 88
+ UINT32 DCC : 1; ///< Bit 0 - Enable/Disable Duty Cycle Correction: 0=Disable, 1=Enable.
+ UINT32 RDVC1D : 1; ///< Bit 1 - Enable/Disable Read Voltage Centering 1D: 0=Disable, 1=Enable.
+ UINT32 TXTCO : 1; ///< Bit 2 - Enable/Disable Write TCO Comp Training: 0=Disable, 1=Enable.
+ UINT32 CLKTCO : 1; ///< Bit 3 - Enable/Disable Clock TCO Comp Training: 0=Disable, 1=Enable.
+ UINT32 CMDSR : 1; ///< Bit 4 - Enable/Disable CMD Slew Rate Training: 0=Disable, 1=Enable.
+ UINT32 CMDDSEQ : 1; ///< Bit 5 - Enable/Disable CMD Drive Strength and Tx Equalization: 0=Disable, 1=Enable.
+ UINT32 DIMMODTCA : 1; ///< Bit 6 - Enable/Disable Dimm ODT CA Training: 0=Disable, 1=Enable.
+ UINT32 TXTCODQS : 1; ///< Bit 7 - Enable/Disable Write TCO Dqs Training: 0=Disable, 1=Enable.
+ UINT32 CMDDRUD : 1; ///< Bit 8 - Enable/Disable CMD/CTL Drive Strength Up/Dn 2D: 0=Disable, 1=Enable.
+ UINT32 VCCDLLBP : 1; ///< Bit 9 - Enable/Disable VccDLL bypass to VccIOG training: 0=Disable, 1=Enable.
+ UINT32 PVTTDNLP : 1; ///< Bit 10 - Enable/Disable PanicVttDnLp Training: 0=Disable, 1=Enable.
+ UINT32 RDVREFDC : 1; ///< Bit 11 - Enable/Disable Read Vref Decap Training: 0=Disable, 1=Enable.
+ UINT32 VDDQT : 1; ///< Bit 12 - Enable/Disable Vddq Training: 0=Disable, 1=Enable.
+ UINT32 RMTBIT : 1; ///< Bit 13 - Enable/Disable Rank Margin Tool Per Bit: 0=Disable, 1=Enable.
+ UINT32 PDA : 1; ///< BIT 14 - Enable/Disable PDA Enumeration Training. Note it is not recommended to change this setting from the default value: 0=Disable, <b>1=Enable</b>.
+ UINT32 DIMMDFE : 1; ///< BIT 15 - Enable/Disable DIMM DFE Training: 0=Disable, <b>1=Enable</b>.
+ UINT32 TXDQSDCC : 1; ///< BIT 16 - Enable/Disable TX DQS DCC Training: 0=Disable, <b>1=Enable</b>.
+ UINT32 DRAMDCA : 1; ///< BIT 17 - Enable/Disable DRAM DCA Training: 0=Disable, <b>1=Enable</b>.
+ UINT32 WRDS : 1; ///< BIT 18 - Enable/Disable Write Driver Strength Training: 0=Disable, <b>1=Enable</b>.
+ UINT32 EARLYDIMMDFE : 1; ///< BIT 19 - Enable/Disable EARLY DIMM DFE Training: 0=Disable, <b>1=Enable</b>.
+ UINT32 ReservedBits2 :12; ///< Bits 20:31 - Reserved
+
+ UINT32 MrcTimeMeasure:1; ///< Offset 92 Bit 0 - Enables serial debug level to display the MRC execution times only: <b>0=Disable</b>, 1=Enable
+ UINT32 MrcFastBoot:1; ///< Bit 1 - Enables the MRC fast boot path for faster cold boot execution: 0=Disable, <b>1=Enable</b>
+ UINT32 DqPinsInterleaved:1; ///< Bit 2 - Interleaving mode of DQ/DQS pins which depends on board routing: <b>0=Disable</b>, 1=Enable
+ UINT32 RankInterleave:1; ///< Bit 3 - Rank Interleave Mode: 0=Disable, <b>1=Enable</b>
+ UINT32 EnhancedInterleave:1; ///< Bit 4 - Enhanced Interleave Mode: 0=Disable, <b>1=Enable</b>
+ UINT32 WeaklockEn:1; ///< Bit 5 - Weak Lock Enable: 0=Disable, <b>1=Enable</b>
+ UINT32 ChHashEnable:1; ///< Bit 6 - Channel Hash Enable: 0=Disable, <b>1=Enable</b>
+ UINT32 EnablePwrDn:1; ///< Bit 7 - Enable Power Down control for DDR: 0=PCODE control, <b>1=BIOS control</b>
+ UINT32 EnablePwrDnLpddr:1; ///< Bit 8 - Enable Power Down for LPDDR: 0=PCODE control, <b>1=BIOS control</b>
+ UINT32 SrefCfgEna:1; ///< Bit 9 - Enable Self Refresh: 0=Disable, <b>1=Enable</b>
+ UINT32 ThrtCkeMinDefeatLpddr:1; ///< Bit 10 - Throttler CKE min defeature for LPDDR: 0=Disable, <b>1=Enable</b>
+ UINT32 ThrtCkeMinDefeat:1; ///< Bit 11 - Throttler CKE min defeature: <b>0=Disable</b>, 1=Enable
+ UINT32 AutoSelfRefreshSupport:1; ///< Bit 12 - FALSE = No auto self refresh support, <b>TRUE = auto self refresh support</b>
+ UINT32 ExtTemperatureSupport:1; ///< Bit 13 - FALSE = No extended temperature support, <b>TRUE = extended temperature support</b>
+ UINT32 MobilePlatform:1; ///< Bit 14 - Memory controller device id indicates: <b>TRUE if mobile</b>, FALSE if not. Note: This will be auto-detected and updated.
+ UINT32 Force1Dpc:1; ///< Bit 15 - TRUE means force one DIMM per channel, <b>FALSE means no limit</b>
+ UINT32 ForceSingleRank:1; ///< Bit 16 - TRUE means use Rank0 only (in each DIMM): <b>0=Disable</b>, 1=Enable
+ UINT32 VttTermination:1; ///< Bit 17 - Vtt Termination for Data ODT: <b>0=Disable</b>, 1=Enable
+ UINT32 VttCompForVsshi:1; ///< Bit 18 - Enable/Disable Vtt Comparator For Vsshi: <b>0=Disable</b>, 1=Enable
+ UINT32 ExitOnFailure:1; ///< Bit 19 - MRC option for exit on failure or continue on failure: 0=Disable, <b>1=Enable</b>
+ UINT32 NewFeatureEnable1:1; ///< Bit 20 - Generic enable knob for new feature set 1 <b>0: Disable </b>; 1: Enable
+ UINT32 NewFeatureEnable2:1; ///< Bit 21 - Generic enable knob for new feature set 2 <b>0: Disable </b>; 1: Enable
+ UINT32 RhSelect:2; ///< Bit 22-23 - RH Select: <b>0=Disable</b>, 1=RFM, 2=pTRR
+ UINT32 RefreshPanicWm:4; ///< Bit 24-27 - Deprecated from revision 17. Use RefreshWm instead.
+ UINT32 RefreshHpWm:4; ///< Bit 28-31 - Deprecated from revision 17. Use RefreshWm instead.
+ UINT32 VddSettleWaitTime; ///< Offset 96 Amount of time in microseconds to wait for Vdd to settle on top of 200us required by JEDEC spec: <b>Default=0</b>
+ UINT16 SrefCfgIdleTmr; ///< Offset 100 Self Refresh idle timer: <b>512=Minimal</b>, 65535=Maximum
+ UINT16 ChHashMask; ///< Offset 102 Channel Hash Mask: 0x0001=BIT6 set(Minimal), 0x3FFF=BIT[19:6] set(Maximum), <b>0x30CE= BIT[19:18, 13:12 ,9:7] set</b>
+ UINT16 DdrFreqLimit; ///< Offset 104 Memory Frequency limit: <b>0 = Auto</b>, or memory speed value in MT/s: 1067, 1333, 1600 etc. See the possible values in MrcInterface.h
+ UINT8 MaxRttWr; ///< Offset 106 Maximum DIMM RTT_WR to use in power training: <b>0=ODT Off</b>, 1 = 120 ohms
+ UINT8 ThrtCkeMinTmr; ///< Offset 107 Throttler CKE min timer: 0=Minimal, 0xFF=Maximum, <b>0x00=Default</b>
+ UINT8 ThrtCkeMinTmrLpddr; ///< Offset 108 Throttler CKE min timer for LPDDR: 0=Minimal, 0xFF=Maximum, <b>0x00=Default</b>
+ BOOLEAN PerBankRefresh; ///< Offset 109 Enables and Disables the per bank refresh. This only impacts memory technologies that support PBR: LPDDR4, LPDDR5 and DDR5. FALSE=Disabled, <b>TRUE=Enabled</b>
+ UINT8 SaGv; ///< Offset 110 SA GV: <b>0=Disabled</b>, 1=Point1, 2=Point2, 3=Point3, 4=Point4, 5=Enabled
+ UINT8 NModeSupport; ///< Offset 111 Memory N Mode Support - Enable user to select Auto, 1N or 2N: <b>0=AUTO</b>, 1=1N, 2=2N.
+ UINT8 RefClk; ///< Offset 112 Selects the DDR base reference clock. 0x01 = 100MHz, <b>0x00 = 133MHz</b>
+ UINT8 EnCmdRate; ///< Offset 113 CMD Rate Enable: 0=Disable, 5=2 CMDs, <b>7=3 CMDs</b>, 9=4 CMDs, 11=5 CMDs, 13=6 CMDs, 15=7 CMDs
+ UINT8 Refresh2X; ///< Offset 114 Refresh 2x: <b>0=Disable</b>, 1=Enable for WARM or HOT, 2=Enable for HOT only
+ UINT8 EpgEnable; ///< Offset 115 Enable Energy Performance Gain.
+ UINT8 UserThresholdEnable; ///< Offset 116 Flag to manually select the DIMM CLTM Thermal Threshold, 0=Disable, 1=Enable, <b>0=Default</b>
+ UINT8 UserBudgetEnable; ///< Offset 117 Flag to manually select the Budget Registers for CLTM Memory Dimms , 0=Disable, 1=Enable, <b>0=Default</b>
+ UINT8 RetrainOnFastFail; ///< Offset 118 Restart MRC in Cold mode if SW MemTest fails during Fast flow. 0 = Disabled, <b>1 = Enabled</b>
+ UINT8 PowerDownMode; ///< Offset 119 CKE Power Down Mode: <b>0xFF=AUTO</b>, 0=No Power Down, 1= APD mode, 6=PPD-DLL Off mode
+ UINT8 PwdwnIdleCounter; ///< Offset 120 CKE Power Down Mode Idle Counter: 0=Minimal, 255=Maximum, <b>0x80=0x80 DCLK</b>
+ UINT8 CmdRanksTerminated; ///< Offset 121 LPDDR: Bitmask of ranks that have CA bus terminated. <b>0x01=Default, Rank0 is terminating and Rank1 is non-terminating</b>
+ UINT16 MsHashMask; ///< Offset 122 Controller Hash Mask: 0x0001=BIT6 set(Minimal), 0x3FFF=BIT[19:6] set(Maximum), <b>0x30CE= BIT[19:18, 13:12 ,9:7] set</b>
+ UINT32 Lp5CccConfig; ///< Offset 124 BitMask where bits [3:0] are controller 0 Channel [3:0] and [7:4] are Controller 1 Channel [3:0]. 0 selects Ascending mapping and 1 selects Descending mapping.
+ UINT8 RMTLoopCount; ///< Offset 128 Indicates the Loop Count to be used for Rank Margin Tool Testing: 1=Minimal, 32=Maximum, 0=AUTO, <b>0=Default</b>
+ UINT8 MsHashInterleaveBit; ///< Offset 129 Option to select interleave Address bit. Valid values are 0 - 3 for BITS 6 - 9
+ UINT8 GearRatio; ///< Offset 130 Gear mode when SAGV is disabled: <b>0=Auto</b>, 1 - Gear1, 2 - Gear2, 4 - Gear4.
+ UINT8 Ddr4OneDpc; ///< Offset 131 DDR4 1DPC performance feature: 0 - Disabled; 1 - Enabled on DIMM0 only, 2 - Enabled on DIMM1 only; 3 - Enabled on both DIMMs. (bit [0] - DIMM0, bit [1] - DIMM1)
+ UINT32 BclkRfiFreq[MEM_MAX_SAGV_POINTS]; ///< Offset 132 Bclk RFI Frequency for each SAGV point in Hz units. 98000000Hz = 98MHz <b>0 - No RFI Tuning</b>. Range is 98Mhz-100Mhz.
+ UINT16 SaGvFreq[MEM_MAX_SAGV_POINTS]; ///< Offset 148 Frequency per SAGV point. 0 is Auto, otherwise holds the frequency value expressed as an integer: <b>0=Default</b>, 1067, 1333, 1600, 1800, 1867, etc.
+ UINT8 SaGvGear[MEM_MAX_SAGV_POINTS]; ///< Offset 156 Gear ratio per SAGV point. 0 is Auto, otherwise holds the Gear ratio expressed as an integer: <b>0=Auto</b>, 1, 2, 4
+ UINT8 IbeccProtectedRangeEnable[MEM_MAX_IBECC_REGIONS]; ///< Offset 160 Enable use of address range for ECC Protection: <b>0=Disabled</b>, 1=Enabled
+ UINT32 IbeccProtectedRangeBase[MEM_MAX_IBECC_REGIONS]; ///< Offset 168 Base address for address range of ECC Protection: [0..0x3FFFFFF]
+ UINT32 IbeccProtectedRangeMask[MEM_MAX_IBECC_REGIONS]; ///< Offset 200 Mask address for address range of ECC Protection: [1..0x3FFFFFF]
+
+ UINT8 McRefresh2X; ///< Offset 232 Deprecated from revision 19, use McRefreshRate instead
+ UINT8 Lfsr0Mask; ///< Offset 233 RH pTRR LFSR0 Mask
+ UINT8 Lfsr1Mask; ///< Offset 234 RH pTRR LFSR1 Mask
+ UINT8 CmdMirror; ///< Offset 235 BitMask where bits [3:0] are controller 0 Channel [3:0] and [7:4] are Controller 1 Channel [3:0]. 0 = No Command Mirror and 1 = Command Mirror.
+ UINT8 AllowOppRefBelowWriteThrehold; ///< Offset 236 Option to allow opportunistic refreshes while we don't exit power down.
+ UINT8 WriteThreshold; ///< Offset 237 Option to set number of writes that can be accumulated while CKE is low before CKE is asserted.
+ UINT8 PprEnable; ///< Offset 238 Post-Package Repair: 0: Disabled, 2: Hard PPR
+ UINT8 MarginLimitCheck; ///< Offset 239 Margin limit check enable: <b>0=Disable</b>, 1=L1 only, 2=L2 only, 3=Both L1 and L2
+ UINT16 MarginLimitL2; ///< Offset 240 Margin limit check L2 threshold: <b>100=Default</b>
+ UINT8 LpddrRttWr; ///< Offset 242 Initial RttWr for LP4/5 in Ohms, 0 means Auto
+ UINT8 LpddrRttCa; ///< Offset 243 Initial RttCa for LP4/5 in Ohms, 0 means Auto
+ UINT16 VddqVoltage; ///< Offset 244 DRAM voltage (Vddq) in millivolts: <b>0=Platform Default (no override)</b>, 1200=1.2V, 1350=1.35V etc.
+ UINT16 VppVoltage; ///< Offset 246 DRAM voltage (Vpp) in millivolts: <b>0=Platform Default (no override)</b>, 1800=1.8V, 2050=2.05V etc.
+ UINT8 ExtendedBankHashing; ///< Offset 248 Enable EBH (Extended Bank Hashing): 0=Disabled; <b>1 = Enabled</b>
+ UINT8 DynamicMemoryBoost; ///< Offset 249 Enable/Disable Dynamic Memory Boost Feature. Only valid if SpdProfileSelected is an XMP Profile; otherwise ignored. <b>0=Disabled</b>, 1=Enabled.
+ UINT8 IbeccErrInjControl; ///< Offset 250 In-band ECC: Error Injection Control 0: No Error Injection, 1:Inject Correctable Error Address match, 3:Inject Correctable Error on insertion counter, 5: Inject Uncorrectable Error Address match, 7:Inject Uncorrectable Error on insertion counter
+ UINT8 RealtimeMemoryFrequency; ///< Offset 251 Enable/Disable Realtime Memory Frequency feature. Only valid if SpdProfileSelected is an XMP Profile; otherwise ignored. <b>0=Disabled</b>, 1=Enabled.
+ UINT32 IbeccErrInjCount; ///< Offset 252 Number of transactions between ECC error injection
+ UINT64 IbeccErrInjAddress; ///< Offset 256 Address to match against for ECC error injection
+ UINT64 IbeccErrInjMask; ///< Offset 264 Mask to match against for ECC error injection
+ UINT8 RefreshWm; ///< Offset 272 Refresh Watermarks, 0 = Low, <b>1 = High</b>
+ UINT8 McRefreshRate; ///< Offset 273 Type of solution to be used for RHP - 0/1/2/3 = RefreshNORMAL/Refresh1x/Refresh2x/Refresh4x
+ UINT8 Reserved274[2]; ///< Offset 274-275 Reserved for natural alignment
+ UINT32 DebugValue; ///< Offset 276 Debug Value for general use
+ UINT16 tRFCpb; ///< Offset 280 User defined Memory Timing tRFCpb value, valid when SpdProfileSelected is CUSTOM_PROFILE: <b>0=AUTO</b>, 28=Maximum.
+ UINT16 tRFC2; ///< Offset 282 User defined Memory Timing tRFC2 value, valid when SpdProfileSelected is CUSTOM_PROFILE: <b>0=AUTO</b>, 28=Maximum.
+ UINT16 tRFC4; ///< Offset 284 User defined Memory Timing tRFC4 value, valid when SpdProfileSelected is CUSTOM_PROFILE: <b>0=AUTO</b>, 28=Maximum.
+ UINT16 tRRD_L; ///< Offset 286 User defined Memory Timing tRRD_L value, valid when SpdProfileSelected is CUSTOM_PROFILE: <b>0=AUTO</b>, 28=Maximum.
+ UINT16 tRRD_S; ///< Offset 288 User defined Memory Timing tRRD_S value, valid when SpdProfileSelected is CUSTOM_PROFILE: <b>0=AUTO</b>, 28=Maximum.
+ UINT16 tWTR_L; ///< Offset 290 User defined Memory Timing tWTR_L value, valid when SpdProfileSelected is CUSTOM_PROFILE: <b>0=AUTO</b>, 28=Maximum.
+ UINT16 tCCD_L; ///< Offset 292 User defined Memory Timing tCCD_L value, valid when SpdProfileSelected is CUSTOM_PROFILE: <b>0=AUTO</b>, 28=Maximum.
+ UINT16 tWTR_S; ///< Offset 294 User defined Memory Timing tWTR_S value, valid when SpdProfileSelected is CUSTOM_PROFILE: <b>0=AUTO</b>, 28=Maximum.
+ UINT64 EccErrInjAddress; ///< Offset 296 Address to match against for ECC error injection
+ UINT64 EccErrInjMask; ///< Offset 304 Mask to match against for ECC error injection
+ UINT32 EccErrInjCount; ///< Offset 312 Number of transactions between ECC error injection
+
+
+ UINT16 FreqLimitMixedConfig; ///< Offset 316 Override the reduced speed in mixed 2DPC config or non-POR 2DPC config. <b>0=Auto</b>, otherwise speed in MT/s: 1067, 1333 etc. See the possible values in MrcInterface.h
+ UINT8 FirstDimmBitMask; ///< Offset 318 Defines which DIMM should be populated first on a 2DPC board.
+ ///< 4 bit mask: Bit[0]: MC0 DIMM0, Bit[1]: MC0 DIMM1, Bit[2]: MC1 DIMM0, Bit[3]: MC1 DIMM1.
+ ///< For each MC, the first DIMM to be populated should be set to '1'.
+ ///< Note: this mask is only for non-ECC DIMM.
+ UINT8 UserBd; ///< Offset 319 MrcBoardType
+ ///< 1 - Desktop 1DPC
+ ///< 2 - Desktop 2DPC, Daisy Chain, far DIMM should be populated first
+ ///< 3 - Desktop 2DPC, T-topology with asymmetrical DIMM0/1 routing, has particular DIMM population order
+ ///< 4 - Desktop 2DPC, T-topology with symmetrical DIMM0/1 routing, no particular DIMM population order
+ ///< 5 - ULT Mobile
+ UINT8 SagvSwitchFactorIA; ///< Offset 320 Sagv Switch Factor: <b>1 </b>, 50=Maximum, default 30.
+ UINT8 SagvSwitchFactorGT; ///< Offset 321 Sagv Switch Factor: <b>1 </b>, 50=Maximum, default 30.
+ UINT8 SagvSwitchFactorIO; ///< Offset 322 Sagv Switch Factor: <b>1 </b>, 50=Maximum, default 30.
+ UINT8 SagvSwitchFactorStall; ///< Offset 323 Sagv Switch Factor: <b>1 </b>, 50=Maximum, default 30.
+ UINT8 SagvHeuristicsUpControl;///< Offset 324 Sagv duration in ms before heuristics up: <b>1 </b>, 50=Maximum, default 1ms.
+ UINT8 SagvHeuristicsDownControl; ///< Offset 325 Sagv duration in ms before heuristics down: <b>1 </b>, 50=Maximum, default 1ms.
+ UINT16 FreqLimitMixedConfig_1R1R_8GB; ///< Offset 326 The frequency limit for mixed DIMM configuration 1R1R_8GB (1R 8GB and 1R 8GB in one channel).
+ ///< It's to be set by customer. Customer can connect it to a setup option, or an UPD, etc. By default, the value will be 2000.
+ UINT16 FreqLimitMixedConfig_1R1R_16GB; ///< Offset 328 The frequency limit for mixed DIMM configuration 1R1R_16GB (1R 16GB and 1R 16GB in one channel).
+ ///< It's to be set by customer. Customer can connect it to a setup option, or an UPD, etc. By default, the value will be 2000.
+ UINT16 FreqLimitMixedConfig_1R1R_8GB_16GB; ///< Offset 330 The frequency limit for mixed DIMM configuration 1R1R_8GB_16GB (1R 8GB and 1R 16GB in one channel).
+ ///< It's to be set by customer. Customer can connect it to a setup option, or an UPD, etc. By default, the value will be 2000.
+ UINT16 FreqLimitMixedConfig_2R2R; ///< Offset 332 The frequency limit for mixed DIMM configuration 2R_2R (2R 32GB and 2R 32GB in one channel).
+ ///< It's to be set by customer. Customer can connect it to a setup option, or an UPD, etc. By default, the value will be 2000.
+ UINT16 LctCmdEyeWidth; ///< Offset 334 LCT Command eyewidth
+ UINT8 FirstDimmBitMaskEcc; ///< Offset 336 Defines which ECC DIMM should be populated first on a 2DPC board.
+ ///< 4 bit mask: Bit[0]: MC0 DIMM0, Bit[1]: MC0 DIMM1, Bit[2]: MC1 DIMM0, Bit[3]: MC1 DIMM1.
+ ///< For each MC, the first DIMM to be populated should be set to '1'.
+ ///< For example, if one MC is T-topology, there is no special population rule, can put it as 11 for this MC and it means either D0 or D1 can be
+ ///< be populated firstly.
+ ///< Note: this mask is only for ECC DIMM, not for non-ECC DIMM.
+ UINT8 Lp5BankMode; ///< Offset 337 LP5 Bank Mode
+ UINT8 OverloadSAM; ///< Offset 338 Overload SAM to copy the sagv frquency point.
+ UINT8 Reserved339[5]; ///< Offset 339-343 Reserved for natural alignment
+} MEMORY_CONFIGURATION;
+
+/// Memory Configuration
+/// The contents of this structure are not CRC'd by the MRC for option change detection.
+/// <b>Revision 1</b>: - Initial version.
+/// <b>Revision 2</b>: - Added MemTestOnWarmBoot
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Block Header
+ SA_FUNCTION_CALLS SaCall; ///< Offset 28 Function calls into the SA.
+ SA_MEMORY_FUNCTIONS MrcCall; ///< Offset 212 Function calls into the MRC.
+ SPD_DATA_BUFFER *SpdData; ///< Offset 236 Memory SPD data, will be used by the MRC when SPD SmBus address is zero.
+ SA_MEMORY_DQDQS_MAPPING *DqDqsMap; ///< Offset 240 LPDDR DQ bit and DQS byte swizzling between CPU and DRAM.
+ SA_MEMORY_RCOMP *RcompData; ///< Offset 244 DDR RCOMP resistors and target values.
+ UINT64 PlatformMemorySize; ///< Offset 248 The minimum platform memory size required to pass control into DXE
+ UINT32 CleanMemory:1; ///< Offset 256 Ask MRC to clear memory content: <b>FALSE=Do not Clear Memory</b>; TRUE=Clear Memory
+ UINT32 ReservedBits5:31;
+ /**
+ Sets the serial debug message level\n
+ 0x00 = Disabled\n
+ 0x01 = Errors only\n
+ 0x02 = Errors and Warnings\n
+ <b>0x03 = Errors, Warnings, and Info</b>\n
+ 0x04 = Errors, Warnings, Info, and Events\n
+ 0x05 = Displays Memory Init Execution Time Summary only\n
+ **/
+ UINT8 SerialDebugLevel; ///< Offset 260
+ UINT8 MemTestOnWarmBoot; ///< Offset 261 Run Base Memory Test On WarmBoot: 0=Disabled, <b>1=Enabled</b>
+ UINT8 Reserved11[2]; ///< Offset 262 - 263 Reserved
+} MEMORY_CONFIG_NO_CRC;
+#pragma pack(pop)
+
+#endif // _MEMORY_CONFIG_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/PchDmi/PchDmiConfig.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/PchDmi/PchDmiConfig.h
new file mode 100644
index 0000000000..84cc21091f
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/PchDmi/PchDmiConfig.h
@@ -0,0 +1,65 @@
+/** @file
+ DMI policy
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _PCH_DMI_CONFIG_H_
+#define _PCH_DMI_CONFIG_H_
+
+extern EFI_GUID gPchDmiConfigGuid;
+
+/*
+<b>Revision 1</b>: - Initial version.
+*/
+#define PCH_DMI_PREMEM_CONFIG_REVISION 1
+extern EFI_GUID gPchDmiPreMemConfigGuid;
+
+#pragma pack (push,1)
+
+#define PCH_DMI_HWEQ_COEFFS_MAX 8
+/**
+ Lane specific Dmi Gen3, Gen4 equalization parameters.
+**/
+typedef struct {
+ UINT8 Cm; ///< Coefficient C-1
+ UINT8 Cp; ///< Coefficient C+1
+ UINT8 Rsvd0[2]; ///< Reserved bytes
+} PCH_DMI_EQ_PARAM;
+
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Config Block
+ PCH_DMI_EQ_PARAM DmiHwEqGen3CoeffList[PCH_DMI_HWEQ_COEFFS_MAX];
+ UINT8 DmiHweq;
+ UINT8 Reserved[3];
+} PCH_DMI_PREMEM_CONFIG;
+
+
+/**
+ The PCH_DMI_CONFIG block describes the expected configuration of the PCH for DMI.
+ <b>Revision 1</b>:
+ - Initial version.
+**/
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Config Block Header
+
+ UINT32 PwrOptEnable : 1; ///< <b>0: Disable</b>; 1: Enable DMI Power Optimizer on PCH side.
+ UINT32 DmiAspmCtrl : 8; ///< ASPM configuration on the PCH side of the DMI/OPI Link. Default is <b>PchPcieAspmAutoConfig</b>
+ UINT32 CwbEnable : 1; ///< 0: Disable; <b>1: Enable</b> Central Write Buffer feature configurable and enabled by default
+ UINT32 L1RpCtl : 1; ///< 0: Disable; <b>1: Enable</b> Allow DMI enter L1 when all root ports are in L1, L0s or link down. Disabled by default.
+ /**
+ When set to TRUE turns on:
+ - L1 State Controller Power Gating
+ - L1 State PHY Data Lane Power Gating
+ - PHY Common Lane Power Gating
+ - Hardware Autonomous Enable
+ - PMC Request Enable and Sleep Enable
+ **/
+ UINT32 DmiPowerReduction : 1;
+ UINT32 ClockGating : 1; ///< 0: Disable; 1: Enable clock gating.
+ UINT32 Rsvdbits : 19; ///< Reserved bits
+} PCH_DMI_CONFIG;
+
+#pragma pack (pop)
+
+#endif // _PCH_DMI_CONFIG_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/PcieRp/PchPcieRp/PchPcieRpConfig.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/PcieRp/PchPcieRp/PchPcieRpConfig.h
new file mode 100644
index 0000000000..d97f3b878a
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/PcieRp/PchPcieRp/PchPcieRpConfig.h
@@ -0,0 +1,180 @@
+/** @file
+ PCH Pcie root port policy
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _PCH_PCIERP_CONFIG_H_
+#define _PCH_PCIERP_CONFIG_H_
+
+#include <PchLimits.h>
+#include <PcieConfig.h>
+#include <ConfigBlock.h>
+
+
+
+
+
+/*
+ Making any setup structure change after code frozen
+ will need to maintain backward compatibility, bump up
+ structure revision and update below history table\n
+
+<b>Revision 1</b>: - Initial version.
+*/
+#define PCIE_RP_DXE_CONFIG_REVISION 1
+
+extern EFI_GUID gPchPcieConfigGuid;
+extern EFI_GUID gPcieRpPreMemConfigGuid;
+
+#pragma pack (push,1)
+
+typedef enum {
+ PchPcieOverrideDisabled = 0,
+ PchPcieL1L2Override = 0x01,
+ PchPcieL1SubstatesOverride = 0x02,
+ PchPcieL1L2AndL1SubstatesOverride = 0x03,
+ PchPcieLtrOverride = 0x04
+} PCH_PCIE_OVERRIDE_CONFIG;
+
+///
+/// The values before AutoConfig match the setting of PCI Express Base Specification 1.1, please be careful for adding new feature
+///
+typedef enum {
+ PchPcieAspmDisabled,
+ PchPcieAspmL0s,
+ PchPcieAspmL1,
+ PchPcieAspmL0sL1,
+ PchPcieAspmAutoConfig,
+ PchPcieAspmMax
+} PCH_PCIE_ASPM_CONTROL;
+
+/**
+ Refer to PCH EDS for the PCH implementation values corresponding
+ to below PCI-E spec defined ranges
+**/
+typedef enum {
+ PchPcieL1SubstatesDisabled,
+ PchPcieL1SubstatesL1_1,
+ PchPcieL1SubstatesL1_1_2,
+ PchPcieL1SubstatesMax
+} PCH_PCIE_L1SUBSTATES_CONTROL;
+
+enum PCH_PCIE_MAX_PAYLOAD {
+ PchPcieMaxPayload128 = 0,
+ PchPcieMaxPayload256,
+ PchPcieMaxPayloadMax
+};
+
+
+/**
+ PCH_PCIE_CLOCK describes PCIe source clock generated by PCH.
+**/
+typedef struct {
+ UINT8 Usage; ///< Purpose of given clock (see PCH_PCIE_CLOCK_USAGE). Default: Unused, 0xFF
+ UINT8 ClkReq; ///< ClkSrc - ClkReq mapping. Default: 1:1 mapping with Clock numbers
+ UINT8 RsvdBytes[2]; ///< Reserved byte
+ UINT32 ClkReqGpioPinMux; /// Muxed GPIO details. Refer GPIO_*_MUXING_SRC_CLKREQ_x*
+} PCH_PCIE_CLOCK;
+
+
+/**
+ The PCH_PCI_EXPRESS_ROOT_PORT_CONFIG describe the feature and capability of each PCH PCIe root port.
+**/
+typedef struct {
+ PCIE_ROOT_PORT_COMMON_CONFIG PcieRpCommonConfig; ///an instance of Pcie Common Config
+ UINT8 ExtSync; ///< Indicate whether the extended synch is enabled. <b>0: Disable</b>; 1: Enable.
+ //
+ // Error handlings
+ //
+ UINT8 SystemErrorEnable; ///< Indicate whether the System Error is enabled. <b>0: Disable</b>; 1: Enable.
+ /**
+ The Multiple VC (MVC) supports hardware to avoid HoQ block for latency sensitive TC.
+ Currently it is only applicable to Root Ports with 2pX4 port configuration with 2 VCs,or
+ DMI port configuration with 3 VCs. For Root Ports 2pX4 configuration, two RPs (RP0,
+ RP2) shall support two PCIe VCs (VC0 & VC1) and the other RPs (RP1, RP3) shall be
+ disabled.
+ <b>0: Disable</b>; 1: Enable
+ **/
+ UINT8 MvcEnabled;
+ /**
+ Virtual Pin Port is industry standard introduced to PCIe Hot Plug support in systems
+ when GPIO pins expansion is needed. It is server specific feature.
+ <b>0x00: Default</b>; 0xFF: Disabled
+ **/
+ UINT8 VppPort;
+ UINT8 VppAddress; ///< PCIe Hot Plug VPP SMBus Address. Default is zero.
+ UINT8 RsvdBytes0[3]; ///< Reserved bytes
+} PCH_PCIE_ROOT_PORT_CONFIG;
+
+/**
+ The PCH_PCIE_CONFIG block describes the expected configuration of the PCH PCI Express controllers
+ <b>Revision 1</b>:
+ - Initial version.
+ <b>Revision 2</b>:
+ - Moved EnablePort8xhDecode policy to PCIE_COMMON_CONFIG
+**/
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Config Block Header
+ ///
+ /// These members describe the configuration of each PCH PCIe root port.
+ ///
+ PCIE_COMMON_CONFIG PcieCommonConfig;
+ PCH_PCIE_ROOT_PORT_CONFIG RootPort[PCH_MAX_PCIE_ROOT_PORTS];
+ PCH_PCIE_ROOT_PORT_CONFIG DmiPort;
+
+ ///
+ /// <b>(Test)</b> The Index of PCIe Port that is selected for Port8xh Decode (0 Based)
+ ///
+ UINT8 PchPciePort8xhDecodePortIndex;
+ UINT8 DmiPowerReduction;
+ UINT8 RsvdBytes0[2];
+} PCH_PCIE_CONFIG;
+
+/**
+ The PCH_PCIE_RP_PREMEM_CONFIG block describes early configuration of the PCH PCI Express controllers
+ <b>Revision 1</b>:
+ - Initial version.
+**/
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Config Block Header
+ /**
+ Root Port enabling mask.
+ Bit0 presents RP1, Bit1 presents RP2, and so on.
+ 0: Disable; <b>1: Enable</b>.
+ **/
+ UINT32 RpEnabledMask;
+ /// Configuration of PCIe source clocks
+ ///
+ PCH_PCIE_CLOCK PcieClock[PCH_MAX_PCIE_CLOCKS];
+
+ /**
+ Per Controller Bifurcation Configuration
+ <b>0: Disabled</b>; 1: 4x1; 2: 1x2_2x1; 3: 2x2; 4: 1x4; 5: 4x2; 6: 1x4_2x2; 7: 2x2_1x4; 8: 2x4; 9: 1x8 (see: PCIE_BIFURCATION_CONFIG)
+ **/
+ UINT8 Bifurcation[PCH_MAX_PCIE_CONTROLLERS];
+ UINT8 Rsvd4[(4 - PCH_MAX_PCIE_CONTROLLERS % 4) % 4];
+} PCH_PCIE_RP_PREMEM_CONFIG;
+
+/**
+ The PCIE_RP_DXE_CONFIG block describes the expected configuration of the PCH PCI Express controllers in DXE phase
+
+ <b>Revision 1</b>:
+ - Init version
+**/
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Config Block Header
+
+ /**
+ PCIe device override table
+ The PCIe device table is being used to override PCIe device ASPM settings.
+ And it's only used in DXE phase.
+ Please refer to PCIE_DEVICE_OVERRIDE structure for the table.
+ Last entry VendorId must be 0.
+ **/
+ PCIE_DEVICE_OVERRIDE *PcieDeviceOverrideTablePtr;
+} PCIE_RP_DXE_CONFIG;
+
+#pragma pack (pop)
+
+#endif // _PCH_PCIERP_CONFIG_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/PcieRp/PcieConfig.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/PcieRp/PcieConfig.h
new file mode 100644
index 0000000000..07a5644f43
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/PcieRp/PcieConfig.h
@@ -0,0 +1,408 @@
+/** @file
+ PCIe Config Block
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _PCIE_CONFIG_H_
+#define _PCIE_CONFIG_H_
+#include <CpuPcieInfo.h>
+
+#define PCIE_LINK_EQ_COEFFICIENTS_MAX 10
+#define PCIE_LINK_EQ_PRESETS_MAX 11
+extern EFI_GUID gPcieConfigGuid;
+
+#pragma pack (push,1)
+
+enum PCIE_COMPLETION_TIMEOUT {
+ PcieCompletionTO_Default,
+ PcieCompletionTO_50_100us,
+ PcieCompletionTO_1_10ms,
+ PcieCompletionTO_16_55ms,
+ PcieCompletionTO_65_210ms,
+ PcieCompletionTO_260_900ms,
+ PcieCompletionTO_1_3P5s,
+ PcieCompletionTO_4_13s,
+ PcieCompletionTO_17_64s,
+ PcieCompletionTO_Disabled
+};
+
+typedef enum {
+ PcieAuto,
+ PcieGen1,
+ PcieGen2,
+ PcieGen3,
+ PcieGen4,
+ PcieGen5
+} PCIE_SPEED;
+
+typedef enum {
+ PcieDisabled,
+ PcieL1SUB_1,
+ PcieL1SUB_1_2
+}L1_SUBSTATES;
+
+/**
+ Represent lane specific PCIe Gen3 equalization parameters.
+**/
+typedef struct {
+ UINT8 Cm; ///< Coefficient C-1
+ UINT8 Cp; ///< Coefficient C+1
+ UINT8 Rsvd0[2]; ///< Reserved bytes
+} PCIE_EQ_PARAM;
+
+typedef struct {
+ UINT16 LtrMaxSnoopLatency; ///< <b>(Test)</b> Latency Tolerance Reporting, Max Snoop Latency.
+ UINT16 LtrMaxNoSnoopLatency; ///< <b>(Test)</b> Latency Tolerance Reporting, Max Non-Snoop Latency.
+ UINT8 SnoopLatencyOverrideMode; ///< <b>(Test)</b> Latency Tolerance Reporting, Snoop Latency Override Mode.
+ UINT8 SnoopLatencyOverrideMultiplier; ///< <b>(Test)</b> Latency Tolerance Reporting, Snoop Latency Override Multiplier.
+ UINT16 SnoopLatencyOverrideValue; ///< <b>(Test)</b> Latency Tolerance Reporting, Snoop Latency Override Value.
+ UINT8 NonSnoopLatencyOverrideMode; ///< <b>(Test)</b> Latency Tolerance Reporting, Non-Snoop Latency Override Mode.
+ UINT8 NonSnoopLatencyOverrideMultiplier; ///< <b>(Test)</b> Latency Tolerance Reporting, Non-Snoop Latency Override Multiplier.
+ UINT16 NonSnoopLatencyOverrideValue; ///< <b>(Test)</b> Latency Tolerance Reporting, Non-Snoop Latency Override Value.
+ UINT8 LtrConfigLock; ///< <b>0: Disable</b>; 1: Enable.
+ UINT8 ForceLtrOverride;
+ UINT16 RsvdByte1;
+} PCIE_LTR_CONFIG;
+
+
+/**
+ Specifies the form factor that the slot
+ implements. For custom form factors that
+ do not require any special handling please
+ set PcieFormFactorOther.
+**/
+typedef enum {
+ PcieFormFactorOther = 0,
+ PcieFormFactorCem,
+ PcieFormFactorMiniPci,
+ PcieFormFactorM2,
+ PcieFormFactorOcuLink,
+ PcieFormFactorExpressModule, // Also known as Server IO module(SIOM)
+ PcieFormFactorExpressCard,
+ PcieFormFactorU2 // Also known as SF-8639
+} PCIE_FORM_FACTOR;
+
+typedef enum {
+ PcieLinkHardwareEq = 0, ///< Hardware is responsible for performing coefficient/preset search.
+ PcieLinkFixedEq ///< No coefficient/preset search is performed. Fixed values are used.
+} PCIE_LINK_EQ_METHOD;
+
+typedef enum {
+ PcieLinkEqPresetMode = 0, ///< Use presets during PCIe link equalization
+ PcieLinkEqCoefficientMode ///< Use coefficients during PCIe link equalization
+} PCIE_LINK_EQ_MODE;
+
+typedef struct {
+ UINT32 PreCursor; ///< Pre-cursor coefficient
+ UINT32 PostCursor; ///< Post-cursor coefficient
+} PCIE_LINK_EQ_COEFFICIENTS;
+
+/**
+ PCIe Link EQ Platform Settings
+**/
+typedef struct {
+ UINT8 PcieLinkEqMethod; ///< Tells BIOS which link EQ method should be used for this port. Please refer to PCIE_LINK_EQ_METHOD for details of supported methods. Default: PcieLinkHardwareEq
+ UINT8 PcieLinkEqMode; ///< Tells BIOS which mode should be used for PCIe link EQ. Please refer to PCIE_LINK_EQ_MODE for details of supported modes. Default: depends on SoC
+ /**
+ Specifies if BIOS should perform local transmitter override during phase 2 of EQ process.
+ If enabled value in Ph2LocalTransmitterOverridePreset must be valid.
+ <b>0: Disabled</b>; 1: Enabled
+ **/
+ UINT8 LocalTransmitterOverrideEnable;
+ /**
+ Tells BIOS how many presets/coefficients should be used during link EQ.
+ Entries in the Ph3CoefficientsList or Ph3PresetList(depending on chosen mode) need to be valid up to the number specified in this field.
+ **/
+ UINT8 Ph3NumberOfPresetsOrCoefficients;
+
+ PCIE_LINK_EQ_COEFFICIENTS Ph3CoefficientsList[PCIE_LINK_EQ_COEFFICIENTS_MAX]; ///< List of the PCIe coefficients to be used during equalization process. Only valid if PcieLinkEqMode is PcieLinkEqCoefficientMode
+ UINT32 Ph3PresetList[PCIE_LINK_EQ_PRESETS_MAX]; ///< List of the PCIe preset values to be used during equalization process. Only valid if PcieLinkEqMode is PcieLinkEqPresetMode
+ UINT32 Ph1DownstreamPortTransmitterPreset; ///< Specifies the value of the downstream port transmitter preset to be used during phase 1 of the equalization process. Will be applied to all lanes
+ UINT32 Ph1UpstreamPortTransmitterPreset; ///< Specifies the value of the upstream port transmitter preset to be used during phase 1 of the equalization process. Will be applied to all lanes
+ /**
+ Specifies the preset that should be used during local transmitter override during phase 2 of EQ process.
+ Used only if LocalTransmitterOverrideEnable is TRUE. Will be applied to all PCIe lanes of the root port.
+ Valid up to the PCIE_LINK_EQ_PRESET_MAX value. <b>Default: 0<\b>
+ **/
+ UINT32 Ph2LocalTransmitterOverridePreset;
+ UINT32 PCETTimer; ///< PCET Timer value for single PCIe speed.
+ UINT8 RemotePresetCoeffoverride; ///< Remote Transmitter Preset Coefficient Override for single PCIe speed.
+ /**
+ PCIe Equalization Phase 3 Enable Control
+ - <b>Disabled</b> (0x0) : Disable phase 3 (Default)
+ - Enabled (0x1) : Enable phase 3
+ **/
+ UINT8 EqPh3Bypass;
+ /**
+ PCIe Equalization Phase 2-3 Enable Control
+ - <b>Disabled</b> (0x0) : Disable Phase 2 - Phase 3 (Default)
+ - Enabled (0x1) : Enable Phase 2 - Phase 3
+ **/
+ UINT8 EqPh23Bypass;
+ UINT8 TsLockTimer; ///< 8.0GT/s Training Sequence Wait Latency For Presets / Coefficients Evaluation - Gen3 TS Lock Timer
+} PCIE_LINK_EQ_PLATFORM_SETTINGS;
+
+//Note: This structure will be expanded to hold all common PCIe policies between SA and PCH RootPort
+typedef struct {
+ UINT32 HotPlug : 1; ///< Indicate whether the root port is hot plug available. <b>0: Disable</b>; 1: Enable.
+ UINT32 PmSci : 1; ///< Indicate whether the root port power manager SCI is enabled. 0: Disable; <b>1: Enable</b>.
+ UINT32 TransmitterHalfSwing : 1; ///< Indicate whether the Transmitter Half Swing is enabled. <b>0: Disable</b>; 1: Enable.
+ UINT32 AcsEnabled : 1; ///< Indicate whether the ACS is enabled. 0: Disable; <b>1: Enable</b>.
+ //
+ // Error handlings
+ //
+ UINT32 AdvancedErrorReporting : 1; ///< Indicate whether the Advanced Error Reporting is enabled. <b>0: Disable</b>; 1: Enable.
+ UINT32 UnsupportedRequestReport : 1; ///< Indicate whether the Unsupported Request Report is enabled. <b>0: Disable</b>; 1: Enable.
+ UINT32 FatalErrorReport : 1; ///< Indicate whether the Fatal Error Report is enabled. <b>0: Disable</b>; 1: Enable.
+ UINT32 NoFatalErrorReport : 1; ///< Indicate whether the No Fatal Error Report is enabled. <b>0: Disable</b>; 1: Enable.
+ UINT32 CorrectableErrorReport : 1; ///< Indicate whether the Correctable Error Report is enabled. <b>0: Disable</b>; 1: Enable.
+ UINT32 SystemErrorOnFatalError : 1; ///< Indicate whether the System Error on Fatal Error is enabled. <b>0: Disable</b>; 1: Enable.
+ UINT32 SystemErrorOnNonFatalError : 1; ///< Indicate whether the System Error on Non Fatal Error is enabled. <b>0: Disable</b>; 1: Enable.
+ UINT32 SystemErrorOnCorrectableError : 1; ///< Indicate whether the System Error on Correctable Error is enabled. <b>0: Disable</b>; 1: Enable.
+ /**
+ Max Payload Size supported, Default <b>128B</b>, see enum CPU_PCIE_MAX_PAYLOAD
+ Changes Max Payload Size Supported field in Device Capabilities of the root port.
+ **/
+ UINT32 MaxPayload : 2;
+ UINT32 DpcEnabled : 1; ///< Downstream Port Containment. 0: Disable; <b>1: Enable</b>
+ UINT32 RpDpcExtensionsEnabled : 1; ///< RP Extensions for Downstream Port Containment. 0: Disable; <b>1: Enable</b>
+ /**
+ Indicates how this root port is connected to endpoint. 0: built-in device; <b>1: slot</b>
+ Built-in is incompatible with hotplug-capable ports.
+ **/
+ UINT32 SlotImplemented : 1;
+ UINT32 PtmEnabled : 1; ///< Enables PTM capability
+ UINT32 SlotPowerLimitScale : 2; ///< <b>(Test)</b> Specifies scale used for slot power limit value. Leave as 0 to set to default. Default is <b>zero</b>.
+ UINT32 SlotPowerLimitValue : 12; //< <b>(Test)</b> Specifies upper limit on power supplies by slot. Leave as 0 to set to default. Default is <b>zero</b>.
+ /**
+ Probe CLKREQ# signal before enabling CLKREQ# based power management.
+ Conforming device shall hold CLKREQ# low until CPM is enabled. This feature attempts
+ to verify CLKREQ# signal is connected by testing pad state before enabling CPM.
+ In particular this helps to avoid issues with open-ended PCIe slots.
+ This is only applicable to non hot-plug ports.
+ <b>0: Disable</b>; 1: Enable.
+ **/
+ UINT32 ClkReqDetect : 1;
+ /**
+ Set if the slot supports manually operated retention latch.
+ **/
+ UINT32 MrlSensorPresent : 1;
+ UINT32 RelaxedOrder : 1;
+ UINT32 NoSnoop : 1;
+ ///
+ /// This member describes whether Peer Memory Writes are enabled on the platform. <b>0: Disable</b>; 1: Enable.
+ ///
+ UINT32 EnablePeerMemoryWrite : 1;
+ ///
+ /// This member describes whether the PCI Express Clock Gating for each root port
+ /// is enabled by platform modules. <b>0: Disable</b>; 1: Enable.
+ ///
+ UINT32 ClockGating : 1;
+ ///
+ /// This member describes whether the PCI Express Power Gating for each root port
+ /// is enabled by platform modules. <b>0: Disable</b>; 1: Enable.
+ ///
+ UINT32 PowerGating : 1;
+ UINT32 RsvdBits0 : 25; ///< Reserved bits.
+ /**
+ PCIe Gen3 Equalization Phase 3 Method (see CPU_PCIE_EQ_METHOD).
+ 0: DEPRECATED, hardware equalization; <b>1: hardware equalization</b>; 4: Fixed Coefficients
+ **/
+ UINT8 Gen3EqPh3Method;
+ UINT8 PhysicalSlotNumber; ///< Indicates the slot number for the root port. Default is the value as root port index.
+ UINT8 CompletionTimeout; ///< The completion timeout configuration of the root port (see: CPU_PCIE_COMPLETION_TIMEOUT). Default is <b>PchPcieCompletionTO_Default</b>.
+ //
+ // Power Management
+ //
+ UINT8 Aspm; ///< The ASPM configuration of the root port (see: CPU_PCIE_ASPM_CONTROL). Default is <b>PchPcieAspmAutoConfig</b>.
+ UINT8 L1Substates; ///< The L1 Substates configuration of the root port (see: CPU_PCIE_L1SUBSTATES_CONTROL). Default is <b>PchPcieL1SubstatesL1_1_2</b>.
+ UINT8 LtrEnable; ///< Latency Tolerance Reporting Mechanism. <b>0: Disable</b>; 1: Enable.
+ UINT8 EnableCpm; ///< Enables Clock Power Management; even if disabled, CLKREQ# signal can still be controlled by L1 PM substates mechanism
+ UINT8 PcieSpeed; ///< Contains speed of PCIe bus (see: PCIE_SPEED)
+ /**
+ <b>(Test)</b>
+ Forces LTR override to be permanent
+ The default way LTR override works is:
+ rootport uses LTR override values provided by BIOS until connected device sends an LTR message, then it will use values from the message
+ This settings allows force override of LTR mechanism. If it's enabled, then:
+ rootport will use LTR override values provided by BIOS forever; LTR messages sent from connected device will be ignored
+ **/
+ PCIE_LTR_CONFIG PcieRpLtrConfig; ///< <b>(Test)</b> Latency Tolerance Reporting Policies including LTR limit and Override
+ /**
+ The number of milliseconds reference code will wait for link to exit Detect state for enabled ports
+ before assuming there is no device and potentially disabling the port.
+ It's assumed that the link will exit detect state before root port initialization (sufficient time
+ elapsed since PLTRST de-assertion) therefore default timeout is zero. However this might be useful
+ if device power-up seqence is controlled by BIOS or a specific device requires more time to detect.
+ In case of non-common clock enabled the default timout is 15ms.
+ <b>Default: 0</b>
+ **/
+ UINT16 DetectTimeoutMs;
+ UINT8 FormFactor; // Please check PCIE_FORM_FACTOR for supported values
+ UINT8 L1Low; ///< L1.LOW enable/disable. <b>0: Disable</b>; 1: Enable.
+ UINT8 LinkDownGpios;
+ ///
+ /// <b>0: Use project default equalization settings</b>; 1: Use equalization settings from PcieLinkEqPlatformSettings
+ ///
+ UINT8 OverrideEqualizationDefaults;
+ UINT8 Reserved[2];
+ PCIE_LINK_EQ_PLATFORM_SETTINGS PcieGen3LinkEqPlatformSettings; ///< Global PCIe Gen3 link EQ settings that BIOS will use during PCIe link EQ for every port.
+ PCIE_LINK_EQ_PLATFORM_SETTINGS PcieGen4LinkEqPlatformSettings; ///< Global PCIe Gen4 link EQ settings that BIOS will use during PCIe link EQ for every port.
+ PCIE_LINK_EQ_PLATFORM_SETTINGS PcieGen5LinkEqPlatformSettings; ///< Global PCIe Gen5 link EQ settings that BIOS will use during PCIe link EQ for every port.
+} PCIE_ROOT_PORT_COMMON_CONFIG;
+
+/**
+ PCIe Common Config
+ @note This structure will be expanded to hold all common PCIe policies between SA and PCH
+**/
+typedef struct {
+ /**
+ RpFunctionSwap allows BIOS to use root port function number swapping when root port of function 0 is disabled.
+ A PCIE device can have higher functions only when Function0 exists. To satisfy this requirement,
+ BIOS will always enable Function0 of a device that contains more than 0 enabled root ports.
+ - <b>Enabled: One of enabled root ports get assigned to Function0.</b>
+ This offers no guarantee that any particular root port will be available at a specific DevNr:FuncNr location
+ - Disabled: Root port that corresponds to Function0 will be kept visible even though it might be not used.
+ That way rootport - to - DevNr:FuncNr assignment is constant. This option will impact ports 1, 9, 17.
+ NOTE: This option will not work if ports 1, 9, 17 are fused or configured for RST PCIe storage or disabled through policy
+ In other words, it only affects ports that would become hidden because they have no device connected.
+ NOTE: Disabling function swap may have adverse impact on power management. This option should ONLY
+ be used when each one of root ports 1, 9, 17:
+ - is configured as PCIe and has correctly configured ClkReq signal, or
+ - does not own any mPhy lanes (they are configured as SATA or USB)
+ **/
+ UINT32 RpFunctionSwap : 1;
+ /**
+ Compliance Test Mode shall be enabled when using Compliance Load Board.
+ <b>0: Disable</b>, 1: Enable
+ **/
+ UINT32 ComplianceTestMode : 1;
+ UINT32 RsvdBits0 : 30; ///< Reserved bits
+ ///
+ /// <b>(Test)</b> This member describes whether PCIE root port Port 8xh Decode is enabled. <b>0: Disable</b>; 1: Enable.
+ ///
+ UINT8 EnablePort8xhDecode;
+ UINT8 RsvdBytes0[3];
+ ///
+ /// List of coefficients used during equalization (applicable to both software and hardware EQ)
+ /// Deprecated Policy
+ ///
+ PCIE_EQ_PARAM HwEqGen3CoeffList[PCIE_HWEQ_COEFFS_MAX];
+} PCIE_COMMON_CONFIG;
+
+typedef struct {
+ PCIE_EQ_PARAM HwEqGen3CoeffList[CPU_PCIE_MAX_ROOT_PORTS][PCIE_HWEQ_COEFFS_MAX];
+ PCIE_EQ_PARAM HwEqGen4CoeffList[CPU_PCIE_MAX_ROOT_PORTS][PCIE_HWEQ_COEFFS_MAX];
+ PCIE_EQ_PARAM HwEqGen5CoeffList[CPU_PCIE_MAX_ROOT_PORTS][PCIE_HWEQ_COEFFS_MAX];
+} PCIE_COMMON_CONFIG2;
+
+
+/**
+ PCIe device table entry entry
+
+ The PCIe device table is being used to override PCIe device ASPM settings.
+ To take effect table consisting of such entries must be instelled as PPI
+ on gPchPcieDeviceTablePpiGuid.
+ Last entry VendorId must be 0.
+**/
+typedef struct {
+ UINT16 VendorId; ///< The vendor Id of Pci Express card ASPM setting override, 0xFFFF means any Vendor ID
+ UINT16 DeviceId; ///< The Device Id of Pci Express card ASPM setting override, 0xFFFF means any Device ID
+ UINT8 RevId; ///< The Rev Id of Pci Express card ASPM setting override, 0xFF means all steppings
+ UINT8 BaseClassCode; ///< The Base Class Code of Pci Express card ASPM setting override, 0xFF means all base class
+ UINT8 SubClassCode; ///< The Sub Class Code of Pci Express card ASPM setting override, 0xFF means all sub class
+ UINT8 EndPointAspm; ///< Override device ASPM (see: PCH_PCIE_ASPM_CONTROL)
+ ///< Bit 1 must be set in OverrideConfig for this field to take effect
+ UINT16 OverrideConfig; ///< The override config bitmap (see: PCH_PCIE_OVERRIDE_CONFIG).
+ /**
+ The L1Substates Capability Offset Override. (applicable if bit 2 is set in OverrideConfig)
+ This field can be zero if only the L1 Substate value is going to be override.
+ **/
+ UINT16 L1SubstatesCapOffset;
+ /**
+ L1 Substate Capability Mask. (applicable if bit 2 is set in OverrideConfig)
+ Set to zero then the L1 Substate Capability [3:0] is ignored, and only L1s values are override.
+ Only bit [3:0] are applicable. Other bits are ignored.
+ **/
+ UINT8 L1SubstatesCapMask;
+ /**
+ L1 Substate Port Common Mode Restore Time Override. (applicable if bit 2 is set in OverrideConfig)
+ L1sCommonModeRestoreTime and L1sTpowerOnScale can have a valid value of 0, but not the L1sTpowerOnValue.
+ If L1sTpowerOnValue is zero, all L1sCommonModeRestoreTime, L1sTpowerOnScale, and L1sTpowerOnValue are ignored,
+ and only L1SubstatesCapOffset is override.
+ **/
+ UINT8 L1sCommonModeRestoreTime;
+ /**
+ L1 Substate Port Tpower_on Scale Override. (applicable if bit 2 is set in OverrideConfig)
+ L1sCommonModeRestoreTime and L1sTpowerOnScale can have a valid value of 0, but not the L1sTpowerOnValue.
+ If L1sTpowerOnValue is zero, all L1sCommonModeRestoreTime, L1sTpowerOnScale, and L1sTpowerOnValue are ignored,
+ and only L1SubstatesCapOffset is override.
+ **/
+ UINT8 L1sTpowerOnScale;
+ /**
+ L1 Substate Port Tpower_on Value Override. (applicable if bit 2 is set in OverrideConfig)
+ L1sCommonModeRestoreTime and L1sTpowerOnScale can have a valid value of 0, but not the L1sTpowerOnValue.
+ If L1sTpowerOnValue is zero, all L1sCommonModeRestoreTime, L1sTpowerOnScale, and L1sTpowerOnValue are ignored,
+ and only L1SubstatesCapOffset is override.
+ **/
+ UINT8 L1sTpowerOnValue;
+
+ /**
+ SnoopLatency bit definition
+ Note: All Reserved bits must be set to 0
+
+ BIT[15] - When set to 1b, indicates that the values in bits 9:0 are valid
+ When clear values in bits 9:0 will be ignored
+ BITS[14:13] - Reserved
+ BITS[12:10] - Value in bits 9:0 will be multiplied with the scale in these bits
+ 000b - 1 ns
+ 001b - 32 ns
+ 010b - 1024 ns
+ 011b - 32,768 ns
+ 100b - 1,048,576 ns
+ 101b - 33,554,432 ns
+ 110b - Reserved
+ 111b - Reserved
+ BITS[9:0] - Snoop Latency Value. The value in these bits will be multiplied with
+ the scale in bits 12:10
+
+ This field takes effect only if bit 3 is set in OverrideConfig.
+ **/
+ UINT16 SnoopLatency;
+ /**
+ NonSnoopLatency bit definition
+ Note: All Reserved bits must be set to 0
+
+ BIT[15] - When set to 1b, indicates that the values in bits 9:0 are valid
+ When clear values in bits 9:0 will be ignored
+ BITS[14:13] - Reserved
+ BITS[12:10] - Value in bits 9:0 will be multiplied with the scale in these bits
+ 000b - 1 ns
+ 001b - 32 ns
+ 010b - 1024 ns
+ 011b - 32,768 ns
+ 100b - 1,048,576 ns
+ 101b - 33,554,432 ns
+ 110b - Reserved
+ 111b - Reserved
+ BITS[9:0] - Non Snoop Latency Value. The value in these bits will be multiplied with
+ the scale in bits 12:10
+
+ This field takes effect only if bit 3 is set in OverrideConfig.
+ **/
+ UINT16 NonSnoopLatency;
+
+ /**
+ Forces LTR override to be permanent
+ The default way LTR override works is:
+ rootport uses LTR override values provided by BIOS until connected device sends an LTR message, then it will use values from the message
+ This settings allows force override of LTR mechanism. If it's enabled, then:
+ rootport will use LTR override values provided by BIOS forever; LTR messages sent from connected device will be ignored
+ **/
+ UINT8 ForceLtrOverride;
+ UINT8 Reserved[3];
+} PCIE_DEVICE_OVERRIDE;
+
+#pragma pack (pop)
+#endif // _PCIE_CONFIG_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/PcieRp/PciePreMemConfig.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/PcieRp/PciePreMemConfig.h
new file mode 100644
index 0000000000..fe0be3ec12
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/PcieRp/PciePreMemConfig.h
@@ -0,0 +1,36 @@
+/** @file
+ PCIe Config Block PreMem
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _PCIE_PREMEM_CONFIG_H_
+#define _PCIE_PREMEM_CONFIG_H_
+
+
+extern EFI_GUID gPciePreMemConfigGuid;
+
+#pragma pack (push,1)
+
+/**
+ PCIe IMR Config
+**/
+typedef struct {
+ UINT8 ImrEnabled; ///< PCIe IMR. <b>0: Disable</b>; 1: Enable.
+ UINT8 ImrRpLocation; ///< 0: PCH_PCIe; 1: CPU_PCIe. If PCIeImrEnabled is TRUE then this will use to select the Root port location from PCH PCIe or CPU PCIe.Refer PCIE_IMR_ROOT_PORT_LOCATION above
+ UINT16 ImrSize; ///< PCIe IMR size in megabytes
+ UINT8 ImrRpSelection; ///< Index of root port that is selected for PCIe IMR (0 based)
+ UINT8 Rsvd0[3];
+} PCIE_IMR_CONFIG;
+
+/**
+ PCIe Pre-Memory Configuration
+ <b>Revision 1</b>: - Initial version.
+**/
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Offset 0 - 27 Config Block Header
+ PCIE_IMR_CONFIG PcieImr; ///< IMR Configuration
+} PCIE_PREMEM_CONFIG;
+
+#pragma pack (pop)
+#endif // _PCIE_PREMEM_CONFIG_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Pmc/AdrConfig.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Pmc/AdrConfig.h
new file mode 100644
index 0000000000..35ecb53ed2
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Pmc/AdrConfig.h
@@ -0,0 +1,76 @@
+/** @file
+ ADR policy
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _ADR_CONFIG_H_
+#define _ADR_CONFIG_H_
+
+#include <ConfigBlock.h>
+
+extern EFI_GUID gAdrConfigGuid;
+
+#pragma pack (push,1)
+
+
+/**
+ ADR Source Enable
+**/
+typedef union {
+ struct {
+ UINT32 Reserved1 : 1;
+ UINT32 AdrSrcPbo : 1;
+ UINT32 AdrSrcPmcUncErr : 1;
+ UINT32 AdrSrcPchThrm : 1;
+ UINT32 AdrSrcMePbo : 1;
+ UINT32 AdrSrcCpuThrm : 1;
+ UINT32 AdrSrcMegbl : 1;
+ UINT32 AdrSrcLtReset : 1;
+ UINT32 AdrSrcPmcWdt : 1;
+ UINT32 AdrSrcMeWdt : 1;
+ UINT32 AdrSrcPmcFw : 1;
+ UINT32 AdrSrcPchpwrFlr : 1;
+ UINT32 AdrSrcSyspwrFlr : 1;
+ UINT32 Reserved2 : 1;
+ UINT32 AdrSrcMiaUxsErr : 1;
+ UINT32 AdrSrcMiaUxErr : 1;
+ UINT32 AdrSrcCpuThrmWdt : 1;
+ UINT32 AdrSrcMeUncErr : 1;
+ UINT32 AdrSrcAdrGpio : 1;
+ UINT32 AdrSrcOcwdtNoicc : 1;
+ UINT32 AdrSrcOcwdtIcc : 1;
+ UINT32 AdrSrcCseHecUncErr : 1;
+ UINT32 AdrSrcPmcSramUncErr : 1;
+ UINT32 AdrSrcPmcIromParity : 1;
+ UINT32 AdrSrcPmcRfFusaErr : 1;
+ UINT32 Reserved3 : 4;
+ UINT32 AdrSrcPpbrParityErr : 1;
+ UINT32 Reserved4 : 2;
+ } Field;
+ UINT32 Value;
+} ADR_SOURCE_ENABLE;
+
+/**
+ ADR Configuration
+ <b>Revision 1</b>: - Initial version.
+**/
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Config Block Header
+ UINT32 AdrEn : 2; ///< Determine if Adr is enabled - 0: PLATFORM_POR, 1: FORCE_ENABLE, 2: FORCE_DISABLE
+ UINT32 AdrTimerEn : 2; ///< Determine if Adr timer options are enabled - 0: PLATFORM_POR, 1: FORCE_ENABLE, 2: FORCE_DISABLE
+ UINT32 AdrTimer1Val : 8; ///< Determines the Timeout value used for the ADR timer 1. A value of zero bypasses the timer
+ UINT32 AdrMultiplier1Val : 3; ///< Specifies the tick frequency upon which the timer 1 will increment. ADR_TIMER_SCALE should be used to encode values
+ UINT32 AdrTimer2Val : 8; ///< Determines the Timeout value used for the ADR timer 2. A value of zero bypasses the timer
+ UINT32 AdrMultiplier2Val : 3; ///< Specifies the tick frequency upon which the timer 2 will increment. ADR_TIMER_SCALE should be used to encode values
+ UINT32 AdrHostPartitionReset : 2; ///< Determine if Host Partition Reset is enabled - 0: PLATFORM_POR, 1: FORCE_ENABLE, 2: FORCE_DISABLE
+ UINT32 AdrSrcOverride : 1; ///< Check if default ADR sources will be overriten with custom 0: Not overwritten, 1: Overwritten
+ UINT32 AdrPlatAckEn : 2; ///< Determine if Platform Acknowledge is enabled - 0: PLATFORM_POR, 1: FORCE_ENABLE, 2: FORCE_DISABLE
+ UINT32 ReservedBits : 1;
+ ADR_SOURCE_ENABLE AdrSrcSel; ///< Determine which ADR sources are enabled - 0: Enabled, 1: Disabled
+} ADR_CONFIG;
+
+#pragma pack (pop)
+
+#endif // _ADR_CONFIG_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Pmc/PmConfig.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Pmc/PmConfig.h
new file mode 100644
index 0000000000..0a2ae50e6a
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Pmc/PmConfig.h
@@ -0,0 +1,86 @@
+/** @file
+ Power Management policy
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _PM_CONFIG_H_
+#define _PM_CONFIG_H_
+
+#include <ConfigBlock.h>
+
+extern EFI_GUID gPmConfigGuid;
+
+#pragma pack (push,1)
+
+/**
+ Description of Global Reset Trigger/Event Mask register
+**/
+typedef union {
+ struct {
+ UINT32 Reserved1 : 1;
+ UINT32 Pbo : 1;
+ UINT32 PmcUncErr : 1;
+ UINT32 PchThrm : 1;
+ UINT32 MePbo : 1;
+ UINT32 CpuThrm : 1;
+ UINT32 Megbl : 1;
+ UINT32 LtReset : 1;
+ UINT32 PmcWdt : 1;
+ UINT32 MeWdt : 1;
+ UINT32 PmcFw : 1;
+ UINT32 PchpwrFlr : 1;
+ UINT32 SyspwrFlr : 1;
+ UINT32 Reserved2 : 1;
+ UINT32 MiaUxsErr : 1;
+ UINT32 MiaUxErr : 1;
+ UINT32 CpuThrmWdt : 1;
+ UINT32 MeUncErr : 1;
+ UINT32 AdrGpio : 1;
+ UINT32 OcwdtNoicc : 1;
+ UINT32 OcwdtIcc : 1;
+ UINT32 CseHecUncErr : 1;
+ UINT32 PmcSramUncErr : 1;
+ UINT32 PmcIromParity : 1;
+ UINT32 PmcRfFusaErr : 1;
+ UINT32 Reserved3 : 4;
+ UINT32 PpbrParityErr : 1;
+ UINT32 Reserved4 : 2;
+ } Field;
+ UINT32 Value;
+} PMC_GLOBAL_RESET_MASK;
+
+typedef union {
+ struct {
+ UINT32 HostResetTimeout : 1;
+ UINT32 SxEntryTimeout : 1;
+ UINT32 HostRstProm : 1;
+ UINT32 HsmbMsg : 1;
+ UINT32 Pmc3Strike : 1;
+ UINT32 FwGblrstScratch5 : 1;
+ UINT32 PmcDmaTimeout : 1;
+ UINT32 EspiType7 : 1;
+ UINT32 EspiType8 : 1;
+ UINT32 FwGblRstScratch10 : 1;
+ UINT32 FwGblRstScratch11 : 1;
+ UINT32 LpmFwErr : 1;
+ UINT32 BscanMode : 1;
+ UINT32 SlpLvlRspErr : 1;
+ UINT32 FwGblrstScratch15 : 1;
+ UINT32 FwGblrstScratch16 : 1;
+ UINT32 FwGblrstScratch17 : 1;
+ UINT32 FwGblrstScratch18 : 1;
+ UINT32 FwGblrstScratch19 : 1;
+ UINT32 FwGblrstScratch20 : 1;
+ UINT32 FwGblrstScratch21 : 1;
+ UINT32 FwGblrstScratch22 : 1;
+ UINT32 FwGblrstScratch23 : 1;
+ UINT32 Rsvd : 9;
+ } Field;
+ UINT32 Value;
+} PMC_GLOBAL_RESET_MASK1;
+
+
+#pragma pack (pop)
+
+#endif // _PM_CONFIG_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Rtc/RtcConfig.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Rtc/RtcConfig.h
new file mode 100644
index 0000000000..62f8303558
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Rtc/RtcConfig.h
@@ -0,0 +1,37 @@
+/** @file
+ RTC policy
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _RTC_CONFIG_H_
+#define _RTC_CONFIG_H_
+
+extern EFI_GUID gRtcConfigGuid;
+
+#pragma pack (push,1)
+
+/**
+ The RTC_CONFIG block describes the expected configuration of RTC configuration.
+**/
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Config Block Header
+ /**
+ When set, prevents RTC TS (BUC.TS) from being changed.
+ This BILD bit has different function compared to LPC/eSPI, SPI.
+ 0: Disabled; <b>1: Enabled</b>
+ **/
+ UINT32 BiosInterfaceLock : 1;
+ /**
+ When set, bytes 38h-3Fh in the upper 128bytes bank of RTC RAM are locked
+ and cannot be accessed.
+ Writes will be droipped and reads will not return any guaranteed data.
+ 0: Disabled; <b>1: Enabled</b>
+ **/
+ UINT32 MemoryLock : 1;
+ UINT32 RsvdBits0 : 30;
+} RTC_CONFIG;
+
+#pragma pack (pop)
+
+#endif // _RTC_CONFIG_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/SerialIo/SerialIoConfig.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/SerialIo/SerialIoConfig.h
new file mode 100644
index 0000000000..b5c3b21606
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/SerialIo/SerialIoConfig.h
@@ -0,0 +1,33 @@
+/** @file
+ Serial IO policy
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _SERIAL_IO_CONFIG_H_
+#define _SERIAL_IO_CONFIG_H_
+
+extern EFI_GUID gSerialIoConfigGuid;
+
+#include <SerialIoDevices.h>
+
+#pragma pack (push,1)
+
+/**
+ The SERIAL_IO_CONFIG block provides the configurations to set the Serial IO controllers
+
+ <b>Revision 1:</b>
+ - Inital version.
+ <b>Revision 2:</b>
+ - Modified SPI Config to support pinmux functionality.
+**/
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Config Block Header
+ SERIAL_IO_SPI_CONFIG SpiDeviceConfig[PCH_MAX_SERIALIO_SPI_CONTROLLERS]; ///< SPI Configuration
+ SERIAL_IO_I2C_CONFIG I2cDeviceConfig[PCH_MAX_SERIALIO_I2C_CONTROLLERS]; ///< I2C Configuration
+ SERIAL_IO_UART_CONFIG UartDeviceConfig[PCH_MAX_SERIALIO_UART_CONTROLLERS]; ///< UART Configuration
+} SERIAL_IO_CONFIG;
+
+#pragma pack (pop)
+
+#endif // _SERIAL_IO_CONFIG_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/SiConfig.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/SiConfig.h
new file mode 100644
index 0000000000..5b59f08df2
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/SiConfig.h
@@ -0,0 +1,105 @@
+/** @file
+ Si Config Block
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _SI_CONFIG_H_
+#define _SI_CONFIG_H_
+
+#define SI_CONFIG_REVISION 1
+
+extern EFI_GUID gSiConfigGuid;
+
+
+#pragma pack (push,1)
+
+/**
+ The Silicon Policy allows the platform code to publish a set of configuration
+ information that the RC drivers will use to configure the silicon hardware.
+
+ <b>Revision 1</b>: - Initial version.
+**/
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Offset 0 - 27 Config Block Header
+ //
+ // Platform specific common policies that used by several silicon components.
+ //
+ UINT8 CsmFlag; ///< offset 28 CSM status flag.@deprecated.
+ /**
+ This is used to skip the SSID programming in silicon code.
+ When set to TRUE, silicon code will not do any SSID programming and platform code
+ needs to handle that by itself properly.
+ <b>0: FALSE</b>, 1: TRUE
+ **/
+ UINT8 SkipSsidProgramming; ///< offset 29
+ UINT8 RsvdBytes0[2]; ///< offset 30 - 31
+ /**
+ When SkipSsidProgramming is FALSE, silicon code will use this as default value
+ to program the SVID for all internal devices.
+ <b>0: use silicon default SVID 0x8086 </b>, Non-zero: use customized SVID.
+ **/
+ UINT16 CustomizedSvid; ///< offset 32 - 33
+ /**
+ When SkipSsidProgramming is FALSE, silicon code will use this as default value
+ to program the Sid for all internal devices.
+ <b>0: use silicon default SSID 0x7270 </b>, Non-zero: use customized SSID.
+ **/
+ UINT16 CustomizedSsid; ///< offset 34 - 35
+ UINT32 *SsidTablePtr; ///< offset 36 - 39
+ /**
+ Number of valid enties in SsidTablePtr.
+ This is valid when SkipSsidProgramming is FALSE;
+ <b>Default is 0.</b>
+ **/
+ UINT16 NumberOfSsidTableEntry; ///< offset 40 - 41
+ UINT8 RsvdBytes1[2]; ///< offset 42 - 43
+ /**
+ This is used to skip setting BIOS_DONE MSR during firmware update boot mode.
+ When set to TRUE and boot mode is BOOT_ON_FLASH_UPDATE,
+ skip setting BIOS_DONE MSR at EndofPei.
+ <b>0: FALSE</b>, 1: TRUE
+ **/
+ UINT8 SkipBiosDoneWhenFwUpdate; ///< Offset 44
+ UINT8 RsvdBytes2[3]; ///< Offset 45 - 47
+} SI_CONFIG;
+
+#pragma pack (pop)
+
+
+///
+/// Subsystem Vendor ID / Subsystem ID
+///
+typedef struct {
+ UINT16 SubSystemVendorId;
+ UINT16 SubSystemId;
+} SVID_SID_VALUE;
+
+//
+// Below is to match PCI_SEGMENT_LIB_ADDRESS () which can directly send to PciSegmentRead/Write functions.
+//
+typedef struct {
+ union {
+ struct {
+ UINT32 Register:12;
+ UINT32 Function:3;
+ UINT32 Device:5;
+ UINT32 Bus:8;
+ UINT32 Reserved1:4;
+ UINT32 Segment:16;
+ UINT32 Reserved2:16;
+ } Bits;
+ UINT64 SegBusDevFuncRegister;
+ } Address;
+ SVID_SID_VALUE SvidSidValue;
+ UINT32 Reserved;
+} SVID_SID_INIT_ENTRY;
+
+
+typedef struct {
+ UINT32 SkipBus;
+ UINT32 SkipDevice;
+ UINT32 SkipFunction;
+} SVID_SID_SKIP_TABLE;
+
+#endif // _SI_CONFIG_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/SiPreMemConfig.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/SiPreMemConfig.h
new file mode 100644
index 0000000000..584a0d4169
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/SiPreMemConfig.h
@@ -0,0 +1,63 @@
+/** @file
+ Si Config Block PreMem
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _SI_PREMEM_CONFIG_H_
+#define _SI_PREMEM_CONFIG_H_
+
+#define SI_PREMEM_CONFIG_REVISION 1
+
+extern EFI_GUID gSiPreMemConfigGuid;
+
+typedef enum {
+ ProbeTypeDisabled = 0x00,
+ ProbeTypeDciOob = 0x02,
+ ProbeType2WireDciOob = 0x06,
+ ProbeTypeManual = 0x07,
+ ProbeTypeMax
+} PLATFORM_DEBUG_CONSENT_PROBE_TYPE;
+
+#pragma pack (push,1)
+/**
+ The Silicon PreMem Policy allows the platform code to publish a set of configuration
+ information that the RC drivers will use to configure the silicon hardware.
+
+ <b>Revision 1</b>:
+ - Initial version.
+**/
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Offset 0 - 27 Config Block Header
+ /**
+ Platform Debug Consent
+ As a main switch to enable platform debug capability and relevant settings with specified probe type.
+ Manual: Do not use Platform Debug Consent to override other debug-relevant policies, but the user must set each debug option manually, aimed at advanced users.
+
+ PDC-dependent policies are listed:
+ DciPreMemConfig->DciEn
+ CpuTraceHubConfig->EnableMode
+ CpuTraceHubConfig->CpuTraceHubMemReg0Size
+ CpuTraceHubConfig->CpuTraceHubMemReg1Size
+ PchTraceHubPreMemConfig->EnableMode
+ PchTraceHubPreMemConfig->MemReg0Size
+ PchTraceHubPreMemConfig->MemReg1Size
+
+ Note: DCI OOB (aka BSSB) uses CCA probe.
+ Refer to definition of PLATFORM_DEBUG_CONSENT_PROBE_TYPE
+ <b>0:Disabled</b>; 2:DCI OOB (All + TraceHubs); 6:2-wire DCI OOB (Low power); 7:Manual
+ **/
+ UINT32 PlatformDebugConsent : 4; /// offset 28 - 31
+ UINT32 RsvdBits : 28;
+ /**
+ This is used to skip override boot mode during firmware update boot mode.
+ When set to TRUE and boot mode is BOOT_ON_FLASH_UPDATE,
+ skip setting boot mode to BOOT_WITH_FULL_CONFIGURATION in PEI memory init.
+ <b>0: FALSE</b>, 1: TRUE
+ **/
+ UINT8 SkipOverrideBootModeWhenFwUpdate; /// offset 32
+ UINT8 RsvdBytes[3]; /// offset 33 - 35
+} SI_PREMEM_CONFIG;
+
+#pragma pack (pop)
+#endif // _SI_PREMEM_CONFIG_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Smbus/SmbusConfig.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Smbus/SmbusConfig.h
new file mode 100644
index 0000000000..2fc724552b
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Smbus/SmbusConfig.h
@@ -0,0 +1,49 @@
+/** @file
+ Smbus policy
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _SMBUS_CONFIG_H_
+#define _SMBUS_CONFIG_H_
+
+extern EFI_GUID gSmbusPreMemConfigGuid;
+
+#pragma pack (push,1)
+
+#define PCH_MAX_SMBUS_RESERVED_ADDRESS 128
+
+///
+/// The SMBUS_CONFIG block lists the reserved addresses for non-ARP capable devices in the platform.
+///
+typedef struct {
+ /**
+ Revision 1: Init version
+ **/
+ CONFIG_BLOCK_HEADER Header; ///< Config Block Header
+ /**
+ This member describes whether or not the SMBus controller of PCH should be enabled.
+ 0: Disable; <b>1: Enable</b>.
+ **/
+ UINT32 Enable : 1;
+ UINT32 ArpEnable : 1; ///< Enable SMBus ARP support, <b>0: Disable</b>; 1: Enable.
+ UINT32 DynamicPowerGating : 1; ///< <b>(Test)</b> <b>Disable</b> or Enable Smbus dynamic power gating.
+ ///
+ /// <b>(Test)</b> SPD Write Disable, 0: leave SPD Write Disable bit; <b>1: set SPD Write Disable bit.</b>
+ /// For security recommendations, SPD write disable bit must be set.
+ ///
+ UINT32 SpdWriteDisable : 1;
+ UINT32 SmbAlertEnable : 1; ///< Enable SMBus Alert pin (SMBALERT#). 0: <b>Disabled<b>, 1: Enabled.
+ UINT32 RsvdBits0 : 27; ///< Reserved bits
+ UINT16 SmbusIoBase; ///< SMBUS Base Address (IO space). Default is <b>0xEFA0</b>.
+ UINT8 Rsvd0; ///< Reserved bytes
+ UINT8 NumRsvdSmbusAddresses; ///< The number of elements in the RsvdSmbusAddressTable.
+ /**
+ Array of addresses reserved for non-ARP-capable SMBus devices.
+ **/
+ UINT8 RsvdSmbusAddressTable[PCH_MAX_SMBUS_RESERVED_ADDRESS];
+} PCH_SMBUS_PREMEM_CONFIG;
+
+#pragma pack (pop)
+
+#endif // _SMBUS_CONFIG_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Spi/FlashProtectionConfig.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Spi/FlashProtectionConfig.h
new file mode 100644
index 0000000000..45dc538064
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Spi/FlashProtectionConfig.h
@@ -0,0 +1,54 @@
+/** @file
+ FlashProtection policy
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _FLASH_PROTECTION_CONFIG_H_
+#define _FLASH_PROTECTION_CONFIG_H_
+
+extern EFI_GUID gFlashProtectionConfigGuid;
+
+#pragma pack (push,1)
+
+//
+// Flash Protection Range Register
+//
+#define PCH_FLASH_PROTECTED_RANGES 5
+
+/**
+ Protected Flash Range
+**/
+typedef struct {
+ UINT32 WriteProtectionEnable : 1; ///< Write or erase is blocked by hardware. <b>0: Disable</b>; 1: Enable.
+ UINT32 ReadProtectionEnable : 1; ///< Read is blocked by hardware. <b>0: Disable</b>; 1: Enable.
+ UINT32 RsvdBits : 30; ///< Reserved
+ /**
+ The address of the upper limit of protection
+ This is a left shifted address by 12 bits with address bits 11:0 are assumed to be FFFh for limit comparison
+ **/
+ UINT16 ProtectedRangeLimit;
+ /**
+ The address of the upper limit of protection
+ This is a left shifted address by 12 bits with address bits 11:0 are assumed to be 0
+ **/
+ UINT16 ProtectedRangeBase;
+} PROTECTED_RANGE;
+
+/**
+ The PCH provides a method for blocking writes and reads to specific ranges
+ in the SPI flash when the Protected Ranges are enabled.
+ PROTECTED_RANGE is used to specify if flash protection are enabled,
+ the write protection enable bit and the read protection enable bit,
+ and to specify the upper limit and lower base for each register
+ Platform code is responsible to get the range base by PchGetSpiRegionAddresses routine,
+ and set the limit and base accordingly.
+**/
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Config Block Header
+ PROTECTED_RANGE ProtectRange[PCH_FLASH_PROTECTED_RANGES]; ///< Protected Flash Ranges
+} PCH_FLASH_PROTECTION_CONFIG;
+
+#pragma pack (pop)
+
+#endif // _FLASH_PROTECTION_CONFIG_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Tcss/TcssPeiConfig.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Tcss/TcssPeiConfig.h
new file mode 100644
index 0000000000..95bcaaa951
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Tcss/TcssPeiConfig.h
@@ -0,0 +1,71 @@
+/** @file
+ TCSS PEI policy
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _TCSS_PEI_CONFIG_H_
+#define _TCSS_PEI_CONFIG_H_
+
+#include <ConfigBlock.h>
+
+extern EFI_GUID gTcssPeiConfigGuid;
+
+#pragma pack (push,1)
+
+
+#define MAX_IOM_AUX_BIAS_COUNT 4
+
+///
+/// The IOM_AUX_ORI_PAD_CONFIG describes IOM TypeC port map GPIO pin.
+/// Those GPIO setting for DP Aux Orientation Bias Control when the TypeC port didn't have re-timer.
+/// IOM needs know Pull-Up and Pull-Down pin for Bias control
+///
+typedef struct {
+ UINT32 GpioPullN; ///< GPIO Pull Up Ping number that is for IOM indecate the pull up pin from TypeC port.
+ UINT32 GpioPullP; ///< GPIO Pull Down Ping number that is for IOM indecate the pull down pin from TypeC port.
+} IOM_AUX_ORI_PAD_CONFIG;
+
+///
+/// The IOM_EC_INTERFACE_CONFIG block describes interaction between BIOS and IOM-EC.
+///
+
+typedef struct {
+ UINT32 VccSt; ///< IOM VCCST request. (Not equal to actual VCCST value)
+ UINT32 UsbOverride; ///< IOM to override USB connection.
+ UINT32 D3ColdEnable; ///< Enable/disable D3 Cold support in TCSS
+ UINT32 D3HotEnable; ///< Enable/disable D3 Hot support in TCSS
+} IOM_INTERFACE_CONFIG;
+
+///
+/// The PMC_INTERFACE_CONFIG block describes interaction between BIOS and PMC
+///
+typedef struct {
+ UINT8 PmcPdEnable; ///< PMC PD Solution Enable
+ UINT8 Rsvd[3];
+} PMC_INTERFACE_CONFIG;
+
+///
+/// The TCSS_IOM_PEI_CONFIG block describes IOM Aux/HSL override settings for TCSS.
+///
+typedef struct {
+ UINT16 AuxOri; ///< Bits defining value for IOM Aux Orientation Register
+ UINT16 HslOri; ///< Bits defining value for IOM HSL Orientation Register
+} TCSS_IOM_ORI_OVERRIDE;
+
+///
+/// The TCSS_IOM_PEI_CONFIG block describes IOM settings for TCSS.
+///
+typedef struct {
+ IOM_AUX_ORI_PAD_CONFIG IomAuxPortPad[MAX_IOM_AUX_BIAS_COUNT]; ///< The IOM_AUX_ORI_BIAS_CTRL port config setting.
+ TCSS_IOM_ORI_OVERRIDE IomOverrides;
+ IOM_INTERFACE_CONFIG IomInterface; ///< Config settings are BIOS <-> IOM interface.
+ PMC_INTERFACE_CONFIG PmcInterface; ///< Config settings for BIOS <-> PMC interface
+ UINT8 TcStateLimit; ///< Tcss C-State deep stage
+ UINT8 Reserved[3]; ///< Reserved bytes for future use
+} TCSS_IOM_PEI_CONFIG;
+
+
+#pragma pack (pop)
+
+#endif /* _TCSS_PEI_CONFIG_H_ */
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Vmd/VmdPeiConfig.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Vmd/VmdPeiConfig.h
new file mode 100644
index 0000000000..37e6439abb
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Vmd/VmdPeiConfig.h
@@ -0,0 +1,60 @@
+/** @file
+ VMD PEI policy
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _VMD_PEI_CONFIG_H_
+#define _VMD_PEI_CONFIG_H_
+
+#include <ConfigBlock.h>
+
+#pragma pack (push,1)
+
+#define VMD_MAX_DEVICES 31
+
+typedef struct {
+ UINT8 RpBus;
+ UINT8 RpDevice;
+ UINT8 RpFunction;
+ UINT8 RpEnable;
+} RP_BDF_DATA;
+
+/**
+ This configuration block is to configure VMD related variables used in PostMem PEI.
+ If VMD Device is not supported, all policies can be ignored.
+ <b>Revision 1</b>:
+ - Initial version.
+ <b>Revision 2</b>:
+ - Deprecated VmdPortAEnable, VmdPortBEnable, VmdPortCEnable, VmdPortDEnable.
+ - Added VmdPortEnable[VMD_MAX_DEVICES] and structure to hold Vmd EFI Variable details.
+ (Added B/D/F fields along with Port Enable for up to max 31 devices).
+ <b>Revision 3</b>:
+ Added policy to get the Bar values from platform PCD.
+ <b>Revision 4</b>: Added VmdGlobalMapping to map all the storage devices under VMD
+**/
+
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Block Header
+ UINT8 VmdEnable; ///< Offset 28 This field used to enable VMD controller 1=Enable <b>0=Disable(default)</b>
+ UINT8 VmdPortAEnable; /// Deprecated < Offset 29 This field used to enable VMD portA Support 1=Enable and 0=Disable (default)
+ UINT8 VmdPortBEnable; /// Deprecated < Offset 30 This field used to enable VMD portB Support 1=Enable and 0=Disable (default)
+ UINT8 VmdPortCEnable; /// Deprecated < Offset 31 This field used to enable VMD portC Support 1=Enable and 0=Disable (default)
+ UINT8 VmdPortDEnable; /// Deprecated < Offset 32 This field used to enable VMD portD Support 1=Enable and 0=Disable (default)
+ UINT8 VmdCfgBarSize; ///< Offset 33 This is used to set the VMD Config Bar Size. <b>25(32MB)</b>
+ UINT8 VmdCfgBarAttr; ///< Offset 34 This is used to set VMD Config Bar Attributes 0: VMD_32BIT_NONPREFETCH, 1: VMD_64BIT_PREFETCH, <b>2: VMD_64BIT_NONPREFETCH(Default)</b>
+ UINT8 VmdMemBarSize1; ///< Offset 35 This is used to set the VMD Mem Bar1 size. <b>25 (32MB)</b>.
+ UINT8 VmdMemBar1Attr; ///< Offset 36 This is used to set VMD Mem Bar1 Attributes <b>0: VMD_32BIT_NONPREFETCH(Default) </b> 1: VMD_64BIT_NONPREFETCH, 2: VMD_64BIT_PREFETCH
+ UINT8 VmdMemBarSize2; ///< Offset 37 This is used to set the VMD Mem Bar2 size. <b>20(1MB)</b>.
+ UINT8 VmdMemBar2Attr; ///< Offset 38 This is used to set VMD Mem Bar2 Attributes 0: VMD_32BIT_NONPREFETCH <b>1: VMD_64BIT_NONPREFETCH(Default)</b>, 2: VMD_64BIT_PREFETCH
+ UINT8 VmdGlobalMapping; ///< Offset 39 This field used to enable Global Mapping 1=Enable <b>0=Disable(default)</b>
+ RP_BDF_DATA VmdPortEnable[VMD_MAX_DEVICES]; ///< Offset 40 to 163 This field used to to store b/d/f for each root port along with enable Support 1=Enable <b>0=Disable (default)</b>
+ VOID *VmdVariablePtr; /// This config block will be updated as per the EFI variable.
+ UINT32 VmdCfgBarBase; /// Temp Address VMD CFG BAR Default is <b>0xA0000000</b>
+ UINT32 VmdMemBar1Base; /// Temp Address VMD CFG BAR Default is <b>0xA2000000</b>
+ UINT32 VmdMemBar2Base; /// Temp Address VMD CFG BAR Default is <b>0xA4000000</b>
+} VMD_PEI_CONFIG;
+
+#pragma pack (pop)
+
+#endif /* _VMD_PEI_PREMEM_CONFIG_H_ */
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Wdt/WatchDogConfig.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Wdt/WatchDogConfig.h
new file mode 100644
index 0000000000..ad17488ecc
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Wdt/WatchDogConfig.h
@@ -0,0 +1,30 @@
+/** @file
+ WatchDog policy
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _WATCH_DOG_CONFIG_H_
+#define _WATCH_DOG_CONFIG_H_
+
+extern EFI_GUID gWatchDogPreMemConfigGuid;
+
+#pragma pack (push,1)
+
+/**
+ This policy clears status bits and disable watchdog, then lock the
+ WDT registers.
+ while WDT is designed to be disabled and locked by Policy,
+ bios should not enable WDT by WDT PPI. In such case, bios shows the
+ warning message but not disable and lock WDT register to make sure
+ WDT event trigger correctly.
+**/
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Config Block Header
+ UINT32 DisableAndLock : 1; ///< <b>(Test)</b> Set 1 to clear WDT status, then disable and lock WDT registers. <b>0: Disable</b>; 1: Enable.
+ UINT32 RsvdBits : 31;
+} PCH_WDT_PREMEM_CONFIG;
+
+#pragma pack (pop)
+
+#endif // _WATCH_DOG_CONFIG_H_
--
2.36.1.windows.1
-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#108691): https://edk2.groups.io/g/devel/message/108691
Mute This Topic: https://groups.io/mt/101373949/7686176
Group Owner: devel+owner@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [rebecca@openfw.io]
-=-=-=-=-=-=-=-=-=-=-=-
^ permalink raw reply related [flat|nested] 41+ messages in thread
* Re: [edk2-devel] [PATCH v2 06/10] AlderlakeSiliconPkg/Include: Add Library, Pins, Ppi Includes
2023-09-15 4:45 ` [edk2-devel] [PATCH v2 06/10] AlderlakeSiliconPkg/Include: Add Library, Pins, Ppi Includes Saloni Kasbekar
@ 2023-09-15 5:43 ` Chaganty, Rangasai V
2023-09-15 13:28 ` Chuang, Rosen
2023-09-15 23:56 ` Nate DeSimone
1 sibling, 1 reply; 41+ messages in thread
From: Chaganty, Rangasai V @ 2023-09-15 5:43 UTC (permalink / raw)
To: Kasbekar, Saloni, devel@edk2.groups.io
Cc: Desimone, Nathaniel L, Chuang, Rosen
Reviewed-by: Sai Chaganty <rangasai.v.chaganty@intel.com>
-----Original Message-----
From: Kasbekar, Saloni <saloni.kasbekar@intel.com>
Sent: Thursday, September 14, 2023 9:46 PM
To: devel@edk2.groups.io
Cc: Kasbekar, Saloni <saloni.kasbekar@intel.com>; Chaganty, Rangasai V <rangasai.v.chaganty@intel.com>; Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>; Chuang, Rosen <rosen.chuang@intel.com>
Subject: [PATCH v2 06/10] AlderlakeSiliconPkg/Include: Add Library, Pins, Ppi Includes
Adds the following Includes:
- Include/Library
- Include/Pins
- Include/Ppi
Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Rosen Chuang <rosen.chuang@intel.com>
Signed-off-by: Saloni Kasbekar <saloni.kasbekar@intel.com>
---
.../Include/Library/ConfigBlockLib.h | 64 +++
.../Include/Library/EspiLib.h | 34 ++
.../Include/Library/GpioConfig.h | 372 ++++++++++++++++++
.../Include/Library/GpioLib.h | 174 ++++++++
.../Include/Library/GpioNativeLib.h | 135 +++++++
.../Include/Library/GraphicsInfoLib.h | 46 +++
.../Include/Library/MmPciLib.h | 27 ++
.../Include/Library/PchPcieRpLib.h | 41 ++
.../Include/Library/PchPcrLib.h | 221 +++++++++++
.../Library/PeiDxeSmmReserveMmio64SizeLib.h | 21 +
.../Include/Library/PeiSiPolicyUpdateLib.h | 154 ++++++++
.../Include/Library/PmcLib.h | 40 ++
.../Include/Library/ResetSystemLib.h | 68 ++++
.../Include/Library/SecPlatformLib.h | 81 ++++
.../Include/Library/SiConfigBlockLib.h | 56 +++
.../Include/Library/SiPolicyLib.h | 39 ++
.../Include/Library/SpiLib.h | 21 +
.../Include/Pins/GpioPinsVer2Lp.h | 36 ++
.../Include/Ppi/FspmArchConfigPpi.h | 32 ++
.../Include/Ppi/PeiPreMemSiDefaultPolicy.h | 33 ++
.../Include/Ppi/PeiSiDefaultPolicy.h | 33 ++
.../AlderlakeSiliconPkg/Include/Ppi/Spi.h | 29 ++
.../AlderlakeSiliconPkg/Include/Ppi/Wdt.h | 22 ++
23 files changed, 1779 insertions(+)
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Library/ConfigBlockLib.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Library/EspiLib.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Library/GpioConfig.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Library/GpioLib.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Library/GpioNativeLib.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Library/GraphicsInfoLib.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Library/MmPciLib.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Library/PchPcieRpLib.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Library/PchPcrLib.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Library/PeiDxeSmmReserveMmio64SizeLib.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Library/PeiSiPolicyUpdateLib.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Library/PmcLib.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Library/ResetSystemLib.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Library/SecPlatformLib.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Library/SiConfigBlockLib.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Library/SiPolicyLib.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Library/SpiLib.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Pins/GpioPinsVer2Lp.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Ppi/FspmArchConfigPpi.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Ppi/PeiPreMemSiDefaultPolicy.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Ppi/PeiSiDefaultPolicy.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Ppi/Spi.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Ppi/Wdt.h
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/ConfigBlockLib.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/ConfigBlockLib.h
new file mode 100644
index 0000000000..d9966c76e9
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/ConfigBlockLib.h
@@ -0,0 +1,64 @@
+/** @file
+ Header file for Config Block Lib implementation
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _CONFIG_BLOCK_LIB_H_
+#define _CONFIG_BLOCK_LIB_H_
+
+/**
+ Create config block table
+
+ @param[in] TotalSize - Max size to be allocated for the Config Block Table
+ @param[out] ConfigBlockTableAddress - On return, points to a pointer to the beginning of Config Block Table Address
+
+ @retval EFI_INVALID_PARAMETER - Invalid Parameter
+ @retval EFI_OUT_OF_RESOURCES - Out of resources
+ @retval EFI_SUCCESS - Successfully created Config Block Table at ConfigBlockTableAddress
+**/
+EFI_STATUS
+EFIAPI
+CreateConfigBlockTable (
+ IN UINT16 TotalSize,
+ OUT VOID **ConfigBlockTableAddress
+ );
+
+/**
+ Add config block into config block table structure
+
+ @param[in] ConfigBlockTableAddress - A pointer to the beginning of Config Block Table Address
+ @param[out] ConfigBlockAddress - On return, points to a pointer to the beginning of Config Block Address
+
+ @retval EFI_OUT_OF_RESOURCES - Config Block Table is full and cannot add new Config Block or
+ Config Block Offset Table is full and cannot add new Config Block.
+ @retval EFI_SUCCESS - Successfully added Config Block
+**/
+EFI_STATUS
+EFIAPI
+AddConfigBlock (
+ IN VOID *ConfigBlockTableAddress,
+ OUT VOID **ConfigBlockAddress
+ );
+
+/**
+ Retrieve a specific Config Block data by GUID
+
+ @param[in] ConfigBlockTableAddress - A pointer to the beginning of Config Block Table Address
+ @param[in] ConfigBlockGuid - A pointer to the GUID uses to search specific Config Block
+ @param[out] ConfigBlockAddress - On return, points to a pointer to the beginning of Config Block Address
+
+ @retval EFI_NOT_FOUND - Could not find the Config Block
+ @retval EFI_SUCCESS - Config Block found and return
+**/
+EFI_STATUS
+EFIAPI
+GetConfigBlock (
+ IN VOID *ConfigBlockTableAddress,
+ IN EFI_GUID *ConfigBlockGuid,
+ OUT VOID **ConfigBlockAddress
+ );
+
+#endif // _CONFIG_BLOCK_LIB_H_
+
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/EspiLib.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/EspiLib.h
new file mode 100644
index 0000000000..3c37def986
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/EspiLib.h
@@ -0,0 +1,34 @@
+/** @file
+ Header file for PchEspiLib.
+ All function in this library is available for PEI, DXE, and SMM,
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _ESPI_LIB_H_
+#define _ESPI_LIB_H_
+
+/**
+ Checks if there's second device connected under CS#1
+
+ @retval TRUE There's second device
+ @retval FALSE There's no second device
+**/
+BOOLEAN
+IsEspiSecondSlaveSupported (
+ VOID
+ );
+
+/**
+ Is eSPI enabled in strap.
+
+ @retval TRUE Espi is enabled in strap
+ @retval FALSE Espi is disabled in strap
+**/
+BOOLEAN
+IsEspiEnabled (
+ VOID
+ );
+
+#endif // _ESPI_LIB_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/GpioConfig.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/GpioConfig.h
new file mode 100644
index 0000000000..43c0da46d7
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/GpioConfig.h
@@ -0,0 +1,372 @@
+/** @file
+ Header file for GpioConfig structure used by GPIO library.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _GPIO_CONFIG_H_
+#define _GPIO_CONFIG_H_
+
+#pragma pack(push, 1)
+
+///
+/// For any GpioPad usage in code use GPIO_PAD type
+///
+typedef UINT32 GPIO_PAD;
+
+///
+/// GpioPad with additional native function information.
+/// This type is used to represent signal muxing alternatives. Platform will provide such value to
+/// identify muxing selection for given signal on a specific SOC.
+/// Please refer to the board layout
+///
+typedef UINT32 GPIO_NATIVE_PAD;
+
+
+///
+/// For any GpioGroup usage in code use GPIO_GROUP type
+///
+typedef UINT32 GPIO_GROUP;
+
+/**
+ GPIO configuration structure used for pin programming.
+ Structure contains fields that can be used to configure pad.
+**/
+typedef struct {
+ /**
+ Pad Mode
+ Pad can be set as GPIO or one of its native functions.
+ When in native mode setting Direction (except Inversion), OutputState,
+ InterruptConfig, Host Software Pad Ownership and OutputStateLock are unnecessary.
+ Refer to definition of GPIO_PAD_MODE.
+ Refer to EDS for each native mode according to the pad.
+ **/
+ UINT32 PadMode : 5;
+ /**
+ Host Software Pad Ownership
+ Set pad to ACPI mode or GPIO Driver Mode.
+ Refer to definition of GPIO_HOSTSW_OWN.
+ **/
+ UINT32 HostSoftPadOwn : 2;
+ /**
+ GPIO Direction
+ Can choose between In, In with inversion, Out, both In and Out, both In with inversion and out or disabling both.
+ Refer to definition of GPIO_DIRECTION for supported settings.
+ **/
+ UINT32 Direction : 6;
+ /**
+ Output State
+ Set Pad output value.
+ Refer to definition of GPIO_OUTPUT_STATE for supported settings.
+ This setting takes place when output is enabled.
+ **/
+ UINT32 OutputState : 2;
+ /**
+ GPIO Interrupt Configuration
+ Set Pad to cause one of interrupts (IOxAPIC/SCI/SMI/NMI).
+ This setting is applicable only if GPIO is in GpioMode with input enabled.
+ Refer to definition of GPIO_INT_CONFIG for supported settings.
+ **/
+ UINT32 InterruptConfig : 9;
+ /**
+ GPIO Power Configuration.
+ This setting controls Pad Reset Configuration.
+ Refer to definition of GPIO_RESET_CONFIG for supported settings.
+ **/
+ UINT32 PowerConfig : 8;
+ /**
+ GPIO Electrical Configuration
+ This setting controls pads termination.
+ Refer to definition of GPIO_ELECTRICAL_CONFIG for supported settings.
+ **/
+ UINT32 ElectricalConfig : 9;
+ /**
+ GPIO Lock Configuration
+ This setting controls pads lock.
+ Refer to definition of GPIO_LOCK_CONFIG for supported settings.
+ **/
+ UINT32 LockConfig : 4;
+ /**
+ Additional GPIO configuration
+ Refer to definition of GPIO_OTHER_CONFIG for supported settings.
+ **/
+ UINT32 OtherSettings : 9;
+
+ /**
+ Virtual GPIO eSPI Chip Select configuration
+ This setting selects between CS0 and CS1.
+ Refer to definition of VGPIO_CS_CONFIG for supported settings.
+ **/
+ UINT32 VgpioCs : 2;
+
+ UINT32 RsvdBits : 8; ///< Reserved bits for future extension
+} GPIO_CONFIG;
+
+
+typedef enum {
+ GpioHardwareDefault = 0x0 ///< Leave setting unmodified
+} GPIO_HARDWARE_DEFAULT;
+
+/**
+ GPIO Pad Mode
+ Refer to GPIO documentation on native functions available for certain pad.
+ If GPIO is set to one of NativeX modes then following settings are not applicable
+ and can be skipped:
+ - Interrupt related settings
+ - Host Software Ownership
+ - Output/Input enabling/disabling
+ - Output lock
+**/
+typedef enum {
+ GpioPadModeHwDefault = 0x0,
+ GpioPadModeGpio = 0x1,
+ GpioPadModeNative1 = 0x3,
+ GpioPadModeNative2 = 0x5,
+ GpioPadModeNative3 = 0x7,
+ GpioPadModeNative4 = 0x9,
+ GpioPadModeNative5 = 0xB,
+ GpioPadModeNative6 = 0xD,
+ GpioPadModeNative7 = 0xF
+} GPIO_PAD_MODE;
+
+/**
+ Host Software Pad Ownership modes
+ This setting affects GPIO interrupt status registers. Depending on chosen ownership
+ some GPIO Interrupt status register get updated and other masked.
+ Please refer to EDS for HOSTSW_OWN register description.
+**/
+typedef enum {
+ GpioHostOwnDefault = 0x0, ///< Leave ownership value unmodified
+ /**
+ Set HOST ownership to ACPI.
+ Use this setting if pad is not going to be used by GPIO OS driver.
+ If GPIO is configured to generate SCI/SMI/NMI then this setting must be
+ used for interrupts to work
+ **/
+ GpioHostOwnAcpi = 0x1,
+ /**
+ Set HOST ownership to GPIO Driver mode.
+ Use this setting only if GPIO pad should be controlled by GPIO OS Driver.
+ GPIO OS Driver will be able to control the pad if appropriate entry in
+ ACPI exists (refer to ACPI specification for GpioIo and GpioInt descriptors)
+ **/
+ GpioHostOwnGpio = 0x3
+} GPIO_HOSTSW_OWN;
+
+///
+/// GPIO Direction
+///
+typedef enum {
+ GpioDirDefault = 0x0, ///< Leave pad direction setting unmodified
+ GpioDirInOut = (0x1 | (0x1 << 3)), ///< Set pad for both output and input
+ GpioDirInInvOut = (0x1 | (0x3 << 3)), ///< Set pad for both output and input with inversion
+ GpioDirIn = (0x3 | (0x1 << 3)), ///< Set pad for input only
+ GpioDirInInv = (0x3 | (0x3 << 3)), ///< Set pad for input with inversion
+ GpioDirOut = 0x5, ///< Set pad for output only
+ GpioDirNone = 0x7 ///< Disable both output and input
+} GPIO_DIRECTION;
+
+/**
+ GPIO Output State
+ This field is relevant only if output is enabled
+**/
+typedef enum {
+ GpioOutDefault = 0x0, ///< Leave output value unmodified
+ GpioOutLow = 0x1, ///< Set output to low
+ GpioOutHigh = 0x3 ///< Set output to high
+} GPIO_OUTPUT_STATE;
+
+/**
+ GPIO interrupt configuration
+ This setting is applicable only if pad is in GPIO mode and has input enabled.
+ GPIO_INT_CONFIG allows to choose which interrupt is generated (IOxAPIC/SCI/SMI/NMI)
+ and how it is triggered (edge or level). Refer to PADCFG_DW0 register description in
+ EDS for details on this settings.
+ Field from GpioIntNmi to GpioIntApic can be OR'ed with GpioIntLevel to GpioIntBothEdge
+ to describe an interrupt e.g. GpioIntApic | GpioIntLevel
+ If GPIO is set to cause an SCI then also GPI_GPE_EN is enabled for this pad.
+ If GPIO is set to cause an NMI then also GPI_NMI_EN is enabled for this pad.
+ Not all GPIO are capable of generating an SMI or NMI interrupt.
+ When routing GPIO to cause an IOxAPIC interrupt care must be taken, as this
+ interrupt cannot be shared and its IRQn number is not configurable.
+ Refer to EDS for GPIO pads IRQ numbers (PADCFG_DW1.IntSel)
+ If GPIO is under GPIO OS driver control and appropriate ACPI GpioInt descriptor
+ exist then use only trigger type setting (from GpioIntLevel to GpioIntBothEdge).
+ This type of GPIO Driver interrupt doesn't have any additional routing setting
+ required to be set by BIOS. Interrupt is handled by GPIO OS Driver.
+**/
+
+typedef enum {
+ GpioIntDefault = 0x0, ///< Leave value of interrupt routing unmodified
+ GpioIntDis = 0x1, ///< Disable IOxAPIC/SCI/SMI/NMI interrupt generation
+ GpioIntNmi = 0x3, ///< Enable NMI interrupt only
+ GpioIntSmi = 0x5, ///< Enable SMI interrupt only
+ GpioIntSci = 0x9, ///< Enable SCI interrupt only
+ GpioIntApic = 0x11, ///< Enable IOxAPIC interrupt only
+ GpioIntLevel = (0x1 << 5), ///< Set interrupt as level triggered
+ GpioIntEdge = (0x3 << 5), ///< Set interrupt as edge triggered (type of edge depends on input inversion)
+ GpioIntLvlEdgDis = (0x5 << 5), ///< Disable interrupt trigger
+ GpioIntBothEdge = (0x7 << 5) ///< Set interrupt as both edge triggered
+} GPIO_INT_CONFIG;
+
+#define B_GPIO_INT_CONFIG_INT_SOURCE_MASK 0x1F ///< Mask for GPIO_INT_CONFIG for interrupt source
+#define B_GPIO_INT_CONFIG_INT_TYPE_MASK 0xE0 ///< Mask for GPIO_INT_CONFIG for interrupt type
+
+/**
+ GPIO Power Configuration
+ GPIO_RESET_CONFIG allows to set GPIO Reset type (PADCFG_DW0.PadRstCfg) which will
+ be used to reset certain GPIO settings.
+ Refer to EDS for settings that are controllable by PadRstCfg.
+**/
+typedef enum {
+ GpioResetDefault = 0x00, ///< Leave value of pad reset unmodified
+ /**
+ Resume Reset (RSMRST)
+ GPP: PadRstCfg = 00b = "Powergood"
+ GPD: PadRstCfg = 11b = "Resume Reset"
+ Pad setting will reset on:
+ - DeepSx transition
+ - G3
+ Pad settings will not reset on:
+ - S3/S4/S5 transition
+ - Warm/Cold/Global reset
+ **/
+ GpioResumeReset = 0x01,
+ /**
+ Host Deep Reset
+ PadRstCfg = 01b = "Deep GPIO Reset"
+ Pad settings will reset on:
+ - Warm/Cold/Global reset
+ - DeepSx transition
+ - G3
+ Pad settings will not reset on:
+ - S3/S4/S5 transition
+ **/
+ GpioHostDeepReset = 0x03,
+ /**
+ Platform Reset (PLTRST)
+ PadRstCfg = 10b = "GPIO Reset"
+ Pad settings will reset on:
+ - S3/S4/S5 transition
+ - Warm/Cold/Global reset
+ - DeepSx transition
+ - G3
+ **/
+ GpioPlatformReset = 0x05,
+ /**
+ Deep Sleep Well Reset (DSW_PWROK)
+ GPP: not applicable
+ GPD: PadRstCfg = 00b = "Powergood"
+ Pad settings will reset on:
+ - G3
+ Pad settings will not reset on:
+ - S3/S4/S5 transition
+ - Warm/Cold/Global reset
+ - DeepSx transition
+ **/
+ GpioDswReset = 0x07,
+ /**
+ Global reset. Server chipsets only.
+ PadRstCfg = 11b = "Global reset"
+ Pad settings will reset on:
+ - Global reset
+ - G3
+ Pad settings will not reset on:
+ - S3/S4/S5 transition
+ - Warm/Cold reset
+ - DeepSx transition
+ **/
+ GpioGlobalReset = 0x09
+} GPIO_RESET_CONFIG;
+
+/**
+ GPIO Electrical Configuration
+ Configuration options for GPIO termination setting
+**/
+typedef enum {
+ GpioTermDefault = 0x0, ///< Leave termination setting unmodified
+ GpioTermNone = 0x1, ///< none
+ GpioTermWpd5K = 0x5, ///< 5kOhm weak pull-down
+ GpioTermWpd20K = 0x9, ///< 20kOhm weak pull-down
+ GpioTermWpu1K = 0x13, ///< 1kOhm weak pull-up
+ GpioTermWpu2K = 0x17, ///< 2kOhm weak pull-up
+ GpioTermWpu5K = 0x15, ///< 5kOhm weak pull-up
+ GpioTermWpu20K = 0x19, ///< 20kOhm weak pull-up
+ GpioTermWpu1K2K = 0x1B, ///< 1kOhm & 2kOhm weak pull-up
+ /**
+ Native function controls pads termination
+ This setting is applicable only to some native modes.
+ Please check EDS to determine which native functionality
+ can control pads termination
+ **/
+ GpioTermNative = 0x1F
+} GPIO_ELECTRICAL_CONFIG;
+
+#define B_GPIO_ELECTRICAL_CONFIG_TERMINATION_MASK 0x1F ///< Mask for GPIO_ELECTRICAL_CONFIG for termination value
+
+/**
+ GPIO LockConfiguration
+ Set GPIO configuration lock and output state lock.
+ GpioPadConfigUnlock/Lock and GpioOutputStateUnlock can be OR'ed.
+ By default GPIO pads will be locked unless GPIO lib is explicitly
+ informed that certain pad is to be left unlocked.
+ Lock settings reset is in Powergood domain. Care must be taken when using this setting
+ as fields it locks may be reset by a different signal and can be controlled
+ by what is in GPIO_RESET_CONFIG (PADCFG_DW0.PadRstCfg). GPIO library provides
+ functions which allow to unlock a GPIO pad. If possible each GPIO lib function will try to unlock
+ an already locked pad upon request for reconfiguration
+**/
+typedef enum {
+ /**
+ Perform default action
+ - if pad is an GPO, lock configuration but leave output unlocked
+ - if pad is an GPI, lock everything
+ - if pad is in native, lock everything
+**/
+ GpioLockDefault = 0x0,
+ GpioPadConfigUnlock = 0x3, ///< Leave Pad configuration unlocked
+ GpioPadConfigLock = 0x1, ///< Lock Pad configuration
+ GpioOutputStateUnlock = 0xC, ///< Leave Pad output control unlocked
+ GpioPadUnlock = 0xF, ///< Leave both Pad configuration and output control unlocked
+ GpioPadLock = 0x5, ///< Lock both Pad configuration and output control
+ /**
+ Below statuses are used for
+ return from GpioGetPadConfig function
+ **/
+ GpioLockTxLockCfgUnLock = 0x7, ///< Tx State locked, Pad Configuration unlocked
+ GpioLockTxUnLockCfgLock = 0xD ///< Tx State unlocked, Pad Configuration locked
+} GPIO_LOCK_CONFIG;
+
+#define B_GPIO_LOCK_CONFIG_PAD_CONF_LOCK_MASK 0x3 ///< Mask for GPIO_LOCK_CONFIG for Pad Configuration Lock
+#define B_GPIO_LOCK_CONFIG_OUTPUT_LOCK_MASK 0xC ///< Mask for GPIO_LOCK_CONFIG for Pad Output Lock
+
+/**
+ Other GPIO Configuration
+ GPIO_OTHER_CONFIG is used for less often settings and for future extensions
+ Supported settings:
+ - RX raw override to '1' - allows to override input value to '1'
+ This setting is applicable only if in input mode (both in GPIO and native usage).
+ The override takes place at the internal pad state directly from buffer and before the RXINV.
+**/
+typedef enum {
+ GpioRxRaw1Default = 0x0, ///< Use default input override value
+ GpioRxRaw1Dis = 0x1, ///< Don't override input
+ GpioRxRaw1En = 0x3 ///< Override input to '1'
+} GPIO_OTHER_CONFIG;
+
+/**
+ Virtual GPIO eSPI Chip Select configuration
+ This setting selects between CS0 and CS1.
+ Supported settings:
+ - Chipselect CS0 and CS1
+**/
+typedef enum {
+ VgpioCs0 = 0x0, ///< Chipselect CS0
+ VgpioCs1 = 0x1, ///< Chipselect CS1
+} VGPIO_CS_CONFIG;
+
+#define B_GPIO_OTHER_CONFIG_RXRAW_MASK 0x3 ///< Mask for GPIO_OTHER_CONFIG for RxRaw1 setting
+
+#pragma pack(pop)
+
+#endif //_GPIO_CONFIG_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/GpioLib.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/GpioLib.h
new file mode 100644
index 0000000000..d787e13be4
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/GpioLib.h
@@ -0,0 +1,174 @@
+/** @file
+ Header file for GpioLib.
+ All function in this library is available for PEI, DXE, and SMM
+
+ @note: When GPIO pads are owned by ME Firmware, BIOS/host should not
+ attempt to access these GPIO Pads registers, registers value
+ returned in this case will be 0xFF.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _GPIO_LIB_H_
+#define _GPIO_LIB_H_
+
+#include <Library/GpioConfig.h>
+
+typedef struct {
+ GPIO_PAD GpioPad;
+ GPIO_CONFIG GpioConfig;
+} GPIO_INIT_CONFIG;
+
+/**
+ This procedure will initialize multiple GPIO pins. Use GPIO_INIT_CONFIG structure.
+ Structure contains fields that can be used to configure each pad.
+ Pad not configured using GPIO_INIT_CONFIG will be left with hardware default values.
+ Separate fields could be set to hardware default if it does not matter, except
+ GpioPad and PadMode.
+ Function will work in most efficient way if pads which belong to the same group are
+ placed in adjacent records of the table.
+ Although function can enable pads for Native mode, such programming is done
+ by reference code when enabling related silicon feature.
+
+ @param[in] NumberofItem Number of GPIO pads to be updated
+ @param[in] GpioInitTableAddress GPIO initialization table
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid group or pad number
+**/
+EFI_STATUS
+GpioConfigurePads (
+ IN UINT32 NumberOfItems,
+ IN GPIO_INIT_CONFIG *GpioInitTableAddress
+ );
+
+///
+/// Possible values of Pad Ownership
+/// If Pad is not under Host ownership then GPIO registers
+/// are not accessible by host (e.g. BIOS) and reading them
+/// will return 0xFFs.
+///
+typedef enum {
+ GpioPadOwnHost = 0x0,
+ GpioPadOwnCsme = 0x1,
+ GpioPadOwnIsh = 0x2,
+} GPIO_PAD_OWN;
+
+/**
+ This procedure will get Gpio Pad Ownership
+
+ @param[in] GpioPad GPIO pad
+ @param[out] PadOwnVal Value of Pad Ownership
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid GpioPad
+**/
+EFI_STATUS
+GpioGetPadOwnership (
+ IN GPIO_PAD GpioPad,
+ OUT GPIO_PAD_OWN *PadOwnVal
+ );
+
+/**
+ This procedure will check state of Pad Config Lock for pads within one group
+
+ @param[in] Group GPIO group
+ @param[in] DwNum PadCfgLock register number for current group.
+ For group which has less then 32 pads per group DwNum must be 0.
+ @param[out] PadCfgLockRegVal Value of PadCfgLock register
+ Bit position - PadNumber
+ Bit value - 0: NotLocked, 1: Locked
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid group or DwNum parameter number
+**/
+EFI_STATUS
+GpioGetPadCfgLockForGroupDw (
+ IN GPIO_GROUP Group,
+ IN UINT32 DwNum,
+ OUT UINT32 *PadCfgLockRegVal
+ );
+
+/**
+ This procedure will check state of Pad Config Tx Lock for pads within one group
+
+ @param[in] Group GPIO group
+ @param[in] DwNum PadCfgLockTx register number for current group.
+ For group which has less then 32 pads per group DwNum must be 0.
+ @param[out] PadCfgLockTxRegVal Value of PadCfgLockTx register
+ Bit position - PadNumber
+ Bit value - 0: NotLockedTx, 1: LockedTx
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid group or DwNum parameter number
+**/
+EFI_STATUS
+GpioGetPadCfgLockTxForGroupDw (
+ IN GPIO_GROUP Group,
+ IN UINT32 DwNum,
+ OUT UINT32 *PadCfgLockTxRegVal
+ );
+
+/**
+ This procedure will clear PadCfgLock for selected pads within one group.
+ Unlocking a pad will cause an SMI (if enabled)
+
+ @param[in] Group GPIO group
+ @param[in] DwNum PadCfgLock register number for current group.
+ For group which has less then 32 pads per group DwNum must be 0.
+ @param[in] PadsToUnlock Bitmask for pads which are going to be unlocked,
+ Bit position - PadNumber
+ Bit value - 0: DoNotUnlock, 1: Unlock
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid group or pad number
+**/
+EFI_STATUS
+GpioUnlockPadCfgForGroupDw (
+ IN GPIO_GROUP Group,
+ IN UINT32 DwNum,
+ IN UINT32 PadsToUnlock
+ );
+
+/**
+ This procedure will set PadCfgLock for selected pads within one group
+
+ @param[in] Group GPIO group
+ @param[in] DwNum PadCfgLock register number for current group.
+ For group which has less then 32 pads per group DwNum must be 0.
+ @param[in] PadsToLock Bitmask for pads which are going to be locked,
+ Bit position - PadNumber
+ Bit value - 0: DoNotLock, 1: Lock
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid group or DwNum parameter number
+**/
+EFI_STATUS
+GpioLockPadCfgForGroupDw (
+ IN GPIO_GROUP Group,
+ IN UINT32 DwNum,
+ IN UINT32 PadsToLock
+ );
+
+/**
+ This procedure will clear PadCfgLockTx for selected pads within one group.
+ Unlocking a pad will cause an SMI (if enabled)
+
+ @param[in] Group GPIO group
+ @param[in] DwNum PadCfgLockTx register number for current group.
+ For group which has less then 32 pads per group DwNum must be 0.
+ @param[in] PadsToUnlockTx Bitmask for pads which are going to be unlocked,
+ Bit position - PadNumber
+ Bit value - 0: DoNotUnLockTx, 1: LockTx
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid group or pad number
+**/
+EFI_STATUS
+GpioUnlockPadCfgTxForGroupDw (
+ IN GPIO_GROUP Group,
+ IN UINT32 DwNum,
+ IN UINT32 PadsToUnlockTx
+ );
+
+#endif // _GPIO_LIB_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/GpioNativeLib.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/GpioNativeLib.h
new file mode 100644
index 0000000000..971f931442
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/GpioNativeLib.h
@@ -0,0 +1,135 @@
+/** @file
+ Header file for GpioLib for native and Si specific usage.
+ All function in this library is available for PEI, DXE, and SMM,
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _GPIO_NATIVE_LIB_H_
+#define _GPIO_NATIVE_LIB_H_
+
+#include <Library/GpioConfig.h>
+
+/**
+ This procedure will get number of pads for certain GPIO group
+
+ @param[in] Group GPIO group number
+
+ @retval Value Pad number for group
+ If illegal group number then return 0
+**/
+UINT32
+GpioGetPadPerGroup (
+ IN GPIO_GROUP Group
+ );
+
+/**
+ This procedure will get number of groups
+
+ @param[in] none
+
+ @retval Value Group number
+**/
+UINT32
+GpioGetNumberOfGroups (
+ VOID
+ );
+/**
+ This procedure will get lowest group
+
+ @param[in] none
+
+ @retval Value Lowest Group
+**/
+GPIO_GROUP
+GpioGetLowestGroup (
+ VOID
+ );
+
+/**
+ This procedure will get highest group
+
+ @param[in] none
+
+ @retval Value Highest Group
+**/
+GPIO_GROUP
+GpioGetHighestGroup (
+ VOID
+ );
+
+/**
+ This procedure will get group
+
+ @param[in] GpioPad Gpio Pad
+
+ @retval Value Group
+**/
+GPIO_GROUP
+GpioGetGroupFromGpioPad (
+ IN GPIO_PAD GpioPad
+ );
+
+/**
+ This procedure will get group index (0 based) from GpioPad
+
+ @param[in] GpioPad Gpio Pad
+
+ @retval Value Group Index
+**/
+UINT32
+GpioGetGroupIndexFromGpioPad (
+ IN GPIO_PAD GpioPad
+ );
+
+/**
+ This procedure will get group index (0 based) from group
+
+ @param[in] GpioGroup Gpio Group
+
+ @retval Value Group Index
+**/
+UINT32
+GpioGetGroupIndexFromGroup (
+ IN GPIO_GROUP GpioGroup
+ );
+
+/**
+ This procedure will get group from group index (0 based)
+
+ @param[in] GroupIndex Group Index
+
+ @retval GpioGroup Gpio Group
+**/
+GPIO_GROUP
+GpioGetGroupFromGroupIndex (
+ IN UINT32 GroupIndex
+ );
+
+/**
+ This procedure will get pad number (0 based) from Gpio Pad
+
+ @param[in] GpioPad Gpio Pad
+
+ @retval Value Pad Number
+**/
+UINT32
+GpioGetPadNumberFromGpioPad (
+ IN GPIO_PAD GpioPad
+ );
+
+/**
+ This procedure will return GpioPad from Group and PadNumber
+
+ @param[in] Group GPIO group
+ @param[in] PadNumber GPIO PadNumber
+
+ @retval GpioPad GpioPad
+**/
+GPIO_PAD
+GpioGetGpioPadFromGroupAndPadNumber (
+ IN GPIO_GROUP Group,
+ IN UINT32 PadNumber
+ );
+
+#endif // _GPIO_NATIVE_LIB_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/GraphicsInfoLib.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/GraphicsInfoLib.h
new file mode 100644
index 0000000000..bd9a7734b1
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/GraphicsInfoLib.h
@@ -0,0 +1,46 @@
+/** @file
+ Header file for Graphics Private Info Lib implementation.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _GRAPHICS_INFO_LIB_H_
+#define _GRAPHICS_INFO_LIB_H_
+
+#include <Library/BaseLib.h>
+#include <Library/PciSegmentLib.h>
+#include <IndustryStandard/Pci22.h>
+#include <Register/SaRegsHostBridge.h>
+
+/**
+ GetIgdBusNumber: Get IGD Bus Number
+
+ @retval PCI bus number for IGD
+**/
+UINT8
+GetIgdBusNumber (
+ VOID
+ );
+
+/**
+ GetIgdDevNumber: Get IGD Dev Number
+
+ @retval PCI dev number for IGD
+**/
+UINT8
+GetIgdDevNumber (
+ VOID
+ );
+
+/**
+ GetIgdFunNumber: Get IGD Fun Number
+
+ @retval PCI fun number for IGD
+**/
+UINT8
+GetIgdFuncNumber (
+ VOID
+ );
+
+#endif
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/MmPciLib.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/MmPciLib.h
new file mode 100644
index 0000000000..04249eefdf
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/MmPciLib.h
@@ -0,0 +1,27 @@
+/** @file
+ Get Pci Express address library implementation.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _MM_PCI_LIB_H_
+#define _MM_PCI_LIB_H_
+
+/**
+ This procedure will get PCIE address
+
+ @param[in] Bus Pci Bus Number
+ @param[in] Device Pci Device Number
+ @param[in] Function Pci Function Number
+
+ @retval PCIE address
+**/
+UINTN
+EFIAPI
+MmPciBase (
+ IN UINT32 Bus,
+ IN UINT32 Device,
+ IN UINT32 Function
+);
+
+#endif // _PEI_DXE_SMM_MM_PCI_LIB_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/PchPcieRpLib.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/PchPcieRpLib.h
new file mode 100644
index 0000000000..d9ca215d85
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/PchPcieRpLib.h
@@ -0,0 +1,41 @@
+/** @file
+ Header file for PchPcieRpLib.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _PCH_PCIERP_LIB_H_
+#define _PCH_PCIERP_LIB_H_
+
+#include <Uefi.h>
+#include <Library/PchPcrLib.h>
+
+/**
+ Get Pch Pcie Root Port Device and Function Number by Root Port physical Number
+
+ @param[in] RpNumber Root port physical number. (0-based)
+ @param[out] RpDev Return corresponding root port device number.
+ @param[out] RpFun Return corresponding root port function number.
+
+ @retval EFI_SUCCESS
+**/
+EFI_STATUS
+EFIAPI
+GetPchPcieRpDevFun (
+ IN UINTN RpNumber,
+ OUT UINTN *RpDev,
+ OUT UINTN *RpFun
+ );
+
+/**
+ Gets pci segment base address of PCIe root port.
+
+ @param RpIndex Root Port Index (0 based)
+ @return PCIe port base address.
+**/
+UINT64
+PchPcieBase (
+ IN UINT32 RpIndex
+ );
+
+#endif // _PCH_PCIERP_LIB_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/PchPcrLib.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/PchPcrLib.h
new file mode 100644
index 0000000000..19a1a98639
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/PchPcrLib.h
@@ -0,0 +1,221 @@
+/** @file
+ Header file for PchPcrLib.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _PCH_PCR_LIB_H_
+#define _PCH_PCR_LIB_H_
+
+#include <PchReservedResources.h>
+
+/**
+ Definition for PCR address
+ The PCR address is used to the PCR MMIO programming
+
+ SBREG_BAR_20BITADDRESS is configured by SoC
+
+ SBREG_BAR_20BITADDRESS=1, the format has included 16b addressing.
+ +---------------------------------------------------------------------------------------------+
+ | Addr[63:28] | Addr[27:24] | Addr[23:16] | Addr[15:2] | Addr[1:0] |
+ +----------------+-----------------------+-----------------+----------------------------------+
+ | REG_BAR[63:28] | TargetRegister[19:16] | TargetPort[7:0] | TargetRegister[15:2] |
+ +---------------------------------------------------------------------------------------------+
+
+ SBREG_BAR_20BITADDRESS=0
+ +---------------------------------------------------------------------------------------------+
+ | Addr[63:24] | Addr[27:24] | Addr[23:16] | Addr[15:2] | Addr[1:0] |
+ +----------------+-----------------------+-----------------+----------------------------------+
+ | REG_BAR[63:24] | REG_BAR[27:24] | TargetPort[7:0] | TargetRegister[15:2] |
+ +---------------------------------------------------------------------------------------------+
+**/
+#define PCH_PCR_ADDRESS(Pid, Offset) (PCH_PCR_BASE_ADDRESS | (UINT32) (((Offset) & 0x0F0000) << 8) | ((UINT8)(Pid) << 16) | (UINT16) ((Offset) & 0xFFFF))
+
+/**
+ PCH PCR boot script accessing macro
+ Those macros are only available for DXE phase.
+**/
+#define PCH_PCR_BOOT_SCRIPT_WRITE(Width, Pid, Offset, Count, Buffer) \
+ S3BootScriptSaveMemWrite (Width, PCH_PCR_ADDRESS (Pid, Offset), Count, Buffer); \
+
+#define PCH_PCR_BOOT_SCRIPT_READ_WRITE(Width, Pid, Offset, DataOr, DataAnd) \
+ S3BootScriptSaveMemReadWrite (Width, PCH_PCR_ADDRESS (Pid, Offset), DataOr, DataAnd); \
+
+#define PCH_PCR_BOOT_SCRIPT_READ(Width, Pid, Offset, BitMask, BitValue) \
+ S3BootScriptSaveMemPoll (Width, PCH_PCR_ADDRESS (Pid, Offset), BitMask, BitValue, 1, 1);
+
+typedef UINT8 PCH_SBI_PID;
+
+/**
+ Read PCR register.
+ It returns PCR register and size in 4bytes.
+ The Offset should not exceed 0xFFFF and must be aligned with size.
+
+ @param[in] Pid Port ID
+ @param[in] Offset Register offset of this Port ID
+
+ @retval UINT32 PCR register value.
+**/
+UINT32
+PchPcrRead32 (
+ IN PCH_SBI_PID Pid,
+ IN UINT32 Offset
+ );
+
+/**
+ Read PCR register.
+ It returns PCR register and size in 2bytes.
+ The Offset should not exceed 0xFFFF and must be aligned with size.
+
+ @param[in] Pid Port ID
+ @param[in] Offset Register offset of this Port ID
+
+ @retval UINT16 PCR register value.
+**/
+UINT16
+PchPcrRead16 (
+ IN PCH_SBI_PID Pid,
+ IN UINT32 Offset
+ );
+
+/**
+ Read PCR register.
+ It returns PCR register and size in 1bytes.
+ The Offset should not exceed 0xFFFF and must be aligned with size.
+
+ @param[in] Pid Port ID
+ @param[in] Offset Register offset of this Port ID
+
+ @retval UINT8 PCR register value
+**/
+UINT8
+PchPcrRead8 (
+ IN PCH_SBI_PID Pid,
+ IN UINT32 Offset
+ );
+
+/**
+ Write PCR register.
+ It programs PCR register and size in 4bytes.
+ The Offset should not exceed 0xFFFF and must be aligned with size.
+
+ @param[in] Pid Port ID
+ @param[in] Offset Register offset of Port ID.
+ @param[in] Data Input Data. Must be the same size as Size parameter.
+
+ @retval UINT32 Value written to register
+**/
+UINT32
+PchPcrWrite32 (
+ IN PCH_SBI_PID Pid,
+ IN UINT32 Offset,
+ IN UINT32 InData
+ );
+
+/**
+ Write PCR register.
+ It programs PCR register and size in 2bytes.
+ The Offset should not exceed 0xFFFF and must be aligned with size.
+
+ @param[in] Pid Port ID
+ @param[in] Offset Register offset of Port ID.
+ @param[in] Data Input Data. Must be the same size as Size parameter.
+
+ @retval UINT16 Value written to register
+**/
+UINT16
+PchPcrWrite16 (
+ IN PCH_SBI_PID Pid,
+ IN UINT32 Offset,
+ IN UINT16 InData
+ );
+
+/**
+ Write PCR register.
+ It programs PCR register and size in 1bytes.
+ The Offset should not exceed 0xFFFF and must be aligned with size.
+
+ @param[in] Pid Port ID
+ @param[in] Offset Register offset of Port ID.
+ @param[in] Data Input Data. Must be the same size as Size parameter.
+
+ @retval UINT8 Value written to register
+**/
+UINT8
+PchPcrWrite8 (
+ IN PCH_SBI_PID Pid,
+ IN UINT32 Offset,
+ IN UINT8 InData
+ );
+
+/**
+ Write PCR register.
+ It programs PCR register and size in 4bytes.
+ The Offset should not exceed 0xFFFF and must be aligned with size.
+
+ @param[in] Pid Port ID
+ @param[in] Offset Register offset of Port ID.
+ @param[in] AndData AND Data. Must be the same size as Size parameter.
+ @param[in] OrData OR Data. Must be the same size as Size parameter.
+
+ @retval UINT32 Value written to register
+
+**/
+UINT32
+PchPcrAndThenOr32 (
+ IN PCH_SBI_PID Pid,
+ IN UINT32 Offset,
+ IN UINT32 AndData,
+ IN UINT32 OrData
+ );
+
+/**
+ Write PCR register.
+ It programs PCR register and size in 2bytes.
+ The Offset should not exceed 0xFFFF and must be aligned with size.
+
+ @param[in] Pid Port ID
+ @param[in] Offset Register offset of Port ID.
+ @param[in] AndData AND Data. Must be the same size as Size parameter.
+ @param[in] OrData OR Data. Must be the same size as Size parameter.
+
+ @retval UINT16 Value written to register
+
+**/
+UINT16
+PchPcrAndThenOr16 (
+ IN PCH_SBI_PID Pid,
+ IN UINT32 Offset,
+ IN UINT16 AndData,
+ IN UINT16 OrData
+ );
+
+/**
+ Write PCR register.
+ It programs PCR register and size in 1bytes.
+ The Offset should not exceed 0xFFFF and must be aligned with size.
+
+ @param[in] Pid Port ID
+ @param[in] Offset Register offset of Port ID.
+ @param[in] AndData AND Data. Must be the same size as Size parameter.
+ @param[in] OrData OR Data. Must be the same size as Size parameter.
+
+ @retval UINT8 Value written to register
+
+**/
+UINT8
+PchPcrAndThenOr8 (
+ IN PCH_SBI_PID Pid,
+ IN UINT32 Offset,
+ IN UINT8 AndData,
+ IN UINT8 OrData
+ );
+
+
+typedef enum {
+ PchIpDmi = 1,
+ PchIpIclk,
+} PCH_IP_PID_ENUM;
+
+
+#endif // _PCH_PCR_LIB_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/PeiDxeSmmReserveMmio64SizeLib.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/PeiDxeSmmReserveMmio64SizeLib.h
new file mode 100644
index 0000000000..d27f858892
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/PeiDxeSmmReserveMmio64SizeLib.h
@@ -0,0 +1,21 @@
+/** @file
+ PEI/DXE/SMM library for reserved 64-bit MMIO space.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PEI_DXE_SMM_RESERVE_MMIO_64_SIZE_LIB_H_
+#define _PEI_DXE_SMM_RESERVE_MMIO_64_SIZE_LIB_H_
+
+/**
+ The function return the 64 bit MMIO size to reserve.
+
+ @retval The 64-bit MMIO size
+**/
+UINT64
+ReserveMmio64Size (
+ VOID
+ );
+
+#endif // _PEI_DXE_SMM_RESERVE_MMIO_64_SIZE_LIB_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/PeiSiPolicyUpdateLib.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/PeiSiPolicyUpdateLib.h
new file mode 100644
index 0000000000..79e7752e4a
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/PeiSiPolicyUpdateLib.h
@@ -0,0 +1,154 @@
+/** @file
+ Header file for PEI SiPolicyUpdate Library.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PEI_SI_POLICY_UPDATE_LIB_H_
+#define _PEI_SI_POLICY_UPDATE_LIB_H_
+
+#include <Ppi/SiPolicy.h>
+
+/**
+ This function performs CPU PEI Policy initialization in Post-memory.
+
+ @retval EFI_SUCCESS The PPI is installed and initialized.
+ @retval EFI ERRORS The PPI is not successfully installed.
+ @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize the driver
+**/
+EFI_STATUS
+EFIAPI
+UpdatePeiCpuPolicy (
+ VOID
+ );
+
+/**
+ This function performs CPU PEI Policy initialization in PreMem.
+
+ @retval EFI_SUCCESS The PPI is installed and initialized.
+ @retval EFI ERRORS The PPI is not successfully installed.
+ @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize the driver
+**/
+EFI_STATUS
+EFIAPI
+UpdatePeiCpuPolicyPreMem (
+ VOID
+ );
+
+
+/**
+ This function performs SA PEI Policy initialization.
+
+ @retval EFI_SUCCESS The PPI is installed and initialized.
+**/
+EFI_STATUS
+EFIAPI
+UpdatePeiSaPolicy (
+ VOID
+ );
+
+/**
+ This function performs SA PEI Policy initialization for PreMem.
+
+ @retval EFI_SUCCESS Update complete.
+**/
+EFI_STATUS
+EFIAPI
+UpdatePeiSaPolicyPreMem (
+ VOID
+ );
+
+/**
+ This function performs PCH PEI Policy initialization.
+
+ @retval EFI_SUCCESS The PPI is installed and initialized.
+ @retval EFI ERRORS The PPI is not successfully installed.
+ @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize the driver
+**/
+EFI_STATUS
+EFIAPI
+UpdatePeiPchPolicy (
+ VOID
+ );
+
+/**
+ This function performs PCH PEI Policy initialization.
+
+ @retval EFI_SUCCESS The PPI is installed and initialized.
+ @retval EFI ERRORS The PPI is not successfully installed.
+ @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize the driver
+**/
+EFI_STATUS
+EFIAPI
+UpdatePeiPchPolicyPreMem (
+ VOID
+ );
+
+/**
+ Update the ME Policy Library
+
+ @retval EFI_SUCCESS Update complete.
+ @retval Others Update unsuccessful.
+**/
+EFI_STATUS
+EFIAPI
+UpdatePeiMePolicy (
+ VOID
+ );
+
+/**
+ Update the ME Policy Library
+
+ @retval EFI_SUCCESS Update complete.
+**/
+EFI_STATUS
+EFIAPI
+UpdatePeiMePolicyPreMem (
+ VOID
+ );
+
+
+
+/**
+ Update the TBT Policy Library
+
+ @retval EFI_SUCCESS Update complete.
+**/
+EFI_STATUS
+EFIAPI
+UpdatePeiTbtPolicy (
+ VOID
+ );
+
+/**
+ Update the ME Server Policy Ppi (pre mem)
+
+ @param[in, out] SiPreMemPolicyPpi PEI Pre Mem Si Policy
+
+ @retval EFI_SUCCESS Initialization complete.
+ @retval EFI_UNSUPPORTED The chipset is unsupported by this driver.
+ @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize the driver.
+ @retval EFI_DEVICE_ERROR Device error, driver exits abnormally.
+ @retval EFI_INVALID_PARAMETER Wrong pointer passed to the function
+**/
+EFI_STATUS
+UpdatePeiMeServerPreMemPolicy (
+ IN OUT SI_PREMEM_POLICY_PPI *SiPreMemPolicy
+ );
+
+/**
+ Update the ME Server Policy Ppi (post mem)
+
+ @param[in, out] SiPolicyPpi PEI Si Policy
+
+ @retval EFI_SUCCESS Initialization complete.
+ @retval EFI_UNSUPPORTED The chipset is unsupported by this driver.
+ @retval EFI_DEVICE_ERROR Device error, driver exits abnormally.
+ @retval EFI_INVALID_PARAMETER Wrong pointer passed to the function
+**/
+ EFI_STATUS
+UpdatePeiMeServerPolicy (
+ IN OUT SI_POLICY_PPI *SiPolicyPpi
+ );
+#endif
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/PmcLib.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/PmcLib.h
new file mode 100644
index 0000000000..7d49a14164
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/PmcLib.h
@@ -0,0 +1,40 @@
+/** @file
+ Header file for PmcLib.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _PMC_LIB_H_
+#define _PMC_LIB_H_
+
+#include <PmConfig.h>
+
+
+typedef struct {
+ UINT32 Buf0;
+ UINT32 Buf1;
+ UINT32 Buf2;
+ UINT32 Buf3;
+} PMC_IPC_COMMAND_BUFFER;
+
+/**
+ Get PCH ACPI base address.
+
+ @retval Address Address of PWRM base address.
+**/
+UINT16
+PmcGetAcpiBase (
+ VOID
+ );
+
+/**
+ Get PCH PWRM base address.
+
+ @retval Address Address of PWRM base address.
+**/
+UINT32
+PmcGetPwrmBase (
+ VOID
+ );
+
+#endif // _PMC_LIB_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/ResetSystemLib.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/ResetSystemLib.h
new file mode 100644
index 0000000000..6146e8610d
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/ResetSystemLib.h
@@ -0,0 +1,68 @@
+/** @file
+ System reset Library Services. This library class defines a set of
+ methods that reset the whole system.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef __RESET_SYSTEM_LIB_H__
+#define __RESET_SYSTEM_LIB_H__
+
+/**
+ This function causes a system-wide reset (cold reset), in which
+ all circuitry within the system returns to its initial state. This type of reset
+ is asynchronous to system operation and operates without regard to
+ cycle boundaries.
+
+ If this function returns, it means that the system does not support cold reset.
+**/
+VOID
+EFIAPI
+ResetCold (
+ VOID
+ );
+
+/**
+ This function causes a system-wide initialization (warm reset), in which all processors
+ are set to their initial state. Pending cycles are not corrupted.
+
+ If this function returns, it means that the system does not support warm reset.
+**/
+VOID
+EFIAPI
+ResetWarm (
+ VOID
+ );
+
+/**
+ This function causes the system to enter a power state equivalent
+ to the ACPI G2/S5 or G3 states.
+
+ If this function returns, it means that the system does not support shutdown reset.
+**/
+VOID
+EFIAPI
+ResetShutdown (
+ VOID
+ );
+
+/**
+ This function causes a systemwide reset. The exact type of the reset is
+ defined by the EFI_GUID that follows the Null-terminated Unicode string passed
+ into ResetData. If the platform does not recognize the EFI_GUID in ResetData
+ the platform must pick a supported reset type to perform.The platform may
+ optionally log the parameters from any non-normal reset that occurs.
+
+ @param[in] DataSize The size, in bytes, of ResetData.
+ @param[in] ResetData The data buffer starts with a Null-terminated string,
+ followed by the EFI_GUID.
+**/
+VOID
+EFIAPI
+ResetPlatformSpecific (
+ IN UINTN DataSize,
+ IN VOID *ResetData
+ );
+
+#endif
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/SecPlatformLib.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/SecPlatformLib.h
new file mode 100644
index 0000000000..7fa23b1a51
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/SecPlatformLib.h
@@ -0,0 +1,81 @@
+/** @file
+ Prototype of SEC Platform hook library.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _SEC_PLATFORM_LIB_H_
+#define _SEC_PLATFORM_LIB_H_
+
+#include <Ppi/SecPlatformInformation.h>
+#include <Ppi/SecPerformance.h>
+
+/**
+ A developer supplied function to perform platform specific operations.
+
+ It's a developer supplied function to perform any operations appropriate to a
+ given platform. It's invoked just before passing control to PEI core by SEC
+ core. Platform developer may modify the SecCoreData passed to PEI Core.
+ It returns a platform specific PPI list that platform wishes to pass to PEI core.
+ The Generic SEC core module will merge this list to join the final list passed to
+ PEI core.
+
+ @param SecCoreData The same parameter as passing to PEI core. It
+ could be overridden by this function.
+
+ @return The platform specific PPI list to be passed to PEI core or
+ NULL if there is no need of such platform specific PPI list.
+
+**/
+EFI_PEI_PPI_DESCRIPTOR *
+EFIAPI
+SecPlatformMain (
+ IN OUT EFI_SEC_PEI_HAND_OFF *SecCoreData
+ );
+
+
+/**
+ This interface conveys state information out of the Security (SEC) phase into PEI.
+
+ @param PeiServices Pointer to the PEI Services Table.
+ @param StructureSize Pointer to the variable describing size of the input buffer.
+ @param PlatformInformationRecord Pointer to the EFI_SEC_PLATFORM_INFORMATION_RECORD.
+
+ @retval EFI_SUCCESS The data was successfully returned.
+ @retval EFI_BUFFER_TOO_SMALL The buffer was too small.
+
+**/
+EFI_STATUS
+EFIAPI
+SecPlatformInformation (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN OUT UINT64 *StructureSize,
+ OUT EFI_SEC_PLATFORM_INFORMATION_RECORD *PlatformInformationRecord
+ );
+
+/**
+ This interface conveys performance information out of the Security (SEC) phase into PEI.
+
+ This service is published by the SEC phase. The SEC phase handoff has an optional
+ EFI_PEI_PPI_DESCRIPTOR list as its final argument when control is passed from SEC into the
+ PEI Foundation. As such, if the platform supports collecting performance data in SEC,
+ this information is encapsulated into the data structure abstracted by this service.
+ This information is collected for the boot-strap processor (BSP) on IA-32.
+
+ @param[in] PeiServices The pointer to the PEI Services Table.
+ @param[in] This The pointer to this instance of the PEI_SEC_PERFORMANCE_PPI.
+ @param[out] Performance The pointer to performance data collected in SEC phase.
+
+ @retval EFI_SUCCESS The data was successfully returned.
+**/
+EFI_STATUS
+EFIAPI
+SecGetPerformance (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN PEI_SEC_PERFORMANCE_PPI *This,
+ OUT FIRMWARE_SEC_PERFORMANCE *Performance
+ );
+
+#endif
+
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/SiConfigBlockLib.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/SiConfigBlockLib.h
new file mode 100644
index 0000000000..7bb111a932
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/SiConfigBlockLib.h
@@ -0,0 +1,56 @@
+/** @file
+ Prototype of the SiConfigBlockLib library.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _SI_CONFIG_BLOCK_LIB_H_
+#define _SI_CONFIG_BLOCK_LIB_H_
+
+
+typedef
+VOID
+(*LOAD_DEFAULT_FUNCTION) (
+ IN VOID *ConfigBlockPointer
+ );
+
+typedef struct {
+ EFI_GUID *Guid;
+ UINT16 Size;
+ UINT8 Revision;
+ LOAD_DEFAULT_FUNCTION LoadDefault;
+} COMPONENT_BLOCK_ENTRY;
+
+/**
+ GetComponentConfigBlockTotalSize get config block table total size.
+
+ @param[in] ComponentBlocks Component blocks array
+ @param[in] TotalBlockCount Number of blocks
+
+ @retval Size of config block table
+**/
+UINT16
+EFIAPI
+GetComponentConfigBlockTotalSize (
+ IN COMPONENT_BLOCK_ENTRY *ComponentBlocks,
+ IN UINT16 TotalBlockCount
+ );
+
+/**
+ AddComponentConfigBlocks add all config blocks.
+
+ @param[in] ConfigBlockTableAddress The pointer to add config blocks
+ @param[in] ComponentBlocks Config blocks array
+ @param[in] TotalBlockCount Number of blocks
+
+ @retval EFI_SUCCESS The policy default is initialized.
+ @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer
+**/
+EFI_STATUS
+EFIAPI
+AddComponentConfigBlocks (
+ IN VOID *ConfigBlockTableAddress,
+ IN COMPONENT_BLOCK_ENTRY *ComponentBlocks,
+ IN UINT16 TotalBlockCount
+ );
+#endif // _SI_CONFIG_BLOCK_LIB_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/SiPolicyLib.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/SiPolicyLib.h
new file mode 100644
index 0000000000..f821ea2fdf
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/SiPolicyLib.h
@@ -0,0 +1,39 @@
+/** @file
+ Prototype of the SiPolicyLib library.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _SI_POLICY_LIB_H_
+#define _SI_POLICY_LIB_H_
+
+#include <Ppi/SiPolicy.h>
+
+/**
+ SiPreMemInstallPolicyReadyPpi installs SiPreMemPolicyReadyPpi.
+ While installed, RC assumes the Policy is ready and finalized. So please update and override
+ any setting before calling this function.
+
+ @retval EFI_SUCCESS The policy is installed.
+ @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer
+**/
+EFI_STATUS
+EFIAPI
+SiPreMemInstallPolicyReadyPpi (
+ VOID
+ );
+
+/**
+ SiInstallPolicyReadyPpi installs SiPolicyReadyPpi.
+ While installed, RC assumes the Policy is ready and finalized. So please update and override
+ any setting before calling this function.
+
+ @retval EFI_SUCCESS The policy is installed.
+ @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer
+**/
+EFI_STATUS
+EFIAPI
+SiInstallPolicyReadyPpi (
+ VOID
+ );
+#endif // _SI_POLICY_LIB_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/SpiLib.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/SpiLib.h
new file mode 100644
index 0000000000..ca56e74e0f
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/SpiLib.h
@@ -0,0 +1,21 @@
+/** @file
+ Header file for Spi Library.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _SPI_LIB_H_
+#define _SPI_LIB_H_
+
+/**
+ This function Initial SPI services
+
+ @retval EFI_STATUS Results of the installation of the SPI services
+**/
+EFI_STATUS
+EFIAPI
+SpiServiceInit (
+ VOID
+ );
+
+#endif
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Pins/GpioPinsVer2Lp.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Pins/GpioPinsVer2Lp.h
new file mode 100644
index 0000000000..2f58de78f6
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Pins/GpioPinsVer2Lp.h
@@ -0,0 +1,36 @@
+/** @file
+ GPIO pins for TGL-PCH-LP,
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _GPIO_PINS_VER2_LP_H_
+#define _GPIO_PINS_VER2_LP_H_
+///
+/// This header file should be used together with
+/// PCH GPIO lib in C and ASL. All defines used
+/// must match both ASL/C syntax
+///
+
+///
+/// Unique ID used in GpioPad defines
+///
+#define GPIO_VER2_LP_CHIPSET_ID 0x9
+
+///
+/// TGL LP GPIO pins
+/// Use below for functions from PCH GPIO Lib which
+/// require GpioPad as argument. Encoding used here
+/// has all information required by library functions
+///
+#define GPIO_VER2_LP_GPP_H0 0x09070000
+#define GPIO_VER2_LP_GPP_H1 0x09070001
+#define GPIO_VER2_LP_GPP_D16 0x09080010
+#define GPIO_VER2_LP_GPP_C2 0x090B0002
+
+#define GPIO_VER2_LP_GPP_F9 0x090C0009
+#define GPIO_VER2_LP_GPP_F10 0x090C000A
+#define GPIO_VER2_LP_GPP_F20 0x090C0014
+
+#define GPIO_VER2_LP_GPP_E7 0x090E0007
+#endif // _GPIO_PINS_VER2_LP_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Ppi/FspmArchConfigPpi.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Ppi/FspmArchConfigPpi.h
new file mode 100644
index 0000000000..7ed834b9f5
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Ppi/FspmArchConfigPpi.h
@@ -0,0 +1,32 @@
+/** @file
+ Header file for FSP-M Arch Config PPI
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _FSPM_ARCH_CONFIG_PPI_H_
+#define _FSPM_ARCH_CONFIG_PPI_H_
+
+///
+/// Global ID for the FSPM_ARCH_CONFIG_PPI.
+///
+#define FSPM_ARCH_CONFIG_GUID \
+ { \
+ 0x824d5a3a, 0xaf92, 0x4c0c, { 0x9f, 0x19, 0x19, 0x52, 0x6d, 0xca, 0x4a, 0xbb } \
+ }
+
+///
+/// This PPI provides FSP-M Arch Config PPI.
+///
+typedef struct {
+ UINT8 Revision;
+ UINT8 Reserved[3];
+ VOID *NvsBufferPtr;
+ UINT32 BootLoaderTolumSize;
+ UINT8 Reserved1[4];
+} FSPM_ARCH_CONFIG_PPI;
+
+extern EFI_GUID gFspmArchConfigPpiGuid;
+
+#endif // _FSPM_ARCH_CONFIG_PPI_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Ppi/PeiPreMemSiDefaultPolicy.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Ppi/PeiPreMemSiDefaultPolicy.h
new file mode 100644
index 0000000000..0713dbd55b
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Ppi/PeiPreMemSiDefaultPolicy.h
@@ -0,0 +1,33 @@
+/** @file
+ This file defines the function to initialize default silicon policy PPI.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI_H_
+#define _PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI_H_
+
+//
+// Forward declaration for the PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI.
+//
+typedef struct _PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI;
+
+/**
+ Initialize and install default silicon policy PPI
+**/
+typedef
+EFI_STATUS
+(EFIAPI *PEI_PREMEM_POLICY_INIT) (
+ VOID
+ );
+
+///
+/// This PPI provides function to install default silicon policy
+///
+struct _PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI {
+ PEI_PREMEM_POLICY_INIT PeiPreMemPolicyInit; ///< PeiPreMemPolicyInit()
+};
+
+extern EFI_GUID gSiPreMemDefaultPolicyInitPpiGuid;
+
+#endif // _PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Ppi/PeiSiDefaultPolicy.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Ppi/PeiSiDefaultPolicy.h
new file mode 100644
index 0000000000..83bdbe0f6e
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Ppi/PeiSiDefaultPolicy.h
@@ -0,0 +1,33 @@
+/** @file
+ This file defines the function to initialize default silicon policy PPI.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _PEI_SI_DEFAULT_POLICY_INIT_PPI_H_
+#define _PEI_SI_DEFAULT_POLICY_INIT_PPI_H_
+
+//
+// Forward declaration for the PEI_SI_DEFAULT_POLICY_INIT_PPI.
+//
+typedef struct _PEI_SI_DEFAULT_POLICY_INIT_PPI PEI_SI_DEFAULT_POLICY_INIT_PPI;
+
+/**
+ Initialize and install default silicon policy PPI
+**/
+typedef
+EFI_STATUS
+(EFIAPI *PEI_POLICY_INIT) (
+ VOID
+ );
+
+///
+/// This PPI provides function to install default silicon policy
+///
+struct _PEI_SI_DEFAULT_POLICY_INIT_PPI {
+ PEI_POLICY_INIT PeiPolicyInit; ///< PeiPolicyInit()
+};
+
+extern EFI_GUID gSiDefaultPolicyInitPpiGuid;
+
+#endif // _PEI_SI_DEFAULT_POLICY_INIT_PPI_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Ppi/Spi.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Ppi/Spi.h
new file mode 100644
index 0000000000..0faf1e3443
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Ppi/Spi.h
@@ -0,0 +1,29 @@
+/** @file
+ This file defines the PCH SPI PPI which implements the
+ Intel(R) PCH SPI Host Controller Compatibility Interface.
+
+ @note The APIs in this file are designed to be backward compatible with
+ previous versions. Any change in behavior of these APIs will result in
+ newer version of the API.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _PCH_SPI_PPI_H_
+#define _PCH_SPI_PPI_H_
+
+#include <Protocol/Spi.h>
+
+//
+// Extern the GUID for PPI users.
+//
+extern EFI_GUID gPchSpiPpiGuid;
+
+/**
+ Reuse the PCH_SPI_PROTOCOL definitions
+ This is possible becaues the PPI implementation does not rely on a PeiService pointer,
+ as it uses EDKII Glue Lib to do IO accesses
+**/
+typedef PCH_SPI_PROTOCOL PCH_SPI_PPI;
+
+#endif
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Ppi/Wdt.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Ppi/Wdt.h
new file mode 100644
index 0000000000..bd8163fea0
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Ppi/Wdt.h
@@ -0,0 +1,22 @@
+/** @file
+ Watchdog Timer PPI
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _PEI_WDT_H_
+#define _PEI_WDT_H_
+
+#include <Protocol/Wdt.h>
+
+//
+// Extern the GUID for PPI users.
+//
+extern EFI_GUID gWdtPpiGuid;
+
+///
+/// Reuse WDT_PROTOCOL definition
+///
+typedef WDT_PROTOCOL WDT_PPI;
+
+#endif
--
2.36.1.windows.1
-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#108692): https://edk2.groups.io/g/devel/message/108692
Mute This Topic: https://groups.io/mt/101373950/7686176
Group Owner: devel+owner@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [rebecca@openfw.io]
-=-=-=-=-=-=-=-=-=-=-=-
^ permalink raw reply related [flat|nested] 41+ messages in thread
* Re: [edk2-devel] [PATCH v2 07/10] AlderlakeSiliconPkg/Include: Add Protocol, Register, Other Includes
2023-09-15 4:45 ` [edk2-devel] [PATCH v2 07/10] AlderlakeSiliconPkg/Include: Add Protocol, Register, Other Includes Saloni Kasbekar
@ 2023-09-15 5:43 ` Chaganty, Rangasai V
2023-09-15 13:28 ` Chuang, Rosen
2023-09-15 23:56 ` Nate DeSimone
1 sibling, 1 reply; 41+ messages in thread
From: Chaganty, Rangasai V @ 2023-09-15 5:43 UTC (permalink / raw)
To: Kasbekar, Saloni, devel@edk2.groups.io
Cc: Desimone, Nathaniel L, Chuang, Rosen
Reviewed-by: Sai Chaganty <rangasai.v.chaganty@intel.com>
-----Original Message-----
From: Kasbekar, Saloni <saloni.kasbekar@intel.com>
Sent: Thursday, September 14, 2023 9:46 PM
To: devel@edk2.groups.io
Cc: Kasbekar, Saloni <saloni.kasbekar@intel.com>; Chaganty, Rangasai V <rangasai.v.chaganty@intel.com>; Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>; Chuang, Rosen <rosen.chuang@intel.com>
Subject: [PATCH v2 07/10] AlderlakeSiliconPkg/Include: Add Protocol, Register, Other Includes
Adds the following Includes:
- Include/
- Include/Protocol
- Include/Register
Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Rosen Chuang <rosen.chuang@intel.com>
Signed-off-by: Saloni Kasbekar <saloni.kasbekar@intel.com>
---
.../AlderlakeSiliconPkg/Include/ConfigBlock.h | 53 +++
.../AlderlakeSiliconPkg/Include/CpuPcieHob.h | 48 +++
.../Include/Protocol/IgdOpRegion.h | 22 ++
.../Include/Protocol/Spi.h | 346 ++++++++++++++++++
.../Include/Protocol/Wdt.h | 111 ++++++
.../Include/Register/FlashRegs.h | 73 ++++
.../Include/Register/GpioRegs.h | 103 ++++++
.../Include/Register/GpioRegsVer2.h | 211 +++++++++++
.../Include/Register/PchDmi14Regs.h | 49 +++
.../Include/Register/PchDmiRegs.h | 51 +++
.../Include/Register/PchPcieRpRegs.h | 45 +++
.../Include/Register/PchRegsLpc.h | 77 ++++
.../Include/Register/PmcRegs.h | 134 +++++++
.../Include/Register/RtcRegs.h | 44 +++
.../Include/Register/TcoRegs.h | 71 ++++
.../Include/SerialIoDevices.h | 226 ++++++++++++
.../AlderlakeSiliconPkg/Include/SiConfigHob.h | 17 +
.../Include/SiPolicyStruct.h | 64 ++++
18 files changed, 1745 insertions(+)
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/CpuPcieHob.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Protocol/IgdOpRegion.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Protocol/Spi.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Protocol/Wdt.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Register/FlashRegs.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Register/GpioRegs.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Register/GpioRegsVer2.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Register/PchDmi14Regs.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Register/PchDmiRegs.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Register/PchPcieRpRegs.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Register/PchRegsLpc.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Register/PmcRegs.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Register/RtcRegs.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Register/TcoRegs.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/SerialIoDevices.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/SiConfigHob.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/SiPolicyStruct.h
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock.h
new file mode 100644
index 0000000000..2e609bc8d9
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock.h
@@ -0,0 +1,53 @@
+/** @file
+ Header file for Config Block Lib implementation
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _CONFIG_BLOCK_H_
+#define _CONFIG_BLOCK_H_
+
+#include <Uefi/UefiBaseType.h>
+#include <Uefi/UefiMultiPhase.h>
+#include <Pi/PiBootMode.h>
+#include <Pi/PiHob.h>
+
+#pragma pack (push,1)
+
+///
+/// Config Block Header
+///
+typedef struct _CONFIG_BLOCK_HEADER {
+ EFI_HOB_GUID_TYPE GuidHob; ///< Offset 0-23 GUID extension HOB header
+ UINT8 Revision; ///< Offset 24 Revision of this config block
+ UINT8 Attributes; ///< Offset 25 The main revision for config block
+ UINT8 Reserved[2]; ///< Offset 26-27 Reserved for future use
+} CONFIG_BLOCK_HEADER;
+
+///
+/// Config Block
+///
+typedef struct _CONFIG_BLOCK {
+ CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Header of config block
+ //
+ // Config Block Data
+ //
+} CONFIG_BLOCK;
+
+///
+/// Config Block Table Header
+///
+typedef struct _CONFIG_BLOCK_TABLE_STRUCT {
+ CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 GUID number for main entry of config block
+ UINT8 Rsvd0[2]; ///< Offset 28-29 Reserved for future use
+ UINT16 NumberOfBlocks; ///< Offset 30-31 Number of config blocks (N)
+ UINT32 AvailableSize; ///< Offset 32-35 Current config block table size
+///
+/// Individual Config Block Structures are added here in memory as part of AddConfigBlock()
+///
+} CONFIG_BLOCK_TABLE_HEADER;
+#pragma pack (pop)
+
+#endif // _CONFIG_BLOCK_H_
+
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/CpuPcieHob.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/CpuPcieHob.h
new file mode 100644
index 0000000000..dccd6e7d7a
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/CpuPcieHob.h
@@ -0,0 +1,48 @@
+/** @file
+ The GUID definition for CpuPcieHob
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _CPU_PCIE_HOB_H_
+#define _CPU_PCIE_HOB_H_
+
+#include <Base.h>
+#include <CpuPcieInfo.h>
+#include <CpuPcieConfig.h>
+
+extern EFI_GUID gCpuPcieHobGuid;
+#pragma pack (push,1)
+
+
+/**
+ The CPU_PCIE_HOB block describes the expected configuration of the CpuPcie controllers
+**/
+typedef struct {
+ ///
+ /// These members describe the configuration of each CPU PCIe root port.
+ ///
+ EFI_HOB_GUID_TYPE EfiHobGuidType; ///< Offset 0 - 23: GUID Hob type structure for gCpuPcieHobGuid
+ CPU_PCIE_ROOT_PORT_CONFIG RootPort[CPU_PCIE_MAX_ROOT_PORTS];
+ UINT8 L1SubStates[CPU_PCIE_MAX_ROOT_PORTS]; ///< The L1 Substates configuration of the root port
+
+ UINT32 DekelFwVersionMinor; ///< Dekel Firmware Minor Version
+ UINT32 DekelFwVersionMajor; ///< Dekel Firmware Major Version
+ BOOLEAN InitPcieAspmAfterOprom; ///< 1=initialize PCIe ASPM after Oprom; 0=before (This will be set basing on policy)
+ UINT32 RpEnabledMask; ///< Rootport enabled mask based on DEVEN register
+ UINT32 RpEnMaskFromDevEn; ///< Rootport enabled mask based on Device Id
+ UINT8 DisableClkReqMsg[CPU_PCIE_MAX_ROOT_PORTS]; ///< 1=ClkReqMsg disabled, 0=ClkReqMsg enabled
+ UINT8 SlotSelection; ///< 1=M2 slot, 0=CEMx4 slot
+ BOOLEAN ComplianceTest; ///< Compliance Test based on policy
+ UINT32 HsPhyRecipeVersionMajor; ///< HS-Phy Recipe Major Version
+ UINT32 HsPhyRecipeVersionMinor; ///< HS-Phy Recipe Minor Version
+ UINT32 HsPhyFwProdMajor; ///< HS-Phy Firmware Product Major Verison
+ UINT32 HsPhyFwProdMinor; ///< HS-Phy Firmware Product Minor Verison
+ UINT32 HsPhyFwHotFix; ///< HS-Phy Firmware Hot Fix Version
+ UINT32 HsPhyFwBuild; ///< HS-Phy Firmware Build version
+ UINT32 HsPhyFwEvBitProgMajor; ///< HS-Phy Firmware EV Bit Prog Major
+ UINT32 HsPhyFwEvBitProgMinor; ///< HS-Phy Firmware EV Bit Prog Minor
+ UINT32 HsPhyMap; ///< HS-Phy Mapping Based on HS-Py supported ports
+} CPU_PCIE_HOB;
+#pragma pack (pop)
+#endif
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Protocol/IgdOpRegion.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Protocol/IgdOpRegion.h
new file mode 100644
index 0000000000..9f69671f35
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Protocol/IgdOpRegion.h
@@ -0,0 +1,22 @@
+/** @file
+ This file is part of the IGD OpRegion Implementation. The IGD OpRegion is
+ an interface between system BIOS, ASL code, and Graphics drivers.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _IGD_OPREGION_PROTOCOL_H_
+#define _IGD_OPREGION_PROTOCOL_H_
+
+#include <IndustryStandard/IgdOpRegion.h>
+
+extern EFI_GUID gIgdOpRegionProtocolGuid;
+
+///
+/// IGD OpRegion Protocol
+///
+typedef struct {
+ IGD_OPREGION_STRUCTURE *OpRegion; ///< IGD Operation Region Structure
+} IGD_OPREGION_PROTOCOL;
+
+#endif
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Protocol/Spi.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Protocol/Spi.h
new file mode 100644
index 0000000000..cbf2883fa4
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Protocol/Spi.h
@@ -0,0 +1,346 @@
+/** @file
+ This file defines the PCH SPI Protocol which implements the
+ Intel(R) PCH SPI Host Controller Compatibility Interface.
+
+ @note The APIs in this file are designed to be backward compatible with
+ previous versions. Any change in behavior of these APIs will result in
+ newer version of the API.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _PCH_SPI_PROTOCOL_H_
+#define _PCH_SPI_PROTOCOL_H_
+
+//
+// Extern the GUID for protocol users.
+//
+extern EFI_GUID gPchSpiProtocolGuid;
+extern EFI_GUID gPchSmmSpiProtocolGuid;
+
+//
+// Forward reference for ANSI C compatibility
+//
+typedef struct _PCH_SPI_PROTOCOL PCH_SPI_PROTOCOL;
+
+//
+// SPI protocol data structures and definitions
+//
+
+/**
+ Flash Region Type
+**/
+typedef enum {
+ FlashRegionDescriptor,
+ FlashRegionBios,
+ FlashRegionMe,
+ FlashRegionGbE,
+ FlashRegionPlatformData,
+ FlashRegionDer,
+ FlashRegionSecondaryBios,
+ FlashRegionuCodePatch,
+ FlashRegionEC,
+ FlashRegionDeviceExpansion2,
+ FlashRegionIE,
+ FlashRegion10Gbe_A,
+ FlashRegion10Gbe_B,
+ FlashRegion13,
+ FlashRegion14,
+ FlashRegion15,
+ FlashRegionAll,
+ FlashRegionMax
+} FLASH_REGION_TYPE;
+
+//
+// Protocol member functions
+//
+
+/**
+ Read data from the flash part.
+
+ @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
+ @param[in] FlashRegionType The Flash Region type for flash cycle which
+ is listed in the Descriptor.
+ @param[in] Address The Flash Linear Address must fall within a
+ region for which BIOS has access permissions.
+ @param[in] ByteCount Number of bytes in the data portion of the
+ SPI cycle.
+ @param[out] Buffer The Pointer to caller-allocated buffer
+ containing the dada received.
+ It is the caller's responsibility to make
+ sure Buffer is large enough for the total
+ number of bytes read.
+
+ @retval EFI_SUCCESS Command succeed.
+ @retval EFI_INVALID_PARAMETER The parameters specified are not valid.
+ @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *PCH_SPI_FLASH_READ) (
+ IN PCH_SPI_PROTOCOL *This,
+ IN FLASH_REGION_TYPE FlashRegionType,
+ IN UINT32 Address,
+ IN UINT32 ByteCount,
+ OUT UINT8 *Buffer
+ );
+
+/**
+ Write data to the flash part. Remark: Erase may be needed before write to the
+ flash part.
+
+ @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
+ @param[in] FlashRegionType The Flash Region type for flash cycle which
+ is listed in the Descriptor.
+ @param[in] Address The Flash Linear Address must fall within a
+ region for which BIOS has access permissions.
+ @param[in] ByteCount Number of bytes in the data portion of the
+ SPI cycle.
+ @param[in] Buffer Pointer to caller-allocated buffer containing
+ the data sent during the SPI cycle.
+
+ @retval EFI_SUCCESS Command succeed.
+ @retval EFI_INVALID_PARAMETER The parameters specified are not valid.
+ @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *PCH_SPI_FLASH_WRITE) (
+ IN PCH_SPI_PROTOCOL *This,
+ IN FLASH_REGION_TYPE FlashRegionType,
+ IN UINT32 Address,
+ IN UINT32 ByteCount,
+ IN UINT8 *Buffer
+ );
+
+/**
+ Erase area on the flash part.
+
+ @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
+ @param[in] FlashRegionType The Flash Region type for flash cycle which
+ is listed in the Descriptor.
+ @param[in] Address The Flash Linear Address must fall within a
+ region for which BIOS has access permissions.
+ @param[in] ByteCount Number of bytes in the data portion of the
+ SPI cycle.
+
+ @retval EFI_SUCCESS Command succeed.
+ @retval EFI_INVALID_PARAMETER The parameters specified are not valid.
+ @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *PCH_SPI_FLASH_ERASE) (
+ IN PCH_SPI_PROTOCOL *This,
+ IN FLASH_REGION_TYPE FlashRegionType,
+ IN UINT32 Address,
+ IN UINT32 ByteCount
+ );
+
+/**
+ Read SFDP data from the flash part.
+
+ @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
+ @param[in] ComponentNumber The Componen Number for chip select
+ @param[in] Address The starting byte address for SFDP data read.
+ @param[in] ByteCount Number of bytes in SFDP data portion of the
+ SPI cycle
+ @param[out] SfdpData The Pointer to caller-allocated buffer
+ containing the SFDP data received
+ It is the caller's responsibility to make
+ sure Buffer is large enough for the total
+ number of bytes read
+
+ @retval EFI_SUCCESS Command succeed.
+ @retval EFI_INVALID_PARAMETER The parameters specified are not valid.
+ @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *PCH_SPI_FLASH_READ_SFDP) (
+ IN PCH_SPI_PROTOCOL *This,
+ IN UINT8 ComponentNumber,
+ IN UINT32 Address,
+ IN UINT32 ByteCount,
+ OUT UINT8 *SfdpData
+ );
+
+/**
+ Read Jedec Id from the flash part.
+
+ @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
+ @param[in] ComponentNumber The Componen Number for chip select
+ @param[in] ByteCount Number of bytes in JedecId data portion of
+ the SPI cycle, the data size is 3 typically
+ @param[out] JedecId The Pointer to caller-allocated buffer
+ containing JEDEC ID received.
+ It is the caller's responsibility to make
+ sure Buffer is large enough for the total
+ number of bytes read.
+
+ @retval EFI_SUCCESS Command succeed.
+ @retval EFI_INVALID_PARAMETER The parameters specified are not valid.
+ @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *PCH_SPI_FLASH_READ_JEDEC_ID) (
+ IN PCH_SPI_PROTOCOL *This,
+ IN UINT8 ComponentNumber,
+ IN UINT32 ByteCount,
+ OUT UINT8 *JedecId
+ );
+
+/**
+ Write the status register in the flash part.
+
+ @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
+ @param[in] ByteCount Number of bytes in Status data portion of the
+ SPI cycle, the data size is 1 typically
+ @param[in] StatusValue The Pointer to caller-allocated buffer
+ containing the value of Status register writing
+
+ @retval EFI_SUCCESS Command succeed.
+ @retval EFI_INVALID_PARAMETER The parameters specified are not valid.
+ @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *PCH_SPI_FLASH_WRITE_STATUS) (
+ IN PCH_SPI_PROTOCOL *This,
+ IN UINT32 ByteCount,
+ IN UINT8 *StatusValue
+ );
+
+/**
+ Read status register in the flash part.
+
+ @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
+ @param[in] ByteCount Number of bytes in Status data portion of the
+ SPI cycle, the data size is 1 typically
+ @param[out] StatusValue The Pointer to caller-allocated buffer
+ containing the value of Status register received.
+
+ @retval EFI_SUCCESS Command succeed.
+ @retval EFI_INVALID_PARAMETER The parameters specified are not valid.
+ @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *PCH_SPI_FLASH_READ_STATUS) (
+ IN PCH_SPI_PROTOCOL *This,
+ IN UINT32 ByteCount,
+ OUT UINT8 *StatusValue
+ );
+
+/**
+ Get the SPI region base and size, based on the enum type
+
+ @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
+ @param[in] FlashRegionType The Flash Region type for for the base address
+ which is listed in the Descriptor.
+ @param[out] BaseAddress The Flash Linear Address for the Region 'n'
+ Base
+ @param[out] RegionSize The size for the Region 'n'
+
+ @retval EFI_SUCCESS Read success
+ @retval EFI_INVALID_PARAMETER Invalid region type given
+ @retval EFI_DEVICE_ERROR The region is not used
+**/
+typedef
+EFI_STATUS
+(EFIAPI *PCH_SPI_GET_REGION_ADDRESS) (
+ IN PCH_SPI_PROTOCOL *This,
+ IN FLASH_REGION_TYPE FlashRegionType,
+ OUT UINT32 *BaseAddress,
+ OUT UINT32 *RegionSize
+ );
+
+/**
+ Read PCH Soft Strap Values
+
+ @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
+ @param[in] SoftStrapAddr PCH Soft Strap address offset from FPSBA.
+ @param[in] ByteCount Number of bytes in SoftStrap data portion of
+ the SPI cycle
+ @param[out] SoftStrapValue The Pointer to caller-allocated buffer
+ containing PCH Soft Strap Value.
+ If the value of ByteCount is 0, the data type
+ of SoftStrapValue should be UINT16 and
+ SoftStrapValue will be PCH Soft Strap Length.
+ It is the caller's responsibility to make sure
+ Buffer is large enough for the total number of
+ bytes read.
+
+ @retval EFI_SUCCESS Command succeed.
+ @retval EFI_INVALID_PARAMETER The parameters specified are not valid.
+ @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *PCH_SPI_READ_PCH_SOFTSTRAP) (
+ IN PCH_SPI_PROTOCOL *This,
+ IN UINT32 SoftStrapAddr,
+ IN UINT32 ByteCount,
+ OUT VOID *SoftStrapValue
+ );
+
+/**
+ Read CPU Soft Strap Values
+
+ @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
+ @param[in] SoftStrapAddr CPU Soft Strap address offset from FCPUSBA.
+ @param[in] ByteCount Number of bytes in SoftStrap data portion of
+ the SPI cycle.
+ @param[out] SoftStrapValue The Pointer to caller-allocated buffer
+ containing CPU Soft Strap Value.
+ If the value of ByteCount is 0, the data type
+ of SoftStrapValue should be UINT16 and
+ SoftStrapValue will be PCH Soft Strap Length
+ It is the caller's responsibility to make sure
+ Buffer is large enough for the total number
+ of bytes read.
+
+ @retval EFI_SUCCESS Command succeed.
+ @retval EFI_INVALID_PARAMETER The parameters specified are not valid.
+ @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *PCH_SPI_READ_CPU_SOFTSTRAP) (
+ IN PCH_SPI_PROTOCOL *This,
+ IN UINT32 SoftStrapAddr,
+ IN UINT32 ByteCount,
+ OUT VOID *SoftStrapValue
+ );
+
+/**
+ These protocols/PPI allows a platform module to perform SPI operations
+ through the Intel PCH SPI Host Controller Interface.
+**/
+struct _PCH_SPI_PROTOCOL {
+ /**
+ This member specifies the revision of this structure. This field is
+ used to indicate backwards compatible changes to the protocol.
+ **/
+ UINT8 Revision;
+ PCH_SPI_FLASH_READ FlashRead; ///< Read data from the flash part.
+ PCH_SPI_FLASH_WRITE FlashWrite; ///< Write data to the flash part. Remark: Erase may be needed before write to the flash part.
+ PCH_SPI_FLASH_ERASE FlashErase; ///< Erase some area on the flash part.
+ PCH_SPI_FLASH_READ_SFDP FlashReadSfdp; ///< Read SFDP data from the flash part.
+ PCH_SPI_FLASH_READ_JEDEC_ID FlashReadJedecId; ///< Read Jedec Id from the flash part.
+ PCH_SPI_FLASH_WRITE_STATUS FlashWriteStatus; ///< Write the status register in the flash part.
+ PCH_SPI_FLASH_READ_STATUS FlashReadStatus; ///< Read status register in the flash part.
+ PCH_SPI_GET_REGION_ADDRESS GetRegionAddress; ///< Get the SPI region base and size
+ PCH_SPI_READ_PCH_SOFTSTRAP ReadPchSoftStrap; ///< Read PCH Soft Strap Values
+ PCH_SPI_READ_CPU_SOFTSTRAP ReadCpuSoftStrap; ///< Read CPU Soft Strap Values
+};
+
+/**
+ PCH SPI PPI/PROTOCOL revision number
+
+ Revision 1: Initial version
+**/
+#define PCH_SPI_SERVICES_REVISION 1
+
+#endif
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Protocol/Wdt.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Protocol/Wdt.h
new file mode 100644
index 0000000000..a68085fa54
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Protocol/Wdt.h
@@ -0,0 +1,111 @@
+/** @file
+ Watchdog Timer protocol
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _DXE_WDT_H_
+#define _DXE_WDT_H_
+
+//
+// Extern the GUID for protocol users.
+//
+extern EFI_GUID gWdtProtocolGuid;
+//
+// Forward reference for ANSI C compatibility
+//
+typedef struct _WDT_PROTOCOL WDT_PROTOCOL;
+
+/**
+ Reloads WDT with new timeout value and starts it. Also sets Unexpected Reset bit, which
+ causes the next reset to be treated as watchdog expiration - unless AllowKnownReset()
+ function was called too.
+
+ @param[in] TimeoutValue Time in seconds before WDT times out. Supported range = 1 - 1024.
+
+ @retval EFI_SUCCESS if everything's OK
+ @retval EFI_INVALID_PARAMETER if TimeoutValue parameter is wrong
+**/
+typedef
+EFI_STATUS
+(EFIAPI *WDT_RELOAD_AND_START) (
+ UINT32 TimeoutValue
+ );
+
+/**
+ Returns WDT failure status.
+
+ @retval V_PCH_OC_WDT_CTL_STATUS_FAILURE If there was WDT expiration or unexpected reset
+ @retval V_PCH_OC_WDT_CTL_STATUS_OK Otherwise
+**/
+typedef
+UINT8
+(EFIAPI *WDT_CHECK_STATUS) (
+ VOID
+ );
+
+/**
+ Returns information if WDT coverage for the duration of BIOS execution
+ was requested by an OS application.
+
+ @retval TRUE if WDT was requested
+ @retval FALSE if WDT was not requested
+**/
+typedef
+UINT8
+(EFIAPI *IS_WDT_REQUIRED) (
+ VOID
+ );
+
+/**
+ Returns WDT enabled/disabled status.
+
+ @retval TRUE if WDT is enabled
+ @retval FALSE if WDT is disabled
+**/
+typedef
+UINT8
+(EFIAPI *IS_WDT_ENABLED) (
+ VOID
+ );
+
+/**
+ Disables WDT timer.
+**/
+typedef
+VOID
+(EFIAPI *WDT_DISABLE) (
+ VOID
+ );
+
+/**
+ Normally, each reboot performed while watchdog runs is considered a failure.
+ This function allows platform to perform expected reboots with WDT running,
+ without being interpreted as failures.
+ In DXE phase, it is enough to call this function any time before reset.
+ In PEI phase, between calling this function and performing reset, ReloadAndStart()
+ must not be called.
+**/
+typedef
+VOID
+(EFIAPI *WDT_ALLOW_KNOWN_RESET) (
+ VOID
+ );
+
+/**
+ These protocols and PPI allow a platform module to perform watch dog timer operations
+ through the Intel PCH LPC Host Controller Interface. The WDT protocol and WDT PPI
+ implement the Intel (R) Watch Dog timer for DXE, and PEI environments, respectively.
+ WDT_PROTOCOL referenced hereafter represents both WDT_PROTOCOL and WDT_PPI, as they
+ share the identical data structure.
+**/
+struct _WDT_PROTOCOL {
+ WDT_RELOAD_AND_START ReloadAndStart; ///< Reloads WDT with new timeout value and starts it.
+ WDT_CHECK_STATUS CheckStatus; ///< Returns WDT failure status.
+ WDT_DISABLE Disable; ///< Disables WDT timer.
+ WDT_ALLOW_KNOWN_RESET AllowKnownReset; ///< Perform expected reboots with WDT running, without being interpreted as failures.
+ IS_WDT_REQUIRED IsWdtRequired; ///< Returns information if WDT coverage for the duration of BIOS execution was requested by an OS application.
+ IS_WDT_ENABLED IsWdtEnabled; ///< Returns WDT enabled/disabled status.
+};
+
+#endif
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/FlashRegs.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/FlashRegs.h
new file mode 100644
index 0000000000..860f823655
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/FlashRegs.h
@@ -0,0 +1,73 @@
+/** @file
+ Register names for Flash registers
+
+ Conventions:
+
+ - Register definition format:
+ Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_RegisterName
+ - Prefix:
+ Definitions beginning with "R_" are registers
+ Definitions beginning with "B_" are bits within registers
+ Definitions beginning with "V_" are meaningful values within the bits
+ Definitions beginning with "S_" are register size
+ Definitions beginning with "N_" are the bit position
+ - [GenerationName]:
+ Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc.).
+ Register name without GenerationName applies to all generations.
+ - [ComponentName]:
+ This field indicates the component name that the register belongs to (e.g. PCH, SA etc.)
+ Register name without ComponentName applies to all components.
+ Register that is specific to -H denoted by "_PCH_H_" in component name.
+ Register that is specific to -LP denoted by "_PCH_LP_" in component name.
+ - SubsystemName:
+ This field indicates the subsystem name of the component that the register belongs to
+ (e.g. PCIE, USB, SATA, GPIO, PMC etc.).
+ - RegisterSpace:
+ MEM - MMIO space register of subsystem.
+ IO - IO space register of subsystem.
+ PCR - Private configuration register of subsystem.
+ CFG - PCI configuration space register of subsystem.
+ - RegisterName:
+ Full register name.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _FLASH_REGS_H_
+#define _FLASH_REGS_H_
+
+
+//
+// Flash Descriptor Base Address Region (FDBAR) from Flash Region 0
+//
+#define R_FLASH_FDBAR_FLASH_MAP0 0x04
+#define B_FLASH_FDBAR_NC 0x00000300 ///< Number Of Components
+#define N_FLASH_FDBAR_NC 8 ///< Number Of Components
+#define R_FLASH_FDBAR_FLASH_MAP1 0x08
+#define B_FLASH_FDBAR_FPSBA 0x00FF0000 ///< PCH Strap Base Address, [23:16] represents [11:4]
+#define N_FLASH_FDBAR_FPSBA 16 ///< PCH Strap base Address bit position
+#define N_FLASH_FDBAR_FPSBA_REPR 4 ///< PCH Strap base Address bit represents position
+#define B_FLASH_FDBAR_PCHSL 0xFF000000 ///< PCH Strap Length, [31:24] represents number of Dwords
+#define N_FLASH_FDBAR_PCHSL 24 ///< PCH Strap Length bit position
+#define R_FLASH_FDBAR_FLASH_MAP2 0x0C
+#define B_FLASH_FDBAR_FCPUSBA 0x00000FFC ///< CPU Strap Base Address [11:2]
+#define N_FLASH_FDBAR_FCPUSBA 2 ///< CPU Strap Base Address bit position
+#define B_FLASH_FDBAR_CPUSL 0x00FF0000 ///< CPU Strap Length, [23:16] represents number of Dwords
+#define N_FLASH_FDBAR_CPUSL 16 ///< CPU Strap Length bit position
+
+//
+// Flash Component Base Address (FCBA) from Flash Region 0
+//
+#define R_FLASH_FCBA_FLCOMP 0x00 ///< Flash Components Register
+#define B_FLASH_FLCOMP_COMP1_MASK 0xF0 ///< Flash Component 1 Size MASK
+#define N_FLASH_FLCOMP_COMP1 4 ///< Flash Component 1 Size bit position
+#define B_FLASH_FLCOMP_COMP0_MASK 0x0F ///< Flash Component 0 Size MASK
+#define V_FLASH_FLCOMP_COMP_512KB 0x80000
+//
+// Descriptor Upper Map Section from Flash Region 0
+//
+#define R_FLASH_UMAP1 0xEFC ///< Flash Upper Map 1
+#define B_FLASH_UMAP1_MDTBA 0xFF000000 ///< MIP Descriptor Table Base Address
+#define N_FLASH_UMAP1_MDTBA 24 ///< MDTBA bits position
+#define N_FLASH_UMAP1_MDTBA_REPR 4 ///< MDTBA address representation position
+#endif
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/GpioRegs.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/GpioRegs.h
new file mode 100644
index 0000000000..c89dccb7bd
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/GpioRegs.h
@@ -0,0 +1,103 @@
+/** @file
+ Register names for PCH GPIO
+
+Conventions:
+
+ - Register definition format:
+ Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_RegisterName
+ - Prefix:
+ Definitions beginning with "R_" are registers
+ Definitions beginning with "B_" are bits within registers
+ Definitions beginning with "V_" are meaningful values within the bits
+ Definitions beginning with "S_" are register size
+ Definitions beginning with "N_" are the bit position
+ - [GenerationName]:
+ Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc.).
+ Register name without GenerationName applies to all generations.
+ - [ComponentName]:
+ This field indicates the component name that the register belongs to (e.g. PCH, SA etc.)
+ Register name without ComponentName applies to all components.
+ Register that is specific to -H denoted by "_PCH_H_" in component name.
+ Register that is specific to -LP denoted by "_PCH_LP_" in component name.
+ - SubsystemName:
+ This field indicates the subsystem name of the component that the register belongs to
+ (e.g. PCIE, USB, SATA, GPIO, PMC etc.).
+ - RegisterSpace:
+ MEM - MMIO space register of subsystem.
+ IO - IO space register of subsystem.
+ PCR - Private configuration register of subsystem.
+ CFG - PCI configuration space register of subsystem.
+ - RegisterName:
+ Full register name.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _GPIO_REGS_H_
+#define _GPIO_REGS_H_
+
+//
+// PADCFG register is split into multiple DW registers
+// S_GPIO_PCR_PADCFG refers to number of bytes used by all those registers for one pad
+//
+#define S_GPIO_PCR_PADCFG 0x10
+
+//
+// Pad Configuration Register DW0
+//
+
+
+//RX Raw Override to 1
+#define B_GPIO_PCR_RX_RAW1 BIT28
+#define N_GPIO_PCR_RX_RAW1 28
+
+//RX Level/Edge Configuration
+#define B_GPIO_PCR_RX_LVL_EDG (BIT26 | BIT25)
+#define N_GPIO_PCR_RX_LVL_EDG 25
+
+//RX Invert
+#define B_GPIO_PCR_RXINV BIT23
+#define N_GPIO_PCR_RXINV 23
+
+//GPIO Input Route IOxAPIC
+#define B_GPIO_PCR_RX_APIC_ROUTE BIT20
+
+//GPIO Input Route SCI
+#define B_GPIO_PCR_RX_SCI_ROUTE BIT19
+
+//GPIO Input Route SMI
+#define B_GPIO_PCR_RX_SMI_ROUTE BIT18
+
+//GPIO Input Route NMI
+#define B_GPIO_PCR_RX_NMI_ROUTE BIT17
+#define N_GPIO_PCR_RX_NMI_ROUTE 17
+
+//GPIO Pad Mode
+#define B_GPIO_PCR_PAD_MODE (BIT12 | BIT11 | BIT10)
+#define N_GPIO_PCR_PAD_MODE 10
+
+//GPIO RX Disable
+#define B_GPIO_PCR_RXDIS BIT9
+
+//GPIO TX Disable
+#define B_GPIO_PCR_TXDIS BIT8
+#define N_GPIO_PCR_TXDIS 8
+
+//GPIO TX State
+#define B_GPIO_PCR_TX_STATE BIT0
+#define N_GPIO_PCR_TX_STATE 0
+
+//Termination
+#define B_GPIO_PCR_TERM (BIT13 | BIT12 | BIT11 | BIT10)
+#define N_GPIO_PCR_TERM 10
+
+
+///
+/// GPIO SMI data used for EFI_SMM_GPI_DISPATCH2_PROTOCOL
+/// Below defines are to be used internally by PCH SMI dispatcher only
+///
+#define PCH_GPIO_NUM_SUPPORTED_GPIS 512
+#define S_GPIO_PCR_GP_SMI_STS 4
+
+#endif // _GPIO_REGS_H_
+
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/GpioRegsVer2.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/GpioRegsVer2.h
new file mode 100644
index 0000000000..7789236b5e
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/GpioRegsVer2.h
@@ -0,0 +1,211 @@
+/** @file
+ Register names for VER2 GPIO
+
+Conventions:
+
+ - Register definition format:
+ Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_RegisterName
+ - Prefix:
+ Definitions beginning with "R_" are registers
+ Definitions beginning with "B_" are bits within registers
+ Definitions beginning with "V_" are meaningful values within the bits
+ Definitions beginning with "S_" are register size
+ Definitions beginning with "N_" are the bit position
+ - [GenerationName]:
+ Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc.).
+ Register name without GenerationName applies to all generations.
+ - [ComponentName]:
+ This field indicates the component name that the register belongs to (e.g. PCH, SA etc.)
+ Register name without ComponentName applies to all components.
+ Register that is specific to -H denoted by "_PCH_H_" in component name.
+ Register that is specific to -LP denoted by "_PCH_LP_" in component name.
+ - SubsystemName:
+ This field indicates the subsystem name of the component that the register belongs to
+ (e.g. PCIE, USB, SATA, GPIO, PMC etc.).
+ - RegisterSpace:
+ MEM - MMIO space register of subsystem.
+ IO - IO space register of subsystem.
+ PCR - Private configuration register of subsystem.
+ CFG - PCI configuration space register of subsystem.
+ - RegisterName:
+ Full register name.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _GPIO_REGS_VER2_H_
+#define _GPIO_REGS_VER2_H_
+
+#define GPIO_VER2_PCH_LP_GPIO_GPP_B_PAD_MAX 26
+#define GPIO_VER2_PCH_LP_GPIO_GPP_A_PAD_MAX 25
+#define GPIO_VER2_PCH_LP_GPIO_GPP_R_PAD_MAX 8
+#define GPIO_VER2_PCH_LP_GPIO_GPD_PAD_MAX 17
+#define GPIO_VER2_PCH_LP_GPIO_GPP_S_PAD_MAX 8
+#define GPIO_VER2_PCH_LP_GPIO_GPP_H_PAD_MAX 24
+#define GPIO_VER2_PCH_LP_GPIO_GPP_D_PAD_MAX 21
+#define GPIO_VER2_PCH_LP_GPIO_GPP_F_PAD_MAX 25
+#define GPIO_VER2_PCH_LP_GPIO_GPP_C_PAD_MAX 24
+#define GPIO_VER2_PCH_LP_GPIO_GPP_E_PAD_MAX 25
+
+//
+// GPIO Community 0 Private Configuration Registers
+//
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_PAD_OWN 0x20
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_A_PAD_OWN 0x38
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_PADCFGLOCK 0x80
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_PADCFGLOCKTX 0x84
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_A_PADCFGLOCK 0x90
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_A_PADCFGLOCKTX 0x94
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_HOSTSW_OWN 0xB0
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_A_HOSTSW_OWN 0xB8
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_GPI_IS 0x0100
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_A_GPI_IS 0x0108
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_GPI_IE 0x0120
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_A_GPI_IE 0x0128
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_GPI_GPE_STS 0x0140
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_A_GPI_GPE_STS 0x0148
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_GPI_GPE_EN 0x0160
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_A_GPI_GPE_EN 0x0168
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_SMI_STS 0x0180
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_SMI_EN 0x01A0
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_NMI_STS 0x01C0
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_NMI_EN 0x01E0
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_PADCFG_OFFSET 0x700
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_A_PADCFG_OFFSET 0x9A0
+
+//
+// GPIO Community 1 Private Configuration Registers
+//
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_S_PAD_OWN 0x20
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_H_PAD_OWN 0x24
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_PAD_OWN 0x30
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_S_PADCFGLOCK 0x80
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_S_PADCFGLOCKTX 0x84
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_H_PADCFGLOCK 0x88
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_H_PADCFGLOCKTX 0x8C
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_PADCFGLOCK 0x90
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_PADCFGLOCKTX 0x94
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_S_HOSTSW_OWN 0xB0
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_H_HOSTSW_OWN 0xB4
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_HOSTSW_OWN 0xB8
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_S_GPI_IS 0x0100
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_H_GPI_IS 0x0104
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_GPI_IS 0x0108
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_S_GPI_IE 0x0120
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_H_GPI_IE 0x0124
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_GPI_IE 0x0128
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_S_GPI_GPE_STS 0x0140
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_H_GPI_GPE_STS 0x0144
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_GPI_GPE_STS 0x0148
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_S_GPI_GPE_EN 0x0160
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_H_GPI_GPE_EN 0x0164
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_GPI_GPE_EN 0x0168
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_SMI_STS 0x0188
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_SMI_EN 0x01A8
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_NMI_STS 0x01C8
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_NMI_EN 0x01E8
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_S_PADCFG_OFFSET 0x700
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_H_PADCFG_OFFSET 0x780
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_PADCFG_OFFSET 0x900
+//
+// GPIO Community 2 Private Configuration Registers
+//
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPD_PAD_OWN 0x20
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPD_PADCFGLOCK 0x80
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPD_PADCFGLOCKTX 0x84
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPD_HOSTSW_OWN 0xB0
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPD_GPI_IS 0x0100
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPD_GPI_IE 0x0120
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPD_GPI_GPE_STS 0x0140
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPD_GPI_GPE_EN 0x0160
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPD_PADCFG_OFFSET 0x700
+
+//
+// GPIO Community 4 Private Configuration Registers
+//
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_PAD_OWN 0x20
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_F_PAD_OWN 0x2C
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_PAD_OWN 0x40
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_PADCFGLOCK 0x80
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_PADCFGLOCKTX 0x84
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_F_PADCFGLOCK 0x88
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_F_PADCFGLOCKTX 0x8C
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_PADCFGLOCK 0x98
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_PADCFGLOCKTX 0x9C
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_HOSTSW_OWN 0xB0
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_F_HOSTSW_OWN 0xB4
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_HOSTSW_OWN 0xBC
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_GPI_IS 0x0100
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_F_GPI_IS 0x0104
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_GPI_IS 0x010C
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_GPI_IE 0x0120
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_F_GPI_IE 0x0124
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_GPI_IE 0x012C
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_GPI_GPE_STS 0x0140
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_F_GPI_GPE_STS 0x0144
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_GPI_GPE_STS 0x014C
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_GPI_GPE_EN 0x0160
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_F_GPI_GPE_EN 0x0164
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_GPI_GPE_EN 0x016C
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_SMI_STS 0x0180
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_SMI_STS 0x018C
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_SMI_EN 0x01A0
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_SMI_EN 0x01AC
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_NMI_STS 0x01C0
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_NMI_STS 0x01CC
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_NMI_EN 0x01E0
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_NMI_EN 0x01EC
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_PADCFG_OFFSET 0x700
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_F_PADCFG_OFFSET 0x880
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_PADCFG_OFFSET 0xA70
+
+//
+// GPIO Community 5 Private Configuration Registers
+//
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_R_PAD_OWN 0x20
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_R_PADCFGLOCK 0x80
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_R_PADCFGLOCKTX 0x84
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_R_HOSTSW_OWN 0xB0
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_R_GPI_IS 0x0100
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_R_GPI_IE 0x0120
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_R_GPI_GPE_STS 0x0140
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_R_GPI_GPE_EN 0x0160
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_R_PADCFG_OFFSET 0x700
+
+#endif // _GPIO_REGS_VER2_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/PchDmi14Regs.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/PchDmi14Regs.h
new file mode 100644
index 0000000000..f30bf62614
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/PchDmi14Regs.h
@@ -0,0 +1,49 @@
+/** @file
+ Register names for PCH DMI SIP14
+
+Conventions:
+
+ - Register definition format:
+ Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_RegisterName
+ - Prefix:
+ Definitions beginning with "R_" are registers
+ Definitions beginning with "B_" are bits within registers
+ Definitions beginning with "V_" are meaningful values within the bits
+ Definitions beginning with "S_" are register size
+ Definitions beginning with "N_" are the bit position
+ - [GenerationName]:
+ Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc.).
+ Register name without GenerationName applies to all generations.
+ - [ComponentName]:
+ This field indicates the component name that the register belongs to (e.g. PCH, SA etc.)
+ Register name without ComponentName applies to all components.
+ Register that is specific to -H denoted by "_PCH_H_" in component name.
+ Register that is specific to -LP denoted by "_PCH_LP_" in component name.
+ - SubsystemName:
+ This field indicates the subsystem name of the component that the register belongs to
+ (e.g. PCIE, USB, SATA, GPIO, PMC etc.).
+ - RegisterSpace:
+ MEM - MMIO space register of subsystem.
+ IO - IO space register of subsystem.
+ PCR - Private configuration register of subsystem.
+ CFG - PCI configuration space register of subsystem.
+ - RegisterName:
+ Full register name.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _PCH_DMI14_REGS_H_
+#define _PCH_DMI14_REGS_H_
+
+//
+// DMI Chipset Configuration Registers (PID:DMI)
+//
+
+//
+// DMI Control
+//
+#define R_PCH_DMI14_PCR_DMIC 0x2234 ///< DMI Control
+#define B_PCH_DMI14_PCR_DMIC_SRL BIT31 ///< Secured register lock
+
+#endif
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/PchDmiRegs.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/PchDmiRegs.h
new file mode 100644
index 0000000000..649e8dd17b
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/PchDmiRegs.h
@@ -0,0 +1,51 @@
+/** @file
+ Register names for PCH DMI and OP-DMI
+
+Conventions:
+
+ - Register definition format:
+ Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_RegisterName
+ - Prefix:
+ Definitions beginning with "R_" are registers
+ Definitions beginning with "B_" are bits within registers
+ Definitions beginning with "V_" are meaningful values within the bits
+ Definitions beginning with "S_" are register size
+ Definitions beginning with "N_" are the bit position
+ - [GenerationName]:
+ Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc.).
+ Register name without GenerationName applies to all generations.
+ - [ComponentName]:
+ This field indicates the component name that the register belongs to (e.g. PCH, SA etc.)
+ Register name without ComponentName applies to all components.
+ Register that is specific to -H denoted by "_PCH_H_" in component name.
+ Register that is specific to -LP denoted by "_PCH_LP_" in component name.
+ - SubsystemName:
+ This field indicates the subsystem name of the component that the register belongs to
+ (e.g. PCIE, USB, SATA, GPIO, PMC etc.).
+ - RegisterSpace:
+ MEM - MMIO space register of subsystem.
+ IO - IO space register of subsystem.
+ PCR - Private configuration register of subsystem.
+ CFG - PCI configuration space register of subsystem.
+ - RegisterName:
+ Full register name.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _PCH_DMI_REGS_H_
+#define _PCH_DMI_REGS_H_
+
+//
+// PCH DMI Chipset Configuration Registers (PID:DMI)
+//
+
+//
+// PCH DMI Source Decode PCRs (Common)
+//
+#define R_PCH_DMI_PCR_LPCIOD 0x2770 ///< LPC I/O Decode Ranges
+#define R_PCH_DMI_PCR_LPCIOE 0x2774 ///< LPC I/O Enables
+#define R_PCH_DMI_PCR_TCOBASE 0x2778 ///< TCO Base Address
+#define B_PCH_DMI_PCR_TCOBASE_TCOBA 0xFFE0 ///< TCO Base Address Mask
+
+#endif
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/PchPcieRpRegs.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/PchPcieRpRegs.h
new file mode 100644
index 0000000000..17c68cbaaa
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/PchPcieRpRegs.h
@@ -0,0 +1,45 @@
+/** @file
+ Register names for PCH PCI-E root port devices
+
+ Conventions:
+
+ - Register definition format:
+ Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_RegisterName
+ - Prefix:
+ Definitions beginning with "R_" are registers
+ Definitions beginning with "B_" are bits within registers
+ Definitions beginning with "V_" are meaningful values within the bits
+ Definitions beginning with "S_" are register size
+ Definitions beginning with "N_" are the bit position
+ - [GenerationName]:
+ Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc.).
+ Register name without GenerationName applies to all generations.
+ - [ComponentName]:
+ This field indicates the component name that the register belongs to (e.g. PCH, SA etc.)
+ Register name without ComponentName applies to all components.
+ Register that is specific to -H denoted by "_PCH_H_" in component name.
+ Register that is specific to -LP denoted by "_PCH_LP_" in component name.
+ - SubsystemName:
+ This field indicates the subsystem name of the component that the register belongs to
+ (e.g. PCIE, USB, SATA, GPIO, PMC etc.).
+ - RegisterSpace:
+ MEM - MMIO space register of subsystem.
+ IO - IO space register of subsystem.
+ PCR - Private configuration register of subsystem.
+ CFG - PCI configuration space register of subsystem.
+ - RegisterName:
+ Full register name.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _PCH_REGS_PCIE_H_
+#define _PCH_REGS_PCIE_H_
+
+//
+// PCIE PCRs (PID:SPA SPB SPC SPD SPE SPF)
+//
+#define R_SPX_PCR_PCD 0 ///< Port configuration and disable
+#define B_SPX_PCR_PCD_RP1FN (BIT2 | BIT1 | BIT0) ///< Port 1 Function Number
+#define S_SPX_PCR_PCD_RP_FIELD 4 ///< 4 bits for each RP FN
+#endif
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/PchRegsLpc.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/PchRegsLpc.h
new file mode 100644
index 0000000000..326b266352
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/PchRegsLpc.h
@@ -0,0 +1,77 @@
+/** @file
+ Register names for PCH LPC/eSPI device
+
+Conventions:
+
+ - Register definition format:
+ Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_RegisterName
+ - Prefix:
+ Definitions beginning with "R_" are registers
+ Definitions beginning with "B_" are bits within registers
+ Definitions beginning with "V_" are meaningful values within the bits
+ Definitions beginning with "S_" are register size
+ Definitions beginning with "N_" are the bit position
+ - [GenerationName]:
+ Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc.).
+ Register name without GenerationName applies to all generations.
+ - [ComponentName]:
+ This field indicates the component name that the register belongs to (e.g. PCH, SA etc.)
+ Register name without ComponentName applies to all components.
+ Register that is specific to -H denoted by "_PCH_H_" in component name.
+ Register that is specific to -LP denoted by "_PCH_LP_" in component name.
+ - SubsystemName:
+ This field indicates the subsystem name of the component that the register belongs to
+ (e.g. PCIE, USB, SATA, GPIO, PMC etc.).
+ - RegisterSpace:
+ MEM - MMIO space register of subsystem.
+ IO - IO space register of subsystem.
+ PCR - Private configuration register of subsystem.
+ CFG - PCI configuration space register of subsystem.
+ - RegisterName:
+ Full register name.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _PCH_REGS_LPC_H_
+#define _PCH_REGS_LPC_H_
+
+//
+// PCI to LPC Bridge Registers
+//
+
+#define R_LPC_CFG_IOD 0x80
+#define R_LPC_CFG_IOE 0x82
+#define R_ESPI_CFG_CS1IORE 0xA0
+
+#define R_LPC_CFG_ULKMC 0x94
+#define B_LPC_CFG_ULKMC_A20PASSEN BIT5
+#define B_LPC_CFG_ULKMC_64WEN BIT3
+#define B_LPC_CFG_ULKMC_64REN BIT2
+#define B_LPC_CFG_ULKMC_60WEN BIT1
+#define B_LPC_CFG_ULKMC_60REN BIT0
+
+//
+// APM Registers
+//
+#define R_PCH_IO_APM_CNT 0xB2
+#define R_PCH_IO_APM_STS 0xB3
+#define R_LPC_CFG_BC 0xDC ///< Bios Control
+#define S_LPC_CFG_BC 1
+#define N_LPC_CFG_BC_LE 1
+
+//
+// Reset Generator I/O Port
+//
+#define R_PCH_IO_RST_CNT 0xCF9
+#define V_PCH_IO_RST_CNT_FULLRESET 0x0E
+#define V_PCH_IO_RST_CNT_HARDRESET 0x06
+//
+// eSPI PCR Registers
+//
+#define R_ESPI_PCR_CFG_VAL 0xC00C ///< ESPI Enabled Strap
+#define B_ESPI_PCR_CFG_VAL_ESPI_EN BIT0 ///< ESPI Enabled Strap bit position
+#define R_ESPI_PCR_SOFTSTRAPS 0xC210 ///< eSPI Sofstraps Register 0
+#define B_ESPI_PCR_SOFTSTRAPS_CS1_EN BIT12 ///< CS1# Enable
+
+#endif
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/PmcRegs.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/PmcRegs.h
new file mode 100644
index 0000000000..f7153b931c
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/PmcRegs.h
@@ -0,0 +1,134 @@
+/** @file
+ Register names for PCH PMC device
+
+ Conventions:
+
+ - Register definition format:
+ Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_RegisterName
+ - Prefix:
+ Definitions beginning with "R_" are registers
+ Definitions beginning with "B_" are bits within registers
+ Definitions beginning with "V_" are meaningful values within the bits
+ Definitions beginning with "S_" are register size
+ Definitions beginning with "N_" are the bit position
+ - [GenerationName]:
+ Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc.).
+ Register name without GenerationName applies to all generations.
+ - [ComponentName]:
+ This field indicates the component name that the register belongs to (e.g. PCH, SA etc.)
+ Register name without ComponentName applies to all components.
+ Register that is specific to -H denoted by "_PCH_H_" in component name.
+ Register that is specific to -LP denoted by "_PCH_LP_" in component name.
+ - SubsystemName:
+ This field indicates the subsystem name of the component that the register belongs to
+ (e.g. PCIE, USB, SATA, GPIO, PMC etc.).
+ - RegisterSpace:
+ MEM - MMIO space register of subsystem.
+ IO - IO space register of subsystem.
+ PCR - Private configuration register of subsystem.
+ CFG - PCI configuration space register of subsystem.
+ - RegisterName:
+ Full register name.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _PCH_REGS_PMC_H_
+#define _PCH_REGS_PMC_H_
+
+//
+// ACPI and legacy I/O register offsets from ACPIBASE
+//
+#define R_ACPI_IO_PM1_STS 0x00
+#define S_ACPI_IO_PM1_STS 2
+#define B_ACPI_IO_PM1_STS_PRBTNOR BIT11
+#define B_ACPI_IO_PM1_STS_PWRBTN BIT8
+#define N_ACPI_IO_PM1_STS_RTC 10
+#define N_ACPI_IO_PM1_STS_PWRBTN 8
+#define N_ACPI_IO_PM1_STS_TMROF 0
+
+#define R_ACPI_IO_PM1_EN 0x02
+#define S_ACPI_IO_PM1_EN 2
+#define B_ACPI_IO_PM1_EN_PWRBTN BIT8
+#define N_ACPI_IO_PM1_EN_RTC 10
+#define N_ACPI_IO_PM1_EN_PWRBTN 8
+#define N_ACPI_IO_PM1_EN_TMROF 0
+
+#define R_ACPI_IO_PM1_CNT 0x04 ///< Power Management 1 Control
+#define B_ACPI_IO_PM1_CNT_SLP_EN BIT13 ///< Sleep Enable
+#define B_ACPI_IO_PM1_CNT_SLP_TYP (BIT12 | BIT11 | BIT10) ///< Sleep Type
+#define V_ACPI_IO_PM1_CNT_S0 0
+#define V_ACPI_IO_PM1_CNT_S1 BIT10
+#define V_ACPI_IO_PM1_CNT_S3 (BIT12 | BIT10)
+#define V_ACPI_IO_PM1_CNT_S4 (BIT12 | BIT11)
+#define V_ACPI_IO_PM1_CNT_S5 (BIT12 | BIT11 | BIT10)
+#define B_ACPI_IO_PM1_CNT_SCI_EN BIT0 ///< SCI Enable
+
+#define R_ACPI_IO_PM1_TMR 0x08 ///< Power Management 1 Timer
+#define B_ACPI_IO_PM1_TMR_TMR_VAL 0xFFFFFF ///< Timer Value
+#define V_ACPI_IO_PM1_TMR_MAX_VAL 0x1000000 ///< The timer is 24 bit overflow
+
+#define R_ACPI_IO_SMI_EN 0x30 ///< SMI Control and Enable
+#define S_ACPI_IO_SMI_EN 4
+#define B_ACPI_IO_SMI_EN_LEGACY_USB2 BIT17
+#define B_ACPI_IO_SMI_EN_TCO BIT13
+#define B_ACPI_IO_SMI_EN_SWSMI_TMR BIT6
+#define B_ACPI_IO_SMI_EN_APMC BIT5
+#define B_ACPI_IO_SMI_EN_LEGACY_USB BIT3
+#define B_ACPI_IO_SMI_EN_EOS BIT1 ///< End of SMI
+#define B_ACPI_IO_SMI_EN_GBL_SMI BIT0
+#define N_ACPI_IO_SMI_EN_LEGACY_USB3 31
+#define N_ACPI_IO_SMI_EN_PERIODIC 14
+#define N_ACPI_IO_SMI_EN_TCO 13
+#define N_ACPI_IO_SMI_EN_MCSMI 11
+#define N_ACPI_IO_SMI_EN_SWSMI_TMR 6
+#define N_ACPI_IO_SMI_EN_APMC 5
+#define N_ACPI_IO_SMI_EN_ON_SLP_EN 4
+#define N_ACPI_IO_SMI_EN_LEGACY_USB 3
+
+#define R_ACPI_IO_SMI_STS 0x34 ///< SMI Status Register
+#define S_ACPI_IO_SMI_STS 4
+#define B_ACPI_IO_SMI_STS_GPIO_UNLOCK BIT27
+#define B_ACPI_IO_SMI_STS_TCO BIT13
+#define B_ACPI_IO_SMI_STS_APM BIT5
+#define N_ACPI_IO_SMI_STS_LEGACY_USB3 31
+#define N_ACPI_IO_SMI_STS_SPI 26
+#define N_ACPI_IO_SMI_STS_SMBUS 16
+#define N_ACPI_IO_SMI_STS_SERIRQ 15
+#define N_ACPI_IO_SMI_STS_PERIODIC 14
+#define N_ACPI_IO_SMI_STS_TCO 13
+#define N_ACPI_IO_SMI_STS_MCSMI 11
+#define N_ACPI_IO_SMI_STS_GPIO_SMI 10
+#define N_ACPI_IO_SMI_STS_GPE0 9
+#define N_ACPI_IO_SMI_STS_PM1_STS_REG 8
+#define N_ACPI_IO_SMI_STS_SWSMI_TMR 6
+#define N_ACPI_IO_SMI_STS_APM 5
+#define N_ACPI_IO_SMI_STS_ON_SLP_EN 4
+#define N_ACPI_IO_SMI_STS_LEGACY_USB 3
+
+#define R_ACPI_IO_GPE0_STS_127_96 0x6C ///< General Purpose Event 0 Status [127:96]
+#define S_ACPI_IO_GPE0_STS_127_96 4
+#define B_ACPI_IO_GPE0_STS_127_96_WADT BIT18
+#define N_ACPI_IO_GPE0_STS_127_96_PME_B0 13
+#define N_ACPI_IO_GPE0_STS_127_96_PME 11
+#define R_ACPI_IO_GPE0_EN_127_96 0x7C ///< General Purpose Event 0 Enable [127:96]
+#define S_ACPI_IO_GPE0_EN_127_96 4
+#define B_ACPI_IO_GPE0_EN_127_96_WADT BIT18
+#define N_ACPI_IO_GPE0_EN_127_96_PME_B0 13
+#define N_ACPI_IO_GPE0_EN_127_96_PME 11
+
+//
+// PWRM Registers
+//
+#define R_PMC_PWRM_GEN_PMCON_A 0x1020 ///< General PM Configuration A
+#define B_PMC_PWRM_GEN_PMCON_A_SWSMI_RTSL 0xC0
+#define V_PMC_PWRM_GEN_PMCON_A_SWSMI_RTSL_64MS 0xC0
+#define V_PMC_PWRM_GEN_PMCON_A_SWSMI_RTSL_32MS 0x80
+#define V_PMC_PWRM_GEN_PMCON_A_SWSMI_RTSL_16MS 0x40
+#define V_PMC_PWRM_GEN_PMCON_A_SWSMI_RTSL_1_5MS 0x00
+#define B_PMC_PWRM_GEN_PMCON_A_PER_SMI_SEL (BIT2|BIT1) ///< Period SMI Select
+#define V_PMC_PWRM_GEN_PMCON_A_PER_SMI_64S 0x0000
+#define V_PMC_PWRM_GEN_PMCON_A_PER_SMI_32S 0x0002
+#define V_PMC_PWRM_GEN_PMCON_A_PER_SMI_16S 0x0004
+#define V_PMC_PWRM_GEN_PMCON_A_PER_SMI_8S 0x0006
+#endif
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/RtcRegs.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/RtcRegs.h
new file mode 100644
index 0000000000..8424ef5897
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/RtcRegs.h
@@ -0,0 +1,44 @@
+/** @file
+ Register names for RTC device
+
+Conventions:
+
+ - Register definition format:
+ Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_RegisterName
+ - Prefix:
+ Definitions beginning with "R_" are registers
+ Definitions beginning with "B_" are bits within registers
+ Definitions beginning with "V_" are meaningful values within the bits
+ Definitions beginning with "S_" are register size
+ Definitions beginning with "N_" are the bit position
+ - [GenerationName]:
+ Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc.).
+ Register name without GenerationName applies to all generations.
+ - [ComponentName]:
+ This field indicates the component name that the register belongs to (e.g. PCH, SA etc.)
+ Register name without ComponentName applies to all components.
+ Register that is specific to -H denoted by "_PCH_H_" in component name.
+ Register that is specific to -LP denoted by "_PCH_LP_" in component name.
+ - SubsystemName:
+ This field indicates the subsystem name of the component that the register belongs to
+ (e.g. PCIE, USB, SATA, GPIO, PMC etc.).
+ - RegisterSpace:
+ MEM - MMIO space register of subsystem.
+ IO - IO space register of subsystem.
+ PCR - Private configuration register of subsystem.
+ CFG - PCI configuration space register of subsystem.
+ - RegisterName:
+ Full register name.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _REGS_RTC_H_
+#define _REGS_RTC_H_
+
+#define R_RTC_IO_INDEX_ALT 0x74
+#define R_RTC_IO_TARGET_ALT 0x75
+#define R_RTC_IO_EXT_INDEX_ALT 0x76
+#define R_RTC_IO_REGD 0x0D
+
+#endif
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/TcoRegs.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/TcoRegs.h
new file mode 100644
index 0000000000..c3afcd5079
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/TcoRegs.h
@@ -0,0 +1,71 @@
+/** @file
+ Register names for PCH TCO device
+
+ Conventions:
+
+ - Register definition format:
+ Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_RegisterName
+ - Prefix:
+ Definitions beginning with "R_" are registers
+ Definitions beginning with "B_" are bits within registers
+ Definitions beginning with "V_" are meaningful values within the bits
+ Definitions beginning with "S_" are register size
+ Definitions beginning with "N_" are the bit position
+ - [GenerationName]:
+ Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc.).
+ Register name without GenerationName applies to all generations.
+ - [ComponentName]:
+ This field indicates the component name that the register belongs to (e.g. PCH, SA etc.)
+ Register name without ComponentName applies to all components.
+ Register that is specific to -H denoted by "_PCH_H_" in component name.
+ Register that is specific to -LP denoted by "_PCH_LP_" in component name.
+ - SubsystemName:
+ This field indicates the subsystem name of the component that the register belongs to
+ (e.g. PCIE, USB, SATA, GPIO, PMC etc.).
+ - RegisterSpace:
+ MEM - MMIO space register of subsystem.
+ IO - IO space register of subsystem.
+ PCR - Private configuration register of subsystem.
+ CFG - PCI configuration space register of subsystem.
+ - RegisterName:
+ Full register name.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _TCO_REGS_H_
+#define _TCO_REGS_H_
+
+//
+// TCO register I/O map
+//
+#define R_TCO_IO_TCO1_STS 0x04
+#define S_TCO_IO_TCO1_STS 2
+#define B_TCO_IO_TCO1_STS_DMISERR BIT12
+#define B_TCO_IO_TCO1_STS_DMISMI BIT10
+#define B_TCO_IO_TCO1_STS_DMISCI BIT9
+#define B_TCO_IO_TCO1_STS_BIOSWR BIT8
+#define B_TCO_IO_TCO1_STS_NEWCENTURY BIT7
+#define B_TCO_IO_TCO1_STS_TIMEOUT BIT3
+#define B_TCO_IO_TCO1_STS_TCO_INT BIT2
+#define B_TCO_IO_TCO1_STS_SW_TCO_SMI BIT1
+#define N_TCO_IO_TCO1_STS_DMISMI 10
+#define N_TCO_IO_TCO1_STS_BIOSWR 8
+#define N_TCO_IO_TCO1_STS_NEWCENTURY 7
+#define N_TCO_IO_TCO1_STS_TIMEOUT 3
+#define N_TCO_IO_TCO1_STS_SW_TCO_SMI 1
+#define N_TCO_IO_TCO1_STS_NMI2SMI 0
+
+#define R_TCO_IO_TCO2_STS 0x06
+#define S_TCO_IO_TCO2_STS 2
+#define N_TCO_IO_TCO2_STS_INTRD_DET 0
+
+#define R_TCO_IO_TCO1_CNT 0x08
+#define S_TCO_IO_TCO1_CNT 2
+#define N_TCO_IO_TCO1_CNT_NMI2SMI_EN 9
+
+#define R_TCO_IO_TCO2_CNT 0x0A
+#define S_TCO_IO_TCO2_CNT 2
+#define N_TCO_IO_TCO2_CNT_INTRD_SEL 2
+
+#endif
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/SerialIoDevices.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/SerialIoDevices.h
new file mode 100644
index 0000000000..1829fb90ff
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/SerialIoDevices.h
@@ -0,0 +1,226 @@
+/** @file
+ Serial IO policy
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _SERIAL_IO_DEVICES_H_
+#define _SERIAL_IO_DEVICES_H_
+
+#include <Protocol/SerialIo.h>
+#include <PchLimits.h>
+
+#pragma pack (push,1)
+
+/**
+ Available working modes for SerialIo SPI Host Controller
+
+ 0: SerialIoSpiDisabled;
+ - Device is placed in D3
+ - Gpio configuration is skipped
+ - PSF:
+ !important! If given device is Function 0 and other higher functions on given device
+ are enabled, PSF disabling is skipped. PSF default will remain and device PCI CFG Space will still be visible.
+ This is needed to allow PCI enumerator access functions above 0 in a multifunction device.
+ <b>1: SerialIoSpiPci;</b>
+ - Gpio pin configuration in native mode for each assigned pin
+ - Device will be enabled in PSF
+ - Only BAR0 will be enabled
+ 2: SerialIoSpiHidden;
+ - Gpio pin configuration in native mode for each assigned pin
+ - Device disabled in the PSF
+ - Both BARs are enabled, BAR1 becomes devices Pci Config Space
+ - BAR0 assigned from the global PCH reserved memory range, reported as motherboard resource by SIRC
+ @note
+ If this controller is located at function 0 and it's mode is set to hidden it will not be visible in the PCI space.
+**/
+typedef enum {
+ SerialIoSpiDisabled,
+ SerialIoSpiPci,
+ SerialIoSpiHidden
+} SERIAL_IO_SPI_MODE;
+
+/**
+ Used to set Inactive/Idle polarity of Spi Chip Select
+**/
+typedef enum {
+ SerialIoSpiCsActiveLow = 0,
+ SerialIoSpiCsActiveHigh = 1
+} SERIAL_IO_CS_POLARITY;
+
+/**
+ SPI signals pin muxing settings. If signal can be enable only on a single pin
+ then this parameter is ignored by RC. Refer to GPIO_*_MUXING_SERIALIO_SPIx_* in GpioPins*.h
+ for supported settings on a given platform
+**/
+typedef struct {
+ UINT32 Cs[PCH_MAX_SERIALIO_SPI_CHIP_SELECTS]; ///< CS Pin mux configuration. Refer to GPIO_*_MUXING_SERIALIO_SPIx_CS_*
+ UINT32 Clk; ///< CLK Pin mux configuration. Refer to GPIO_*_MUXING_SERIALIO_SPIx_CLK_*
+ UINT32 Miso; ///< MISO Pin mux configuration. Refer to GPIO_*_MUXING_SERIALIO_SPIx_MISO_*
+ UINT32 Mosi; ///< MOSI Pin mux configuration. Refer to GPIO_*_MUXING_SERIALIO_SPIx_MOSI_*
+} SPI_PIN_MUX;
+
+/**
+ The SERIAL_IO_SPI_CONFIG provides the configurations to set the Serial IO SPI controller
+**/
+typedef struct {
+ UINT8 Mode; ///< <b>SerialIoSpiPci </b> see SERIAL_IO_SPI_MODE
+ UINT8 DefaultCsOutput; ///< <b>0 = CS0</b> CS1, CS2, CS3. Default CS used by the SPI HC
+ UINT8 CsPolarity[PCH_MAX_SERIALIO_SPI_CHIP_SELECTS]; ///< Selects SPI ChipSelect signal polarity, 0 = low <b>1 = High</b>
+ UINT8 CsEnable[PCH_MAX_SERIALIO_SPI_CHIP_SELECTS]; ///< <b>0 = Enable</b> 1 = Disable. Based on this setting GPIO for given SPIx CSx will be configured in Native mode
+ UINT8 CsMode; ///< <b>0 = HW Control</b> 1 = SW Control. Sets Chip Select Control mode Hardware or Software.
+ UINT8 CsState; ///< <b>0 = CS is set to low</b> 1 = CS is set to high
+ SPI_PIN_MUX PinMux; ///< SPI Pinmux configuration
+} SERIAL_IO_SPI_CONFIG;
+
+/**
+ Available working modes for SerialIo UART Host Controller
+
+ 0: SerialIoUartDisabled;
+ - Device is placed in D3
+ - Gpio configuration is skipped
+ - PSF:
+ !important! If given device is Function 0 and other higher functions on given device
+ are enabled, PSF disabling is skipped. PSF default will remain and device PCI CFG Space will still be visible.
+ This is needed to allow PCI enumerator access functions above 0 in a multifunction device.
+ <b>1: SerialIoUartPci;</b>
+ - Designated for Serial IO UART OS driver usage
+ - Gpio pin configuration in native mode for each assigned pin
+ - Device will be enabled in PSF
+ - Only BAR0 will be enabled
+ 2: SerialIoUartHidden;
+ - Designated for BIOS and/or DBG2 OS kernel debug
+ - Gpio pin configuration in native mode for each assigned pin
+ - Device disabled in the PSF
+ - Both BARs are enabled, BAR1 becomes devices Pci Config Space
+ - BAR0 assigned from the global PCH reserved memory range, reported as motherboard resource by SIRC
+ @note
+ If this controller is located at function 0 and it's mode is set to hidden it will not be visible in the PCI space.
+ 3: SerialIoUartCom;
+ - Designated for 16550/PNP0501 compatible COM device
+ - Gpio pin configuration in native mode for each assigned pin
+ - Device disabled in the PSF
+ - Both BARs are enabled, BAR1 becomes devices Pci Config Space
+ - BAR0 assigned from the global PCH reserved memory range, reported as motherboard resource by SIRC
+ 4: SerialIoUartSkipInit;
+ - Gpio configuration is skipped
+ - PSF configuration is skipped
+ - BAR assignemnt is skipped
+ - D-satate setting is skipped
+
+**/
+typedef enum {
+ SerialIoUartDisabled,
+ SerialIoUartPci,
+ SerialIoUartHidden,
+ SerialIoUartCom,
+ SerialIoUartSkipInit
+} SERIAL_IO_UART_MODE;
+
+/**
+ UART Settings
+**/
+typedef struct {
+ UINT32 BaudRate; ///< <b> 115200 </b> Max 6000000 MdePkg.dec PcdUartDefaultBaudRate
+ UINT8 Parity; ///< <b> 1 - No Parity</b> see EFI_PARITY_TYPE MdePkg.dec PcdUartDefaultParity
+ UINT8 DataBits; ///< <b>8</b> MdePkg.dec PcdUartDefaultDataBits
+ UINT8 StopBits; ///< <b>1 - One Stop Bit</b> see EFI_STOP_BITS_TYPE MdePkg.dec PcdUartDefaultStopBits
+ UINT8 AutoFlow; ///< <b>FALSE</b> IntelFrameworkModulePkg.dsc PcdIsaBusSerialUseHalfHandshake
+} SERIAL_IO_UART_ATTRIBUTES;
+
+/**
+ UART signals pin muxing settings. If signal can be enable only on a single pin
+ then this parameter is ignored by RC. Refer to GPIO_*_MUXING_SERIALIO_UARTx_* in GpioPins*.h
+ for supported settings on a given platform
+**/
+typedef struct {
+ UINT32 Rx; ///< RXD Pin mux configuration. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RXD_*
+ UINT32 Tx; ///< TXD Pin mux configuration. Refer to GPIO_*_MUXING_SERIALIO_UARTx_TXD_*
+ UINT32 Rts; ///< RTS Pin mux configuration. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RTS_*
+ UINT32 Cts; ///< CTS Pin mux configuration. Refer to GPIO_*_MUXING_SERIALIO_UARTx_CTS_*
+} UART_PIN_MUX;
+
+/**
+ Serial IO UART Controller Configuration
+**/
+typedef struct {
+ SERIAL_IO_UART_ATTRIBUTES Attributes; ///< see SERIAL_IO_UART_ATTRIBUTES
+ UART_PIN_MUX PinMux; ///< UART pin mux configuration
+ UINT8 Mode; ///< <b> SerialIoUartPci </b> see SERIAL_IO_UART_MODE
+ UINT8 DBG2; ///< <b> FALSE </b> If TRUE adds UART to DBG2 table and overrides UartPg to SerialIoUartPgDisabled
+ UINT8 PowerGating; ///< <b> SerialIoUartPgAuto </b> Applies to Hidden/COM/SkipInit see SERIAL_IO_UART_PG
+ UINT8 DmaEnable; ///< <b> TRUE </b> Applies to SerialIoUartPci only. Informs OS driver to use DMA, if false it will run in PIO mode
+} SERIAL_IO_UART_CONFIG;
+
+typedef enum {
+ SerialIoUartPgDisabled, ///< No _PS0/_PS3 support, device left in D0, after initialization
+/**
+ In mode: SerialIoUartCom;
+ _PS0/_PS3 that supports getting device out of reset
+ In mode: SerialIoUartPci
+ Keeps UART in D0 and assigns Fixed MMIO for SEC/PEI usage only
+**/
+ SerialIoUartPgEnabled,
+ SerialIoUartPgAuto ///< _PS0 and _PS3, detection through ACPI if device was initialized prior to first PG. If it was used (DBG2) PG is disabled,
+} SERIAL_IO_UART_PG;
+
+/**
+ Available working modes for SerialIo I2C Host Controller
+
+ 0: SerialIoI2cDisabled;
+ - Device is placed in D3
+ - Gpio configuration is skipped
+ - PSF:
+ !important! If given device is Function 0 and other higher functions on given device
+ are enabled, PSF disabling is skipped. PSF default will remain and device PCI CFG Space will still be visible.
+ This is needed to allow PCI enumerator access functions above 0 in a multifunction device.
+ <b>1: SerialIoI2cPci;</b>
+ - Gpio pin configuration in native mode for each assigned pin
+ - Device will be enabled in PSF
+ - Only BAR0 will be enabled
+ 2: SerialIoI2cHidden;
+ - Gpio pin configuration in native mode for each assigned pin
+ - Device disabled in the PSF
+ - Both BARs are enabled, BAR1 becomes devices Pci Config Space
+ - BAR0 assigned from the global PCH reserved memory range, reported as motherboard resource by SIRC
+ @note
+ If this controller is located at function 0 and it's mode is set to hidden it will not be visible in the PCI space.
+**/
+typedef enum {
+ SerialIoI2cDisabled,
+ SerialIoI2cPci,
+ SerialIoI2cHidden
+} SERIAL_IO_I2C_MODE;
+
+/**
+ I2C signals pin muxing settings. If signal can be enable only on a single pin
+ then this parameter is ignored by RC. Refer to GPIO_*_MUXING_SERIALIO_I2Cx_* in GpioPins*.h
+ for supported settings on a given platform
+**/
+typedef struct {
+ UINT32 Sda; ///< SDA Pin mux configuration. Refer to GPIO_*_MUXING_SERIALIO_I2Cx_SDA_*
+ UINT32 Scl; ///< SCL Pin mux configuration. Refer to GPIO_*_MUXING_SERIALIO_I2Cx_SCL_*
+} I2C_PIN_MUX;
+
+/**
+ Serial IO I2C Controller Configuration
+**/
+typedef struct {
+ UINT8 Mode; /// <b>SerialIoI2cPci <b> see SERIAL_IO_I2C_MODE
+ /**
+ I2C Pads Internal Termination.
+ For more information please see Platform Design Guide.
+ Supported values (check GPIO_ELECTRICAL_CONFIG for reference):
+ <b>GpioTermNone: No termination</b>,
+ GpioTermWpu1K: 1kOhm weak pull-up,
+ GpioTermWpu5K: 5kOhm weak pull-up,
+ GpioTermWpu20K: 20kOhm weak pull-up
+ **/
+ UINT8 PadTermination;
+ UINT8 Reserved[2];
+ I2C_PIN_MUX PinMux; ///< I2C pin mux configuration
+} SERIAL_IO_I2C_CONFIG;
+
+#pragma pack (pop)
+
+#endif // _SERIAL_IO_DEVICES_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/SiConfigHob.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/SiConfigHob.h
new file mode 100644
index 0000000000..089141d143
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/SiConfigHob.h
@@ -0,0 +1,17 @@
+/** @file
+ Silicon Config HOB is used for gathering platform
+ related Intel silicon information and config setting.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _SI_CONFIG_HOB_H_
+#define _SI_CONFIG_HOB_H_
+
+#include <SiPolicyStruct.h>
+
+extern EFI_GUID gSiConfigHobGuid;
+
+// Rename SI_CONFIG_HOB into SI_CONFIG_HOB_DATA for it does not follow HOB structure.
+typedef CONST SI_CONFIG SI_CONFIG_HOB_DATA;
+#endif
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/SiPolicyStruct.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/SiPolicyStruct.h
new file mode 100644
index 0000000000..4dacba242e
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/SiPolicyStruct.h
@@ -0,0 +1,64 @@
+/** @file
+ Intel reference code configuration policies.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _SI_POLICY_STRUCT_H_
+#define _SI_POLICY_STRUCT_H_
+
+#include <ConfigBlock.h>
+#include <ConfigBlock/SiPreMemConfig.h>
+#include <ConfigBlock/SiConfig.h>
+
+/**
+ Silicon Policy revision number
+ Any change to this structure will result in an update in the revision number
+
+ This member specifies the revision of the Silicon Policy. This field is used to indicate change
+ to the policy structure.
+
+ <b>Revision 1</b>:
+ - Initial version.
+**/
+#define SI_POLICY_REVISION 1
+
+/**
+ Silicon pre-memory Policy revision number
+ Any change to this structure will result in an update in the revision number
+
+ <b>Revision 1</b>:
+ - Initial version.
+**/
+#define SI_PREMEM_POLICY_REVISION 1
+
+
+/**
+ SI Policy PPI in Pre-Mem\n
+ All SI config block change history will be listed here\n\n
+
+ - <b>Revision 1</b>:
+ - Initial version.\n
+**/
+struct _SI_PREMEM_POLICY_STRUCT {
+ CONFIG_BLOCK_TABLE_HEADER TableHeader; ///< Config Block Table Header
+/*
+ Individual Config Block Structures are added here in memory as part of AddConfigBlock()
+*/
+};
+
+/**
+ SI Policy PPI\n
+ All SI config block change history will be listed here\n\n
+
+ - <b>Revision 1</b>:
+ - Initial version.\n
+**/
+struct _SI_POLICY_STRUCT {
+ CONFIG_BLOCK_TABLE_HEADER TableHeader; ///< Config Block Table Header
+/*
+ Individual Config Block Structures are added here in memory as part of AddConfigBlock()
+*/
+};
+
+#endif
--
2.36.1.windows.1
-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#108694): https://edk2.groups.io/g/devel/message/108694
Mute This Topic: https://groups.io/mt/101373951/7686176
Group Owner: devel+owner@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [rebecca@openfw.io]
-=-=-=-=-=-=-=-=-=-=-=-
^ permalink raw reply related [flat|nested] 41+ messages in thread
* Re: [edk2-devel] [PATCH v2 08/10] AlderlakeSiliconPkg/Fru: Add AdlCpu Fru
2023-09-15 4:45 ` [edk2-devel] [PATCH v2 08/10] AlderlakeSiliconPkg/Fru: Add AdlCpu Fru Saloni Kasbekar
@ 2023-09-15 5:43 ` Chaganty, Rangasai V
2023-09-15 13:29 ` Chuang, Rosen
2023-09-15 23:56 ` Nate DeSimone
1 sibling, 1 reply; 41+ messages in thread
From: Chaganty, Rangasai V @ 2023-09-15 5:43 UTC (permalink / raw)
To: Kasbekar, Saloni, devel@edk2.groups.io
Cc: Desimone, Nathaniel L, Chuang, Rosen
Reviewed-by: Sai Chaganty <rangasai.v.chaganty@intel.com>
-----Original Message-----
From: Kasbekar, Saloni <saloni.kasbekar@intel.com>
Sent: Thursday, September 14, 2023 9:46 PM
To: devel@edk2.groups.io
Cc: Kasbekar, Saloni <saloni.kasbekar@intel.com>; Chaganty, Rangasai V <rangasai.v.chaganty@intel.com>; Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>; Chuang, Rosen <rosen.chuang@intel.com>
Subject: [PATCH v2 08/10] AlderlakeSiliconPkg/Fru: Add AdlCpu Fru
Adds the following modules:
- AdlCpu/CpuPcieRp
- AdlCpu/Include
- AdlCpu/IncludePrivate
- AdlCpu/LibraryPrivate
- AdlCpu/PeiReportCpuHob
- AdlCpu DSCs
Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Rosen Chuang <rosen.chuang@intel.com>
Signed-off-by: Saloni Kasbekar <saloni.kasbekar@intel.com>
---
.../Fru/AdlCpu/CommonLib.dsc | 9 +
.../CpuPcieInfoFruLib.c | 87 ++++++++++
.../PeiDxeSmmCpuPcieInfoFruLib.inf | 39 +++++
.../AlderlakeSiliconPkg/Fru/AdlCpu/DxeLib.dsc | 8 +
.../Fru/AdlCpu/Include/CpuGenInfo.h | 42 +++++
.../Include/Library/CpuPcieInfoFruLib.h | 45 +++++
.../Include/Register/SaRegsHostBridge.h | 64 +++++++
.../AdlCpu/IncludePrivate/CpuGenInfoFruLib.h | 44 +++++ .../AdlCpu/IncludePrivate/Register/IgdRegs.h | 34 ++++
.../BaseCpuInfoFruLib/BaseCpuInfoFruLib.c | 164 ++++++++++++++++++
.../BaseCpuInfoFruLib/BaseCpuInfoFruLib.inf | 29 ++++
.../PeiReportCpuHobLib/PeiReportCpuHobLib.c | 22 +++
.../PeiReportCpuHobLib/PeiReportCpuHobLib.inf | 26 +++
13 files changed, 613 insertions(+)
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/CommonLib.dsc
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/CpuPcieRp/Library/PeiDxeSmmCpuPcieInfoFruLib/CpuPcieInfoFruLib.c
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/CpuPcieRp/Library/PeiDxeSmmCpuPcieInfoFruLib/PeiDxeSmmCpuPcieInfoFruLib.inf
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/DxeLib.dsc
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/Include/CpuGenInfo.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/Include/Library/CpuPcieInfoFruLib.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/Include/Register/SaRegsHostBridge.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/IncludePrivate/CpuGenInfoFruLib.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/IncludePrivate/Register/IgdRegs.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/LibraryPrivate/BaseCpuInfoFruLib/BaseCpuInfoFruLib.c
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/LibraryPrivate/BaseCpuInfoFruLib/BaseCpuInfoFruLib.inf
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/PeiReportCpuHob/Library/PeiReportCpuHobLib/PeiReportCpuHobLib.c
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/PeiReportCpuHob/Library/PeiReportCpuHobLib/PeiReportCpuHobLib.inf
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/CommonLib.dsc b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/CommonLib.dsc
new file mode 100644
index 0000000000..35a3cce916
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/CommonLib.dsc
@@ -0,0 +1,9 @@
+## @file
+# Component description file for the AlderLake CPU Common FRU libraries.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+CpuPcieInfoFruLib|$(PLATFORM_SI_PACKAGE)/Fru/AdlCpu/CpuPcieRp/Library/P
+CpuPcieInfoFruLib|eiDxeSmmCpuPcieInfoFruLib/PeiDxeSmmCpuPcieInfoFruLib.
+CpuPcieInfoFruLib|inf
+CpuInfoFruLib|$(PLATFORM_SI_PACKAGE)/Fru/AdlCpu/LibraryPrivate/BaseCpuI
+CpuInfoFruLib|nfoFruLib/BaseCpuInfoFruLib.inf
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/CpuPcieRp/Library/PeiDxeSmmCpuPcieInfoFruLib/CpuPcieInfoFruLib.c b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/CpuPcieRp/Library/PeiDxeSmmCpuPcieInfoFruLib/CpuPcieInfoFruLib.c
new file mode 100644
index 0000000000..277b73fe67
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/CpuPcieRp/Library/Pei
+++ DxeSmmCpuPcieInfoFruLib/CpuPcieInfoFruLib.c
@@ -0,0 +1,87 @@
+/** @file
+ CPU PCIe information library.
+
+ All function in this library is available for PEI, DXE, and SMM, But
+ do not support UEFI RUNTIME environment call.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/ #include
+<Uefi/UefiBaseType.h> #include <Library/CpuPlatformLib.h> #include
+<Library/DebugLib.h> #include <Library/BaseLib.h> #include
+<Library/PciSegmentLib.h> #include <Register/SaRegsHostBridge.h>
+#include <Library/CpuPcieInfoFruLib.h> #include <CpuPcieInfo.h>
+
+/**
+ Get Maximum CPU Pcie Root Port Number
+
+ @retval Maximum CPU Pcie Root Port Number **/
+UINT8
+GetMaxCpuPciePortNum (
+ VOID
+ )
+{
+ switch (GetCpuSku ()) {
+ case EnumCpuUlt:
+ return CPU_PCIE_ULT_MAX_ROOT_PORT;
+ case EnumCpuUlx:
+ return CPU_PCIE_ULX_MAX_ROOT_PORT;
+ default:
+ return CPU_PCIE_ULT_MAX_ROOT_PORT;
+ }
+}
+
+/**
+ Get CPU Pcie Root Port Device and Function Number by Root Port
+physical Number
+
+ @param[in] RpNumber Root port physical number. (0-based)
+ @param[out] RpDev Return corresponding root port device number.
+ @param[out] RpFun Return corresponding root port function number.
+
+ @retval EFI_SUCCESS Root port device and function is retrieved
+ @retval EFI_INVALID_PARAMETER RpNumber is invalid
+**/
+EFI_STATUS
+EFIAPI
+GetCpuPcieRpDevFun (
+ IN UINTN RpNumber,
+ OUT UINTN *RpDev,
+ OUT UINTN *RpFun
+ )
+{
+ if (RpNumber > GetMaxCpuPciePortNum ()) {
+ DEBUG ((DEBUG_ERROR, "GetCpuPcieRpDevFun invalid RpNumber %x", RpNumber));
+ ASSERT (FALSE);
+ return EFI_INVALID_PARAMETER;
+ }
+
+ switch (RpNumber) {
+ case 0:
+ *RpDev = 6;
+ *RpFun = 0;
+ break;
+ case 1:
+ *RpDev = 1;
+ *RpFun = 0;
+ break;
+ case 2:
+ if (GetCpuSku () == EnumCpuTrad) {
+ *RpDev = 1;
+ *RpFun = 1;
+ } else {
+ *RpDev = 6;
+ *RpFun = 2;
+ }
+ break;
+ default:
+ *RpDev = 6;
+ *RpFun = 0;
+ break;
+ }
+ return EFI_SUCCESS;
+}
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/CpuPcieRp/Library/PeiDxeSmmCpuPcieInfoFruLib/PeiDxeSmmCpuPcieInfoFruLib.inf b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/CpuPcieRp/Library/PeiDxeSmmCpuPcieInfoFruLib/PeiDxeSmmCpuPcieInfoFruLib.inf
new file mode 100644
index 0000000000..f850f1a5f1
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/CpuPcieRp/Library/Pei
+++ DxeSmmCpuPcieInfoFruLib/PeiDxeSmmCpuPcieInfoFruLib.inf
@@ -0,0 +1,39 @@
+## @file
+# CPU PCIe information library for TigerLake PCH.
+#
+# All function in this library is available for PEI, DXE, and SMM, #
+But do not support UEFI RUNTIME environment call.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+
+[Defines]
+INF_VERSION = 0x00010017
+BASE_NAME = PeiDxeSmmCpuPcieInfoFruLib
+FILE_GUID = 59CA5352-ED46-4449-BF1C-0D0074C4D5B1
+VERSION_STRING = 1.0
+MODULE_TYPE = BASE
+LIBRARY_CLASS = CpuPcieInfoFruLib
+
+
+[LibraryClasses]
+IoLib
+BaseLib
+DebugLib
+PrintLib
+PciSegmentLib
+PchPcrLib
+PmcPrivateLib
+PcdLib
+ConfigBlockLib
+CpuPlatformLib
+
+[Packages]
+MdePkg/MdePkg.dec
+AlderlakeSiliconPkg/SiPkg.dec
+
+[Sources]
+CpuPcieInfoFruLib.c
+
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/DxeLib.dsc b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/DxeLib.dsc
new file mode 100644
index 0000000000..644230484e
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/DxeLib.dsc
@@ -0,0 +1,8 @@
+# @file
+# Component description file for the AlderLake CPU DXE FRU libraries.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+DxeGraphicsPolicyLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Graphics/LibraryPri
+DxeGraphicsPolicyLib|vate/DxeGraphicsPolicyLib/DxeGraphicsPolicyLib.inf
+DxeIgdOpRegionInitLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Graphics/LibraryPr
+DxeIgdOpRegionInitLib|ivate/DxeIgdOpRegionInitLib/DxeIgdOpRegionInitLib
+DxeIgdOpRegionInitLib|.inf
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/Include/CpuGenInfo.h b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/Include/CpuGenInfo.h
new file mode 100644
index 0000000000..482316829d
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/Include/CpuGenInfo.h
@@ -0,0 +1,42 @@
+/** @file
+ Header file for Cpu Information
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/ #ifndef
+_CPU_GEN_INFO_H_ #define _CPU_GEN_INFO_H_
+
+#include <CpuRegs.h>
+
+//
+// Processor Definitions
+//
+#define CPUID_FULL_FAMILY_MODEL_ALDERLAKE_MOBILE 0x000906A0
+
+///
+/// Enums for CPU Stepping IDs
+///
+typedef enum {
+
+ ///
+ /// AlderLake Mobile Steppings(ULT)
+ ///
+ EnumAdlJ0 = 0,
+ EnumAdlK0 = 2,
+ EnumAdlL0 = 3,
+
+ ///
+ /// AlderLake Mobile Steppings(ULX)
+ ///
+ EnumAdlQ0 = 1,
+ EnumAdlR0 = 4,
+ EnumAdlS0 = 5,
+
+
+ ///
+ /// Max Stepping
+ ///
+ EnumCpuSteppingMax = CPUID_FULL_STEPPING } CPU_STEPPING; #endif
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/Include/Library/CpuPcieInfoFruLib.h b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/Include/Library/CpuPcieInfoFruLib.h
new file mode 100644
index 0000000000..9dafa98631
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/Include/Library/CpuPc
+++ ieInfoFruLib.h
@@ -0,0 +1,45 @@
+/** @file
+ Header file for CpuPcieInfoFruLib.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/ #ifndef
+_CPU_PCIE_INFO_FRU_LIB_H_ #define _CPU_PCIE_INFO_FRU_LIB_H_
+
+#include <CpuPcieInfo.h>
+
+#define CPU_PCIE_MAX_ROOT_PORTS 4
+#define CPU_PCIE_MAX_CONTROLLERS 3
+
+#define CPU_PCIE_ULT_MAX_ROOT_PORT 3
+#define CPU_PCIE_ULX_MAX_ROOT_PORT 1
+
+/**
+ Get CPU Maximum Pcie Root Port Number
+
+ @retval PcieMaxRootPort Pch Maximum Pcie Root Port Number
+**/
+UINT8
+GetMaxCpuPciePortNum (
+ VOID
+ );
+
+/**
+ Get CPU Pcie Root Port Device and Function Number by Root Port
+physical Number
+
+ @param[in] RpNumber Root port physical number. (0-based)
+ @param[out] RpDev Return corresponding root port device number.
+ @param[out] RpFun Return corresponding root port function number.
+
+ @retval EFI_SUCCESS Root port device and function is retrieved
+ @retval EFI_INVALID_PARAMETER RpNumber is invalid
+**/
+EFI_STATUS
+EFIAPI
+GetCpuPcieRpDevFun (
+ IN UINTN RpNumber,
+ OUT UINTN *RpDev,
+ OUT UINTN *RpFun
+ );
+#endif // _CPU_PCIE_INFO_FRU_LIB_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/Include/Register/SaRegsHostBridge.h b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/Include/Register/SaRegsHostBridge.h
new file mode 100644
index 0000000000..be4bba3283
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/Include/Register/SaRe
+++ gsHostBridge.h
@@ -0,0 +1,64 @@
+/** @file
+ Register names for Host Bridge block
+ <b>Conventions</b>:
+ - Prefixes:
+ - Definitions beginning with "R_" are registers
+ - Definitions beginning with "B_" are bits within registers
+ - Definitions beginning with "V_" are meaningful values of bits within the registers
+ - Definitions beginning with "S_" are register sizes
+ - Definitions beginning with "N_" are the bit position
+ - In general, SA registers are denoted by "_SA_" in register names
+ - Registers / bits that are different between SA generations are denoted by
+ "_SA_[generation_name]_" in register/bit names. e.g., "_SA_HSW_"
+ - Registers / bits that are different between SKUs are denoted by "_[SKU_name]"
+ at the end of the register/bit names
+ - Registers / bits of new devices introduced in a SA generation will be just named
+ as "_SA_" without [generation_name] inserted.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/ #ifndef
+_SA_REGS_HOST_BRIDGE_H_ #define _SA_REGS_HOST_BRIDGE_H_
+
+#define SA_SEG_NUM 0x00
+//
+// DEVICE 0 (Memory Controller Hub)
+//
+#define SA_MC_BUS 0x00
+#define SA_MC_DEV 0x00
+#define SA_MC_FUN 0x00
+#define R_SA_MC_DEVICE_ID 0x02
+
+//
+// AlderLake CPU Mobile SA Device IDs B0:D0:F0 //
+#define V_SA_DEVICE_ID_MB_ULT_1 0x4641 ///< AlderLake P (6+8+GT) SA DID
+#define V_SA_DEVICE_ID_MB_ULT_2 0x4649 ///< AlderLake P (6+4(f)+GT) SA DID
+#define V_SA_DEVICE_ID_MB_ULT_3 0x4621 ///< AlderLake P (4(f)+8+GT) SA DID
+#define V_SA_DEVICE_ID_MB_ULT_4 0x4609 ///< AlderLake P (2(f)+4(f)+GT) SA DID
+#define V_SA_DEVICE_ID_MB_ULT_5 0x4601 ///< AlderLake P (2+8+GT) SA DID
+#define V_SA_DEVICE_ID_MB_ULT_6 0x4661 ///< AlderLake P (6+8+2) SA DID
+#define V_SA_DEVICE_ID_MB_ULT_7 0x4629 ///< AlderLake P (4+4+1) SA DID
+#define V_SA_DEVICE_ID_MB_ULT_8 0x4619 ///< AlderLake P (1+4+GT) SA DID
+#define V_SA_DEVICE_ID_MB_ULT_9 0x4659 ///< AlderLake P (1+8+GT) SA DID
+#define V_SA_DEVICE_ID_MB_ULT_10 0x4645 ///< AlderLake P (6+6+GT) SA DID
+///
+/// Description:
+/// The SMRAMC register controls how accesses to Compatible SMRAM spaces are treated. The Open, Close and Lock bits function only when G_SMRAME bit is set to 1. Also, the Open bit must be reset before the Lock bit is set.
+///
+#define R_SA_SMRAMC (0x88)
+
+///
+/// Description:
+/// This register contains the Top of low memory address.
+///
+#define R_SA_TOLUD (0xbc)
+///
+/// Description of TOLUD (20:31)
+/// This register contains bits 31 to 20 of an address one byte above the maximum DRAM memory below 4G that is usable by the operating system. Address bits 31 down to 20 programmed to 01h implies a minimum memory size of 1MB. Configuration software must set this value to the smaller of the following 2 choices: maximum amount memory in the system minus ME stolen memory plus one byte or the minimum address allocated for PCI memory. Address bits 19:0 are assumed to be 0_0000h for the purposes of address comparison. The Host interface positively decodes an address towards DRAM if the incoming address is less than the value programmed in this register.
+/// The Top of Low Usable DRAM is the lowest address above both Graphics Stolen memory and Tseg. BIOS determines the base of Graphics Stolen Memory by subtracting the Graphics Stolen Memory Size from TOLUD and further decrements by Tseg size to determine base of Tseg. All the Bits in this register are locked in LT mode.
+/// This register must be 1MB aligned when reclaim is enabled.
+///
+#define B_SA_TOLUD_TOLUD_MASK (0xfff00000)
+#endif
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/IncludePrivate/CpuGenInfoFruLib.h b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/IncludePrivate/CpuGenInfoFruLib.h
new file mode 100644
index 0000000000..5ad7bf4982
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/IncludePrivate/CpuGen
+++ InfoFruLib.h
@@ -0,0 +1,44 @@
+ /** @file
+ This file contains Cpu Information for specific generation.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/ #ifndef
+_CPU_GEN_INFO_FRU_LIB_H_ #define _CPU_GEN_INFO_FRU_LIB_H_ #include
+<CpuRegs.h> #include <CpuGenInfo.h> #include <Register/CommonMsr.h>
+
+///
+/// Used to identify the CPU used for programming with the VR override
+table /// typedef enum {
+ EnumUnknownCpuId = 0,
+ EnumMinCpuId = 1,
+
+ ///
+ /// ADL P
+ ///
+ EnumAdlP15Watt282fCpuId = 0x30,
+ EnumAdlP28Watt482fCpuId = 0x31,
+ EnumAdlP28Watt682fCpuId = 0x32,
+ EnumAdlP45Watt682fCpuId = 0x35,
+ EnumAdlP15Watt142fCpuId = 0x36,
+ EnumAdlP15Watt242fCpuId = 0x37,
+ EnumAdlP45Watt482fCpuId = 0x38,
+ EnumAdlP45Watt442fCpuId = 0x39,
+ EnumAdlP28Watt442fCpuId = 0x3A,
+ EnumAdlP28Watt282fCpuId = 0x3B,
+ EnumAdlP28Watt242fCpuId = 0x3C,
+ EnumAdlP28Watt142fCpuId = 0x3D,
+ EnumAdlP45Watt242fCpuId = 0x3E,
+ EnumAdlP28Watt182fCpuId = 0x3F,
+ EnumAdlP28Watt662fCpuId = 0x40,
+ EnumAdlP28Watt642fCpuId = 0x41,
+ EnumAdlP45Watt642fCpuId = 0x42,
+ EnumAdlPMaxCpuId = EnumAdlP45Watt642fCpuId,
+
+} CPU_IDENTIFIER;
+
+#endif // _CPU_GEN_INFO_FRU_LIB_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/IncludePrivate/Register/IgdRegs.h b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/IncludePrivate/Register/IgdRegs.h
new file mode 100644
index 0000000000..289b293b32
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/IncludePrivate/Regist
+++ er/IgdRegs.h
@@ -0,0 +1,34 @@
+/** @file
+ Register names for IGD block
+ <b>Conventions</b>:
+ - Prefixes:
+ - Definitions beginning with "R_" are registers
+ - Definitions beginning with "B_" are bits within registers
+ - Definitions beginning with "V_" are meaningful values of bits within the registers
+ - Definitions beginning with "S_" are register sizes
+ - Definitions beginning with "N_" are the bit position
+ - In general, SA registers are denoted by "_SA_" in register names
+ - Registers / bits that are different between SA generations are denoted by
+ "_SA_[generation_name]_" in register/bit names. e.g., "_SA_HSW_"
+ - Registers / bits that are different between SKUs are denoted by "_[SKU_name]"
+ at the end of the register/bit names
+ - Registers / bits of new devices introduced in a SA generation will be just named
+ as "_SA_" without [generation_name] inserted.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/ #ifndef
+_IGD_REGS_H_ #define _IGD_REGS_H_
+
+///
+/// Device 2 Register Equates
+///
+//
+// The following equates must be reviewed and revised when the specification is ready.
+//
+#define IGD_BUS_NUM 0x00
+#define IGD_DEV_NUM 0x02
+#define IGD_FUN_NUM 0x00
+
+#endif
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/LibraryPrivate/BaseCpuInfoFruLib/BaseCpuInfoFruLib.c b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/LibraryPrivate/BaseCpuInfoFruLib/BaseCpuInfoFruLib.c
new file mode 100644
index 0000000000..d93048eb6e
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/LibraryPrivate/BaseCp
+++ uInfoFruLib/BaseCpuInfoFruLib.c
@@ -0,0 +1,164 @@
+/** @file
+ This file contains the Cpu Information for specific generation.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/ #include
+<CpuGenInfoFruLib.h> #include <Library/BaseLib.h> #include
+<Library/DebugLib.h> #include <Register/Cpuid.h> #include
+<Library/CpuPlatformLib.h> #include <Library/CpuInfoFruLib.h> #include
+<Register/ArchitecturalMsr.h> #include <Library/MemoryAllocationLib.h>
+#include <Register/CommonMsr.h> #include <IndustryStandard/SmBios.h>
+#include <Library/PcdLib.h> #include <Library/PchInfoLib.h> #include
+<IndustryStandard/Pci22.h> #include <Register/IgdRegs.h>
+
+
+STATIC CONST CHAR8 mAdlCpuFamilyString[] = "AlderLake"; typedef struct
+{
+ UINT32 CPUID;
+ UINT8 CpuSku;
+ CHAR8 *String;
+} CPU_REV;
+
+typedef struct {
+ CPU_IDENTIFIER CpuIdentifier;
+ UINT8 SupportedCores;
+ UINT8 SupportedAtomCores;
+} CPU_CORE_COUNT;
+
+GLOBAL_REMOVE_IF_UNREFERENCED CONST CPU_REV mProcessorRevisionTable[] = {
+ {CPUID_FULL_FAMILY_MODEL_ALDERLAKE_MOBILE + EnumAdlJ0, EnumCpuUlt, "J0"},
+ {CPUID_FULL_FAMILY_MODEL_ALDERLAKE_MOBILE + EnumAdlK0, EnumCpuUlt, "K0"},
+ {CPUID_FULL_FAMILY_MODEL_ALDERLAKE_MOBILE + EnumAdlL0, EnumCpuUlt, "L0"},
+ {CPUID_FULL_FAMILY_MODEL_ALDERLAKE_MOBILE + EnumAdlQ0, EnumCpuUlt, "Q0"},
+ {CPUID_FULL_FAMILY_MODEL_ALDERLAKE_MOBILE + EnumAdlR0, EnumCpuUlt, "R0"},
+ {CPUID_FULL_FAMILY_MODEL_ALDERLAKE_MOBILE + EnumAdlQ0, EnumCpuUlx, "Q0"},
+ {CPUID_FULL_FAMILY_MODEL_ALDERLAKE_MOBILE + EnumAdlR0, EnumCpuUlx, "R0"},
+ {CPUID_FULL_FAMILY_MODEL_ALDERLAKE_MOBILE + EnumAdlS0, EnumCpuUlx, "S0"}
+};
+
+///
+/// PowerLimits Override table for all SKUs. Non-cTDP parts would have '0' data for TDP level information.
+///
+GLOBAL_REMOVE_IF_UNREFERENCED PPM_OVERRIDE_TABLE
+mPowerLimitsOverrideTable[] = { ///
+/// CpuIdentifier TDP MSR PL1 MSR PL2 TdpUp TdpUp TdpNominal TdpNominal TdpDown TdpDown MSR MSR Disablefvm
+/// PL1 PL2 PL1 PL2 PL1 PL2 PL1 PL2 PL4 PL4
+ {EnumAdlP15Watt282fCpuId, 1500, 1500, 5500, 0, 5500, 0, 5500, 0, 5500, 12300, 0}, /// 15W 282 ADL-P
+ {EnumAdlP15Watt142fCpuId, 1500, 1500, 5500, 0, 5500, 0, 5500, 0, 5500, 12300, 0}, /// 15W 142 ADL-P
+ {EnumAdlP15Watt242fCpuId, 1500, 1500, 5500, 0, 5500, 0, 5500, 0, 5500, 12300, 0}, /// 15W 242 ADL-P
+ {EnumAdlP28Watt282fCpuId, 2800, 2800, 6400, 0, 6400, 0, 6400, 0, 6400, 9000, 0}, /// 28W 282 ADL-P
+ {EnumAdlP28Watt482fCpuId, 2800, 2800, 6400, 0, 6400, 0, 6400, 0, 6400, 9000, 0}, /// 28W 482 ADL-P
+ {EnumAdlP28Watt682fCpuId, 2800, 2800, 6400, 0, 6400, 0, 6400, 0, 6400, 14000, 0}, /// 26W 682 ADL-P
+ {EnumAdlP28Watt142fCpuId, 2800, 2800, 6400, 0, 6400, 0, 6400, 0, 6400, 9000, 0}, /// 28W 142 ADL-P
+ {EnumAdlP28Watt242fCpuId, 2800, 2800, 6400, 0, 6400, 0, 6400, 0, 6400, 9000, 0}, /// 28W 242 ADL-P
+ {EnumAdlP28Watt442fCpuId, 2800, 2800, 6400, 0, 6400, 0, 6400, 0, 6400, 9000, 0}, /// 28W 442 ADL-P
+ {EnumAdlP28Watt182fCpuId, 2800, 2800, 6400, 0, 6400, 0, 6400, 0, 6400, 9000, 0}, /// 28W 182 ADL-P
+ {EnumAdlP28Watt642fCpuId, 2800, 2800, 6400, 0, 6400, 0, 6400, 0, 6400, 14000, 0}, /// 26W 682 ADL-P
+ {EnumAdlP28Watt662fCpuId, 2800, 2800, 6400, 0, 6400, 0, 6400, 0, 6400, 14000, 0}, /// 26W 682 ADL-P
+ {EnumAdlP45Watt682fCpuId, 4500, 4500, 11500, 0, 11500, 0, 11500, 0, 11500, 21500, 0}, /// 45W 682 ADL-P
+ {EnumAdlP45Watt242fCpuId, 4500, 4500, 9500, 0, 9500, 0, 9500, 0, 9500, 12500, 0}, /// 45W 242 ADL-P
+ {EnumAdlP45Watt482fCpuId, 4500, 4500, 9500, 0, 9500, 0, 9500, 0, 9500, 12500, 0}, /// 45W 482 ADL-P
+ {EnumAdlP45Watt442fCpuId, 4500, 4500, 9500, 0, 9500, 0, 9500, 0, 9500, 12500, 0}, /// 45W 442 ADL-P
+ {EnumAdlP45Watt642fCpuId, 4500, 4500, 11500, 0, 11500, 0, 11500, 0, 11500, 21500, 0}, /// 45W 642 ADL-P
+};
+
+GLOBAL_REMOVE_IF_UNREFERENCED CONST CPU_CORE_COUNT mCpuCoreCountMappingTable[] = {
+ { EnumAdlP15Watt282fCpuId, 2, 8},
+ { EnumAdlP28Watt282fCpuId, 2, 8},
+ { EnumAdlP28Watt482fCpuId, 4, 8},
+ { EnumAdlP28Watt682fCpuId, 6, 8},
+ { EnumAdlP45Watt682fCpuId, 6, 8},
+ { EnumAdlP45Watt482fCpuId, 4, 8},
+ { EnumAdlP45Watt442fCpuId, 4, 4},
+ { EnumAdlP28Watt442fCpuId, 4, 4},
+ { EnumAdlP15Watt142fCpuId, 1, 4},
+ { EnumAdlP28Watt142fCpuId, 1, 4},
+ { EnumAdlP15Watt242fCpuId, 2, 4},
+ { EnumAdlP28Watt242fCpuId, 2, 4},
+ { EnumAdlP45Watt242fCpuId, 2, 4},
+ { EnumAdlP45Watt642fCpuId, 6, 4},
+ { EnumAdlP28Watt182fCpuId, 1, 8},
+ { EnumAdlP28Watt642fCpuId, 6, 4},
+ { EnumAdlP28Watt662fCpuId, 6, 6},
+};
+
+/**
+ Return CPU Sku
+
+ @param[in] UINT32 CpuFamilyModel
+ @param[in] UINT16 CpuDid
+
+ @retval UINT8 CPU Sku
+**/
+UINT8
+GetCpuSkuInfo (
+ IN UINT32 CpuFamilyModel,
+ IN UINT16 CpuDid
+ )
+{
+ UINT8 CpuType;
+ BOOLEAN SkuFound;
+
+ SkuFound = TRUE;
+ CpuType = EnumCpuUnknown;
+
+ switch (CpuFamilyModel) {
+ case CPUID_FULL_FAMILY_MODEL_ALDERLAKE_MOBILE:
+ switch (CpuDid) {
+ case V_SA_DEVICE_ID_MB_ULT_1: // AlderLake P (6+8+GT)
+ case V_SA_DEVICE_ID_MB_ULT_2: // AlderLake P (6+4(f)+GT)
+ case V_SA_DEVICE_ID_MB_ULT_3: // AlderLake P (4(f)+8+GT)
+ case V_SA_DEVICE_ID_MB_ULT_4: // AlderLake P (2(f)+4(f)+GT)
+ case V_SA_DEVICE_ID_MB_ULT_5: // AlderLake P (2+8+GT)
+ case V_SA_DEVICE_ID_MB_ULT_6: // AlderLake P (2+4(f)+GT)
+ case V_SA_DEVICE_ID_MB_ULT_7: // AlderLake P (4+4(f)+GT)
+ case V_SA_DEVICE_ID_MB_ULT_8: // AlderLake P (1+4+GT) SA DID
+ case V_SA_DEVICE_ID_MB_ULT_9: // AlderLake P (1+8+GT) SA DID
+ case V_SA_DEVICE_ID_MB_ULT_10: // AlderLake P (6+6+GT) SA DID
+ CpuType = EnumCpuUlt;
+ break;
+ default:
+ SkuFound = FALSE;
+ break;
+ }
+ break;
+ default:
+ SkuFound = FALSE;
+ break;
+ }
+
+ if (!SkuFound) {
+ DEBUG ((DEBUG_ERROR, "Unsupported CPU SKU, Device ID: 0x%02X, CPUID: 0x%08X!\n", CpuDid, CpuFamilyModel));
+ ASSERT (FALSE);
+ }
+
+ return CpuType;
+}
+
+
+/**
+ This function returns the supported Physical Address Size
+
+ @retval returns the supported Physical Address Size.
+**/
+UINT8
+GetMaxPhysicalAddressSizeFru (
+ VOID
+ )
+{
+ //
+ // Even though CPUID Leaf CPUID_VIR_PHY_ADDRESS_SIZE (0x80000008) MAX_PA will report 46.
+ // For ADL BIOS will return Memory expansion 39 bit (0 - 38) + MKTME (Bits 39-41 must be zero - 3 bit hole in the middle) 42-45 bit is MKTME Keys.
+ //
+ return 39;
+}
+
+
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/LibraryPrivate/BaseCpuInfoFruLib/BaseCpuInfoFruLib.inf b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/LibraryPrivate/BaseCpuInfoFruLib/BaseCpuInfoFruLib.inf
new file mode 100644
index 0000000000..22bcbdf43c
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/LibraryPrivate/BaseCp
+++ uInfoFruLib/BaseCpuInfoFruLib.inf
@@ -0,0 +1,29 @@
+## @file
+# This file contains the Cpu Information for specific generation.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+
+[Defines]
+INF_VERSION = 0x00010017
+BASE_NAME = BaseCpuInfoFruLib
+FILE_GUID = 72E44627-C719-4B2D-8C5D-963E167E5AAC
+VERSION_STRING = 1.0
+MODULE_TYPE = BASE
+LIBRARY_CLASS = CpuInfoFruLib
+
+[LibraryClasses]
+BaseLib
+DebugLib
+PchInfoLib
+
+[Packages]
+MdePkg/MdePkg.dec
+UefiCpuPkg/UefiCpuPkg.dec
+AlderlakeSiliconPkg/SiPkg.dec
+
+[Sources]
+BaseCpuInfoFruLib.c
+
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/PeiReportCpuHob/Library/PeiReportCpuHobLib/PeiReportCpuHobLib.c b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/PeiReportCpuHob/Library/PeiReportCpuHobLib/PeiReportCpuHobLib.c
new file mode 100644
index 0000000000..7ea605a05b
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/PeiReportCpuHob/Libra
+++ ry/PeiReportCpuHobLib/PeiReportCpuHobLib.c
@@ -0,0 +1,22 @@
+/** @file
+
+ Source code file for Report CPU HOB library.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/
+
+#include <Base.h>
+#include <Library/HobLib.h>
+#include <Library/CpuPlatformLib.h>
+
+VOID
+ReportCpuHob (
+ VOID
+ )
+{
+ ///
+ /// Create a CPU hand-off information
+ ///
+ BuildCpuHob (GetMaxPhysicalAddressSize (), 16); }
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/PeiReportCpuHob/Library/PeiReportCpuHobLib/PeiReportCpuHobLib.inf b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/PeiReportCpuHob/Library/PeiReportCpuHobLib/PeiReportCpuHobLib.inf
new file mode 100644
index 0000000000..0ba4744eea
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/PeiReportCpuHob/Libra
+++ ry/PeiReportCpuHobLib/PeiReportCpuHobLib.inf
@@ -0,0 +1,26 @@
+### @file
+# Component information file for the Report CPU HOB library.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+[Defines]
+ INF_VERSION = 0x00010017
+ BASE_NAME = PeiReportCpuHobLib
+ FILE_GUID = F19AA754-CE24-448D-B755-1F939B00C23D
+ VERSION_STRING = 1.0
+ MODULE_TYPE = PEIM
+ LIBRARY_CLASS = ReportCpuHobLib
+
+[LibraryClasses]
+ BaseLib
+ HobLib
+ CpuPlatformLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ AlderlakeSiliconPkg/SiPkg.dec
+
+[Sources]
+ PeiReportCpuHobLib.c
--
2.36.1.windows.1
-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#108693): https://edk2.groups.io/g/devel/message/108693
Mute This Topic: https://groups.io/mt/101373952/7686176
Group Owner: devel+owner@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [rebecca@openfw.io]
-=-=-=-=-=-=-=-=-=-=-=-
^ permalink raw reply related [flat|nested] 41+ messages in thread
* Re: [edk2-devel] [PATCH v2 09/10] AlderlakeSiliconPkg: Add AdlPch Fru and IncludePrivate modules
2023-09-15 4:45 ` [edk2-devel] [PATCH v2 09/10] AlderlakeSiliconPkg: Add AdlPch Fru and IncludePrivate modules Saloni Kasbekar
@ 2023-09-15 5:43 ` Chaganty, Rangasai V
2023-09-15 13:29 ` Chuang, Rosen
2023-09-15 23:57 ` Nate DeSimone
1 sibling, 1 reply; 41+ messages in thread
From: Chaganty, Rangasai V @ 2023-09-15 5:43 UTC (permalink / raw)
To: Kasbekar, Saloni, devel@edk2.groups.io
Cc: Desimone, Nathaniel L, Chuang, Rosen
Reviewed-by: Sai Chaganty <rangasai.v.chaganty@intel.com>
-----Original Message-----
From: Kasbekar, Saloni <saloni.kasbekar@intel.com>
Sent: Thursday, September 14, 2023 9:46 PM
To: devel@edk2.groups.io
Cc: Kasbekar, Saloni <saloni.kasbekar@intel.com>; Chaganty, Rangasai V <rangasai.v.chaganty@intel.com>; Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>; Chuang, Rosen <rosen.chuang@intel.com>
Subject: [PATCH v2 09/10] AlderlakeSiliconPkg: Add AdlPch Fru and IncludePrivate modules
Adds the following modules:
- AdlPch/Include
- AdlPch/IncludePrivate
- AdlPch/Library
- AdlPch DSCs
- IncludePrivate
Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Rosen Chuang <rosen.chuang@intel.com>
Signed-off-by: Saloni Kasbekar <saloni.kasbekar@intel.com>
---
.../Fru/AdlPch/CommonLib.dsc | 29 ++
.../AlderlakeSiliconPkg/Fru/AdlPch/Dxe.dsc | 10 +
.../AlderlakeSiliconPkg/Fru/AdlPch/DxeLib.dsc | 7 +
.../Fru/AdlPch/Include/PchBdfAssignment.h | 81 +++++
.../Fru/AdlPch/Include/PchLimits.h | 47 +++
.../Fru/AdlPch/Include/PchPcieRpInfo.h | 17 ++
.../Fru/AdlPch/Include/PchReservedResources.h | 13 + .../AdlPch/Include/PchReservedResourcesAdpP.h | 36 +++
.../IncludePrivate/Register/PchPcrRegs.h | 59 ++++
.../IncludePrivate/Register/PchRegsLpcAdl.h | 30 ++
.../PeiDxeSmmPchInfoLib/PchInfoLibAdl.c | 223 ++++++++++++++
.../PeiDxeSmmPchInfoLib/PchInfoLibPrivate.h | 44 +++
.../PeiDxeSmmPchInfoLibAdl.inf | 37 +++
.../AlderlakeSiliconPkg/Fru/AdlPch/Pei.dsc | 7 +
.../AlderlakeSiliconPkg/Fru/AdlPch/PeiLib.dsc | 12 +
.../IncludePrivate/RegisterAccess.h | 288 ++++++++++++++++++
16 files changed, 940 insertions(+)
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/CommonLib.dsc
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Dxe.dsc
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/DxeLib.dsc
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Include/PchBdfAssignment.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Include/PchLimits.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Include/PchPcieRpInfo.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Include/PchReservedResources.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Include/PchReservedResourcesAdpP.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/IncludePrivate/Register/PchPcrRegs.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/IncludePrivate/Register/PchRegsLpcAdl.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Library/PeiDxeSmmPchInfoLib/PchInfoLibAdl.c
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Library/PeiDxeSmmPchInfoLib/PchInfoLibPrivate.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Library/PeiDxeSmmPchInfoLib/PeiDxeSmmPchInfoLibAdl.inf
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Pei.dsc
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/PeiLib.dsc
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IncludePrivate/RegisterAccess.h
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/CommonLib.dsc b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/CommonLib.dsc
new file mode 100644
index 0000000000..3f508f83a1
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/CommonLib.dsc
@@ -0,0 +1,29 @@
+## @file
+# Component description file for the AlderLake PCH Common FRU libraries.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+
+ PchPcrLib|$(PLATFORM_SI_PACKAGE)/IpBlock/P2sb/Library/PeiDxeSmmPchPcrL
+ ib/PeiDxeSmmPchPcrLib.inf
+ PchSbiAccessLib|$(PLATFORM_SI_PACKAGE)/IpBlock/P2sb/LibraryPrivate/Pei
+ DxeSmmPchSbiAccessLib/PeiDxeSmmPchSbiAccessLib.inf
+
+ P2SbSidebandAccessLib|$(PLATFORM_SI_PACKAGE)/IpBlock/P2sb/LibraryPriva
+ te/PeiDxeSmmP2SbSidebandAccessLib/PeiDxeSmmP2SbSidebandAccessLib.inf
+
+
+ EspiLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Espi/Library/PeiDxeSmmEspiLib/P
+ eiDxeSmmEspiLib.inf
+
+
+
+ PmcLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Pmc/Library/PeiDxeSmmPmcLib/PeiD
+ xeSmmPmcLib.inf
+ PmcPrivateLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Pmc/LibraryPrivate/PeiDxe
+ SmmPmcPrivateLib/PeiDxeSmmPmcPrivateLib.inf
+
+ SpiCommonLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Spi/LibraryPrivate/BaseSpi
+ CommonLib/BaseSpiCommonLib.inf
+ GpioLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Gpio/Library/PeiDxeSmmGpioLib/P
+ eiDxeSmmGpioLib.inf
+ PchDmiLib|$(PLATFORM_SI_PACKAGE)/IpBlock/PchDmi/LibraryPrivate/PeiDxeS
+ mmPchDmiLib/PeiDxeSmmPchDmiLib.inf
+
+
+ GpioPrivateLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Gpio/LibraryPrivate/PeiD
+ xeSmmGpioPrivateLib/PeiDxeSmmGpioPrivateLibVer2.inf
+
+ PchPcieRpLib|$(PLATFORM_SI_PACKAGE)/IpBlock/PcieRp/Library/PeiDxeSmmPc
+ hPcieRpLib/PeiDxeSmmPchPcieRpLibVer2.inf
+
+
+ #
+ # Common FRU Libraries
+ #
+
+ PchInfoLib|$(PLATFORM_SI_PACKAGE)/Fru/AdlPch/Library/PeiDxeSmmPchInfoL
+ ib/PeiDxeSmmPchInfoLibAdl.inf
+
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Dxe.dsc b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Dxe.dsc
new file mode 100644
index 0000000000..b443611d9a
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Dxe.dsc
@@ -0,0 +1,10 @@
+## @file
+# Component description file for the AlderLake PCH DXE FRU drivers.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+ $(PLATFORM_SI_PACKAGE)/IpBlock/Spi/Smm/SpiSmm.inf
+
+
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/DxeLib.dsc b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/DxeLib.dsc
new file mode 100644
index 0000000000..e350b8e643
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/DxeLib.dsc
@@ -0,0 +1,7 @@
+# @file
+# Component description file for the AlderLake PCH DXE FRU libraries.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+GpioHelpersLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Gpio/LibraryPrivate/BaseG
+pioHelpersLibNull/BaseGpioHelpersLibNull.inf
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Include/PchBdfAssignment.h b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Include/PchBdfAssignment.h
new file mode 100644
index 0000000000..b8af6d7624
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Include/PchBdfAssignm
+++ ent.h
@@ -0,0 +1,81 @@
+/** @file
+ Header file for AlderLake PCH devices PCI Bus Device Function map.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/ #ifndef
+_PCH_BDF_ASSIGNMENT_H_ #define _PCH_BDF_ASSIGNMENT_H_
+
+#define NOT_PRESENT 0xFF
+
+//
+// PCH PCIe Controllers
+//
+#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_1 28
+#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_2 28
+#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_3 28
+#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_4 28
+#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_5 28
+#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_6 28
+#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_7 28
+#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_8 28
+#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_9 29
+#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_10 29
+#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_11 29
+#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_12 29
+#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_13 29
+#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_14 29
+#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_15 29
+#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_16 29
+#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_17 27
+#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_18 27
+#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_19 27
+#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_20 27
+#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_21 27
+#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_22 27
+#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_23 27
+#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_24 27
+#ifdef PCH_ADPP
+#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_25 NOT_PRESENT
+#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_26 NOT_PRESENT
+#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_27 NOT_PRESENT
+#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_28 NOT_PRESENT
+#else
+#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_25 26
+#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_26 26
+#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_27 26
+#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_28 26
+#endif
+
+//
+// USB3 (XHCI) Controller PCI config
+//
+#define PCI_DEVICE_NUMBER_PCH_XHCI 20
+#define PCI_FUNCTION_NUMBER_PCH_XHCI 0
+
+
+
+
+//
+// LPC Controller (D31:F0)
+//
+#define PCI_DEVICE_NUMBER_PCH_LPC 31
+#define PCI_FUNCTION_NUMBER_PCH_LPC 0
+
+//
+// Primary to Sideband (P2SB) Bridge (D31:F1) //
+#define PCI_DEVICE_NUMBER_PCH_P2SB 31
+#define PCI_FUNCTION_NUMBER_PCH_P2SB 1
+
+
+
+//
+// SPI Controller (D31:F5)
+//
+#define PCI_DEVICE_NUMBER_PCH_SPI 31
+#define PCI_FUNCTION_NUMBER_PCH_SPI 5
+
+
+#endif // _PCH_BDF_ASSIGNMENT_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Include/PchLimits.h b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Include/PchLimits.h
new file mode 100644
index 0000000000..dad3a9a073
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Include/PchLimits.h
@@ -0,0 +1,47 @@
+/** @file
+ Build time limits of PCH resources.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/ #ifndef
+_PCH_LIMITS_H_ #define _PCH_LIMITS_H_
+/*
+ * Defines povided in this file are indended to be used only where
+static value
+ * is needed. They are set to values which allow to accomodate multiple
+projects
+ * needs. Where runtime usage is possible please used dedicated
+functions from
+ * PchInfoLib to retrieve accurate values */
+
+
+
+//
+// PCIe limits
+//
+#define PCH_MAX_PCIE_ROOT_PORTS 28
+#define PCH_MAX_PCIE_CONTROLLERS 7
+
+//
+// PCIe clocks limits
+//
+#define PCH_MAX_PCIE_CLOCKS 18
+
+//
+// DMI lanes
+//
+#define PCH_MAX_DMI_LANES 8
+
+//
+// SerialIo limits
+//
+#define PCH_MAX_SERIALIO_I2C_CONTROLLERS 8
+#define PCH_MAX_SERIALIO_SPI_CONTROLLERS 7
+#define PCH_MAX_SERIALIO_SPI_CHIP_SELECTS 2
+#define PCH_MAX_SERIALIO_UART_CONTROLLERS 7
+
+//
+// Number of eSPI slaves
+//
+#define PCH_MAX_ESPI_SLAVES 2
+
+#endif // _PCH_LIMITS_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Include/PchPcieRpInfo.h b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Include/PchPcieRpInfo.h
new file mode 100644
index 0000000000..9276b61e1f
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Include/PchPcieRpInfo
+++ .h
@@ -0,0 +1,17 @@
+/** @file
+ Pcie Root Port info header
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/
+
+#ifndef _PCH_PCIERP_INFO_H_
+#define _PCH_PCIERP_INFO_H_
+
+//
+// Number of PCIe ports per PCIe controller //
+#define PCH_PCIE_CONTROLLER_PORTS 4u
+
+
+#endif
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Include/PchReservedResources.h b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Include/PchReservedResources.h
new file mode 100644
index 0000000000..f4adfab74f
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Include/PchReservedRe
+++ sources.h
@@ -0,0 +1,13 @@
+/** @file
+ PCH preserved MMIO resource definitions.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/
+
+#ifndef _PCH_PRESERVED_RESOURCES_H_
+#define _PCH_PRESERVED_RESOURCES_H_
+#include "PchReservedResourcesAdpP.h"
+
+#endif // _PCH_PRESERVED_RESOURCES_H_
+
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Include/PchReservedResourcesAdpP.h b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Include/PchReservedResourcesAdpP.h
new file mode 100644
index 0000000000..69aac29cea
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Include/PchReservedRe
+++ sourcesAdpP.h
@@ -0,0 +1,36 @@
+/** @file
+ PCH preserved MMIO resource definitions.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/ #ifndef
+_PCH_PRESERVED_RESOURCES_ADP_P_H_
+#define _PCH_PRESERVED_RESOURCES_ADP_P_H_
+
+/**
+ Detailed recommended static allocation
+ +-------------------------------------------------------------------------+
+ | PCH preserved MMIO range, 32 MB, from 0xFC800000 to 0xFE7FFFFF |
+ +-------------------------------------------------------------------------+
+ | Size | Start | End | Usage |
+ | 8 MB | 0xFC800000 | 0xFCFFFFFF | TraceHub SW BAR |
+ | 16 MB | 0xFD000000 | 0xFDFFFFFF | SBREG |
+ | 64 KB | 0xFE000000 | 0xFE00FFFF | PMC MBAR |
+ | 4 KB | 0xFE010000 | 0xFE010FFF | SPI BAR0 |
+ | 176 KB | 0xFE020000 | 0xFE04BFFF | SerialIo BAR in ACPI mode |
+ | 400 KB | 0xFE04C000 | 0xFE0AFFFF | Unused |
+ | 64 KB | 0xFE0B0000 | 0xFE0BFFFF | eSPI LGMR BAR |
+ | 64 KB | 0xFE0C0000 | 0xFE0CFFFF | eSPI2 SEGMR BAR |
+ | 192 KB | 0xFE0D0000 | 0xFE0FFFFF | Unused |
+ | 1 MB | 0xFE100000 | 0xFE1FFFFF | TraceHub MTB BAR |
+ | 2 MB | 0xFE200000 | 0xFE3FFFFF | TraceHub FW BAR |
+ | 2 MB | 0xFE400000 | 0xFE5FFFFF | Unused |
+ | 2 MB | 0xFE600000 | 0xFE7FFFFF | Temp address |
+
++----------------------------------------------------------------------
+---+
+**/
+#define PCH_PCR_BASE_ADDRESS 0xFD000000 ///< SBREG MMIO base address
+#define PCH_PWRM_BASE_ADDRESS 0xFE000000 ///< PMC MBAR MMIO base address
+#define PCH_SPI_BASE_ADDRESS 0xFE010000 ///< SPI BAR0 MMIO base address
+
+#endif // _PCH_PRESERVED_RESOURCES_ADP_P_H_
+
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/IncludePrivate/Register/PchPcrRegs.h b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/IncludePrivate/Register/PchPcrRegs.h
new file mode 100644
index 0000000000..fe548dae4b
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/IncludePrivate/Regist
+++ er/PchPcrRegs.h
@@ -0,0 +1,59 @@
+/** @file
+ Register names for PCH private chipset register
+
+Conventions:
+
+ - Register definition format:
+
+ Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_Re
+ gisterName
+ - Prefix:
+ Definitions beginning with "R_" are registers
+ Definitions beginning with "B_" are bits within registers
+ Definitions beginning with "V_" are meaningful values within the bits
+ Definitions beginning with "S_" are register size
+ Definitions beginning with "N_" are the bit position
+ - [GenerationName]:
+ Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc.).
+ Register name without GenerationName applies to all generations.
+ - [ComponentName]:
+ This field indicates the component name that the register belongs to (e.g. PCH, SA etc.)
+ Register name without ComponentName applies to all components.
+ Register that is specific to -H denoted by "_PCH_H_" in component name.
+ Register that is specific to -LP denoted by "_PCH_LP_" in component name.
+ - SubsystemName:
+ This field indicates the subsystem name of the component that the register belongs to
+ (e.g. PCIE, USB, SATA, GPIO, PMC etc.).
+ - RegisterSpace:
+ MEM - MMIO space register of subsystem.
+ IO - IO space register of subsystem.
+ PCR - Private configuration register of subsystem.
+ CFG - PCI configuration space register of subsystem.
+ - RegisterName:
+ Full register name.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/
+
+#ifndef _PCH_REGS_PCR_H_
+#define _PCH_REGS_PCR_H_
+
+
+/**
+ Definition for SBI PID
+ The PCH_SBI_PID defines the PID for PCR MMIO programming and PCH SBI programming as well.
+**/
+#define PID_DMI 0x88
+#define PID_ESPISPI 0x72
+#define PID_SPF 0x85
+#define PID_SPE 0x84
+#define PID_SPD 0x83
+#define PID_SPC 0x82
+#define PID_SPB 0x81
+#define PID_SPA 0x80
+#define PID_GPIOCOM0 0x6E
+#define PID_GPIOCOM1 0x6D
+#define PID_GPIOCOM2 0x6C
+#define PID_GPIOCOM4 0x6A
+#define PID_GPIOCOM5 0x69
+
+#endif
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/IncludePrivate/Register/PchRegsLpcAdl.h b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/IncludePrivate/Register/PchRegsLpcAdl.h
new file mode 100644
index 0000000000..8b1a01036e
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/IncludePrivate/Regist
+++ er/PchRegsLpcAdl.h
@@ -0,0 +1,30 @@
+/** @file
+ Register names for ADL PCH LPC/eSPI device
+
+ Conventions:
+
+ - Prefixes:
+ Definitions beginning with "R_" are registers
+ Definitions beginning with "B_" are bits within registers
+ Definitions beginning with "V_" are meaningful values within the bits
+ Definitions beginning with "S_" are register sizes
+ Definitions beginning with "N_" are the bit position
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/ #ifndef
+_PCH_REGS_LPC_ADL_H_ #define _PCH_REGS_LPC_ADL_H_
+
+//
+// ADL PCH-P/M LPC Device IDs
+//
+#define V_ADL_PCH_P_LPC_CFG_DEVICE_ID_MB_0 0x5180 ///< LPC/eSPI Controller
+#define V_ADL_PCH_P_LPC_CFG_DEVICE_ID_MB_1 0x5181 ///< LPC/eSPI Controller P SuperSKU
+#define V_ADL_PCH_P_LPC_CFG_DEVICE_ID_MB_2 0x5182 ///< LPC/eSPI Controller P Premium
+#define V_ADL_PCH_P_LPC_CFG_DEVICE_ID_MB_3 0x5183 ///< LPC/eSPI Controller Placeholder
+#define V_ADL_PCH_P_LPC_CFG_DEVICE_ID_MB_4 0x5184 ///< LPC/eSPI Controller
+#define V_ADL_PCH_P_LPC_CFG_DEVICE_ID_MB_5 0x5185 ///< LPC/eSPI Controller
+
+
+#endif
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Library/PeiDxeSmmPchInfoLib/PchInfoLibAdl.c b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Library/PeiDxeSmmPchInfoLib/PchInfoLibAdl.c
new file mode 100644
index 0000000000..c74d665533
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Library/PeiDxeSmmPchI
+++ nfoLib/PchInfoLibAdl.c
@@ -0,0 +1,223 @@
+/** @file
+ Pch information library for ADL.
+
+ All function in this library is available for PEI, DXE, and SMM, But
+ do not support UEFI RUNTIME environment call.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/ #include <Base.h>
+#include <PchPcieRpInfo.h> #include <Uefi/UefiBaseType.h> #include
+<Library/PchInfoLib.h> #include <Library/PmcPrivateLib.h> #include
+<Library/PrintLib.h> #include <Library/IoLib.h> #include
+<Library/DebugLib.h> #include <Library/BaseLib.h> #include
+<Library/PciSegmentLib.h> #include <Library/PcdLib.h> #include
+<Library/PchPciBdfLib.h> #include <Register/PchRegsLpcAdl.h> #include
+<Register/PchRegs.h> #include <Register/PchRegsLpc.h> #include
+<IndustryStandard/Pci30.h> #include "PchInfoLibPrivate.h"
+
+
+/**
+ Return LPC Device Id
+
+ @retval PCH_LPC_DEVICE_ID PCH Lpc Device ID
+**/
+UINT16
+PchGetLpcDid (
+ VOID
+ )
+{
+ UINT64 LpcBaseAddress;
+
+ LpcBaseAddress = LpcPciCfgBase ();
+
+ return PciSegmentRead16 (LpcBaseAddress + PCI_DEVICE_ID_OFFSET);
+}
+
+/**
+ Return Pch Series
+
+ @retval PCH_SERIES Pch Series
+**/
+PCH_SERIES
+PchSeries (
+ VOID
+ )
+{
+ PCH_SERIES PchSer;
+ static PCH_SERIES PchSeries = PCH_UNKNOWN_SERIES;
+
+ if (PchSeries != PCH_UNKNOWN_SERIES) {
+ return PchSeries;
+ }
+
+ PchSer = PchSeriesFromLpcDid (PchGetLpcDid ());
+
+ PchSeries = PchSer;
+
+ return PchSer;
+}
+
+/**
+ Return Pch stepping type
+
+ @retval PCH_STEPPING Pch stepping type
+**/
+PCH_STEPPING
+PchStepping (
+ VOID
+ )
+{
+ UINT8 RevId;
+ UINT64 LpcBaseAddress;
+ static PCH_STEPPING PchStepping = PCH_STEPPING_MAX;
+
+ if (PchStepping != PCH_STEPPING_MAX) {
+ return PchStepping;
+ }
+
+ LpcBaseAddress = LpcPciCfgBase ();
+ RevId = PciSegmentRead8 (LpcBaseAddress + PCI_REVISION_ID_OFFSET);
+
+ RevId = PchSteppingFromRevId (RevId);
+
+ PchStepping = RevId;
+
+ return RevId;
+}
+
+/**
+ Check if this is PCH P series
+
+ @retval TRUE It's PCH P series
+ @retval FALSE It's not PCH P series
+**/
+BOOLEAN
+IsPchP (
+ VOID
+ )
+{
+ return (PchSeries () == PCH_P);
+}
+
+/**
+ return support status for P2SB PCR 20-bit addressing
+
+ @retval TRUE
+ @retval FALSE
+**/
+BOOLEAN
+IsP2sb20bPcrSupported (
+ VOID
+ )
+{
+ return FALSE;
+}
+
+/**
+ Determine Pch Series based on Device Id
+
+ @param[in] LpcDeviceId Lpc Device Id
+
+ @retval PCH_SERIES Pch Series
+**/
+PCH_SERIES
+PchSeriesFromLpcDid (
+ IN UINT16 LpcDeviceId
+ )
+{
+ return PCH_P;
+}
+
+/**
+ Determine Pch Stepping based on Revision ID
+
+ @param[in] RevId Pch Revision Id
+
+ @retval PCH_STEPPING Pch Stepping
+**/
+PCH_STEPPING
+PchSteppingFromRevId (
+ IN UINT8 RevId
+ )
+{
+ return RevId;
+}
+
+
+/**
+ Check if this is PCH LP series
+
+ @retval TRUE It's PCH LP series
+ @retval FALSE It's not PCH LP series
+**/
+BOOLEAN
+IsPchLp (
+ VOID
+ )
+{
+ return (PchSeries () == PCH_LP || PchSeries () == PCH_P || PchSeries () == PCH_M || PchSeries () == PCH_N );
+}
+/**
+ Get RST mode supported by the silicon
+
+ @retval RST_MODE RST mode supported by silicon
+**/
+
+GLOBAL_REMOVE_IF_UNREFERENCED
+struct PCH_SKU_STRING mSkuStrs[] = {
+ //
+ // ADL PCH LPC Device IDs
+ //
+ {V_ADL_PCH_P_LPC_CFG_DEVICE_ID_MB_0, "ADL SKU 0"},
+ {V_ADL_PCH_P_LPC_CFG_DEVICE_ID_MB_1, "P Super SKU (SSKU)"},
+ {V_ADL_PCH_P_LPC_CFG_DEVICE_ID_MB_2, "P Premium"},
+ {V_ADL_PCH_P_LPC_CFG_DEVICE_ID_MB_3, "ADL No UFS"},
+ {V_ADL_PCH_P_LPC_CFG_DEVICE_ID_MB_4, "ADL SKU 4"},
+ {V_ADL_PCH_P_LPC_CFG_DEVICE_ID_MB_5, "ADL SKU 5"},
+
+ {0xFFFF, NULL}
+};
+
+/**
+ Get Pch Maximum Pcie Root Port Number
+
+ @retval Pch Maximum Pcie Root Port Number
+**/
+UINT8
+GetPchMaxPciePortNum (
+ VOID
+ )
+{
+ switch (PchSeries ()) {
+ case PCH_P:
+ case PCH_N:
+ return 12;
+ case PCH_S:
+ return 28;
+ default:
+ return 0;
+ }
+}
+
+/**
+ Get Pch Maximum Serial IO I2C controllers number
+
+ @retval Pch Maximum Serial IO I2C controllers number
+**/
+UINT8
+GetPchMaxSerialIoI2cControllersNum (
+ VOID
+ )
+{
+ return 8;
+}
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Library/PeiDxeSmmPchInfoLib/PchInfoLibPrivate.h b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Library/PeiDxeSmmPchInfoLib/PchInfoLibPrivate.h
new file mode 100644
index 0000000000..a4bd4d5aa7
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Library/PeiDxeSmmPchInfoLib/PchInfoLibPrivate.h
@@ -0,0 +1,44 @@
+/** @file
+ Private header for PCH Info Lib.
+
+ All function in this library is available for PEI, DXE, and SMM,
+ But do not support UEFI RUNTIME environment call.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+/**
+ Structure for PCH SKU string mapping
+**/
+struct PCH_SKU_STRING {
+ UINT16 Id;
+ CHAR8 *String;
+};
+
+extern struct PCH_SKU_STRING mSkuStrs[];
+
+/**
+ Determine Pch Series based on Device Id
+
+ @param[in] LpcDeviceId Lpc Device Id
+
+ @retval PCH_SERIES Pch Series
+**/
+PCH_SERIES
+PchSeriesFromLpcDid (
+ IN UINT16 LpcDeviceId
+ );
+
+/**
+ Determine Pch Stepping based on Revision ID
+
+ @param[in] RevId Pch Revision Id
+
+ @retval PCH_STEPPING Pch Stepping
+**/
+PCH_STEPPING
+PchSteppingFromRevId (
+ IN UINT8 RevId
+ );
+
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Library/PeiDxeSmmPchInfoLib/PeiDxeSmmPchInfoLibAdl.inf b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Library/PeiDxeSmmPchInfoLib/PeiDxeSmmPchInfoLibAdl.inf
new file mode 100644
index 0000000000..28a6863aed
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Library/PeiDxeSmmPchInfoLib/PeiDxeSmmPchInfoLibAdl.inf
@@ -0,0 +1,37 @@
+## @file
+# PCH information library for Alderlake PCH.
+#
+# All function in this library is available for PEI, DXE, and SMM,
+# But do not support UEFI RUNTIME environment call.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+
+[Defines]
+INF_VERSION = 0x00010017
+BASE_NAME = PeiDxeSmmPchInfoLibAdl
+FILE_GUID = F5B0CBB7-4AFC-4535-A5EC-D9ECEDA24DC5
+VERSION_STRING = 1.0
+MODULE_TYPE = BASE
+LIBRARY_CLASS = PchInfoLib
+
+
+[LibraryClasses]
+BaseLib
+IoLib
+DebugLib
+PrintLib
+PciSegmentLib
+PmcPrivateLib
+PcdLib
+
+
+[Packages]
+MdePkg/MdePkg.dec
+AlderlakeSiliconPkg/SiPkg.dec
+
+
+[Sources]
+PchInfoLibAdl.c
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Pei.dsc b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Pei.dsc
new file mode 100644
index 0000000000..8a923554dd
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Pei.dsc
@@ -0,0 +1,7 @@
+## @file
+# Component description file for the AlderLake PCH PEI FRU drivers.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/PeiLib.dsc b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/PeiLib.dsc
new file mode 100644
index 0000000000..ebe2bbfda0
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/PeiLib.dsc
@@ -0,0 +1,12 @@
+## @file
+# Component description file for the AlderLake PCH PEI FRU libraries.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+ SpiLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Spi/Library/PeiSpiLib/PeiSpiLib.inf
+
+ GpioHelpersLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Gpio/LibraryPrivate/PeiGpioHelpersLib/PeiGpioHelpersLib.inf
+
+
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IncludePrivate/RegisterAccess.h b/Silicon/Intel/AlderlakeSiliconPkg/IncludePrivate/RegisterAccess.h
new file mode 100644
index 0000000000..25a0ba49d2
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IncludePrivate/RegisterAccess.h
@@ -0,0 +1,288 @@
+/** @file
+ Header file for register access.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _REGISTER_ACCESS_H_
+#define _REGISTER_ACCESS_H_
+
+typedef struct _REGISTER_ACCESS REGISTER_ACCESS;
+
+/**
+ Reads an 8-bit register
+
+ @param[in] This Pointer to REGISTER_ACCESS
+ @param[in] Offset Offset of the register in the register bank
+
+ @return The 8-bit register value specified by Offset
+**/
+typedef
+UINT8
+(*REG_READ8) (
+ IN REGISTER_ACCESS *This,
+ IN UINT32 Offset
+ );
+
+/**
+ Writes an 8-bit register
+
+ @param[in] This Pointer to REGISTER_ACCESS
+ @param[in] Offset Offset of the register in the register bank
+ @param[in] Value Value to write to register
+
+ @return The 8-bit register value written to register
+**/
+typedef
+UINT8
+(*REG_WRITE8) (
+ IN REGISTER_ACCESS *This,
+ IN UINT32 Offset,
+ IN UINT8 Value
+ );
+
+/**
+ Performs an 8-bit or on the register
+
+ @param[in] This Pointer to REGISTER_ACCESS
+ @param[in] Offset Offset of the register in the register bank
+ @param[in] OrData Data with which register should be OR-ed
+
+ @return The 8-bit register value written to register
+**/
+typedef
+UINT8
+(*REG_OR8) (
+ IN REGISTER_ACCESS *This,
+ IN UINT32 Offset,
+ IN UINT8 OrData
+ );
+
+/**
+ Performs an 8-bit and on the register
+
+ @param[in] This Pointer to REGISTER_ACCESS
+ @param[in] Offset Offset of the register in the register bank
+ @param[in] AndData Data with which register should be AND-ed
+
+ @return The 8-bit register value written to register
+**/
+typedef
+UINT8
+(*REG_AND8) (
+ IN REGISTER_ACCESS *This,
+ IN UINT32 Offset,
+ IN UINT8 AndData
+ );
+
+/**
+ Performs an 8-bit and then or on the register
+
+ @param[in] This Pointer to REGISTER_ACCESS
+ @param[in] Offset Offset of the register in the register bank
+ @param[in] AndData Data with which register should be AND-ed
+ @param[in] OrData Data with which register should be OR-ed
+
+ @return The 8-bit register value written to register
+**/
+typedef
+UINT8
+(*REG_AND_THEN_OR8) (
+ IN REGISTER_ACCESS *This,
+ IN UINT32 Offset,
+ IN UINT8 AndData,
+ IN UINT8 OrData
+ );
+
+/**
+ Reads a 16-bit register
+
+ @param[in] This Pointer to REGISTER_ACCESS
+ @param[in] Offset Offset of the register in the register bank
+
+ @return The 16-bit register value specified by Offset
+**/
+typedef
+UINT16
+(*REG_READ16) (
+ IN REGISTER_ACCESS *This,
+ IN UINT32 Offset
+ );
+
+/**
+ Writes a 16-bit register
+
+ @param[in] This Pointer to REGISTER_ACCESS
+ @param[in] Offset Offset of the register in the register bank
+ @param[in] Value Value to write to register
+
+ @return The 16-bit register value written to register
+**/
+typedef
+UINT16
+(*REG_WRITE16) (
+ IN REGISTER_ACCESS *This,
+ IN UINT32 Offset,
+ IN UINT16 Value
+ );
+
+/**
+ Performs a 16-bit or on the register
+
+ @param[in] This Pointer to REGISTER_ACCESS
+ @param[in] Offset Offset of the register in the register bank
+ @param[in] OrData Data with which register should be OR-ed
+
+ @return The 16-bit register value written to register
+**/
+typedef
+UINT16
+(*REG_OR16) (
+ IN REGISTER_ACCESS *This,
+ IN UINT32 Offset,
+ IN UINT16 OrData
+ );
+
+/**
+ Performs a 16-bit and on the register
+
+ @param[in] This Pointer to REGISTER_ACCESS
+ @param[in] Offset Offset of the register in the register bank
+ @param[in] AndData Data with which register should be AND-ed
+
+ @return The 16-bit register value written to register
+**/
+typedef
+UINT16
+(*REG_AND16) (
+ IN REGISTER_ACCESS *This,
+ IN UINT32 Offset,
+ IN UINT16 AndData
+ );
+
+/**
+ Performs a 16-bit and then or on the register
+
+ @param[in] This Pointer to REGISTER_ACCESS
+ @param[in] Offset Offset of the register in the register bank
+ @param[in] AndData Data with which register should be AND-ed
+ @param[in] OrData Data with which register should be OR-ed
+
+ @return The 16-bit register value written to register
+**/
+typedef
+UINT16
+(*REG_AND_THEN_OR16) (
+ IN REGISTER_ACCESS *This,
+ IN UINT32 Offset,
+ IN UINT16 AndData,
+ IN UINT16 OrData
+ );
+
+/**
+ Reads a 32-bit register
+
+ @param[in] This Pointer to REGISTER_ACCESS
+ @param[in] Offset Offset of the register in the register bank
+
+ @return The 32-bit register value specified by Offset
+**/
+typedef
+UINT32
+(*REG_READ32) (
+ IN REGISTER_ACCESS *This,
+ IN UINT32 Offset
+ );
+
+/**
+ Writes a 32-bit register
+
+ @param[in] This Pointer to REGISTER_ACCESS
+ @param[in] Offset Offset of the register in the register bank
+ @param[in] Value Value to write to register
+
+ @return The 32-bit register value written to register
+**/
+typedef
+UINT32
+(*REG_WRITE32) (
+ IN REGISTER_ACCESS *This,
+ IN UINT32 Offset,
+ IN UINT32 Value
+ );
+
+/**
+ Performs a 32-bit or on the register
+
+ @param[in] This Pointer to REGISTER_ACCESS
+ @param[in] Offset Offset of the register in the register bank
+ @param[in] OrData Data with which register should be OR-ed
+
+ @return The 32-bit register value written to register
+**/
+typedef
+UINT32
+(*REG_OR32) (
+ IN REGISTER_ACCESS *This,
+ IN UINT32 Offset,
+ IN UINT32 OrData
+ );
+
+/**
+ Performs a 32-bit and on the register
+
+ @param[in] This Pointer to REGISTER_ACCESS
+ @param[in] Offset Offset of the register in the register bank
+ @param[in] AndData Data with which register should be AND-ed
+
+ @return The 32-bit register value written to register
+**/
+typedef
+UINT32
+(*REG_AND32) (
+ IN REGISTER_ACCESS *This,
+ IN UINT32 Offset,
+ IN UINT32 AndData
+ );
+
+/**
+ Performs a 32-bit and then or on the register
+
+ @param[in] This Pointer to REGISTER_ACCESS
+ @param[in] Offset Offset of the register in the register bank
+ @param[in] AndData Data with which register should be AND-ed
+ @param[in] OrData Data with which register should be OR-ed
+
+ @return The 32-bit register value written to register
+**/
+typedef
+UINT32
+(*REG_AND_THEN_OR32) (
+ IN REGISTER_ACCESS *This,
+ IN UINT32 Offset,
+ IN UINT32 AndData,
+ IN UINT32 OrData
+ );
+
+struct _REGISTER_ACCESS {
+ REG_READ8 Read8;
+ REG_WRITE8 Write8;
+ REG_OR8 Or8;
+ REG_AND8 And8;
+ REG_AND_THEN_OR8 AndThenOr8;
+
+ REG_READ16 Read16;
+ REG_WRITE16 Write16;
+ REG_OR16 Or16;
+ REG_AND16 And16;
+ REG_AND_THEN_OR16 AndThenOr16;
+
+ REG_READ32 Read32;
+ REG_WRITE32 Write32;
+ REG_OR32 Or32;
+ REG_AND32 And32;
+ REG_AND_THEN_OR32 AndThenOr32;
+};
+
+#endif
--
2.36.1.windows.1
-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#108695): https://edk2.groups.io/g/devel/message/108695
Mute This Topic: https://groups.io/mt/101373953/7686176
Group Owner: devel+owner@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [rebecca@openfw.io]
-=-=-=-=-=-=-=-=-=-=-=-
^ permalink raw reply related [flat|nested] 41+ messages in thread
* Re: [edk2-devel] [PATCH v2 10/10] AlderlakeSiliconPkg: Add Alderlake Product and SiPkg.dec
2023-09-15 4:45 ` [edk2-devel] [PATCH v2 10/10] AlderlakeSiliconPkg: Add Alderlake Product and SiPkg.dec Saloni Kasbekar
@ 2023-09-15 5:43 ` Chaganty, Rangasai V
2023-09-15 13:29 ` Chuang, Rosen
2023-09-15 23:57 ` Nate DeSimone
1 sibling, 1 reply; 41+ messages in thread
From: Chaganty, Rangasai V @ 2023-09-15 5:43 UTC (permalink / raw)
To: Kasbekar, Saloni, devel@edk2.groups.io
Cc: Desimone, Nathaniel L, Chuang, Rosen
Reviewed-by: Sai Chaganty <rangasai.v.chaganty@intel.com>
-----Original Message-----
From: Kasbekar, Saloni <saloni.kasbekar@intel.com>
Sent: Thursday, September 14, 2023 9:46 PM
To: devel@edk2.groups.io
Cc: Kasbekar, Saloni <saloni.kasbekar@intel.com>; Chaganty, Rangasai V <rangasai.v.chaganty@intel.com>; Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>; Chuang, Rosen <rosen.chuang@intel.com>
Subject: [PATCH v2 10/10] AlderlakeSiliconPkg: Add Alderlake Product and SiPkg.dec
Adds the following modules:
- Product/Alderlake/Include
- Product/Alderlake/Library
- Product/Alderlake DSCs
- SiPkg.dec
Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Rosen Chuang <rosen.chuang@intel.com>
Signed-off-by: Saloni Kasbekar <saloni.kasbekar@intel.com>
---
.../Product/Alderlake/Include/Ppi/SiPolicy.h | 55 ++
.../Library/PeiSiPolicyLib/PeiSiPolicyLib.c | 47 ++
.../Library/PeiSiPolicyLib/PeiSiPolicyLib.inf | 47 ++
.../PeiSiPolicyLib/PeiSiPolicyLibPreMem.c | 47 ++
.../PeiSiPolicyLib/PeiSiPolicyLibrary.h | 21 +
.../Product/Alderlake/SiPkgBuildOption.dsc | 122 ++++
.../Product/Alderlake/SiPkgCommonLib.dsc | 36 +
.../Product/Alderlake/SiPkgDxe.dsc | 32 +
.../Product/Alderlake/SiPkgDxeLib.dsc | 23 +
.../Product/Alderlake/SiPkgPeiLib.dsc | 19 +
Silicon/Intel/AlderlakeSiliconPkg/SiPkg.dec | 625 ++++++++++++++++++
11 files changed, 1074 insertions(+)
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/Include/Ppi/SiPolicy.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/Library/PeiSiPolicyLib/PeiSiPolicyLib.c
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/Library/PeiSiPolicyLib/PeiSiPolicyLib.inf
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/Library/PeiSiPolicyLib/PeiSiPolicyLibPreMem.c
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/Library/PeiSiPolicyLib/PeiSiPolicyLibrary.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/SiPkgBuildOption.dsc
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/SiPkgCommonLib.dsc
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/SiPkgDxe.dsc
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/SiPkgDxeLib.dsc
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/SiPkgPeiLib.dsc
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/SiPkg.dec
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/Include/Ppi/SiPolicy.h b/Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/Include/Ppi/SiPolicy.h
new file mode 100644
index 0000000000..703f0221bd
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/Include/Ppi/Si
+++ Policy.h
@@ -0,0 +1,55 @@
+/** @file
+ Silicon Policy PPI is used for specifying platform
+ related Intel silicon information and policy setting.
+ This PPI is consumed by the silicon PEI modules and carried
+ over to silicon DXE modules.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/
+
+#ifndef _SI_POLICY_PPI_H_
+#define _SI_POLICY_PPI_H_
+
+#include <SiPolicyStruct.h>
+#include <PchPolicyCommon.h>
+#include <PchPreMemPolicyCommon.h>
+#include <Uefi.h>
+#include <ConfigBlock/CpuConfig.h>
+#include <ConfigBlock/CpuConfigLibPreMemConfig.h>
+#include <ConfigBlock/CpuSecurityPreMemConfig.h>
+
+#ifndef DISABLED
+#define DISABLED 0
+#endif
+#ifndef ENABLED
+#define ENABLED 1
+#endif
+
+extern EFI_GUID gSiPreMemPolicyPpiGuid; extern EFI_GUID
+gSiPolicyPpiGuid;
+
+
+#include <GraphicsConfig.h>
+
+
+#include <CpuPcieConfigGen3.h>
+#include <CpuPcieConfig.h>
+extern EFI_GUID gCpuPciePeiPreMemConfigGuid; extern EFI_GUID
+gCpuPcieRpConfigGuid;
+
+#include <MemoryConfig.h>
+extern EFI_GUID gMemoryConfigGuid;
+extern EFI_GUID gMemoryConfigNoCrcGuid;
+
+#include <ConfigBlock/SaMiscPeiPreMemConfig.h>
+extern EFI_GUID gSaMiscPeiPreMemConfigGuid;
+
+#include <HostBridgeConfig.h>
+extern EFI_GUID gHostBridgePeiPreMemConfigGuid; extern EFI_GUID
+gHostBridgePeiConfigGuid;
+
+typedef struct _SI_PREMEM_POLICY_STRUCT SI_PREMEM_POLICY_PPI; typedef
+struct _SI_POLICY_STRUCT SI_POLICY_PPI;
+
+#endif // _SI_POLICY_PPI_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/Library/PeiSiPolicyLib/PeiSiPolicyLib.c b/Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/Library/PeiSiPolicyLib/PeiSiPolicyLib.c
new file mode 100644
index 0000000000..886415bdaa
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/Library/PeiSiP
+++ olicyLib/PeiSiPolicyLib.c
@@ -0,0 +1,47 @@
+/** @file
+ This file is PeiSiPolicyLib library creates default settings of RC
+ Policy and installs RC Policy PPI.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/ #include
+"PeiSiPolicyLibrary.h"
+#include <Library/PcdLib.h>
+#include <Library/PchInfoLib.h>
+
+
+/**
+ SiInstallPolicyReadyPpi installs SiPolicyReadyPpi.
+ While installed, RC assumes the Policy is ready and finalized. So
+please update and override
+ any setting before calling this function.
+
+ @retval EFI_SUCCESS The policy is installed.
+ @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer
+**/
+EFI_STATUS
+EFIAPI
+SiInstallPolicyReadyPpi (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+ EFI_PEI_PPI_DESCRIPTOR *SiPolicyReadyPpiDesc;
+
+ SiPolicyReadyPpiDesc = (EFI_PEI_PPI_DESCRIPTOR *) AllocateZeroPool
+ (sizeof (EFI_PEI_PPI_DESCRIPTOR)); if (SiPolicyReadyPpiDesc == NULL) {
+ ASSERT (FALSE);
+ return EFI_OUT_OF_RESOURCES;
+ }
+
+ SiPolicyReadyPpiDesc->Flags = EFI_PEI_PPI_DESCRIPTOR_PPI |
+ EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST;
+ SiPolicyReadyPpiDesc->Guid = &gSiPolicyReadyPpiGuid;
+ SiPolicyReadyPpiDesc->Ppi = NULL;
+
+ //
+ // Install Silicon Policy Ready PPI
+ //
+ Status = PeiServicesInstallPpi (SiPolicyReadyPpiDesc);
+ ASSERT_EFI_ERROR (Status);
+ return Status;
+}
+
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/Library/PeiSiPolicyLib/PeiSiPolicyLib.inf b/Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/Library/PeiSiPolicyLib/PeiSiPolicyLib.inf
new file mode 100644
index 0000000000..7dab1ff510
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/Library/PeiSiP
+++ olicyLib/PeiSiPolicyLib.inf
@@ -0,0 +1,47 @@
+## @file
+# Component description file for the PeiSiPolicyLib library.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+
+[Defines]
+INF_VERSION = 0x00010017
+BASE_NAME = PeiSiPolicyLib
+FILE_GUID = 97584FAE-9299-4202-9889-2D339E4BFA5B
+VERSION_STRING = 1.0
+MODULE_TYPE = PEIM
+LIBRARY_CLASS = SiPolicyLib
+
+
+[LibraryClasses]
+DebugLib
+IoLib
+PeiServicesLib
+BaseMemoryLib
+MemoryAllocationLib
+ConfigBlockLib
+PcdLib
+CpuPlatformLib
+
+[Packages]
+MdePkg/MdePkg.dec
+AlderlakeSiliconPkg/SiPkg.dec
+
+[Sources]
+PeiSiPolicyLib.c
+PeiSiPolicyLibrary.h
+PeiSiPolicyLibPreMem.c
+
+
+[Guids]
+gSiConfigGuid ## CONSUMES
+gSiPreMemConfigGuid ## CONSUMES
+gPciePreMemConfigGuid ## CONSUMES
+
+[Ppis]
+gSiPolicyPpiGuid ## PRODUCES
+gSiPreMemPolicyPpiGuid ## PRODUCES
+gSiPolicyReadyPpiGuid ## CONSUMES
+gSiPreMemPolicyReadyPpiGuid ## CONSUMES
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/Library/PeiSiPolicyLib/PeiSiPolicyLibPreMem.c b/Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/Library/PeiSiPolicyLib/PeiSiPolicyLibPreMem.c
new file mode 100644
index 0000000000..93bffac2b0
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/Library/PeiSiP
+++ olicyLib/PeiSiPolicyLibPreMem.c
@@ -0,0 +1,47 @@
+/** @file
+ This file is PeiSiPolicyLib library creates default settings of RC
+ Policy and installs RC Policy PPI.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/ #include
+"PeiSiPolicyLibrary.h"
+#include <Base.h>
+#include <PciePreMemConfig.h>
+#include <Library/PchInfoLib.h>
+#include <Library/CpuPlatformLib.h>
+
+/**
+ SiPreMemInstallPolicyReadyPpi installs SiPreMemPolicyReadyPpi.
+ While installed, RC assumes the Policy is ready and finalized. So
+please update and override
+ any setting before calling this function.
+
+ @retval EFI_SUCCESS The policy is installed.
+ @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer
+**/
+EFI_STATUS
+EFIAPI
+SiPreMemInstallPolicyReadyPpi (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+ EFI_PEI_PPI_DESCRIPTOR *SiPolicyReadyPreMemPpiDesc;
+
+ SiPolicyReadyPreMemPpiDesc = (EFI_PEI_PPI_DESCRIPTOR *)
+ AllocateZeroPool (sizeof (EFI_PEI_PPI_DESCRIPTOR)); if (SiPolicyReadyPreMemPpiDesc == NULL) {
+ ASSERT (FALSE);
+ return EFI_OUT_OF_RESOURCES;
+ }
+
+ SiPolicyReadyPreMemPpiDesc->Flags = EFI_PEI_PPI_DESCRIPTOR_PPI |
+ EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST;
+ SiPolicyReadyPreMemPpiDesc->Guid = &gSiPreMemPolicyReadyPpiGuid;
+ SiPolicyReadyPreMemPpiDesc->Ppi = NULL;
+
+ //
+ // Install PreMem Silicon Policy Ready PPI
+ //
+ Status = PeiServicesInstallPpi (SiPolicyReadyPreMemPpiDesc);
+ ASSERT_EFI_ERROR (Status);
+ return Status;
+}
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/Library/PeiSiPolicyLib/PeiSiPolicyLibrary.h b/Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/Library/PeiSiPolicyLib/PeiSiPolicyLibrary.h
new file mode 100644
index 0000000000..aac24cf187
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/Library/PeiSiP
+++ olicyLib/PeiSiPolicyLibrary.h
@@ -0,0 +1,21 @@
+/** @file
+ Header file for the PeiSiPolicyLib library.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/ #ifndef
+_PEI_SI_POLICY_LIBRARY_H_ #define _PEI_SI_POLICY_LIBRARY_H_
+
+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/PeiServicesLib.h>
+#include <Library/MemoryAllocationLib.h> #include
+<Library/ConfigBlockLib.h> #include <Ppi/SiPolicy.h> #include
+<Library/SiPolicyLib.h>
+
+
+
+#endif // _PEI_SI_POLICY_LIBRARY_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/SiPkgBuildOption.dsc b/Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/SiPkgBuildOption.dsc
new file mode 100644
index 0000000000..290d6eb885
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/SiPkgBuildOpti
+++ on.dsc
@@ -0,0 +1,122 @@
+## @file
+# Silicon build option configuration file.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+[BuildOptions]
+# Define Build Options both for EDK and EDKII drivers.
+
+# SA
+!if gSiPkgTokenSpaceGuid.PcdAdlLpSupport == TRUE DEFINE
+PCH_BUILD_OPTIONS = -DPCH_ADPP !else DEFINE PCH_BUILD_OPTIONS =
+-DPCH_ADL !endif # # SA # !if gSiPkgTokenSpaceGuid.PcdBdatEnable ==
+TRUE
+ DEFINE BDAT_BUILD_OPTION = -DBDAT_SUPPORT=1 !else
+ DEFINE BDAT_BUILD_OPTION =
+!endif
+
+ DEFINE SLE_BUILD_OPTIONS =
+!if $(TARGET) == RELEASE
+!if gSiPkgTokenSpaceGuid.PcdSiCatalogDebugEnable == TRUE
+ DEFINE DEBUG_BUILD_OPTIONS =
+!else
+ # MDEPKG_NDEBUG is introduced for the intention
+ # of size reduction when compiler optimization is disabled. If
+MDEPKG_NDEBUG is
+ # defined, then debug and assert related macros wrapped by it are the NULL implementations.
+ DEFINE DEBUG_BUILD_OPTIONS = -DMDEPKG_NDEBUG !endif !else
+ DEFINE DEBUG_BUILD_OPTIONS =
+!endif
+
+!if ($(TARGET) == RELEASE) AND
+(gSiPkgTokenSpaceGuid.PcdSiCatalogDebugEnable == TRUE)
+ DEFINE RELEASE_CATALOG_BUILD_OPTIONS = -DRELEASE_CATALOG !else
+ DEFINE RELEASE_CATALOG_BUILD_OPTIONS = !endif
+
+!if gSiPkgTokenSpaceGuid.PcdOptimizeCompilerEnable == FALSE
+ DEFINE OPTIMIZE_DISABLE_OPTIONS = -Od -GL- !else
+ DEFINE OPTIMIZE_DISABLE_OPTIONS =
+!endif
+
+ DEFINE HSLE_BUILD_OPTIONS =
+
+
+DEFINE CPU_FLAGS = -DCPU_ADL
+
+
+DEFINE DSC_SIPKG_FEATURE_BUILD_OPTIONS = $(BDAT_BUILD_OPTION)
+$(DEBUG_BUILD_OPTIONS) DEFINE DSC_SIPKG_FEATURE_BUILD_OPTIONS =
+$(DSC_SIPKG_FEATURE_BUILD_OPTIONS) $(PCH_BUILD_OPTIONS) $(CPU_FLAGS)
+$(HSLE_BUILD_OPTIONS)
+
+!if gSiPkgTokenSpaceGuid.PcdSourceDebugEnable == TRUE
+ *_*_X64_GENFW_FLAGS = --keepexceptiontable !endif
+
+[BuildOptions.Common.EDKII]
+
+#
+# For IA32 Global Build Flag
+#
+ *_*_IA32_CC_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) -D PI_SPECIFICATION_VERSION=0x00010015 -DASF_PEI
+ *_*_IA32_VFRPP_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS)
+ *_*_IA32_APP_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS)
+ *_*_IA32_ASLPP_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS)
+ *_*_IA32_ASLCC_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS)
+
+#
+# For IA32 Specific Build Flag
+#
+CLANGPDB:*_*_IA32_CC_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) -D PI_SPECIFICATION_VERSION=0x00010015 -DASF_PEI -Wno-enum-conversion -Wno-incompatible-pointer-types-discards-qualifiers -Wno-sometimes-uninitialized -Wno-braced-scalar-init -Wno-nonportable-include-path -Wno-misleading-indentation
+GCC: *_*_IA32_PP_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS)
+MSFT: *_*_IA32_ASM_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS)
+MSFT: *_*_IA32_CC_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) $(OPTIMIZE_DISABLE_OPTIONS) -D PI_SPECIFICATION_VERSION=0x00010015 -DASF_PEI /w34668
+MSFT: *_*_IA32_VFRPP_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) $(OPTIMIZE_DISABLE_OPTIONS)
+MSFT: *_*_IA32_APP_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) $(OPTIMIZE_DISABLE_OPTIONS)
+MSFT: *_*_IA32_ASLPP_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) $(OPTIMIZE_DISABLE_OPTIONS)
+MSFT: *_*_IA32_ASLCC_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) $(OPTIMIZE_DISABLE_OPTIONS)
+
+#
+# For X64 Global Build Flag
+#
+ *_*_X64_CC_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) -D PI_SPECIFICATION_VERSION=0x00010015
+ *_*_X64_VFRPP_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS)
+ *_*_X64_APP_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS)
+ *_*_X64_ASLPP_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS)
+ *_*_X64_ASLCC_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS)
+
+#
+# For X64 Specific Build Flag
+#
+CLANGPDB:*_*_X64_CC_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) -D PI_SPECIFICATION_VERSION=0x00010015 -Wno-enum-conversion -Wno-main-return-type -Wno-incompatible-pointer-types -Wno-implicit-function-declaration -Wno-unused-variable -Wno-incompatible-pointer-types-discards-qualifiers -Wno-ignored-pragma-optimize -Wno-bitwise-op-parentheses -Wno-sometimes-uninitialized -Wno-unused-function -Wno-misleading-indentation
+GCC: *_*_X64_PP_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS)
+MSFT: *_*_X64_ASM_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS)
+MSFT: *_*_X64_CC_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) $(OPTIMIZE_DISABLE_OPTIONS) -D PI_SPECIFICATION_VERSION=0x00010015 /w34668
+MSFT: *_*_X64_VFRPP_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) $(OPTIMIZE_DISABLE_OPTIONS)
+MSFT: *_*_X64_APP_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) $(OPTIMIZE_DISABLE_OPTIONS)
+MSFT: *_*_X64_ASLPP_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS)
+MSFT: *_*_X64_ASLCC_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS)
+
+#
+# For Xcode Specific Build Flag
+#
+# Override assembly code build order
+*_XCODE5_*_*_BUILDRULEORDER = nasm S s
+# Align 47bfbd7f8069e523798ef973c8eb0abd5c6b0746 to fix the usage of
+VA_START in undefined way *_XCODE5_*_CC_FLAGS = -Wno-varargs
+
+# Force PE/COFF sections to be aligned at 4KB boundaries to support
+page level protection of runtime modules [BuildOptions.common.EDKII.DXE_RUNTIME_DRIVER]
+ MSFT: *_*_*_DLINK_FLAGS = /ALIGN:4096
+ GCC: *_GCC*_*_DLINK_FLAGS = -z common-page-size=0x1000
+
+
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/SiPkgCommonLib.dsc b/Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/SiPkgCommonLib.dsc
new file mode 100644
index 0000000000..69eca2ecc1
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/SiPkgCommonLib
+++ .dsc
@@ -0,0 +1,36 @@
+## @file
+# Component description file for the AlderLake SiPkg both Pei and Dxe libraries DSC file.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+#
+#
+# FRUs
+#
+!include $(PLATFORM_SI_PACKAGE)/Fru/AdlCpu/CommonLib.dsc
+!include $(PLATFORM_SI_PACKAGE)/Fru/AdlPch/CommonLib.dsc
+#
+# Common
+#
+ PciSegmentLib|$(PLATFORM_SI_PACKAGE)/Library/BasePciSegmentMultiSegLib
+ PciSegmentLib|Pci/BasePciSegmentMultiSegLibPci.inf
+
+#
+# Cpu
+#
+ CpuPlatformLib|$(PLATFORM_SI_PACKAGE)/Cpu/Library/PeiDxeSmmCpuPlatform
+ CpuPlatformLib|Lib/PeiDxeSmmCpuPlatformLib.inf
+
+#
+# Pch
+#
+ PchCycleDecodingLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/PeiDxeSmmPchCyc
+ PchCycleDecodingLib|leDecodingLib/PeiDxeSmmPchCycleDecodingLib.inf
+
+ ResetSystemLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/BaseResetSystemLib/B
+ ResetSystemLib|aseResetSystemLib.inf
+#private
+ GpioPrivateLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Gpio/LibraryPrivate/PeiD
+ GpioPrivateLib|xeSmmGpioPrivateLib/PeiDxeSmmGpioPrivateLibVer2.inf
+ PchPciBdfLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/BasePchPciBdfLib/BaseP
+ PchPciBdfLib|chPciBdfLib.inf
+
+#
+# SA
+#
+ GraphicsInfoLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Graphics/Library/PeiDxe
+ GraphicsInfoLib|SmmGraphicsInfoLib/GraphicsInfoLibVer1.inf
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/SiPkgDxe.dsc b/Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/SiPkgDxe.dsc
new file mode 100644
index 0000000000..97e63dcc96
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/SiPkgDxe.dsc
@@ -0,0 +1,32 @@
+## @file
+# Component description file for the AlderLake SiPkg DXE drivers.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+#
+# FRUs
+#
+!include $(PLATFORM_SI_PACKAGE)/Fru/AdlPch/Dxe.dsc
+#
+# Common
+#
+
+#
+# Pch
+#
+ $(PLATFORM_SI_PACKAGE)/Pch/SmmControl/RuntimeDxe/SmmControl.inf
+
+ $(PLATFORM_SI_PACKAGE)/Pch/PchSmiDispatcher/Smm/PchSmiDispatcher.inf{
+ <LibraryClasses>
+
+ SmiHandlerProfileLib|MdePkg/Library/SmiHandlerProfileLibNull/SmiHandle
+ rProfileLibNull.inf
+ }
+
+#
+# SystemAgent
+#
+ $(PLATFORM_SI_PACKAGE)/SystemAgent/SaInit/Dxe/SaInitDxe.inf
+
+
+
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/SiPkgDxeLib.dsc b/Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/SiPkgDxeLib.dsc
new file mode 100644
index 0000000000..37876cbfc4
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/SiPkgDxeLib.ds
+++ c
@@ -0,0 +1,23 @@
+# @file
+# Component description file for the AlderLake SiPkg DXE libraries.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+#
+# FRUs
+#
+!include $(PLATFORM_SI_PACKAGE)/Fru/AdlCpu/DxeLib.dsc
+!include $(PLATFORM_SI_PACKAGE)/Fru/AdlPch/DxeLib.dsc
+
+#
+# Common
+#
+ AslUpdateLib|IntelSiliconPkg/Library/DxeAslUpdateLib/DxeAslUpdateLib.i
+ AslUpdateLib|nf
+ SiConfigBlockLib|$(PLATFORM_SI_PACKAGE)/Library/BaseSiConfigBlockLib/B
+ SiConfigBlockLib|aseSiConfigBlockLib.inf
+
+#
+# SystemAgent
+#
+ DxeSaPolicyLib|$(PLATFORM_SI_PACKAGE)/SystemAgent/Library/DxeSaPolicyL
+ DxeSaPolicyLib|ib/DxeSaPolicyLib.inf
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/SiPkgPeiLib.dsc b/Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/SiPkgPeiLib.dsc
new file mode 100644
index 0000000000..21e6ff3851
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/SiPkgPeiLib.ds
+++ c
@@ -0,0 +1,19 @@
+## @file
+# Component description file for the AlderLake SiPkg PEI libraries.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+#
+# FRUs
+#
+!include $(PLATFORM_SI_PACKAGE)/Fru/AdlPch/PeiLib.dsc
+
+
+ SiPolicyLib|$(PLATFORM_SI_PACKAGE)/Product/Alderlake/Library/PeiSiPoli
+ SiPolicyLib|cyLib/PeiSiPolicyLib.inf
+ SiConfigBlockLib|$(PLATFORM_SI_PACKAGE)/Library/BaseSiConfigBlockLib/B
+ SiConfigBlockLib|aseSiConfigBlockLib.inf
+
+
+
+
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/SiPkg.dec b/Silicon/Intel/AlderlakeSiliconPkg/SiPkg.dec
new file mode 100644
index 0000000000..ce9cfe599a
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/SiPkg.dec
@@ -0,0 +1,625 @@
+## @file
+# Component description file for the Silicon Reference Code.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+
+[Defines]
+DEC_SPECIFICATION = 0x00010017
+PACKAGE_NAME = SiPkg
+PACKAGE_VERSION = 0.1
+PACKAGE_GUID = F245E276-44A0-46b3-AEB5-9898BBCF008D
+
+[Includes.Common.Private]
+
+#
+# AlderLake Fru
+#
+Fru/AdlCpu/IncludePrivate
+Fru/AdlPch/IncludePrivate
+
+##
+# IpBlock IncludePrivate
+#
+IpBlock/Pmc/IncludePrivate
+IpBlock/Graphics/IncludePrivate
+IpBlock/PchDmi/IncludePrivate
+IpBlock/P2sb/IncludePrivate
+IpBlock/Spi/IncludePrivate
+IpBlock/Gpio/IncludePrivate
+IpBlock/HostBridge/IncludePrivate
+
+# Cpu
+Cpu/IncludePrivate
+
+IncludePrivate
+
+[Includes]
+Product/Alderlake/Include
+#
+# AlderLake
+#
+Fru/AdlCpu/Include
+Fru/AdlPch/Include
+
+
+# CPU PCIe
+IpBlock/CpuPcieRp/Include
+
+#
+# - Memory
+Include/ConfigBlock/Memory/Ver2
+#
+# - Graphics
+Include/ConfigBlock/Graphics/Gen12
+IpBlock/Graphics/Include
+
+#
+# - CPU PCIe
+Include/ConfigBlock/CpuPcieRp/Gen4
+
+#
+# HostBridge
+#
+Include/ConfigBlock/HostBridge/Ver1
+
+Include
+#
+# SystemAgent
+#
+SystemAgent/Include
+Include/ConfigBlock/PcieRp
+Include/ConfigBlock/Vmd
+Include/ConfigBlock/CpuPcieRp/Gen4
+Include/ConfigBlock/CpuPcieRp/Gen3
+
+#
+# Cpu
+#
+Cpu/Include
+
+
+#
+# Pch
+#
+Pch/Include
+Include/ConfigBlock/Espi
+Include/ConfigBlock/Smbus
+Include/ConfigBlock/Pmc
+Include/ConfigBlock/PchDmi
+Include/ConfigBlock/Wdt
+Include/ConfigBlock/PcieRp/PchPcieRp
+Include/ConfigBlock/PcieRp
+Include/ConfigBlock/SerialIo
+
+[Guids.common.Private]
+#
+# PCH
+#
+gGpioLibUnlockHobGuid = { 0xA7892E49, 0x0F9F, 0x4166, { 0xB8, 0xD6, 0x8A, 0x9B, 0xD9, 0x8B, 0x17, 0x38 }}
+
+[Guids]
+gSmbiosProcessorInfoHobGuid = {0xe6d73d92, 0xff56, 0x4146, {0xaf, 0xac, 0x1c, 0x18, 0x81, 0x7d, 0x68, 0x71}}
+gSmbiosCacheInfoHobGuid = {0xd805b74e, 0x1460, 0x4755, {0xbb, 0x36, 0x1e, 0x8c, 0x8a, 0xd6, 0x78, 0xd7}}
+
+##
+## MdeModulePkg
+##
+gEfiMemoryTypeInformationGuid = {0x4c19049f, 0x4137, 0x4dd3, {0x9c,
+0x10, 0x8b, 0x97, 0xa8, 0x3f, 0xfd, 0xfa}} gEfiCapsuleVendorGuid =
+{0x711c703f, 0xc285, 0x4b10, {0xa3, 0xb0, 0x36, 0xec, 0xbd, 0x3c, 0x8b,
+0xe2}} gEfiConsoleOutDeviceGuid = { 0xd3b36f2c, 0xd551, 0x11d4, { 0x9a,
+0x46, 0x0, 0x90, 0x27, 0x3f, 0xc1, 0x4d}} ## ## Common ## ##
+Include/ConfigBlock/SiConfig.h gSiConfigGuid = {0x4ed6d282, 0x22f3,
+0x4fe1, {0xa6, 0x61, 0x6, 0x1a, 0x97, 0x38, 0x59, 0xd8}} ##
+gSiPreMemConfigGuid = {0xb94c004c, 0xa0ab, 0x40f0, {0x9b, 0x61, 0x0b,
+0x25, 0x88, 0xbe, 0xfd, 0xc6}} ## ## gPciePreMemConfigGuid =
+{0xd0f9c2a9, 0x7332, 0x4733, {0x8d, 0xb1, 0x98, 0x79, 0x27, 0x60, 0xda,
+0xe6}} ## gSiPkgTokenSpaceGuid = {0x977c97c1, 0x47e1, 0x4b6b, {0x96,
+0x69, 0x43, 0x66, 0x99, 0xcb, 0xe4, 0x5b}}
+
+gSiConfigHobGuid = {0xb3903068, 0x7482, 0x4424, {0xba, 0x4b, 0x40,
+0x5f, 0x8f, 0xd7, 0x65, 0x4e}}
+
+##
+##
+## SystemAgent
+##
+gSaDataHobGuid = {0xe07d0bda, 0xbf90, 0x46a9, { 0xb0, 0x0e, 0xb2,
+0xc4, 0x4a, 0x0e, 0xd6, 0xd0}} gSaConfigHobGuid = {0x762fa2e6, 0xea3b,
+0x41c8, { 0x8c, 0x52, 0x63, 0x76, 0x6d, 0x70, 0x39, 0xe0}}
+gSaMiscPeiPreMemConfigGuid = {0x4a525577, 0x3469, 0x4f11, { 0x99,
+0xcf, 0xfb, 0xcd, 0x5e, 0xf1, 0x84, 0xe4}} gCpuPciePeiPreMemConfigGuid = { 0x81baf3c9, 0xf295, 0x4572, { 0x8b, 0x21, 0x79, 0x3f, 0xa3, 0x1b, 0xa5, 0xdb}} gVmdPeiConfigGuid = { 0x79b52c74, 0xb9ba, 0x4f36, {0xa2, 0x40, 0xf2, 0x41, 0x0d, 0x20, 0x84, 0x8a}}
+gVmdInfoHobGuid = { 0xccd0306e, 0x7fa1, 0x4df5, {0x99, 0x99, 0xc1, 0xf8, 0x9a, 0x1d, 0x1b, 0xa9}}
+gMemoryConfigGuid = { 0x26cf084c, 0xc9db, 0x41bb, { 0x92, 0xc6, 0xd1,
+0x97, 0xb8, 0xa1, 0xe4, 0xbf}} gMemoryConfigNoCrcGuid = { 0xc56c73d0,
+0x1cdb, 0x4c0c, { 0xa9, 0x57, 0xea, 0x62, 0xa9, 0xe6, 0xf5, 0x0c}}
+gMemoryDxeConfigGuid = {0xa5c7dda8, 0x686b, 0x404f, {0x86, 0x40,
+0xf8, 0x2, 0xd, 0x84, 0x4c, 0x94}} gCpuPcieRpPrememConfigGuid = {
+0x41aef892, 0xc800, 0x4ac0, {0xa9, 0x30, 0x84, 0xac, 0x47, 0xca, 0xca, 0x7e}} gCpuPcieRpConfigGuid = { 0x9749a5fb, 0x9130, 0x44f0, {0x8f, 0x61, 0xdb, 0xff, 0x8e, 0xf2, 0xca, 0xc7}} ## IntelFsp2Pkg/IntelFsp2Pkg.dec gSiMemoryS3DataGuid is the same as gFspNonVolatileStorageHobGuid
+gSiMemoryS3DataGuid = { 0x721acf02, 0x4d77, 0x4c2a, { 0xb3, 0xdc, 0x27, 0x0b, 0x7b, 0xa9, 0xe4, 0xb0 } }
+gSiMemoryInfoDataGuid = { 0x9b2071d4, 0xb054, 0x4e0c, { 0x8d, 0x09, 0x11, 0xcf, 0x8b, 0x9f, 0x03, 0x23 } }
+gSiMemoryPlatformDataGuid = { 0x6210d62f, 0x418d, 0x4999, { 0xa2, 0x45,
+0x22, 0x10, 0x0a, 0x5d, 0xea, 0x44 } } gSaPciePeiConfigGuid = {
+0xdaa929a9, 0x5ec9, 0x486a, { 0xb0, 0xf7, 0x82, 0x3a, 0x55, 0xc7, 0xb5,
+0xb3}} gSaPciePeiPreMemConfigGuid = { 0xfc5e01a3, 0x69f6, 0x4e35, {
+0x9f, 0xcf, 0x6, 0x68, 0x7b, 0xab, 0x31, 0xd7}}
+
+#
+# Host Bridge
+#
+gHostBridgePeiPreMemConfigGuid = {0xbdef6805, 0x2080, 0x44ad, { 0x93,
+0x2e, 0x00, 0x04, 0xf5, 0x2c, 0xb7, 0xa1}} gHostBridgePeiConfigGuid =
+{0x3b6d998e, 0x8b6e, 0x4f53, { 0xbe, 0x41, 0x7, 0x41, 0x95, 0x53, 0x8a,
+0xaf}} gHostBridgeDataHobGuid = {0x3b682d57, 0xd402, 0x40a6, { 0xb1,
+0x34, 0xa0, 0xc4, 0xf6, 0x31, 0x1d, 0x9}}
+
+#
+# Graphics
+#
+gGraphicsPeiConfigGuid = {0x04249ac0, 0x0088, 0x439f, { 0xa7, 0x4e,
+0xa7, 0x04, 0x2a, 0x06, 0x2f, 0x5d}} gGraphicsDxeConfigGuid =
+{0x34d93161, 0xf78e, 0x4915, {0xad, 0xc4, 0xdb, 0x67, 0x16, 0x42, 0x39,
+0x24}}
+
+## Include/SsaCommonConfig.h
+gSsaPostcodeHookGuid = {0xADF0A27B, 0x61A6, 0x4F18, {0x9E, 0xAC, 0x46,
+0x87, 0xE7, 0x9E, 0x6F, 0xBB}} gSsaBiosVariablesGuid = {0x43eeffe8,
+0xa978, 0x41dc, {0x9d, 0xb6, 0x54, 0xc4, 0x27, 0xf2, 0x7e, 0x2a}}
+gSsaBiosResultsGuid = {0x8f4e928, 0xf5f, 0x46d4, {0x84, 0x10, 0x47,
+0x9f, 0xda, 0x27, 0x9d, 0xb6}} gHobUsageDataGuid = {0xc764a821, 0xec41,
+0x450d, { 0x9c, 0x99, 0x27, 0x20, 0xfc, 0x7c, 0xe1, 0xf6 }}
+
+##
+## Cpu
+##
+gCpuAcpiTableStorageGuid = {0xc38fb0e2, 0x0c43, 0x49c9, {0xb5, 0x44,
+0x9b, 0x17, 0xaa, 0x4d, 0xcb, 0xa3}} gCpuSecurityPreMemConfigGuid =
+{0xfd5c346, 0x8260, 0x4067, {0x94, 0x69, 0xcf, 0x91, 0x68, 0xa3, 0x42,
+0x90}} gCpuConfigLibPreMemConfigGuid = {0xfc1c0ec2, 0xc6b4, 0x4f05,
+{0xbb, 0x85, 0xc8, 0x0, 0x8d, 0x5b, 0x4a, 0xb7}} gCpuConfigGuid =
+{0x48c3aac9, 0xd66c, 0x42e4, {0x9b, 0x1d, 0x39, 0x4, 0x5f, 0x46, 0x53,
+0x41}} gCpuDataHobGuid = {0x1eec629f, 0xf3cf, 0x4b02, { 0xa9, 0xa5,
+0x27, 0xa2, 0x33, 0x20, 0xbe, 0x5d}} ## ## Me ## gPciImrHobGuid =
+{0x49b1eac3, 0x0cd6, 0x451e, {0x96, 0x30, 0x92, 0x4b, 0xc2, 0x69, 0x35,
+0x86}} gTpm2AcpiTableStorageGuid = {0x7d279373, 0xeecc, 0x4d4f,
+{0xae, 0x2f, 0xce, 0xc4, 0xb7, 0x06, 0xb0, 0x6a}} gEdkiiTouchPanelGuid
+= {0x91b1d27b, 0xe126, 0x48d1, {0x82, 0x34, 0xd2, 0x8b, 0x81, 0xc8,
+0x83, 0x62}} gMeDidSentHobGuid = {0x4c3d3af1, 0x1720, 0x4c3f, {0xab,
+0x7c, 0x36, 0x50, 0xbb, 0x5b, 0x85, 0x7e}}
+
+##
+## PCH
+##
+gPchGlobalResetGuid = { 0x9db31b4c, 0xf5ef, 0x48bb, { 0x94, 0x2b,
+0x18, 0x1f, 0x7e, 0x3a, 0x3e, 0x40 }}
+
+gPchGeneralPreMemConfigGuid = {0xC65F62FA, 0x52B9, 0x4837, {0x86,
+0xEB, 0x1A, 0xFB, 0xD4, 0xAD, 0xBB, 0x3E}} gWatchDogPreMemConfigGuid =
+{0xFBCE08CC, 0x60F2, 0x4BDF, {0xB7, 0x88, 0x09, 0xBB, 0x81, 0x65, 0x52,
+0x2B}} gPcieRpPreMemConfigGuid = {0x8377AB38, 0xF8B0, 0x476A, { 0x9C,
+0xA1, 0x68, 0xEA, 0x78, 0x57, 0xD8, 0x2A}} gSmbusPreMemConfigGuid =
+{0x77A6E62C, 0x716B, 0x4386, {0x9E, 0x9C, 0x23, 0xA0, 0x2E, 0x13, 0x7B,
+0x3A}} gLpcPreMemConfigGuid = {0xA6E6032F, 0x1E58, 0x407E, {0x9A,
+0xB8, 0xC6, 0x30, 0xC6, 0xC4, 0x11, 0x8E}} gPchDmiPreMemConfigGuid =
+{0x4DA4AA22, 0xB54A, 0x43D7, {0x87, 0xC8, 0xA3, 0xCF, 0x53, 0xE6, 0xC1,
+0x8A}}
+
+gPchGeneralConfigGuid = {0x6ED94C8C, 0x25F7, 0x4686, {0xB2, 0x46,
+0xCA, 0x4D, 0xE2, 0x95, 0x4B, 0x5D}} gPchPcieConfigGuid =
+{0x0A53B507, 0x988B, 0x475C, {0xBF, 0x76, 0x33, 0xDE, 0x10, 0x6D, 0x94,
+0x84}} gPchPcieRpDxeConfigGuid = {0x475530EA, 0xBD72, 0x416F, {0x98,
+0x9F,0x48, 0x70, 0x5F, 0x14, 0x4E, 0xD9}} gIoApicConfigGuid =
+{0x2873D0F1, 0x00F6, 0x40AB, {0xAC, 0x36, 0x9A, 0x68, 0xBA, 0x87, 0x3E,
+0x6C}} gPchDmiConfigGuid = {0xB3A61210, 0x1CD3, 0x4797, {0x8E, 0xE6,
+0xD3, 0x42, 0x9C, 0x4F, 0x17, 0xBD}} gSerialIoConfigGuid =
+{0x6CC06EBF, 0x0D34, 0x4340, {0xBC, 0x16, 0xDA, 0x09, 0xE5, 0x78, 0x3A,
+0xDB}}
+
+##
+## SecurityPkg
+##
+## GUID used to "Tcg2PhysicalPresence" variable and "Tcg2PhysicalPresenceFlags" variable for TPM2 request and response.
+# Include/Guid/Tcg2PhysicalPresenceData.h
+gEfiTcg2PhysicalPresenceGuid = { 0xaeb9c5c1, 0x94f1, 0x4d02, { 0xbf, 0xd9, 0x46, 0x2, 0xdb, 0x2d, 0x3c, 0x54 }}
+
+##
+## FSP
+##
+gFspSiliconFvGuid = { 0x1b5c27fe, 0xf01c, 0x4fbc, { 0xae, 0xae, 0x34, 0x1b, 0x2e, 0x99, 0x2a, 0x17 }}
+gFspTscFrequencyGuid = { 0x0e3b622a, 0xedbb, 0x4e30, { 0x93, 0x60, 0x69, 0x5c, 0xd4, 0xb3, 0x20, 0xc9 }}
+gFspInfoGuid = { 0x067e0f25, 0x374f, 0x47c2, { 0x17, 0x92, 0x86, 0xdc, 0xdb, 0xc4, 0x8a, 0xc9 }}
+
+[Protocols]
+##
+## MdeModulePkg
+##
+gEdkiiSmmExitBootServicesProtocolGuid = { 0x296eb418, 0xc4c8, 0x4e05, {
+0xab, 0x59, 0x39, 0xe8, 0xaf, 0x56, 0xf0, 0xa } }
+
+##
+## SystemAgent
+##
+gIgdOpRegionProtocolGuid = {0x9e67aecf, 0x4fbb, 0x4c84, {0x99, 0xa5, 0x10, 0x73, 0x40, 0x7, 0x6d, 0xb4}}
+gSaPolicyProtocolGuid = {0xc6aa1f27, 0x5597, 0x4802, {0x9f, 0x63, 0xd6, 0x28, 0x36, 0x59, 0x86, 0x35}}
+gGopPolicyProtocolGuid = {0xec2e931b, 0x3281, 0x48a5, {0x81, 0x07, 0xdf, 0x8a, 0x8b, 0xed, 0x3c, 0x5d}}
+
+##
+## PCH
+##
+gPchSpiProtocolGuid = { 0xc7d289, 0x1347, 0x4de0, {0xbf, 0x42, 0xe, 0x26, 0x9d, 0xe, 0xf3, 0x4a}}
+gWdtProtocolGuid = {0xb42b8d12, 0x2acb, 0x499a, {0xa9, 0x20, 0xdd, 0x5b, 0xe6, 0xcf, 0x09, 0xb1}}
+gEfiSmmSmbusProtocolGuid = {0x72e40094, 0x2ee1, 0x497a, {0x8f, 0x33, 0x4c, 0x93, 0x4a, 0x9e, 0x9c, 0x0c}}
+gPchSmmSpiProtocolGuid = {0x56521f06, 0xa62, 0x4822, {0x99, 0x63, 0xdf, 0x1, 0x9d, 0x72, 0xc7, 0xe1}}
+gPchSmmIoTrapControlGuid = {0x514d2afd, 0x2096, 0x4283, {0x9d, 0xa6, 0x70, 0x0c, 0xd2, 0x7d, 0xc7, 0xa5}}
+gPchTcoSmiDispatchProtocolGuid = {0x9e71d609, 0x6d24, 0x47fd, {0xb5, 0x72, 0x61, 0x40, 0xf8, 0xd9, 0xc2, 0xa4}}
+gPchPcieSmiDispatchProtocolGuid = {0x3e7d2b56, 0x3f47, 0x42aa, {0x8f, 0x6b, 0x22, 0xf5, 0x19, 0x81, 0x8d, 0xab}}
+gPchAcpiSmiDispatchProtocolGuid = {0xd52bb262, 0xf022, 0x49ec, {0x86, 0xd2, 0x7a, 0x29, 0x3a, 0x7a, 0x05, 0x4b}}
+gPchSmiDispatchProtocolGuid = {0xE6A81BBF, 0x873D, 0x47FD, {0xB6, 0xBE, 0x61, 0xB3, 0xE5, 0x72, 0x09, 0x93}}
+gPchEspiSmiDispatchProtocolGuid = {0xB3C14FF3, 0xBAE8, 0x456C, {0x86, 0x31, 0x27, 0xFE, 0x0C, 0xEB, 0x34, 0x0C}}
+gPchSmmPeriodicTimerControlGuid = {0x6906E93B, 0x603B, 0x4A0F, {0x86, 0x92, 0x83, 0x20, 0x04, 0xAA, 0xF2, 0xDB}}
+##
+## Silicon Policy
+##
+## Include/Protocol/SiPolicyProtocol.h
+gDxeSiPolicyProtocolGuid = { 0xeca27516, 0x306c, 0x4e28, { 0x8c, 0x94,
+0x4e, 0x52, 0x10, 0x96, 0x69, 0x5e }}
+
+[Ppis.common.Private]
+
+[Ppis]
+##
+## MdeModulePkg
+##
+gEdkiiPlatformSpecificResetFilterPpiGuid = { 0x8c9f4de3, 0x7b90,
+0x47ef, { 0x93, 0x8, 0x28, 0x7c, 0xec, 0xd6, 0x6d, 0xe8 } }
+
+##
+## SecurityPkg
+##
+gPeiTpmInitializationDonePpiGuid = {0xa030d115, 0x54dd, 0x447b, { 0x90,
+0x64, 0xf2, 0x6, 0x88, 0x3d, 0x7c, 0xcc}} ## ## Common ## ##
+Include/Ppi/SiPolicy.h gSiPolicyPpiGuid = {0xaebffa01, 0x7edc,
+0x49ff, {0x8d, 0x88, 0xcb, 0x84, 0x8c, 0x5e, 0x86, 0x70}} ##
+Include/Ppi/SiPolicy.h gSiPreMemPolicyPpiGuid = {0xc133fe57, 0x17c7,
+0x4b09, {0x8b, 0x3c, 0x97, 0xc1, 0x89, 0xd0, 0xab, 0x8d}} ## Silicon
+Initialization PPI is used to export End of Silicon init.
+gEndOfSiInitPpiGuid = {0xE2E3D5D1, 0x8356, 0x4F96, {0x9C, 0x9E, 0x2E, 0xC3, 0x48, 0x1D, 0xEA, 0x88}}
+gEfiEndOfPeiSignal2PpiGuid = {0x22918381, 0xd018, 0x4d7c, {0x9d, 0x62, 0xf5, 0xa5, 0x70, 0x1c, 0x66, 0x80}}
+gFspTempRamExitPpiGuid = {0xbc1cfbdb, 0x7e50, 0x42be, {0xb4, 0x87, 0x22, 0xe0, 0xa9, 0x0c, 0xb0, 0x52}}
+gFspmArchConfigPpiGuid = {0x824d5a3a, 0xaf92, 0x4c0c, {0x9f, 0x19, 0x19, 0x52, 0x6d, 0xca, 0x4a, 0xbb}}
+gSiPreMemDefaultPolicyInitPpiGuid = {0xfec36242, 0xf8d8, 0x4b43,
+{0x87, 0x94, 0x4f, 0x1f, 0x9f, 0x63, 0x8d, 0xdc}}
+gSiPreMemPolicyReadyPpiGuid = {0x85270bef, 0x6984, 0x4375, {0xa6, 0xea, 0xb5, 0xaa, 0x90, 0x6e, 0xdd, 0x4a}} gSiDefaultPolicyInitPpiGuid = {0xf69abf86, 0x4048, 0x44ef, { 0xa8, 0xef, 0x6c, 0x7f, 0x20, 0x4a, 0xc8, 0xda}}
+gSiPolicyReadyPpiGuid = {0xd570de8c, 0xb9c4, 0x4ffa, {0xad, 0xee, 0xa5, 0x82, 0x7c, 0xe3, 0x17, 0x79}}
+gPeiBeforeGraphicsDetectionPpiGuid = {0xa494060d, 0x98c5, 0x4948,
+{0x84, 0x57, 0x74, 0xd7, 0x1a, 0x3d, 0x0e, 0x85}}
+
+##
+## UEFI Variable Support (Override Until BP1.5) ##
+gEdkiiVariableStoragePpiGuid = { 0x90d915c5, 0xe4c1, 0x4da8, {0xa7,
+0x6f, 0x9, 0xe5, 0x78, 0x91, 0x65, 0x48}}
+gEdkiiVariableStorageSelectorPpiGuid = { 0x782546d1, 0x03ab, 0x41e4,
+{0xa0, 0x1d, 0x7a, 0x9b, 0x22, 0xba, 0x2e, 0x1e}}
+gReadOnlyVariablePreMemoryDescriptorPpiGuid = { 0xbe136fc9, 0xc277,
+0x4dd1, {0xbe, 0x42, 0xce, 0xf0, 0x9f, 0xf4, 0x3f, 0x55}}
+gEfiReadyToInstallEndOfPei2PpiGuid = {0xeef72924, 0x2db2, 0x4569, {
+0x86, 0x3f, 0xd4, 0x86, 0xae, 0x7a, 0xe4, 0x12}}
+
+##
+## SystemAgent
+##
+gEnablePeiGraphicsPpiGuid = {0x8e3bb474, 0x545, 0x4902, {0x86, 0xb0,
+0x6c, 0xb5, 0xe2, 0x64, 0xb4, 0xa5}}
+gPeiGraphicsFramebufferReadyPpiGuid = {0x590ad868, 0xb0b1, 0x4d20,
+{0x91, 0xff, 0xc2, 0xa9, 0xd6, 0x88, 0x81, 0x94}}
+gPeiGraphicsPlatformPpiGuid = {0x4eabcd09, 0x43d3, 0x4b4d, {0xb7, 0x3d, 0x43, 0xc8, 0xd9, 0x89, 0x99, 0x05}} ## X Compatibility support PPI gCompatibleMemoryInitPpiGuid = {0xca311f82, 0xf490, 0x4b12, {0x9e, 0xe1, 0x2b, 0x66, 0xa3, 0x6c, 0x3e, 0xa}}
+gVmdInitDonePpiGuid = {0x42a187c8, 0xca0a, 0x4750, {0x82, 0xfd, 0xc9, 0xa0, 0xd5, 0x9, 0xfe, 0xd1}}
+
+##
+## Cpu
+##
+gPeiCachePpiGuid = {0xC153205A, 0xE898, 0x4C24, {0x86, 0x89, 0xA4,
+0xB4, 0xBC, 0xC5, 0xC8, 0xA2}} gPeiTxtMemoryUnlockedPpiGuid =
+{0x38cdd10b, 0x767d, 0x4f6e, {0xa7, 0x44, 0x67, 0xee, 0x1d, 0xfe, 0x2f,
+0xa5}} gPeiTxtReadyToRunMemoryInitPpiGuid = {0x9ecafd30, 0x29e2,
+0x42f6, {0xba, 0xf3, 0x8b, 0x7d, 0xb8, 0xfe, 0x1f, 0x22}}
+gPeiReadyToInstallMpPpiGuid = { 0x1a266768, 0xfd43, 0x4e18, { 0xa8,
+0x8a, 0x35, 0xc7, 0x94, 0xc3, 0x91, 0x0e }}
+
+##
+## PCH
+##
+gWdtPpiGuid = {0xf38d1338, 0xaf7a, 0x4fb6, {0x91, 0xdb, 0x1a, 0x9c,
+0x21, 0x83, 0x57, 0x0d}} gPchSpiPpiGuid = {0xdade7ce3, 0x6971,
+0x4b75, {0x82, 0x5e, 0xe, 0xe0, 0xeb, 0x17, 0x72, 0x2d}}
+gPeiSmbusPolicyPpiGuid = {0x63b6e435, 0x32bc, 0x49c6, {0x81, 0xbd,
+0xb7, 0xa1, 0xa0, 0xfe, 0x1a, 0x6c}} gPchIoExpanderInfoPpiGuid = {
+0xf4a29776, 0x0ff9, 0x4b5c, { 0xb6, 0x9d, 0x88, 0x45, 0x09, 0x9b, 0x8d,
+0xa5 }}
+
+##
+## TCSS
+##
+gTcssPeiInitDonePpiGuid = {0x5ad291b8, 0xace4, 0x416a, {0xb7, 0x50,
+0x7, 0x63, 0x59, 0xfc, 0xc1, 0x5b}}
+
+##
+## ExtendedBiosDecodeReady PPI
+##
+gExtendedBiosDecodeReadyPpiGuid = {0x54b522bc, 0xbef2, 0x419b, {0xa9,
+0x66, 0x7e, 0xc4, 0xf0, 0x15, 0xe8, 0x21}}
+
+##
+## FSP##
+gFsptUpdLocationPpiGuid = { 0xfc4dd4f2, 0x179e, 0x41f8, { 0x9d, 0x6d, 0xfa, 0xd6, 0xf9, 0xd7, 0xb8, 0xb9 }}
+
+[LibraryClasses]
+## @libraryclass
+## Common
+##
+SiPolicyLib|Include/Library/SiPolicyLib.h
+PeiPolicyUpdateLib|Include/Library/PeiSiPolicyUpdateLib.h
+ProcessorTraceMemoryAllocationLib|Include/Library/ProcessorTraceMemoryA
+ProcessorTraceMemoryAllocationLib|llocationLib.h
+PlatformSecLib|Include/Library/SecPlatformLib.h
+SiAssertErrorHandlerLib|Include/Library/SiAssertErrorHandlerLib.h
+SiConfigBlockLib|Include/Library/SiConfigBlockLib.h
+## @libraryclass
+## SampleCode
+##
+## CPU
+##
+CpuPlatformLib|Cpu/Include/Library/CpuPlatformLib.h
+
+
+## @libraryclass
+## Pch
+##
+GpioLib|Include/Library/GpioLib.h
+GpioLib|Include/Library/GpioNativeLib.h
+PchCycleDecodingLib|Pch/Include/Library/PchCycleDecodingLib.h
+EspiLib|Include/Library/EspiLib.h
+PchInfoLib|Pch/Include/Library/PchInfoLib.h
+PchPcieRpLib|Include/Library/PchPcieRpLib.h
+PchPcrLib|Include/Library/PchPcrLib.h
+PchSbiAccessLib|IpBlock/P2sb/IncludePrivate/Library/PchSbiAccessLib.h
+PchPciBdfLib|Pch/Include/Library/PchPciBdfLib.h
+PchRasLib|Pch/Include/Library/PchRasLib.h
+PchRtcLib|Pch/Include/Library/PchRtcLib.h
+ResetSystemLib|Include/Library/ResetSystemLib.h
+## @libraryclass
+## Sa
+##
+DxeSaPolicyLib|SystemAgent/Include/Library/DxeSaPolicyLib.h
+## @libraryclass
+## Fru
+##
+CpuInfoFruLib|Cpu/IncludePrivate/Library/CpuInfoFruLib.h
+## @libraryclass
+## IpBlock
+##
+PmcPrivateLib|IpBlock/Pmc/IncludePrivate/Library/PmcPrivateLib.h
+IehInitLib|IpBlock/Ieh/IncludePrivate/Library/PeiIehInitLib.h
+PeiIehPolicyLib|IpBlock/Ieh/IncludePrivate/Library/PeiIehPolicyLib.h
+DxeGraphicsPolicyLib|IpBlock/Graphics/IncludePrivate/Library/DxeGraphic
+DxeGraphicsPolicyLib|sPolicyLib.h
+DxeIgdOpRegionInitLib|IpBlock/Graphics/IncludePrivate/Library/DxeIgdOpR
+DxeIgdOpRegionInitLib|egionInitLib.h
+PchDmiLib|IpBlock/PchDmi/IncludePrivate/Library/PchDmiLib.h
+P2SbSidebandAccessLib|IpBlock/P2sb/IncludePrivate/Library/P2SbSidebandA
+P2SbSidebandAccessLib|ccessLib.h
+SpiCommonLib|IpBlock/Spi/IncludePrivate/Library/SpiCommonLib.h
+GpioHelpersLib|IpBlock/Gpio/IncludePrivate/Library/GpioHelpersLib.h
+GpioPrivateLib|IpBlock/Gpio/IncludePrivate/Library/GpioPrivateLib.h
+PeiDmiSipInitLib|IpBlock/PcieRp/IncludePrivate/Library/PeiDmiSipInitLib
+PeiDmiSipInitLib|.h
+PeiEnterprisePcieRpInitLib|IpBlock/PcieRp/IncludePrivate/Library/PeiEnt
+PeiEnterprisePcieRpInitLib|erprisePcieRpInitLib.h
+PeiDpInInitLib|IpBlock/Tcss/IncludePrivate/Library/PeiDpInInitLib.h
+CpuPcieRpLib|IpBlock/CpuPcieRp/Include/Library/CpuPcieRpLib.h
+GpioGsxLib|Include/Library/GpioGsxLib.h
+GraphicsInfoLib|Include/Library/GraphicsInfoLib.h
+HeciCommonLib|Include/Library/HeciCommonLib.h
+HeciConfigureLib|Include/Library/HeciConfigureLib.h
+HeciTraceLib|Include/Library/HeciTraceLib.h
+HeciTransportCoreLib|Include/Library/HeciTransportCoreLib.h
+OcPlatformLib|Include/Library/OcPlatformLib.h
+PeiSpsPreMemPolicyLib|Include/Library/PeiSpsPreMemPolicyLib.h
+PmcLib|Include/Library/PmcLib.h
+PmcSsramLib|Include/Library/PmcSsramLib.h
+SpiLib|Include/Library/SpiLib.h
+SpsDxeLib|Include/Library/SpsDxeLib.h
+SpsGetDxeConfigBlockLib|Include/Library/SpsGetDxeConfigBlock.h
+MeGetPeiConfigBlock|Include/Library/MeGetConfigBlock.h
+## @libraryclass
+## Fsp
+##
+FspHelperLib|Fsp/Include/Library/FspHelperLib.h
+FspInfoLib|Fsp/Include/Library/FspInfoLib.h
+FspSerialIoUartDebugHelperLib|Fsp/Include/Library/FspSerialIoUartDebugH
+FspSerialIoUartDebugHelperLib|elperLib.h
+
+
+CpuPcieInfoFruLib|Fru/AdlCpu/Include/Library/CpuPcieInfoFruLib.h
+
+[PcdsFixedAtBuild]
+## From MdeModulePkg.dec
+## Progress Code for S3 Suspend start.
+## PROGRESS_CODE_S3_SUSPEND_START = (EFI_SOFTWARE_SMM_DRIVER | (EFI_OEM_SPECIFIC | 0x00000000)) = 0x03078000
+gSiPkgTokenSpaceGuid.PcdProgressCodeS3SuspendStart|0x03078000|UINT32|0x
+30001032
+## Progress Code for S3 Suspend end.
+## PROGRESS_CODE_S3_SUSPEND_END = (EFI_SOFTWARE_SMM_DRIVER | (EFI_OEM_SPECIFIC | 0x00000001)) = 0x03078001
+gSiPkgTokenSpaceGuid.PcdProgressCodeS3SuspendEnd|0x03078001|UINT32|0x30
+001033
+##
+## PcdNemCodeCacheBase is usally the same as PEI FV Base address, ##
+FLASH_BASE+FLASH_REGION_FV_RECOVERY_OFFSET from PlatformPkg.fdf.
+##
+## Restriction:
+## 1) PcdNemCodeCacheBase - (PcdTemporaryRamBase + PcdTemporaryRamSize)
+>= 4K ## 2) PcdTemporaryRamBase >= 4G - 64M ##
+gSiPkgTokenSpaceGuid.PcdNemCodeCacheBase|0xFFF80000|UINT32|0x20000009
+##
+## NemCodeCacheSize is usally the same as PEI FV Size, ##
+FLASH_REGION_FV_RECOVERY_SIZE from PlatformPkg.fdf.
+##
+## Restriction:
+## 1) PcdNemTotalCacheSize = NemCodeCacheSize + PcdTemporaryRamSize ##
+<= Maximun CPU NEM total size (Code + Data) ## = LLC size - 0.5M ## 2)
+PcdTemporaryRamSize <= Maximum CPU NEM data size ## = MLC size ##
+NOTE: The size restriction may be changed in next generation processor.
+## Please refer to Processor BWG for detail.
+##
+gSiPkgTokenSpaceGuid.PcdBiosAreaBaseAddress|0xFF800000|UINT32|0x1000000
+1
+gSiPkgTokenSpaceGuid.PcdBiosSize|0x00800000|UINT32|0x10000002
+gSiPkgTokenSpaceGuid.PcdTemporaryRamBase|0xfef00000|UINT32|0x00010028
+gSiPkgTokenSpaceGuid.PcdTemporaryRamSize|0x2000|UINT32|0x00010029
+gSiPkgTokenSpaceGuid.PcdTopMemoryCacheSize|0x0|UINT32|0x0001002A
+gSiPkgTokenSpaceGuid.PcdFlashMicrocodeOffset|0x00000060|UINT32|0x300000
+13
+
+gSiPkgTokenSpaceGuid.PcdFspWrapperEnable |FALSE|BOOLEAN|0x3000000F
+
+
+#
+# PCD is using for SOC core boot
+#
+
+#
+# PCD is using for AlderLakeL P/M/S
+# True: ADL-P/M
+# False: ADL-S
+#
+gSiPkgTokenSpaceGuid.PcdAdlLpSupport|TRUE|BOOLEAN|0x30000014
+
+#
+# PCD is using for AlderLakeL S
+#
+gSiPkgTokenSpaceGuid.PcdAdlSSupport|FALSE|BOOLEAN|0x30000015
+
+##
+## PcdEfiGcdAllocateType is using for EFI_GCD_ALLOCATE_TYPE selection
+## value of the struct ## 0x00 EfiGcdAllocateAnySearchBottomUp ##
+0x01 EfiGcdAllocateMaxAddressSearchBottomUp
+## 0x03 EfiGcdAllocateAnySearchTopDown ## 0x04
+EfiGcdAllocateMaxAddressSearchTopDown
+##
+## below value should not using in this situation ## 0x05
+EfiGcdMaxAllocateType : design for max value of struct ## 0x02
+EfiGcdAllocateAddress : design for speccification address allocate ##
+gSiPkgTokenSpaceGuid.PcdEfiGcdAllocateType|0x01|UINT8|0x40000000
+
+
+##
+## Those PCDs are used to control build process.
+##
+gSiPkgTokenSpaceGuid.PcdSmmVariableEnable |TRUE |BOOLEAN|0xF0000002
+gSiPkgTokenSpaceGuid.PcdAcpiEnable |TRUE |BOOLEAN|0xF0000009
+gSiPkgTokenSpaceGuid.PcdSourceDebugEnable |FALSE|BOOLEAN|0xF000000B
+gSiPkgTokenSpaceGuid.PcdTxtEnable |FALSE|BOOLEAN|0xF000000D
+
+gSiPkgTokenSpaceGuid.PcdSmbiosEnable |TRUE |BOOLEAN|0xF0000014
+gSiPkgTokenSpaceGuid.PcdIgdEnable |TRUE |BOOLEAN|0xF000001A
+gSiPkgTokenSpaceGuid.PcdSaDmiEnable |TRUE |BOOLEAN|0xF000001C
+gSiPkgTokenSpaceGuid.PcdBdatEnable |TRUE |BOOLEAN|0xF0000023
+gSiPkgTokenSpaceGuid.PcdOptimizeCompilerEnable |TRUE |BOOLEAN|0xF0000024
+gSiPkgTokenSpaceGuid.PcdPeiDisplayEnable |TRUE |BOOLEAN|0xF0000025
+gSiPkgTokenSpaceGuid.PcdSerialIoUartEnable |TRUE |BOOLEAN|0xF0000033
+gSiPkgTokenSpaceGuid.PcdSiCatalogDebugEnable |FALSE|BOOLEAN|0xF0000037
+
+gSiPkgTokenSpaceGuid.PcdCpuPcieEnable |TRUE |BOOLEAN|0xF0000043
+gSiPkgTokenSpaceGuid.PcdMrcTraceMessageSupported |TRUE |BOOLEAN|0xF0000045
+
+[PcdsDynamic, PcdsPatchableInModule]
+## Default OEM Table ID for ACPI table creation, it is "EDK2 ".
+gSiPkgTokenSpaceGuid.PcdAcpiDefaultOemTableId|0x20202020324B4445|UINT64
+|0x30001035
+
+[PcdsFixedAtBuild, PcdsPatchableInModule] ## This value is used to set
+the base address of PCH devices
+gSiPkgTokenSpaceGuid.PcdSmbusBaseAddress|0x0000EFA0|UINT16|0x00010031
+gSiPkgTokenSpaceGuid.PcdTcoBaseAddress|0x0400|UINT16|0x00010033
+gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress|0x1800|UINT16|0x00010035
+
+##
+## FSP
+##
+## The PCD value here are either dummy or generic for all platforms ##
+Some of them are expected to have different value in platform FSP package DSC.
+##
+## Examples:
+## PcdFspImageIdString, PcdFspVersionRevision, PcdFspVersionBuild, PcdFspVersionMinor
+##
+gSiPkgTokenSpaceGuid.PcdFspImageIdString |0x0|UINT64|0x0001005A
+gSiPkgTokenSpaceGuid.PcdFspVersionRevision |0x00|UINT8|0x0001005C
+gSiPkgTokenSpaceGuid.PcdFspVersionBuild |0x00|UINT8|0x0001005D
+gSiPkgTokenSpaceGuid.PcdFspVersionMinor |0x00|UINT8|0x0001005E
+
+
+## This value is used to set the base address of MCH
+gSiPkgTokenSpaceGuid.PcdMchBaseAddress|0xFEDC0000|UINT64|0x00010030
+
+##
+## Allocate 56 KB [0x2000..0xFFFF] of I/O space for Pci Devices ## If
+PcdPciReservedMemLimit =0 Pci Reserved default MMIO Limit is 0xE0000000 else use PcdPciReservedMemLimit .
+##
+gSiPkgTokenSpaceGuid.PcdPciReservedMemLimit |0x0000 |UINT32|0x00010043
+
+##
+## Default 8MB TSEG for Release build BIOS when IED disabled (Also a
+default) ##
+gSiPkgTokenSpaceGuid.PcdTsegSize|0x00800000|UINT32|0x00010046
+
+##
+## Silicon Reference Code versions
+##
+gSiPkgTokenSpaceGuid.PcdSiliconInitVersionMajor |0x0C|UINT8|0x00010049
+
+##Minor:the program that supported by same core generation.
+gSiPkgTokenSpaceGuid.PcdSiliconInitVersionMinor |0x00|UINT8|0x00010050
+
+##Revision:Weekly build number
+gSiPkgTokenSpaceGuid.PcdSiliconInitVersionRevision|0x82|UINT8|0x0001005
+1
+
+##Build[7:4]:Daily build number.
+##Build[3:0]:Patch build number.
+
+gSiPkgTokenSpaceGuid.PcdSiliconInitVersionBuild |0x30|UINT8|0x00010052
+
+
+
+##
+## This PCD specifies the base address of the HPET timer.
+## The acceptable values are 0xFED00000, 0xFED01000, 0xFED02000, and
+0xFED03000 ##
+gSiPkgTokenSpaceGuid.PcdSiHpetBaseAddress |0xFED00000|UINT32|0x00010057
+##
+## This PCD specifies the base address of the IO APIC.
+## The acceptable values are 0xFECxx000.
+##
+gSiPkgTokenSpaceGuid.PcdSiIoApicBaseAddress
+|0xFEC00000|UINT32|0x00010058
+
+[PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx]
+## ## SerialIo Uart Configuration ##
+gSiPkgTokenSpaceGuid.PcdSerialIoUartDebugEnable |0 |UINT8 |0x00210001 # 0:Disable, 1:Enable and Initialize, 2:Enable without Initializing
+gSiPkgTokenSpaceGuid.PcdSerialIoUartNumber |2 |UINT8 |0x00210002
+gSiPkgTokenSpaceGuid.PcdSerialIoUartMode |2 |UINT8 |0x00210003 # 0:Disabled, 1:Enabled, 2:Hidden, 3:COM, 4:SkipInit
+gSiPkgTokenSpaceGuid.PcdSerialIoUartBaudRate |115200 |UINT32|0x00210004 # 0:Default, Max:6000000
+gSiPkgTokenSpaceGuid.PcdSerialIoUartParity |1 |UINT8 |0x00210008 # 0:DefaultParity, 1:NoParity, 2:EvenParity, 3:OddParity
+gSiPkgTokenSpaceGuid.PcdSerialIoUartDataBits |8 |UINT8 |0x00210009 # 0:Default, 5,6,7,8
+gSiPkgTokenSpaceGuid.PcdSerialIoUartStopBits |1 |UINT8 |0x0021000A # 0:DefaultStopBits, 1:OneStopBit, 2:OneFiveStopBits, 3:TwoStopBits
+gSiPkgTokenSpaceGuid.PcdSerialIoUartAutoFlow |0 |UINT8 |0x0021000B # 0:No HW flow control, Only RX/TX Enabled; 1:HW Flow Control On, Rts/Cts lines enabled;
+gSiPkgTokenSpaceGuid.PcdSerialIoUartRxPinMux |0x0 |UINT32|0x0021000C # Pin muxing config for UART Rx pin
+gSiPkgTokenSpaceGuid.PcdSerialIoUartTxPinMux |0x0 |UINT32|0x00210010 # Pin muxing config for UART Tx pin
+gSiPkgTokenSpaceGuid.PcdSerialIoUartRtsPinMux |0x0 |UINT32|0x00210014 # Pin muxing config for UART Rts pin
+gSiPkgTokenSpaceGuid.PcdSerialIoUartCtsPinMux |0x0 |UINT32|0x00210018 # Pin muxing config for UART Cts pin
+gSiPkgTokenSpaceGuid.PcdSerialIoUartDebugMmioBase |0xFE036000
+|UINT32|0x0021001C # PcdSerialIoUartMode = Enabled, need to assign MMIO
+Resource in SEC/PEI Phase
+
+gSiPkgTokenSpaceGuid.PcdLpcUartDebugEnable |0x1 |UINT8 |0x00210026 # 0:Disable, 1:Enable
+gSiPkgTokenSpaceGuid.PcdDebugInterfaceFlags |0x12 |UINT8 |0x00210027 # BIT0-RAM, BIT1-UART, BIT3-USB3, BIT4-Serial IO, BIT5-TraceHub, BIT2 - Not used.
+gSiPkgTokenSpaceGuid.PcdSerialDebugLevel |0x3 |UINT8 |0x00210028 # {0:Disable, 1:Error Only, 2:Error and Warnings, 3:Load Error Warnings and Info, 4:Load Error Warnings and Info, 5:Load Error Warnings Info and Verbose
+gSiPkgTokenSpaceGuid.PcdIsaSerialUartBase |0x0 |UINT8 |0x00210029 # 0:0x3F8, 1:0x2F8
+
+
+##
+## SerialIo 2nd Uart Configuration
+##
+gSiPkgTokenSpaceGuid.PcdSerialIo2ndUartEnable |0 |UINT8 |0x0021002A # 0:Disable, 1:Enable and Initialize, 2:Enable without Initializing
+gSiPkgTokenSpaceGuid.PcdSerialIo2ndUartNumber |2 |UINT8 |0x0021002B
+gSiPkgTokenSpaceGuid.PcdSerialIo2ndUartMode |2 |UINT8 |0x0021002C # 0:Disabled, 1:Enabled, 2:Hidden, 3:COM, 4:SkipInit
+gSiPkgTokenSpaceGuid.PcdSerialIo2ndUartBaudRate |115200 |UINT32|0x0021002D # 0:Default, Max:6000000
+gSiPkgTokenSpaceGuid.PcdSerialIo2ndUartParity |1 |UINT8 |0x00210031 # 0:DefaultParity, 1:NoParity, 2:EvenParity, 3:OddParity
+gSiPkgTokenSpaceGuid.PcdSerialIo2ndUartDataBits |8 |UINT8 |0x00210032 # 0:Default, 5,6,7,8
+gSiPkgTokenSpaceGuid.PcdSerialIo2ndUartStopBits |1 |UINT8 |0x00210033 # 0:DefaultStopBits, 1:OneStopBit, 2:OneFiveStopBits, 3:TwoStopBits
+gSiPkgTokenSpaceGuid.PcdSerialIo2ndUartAutoFlow |0 |UINT8 |0x00210034 # 0:No HW flow control, Only RX/TX Enabled; 1:HW Flow Control On, Rts/Cts lines enabled;
+gSiPkgTokenSpaceGuid.PcdSerialIo2ndUartRxPinMux |0x0 |UINT32|0x00210035 # Pin muxing config for UART Rx pin
+gSiPkgTokenSpaceGuid.PcdSerialIo2ndUartTxPinMux |0x0 |UINT32|0x00210039 # Pin muxing config for UART Tx pin
+gSiPkgTokenSpaceGuid.PcdSerialIo2ndUartRtsPinMux |0x0 |UINT32|0x0021003D # Pin muxing config for UART Rts pin
+gSiPkgTokenSpaceGuid.PcdSerialIo2ndUartCtsPinMux |0x0 |UINT32|0x00210041 # Pin muxing config for UART Cts pin
+gSiPkgTokenSpaceGuid.PcdSerialIo2ndUartMmioBase |0xFE034000
+|UINT32|0x00210045 # PcdSerialIoUartMode = Enabled, need to assign MMIO
+Resource in SEC/PEI Phase
+
+##
+## PCI Express MMIO region length
+## Valid settings: 0x20000000/512MB, 0x10000000/256MB, 0x8000000/128MB,
+0x4000000/64MB ##
+gSiPkgTokenSpaceGuid.PcdPciExpressRegionLength|0x10000000|UINT32|0x0020
+0001
+##
+## Typically this should be the same with gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress.
+## This PCD is added for supporting different PCD type in different phases.
+##
+gSiPkgTokenSpaceGuid.PcdSiPciExpressBaseAddress
+|0xC0000000|UINT64|0x00200002 ## ## PCI Express MMIO temporary region
+length in SEC phase.
+## Valid settings: 0x20000000/512MB, 0x10000000/256MB, 0x8000000/128MB,
+0x4000000/64MB ##
+gSiPkgTokenSpaceGuid.PcdTemporaryPciExpressRegionLength|0x10000000|UINT
+32|0x00200005
--
2.36.1.windows.1
-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#108696): https://edk2.groups.io/g/devel/message/108696
Mute This Topic: https://groups.io/mt/101373955/7686176
Group Owner: devel+owner@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [rebecca@openfw.io]
-=-=-=-=-=-=-=-=-=-=-=-
^ permalink raw reply related [flat|nested] 41+ messages in thread
* Re: [edk2-devel] [PATCH v2 01/10] AlderlakeSiliconPkg/IpBlock: Add CpuPcieRp, Espi, Gpio components
2023-09-15 5:42 ` [edk2-devel] [PATCH v2 01/10] AlderlakeSiliconPkg/IpBlock: Add CpuPcieRp, Espi, Gpio components Chaganty, Rangasai V
@ 2023-09-15 13:27 ` Chuang, Rosen
0 siblings, 0 replies; 41+ messages in thread
From: Chuang, Rosen @ 2023-09-15 13:27 UTC (permalink / raw)
To: Chaganty, Rangasai V, Kasbekar, Saloni, devel@edk2.groups.io
Cc: Desimone, Nathaniel L
Reviewed-by: Rosen Chuang <rosen.chuang@intel.com>
-----Original Message-----
From: Chaganty, Rangasai V <rangasai.v.chaganty@intel.com>
Sent: Friday, September 15, 2023 1:42 PM
To: Kasbekar, Saloni <saloni.kasbekar@intel.com>; devel@edk2.groups.io
Cc: Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>; Chuang, Rosen <rosen.chuang@intel.com>
Subject: RE: [PATCH v2 01/10] AlderlakeSiliconPkg/IpBlock: Add CpuPcieRp, Espi, Gpio components
Reviewed-by: Sai Chaganty <rangasai.v.chaganty@intel.com>
-----Original Message-----
From: Kasbekar, Saloni <saloni.kasbekar@intel.com>
Sent: Thursday, September 14, 2023 9:46 PM
To: devel@edk2.groups.io
Cc: Kasbekar, Saloni <saloni.kasbekar@intel.com>; Chaganty, Rangasai V <rangasai.v.chaganty@intel.com>; Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>; Chuang, Rosen <rosen.chuang@intel.com>
Subject: [PATCH v2 01/10] AlderlakeSiliconPkg/IpBlock: Add CpuPcieRp, Espi, Gpio components
Adds the following modules:
- IpBlock/CpuPcieRp/Include
- IpBlock/Espi/Library
- IpBlock/Gpio/IncludePrivate
- IpBlock/Gpio/Library
- IpBlock/Gpio/LibraryPrivate
Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Rosen Chuang <rosen.chuang@intel.com>
Signed-off-by: Saloni Kasbekar <saloni.kasbekar@intel.com>
---
.../IpBlock/CpuPcieRp/Include/CpuPcieInfo.h | 25 +
.../Espi/Library/PeiDxeSmmEspiLib/EspiLib.c | 58 ++
.../PeiDxeSmmEspiLib/PeiDxeSmmEspiLib.inf | 38 ++
.../IncludePrivate/Library/GpioHelpersLib.h | 50 ++
.../IncludePrivate/Library/GpioNativePads.h | 245 ++++++++
.../IncludePrivate/Library/GpioPrivateLib.h | 350 +++++++++++
.../Gpio/Library/PeiDxeSmmGpioLib/GpioInit.c | 546 ++++++++++++++++++
.../Gpio/Library/PeiDxeSmmGpioLib/GpioLib.c | 522 +++++++++++++++++
.../Library/PeiDxeSmmGpioLib/GpioLibrary.h | 29 +
.../Library/PeiDxeSmmGpioLib/GpioNativeLib.c | 177 ++++++
.../PeiDxeSmmGpioLib/PeiDxeSmmGpioLib.inf | 44 ++
.../BaseGpioHelpersLibNull.c | 51 ++
.../BaseGpioHelpersLibNull.inf | 25 +
.../GpioNativePrivateLibInternal.h | 48 ++
.../PeiDxeSmmGpioPrivateLib/GpioPrivateLib.c | 267 +++++++++
.../GpioPrivateLibPch.c | 172 ++++++
.../GpioPrivateLibVer2.c | 81 +++
.../PeiDxeSmmGpioPrivateLibVer2.inf | 40 ++
.../PeiGpioHelpersLib/PeiGpioHelpersLib.c | 218 +++++++
.../PeiGpioHelpersLib/PeiGpioHelpersLib.inf | 46 ++
20 files changed, 3032 insertions(+)
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/CpuPcieRp/Include/CpuPcieInfo.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Espi/Library/PeiDxeSmmEspiLib/EspiLib.c
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Espi/Library/PeiDxeSmmEspiLib/PeiDxeSmmEspiLib.inf
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/IncludePrivate/Library/GpioHelpersLib.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/IncludePrivate/Library/GpioNativePads.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/IncludePrivate/Library/GpioPrivateLib.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/Library/PeiDxeSmmGpioLib/GpioInit.c
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/Library/PeiDxeSmmGpioLib/GpioLib.c
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/Library/PeiDxeSmmGpioLib/GpioLibrary.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/Library/PeiDxeSmmGpioLib/GpioNativeLib.c
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/Library/PeiDxeSmmGpioLib/PeiDxeSmmGpioLib.inf
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/BaseGpioHelpersLibNull/BaseGpioHelpersLibNull.c
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/BaseGpioHelpersLibNull/BaseGpioHelpersLibNull.inf
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiDxeSmmGpioPrivateLib/GpioNativePrivateLibInternal.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiDxeSmmGpioPrivateLib/GpioPrivateLib.c
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiDxeSmmGpioPrivateLib/GpioPrivateLibPch.c
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiDxeSmmGpioPrivateLib/GpioPrivateLibVer2.c
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiDxeSmmGpioPrivateLib/PeiDxeSmmGpioPrivateLibVer2.inf
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiGpioHelpersLib/PeiGpioHelpersLib.c
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiGpioHelpersLib/PeiGpioHelpersLib.inf
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/CpuPcieRp/Include/CpuPcieInfo.h b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/CpuPcieRp/Include/CpuPcieInfo.h
new file mode 100644
index 0000000000..a6f8b16d10
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/CpuPcieRp/Include/CpuPcieInfo.h
@@ -0,0 +1,25 @@
+/** @file
+ This file contains definitions of PCIe controller information
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _CPU_PCIE_INFO_H_
+#define _CPU_PCIE_INFO_H_
+
+#define PCIE_HWEQ_COEFFS_MAX 5
+
+
+//
+// SA PCI Express* Port configuration
+//
+
+#define CPU_PCIE_MAX_ROOT_PORTS 4
+#define CPU_PCIE_MAX_CONTROLLERS 3
+
+#define SA_PEG_MAX_FUN 0x04
+#define SA_PEG_MAX_LANE 0x14
+
+
+
+#endif
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Espi/Library/PeiDxeSmmEspiLib/EspiLib.c b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Espi/Library/PeiDxeSmmEspiLib/EspiLib.c
new file mode 100644
index 0000000000..2e4d1375ca
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Espi/Library/PeiDxeSmmEspiLib/EspiLib.c
@@ -0,0 +1,58 @@
+/** @file
+ This file contains routines for eSPI
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#include <Base.h>
+#include <Uefi/UefiBaseType.h>
+#include <Library/IoLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/EspiLib.h>
+#include <Library/PchPcrLib.h>
+#include <Library/PchInfoLib.h>
+#include <Library/TimerLib.h>
+#include <PchLimits.h>
+#include <Register/PchPcrRegs.h>
+#include <Register/PchRegsLpc.h>
+
+
+/**
+ Checks if second device capability is enabled
+
+ @retval TRUE There's second device
+ @retval FALSE There's no second device
+**/
+BOOLEAN
+IsEspiSecondSlaveSupported (
+ VOID
+ )
+{
+ return ((PchPcrRead32 (PID_ESPISPI, R_ESPI_PCR_SOFTSTRAPS) & B_ESPI_PCR_SOFTSTRAPS_CS1_EN) != 0);
+}
+
+
+/**
+ Is eSPI enabled in strap.
+
+ @retval TRUE Espi is enabled in strap
+ @retval FALSE Espi is disabled in strap
+**/
+BOOLEAN
+IsEspiEnabled (
+ VOID
+ )
+{
+ return (PchPcrRead32 (PID_ESPISPI, R_ESPI_PCR_CFG_VAL) & B_ESPI_PCR_CFG_VAL_ESPI_EN) != 0;
+}
+
+typedef enum {
+ EspiSlaveOperationConfigRead,
+ EspiSlaveOperationConfigWrite,
+ EspiSlaveOperationStatusRead,
+ EspiSlaveOperationInBandReset
+} ESPI_SLAVE_OPERATION;
+
+
+
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Espi/Library/PeiDxeSmmEspiLib/PeiDxeSmmEspiLib.inf b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Espi/Library/PeiDxeSmmEspiLib/PeiDxeSmmEspiLib.inf
new file mode 100644
index 0000000000..e8db1e4e8d
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Espi/Library/PeiDxeSmmEspiLib/PeiDxeSmmEspiLib.inf
@@ -0,0 +1,38 @@
+## @file
+# Component description file for the PeiDxeSmmPchEspiLib
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+
+[Defines]
+INF_VERSION = 0x00010017
+BASE_NAME = PeiDxeSmmEspiLib
+FILE_GUID = 7F25F990-7989-4413-B414-1EDE557E9389
+VERSION_STRING = 1.0
+MODULE_TYPE = BASE
+LIBRARY_CLASS = EspiLib
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = IA32 X64 IPF EBC
+#
+
+
+
+[LibraryClasses]
+BaseLib
+IoLib
+DebugLib
+PchPcrLib
+TimerLib
+
+
+[Packages]
+MdePkg/MdePkg.dec
+AlderlakeSiliconPkg/SiPkg.dec
+
+
+[Sources]
+EspiLib.c
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/IncludePrivate/Library/GpioHelpersLib.h b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/IncludePrivate/Library/GpioHelpersLib.h
new file mode 100644
index 0000000000..cf67c81ed0
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/IncludePrivate/Library/GpioHelpersLib.h
@@ -0,0 +1,50 @@
+/** @file
+ Header file for GPIO Helpers Lib implementation.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _GPIO_HELPERS_LIB_H_
+#define _GPIO_HELPERS_LIB_H_
+
+#include <Library/GpioConfig.h>
+
+/**
+ This procedure stores GPIO group data about pads which PadConfig needs to be unlocked.
+
+ @param[in] GroupIndex GPIO group index
+ @param[in] DwNum DWORD index for a group.
+ For group which has less then 32 pads per group DwNum must be 0.
+ @param[in] PadsToLock DWORD bitmask for pads which are going to be left unlocked
+ Bit position - PadNumber
+ Bit value - 0: Skip, 1: Leave unlocked
+
+ @retval Status
+**/
+EFI_STATUS
+GpioStoreGroupDwUnlockPadConfigData (
+ IN UINT32 GroupIndex,
+ IN UINT32 DwNum,
+ IN UINT32 UnlockedPads
+ );
+
+/**
+ This procedure stores GPIO group data about pads which Output state needs to be unlocked.
+
+ @param[in] GroupIndex GPIO group index
+ @param[in] DwNum DWORD index for a group.
+ For group which has less then 32 pads per group DwNum must be 0.
+ @param[in] PadsToLock DWORD bitmask for pads which are going to be left unlocked
+ Bit position - PadNumber
+ Bit value - 0: Skip, 1: Leave unlocked
+
+ @retval Status
+**/
+EFI_STATUS
+GpioStoreGroupDwUnlockOutputData (
+ IN UINT32 GroupIndex,
+ IN UINT32 DwNum,
+ IN UINT32 UnlockedPads
+ );
+
+#endif // _GPIO_HELPERS_LIB_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/IncludePrivate/Library/GpioNativePads.h b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/IncludePrivate/Library/GpioNativePads.h
new file mode 100644
index 0000000000..dbd13963fa
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/IncludePrivate/Library/GpioNativePads.h
@@ -0,0 +1,245 @@
+/** @file
+ Header file for GPIO Native pads support
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _GPIO_NATIVE_PADS_H_
+#define _GPIO_NATIVE_PADS_H_
+
+//
+// GpioPad can contain additional information used to provide data on
+// native functions. Please refer to description of GPIO_NATIVE_PAD
+//
+// FFFF CCCC TTTG GGGG TTTT TTTP PPPP PPPP
+//
+// F - 2^4 = 16, native function number
+// C - 2^4 = 16, chipset ID
+// T - 2^10 = 1024 , abstract type representing native mode of a pad (e.g. SERIALIO_UART2_TX)
+// G - 2^5 = 32, group
+// P - 2^9 = 512, pad number
+//
+// F & T contain additional optional settings used for native pads
+//
+#define GPIO_NATIVE_PAD_DEF(GpioNativePad, NativeMode, NativeFunction) \
+ (GpioNativePad | (NativeMode << 28) | ((NativeFunction & 0x7F) << 9) | ((NativeFunction & 0x380) << 14))
+
+#define GPIO_NATIVE_GET_FUNCTION(GpioNativePad) ((((GpioNativePad) & 0xFE00) >> 9) | (((GpioNativePad) & 0xE00000) >> 14))
+#define GPIO_NATIVE_GET_PAD_FN(GpioNativePad) (((GpioNativePad) >> 28) & 0xF)
+#define GPIO_NATIVE_GET_PAD_MODE(GpioNativePad) ((GPIO_NATIVE_GET_PAD_FN(GpioNativePad) << 1) | 1)
+#define GPIO_NATIVE_TO_GPIO_PAD(GpioNativePad) (GpioNativePad & 0xF1F01FF)
+
+//
+// Below defines and macros are used to build abstract type
+// to help encode native pin information in GPIO_PAD
+//
+
+//
+// Macro used to define GPIO native function.
+// <Min,Max> defines range that can be used to encode given native signal.
+// Numbering must be unique and cannot overlap.
+// If there are many instances of similar signal (e.g. per controller) the lower
+// word will store value for a given instance in the form: Min + Instance
+// Upper word (Max) is left untouched and later used for verification
+//
+#define GPIO_NATIVE_FUNCTION_DEF(Min, Max) (((Max) << 16) + (Min))
+#define GPIO_NATIVE_FUNCTION_GET_MAX(NativeFunction) (((NativeFunction) >> 16) & 0xFFFF)
+#define GPIO_NATIVE_FUNCTION_GET_VALUE(NativeFunction) ((NativeFunction) & 0xFFFF)
+
+//
+// Macro GPIO_NATIVE_FUNCTION_GET_SIGNAL is created as synonym to macro GPIO_NATIVE_FUNCTION_GET_MAX
+// GPIO_NATIVE_FUNCTION_GET_SIGNAL used with below defines is more descriptive and easier to read
+// ex.
+// - GPIO_NATIVE_FUNCTION_GET_SIGNAL(GPIO_SERIAL_IO_UART_RX)
+// - GPIO_NATIVE_FUNCTION_GET_SIGNAL(GPIO_ISH_GP)
+// - ...
+//
+#define GPIO_NATIVE_FUNCTION_GET_SIGNAL(NativeFunction) (GPIO_NATIVE_FUNCTION_GET_MAX(NativeFunction))
+
+//
+// GPIO native modes
+// Those defines are internal to this header.
+// GPIO_FUNCTION_<IP>_<signal>(index) defines should be used by other modules instead.
+//
+#define GPIO_SERIAL_IO_UART_RX GPIO_NATIVE_FUNCTION_DEF(1,8)
+#define GPIO_SERIAL_IO_UART_TX GPIO_NATIVE_FUNCTION_DEF(9,16)
+#define GPIO_SERIAL_IO_UART_RTS GPIO_NATIVE_FUNCTION_DEF(17,24)
+#define GPIO_SERIAL_IO_UART_CTS GPIO_NATIVE_FUNCTION_DEF(25,31)
+#define GPIO_SERIAL_IO_SPI_MOSI GPIO_NATIVE_FUNCTION_DEF(32,39)
+#define GPIO_SERIAL_IO_SPI_MISO GPIO_NATIVE_FUNCTION_DEF(40,47)
+#define GPIO_SERIAL_IO_SPI_CLK GPIO_NATIVE_FUNCTION_DEF(48,55)
+#define GPIO_SERIAL_IO_SPI_CS GPIO_NATIVE_FUNCTION_DEF(56,71)
+#define GPIO_ISH_GP GPIO_NATIVE_FUNCTION_DEF(80,143)
+#define GPIO_ISH_UART_RX GPIO_NATIVE_FUNCTION_DEF(144,151)
+#define GPIO_ISH_UART_TX GPIO_NATIVE_FUNCTION_DEF(152,159)
+#define GPIO_ISH_UART_RTS GPIO_NATIVE_FUNCTION_DEF(160,167)
+#define GPIO_ISH_UART_CTS GPIO_NATIVE_FUNCTION_DEF(168,175)
+#define GPIO_ISH_SPI_MOSI GPIO_NATIVE_FUNCTION_DEF(184,191)
+#define GPIO_ISH_SPI_MISO GPIO_NATIVE_FUNCTION_DEF(192,199)
+#define GPIO_ISH_SPI_CLK GPIO_NATIVE_FUNCTION_DEF(200,207)
+#define GPIO_ISH_SPI_CS GPIO_NATIVE_FUNCTION_DEF(208,223)
+#define GPIO_ISH_I2C_SCL GPIO_NATIVE_FUNCTION_DEF(232,239)
+#define GPIO_ISH_I2C_SDA GPIO_NATIVE_FUNCTION_DEF(240,247)
+#define GPIO_THC_SPI_INT GPIO_NATIVE_FUNCTION_DEF(248,251)
+#define GPIO_DMIC_DATA GPIO_NATIVE_FUNCTION_DEF(258,261)
+#define GPIO_DMIC_CLKA GPIO_NATIVE_FUNCTION_DEF(262,265)
+#define GPIO_DMIC_CLKB GPIO_NATIVE_FUNCTION_DEF(266,269)
+#define GPIO_DDSP_HPD0 GPIO_NATIVE_FUNCTION_DEF(270,285)
+#define GPIO_PANEL_AVDD_EN GPIO_NATIVE_FUNCTION_DEF(286,289)
+#define GPIO_PANEL_BKLTEN GPIO_NATIVE_FUNCTION_DEF(290,293)
+#define GPIO_PANEL_BKLTCTL GPIO_NATIVE_FUNCTION_DEF(294,297)
+#define GPIO_PANEL_RESET GPIO_NATIVE_FUNCTION_DEF(298,301)
+#define GPIO_PANEL_AVEE_EN GPIO_NATIVE_FUNCTION_DEF(302,305)
+#define GPIO_PANEL_VIO_EN GPIO_NATIVE_FUNCTION_DEF(306,309)
+#define GPIO_PANEL_HPD GPIO_NATIVE_FUNCTION_DEF(310,313)
+#define GPIO_PANEL_TE_EN GPIO_NATIVE_FUNCTION_DEF(314,317)
+#define GPIO_HDMI_GMBUS_SCL GPIO_NATIVE_FUNCTION_DEF(318,325)
+#define GPIO_HDMI_GMBUS_SDA GPIO_NATIVE_FUNCTION_DEF(326,333)
+#define GPIO_SERIAL_IO_I2C_SCL GPIO_NATIVE_FUNCTION_DEF(338,353)
+#define GPIO_SERIAL_IO_I2C_SDA GPIO_NATIVE_FUNCTION_DEF(354,369)
+#define GPIO_SD_DATA GPIO_NATIVE_FUNCTION_DEF(374,377)
+#define GPIO_EMMC_DATA GPIO_NATIVE_FUNCTION_DEF(384,391)
+#define GPIO_THC_CLK_LOOPBACK GPIO_NATIVE_FUNCTION_DEF(395,396)
+#define GPIO_MIPI_PANEL_RESET GPIO_NATIVE_FUNCTION_DEF(401,404)
+#define GPIO_MIPI_SEC_POW_EN_AVEE GPIO_NATIVE_FUNCTION_DEF(405,408)
+#define GPIO_MIPI_SEC_POW_EN_AVDD GPIO_NATIVE_FUNCTION_DEF(409,412)
+#define GPIO_THC_WOT GPIO_NATIVE_FUNCTION_DEF(413,414)
+#define GPIO_SATA_DEVSLP GPIO_NATIVE_FUNCTION_DEF(415,446)
+#define GPIO_PCIE_CLKREQ GPIO_NATIVE_FUNCTION_DEF(447,478)
+
+//
+// Serial IO UART
+//
+
+#define GPIO_FUNCTION_SERIAL_IO_UART_RX(UartDev) (GPIO_SERIAL_IO_UART_RX + ((UINT32)UartDev))
+#define GPIO_FUNCTION_SERIAL_IO_UART_TX(UartDev) (GPIO_SERIAL_IO_UART_TX + ((UINT32)UartDev))
+#define GPIO_FUNCTION_SERIAL_IO_UART_RTS(UartDev) (GPIO_SERIAL_IO_UART_RTS + ((UINT32)UartDev))
+#define GPIO_FUNCTION_SERIAL_IO_UART_CTS(UartDev) (GPIO_SERIAL_IO_UART_CTS + ((UINT32)UartDev))
+
+//
+// Serial IO SPI
+//
+#define GPIO_SERIAL_IO_SPI_RANGE 8 // Number of SerialIo SPIx controllers supported in GPIO_NATIVE_PAD encoding
+
+#define GPIO_FUNCTION_SERIAL_IO_SPI_MOSI(SpiDev) (GPIO_SERIAL_IO_SPI_MOSI + ((UINT32)SpiDev))
+#define GPIO_FUNCTION_SERIAL_IO_SPI_MISO(SpiDev) (GPIO_SERIAL_IO_SPI_MISO + ((UINT32)SpiDev))
+#define GPIO_FUNCTION_SERIAL_IO_SPI_CLK(SpiDev) (GPIO_SERIAL_IO_SPI_CLK + ((UINT32)SpiDev))
+#define GPIO_FUNCTION_SERIAL_IO_SPI_CS(SpiDev, CsNum) (GPIO_SERIAL_IO_SPI_CS + ((UINT32)SpiDev) + ((UINT32)CsNum) * GPIO_SERIAL_IO_SPI_RANGE)
+
+//
+// Serial IO I2C
+//
+
+#define GPIO_FUNCTION_SERIAL_IO_I2C_SCL(I2cDev) (GPIO_SERIAL_IO_I2C_SCL + ((UINT32)I2cDev))
+#define GPIO_FUNCTION_SERIAL_IO_I2C_SDA(I2cDev) (GPIO_SERIAL_IO_I2C_SDA + ((UINT32)I2cDev))
+
+//
+// ISH GP
+//
+
+#define GPIO_FUNCTION_ISH_GP(GpNum) (GPIO_ISH_GP + ((UINT32)GpNum))
+
+//
+// ISH UART
+//
+
+#define GPIO_FUNCTION_ISH_UART_RX(UartDev) (GPIO_ISH_UART_RX + ((UINT32)UartDev))
+#define GPIO_FUNCTION_ISH_UART_TX(UartDev) (GPIO_ISH_UART_TX + ((UINT32)UartDev))
+#define GPIO_FUNCTION_ISH_UART_RTS(UartDev) (GPIO_ISH_UART_RTS + ((UINT32)UartDev))
+#define GPIO_FUNCTION_ISH_UART_CTS(UartDev) (GPIO_ISH_UART_CTS + ((UINT32)UartDev))
+
+//
+// ISH SPI
+//
+#define GPIO_ISH_SPI_RANGE 8 // Number of ISH SPI controllers supported in GPIO_NATIVE_PAD encoding
+
+#define GPIO_FUNCTION_ISH_SPI_MOSI(SpiDev) (GPIO_ISH_SPI_MOSI + ((UINT32)SpiDev))
+#define GPIO_FUNCTION_ISH_SPI_MISO(SpiDev) (GPIO_ISH_SPI_MISO + ((UINT32)SpiDev))
+#define GPIO_FUNCTION_ISH_SPI_CLK(SpiDev) (GPIO_ISH_SPI_CLK + ((UINT32)SpiDev))
+#define GPIO_FUNCTION_ISH_SPI_CS(SpiDev, CsNum) (GPIO_ISH_SPI_CS + ((UINT32)SpiDev) + ((UINT32)CsNum) * GPIO_ISH_SPI_RANGE)
+
+//
+// ISH I2C
+//
+
+#define GPIO_FUNCTION_ISH_I2C_SCL(I2cDev) (GPIO_ISH_I2C_SCL + ((UINT32)I2cDev))
+#define GPIO_FUNCTION_ISH_I2C_SDA(I2cDev) (GPIO_ISH_I2C_SDA + ((UINT32)I2cDev))
+
+//
+// SD Card
+//
+#define GPIO_FUNCTION_SD_DATA(Index) (GPIO_SD_DATA + ((UINT32)Index))
+
+//
+// EMMC
+//
+#define GPIO_FUNCTION_EMMC_DATA(Index) (GPIO_EMMC_DATA + ((UINT32)Index))
+
+//
+// THC SPI
+//
+
+#define GPIO_FUNCTION_THC_SPI_INT(SpiDev) (GPIO_THC_SPI_INT + ((UINT32)SpiDev))
+#define GPIO_FUNCTION_THC_CLK_LOOPBACK(SpiDev) (GPIO_THC_CLK_LOOPBACK + ((UINT32)SpiDev))
+#define GPIO_FUNCTION_THC_WOT(SpiDev) (GPIO_THC_WOT + ((UINT32)SpiDev))
+
+
+//
+// DMIC
+//
+
+#define GPIO_FUNCTION_DMIC_DATA(DmicDev) (GPIO_DMIC_DATA + ((UINT32)DmicDev))
+#define GPIO_FUNCTION_DMIC_CLKA(DmicDev) (GPIO_DMIC_CLKA + ((UINT32)DmicDev))
+#define GPIO_FUNCTION_DMIC_CLKB(DmicDev) (GPIO_DMIC_CLKB + ((UINT32)DmicDev))
+#define GPIO_FUNCTION_DMIC_CLK(DmicDev) (GPIO_DMIC_CLKA + ((UINT32)DmicDev)) // If there is no split between channel A/B use A range for such Clocks
+
+
+//
+// DDSP HPD
+//
+
+#define GPIO_FUNCTION_DDSP_HPD(HpdIndex) \
+ (HpdIndex > 7) ? GPIO_DDSP_HPD0 + 8 + (HpdIndex) - 'A' : GPIO_DDSP_HPD0 + HpdIndex
+
+//
+// HDMI_GMBUS
+//
+
+#define GPIO_FUNCTION_HDMI_SCL(DdiPort) (GPIO_HDMI_GMBUS_SCL + ((UINT32)DdiPort))
+#define GPIO_FUNCTION_HDMI_SDA(DdiPort) (GPIO_HDMI_GMBUS_SDA + ((UINT32)DdiPort))
+
+//
+// Panel
+//
+
+#define GPIO_FUNCTION_PANEL_AVDD_EN(PanelDev) (GPIO_PANEL_AVDD_EN + ((UINT32)PanelDev))
+#define GPIO_FUNCTION_PANEL_BKLTEN(PanelDev) (GPIO_PANEL_BKLTEN + ((UINT32)PanelDev))
+#define GPIO_FUNCTION_PANEL_BKLTCTL(PanelDev) (GPIO_PANEL_BKLTCTL + ((UINT32)PanelDev))
+#define GPIO_FUNCTION_PANEL_RESET(PanelDev) (GPIO_PANEL_RESET + ((UINT32)PanelDev))
+#define GPIO_FUNCTION_PANEL_AVEE_EN(PanelDev) (GPIO_PANEL_AVEE_EN + ((UINT32)PanelDev))
+#define GPIO_FUNCTION_PANEL_VIO_EN(PanelDev) (GPIO_PANEL_VIO_EN + ((UINT32)PanelDev))
+#define GPIO_FUNCTION_PANEL_HPD(PanelDev) (GPIO_PANEL_HPD + ((UINT32)PanelDev))
+#define GPIO_FUNCTION_PANEL_TE_EN(PanelDev) (GPIO_PANEL_TE_EN + ((UINT32)PanelDev))
+
+//
+// MIPI
+//
+#define GPIO_FUNCTION_MIPI_PANEL_RESET(PanelDev) (GPIO_MIPI_PANEL_RESET + ((UINT32)PanelDev))
+#define GPIO_FUNCTION_MIPI_SEC_POW_EN_AVEE(PanelDev) (GPIO_MIPI_SEC_POW_EN_AVEE + ((UINT32)PanelDev))
+#define GPIO_FUNCTION_MIPI_SEC_POW_EN_AVDD(PanelDev) (GPIO_MIPI_SEC_POW_EN_AVDD + ((UINT32)PanelDev))
+
+
+//
+// SATA DevSlp
+//
+#define GPIO_SATA_DEVSLP_RANGE 32 // Number of SATA DevSlp instances per controller supported in GPIO_NATIVE_PAD encoding
+
+#define GPIO_FUNCTION_SATA_DEVSLP(CsNum, SataDevSlpIndex) (GPIO_SATA_DEVSLP + ((UINT32)SataDevSlpIndex) + ((UINT32)CsNum) * GPIO_SATA_DEVSLP_RANGE)
+
+//
+// SRC CLKREQ
+//
+
+#define GPIO_FUNCTION_PCIE_CLKREQ(ClkReqIndex) (GPIO_PCIE_CLKREQ + ((UINT32)ClkReqIndex))
+
+#endif // _GPIO_NATIVE_PADS_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/IncludePrivate/Library/GpioPrivateLib.h b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/IncludePrivate/Library/GpioPrivateLib.h
new file mode 100644
index 0000000000..a757a4b057
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/IncludePrivate/Library/GpioPrivateLib.h
@@ -0,0 +1,350 @@
+/** @file
+ Header file for GpioPrivateLib.
+ All function in this library is available for PEI, DXE, and SMM,
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _GPIO_PRIVATE_LIB_H_
+#define _GPIO_PRIVATE_LIB_H_
+
+#include <Uefi/UefiBaseType.h>
+#include <Library/GpioConfig.h>
+#include <Library/PchPcrLib.h>
+
+/**
+ GPIO Standby State configuration
+ Standby State options for GPIO Pads
+**/
+typedef enum {
+ GpioIosStateDefault = 0x0,
+ GpioIosStateLatchLastValue = (0x0 << 1) | 0x01, ///< Latch last value driven on TX, TX Enable and RX Enable
+ GpioIosStateTx0Rx0RxDis = (0x1 << 1) | 0x01, ///< TX: 0, RX: 0 (internally), RX disabled
+ GpioIosStateTx0Rx1RxDis = (0x2 << 1) | 0x01, ///< TX: 0, RX: 1 (internally), RX disabled
+ GpioIosStateTx1Rx0RxDis = (0x3 << 1) | 0x01, ///< TX: 1, RX: 0 (internally), RX disabled
+ GpioIosStateTx1Rx1RxDis = (0x4 << 1) | 0x01, ///< TX: 1, RX: 1 (internally), RX disabled
+ GpioIosStateTx0RxEn = (0x5 << 1) | 0x01, ///< TX: 0, RX enabled
+ GpioIosStateTx1RxEn = (0x6 << 1) | 0x01, ///< TX: 1, RX enabled
+ GpioIosStateHizRx0 = (0x7 << 1) | 0x01, ///< Hi-Z, RX: 0 (internally)
+ GpioIosStateHizRx1 = (0x8 << 1) | 0x01, ///< Hi-Z, RX: 1 (internally)
+ GpioIosStateTxDisRxEn = (0x9 << 1) | 0x01, ///< TX Disabled and RX Enabled (i.e. wake or interrupt)
+ GpioIosStateMasked = (0xF << 1) | 0x01 ///< IO Standby signal is masked for this pad. In this mode, a pad operates as if IOStandby has not been asserted.
+} GPIO_IOSTANDBY_STATE;
+
+/**
+ GPIO Standby Term configuration
+ Standby Termination options for GPIO Pads
+**/
+typedef enum {
+ GpioIosTermDefault = 0x00,
+ GpioIosTermSame = (0x00 << 1) | 0x01, ///< Same as state specified in Term
+ GpioIosTermPuDisPdDis = (0x01 << 1) | 0x01, ///< Disable Pullup and Pulldown
+ GpioIosTermPuDisPdEn = (0x02 << 1) | 0x01, ///< Enable Pulldown
+ GpioIosTermPuEnPdDis = (0x03 << 1) | 0x01 ///< Enable Pullup
+} GPIO_IOSTANDBY_TERM;
+
+//
+// Structure for native pin data
+//
+typedef struct {
+ GPIO_PAD Pad;
+ GPIO_PAD_MODE Mode;
+ GPIO_IOSTANDBY_STATE IosState;
+ GPIO_IOSTANDBY_TERM IosTerm;
+} GPIO_PAD_NATIVE_FUNCTION;
+
+//
+// Structure for Serial GPIO pin definition
+//
+typedef struct {
+ GPIO_PAD_NATIVE_FUNCTION Sclock;
+ GPIO_PAD_NATIVE_FUNCTION Sload;
+ GPIO_PAD_NATIVE_FUNCTION Sdataout;
+} SGPIO_PINS;
+
+//
+// Structure for USB Virtual Wire OverCurrent Pad Mode group
+//
+typedef struct {
+ GPIO_PAD OcRxPad;
+ GPIO_PAD OcTxPad;
+} GPIO_VWOC_FUNCTION;
+
+//
+// Below defines are based on GPIO_CONFIG structure fields
+//
+#define B_GPIO_PAD_MODE_MASK 0xF
+#define N_GPIO_PAD_MODE_BIT_POS 0
+#define B_GPIO_DIRECTION_DIR_MASK 0x7
+#define N_GPIO_DIRECTION_DIR_BIT_POS 0
+#define B_GPIO_DIRECTION_INV_MASK 0x18
+#define N_GPIO_DIRECTION_INV_BIT_POS 3
+#define B_GPIO_OUTPUT_MASK 0x3
+#define N_GPIO_OUTPUT_BIT_POS 0
+#define N_GPIO_INT_CONFIG_INT_SOURCE_BIT_POS 0
+#define N_GPIO_INT_CONFIG_INT_TYPE_BIT_POS 5
+#define N_GPIO_ELECTRICAL_CONFIG_TERMINATION_BIT_POS 0
+#define N_GPIO_OTHER_CONFIG_RXRAW_BIT_POS 0
+
+//
+// Structure for storing information about registers offset, community,
+// maximal pad number for available groups
+//
+typedef struct {
+ PCH_SBI_PID Community;
+ UINT16 PadOwnOffset;
+ UINT16 HostOwnOffset;
+ UINT16 GpiIsOffset;
+ UINT16 GpiIeOffset;
+ UINT16 GpiGpeStsOffset;
+ UINT16 GpiGpeEnOffset;
+ UINT16 SmiStsOffset;
+ UINT16 SmiEnOffset;
+ UINT16 NmiStsOffset;
+ UINT16 NmiEnOffset;
+ UINT16 PadCfgLockOffset;
+ UINT16 PadCfgLockTxOffset;
+ UINT16 PadCfgOffset;
+ UINT16 PadPerGroup;
+} GPIO_GROUP_INFO;
+
+//
+// If in GPIO_GROUP_INFO structure certain register doesn't exist
+// it will have value equal to NO_REGISTER_FOR_PROPERTY
+//
+#define NO_REGISTER_FOR_PROPERTY 0xFFFF
+
+#define GPIO_PAD_DEF(Group,Pad) (UINT32)(((Group) << 16) + (Pad))
+#define GPIO_GROUP_DEF(GroupIndex,ChipsetId) ((GroupIndex) | ((ChipsetId) << 8))
+#define GPIO_GET_GROUP_INDEX(Group) ((Group) & 0x1F)
+#define GPIO_GET_GROUP_FROM_PAD(GpioPad) (((GpioPad) & 0x0F1F0000) >> 16)
+#define GPIO_GET_GROUP_INDEX_FROM_PAD(GpioPad) GPIO_GET_GROUP_INDEX (GPIO_GET_GROUP_FROM_PAD(GpioPad))
+#define GPIO_GET_PAD_NUMBER(GpioPad) ((GpioPad) & 0x1FF)
+#define GPIO_GET_CHIPSET_ID(GpioPad) (((GpioPad) >> 24) & 0xF)
+
+#define GPIO_GET_PAD_POSITION(PadNumber) ((PadNumber) % 32)
+#define GPIO_GET_DW_NUM(PadNumber) ((PadNumber) / 32u)
+
+/**
+ This procedure will retrieve address and length of GPIO info table
+
+ @param[out] GpioGroupInfoTableLength Length of GPIO group table
+
+ @retval Pointer to GPIO group table
+**/
+CONST GPIO_GROUP_INFO*
+GpioGetGroupInfoTable (
+ OUT UINT32 *GpioGroupInfoTableLength
+ );
+
+typedef struct {
+ CONST CHAR8* GpioGroupPrefix;
+ CONST GPIO_PAD FirstUniqueGpio;
+ CONST CHAR8** GroupUniqueNames;
+ CONST UINT32 UniqueNamesTableSize;
+} GPIO_GROUP_NAME_INFO;
+
+//
+// Helper macros for initializing GPIO_GROUP_NAME_INFO structures
+//
+#define GPIO_GROUP_NAME(GroupName,FirstUniqueGpio,GroupUniqueNamesTable) \
+ {GroupName, FirstUniqueGpio, GroupUniqueNamesTable, ARRAY_SIZE (GroupUniqueNamesTable)}
+
+#define GPIO_GROUP_NAME_BASIC(GroupName) \
+ {GroupName, 0, NULL, 0}
+
+/**
+ Get GPIO Chipset ID specific to PCH generation and series
+**/
+UINT32
+GpioGetThisChipsetId (
+ VOID
+ );
+
+/**
+ This procedure is used to check if GpioPad is valid for certain chipset
+
+ @param[in] GpioPad GPIO pad
+
+ @retval TRUE This pin is valid on this chipset
+ FALSE Incorrect pin
+**/
+BOOLEAN
+GpioIsCorrectPadForThisChipset (
+ IN GPIO_PAD GpioPad
+ );
+
+
+/**
+ This procedure is used by PchSmiDispatcher and will return information
+ needed to register GPI SMI.
+
+ @param[in] Index GPI SMI number
+ @param[out] GpioPin GPIO pin
+ @param[out] GpiSmiBitOffset GPI SMI bit position within GpiSmi Registers
+ @param[out] GpiHostSwOwnRegAddress Address of HOSTSW_OWN register
+ @param[out] GpiSmiStsRegAddress Address of GPI SMI status register
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid group or pad number
+**/
+EFI_STATUS
+GpioGetPadAndSmiRegs (
+ IN UINT32 Index,
+ OUT GPIO_PAD *GpioPin,
+ OUT UINT8 *GpiSmiBitOffset,
+ OUT UINT32 *GpiHostSwOwnRegAddress,
+ OUT UINT32 *GpiSmiStsRegAddress
+ );
+
+/**
+ This procedure calculates Pad Configuration Register DW offset
+
+ @param[in] GpioPad GPIO pad
+ @param[in] DwReg Index of the configuration register
+
+ @retval DW Register offset
+**/
+UINT32
+GpioGetGpioPadCfgAddressFromGpioPad (
+ IN GPIO_PAD GpioPad,
+ IN UINT32 DwReg
+ );
+
+
+/**
+ This procedure will check if GpioPad argument is valid.
+ Function will check below conditions:
+ - GpioPad represents a pad for current PCH
+ - GpioPad belongs to valid GpioGroup
+ - GPIO PadNumber is not greater than number of pads for this group
+
+ @param[in] GpioPad GPIO pad
+
+ @retval TRUE GPIO pad is valid and can be used with GPIO lib API
+ @retval FALSE GPIO pad is invalid and cannot be used with GPIO lib API
+**/
+BOOLEAN
+GpioIsPadValid (
+ IN GPIO_PAD GpioPad
+ );
+
+/**
+ This procedure will read GPIO Pad Configuration register
+
+ @param[in] GpioPad GPIO pad
+ @param[in] DwReg Choose PADCFG register: 0:DW0, 1:DW1
+
+ @retval PadCfgRegValue PADCFG_DWx value
+**/
+UINT32
+GpioReadPadCfgReg (
+ IN GPIO_PAD GpioPad,
+ IN UINT8 DwReg
+ );
+
+/**
+ Check if 0x13 opcode supported for writing to GPIO lock unlock register
+
+ @retval TRUE It's supported
+ @retval FALSE It's not supported
+**/
+BOOLEAN
+IsGpioLockOpcodeSupported (
+ VOID
+ );
+
+/**
+ Gpio Minimum Set
+
+ Set of Gpio Minimum function to use in Pre Mem phase.
+ To optimise execution and reduce memory footprint thse minimum version
+ of 'full' functions are stripped from:
+ - GpioPad PCH validation
+ - GpioPad Group belonging validation
+ - GpioPad Host ownership validation
+ - IoStandbyState configuration
+ The use of below functions has to be careful and with full
+ understanding of all pros and cons. Please refer to GpioPrivateLib.c
+ to familiarize with details of implementation.
+**/
+
+/**
+ This procedure reads GPIO register
+
+ @param[in] GpioGroupInfo Pointer to GPIO group table info
+ @param[in] Register Register offset
+
+ @retval Register value or "F"s in case of errors
+**/
+UINT32
+GpioRegisterAccessRead32 (
+ IN CONST GPIO_GROUP_INFO *GpioGroupInfo,
+ IN UINT32 Register
+ );
+
+/**
+ This procedure writes GPIO register
+
+ @param[in] GpioGroupInfo Pointer to GPIO group table info
+ @param[in] Register Register offset
+ @param[in] AndValue And value
+ @param[in] OrValue Or value
+
+ @retval EFI_DEVICE_ERROR vGPIO BAR not programmed
+ EFI_SUCCESS Operation completed successfully
+**/
+EFI_STATUS
+GpioRegisterAccessAndThenOr32 (
+ IN CONST GPIO_GROUP_INFO *GpioGroupInfo,
+ IN UINT32 Register,
+ IN UINT32 AndValue,
+ IN UINT32 OrValue
+ );
+
+/**
+ This procedure will calculate PADCFG register value based on GpioConfig data
+ The procedure can be various depending on chipset generation.
+ Available configuration options and corresponding registers fields
+ can distributed in different way in configuration registers.
+
+ @param[in] GpioPad GPIO Pad
+ @param[in] GpioConfig GPIO Configuration data
+ @param[out] PadCfgDwReg PADCFG DWx register value
+ @param[out] PadCfgDwRegMask Mask with PADCFG DWx register bits to be modified
+
+ @retval Status
+**/
+EFI_STATUS
+GpioPadCfgRegValueFromGpioConfig (
+ IN GPIO_PAD GpioPad,
+ IN CONST GPIO_CONFIG *GpioConfig,
+ OUT UINT32 *PadCfgDwReg,
+ OUT UINT32 *PadCfgDwRegMask
+ );
+
+/**
+ This procedure will write GPIO Lock/LockTx register
+ - For PCH SBI message is used.
+ - For IBL MMIO access is used.
+
+ @param[in] RegValue GPIO register (Lock or LockTx) value
+ @param[in] RegOffset GPIO register (Lock or LockTx) base offset
+ @param[in] DwNum Register number for current group.
+ For group which has less then 32 pads per group DwNum must be 0.
+ @param[in] GpioGroupInfo Pointer to GPIO group table info
+ @param[in] GroupIndex GPIO group index in the GpioGroupInfo table
+
+ @retval EFI_SUCCESS The function completed successfully
+ EFI_UNSUPPORTED Feature is not supported for this group or pad
+**/
+EFI_STATUS
+GpioInternalWriteLockRegister (
+ IN UINT32 RegValue,
+ IN UINT32 RegOffset,
+ IN UINT32 DwNum,
+ IN CONST GPIO_GROUP_INFO *GpioGroupInfo,
+ IN UINT32 GroupIndex
+ );
+
+#endif // _GPIO_PRIVATE_LIB_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/Library/PeiDxeSmmGpioLib/GpioInit.c b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/Library/PeiDxeSmmGpioLib/GpioInit.c
new file mode 100644
index 0000000000..cf6f92a50d
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/Library/PeiDxeSmmGpioLib/GpioInit.c
@@ -0,0 +1,546 @@
+/** @file
+ This file contains routines for GPIO initialization
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#include "GpioLibrary.h"
+
+//
+// GPIO_GROUP_DW_DATA structure is used by GpioConfigurePch function
+// to cache values which will be programmed into respective GPIO registers
+// after all GpioPads are processed. This way MMIO accesses are decreased
+// and instead of doing one programming for one GpioPad there is only
+// one access for whole register.
+//
+typedef struct {
+ UINT32 HostSoftOwnReg;
+ UINT32 HostSoftOwnRegMask;
+ UINT32 GpiGpeEnReg;
+ UINT32 GpiGpeEnRegMask;
+ UINT32 GpiNmiEnReg;
+ UINT32 GpiNmiEnRegMask;
+ UINT32 GpiSmiEnReg;
+ UINT32 GpiSmiEnRegMask;
+ UINT32 ConfigUnlockMask;
+ UINT32 OutputUnlockMask;
+} GPIO_GROUP_DW_DATA;
+
+//
+// GPIO_GROUP_DW_NUMBER contains number of DWords required to
+// store Pad data for all groups. Each pad uses one bit.
+//
+// For Cannonlake only vGPIO group has >32 pads but those pads
+// will not be accessed by this function so GPIO_GROUP_DW_NUMBER can be 1
+//
+#define GPIO_GROUP_DW_NUMBER 1
+
+/**
+ Get GPIO DW Register values (HOSTSW_OWN, GPE_EN, NMI_EN, Lock).
+
+ @param[in] PadNumber GPIO pad number
+ @param[in] GpioConfig GPIO Config data
+ @param[in out] DwRegsValues Values for GPIO DW Registers
+
+ @retval None
+**/
+STATIC
+VOID
+GpioDwRegValueFromGpioConfig (
+ IN UINT32 PadNumber,
+ IN CONST GPIO_CONFIG *GpioConfig,
+ IN OUT GPIO_GROUP_DW_DATA *GroupDwData
+ )
+{
+ UINT32 PadBitPosition;
+ UINT32 DwNum;
+
+ PadBitPosition = GPIO_GET_PAD_POSITION (PadNumber);
+ DwNum = GPIO_GET_DW_NUM (PadNumber);
+
+ if (DwNum >= GPIO_GROUP_DW_NUMBER) {
+ ASSERT (FALSE);
+ return;
+ }
+ //
+ // Update value to be programmed in HOSTSW_OWN register
+ //
+ GroupDwData[DwNum].HostSoftOwnRegMask |= (GpioConfig->HostSoftPadOwn & 0x1) << PadBitPosition;
+ GroupDwData[DwNum].HostSoftOwnReg |= (GpioConfig->HostSoftPadOwn >> 0x1) << PadBitPosition;
+
+ //
+ // Update value to be programmed in GPI_GPE_EN register
+ //
+ GroupDwData[DwNum].GpiGpeEnRegMask |= (GpioConfig->InterruptConfig & 0x1) << PadBitPosition;
+ GroupDwData[DwNum].GpiGpeEnReg |= ((GpioConfig->InterruptConfig & GpioIntSci) >> 3) << PadBitPosition;
+
+ //
+ // Update value to be programmed in GPI_NMI_EN register
+ //
+ GroupDwData[DwNum].GpiNmiEnRegMask |= (GpioConfig->InterruptConfig & 0x1) << PadBitPosition;
+ GroupDwData[DwNum].GpiNmiEnReg |= ((GpioConfig->InterruptConfig & GpioIntNmi) >> 1) << PadBitPosition;
+
+ //
+ // Update value to be programmed in GPI_SMI_EN register
+ GroupDwData[DwNum].GpiSmiEnRegMask |= (GpioConfig->InterruptConfig & 0x1) << PadBitPosition;
+ GroupDwData[DwNum].GpiSmiEnReg |= ((GpioConfig->InterruptConfig & GpioIntSmi) >> 2) << PadBitPosition;
+ if ((GpioConfig->InterruptConfig & GpioIntSmi) == GpioIntSmi) {
+ GroupDwData[DwNum].HostSoftOwnRegMask |= 1 << PadBitPosition;
+ GroupDwData[DwNum].HostSoftOwnReg |= 1 << PadBitPosition;
+ }
+
+ //
+ // Update information on Pad Configuration Lock
+ //
+ GroupDwData[DwNum].ConfigUnlockMask |= ((GpioConfig->LockConfig >> 1) & 0x1) << PadBitPosition;
+
+ //
+ // Update information on Pad Configuration Lock Tx
+ //
+ GroupDwData[DwNum].OutputUnlockMask |= ((GpioConfig->LockConfig >> 3) & 0x1) << PadBitPosition;
+
+ //
+ // if pad in GpioMode is an output default action should be to leave output unlocked
+ //
+ if ((GpioConfig->PadMode == GpioPadModeGpio) &&
+ (GpioConfig->Direction == GpioDirOut) &&
+ ((GpioConfig->LockConfig & B_GPIO_LOCK_CONFIG_OUTPUT_LOCK_MASK) == GpioLockDefault)) {
+ GroupDwData[DwNum].OutputUnlockMask |= 0x1 << PadBitPosition;
+ }
+}
+
+/**
+ This internal procedure will scan GPIO initialization table and unlock
+ all pads present in it
+
+ @param[in] NumberOfItem Number of GPIO pad records in table
+ @param[in] GpioInitTableAddress GPIO initialization table
+ @param[in] Index Index of GPIO Initialization table record
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid group or pad number
+**/
+STATIC
+EFI_STATUS
+GpioUnlockPadsForAGroup (
+ IN UINT32 NumberOfItems,
+ IN GPIO_INIT_CONFIG *GpioInitTableAddress,
+ IN UINT32 Index
+ )
+{
+ UINT32 PadsToUnlock[GPIO_GROUP_DW_NUMBER];
+ UINT32 DwNum;
+ UINT32 PadBitPosition;
+ CONST GPIO_GROUP_INFO *GpioGroupInfo;
+ UINT32 GpioGroupInfoLength;
+ CONST GPIO_INIT_CONFIG *GpioData;
+ GPIO_GROUP Group;
+ UINT32 GroupIndex;
+ UINT32 PadNumber;
+
+ GpioGroupInfo = GpioGetGroupInfoTable (&GpioGroupInfoLength);
+
+ GpioData = &GpioInitTableAddress[Index];
+ Group = GpioGetGroupFromGpioPad (GpioData->GpioPad);
+ GroupIndex = GpioGetGroupIndexFromGpioPad (GpioData->GpioPad);
+
+ ZeroMem (PadsToUnlock, sizeof (PadsToUnlock));
+ //
+ // Loop through pads for one group. If pad belongs to a different group then
+ // break and move to register programming.
+ //
+ while (Index < NumberOfItems) {
+
+ GpioData = &GpioInitTableAddress[Index];
+ if (GroupIndex != GpioGetGroupIndexFromGpioPad (GpioData->GpioPad)) {
+ //if next pad is from different group then break loop
+ break;
+ }
+
+ PadNumber = GpioGetPadNumberFromGpioPad (GpioData->GpioPad);
+ //
+ // Check if legal pin number
+ //
+ if (PadNumber >= GpioGroupInfo[GroupIndex].PadPerGroup) {
+ DEBUG ((DEBUG_ERROR, "GPIO ERROR: Pin number (%d) exceeds possible range for group %d\n", PadNumber, GroupIndex));
+ return EFI_INVALID_PARAMETER;
+ }
+
+ PadBitPosition = GPIO_GET_PAD_POSITION (PadNumber);
+ DwNum = GPIO_GET_DW_NUM (PadNumber);
+
+ if (DwNum >= GPIO_GROUP_DW_NUMBER) {
+ ASSERT (FALSE);
+ return EFI_UNSUPPORTED;
+ }
+ //
+ // Update pads which need to be unlocked
+ //
+ PadsToUnlock[DwNum] |= 0x1 << PadBitPosition;
+
+ //Move to next item
+ Index++;
+ }
+
+ for (DwNum = 0; DwNum <= GPIO_GET_DW_NUM (GpioGroupInfo[GroupIndex].PadPerGroup - 1); DwNum++) {
+ //
+ // Unlock pads
+ //
+ if (PadsToUnlock[DwNum] != 0) {
+ GpioUnlockPadCfgForGroupDw (Group, DwNum, PadsToUnlock[DwNum]);
+ GpioUnlockPadCfgTxForGroupDw (Group, DwNum, PadsToUnlock[DwNum]);
+ }
+ }
+
+ return EFI_SUCCESS;
+}
+
+/**
+ This procedure will initialize multiple PCH GPIO pins
+
+ @param[in] NumberofItem Number of GPIO pads to be updated
+ @param[in] GpioInitTableAddress GPIO initialization table
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid group or pad number
+**/
+STATIC
+EFI_STATUS
+GpioConfigurePch (
+ IN UINT32 NumberOfItems,
+ IN GPIO_INIT_CONFIG *GpioInitTableAddress
+ )
+{
+ UINT32 Index;
+ UINT32 PadCfgDwReg[GPIO_PADCFG_DW_REG_NUMBER];
+ UINT32 PadCfgDwRegMask[GPIO_PADCFG_DW_REG_NUMBER];
+ UINT32 PadCfgReg;
+ GPIO_GROUP_DW_DATA GroupDwData[GPIO_GROUP_DW_NUMBER];
+ UINT32 DwNum;
+ CONST GPIO_GROUP_INFO *GpioGroupInfo;
+ UINT32 GpioGroupInfoLength;
+ GPIO_PAD_OWN PadOwnVal;
+ CONST GPIO_INIT_CONFIG *GpioData;
+ UINT32 GroupIndex;
+ UINT32 PadNumber;
+ UINT32 DwRegIndex;
+
+ PadOwnVal = GpioPadOwnHost;
+
+ GpioGroupInfo = GpioGetGroupInfoTable (&GpioGroupInfoLength);
+
+ Index = 0;
+ while (Index < NumberOfItems) {
+
+ GpioData = &GpioInitTableAddress[Index];
+ GroupIndex = GpioGetGroupIndexFromGpioPad (GpioData->GpioPad);
+
+ DEBUG_CODE_BEGIN();
+ if (!GpioIsCorrectPadForThisChipset (GpioData->GpioPad)) {
+ DEBUG ((DEBUG_ERROR, "GPIO ERROR: Incorrect GpioPad (0x%08x) used on this chipset!\n", GpioData->GpioPad));
+ ASSERT (FALSE);
+ return EFI_UNSUPPORTED;
+ }
+ DEBUG_CODE_END ();
+
+ //
+ // Unlock pads for a given group which are going to be reconfigured
+ //
+ //
+ // Because PADCFGLOCK/LOCKTX register reset domain is Powergood, lock settings
+ // will get back to default only after G3 or DeepSx transition. On the other hand GpioPads
+ // configuration is controlled by a configurable type of reset - PadRstCfg. This means that if
+ // PadRstCfg != Powergood GpioPad will have its configuration locked despite it being not the
+ // one desired by BIOS. Before reconfiguring all pads they will get unlocked.
+ //
+ GpioUnlockPadsForAGroup (NumberOfItems, GpioInitTableAddress, Index);
+
+ ZeroMem (GroupDwData, sizeof (GroupDwData));
+ //
+ // Loop through pads for one group. If pad belongs to a different group then
+ // break and move to register programming.
+ //
+ while (Index < NumberOfItems) {
+
+ GpioData = &GpioInitTableAddress[Index];
+ if (GroupIndex != GpioGetGroupIndexFromGpioPad (GpioData->GpioPad)) {
+ //if next pad is from different group then break loop
+ break;
+ }
+
+ PadNumber = GpioGetPadNumberFromGpioPad (GpioData->GpioPad);
+
+ DEBUG_CODE_BEGIN ();
+ //
+ // Check if legal pin number
+ //
+ if (PadNumber >= GpioGroupInfo[GroupIndex].PadPerGroup) {
+ DEBUG ((DEBUG_ERROR, "GPIO ERROR: Pin number (%d) exceeds possible range for group %d\n", PadNumber, GroupIndex));
+ return EFI_INVALID_PARAMETER;
+ }
+
+ //
+ // Check if selected GPIO Pad is not owned by CSME/ISH
+ //
+ GpioGetPadOwnership (GpioData->GpioPad, &PadOwnVal);
+
+ if (PadOwnVal != GpioPadOwnHost) {
+ DEBUG ((DEBUG_ERROR, "GPIO ERROR: Accessing pad not owned by host (Group=%d, Pad=%d)!\n", GroupIndex, PadNumber));
+ DEBUG ((DEBUG_ERROR, "** Please make sure the GPIO usage in sync between CSME and BIOS configuration. \n"));
+ DEBUG ((DEBUG_ERROR, "** All the GPIO occupied by CSME should not do any configuration by BIOS.\n"));
+ //Move to next item
+ goto move_to_next_index;
+ }
+
+ //
+ // Check if Pad enabled for SCI is to be in unlocked state
+ //
+ if (((GpioData->GpioConfig.InterruptConfig & GpioIntSci) == GpioIntSci) &&
+ ((GpioData->GpioConfig.LockConfig & B_GPIO_LOCK_CONFIG_PAD_CONF_LOCK_MASK) != GpioPadConfigUnlock)){
+ DEBUG ((DEBUG_ERROR, "GPIO ERROR: GPIO used for SCI is not unlocked!\n"));
+ ASSERT (FALSE);
+ return EFI_INVALID_PARAMETER;
+ }
+ DEBUG_CODE_END ();
+
+ ZeroMem (PadCfgDwReg, sizeof (PadCfgDwReg));
+ ZeroMem (PadCfgDwRegMask, sizeof (PadCfgDwRegMask));
+ //
+ // Get GPIO PADCFG register value from GPIO config data
+ //
+ GpioPadCfgRegValueFromGpioConfig (
+ GpioData->GpioPad,
+ &GpioData->GpioConfig,
+ PadCfgDwReg,
+ PadCfgDwRegMask
+ );
+
+ //
+ // Write PADCFG DW0, DW1, DW2 registers
+ //
+ for (DwRegIndex = 0; DwRegIndex <= 2; DwRegIndex++) {
+ PadCfgReg = GpioGetGpioPadCfgAddressFromGpioPad (GpioData->GpioPad, DwRegIndex);
+ if (PadCfgReg != 0) {
+ GpioRegisterAccessAndThenOr32 (&GpioGroupInfo[GroupIndex], PadCfgReg, ~PadCfgDwRegMask[DwRegIndex], PadCfgDwReg[DwRegIndex]);
+ }
+ }
+
+ //
+ // Get GPIO DW register values from GPIO config data
+ //
+ GpioDwRegValueFromGpioConfig (
+ PadNumber,
+ &GpioData->GpioConfig,
+ GroupDwData
+ );
+
+ move_to_next_index:
+ //Move to next item
+ Index++;
+ }
+
+ for (DwNum = 0; DwNum <= GPIO_GET_DW_NUM (GpioGroupInfo[GroupIndex].PadPerGroup); DwNum++) {
+ //
+ // Write HOSTSW_OWN registers
+ //
+ if (GpioGroupInfo[GroupIndex].HostOwnOffset != NO_REGISTER_FOR_PROPERTY) {
+ GpioRegisterAccessAndThenOr32 (
+ &GpioGroupInfo[GroupIndex],
+ GpioGroupInfo[GroupIndex].HostOwnOffset + DwNum * 0x4,
+ ~GroupDwData[DwNum].HostSoftOwnRegMask,
+ GroupDwData[DwNum].HostSoftOwnReg
+ );
+ }
+
+ //
+ // Write GPI_GPE_EN registers
+ //
+ if (GpioGroupInfo[GroupIndex].GpiGpeEnOffset != NO_REGISTER_FOR_PROPERTY) {
+ GpioRegisterAccessAndThenOr32 (
+ &GpioGroupInfo[GroupIndex],
+ GpioGroupInfo[GroupIndex].GpiGpeEnOffset + DwNum * 0x4,
+ ~GroupDwData[DwNum].GpiGpeEnRegMask,
+ GroupDwData[DwNum].GpiGpeEnReg
+ );
+ }
+
+ //
+ // Write GPI_NMI_EN registers
+ //
+ if (GpioGroupInfo[GroupIndex].NmiEnOffset != NO_REGISTER_FOR_PROPERTY) {
+ GpioRegisterAccessAndThenOr32 (
+ &GpioGroupInfo[GroupIndex],
+ GpioGroupInfo[GroupIndex].NmiEnOffset + DwNum * 0x4,
+ ~GroupDwData[DwNum].GpiNmiEnRegMask,
+ GroupDwData[DwNum].GpiNmiEnReg
+ );
+ } else if (GroupDwData[DwNum].GpiNmiEnReg != 0x0) {
+ DEBUG ((DEBUG_ERROR, "GPIO ERROR: Group %d has no pads supporting NMI\n", GroupIndex));
+ ASSERT_EFI_ERROR (EFI_UNSUPPORTED);
+ }
+
+ //
+ // Write GPI_SMI_EN registers
+ //
+ if (GpioGroupInfo[GroupIndex].SmiEnOffset != NO_REGISTER_FOR_PROPERTY) {
+ GpioRegisterAccessAndThenOr32 (
+ &GpioGroupInfo[GroupIndex],
+ GpioGroupInfo[GroupIndex].SmiEnOffset + DwNum * 0x4,
+ ~GroupDwData[DwNum].GpiSmiEnRegMask,
+ GroupDwData[DwNum].GpiSmiEnReg
+ );
+ } else if (GroupDwData[DwNum].GpiSmiEnReg != 0x0) {
+ DEBUG ((DEBUG_ERROR, "GPIO ERROR: Group %d has no pads supporting SMI\n", GroupIndex));
+ ASSERT_EFI_ERROR (EFI_UNSUPPORTED);
+ }
+
+ //
+ // Update Pad Configuration unlock data
+ //
+ if (GroupDwData[DwNum].ConfigUnlockMask) {
+ GpioStoreGroupDwUnlockPadConfigData (GroupIndex, DwNum, GroupDwData[DwNum].ConfigUnlockMask);
+ }
+
+ //
+ // Update Pad Output unlock data
+ //
+ if (GroupDwData[DwNum].OutputUnlockMask) {
+ GpioStoreGroupDwUnlockOutputData (GroupIndex, DwNum, GroupDwData[DwNum].OutputUnlockMask);
+ }
+ }
+ }
+
+ return EFI_SUCCESS;
+}
+
+/**
+ This procedure will clear all status bits of any GPIO interrupts.
+
+ @param[in] none
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid group or pad number
+**/
+STATIC
+EFI_STATUS
+GpioClearAllGpioInterrupts (
+ VOID
+ )
+{
+ GPIO_GROUP Group;
+ CONST GPIO_GROUP_INFO *GpioGroupInfo;
+ GPIO_GROUP GpioGroupLowest;
+ GPIO_GROUP GpioGroupHighest;
+ UINT32 GroupIndex;
+ UINT32 GpioGroupInfoLength;
+ UINT32 DwNum;
+
+ GpioGroupInfo = GpioGetGroupInfoTable (&GpioGroupInfoLength);
+
+ GpioGroupLowest = GpioGetLowestGroup ();
+ GpioGroupHighest = GpioGetHighestGroup ();
+
+ for (Group = GpioGroupLowest; Group <= GpioGroupHighest; Group++) {
+ GroupIndex = GpioGetGroupIndexFromGroup (Group);
+ //
+ // Check if group has GPI IS register
+ //
+ if (GpioGroupInfo[GroupIndex].GpiIsOffset != NO_REGISTER_FOR_PROPERTY) {
+ //
+ // Clear all GPI_IS Status bits by writing '1'
+ //
+ for (DwNum = 0; DwNum <= GPIO_GET_DW_NUM (GpioGroupInfo[GroupIndex].PadPerGroup); DwNum++) {
+ GpioRegisterAccessAndThenOr32 (
+ &GpioGroupInfo[GroupIndex],
+ GpioGroupInfo[GroupIndex].GpiIsOffset + DwNum * 0x4,
+ ~(UINT32)0,
+ 0xFFFFFFFF
+ );
+ }
+ }
+
+ //
+ // Check if group has GPI_GPE_STS register
+ //
+ if (GpioGroupInfo[GroupIndex].GpiGpeStsOffset != NO_REGISTER_FOR_PROPERTY) {
+ //
+ // Clear all GPI_GPE_STS Status bits by writing '1'
+ //
+ for (DwNum = 0; DwNum <= GPIO_GET_DW_NUM (GpioGroupInfo[GroupIndex].PadPerGroup); DwNum++) {
+ GpioRegisterAccessAndThenOr32 (
+ &GpioGroupInfo[GroupIndex],
+ GpioGroupInfo[GroupIndex].GpiGpeStsOffset + DwNum * 0x4,
+ ~(UINT32)0,
+ 0xFFFFFFFF
+ );
+ }
+ }
+
+ //
+ // Check if group has SMI_STS register
+ //
+ if (GpioGroupInfo[GroupIndex].SmiStsOffset != NO_REGISTER_FOR_PROPERTY) {
+ //
+ // Clear all SMI_STS Status bits by writing '1'
+ //
+ for (DwNum = 0; DwNum <= GPIO_GET_DW_NUM (GpioGroupInfo[GroupIndex].PadPerGroup); DwNum++) {
+ GpioRegisterAccessAndThenOr32 (
+ &GpioGroupInfo[GroupIndex],
+ GpioGroupInfo[GroupIndex].SmiStsOffset + DwNum * 4,
+ ~(UINT32)0,
+ 0xFFFFFFFF
+ );
+ }
+ }
+
+ //
+ // Check if group has NMI_STS register
+ //
+ if (GpioGroupInfo[GroupIndex].NmiStsOffset != NO_REGISTER_FOR_PROPERTY) {
+ //
+ // Clear all NMI_STS Status bits by writing '1'
+ //
+ for (DwNum = 0; DwNum <= GPIO_GET_DW_NUM (GpioGroupInfo[GroupIndex].PadPerGroup); DwNum++) {
+ GpioRegisterAccessAndThenOr32 (
+ &GpioGroupInfo[GroupIndex],
+ GpioGroupInfo[GroupIndex].NmiStsOffset + DwNum * 4,
+ ~(UINT32)0,
+ 0xFFFFFFFF
+ );
+ }
+ }
+
+ }
+ return EFI_SUCCESS;
+}
+
+/**
+ This procedure will initialize multiple GPIO pins. Use GPIO_INIT_CONFIG structure.
+ Structure contains fields that can be used to configure each pad.
+ Pad not configured using GPIO_INIT_CONFIG will be left with hardware default values.
+ Separate fields could be set to hardware default if it does not matter, except
+ GpioPad and PadMode.
+ Function will work in most efficient way if pads which belong to the same group are
+ placed in adjacent records of the table.
+ Although function can enable pads for Native mode, such programming is done
+ by reference code when enabling related silicon feature.
+
+ @param[in] NumberofItem Number of GPIO pads to be updated
+ @param[in] GpioInitTableAddress GPIO initialization table
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid group or pad number
+**/
+EFI_STATUS
+GpioConfigurePads (
+ IN UINT32 NumberOfItems,
+ IN GPIO_INIT_CONFIG *GpioInitTableAddress
+ )
+{
+ EFI_STATUS Status;
+
+ Status = GpioConfigurePch (NumberOfItems, GpioInitTableAddress);
+
+ GpioClearAllGpioInterrupts ();
+ return Status;
+}
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/Library/PeiDxeSmmGpioLib/GpioLib.c b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/Library/PeiDxeSmmGpioLib/GpioLib.c
new file mode 100644
index 0000000000..19daed97c0
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/Library/PeiDxeSmmGpioLib/GpioLib.c
@@ -0,0 +1,522 @@
+/** @file
+ This file contains routines for GPIO
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#include "GpioLibrary.h"
+#include <Register/PchPcrRegs.h>
+
+/**
+ This procedure will check if GpioGroup argument is correct and
+ supplied DW reg number can be used for this group to access DW registers.
+ Function will check below conditions:
+ - Valid GpioGroup
+ - DwNum is has valid value for this group
+
+ @param[in] Group GPIO group
+ @param[in] DwNum Register number for current group (parameter applicable in accessing whole register).
+ For group which has less then 32 pads per group DwNum must be 0.
+
+ @retval TRUE DW Reg number and GpioGroup is valid
+ @retval FALSE DW Reg number and GpioGroup is invalid
+**/
+STATIC
+BOOLEAN
+GpioIsGroupAndDwNumValid (
+ IN GPIO_GROUP Group,
+ IN UINT32 DwNum
+ )
+{
+ UINT32 GroupIndex;
+ CONST GPIO_GROUP_INFO *GpioGroupInfo;
+ UINT32 GpioGroupInfoLength;
+
+ GpioGroupInfo = GpioGetGroupInfoTable (&GpioGroupInfoLength);
+
+ GroupIndex = GpioGetGroupIndexFromGroup (Group);
+
+ if ((Group < GpioGetLowestGroup ()) || (Group > GpioGetHighestGroup ()) || (GroupIndex >= GpioGroupInfoLength)) {
+ DEBUG ((DEBUG_ERROR, "GPIO ERROR: Group argument (%d) is not within range of possible groups for this PCH\n", GroupIndex));
+ goto Error;
+ }
+
+ //
+ // Check if DwNum argument does not exceed number of DWord registers
+ // resulting from available pads for certain group
+ //
+ if (DwNum > GPIO_GET_DW_NUM (GpioGroupInfo[GroupIndex].PadPerGroup - 1)){
+ goto Error;
+ }
+
+ return TRUE;
+Error:
+ ASSERT (FALSE);
+ return FALSE;
+}
+
+//
+// Possible registers to be accessed using GpioReadReg()/GpioWriteReg() functions
+//
+typedef enum {
+ GpioHostOwnershipRegister = 0,
+ GpioGpeEnableRegister,
+ GpioGpeStatusRegister,
+ GpioSmiEnableRegister,
+ GpioSmiStatusRegister,
+ GpioNmiEnableRegister,
+ GpioPadConfigLockRegister,
+ GpioPadLockOutputRegister
+} GPIO_REG;
+
+/**
+ This procedure will read GPIO register
+
+ @param[in] RegType GPIO register type
+ @param[in] Group GPIO group
+ @param[in] DwNum Register number for current group (parameter applicable in accessing whole register).
+ For group which has less then 32 pads per group DwNum must be 0.
+ @param[out] ReadVal Read data
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_UNSUPPORTED Feature is not supported for this group or pad
+**/
+STATIC
+EFI_STATUS
+GpioReadReg (
+ IN GPIO_REG RegType,
+ IN GPIO_GROUP Group,
+ IN UINT32 DwNum,
+ OUT UINT32 *ReadVal
+ )
+{
+ UINT32 RegOffset;
+ UINT32 GroupIndex;
+ CONST GPIO_GROUP_INFO *GpioGroupInfo;
+ UINT32 GpioGroupInfoLength;
+
+ RegOffset = NO_REGISTER_FOR_PROPERTY;
+ GroupIndex = GpioGetGroupIndexFromGroup (Group);
+
+ GpioGroupInfo = GpioGetGroupInfoTable (&GpioGroupInfoLength);
+
+ switch (RegType) {
+ case GpioHostOwnershipRegister:
+ RegOffset = GpioGroupInfo[GroupIndex].HostOwnOffset;
+ break;
+ case GpioGpeEnableRegister:
+ RegOffset = GpioGroupInfo[GroupIndex].GpiGpeEnOffset;
+ break;
+ case GpioGpeStatusRegister:
+ RegOffset = GpioGroupInfo[GroupIndex].GpiGpeStsOffset;
+ break;
+ case GpioSmiEnableRegister:
+ RegOffset = GpioGroupInfo[GroupIndex].SmiEnOffset;
+ break;
+ case GpioSmiStatusRegister:
+ RegOffset = GpioGroupInfo[GroupIndex].SmiStsOffset;
+ break;
+ case GpioNmiEnableRegister:
+ RegOffset = GpioGroupInfo[GroupIndex].NmiEnOffset;
+ break;
+ case GpioPadConfigLockRegister:
+ RegOffset = GpioGroupInfo[GroupIndex].PadCfgLockOffset;
+ break;
+ case GpioPadLockOutputRegister:
+ RegOffset = GpioGroupInfo[GroupIndex].PadCfgLockTxOffset;
+ break;
+ default:
+ break;
+ }
+
+ //
+ // Check if selected register exists
+ //
+ if (RegOffset == NO_REGISTER_FOR_PROPERTY) {
+ return EFI_UNSUPPORTED;
+ }
+
+ //
+ // If there are more then 32 pads per group then certain
+ // group information would be split into more then one DWord register.
+ //
+ if ((RegType == GpioPadConfigLockRegister) || (RegType == GpioPadLockOutputRegister)) {
+ //
+ // PadConfigLock and OutputLock registers when used for group containing more than 32 pads
+ // are not placed in a continuous way, e.g:
+ // 0x0 - PadConfigLock_DW0
+ // 0x4 - OutputLock_DW0
+ // 0x8 - PadConfigLock_DW1
+ // 0xC - OutputLock_DW1
+ //
+ RegOffset += DwNum * 0x8;
+ } else {
+ RegOffset += DwNum * 0x4;
+ }
+
+ *ReadVal = GpioRegisterAccessRead32 (&GpioGroupInfo[GroupIndex], RegOffset);
+
+ return EFI_SUCCESS;
+}
+
+/**
+ This procedure will write GPIO register
+
+ @param[in] RegType GPIO register type
+ @param[in] Group GPIO group
+ @param[in] DwNum Register number for current group (parameter applicable in accessing whole register).
+ For group which has less then 32 pads per group DwNum must be 0.
+ @param[in] RegAndMask Mask which will be AND'ed with register value
+ @param[in] RegOrMask Mask which will be OR'ed with register value
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_UNSUPPORTED Feature is not supported for this group or pad
+**/
+STATIC
+EFI_STATUS
+GpioWriteReg (
+ IN GPIO_REG RegType,
+ IN GPIO_GROUP Group,
+ IN UINT32 DwNum,
+ IN UINT32 RegAndMask,
+ IN UINT32 RegOrMask
+ )
+{
+ UINT32 RegOffset;
+ UINT32 GroupIndex;
+ CONST GPIO_GROUP_INFO *GpioGroupInfo;
+ UINT32 GpioGroupInfoLength;
+ UINT32 PadCfgLock;
+ BOOLEAN Lockable;
+
+ Lockable = FALSE;
+ PadCfgLock = 0;
+ RegOffset = NO_REGISTER_FOR_PROPERTY;
+ GroupIndex = GpioGetGroupIndexFromGroup (Group);
+
+ GpioGroupInfo = GpioGetGroupInfoTable (&GpioGroupInfoLength);
+
+ switch (RegType) {
+ case GpioHostOwnershipRegister:
+ RegOffset = GpioGroupInfo[GroupIndex].HostOwnOffset;
+ break;
+ case GpioGpeEnableRegister:
+ RegOffset = GpioGroupInfo[GroupIndex].GpiGpeEnOffset;
+ Lockable = TRUE;
+ break;
+ case GpioGpeStatusRegister:
+ RegOffset = GpioGroupInfo[GroupIndex].GpiGpeStsOffset;
+ break;
+ case GpioSmiEnableRegister:
+ RegOffset = GpioGroupInfo[GroupIndex].SmiEnOffset;
+ Lockable = TRUE;
+ break;
+ case GpioSmiStatusRegister:
+ RegOffset = GpioGroupInfo[GroupIndex].SmiStsOffset;
+ break;
+ case GpioNmiEnableRegister:
+ RegOffset = GpioGroupInfo[GroupIndex].NmiEnOffset;
+ Lockable = TRUE;
+ break;
+ case GpioPadConfigLockRegister:
+ case GpioPadLockOutputRegister:
+ default:
+ break;
+ }
+
+ //
+ // Check if selected register exists
+ //
+ if (RegOffset == NO_REGISTER_FOR_PROPERTY) {
+ return EFI_UNSUPPORTED;
+ }
+
+ if (Lockable) {
+ GpioGetPadCfgLockForGroupDw (Group, DwNum, &PadCfgLock);
+ if (PadCfgLock) {
+ //
+ // Check if for pads which are going to be reconfigured lock is set.
+ //
+ if ((~RegAndMask | RegOrMask) & PadCfgLock) {
+ //
+ // Unlock all pads for this Group DW reg for simplicity
+ // even if not all of those pads will have their settings reprogrammed
+ //
+ GpioUnlockPadCfgForGroupDw (Group, DwNum, PadCfgLock);
+ } else {
+ //
+ // No need to perform an unlock as pads which are going to be reconfigured
+ // are not in locked state
+ //
+ PadCfgLock = 0;
+ }
+ }
+ }
+
+ //
+ // If there are more then 32 pads per group then certain
+ // group information would be split into more then one DWord register.
+ //
+ RegOffset += DwNum * 0x4;
+
+ GpioRegisterAccessAndThenOr32 (&GpioGroupInfo[GroupIndex], RegOffset, RegAndMask,RegOrMask);
+
+ if (Lockable && PadCfgLock) {
+ //
+ // Lock previously unlocked pads
+ //
+ GpioLockPadCfgForGroupDw (Group, DwNum, PadCfgLock);
+ }
+
+ return EFI_SUCCESS;
+}
+
+/**
+ This procedure will write GPIO Lock/LockTx register using SBI.
+
+ @param[in] RegType GPIO register (Lock or LockTx)
+ @param[in] Group GPIO group number
+ @param[in] DwNum Register number for current group.
+ For group which has less then 32 pads per group DwNum must be 0.
+ @param[in] LockRegAndMask Mask which will be AND'ed with Lock register value
+ @param[in] LockRegOrMask Mask which will be Or'ed with Lock register value
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_UNSUPPORTED Feature is not supported for this group or pad
+**/
+STATIC
+EFI_STATUS
+GpioWriteLockReg (
+ IN GPIO_REG RegType,
+ IN GPIO_GROUP Group,
+ IN UINT32 DwNum,
+ IN UINT32 LockRegAndMask,
+ IN UINT32 LockRegOrMask
+ )
+{
+ CONST GPIO_GROUP_INFO *GpioGroupInfo;
+ UINT32 GpioGroupInfoLength;
+ UINT32 RegOffset;
+ UINT32 OldLockVal;
+ UINT32 NewLockVal;
+ UINT32 GroupIndex;
+
+ OldLockVal = 0;
+ NewLockVal = 0;
+
+ RegOffset = NO_REGISTER_FOR_PROPERTY;
+ GroupIndex = GpioGetGroupIndexFromGroup (Group);
+
+ GpioGroupInfo = GpioGetGroupInfoTable (&GpioGroupInfoLength);
+
+ switch (RegType) {
+ case GpioPadConfigLockRegister:
+ RegOffset = GpioGroupInfo[GroupIndex].PadCfgLockOffset;
+ GpioGetPadCfgLockForGroupDw (Group, DwNum, &OldLockVal);
+ break;
+ case GpioPadLockOutputRegister:
+ RegOffset = GpioGroupInfo[GroupIndex].PadCfgLockTxOffset;
+ GpioGetPadCfgLockTxForGroupDw (Group, DwNum, &OldLockVal);
+ break;
+ default:
+ break;
+ }
+
+ //
+ // Check if selected register exists
+ //
+ if (RegOffset == NO_REGISTER_FOR_PROPERTY) {
+ return EFI_UNSUPPORTED;
+ }
+
+ NewLockVal = (OldLockVal & LockRegAndMask) | LockRegOrMask;
+
+ return GpioInternalWriteLockRegister (NewLockVal, RegOffset, DwNum, GpioGroupInfo, GroupIndex);
+}
+
+/**
+ This procedure will get Gpio Pad Ownership
+
+ @param[in] GpioPad GPIO pad
+ @param[out] PadOwnVal Value of Pad Ownership
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid group or pad number
+**/
+EFI_STATUS
+GpioGetPadOwnership (
+ IN GPIO_PAD GpioPad,
+ OUT GPIO_PAD_OWN *PadOwnVal
+ )
+{
+ UINT32 Mask;
+ UINT32 RegOffset;
+ UINT32 GroupIndex;
+ UINT32 PadNumber;
+ CONST GPIO_GROUP_INFO *GpioGroupInfo;
+ UINT32 GpioGroupInfoLength;
+ UINT32 PadOwnRegValue;
+
+ if (!GpioIsPadValid (GpioPad)) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ GroupIndex = GpioGetGroupIndexFromGpioPad (GpioPad);
+ PadNumber = GpioGetPadNumberFromGpioPad (GpioPad);
+
+ GpioGroupInfo = GpioGetGroupInfoTable (&GpioGroupInfoLength);
+
+ //
+ // Check if selected register exists
+ //
+ if (GpioGroupInfo[GroupIndex].PadOwnOffset == NO_REGISTER_FOR_PROPERTY) {
+ *PadOwnVal = GpioPadOwnHost;
+ return EFI_UNSUPPORTED;
+ }
+ //
+ // Calculate RegOffset using Pad Ownership offset and GPIO Pad number.
+ // One DWord register contains information for 8 pads.
+ //
+ RegOffset = GpioGroupInfo[GroupIndex].PadOwnOffset + (PadNumber >> 3) * 0x4;
+
+ //
+ // Calculate pad bit position within DWord register
+ //
+ PadNumber %= 8;
+ Mask = (BIT1 | BIT0) << (PadNumber * 4);
+
+ PadOwnRegValue = GpioRegisterAccessRead32 (&GpioGroupInfo[GroupIndex], RegOffset);
+
+ *PadOwnVal = (GPIO_PAD_OWN) ((PadOwnRegValue & Mask) >> (PadNumber * 4));
+
+ return EFI_SUCCESS;
+}
+
+/**
+ This procedure will check state of Pad Config Lock for pads within one group
+
+ @param[in] Group GPIO group
+ @param[in] DwNum PadCfgLock register number for current group.
+ For group which has less then 32 pads per group DwNum must be 0.
+ @param[out] PadCfgLockRegVal Value of PadCfgLock register
+ Bit position - PadNumber
+ Bit value - 0: NotLocked, 1: Locked
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid group or DwNum parameter number
+**/
+EFI_STATUS
+GpioGetPadCfgLockForGroupDw (
+ IN GPIO_GROUP Group,
+ IN UINT32 DwNum,
+ OUT UINT32 *PadCfgLockRegVal
+ )
+{
+ if (!GpioIsGroupAndDwNumValid (Group, DwNum)) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ return GpioReadReg (
+ GpioPadConfigLockRegister,
+ Group,
+ DwNum,
+ PadCfgLockRegVal
+ );
+}
+/**
+ This procedure will check state of Pad Config Tx Lock for pads within one group
+
+ @param[in] Group GPIO group
+ @param[in] DwNum PadCfgLockTx register number for current group.
+ For group which has less then 32 pads per group DwNum must be 0.
+ @param[out] PadCfgLockTxRegVal Value of PadCfgLockTx register
+ Bit position - PadNumber
+ Bit value - 0: NotLockedTx, 1: LockedTx
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid group or DwNum parameter number
+**/
+EFI_STATUS
+GpioGetPadCfgLockTxForGroupDw (
+ IN GPIO_GROUP Group,
+ IN UINT32 DwNum,
+ OUT UINT32 *PadCfgLockTxRegVal
+ )
+{
+ if (!GpioIsGroupAndDwNumValid (Group, DwNum)) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ return GpioReadReg (
+ GpioPadLockOutputRegister,
+ Group,
+ DwNum,
+ PadCfgLockTxRegVal
+ );
+}
+/**
+ This procedure will clear PadCfgLock for selected pads within one group.
+ This function should be used only inside SMI.
+
+ @param[in] Group GPIO group
+ @param[in] DwNum PadCfgLock register number for current group.
+ For group which has less then 32 pads per group DwNum must be 0.
+ @param[in] PadsToUnlock Bitmask for pads which are going to be unlocked,
+ Bit position - PadNumber
+ Bit value - 0: DoNotUnlock, 1: Unlock
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid group or pad number
+**/
+EFI_STATUS
+GpioUnlockPadCfgForGroupDw (
+ IN GPIO_GROUP Group,
+ IN UINT32 DwNum,
+ IN UINT32 PadsToUnlock
+ )
+{
+ if (!GpioIsGroupAndDwNumValid (Group, DwNum)) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ return GpioWriteLockReg (
+ GpioPadConfigLockRegister,
+ Group,
+ DwNum,
+ ~PadsToUnlock,
+ 0
+ );
+}
+/**
+ This procedure will clear PadCfgLockTx for selected pads within one group.
+ This function should be used only inside SMI.
+
+ @param[in] Group GPIO group
+ @param[in] DwNum PadCfgLockTx register number for current group.
+ For group which has less then 32 pads per group DwNum must be 0.
+ @param[in] PadsToUnlockTx Bitmask for pads which are going to be unlocked,
+ Bit position - PadNumber
+ Bit value - 0: DoNotUnLockTx, 1: LockTx
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid group or pad number
+**/
+EFI_STATUS
+GpioUnlockPadCfgTxForGroupDw (
+ IN GPIO_GROUP Group,
+ IN UINT32 DwNum,
+ IN UINT32 PadsToUnlockTx
+ )
+{
+ if (!GpioIsGroupAndDwNumValid (Group, DwNum)) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ return GpioWriteLockReg (
+ GpioPadLockOutputRegister,
+ Group,
+ DwNum,
+ ~PadsToUnlockTx,
+ 0
+ );
+}
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/Library/PeiDxeSmmGpioLib/GpioLibrary.h b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/Library/PeiDxeSmmGpioLib/GpioLibrary.h
new file mode 100644
index 0000000000..2c2b4ee75c
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/Library/PeiDxeSmmGpioLib/GpioLibrary.h
@@ -0,0 +1,29 @@
+/** @file
+ Header file for GPIO Lib implementation.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _GPIO_LIBRARY_H_
+#define _GPIO_LIBRARY_H_
+
+#include <Base.h>
+#include <Uefi/UefiBaseType.h>
+#include <Library/IoLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/GpioLib.h>
+#include <Library/GpioNativeLib.h>
+#include <Library/GpioPrivateLib.h>
+#include <Library/PchInfoLib.h>
+#include <Library/PchCycleDecodingLib.h>
+#include <Library/PmcPrivateLib.h>
+#include <Library/GpioHelpersLib.h>
+#include <Register/GpioRegs.h>
+
+//
+// Number of PADCFG_DW registers
+//
+#define GPIO_PADCFG_DW_REG_NUMBER 4
+
+#endif // _GPIO_LIBRARY_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/Library/PeiDxeSmmGpioLib/GpioNativeLib.c b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/Library/PeiDxeSmmGpioLib/GpioNativeLib.c
new file mode 100644
index 0000000000..4e4c53e588
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/Library/PeiDxeSmmGpioLib/GpioNativeLib.c
@@ -0,0 +1,177 @@
+/** @file
+ This file contains routines for GPIO native and chipset specific usage
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#include "GpioLibrary.h"
+
+/**
+ This procedure will get number of pads for certain GPIO group
+
+ @param[in] Group GPIO group number
+
+ @retval Value Pad number for group
+ If illegal group number then return 0
+**/
+UINT32
+GpioGetPadPerGroup (
+ IN GPIO_GROUP Group
+ )
+{
+ CONST GPIO_GROUP_INFO *GpioGroupInfo;
+ UINT32 GpioGroupInfoLength;
+ UINT32 GroupIndex;
+ //
+ // Check if group argument exceeds GPIO GROUP INFO array
+ //
+ GpioGroupInfo = GpioGetGroupInfoTable (&GpioGroupInfoLength);
+ GroupIndex = GpioGetGroupIndexFromGroup (Group);
+
+ if ((UINTN) GroupIndex >= GpioGroupInfoLength) {
+ return 0;
+ } else {
+ return GpioGroupInfo[GroupIndex].PadPerGroup;
+ }
+}
+
+/**
+ This procedure will get number of groups
+
+ @param[in] none
+
+ @retval Value Group number
+**/
+UINT32
+GpioGetNumberOfGroups (
+ VOID
+ )
+{
+ UINT32 GpioGroupInfoLength;
+
+ GpioGetGroupInfoTable (&GpioGroupInfoLength);
+ return GpioGroupInfoLength;
+}
+/**
+ This procedure will get lowest group
+
+ @param[in] none
+
+ @retval Value Lowest Group
+**/
+GPIO_GROUP
+GpioGetLowestGroup (
+ VOID
+ )
+{
+ return GpioGetGroupFromGroupIndex (0);
+}
+/**
+ This procedure will get highest group
+
+ @param[in] none
+
+ @retval Value Highest Group
+**/
+GPIO_GROUP
+GpioGetHighestGroup (
+ VOID
+ )
+{
+ return GpioGetGroupFromGroupIndex (GpioGetNumberOfGroups () - 1);
+}
+
+/**
+ This procedure will get group number
+
+ @param[in] GpioPad Gpio Pad
+
+ @retval Value Group number
+**/
+GPIO_GROUP
+GpioGetGroupFromGpioPad (
+ IN GPIO_PAD GpioPad
+ )
+{
+ return GPIO_GET_GROUP_FROM_PAD (GpioPad);
+}
+
+/**
+ This procedure will get group index (0 based)
+
+ @param[in] GpioPad Gpio Pad
+
+ @retval Value Group Index
+**/
+UINT32
+GpioGetGroupIndexFromGpioPad (
+ IN GPIO_PAD GpioPad
+ )
+{
+ return (UINT32) GPIO_GET_GROUP_INDEX_FROM_PAD (GpioPad);
+}
+
+/**
+ This procedure will get group index (0 based) from group
+
+ @param[in] GpioGroup Gpio Group
+
+ @retval Value Group Index
+**/
+UINT32
+GpioGetGroupIndexFromGroup (
+ IN GPIO_GROUP GpioGroup
+ )
+{
+ return (UINT32) GPIO_GET_GROUP_INDEX (GpioGroup);
+}
+
+/**
+ This procedure will get group from group index (0 based)
+
+ @param[in] GroupIndex Group Index
+
+ @retval GpioGroup Gpio Group
+**/
+GPIO_GROUP
+GpioGetGroupFromGroupIndex (
+ IN UINT32 GroupIndex
+ )
+{
+ return GPIO_GROUP_DEF (GroupIndex, GpioGetThisChipsetId ());
+}
+
+/**
+ This procedure will get pad number (0 based) from Gpio Pad
+
+ @param[in] GpioPad Gpio Pad
+
+ @retval Value Pad Number
+**/
+UINT32
+GpioGetPadNumberFromGpioPad (
+ IN GPIO_PAD GpioPad
+ )
+{
+ return (UINT32) GPIO_GET_PAD_NUMBER (GpioPad);
+}
+/**
+ This procedure will return GpioPad from Group and PadNumber
+
+ @param[in] Group GPIO group
+ @param[in] PadNumber GPIO PadNumber
+
+ @retval GpioPad GpioPad
+**/
+GPIO_PAD
+GpioGetGpioPadFromGroupAndPadNumber (
+ IN GPIO_GROUP Group,
+ IN UINT32 PadNumber
+ )
+{
+ if (IsPchLp ()) {
+ return GPIO_PAD_DEF (Group,PadNumber);
+ } else {
+ return GPIO_PAD_DEF (Group,PadNumber);
+ }
+}
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/Library/PeiDxeSmmGpioLib/PeiDxeSmmGpioLib.inf b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/Library/PeiDxeSmmGpioLib/PeiDxeSmmGpioLib.inf
new file mode 100644
index 0000000000..21fb4417c1
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/Library/PeiDxeSmmGpioLib/PeiDxeSmmGpioLib.inf
@@ -0,0 +1,44 @@
+## @file
+# Component description file for the PeiDxeSmmGpioLib
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+
+[Defines]
+INF_VERSION = 0x00010017
+BASE_NAME = PeiDxeSmmGpioLib
+FILE_GUID = 16EC5CA8-8195-4847-B6CB-662BD7B763F2
+VERSION_STRING = 1.0
+MODULE_TYPE = BASE
+LIBRARY_CLASS = GpioLib
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = IA32 X64 IPF EBC
+#
+
+
+
+[LibraryClasses]
+BaseLib
+IoLib
+DebugLib
+PrintLib
+PchCycleDecodingLib
+PchSbiAccessLib
+PmcPrivateLib
+GpioPrivateLib
+GpioHelpersLib
+
+[Packages]
+MdePkg/MdePkg.dec
+AlderlakeSiliconPkg/SiPkg.dec
+
+
+[Sources]
+GpioLib.c
+GpioNativeLib.c
+GpioInit.c
+GpioLibrary.h
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/BaseGpioHelpersLibNull/BaseGpioHelpersLibNull.c b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/BaseGpioHelpersLibNull/BaseGpioHelpersLibNull.c
new file mode 100644
index 0000000000..b4b6c14329
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/BaseGpioHelpersLibNull/BaseGpioHelpersLibNull.c
@@ -0,0 +1,51 @@
+/** @file
+ This file contains NULL implementation for GPIO Helpers Lib
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#include <Uefi/UefiBaseType.h>
+#include <Library/GpioConfig.h>
+
+/**
+ This procedure stores GPIO group data about pads which PadConfig needs to be unlocked.
+
+ @param[in] GroupIndex GPIO group index
+ @param[in] DwNum DWORD index for a group.
+ For group which has less then 32 pads per group DwNum must be 0.
+ @param[in] UnlockedPads DWORD bitmask for pads which are going to be left unlocked
+ Bit position - PadNumber
+ Bit value - 0: Skip, 1: Leave unlocked
+
+ @retval Status
+**/
+EFI_STATUS
+GpioStoreGroupDwUnlockPadConfigData (
+ IN UINT32 GroupIndex,
+ IN UINT32 DwNum,
+ IN UINT32 UnlockedPads
+ )
+{
+ return EFI_SUCCESS;
+}
+
+/**
+ This procedure stores GPIO group data about pads which Output state needs to be unlocked.
+
+ @param[in] GroupIndex GPIO group index
+ @param[in] DwNum DWORD index for a group.
+ For group which has less then 32 pads per group DwNum must be 0.
+ @param[in] UnlockedPads DWORD bitmask for pads which are going to be left unlocked
+ Bit position - PadNumber
+ Bit value - 0: Skip, 1: Leave unlocked
+ @retval Status
+**/
+EFI_STATUS
+GpioStoreGroupDwUnlockOutputData (
+ IN UINT32 GroupIndex,
+ IN UINT32 DwNum,
+ IN UINT32 UnlockedPads
+ )
+{
+ return EFI_SUCCESS;
+}
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/BaseGpioHelpersLibNull/BaseGpioHelpersLibNull.inf b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/BaseGpioHelpersLibNull/BaseGpioHelpersLibNull.inf
new file mode 100644
index 0000000000..91d81af4b9
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/BaseGpioHelpersLibNull/BaseGpioHelpersLibNull.inf
@@ -0,0 +1,25 @@
+## @file
+# Component description file for the NULL GpioHelpersLib
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+
+[Defines]
+INF_VERSION = 0x00010017
+BASE_NAME = BaseGpioHelpersLib
+FILE_GUID = AB282608-2A50-4AE3-9242-64064ECF40D4
+VERSION_STRING = 1.0
+MODULE_TYPE = BASE
+LIBRARY_CLASS = GpioHelpersLib
+
+
+[Packages]
+MdePkg/MdePkg.dec
+AlderlakeSiliconPkg/SiPkg.dec
+
+
+[Sources]
+BaseGpioHelpersLibNull.c
+
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiDxeSmmGpioPrivateLib/GpioNativePrivateLibInternal.h b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiDxeSmmGpioPrivateLib/GpioNativePrivateLibInternal.h
new file mode 100644
index 0000000000..480990cb62
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiDxeSmmGpioPrivateLib/GpioNativePrivateLibInternal.h
@@ -0,0 +1,48 @@
+/** @file
+ Header file for GPIO Private Lib Internal functions.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _GPIO_NATIVE_PRIVATE_LIB_INTERNAL_H_
+#define _GPIO_NATIVE_PRIVATE_LIB_INTERNAL_H_
+
+#include <Library/GpioPrivateLib.h>
+
+
+/**
+ This function provides recommended GPIO IO Standby configuration for a given native function
+
+ @param[in] PadFunction PadFunction for a specific native signal. Please refer to GpioNativePads.h
+ @param[out] StandbyState IO Standby State for specified native function
+ @param[out] StandbyTerm IO Standby Termination for specified native function
+
+ @retval Status
+**/
+EFI_STATUS
+GpioGetFunctionIoStandbyConfig (
+ IN UINT32 PadFunction,
+ OUT GPIO_IOSTANDBY_STATE *StandbyState,
+ OUT GPIO_IOSTANDBY_TERM *StandbyTerm
+ );
+
+/**
+ This procedure will calculate PADCFG register value based on GpioConfig data
+ For physical/local/hard (not virtual) GPIO pads
+
+ @param[in] GpioPad GPIO Pad
+ @param[in] GpioConfig GPIO Configuration data
+ @param[out] PadCfgDwReg PADCFG DWx register value
+ @param[out] PadCfgDwRegMask Mask with PADCFG DWx register bits to be modified
+
+ @retval Status
+**/
+EFI_STATUS
+GpioPadCfgRegValueFromGpioConfigHardGpio (
+ IN GPIO_PAD GpioPad,
+ IN CONST GPIO_CONFIG *GpioConfig,
+ OUT UINT32 *PadCfgDwReg,
+ OUT UINT32 *PadCfgDwRegMask
+ );
+
+#endif // _GPIO_NATIVE_PRIVATE_LIB_INTERNAL_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiDxeSmmGpioPrivateLib/GpioPrivateLib.c b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiDxeSmmGpioPrivateLib/GpioPrivateLib.c
new file mode 100644
index 0000000000..7d5fa9fafd
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiDxeSmmGpioPrivateLib/GpioPrivateLib.c
@@ -0,0 +1,267 @@
+/** @file
+ This file contains GPIO routines for RC usage
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#include <Base.h>
+#include <Uefi/UefiBaseType.h>
+#include <Library/IoLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/GpioLib.h>
+#include <Library/GpioNativeLib.h>
+#include <Library/GpioPrivateLib.h>
+#include <Library/GpioNativePads.h>
+#include <Register/GpioRegs.h>
+#include "GpioNativePrivateLibInternal.h"
+
+/**
+ This procedure is used to check if GpioPad is valid for certain chipset
+
+ @param[in] GpioPad GPIO pad
+
+ @retval TRUE This pin is valid on this chipset
+ FALSE Incorrect pin
+**/
+BOOLEAN
+GpioIsCorrectPadForThisChipset (
+ IN GPIO_PAD GpioPad
+ )
+{
+ return ((GPIO_GET_CHIPSET_ID (GpioPad) == GpioGetThisChipsetId ()) &&
+ (GpioGetGroupIndexFromGpioPad (GpioPad) < GpioGetNumberOfGroups ()));
+}
+
+/**
+ This procedure is used by PchSmiDispatcher and will return information
+ needed to register GPI SMI.
+
+ @param[in] Index GPI SMI number
+ @param[out] GpioPin GPIO pin
+ @param[out] GpiSmiBitOffset GPI SMI bit position within GpiSmi Registers
+ @param[out] GpiHostSwOwnRegAddress Address of HOSTSW_OWN register
+ @param[out] GpiSmiStsRegAddress Address of GPI SMI status register
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid group or pad number
+**/
+EFI_STATUS
+GpioGetPadAndSmiRegs (
+ IN UINT32 Index,
+ OUT GPIO_PAD *GpioPin,
+ OUT UINT8 *GpiSmiBitOffset,
+ OUT UINT32 *GpiHostSwOwnRegAddress,
+ OUT UINT32 *GpiSmiStsRegAddress
+ )
+{
+ UINT32 GroupIndex;
+ UINT32 PadNumber;
+ CONST GPIO_GROUP_INFO *GpioGroupInfo;
+ GPIO_GROUP GpioGroup;
+ UINT32 GpioGroupInfoLength;
+ UINT32 SmiStsRegOffset;
+ UINT32 HostSwOwnRegOffset;
+ GPIO_PAD_OWN PadOwnVal;
+
+ GpioGroupInfo = GpioGetGroupInfoTable (&GpioGroupInfoLength);
+
+ PadNumber = 0;
+ GroupIndex = 0;
+ for (GroupIndex = 0; GroupIndex < GpioGroupInfoLength; GroupIndex++) {
+ PadNumber = Index;
+ if (PadNumber < GpioGroupInfo[GroupIndex].PadPerGroup) {
+ //
+ // Found group and pad number
+ //
+ break;
+ }
+ Index = Index - GpioGroupInfo[GroupIndex].PadPerGroup;
+ }
+
+ //
+ // Check if legal pad number
+ //
+ if (PadNumber >= GpioGroupInfo[GroupIndex].PadPerGroup){
+ return EFI_INVALID_PARAMETER;
+ }
+
+ //
+ // Check if selected group has GPI SMI Enable and Status registers
+ //
+ if (GpioGroupInfo[GroupIndex].SmiEnOffset == NO_REGISTER_FOR_PROPERTY) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ GpioGroup = GpioGetGroupFromGroupIndex (GroupIndex);
+ *GpioPin = GpioGetGpioPadFromGroupAndPadNumber (GpioGroup, PadNumber);
+
+ DEBUG_CODE_BEGIN ();
+ //
+ // Check if selected GPIO Pad is not owned by CSME/ISH/IE
+ //
+ GpioGetPadOwnership (*GpioPin, &PadOwnVal);
+ if (PadOwnVal != GpioPadOwnHost) {
+ DEBUG ((DEBUG_ERROR, "GPIO ERROR: GPIO not owned by host!\n"));
+ return EFI_INVALID_PARAMETER;
+ }
+ DEBUG_CODE_END ();
+
+ *GpiSmiBitOffset = (UINT8)(PadNumber % 32);
+
+ HostSwOwnRegOffset = GpioGroupInfo[GroupIndex].HostOwnOffset + (PadNumber / 32) * 0x4;
+ *GpiHostSwOwnRegAddress = PCH_PCR_ADDRESS (GpioGroupInfo[GroupIndex].Community, HostSwOwnRegOffset);
+
+ SmiStsRegOffset = GpioGroupInfo[GroupIndex].SmiStsOffset + (PadNumber / 32) * 0x4;
+ *GpiSmiStsRegAddress = PCH_PCR_ADDRESS (GpioGroupInfo[GroupIndex].Community, SmiStsRegOffset);
+
+ return EFI_SUCCESS;
+}
+
+/**
+ This procedure will check if GpioPad argument is valid.
+ Function will check below conditions:
+ - GpioPad represents a pad for current PCH
+ - GpioPad belongs to valid GpioGroup
+ - GPIO PadNumber is not greater than number of pads for this group
+
+ @param[in] GpioPad GPIO pad
+
+ @retval TRUE GPIO pad is valid and can be used with GPIO lib API
+ @retval FALSE GPIO pad is invalid and cannot be used with GPIO lib API
+**/
+BOOLEAN
+GpioIsPadValid (
+ IN GPIO_PAD GpioPad
+ )
+{
+ CONST GPIO_GROUP_INFO *GpioGroupInfo;
+ UINT32 GpioGroupInfoLength;
+ UINT32 PadNumber;
+ UINT32 GroupIndex;
+
+ if (!GpioIsCorrectPadForThisChipset (GpioPad)) {
+ DEBUG ((DEBUG_ERROR, "GPIO ERROR: Incorrect GpioPad (0x%08x) used on this chipset!\n", GpioPad));
+ goto Error;
+ }
+
+ GpioGroupInfo = GpioGetGroupInfoTable (&GpioGroupInfoLength);
+
+ //
+ // Check if legal pin number
+ //
+ GroupIndex = GpioGetGroupIndexFromGpioPad (GpioPad);
+ PadNumber = GpioGetPadNumberFromGpioPad (GpioPad);
+ if (PadNumber >= GpioGroupInfo[GroupIndex].PadPerGroup) {
+ DEBUG ((DEBUG_ERROR, "GPIO ERROR: Pin number (%d) exceeds range of group (max: %d)\n",
+ PadNumber,
+ GpioGroupInfo[GroupIndex].PadPerGroup));
+ goto Error;
+ }
+
+ return TRUE;
+Error:
+ ASSERT (FALSE);
+ return FALSE;
+}
+
+/**
+ This procedure will read GPIO Pad Configuration register
+
+ @param[in] GpioPad GPIO pad
+ @param[in] DwReg Choose PADCFG register: 0:DW0, 1:DW1
+
+ @retval PadCfgRegValue PADCFG_DWx value
+**/
+UINT32
+GpioReadPadCfgReg (
+ IN GPIO_PAD GpioPad,
+ IN UINT8 DwReg
+ )
+{
+ UINT32 PadCfgReg;
+ CONST GPIO_GROUP_INFO *GpioGroupInfo;
+ UINT32 GpioGroupInfoLength;
+ UINT32 GroupIndex;
+
+ GroupIndex = GpioGetGroupIndexFromGpioPad (GpioPad);
+ GpioGroupInfo = GpioGetGroupInfoTable (&GpioGroupInfoLength);
+
+ //
+ // Create Pad Configuration register offset
+ //
+ PadCfgReg = GpioGetGpioPadCfgAddressFromGpioPad (GpioPad, DwReg);
+ return GpioRegisterAccessRead32 (&GpioGroupInfo[GroupIndex], PadCfgReg);
+}
+
+
+/**
+ This procedure will calculate PADCFG register value based on GpioConfig data
+ For physical/local/hard (not virtual) GPIO pads
+
+ @param[in] GpioPad GPIO Pad
+ @param[in] GpioConfig GPIO Configuration data
+ @param[out] PadCfgDwReg PADCFG DWx register value
+ @param[out] PadCfgDwRegMask Mask with PADCFG DWx register bits to be modified
+
+ @retval Status
+**/
+EFI_STATUS
+GpioPadCfgRegValueFromGpioConfigHardGpio (
+ IN GPIO_PAD GpioPad,
+ IN CONST GPIO_CONFIG *GpioConfig,
+ OUT UINT32 *PadCfgDwReg,
+ OUT UINT32 *PadCfgDwRegMask
+ )
+{
+ //
+ // Configure how interrupt is triggered (RxEvCfg)
+ //
+ PadCfgDwRegMask[0] |= ((((GpioConfig->InterruptConfig & B_GPIO_INT_CONFIG_INT_TYPE_MASK) >> N_GPIO_INT_CONFIG_INT_TYPE_BIT_POS) == GpioHardwareDefault) ? 0x0 : B_GPIO_PCR_RX_LVL_EDG);
+ PadCfgDwReg[0] |= (((GpioConfig->InterruptConfig & B_GPIO_INT_CONFIG_INT_TYPE_MASK) >> (N_GPIO_INT_CONFIG_INT_TYPE_BIT_POS + 1)) << N_GPIO_PCR_RX_LVL_EDG);
+
+ //
+ // Configure interrupt generation (GPIRoutIOxAPIC/SCI/SMI/NMI)
+ //
+ PadCfgDwRegMask[0] |= ((((GpioConfig->InterruptConfig & B_GPIO_INT_CONFIG_INT_SOURCE_MASK) >> N_GPIO_INT_CONFIG_INT_SOURCE_BIT_POS) == GpioHardwareDefault) ? 0x0 : (B_GPIO_PCR_RX_NMI_ROUTE | B_GPIO_PCR_RX_SCI_ROUTE | B_GPIO_PCR_RX_SMI_ROUTE | B_GPIO_PCR_RX_APIC_ROUTE));
+ PadCfgDwReg[0] |= (((GpioConfig->InterruptConfig & B_GPIO_INT_CONFIG_INT_SOURCE_MASK) >> (N_GPIO_INT_CONFIG_INT_SOURCE_BIT_POS + 1)) << N_GPIO_PCR_RX_NMI_ROUTE);
+
+ //
+ // Configure GPIO direction (GPIORxDis and GPIOTxDis)
+ //
+ PadCfgDwRegMask[0] |= ((((GpioConfig->Direction & B_GPIO_DIRECTION_DIR_MASK) >> N_GPIO_DIRECTION_DIR_BIT_POS) == GpioHardwareDefault) ? 0x0 : (B_GPIO_PCR_RXDIS | B_GPIO_PCR_TXDIS));
+ PadCfgDwReg[0] |= (((GpioConfig->Direction & B_GPIO_DIRECTION_DIR_MASK) >> (N_GPIO_DIRECTION_DIR_BIT_POS + 1)) << N_GPIO_PCR_TXDIS);
+
+ //
+ // Configure GPIO input inversion (RXINV)
+ //
+ PadCfgDwRegMask[0] |= ((((GpioConfig->Direction & B_GPIO_DIRECTION_INV_MASK) >> N_GPIO_DIRECTION_INV_BIT_POS) == GpioHardwareDefault) ? 0x0 : B_GPIO_PCR_RXINV);
+ PadCfgDwReg[0] |= (((GpioConfig->Direction & B_GPIO_DIRECTION_INV_MASK) >> (N_GPIO_DIRECTION_INV_BIT_POS + 1)) << N_GPIO_PCR_RXINV);
+
+ //
+ // Configure GPIO output state (GPIOTxState)
+ //
+ PadCfgDwRegMask[0] |= ((((GpioConfig->OutputState & B_GPIO_OUTPUT_MASK) >> N_GPIO_OUTPUT_BIT_POS) == GpioHardwareDefault) ? 0x0 : B_GPIO_PCR_TX_STATE);
+ PadCfgDwReg[0] |= (((GpioConfig->OutputState & B_GPIO_OUTPUT_MASK) >> (N_GPIO_OUTPUT_BIT_POS + 1)) << N_GPIO_PCR_TX_STATE);
+
+ //
+ // Configure GPIO RX raw override to '1' (RXRAW1)
+ //
+ PadCfgDwRegMask[0] |= ((((GpioConfig->OtherSettings & B_GPIO_OTHER_CONFIG_RXRAW_MASK) >> N_GPIO_OTHER_CONFIG_RXRAW_BIT_POS) == GpioHardwareDefault) ? 0x0 : B_GPIO_PCR_RX_RAW1);
+ PadCfgDwReg[0] |= (((GpioConfig->OtherSettings & B_GPIO_OTHER_CONFIG_RXRAW_MASK) >> (N_GPIO_OTHER_CONFIG_RXRAW_BIT_POS + 1)) << N_GPIO_PCR_RX_RAW1);
+
+ //
+ // Configure GPIO Pad Mode (PMode)
+ //
+ PadCfgDwRegMask[0] |= ((((GpioConfig->PadMode & B_GPIO_PAD_MODE_MASK) >> N_GPIO_PAD_MODE_BIT_POS) == GpioHardwareDefault) ? 0x0 : B_GPIO_PCR_PAD_MODE);
+ PadCfgDwReg[0] |= (((GpioConfig->PadMode & B_GPIO_PAD_MODE_MASK) >> (N_GPIO_PAD_MODE_BIT_POS + 1)) << N_GPIO_PCR_PAD_MODE);
+
+ //
+ // Configure GPIO termination (Term)
+ //
+ PadCfgDwRegMask[1] |= ((((GpioConfig->ElectricalConfig & B_GPIO_ELECTRICAL_CONFIG_TERMINATION_MASK) >> N_GPIO_ELECTRICAL_CONFIG_TERMINATION_BIT_POS) == GpioHardwareDefault) ? 0x0 : B_GPIO_PCR_TERM);
+ PadCfgDwReg[1] |= (((GpioConfig->ElectricalConfig & B_GPIO_ELECTRICAL_CONFIG_TERMINATION_MASK) >> (N_GPIO_ELECTRICAL_CONFIG_TERMINATION_BIT_POS + 1)) << N_GPIO_PCR_TERM);
+
+ return EFI_SUCCESS;
+}
+
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiDxeSmmGpioPrivateLib/GpioPrivateLibPch.c b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiDxeSmmGpioPrivateLib/GpioPrivateLibPch.c
new file mode 100644
index 0000000000..3d16fd2acd
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiDxeSmmGpioPrivateLib/GpioPrivateLibPch.c
@@ -0,0 +1,172 @@
+/** @file
+ This file contains hard/physical/local (not virtual) GPIO information
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#include <Uefi/UefiBaseType.h>
+#include <Library/GpioLib.h>
+#include <Library/GpioPrivateLib.h>
+#include <Library/GpioNativeLib.h>
+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+#include <Library/PchSbiAccessLib.h>
+#include <Register/GpioRegs.h>
+#include "GpioNativePrivateLibInternal.h"
+
+/**
+ This procedure calculates Pad Configuration Register DW offset
+
+ @param[in] GpioPad GPIO pad
+ @param[in] DwReg Index of the configuration register
+
+ @retval DW Register offset
+**/
+UINT32
+GpioGetGpioPadCfgAddressFromGpioPad (
+ IN GPIO_PAD GpioPad,
+ IN UINT32 DwReg
+ )
+{
+ UINT32 PadCfgRegAddress;
+ CONST GPIO_GROUP_INFO *GpioGroupInfo;
+ UINT32 GpioGroupInfoLength;
+ UINT32 GroupIndex;
+ UINT32 PadNumber;
+
+ GroupIndex = GpioGetGroupIndexFromGpioPad (GpioPad);
+ PadNumber = GpioGetPadNumberFromGpioPad (GpioPad);
+
+ GpioGroupInfo = GpioGetGroupInfoTable (&GpioGroupInfoLength);
+
+ //
+ // Create Pad Configuration register offset
+ //
+ PadCfgRegAddress = GpioGroupInfo[GroupIndex].PadCfgOffset + DwReg * 4 + S_GPIO_PCR_PADCFG * PadNumber;
+
+ return PadCfgRegAddress;
+}
+
+/**
+ This procedure reads GPIO register
+
+ @param[in] GpioGroupInfo Pointer to GPIO group table info
+ @param[in] Register Register offset
+
+ @retval Register value or "F"s in case of errors
+**/
+UINT32
+GpioRegisterAccessRead32 (
+ IN CONST GPIO_GROUP_INFO *GpioGroupInfo,
+ IN UINT32 Register
+ )
+{
+ return MmioRead32 (PCH_PCR_ADDRESS (GpioGroupInfo->Community, Register));
+}
+
+/**
+ This procedure writes GPIO register
+
+ @param[in] GpioGroupInfo Pointer to GPIO group table info
+ @param[in] Register Register offset
+ @param[in] AndValue And value
+ @param[in] OrValue Or value
+
+ @retval EFI_SUCCESS Operation completed successfully
+**/
+EFI_STATUS
+GpioRegisterAccessAndThenOr32 (
+ IN CONST GPIO_GROUP_INFO *GpioGroupInfo,
+ IN UINT32 Register,
+ IN UINT32 AndValue,
+ IN UINT32 OrValue
+ )
+{
+ MmioAndThenOr32 (
+ PCH_PCR_ADDRESS (GpioGroupInfo->Community, Register),
+ AndValue,
+ OrValue
+ );
+ return EFI_SUCCESS;
+}
+
+/**
+ This procedure will calculate PADCFG register value based on GpioConfig data
+
+ @param[in] GpioPad GPIO Pad
+ @param[in] GpioConfig GPIO Configuration data
+ @param[out] PadCfgDwReg PADCFG DWx register value
+ @param[out] PadCfgDwRegMask Mask with PADCFG DWx register bits to be modified
+
+ @retval Status
+**/
+EFI_STATUS
+GpioPadCfgRegValueFromGpioConfig (
+ IN GPIO_PAD GpioPad,
+ IN CONST GPIO_CONFIG *GpioConfig,
+ OUT UINT32 *PadCfgDwReg,
+ OUT UINT32 *PadCfgDwRegMask
+ )
+{
+ return GpioPadCfgRegValueFromGpioConfigHardGpio (GpioPad, GpioConfig, PadCfgDwReg, PadCfgDwRegMask);
+}
+
+/**
+ This procedure will write GPIO Lock/LockTx register
+ - For PCH SBI message is used.
+
+ @param[in] RegValue GPIO register (Lock or LockTx) value
+ @param[in] RegOffset GPIO register (Lock or LockTx) base offset
+ @param[in] DwNum Register number for current group.
+ For group which has less then 32 pads per group DwNum must be 0.
+ @param[in] GpioGroupInfo Pointer to GPIO group table info
+ @param[in] GroupIndex GPIO group index in the GpioGroupInfo table
+
+ @retval EFI_SUCCESS The function completed successfully
+ EFI_UNSUPPORTED Feature is not supported for this group or pad
+**/
+EFI_STATUS
+GpioInternalWriteLockRegister (
+ IN UINT32 RegValue,
+ IN UINT32 RegOffset,
+ IN UINT32 DwNum,
+ IN CONST GPIO_GROUP_INFO *GpioGroupInfo,
+ IN UINT32 GroupIndex
+ )
+{
+ EFI_STATUS Status;
+ PCH_SBI_OPCODE Opcode;
+ UINT8 Response;
+
+ //
+ // If there are more then 32 pads per group then certain
+ // group information would be split into more then one DWord register.
+ // PadConfigLock and OutputLock registers when used for group containing more than 32 pads
+ // are not placed in a continuous way, e.g:
+ // 0x0 - PadConfigLock_DW0
+ // 0x4 - OutputLock_DW0
+ // 0x8 - PadConfigLock_DW1
+ // 0xC - OutputLock_DW1
+ //
+ RegOffset += DwNum * 0x8;
+
+ if (IsGpioLockOpcodeSupported ()) {
+ Opcode = GpioLockUnlock;
+ } else {
+ Opcode = PrivateControlWrite;
+ }
+
+ Status = PchSbiExecutionEx (
+ GpioGroupInfo[GroupIndex].Community,
+ RegOffset,
+ Opcode,
+ FALSE,
+ 0x000F,
+ 0x0000,
+ 0x0000,
+ &RegValue,
+ &Response
+ );
+ ASSERT_EFI_ERROR (Status);
+ return Status;
+}
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiDxeSmmGpioPrivateLib/GpioPrivateLibVer2.c b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiDxeSmmGpioPrivateLib/GpioPrivateLibVer2.c
new file mode 100644
index 0000000000..1348643553
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiDxeSmmGpioPrivateLib/GpioPrivateLibVer2.c
@@ -0,0 +1,81 @@
+/** @file
+ This file contains VER2 specific GPIO information
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#include <Uefi/UefiBaseType.h>
+#include <Library/DebugLib.h>
+#include <Library/PchInfoLib.h>
+#include <Library/GpioLib.h>
+#include <Library/GpioNativeLib.h>
+#include <Library/GpioNativePads.h>
+#include <Library/GpioPrivateLib.h>
+#include <Library/GpioHelpersLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/IoLib.h>
+#include <Register/GpioRegsVer2.h>
+#include <Register/PchPcrRegs.h>
+#include <Register/GpioRegs.h>
+#include <Pins/GpioPinsVer2Lp.h>
+#include <GpioNativePrivateLibInternal.h>
+#include <Library/PcdLib.h>
+GLOBAL_REMOVE_IF_UNREFERENCED GPIO_GROUP_INFO mPchLpGpioGroupInfo[] = {
+ {PID_GPIOCOM0, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_PAD_OWN, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_HOSTSW_OWN, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_GPI_IS, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_GPI_IE, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_GPI_GPE_STS, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_GPI_GPE_EN, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_SMI_STS, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_SMI_EN, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_NMI_STS, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_NMI_EN, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_PADCFGLOCK, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_PADCFGLOCKTX, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_PADCFG_OFFSET, GPIO_VER2_PCH_LP_GPIO_GPP_B_PAD_MAX}, //TGL PCH-LP GPP_B
+ {PID_GPIOCOM0, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, 0},
+ {PID_GPIOCOM0, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_A_PAD_OWN, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_A_HOSTSW_OWN, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_A_GPI_IS, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_A_GPI_IE, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_A_GPI_GPE_STS, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_A_GPI_GPE_EN, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_A_PADCFGLOCK, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_A_PADCFGLOCKTX, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_A_PADCFG_OFFSET, GPIO_VER2_PCH_LP_GPIO_GPP_A_PAD_MAX}, //TGL PCH-LP GPP_A
+ {PID_GPIOCOM5, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_R_PAD_OWN, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_R_HOSTSW_OWN, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_R_GPI_IS, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_R_GPI_IE, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_R_GPI_GPE_STS, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_R_GPI_GPE_EN, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_R_PADCFGLOCK, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_R_PADCFGLOCKTX, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_R_PADCFG_OFFSET, GPIO_VER2_PCH_LP_GPIO_GPP_R_PAD_MAX}, //TGL PCH-LP GPP_R
+ {PID_GPIOCOM5, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, 0},
+ {PID_GPIOCOM2, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPD_PAD_OWN, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPD_HOSTSW_OWN, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPD_GPI_IS, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPD_GPI_IE, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPD_GPI_GPE_STS, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPD_GPI_GPE_EN, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPD_PADCFGLOCK, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPD_PADCFGLOCKTX, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPD_PADCFG_OFFSET, GPIO_VER2_PCH_LP_GPIO_GPD_PAD_MAX}, //TGL PCH-LP GPD
+ {PID_GPIOCOM1, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_S_PAD_OWN, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_S_HOSTSW_OWN, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_S_GPI_IS, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_S_GPI_IE, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_S_GPI_GPE_STS, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_S_GPI_GPE_EN, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_S_PADCFGLOCK, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_S_PADCFGLOCKTX, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_S_PADCFG_OFFSET, GPIO_VER2_PCH_LP_GPIO_GPP_S_PAD_MAX}, //TGL PCH-LP GPP_S
+ {PID_GPIOCOM1, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_H_PAD_OWN, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_H_HOSTSW_OWN, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_H_GPI_IS, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_H_GPI_IE, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_H_GPI_GPE_STS, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_H_GPI_GPE_EN, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_H_PADCFGLOCK, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_H_PADCFGLOCKTX, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_H_PADCFG_OFFSET, GPIO_VER2_PCH_LP_GPIO_GPP_H_PAD_MAX}, //TGL PCH-LP GPP_H
+ {PID_GPIOCOM1, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_PAD_OWN, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_HOSTSW_OWN, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_GPI_IS, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_GPI_IE, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_GPI_GPE_STS, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_GPI_GPE_EN, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_SMI_STS, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_SMI_EN, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_NMI_STS, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_NMI_EN, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_PADCFGLOCK, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_PADCFGLOCKTX, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_PADCFG_OFFSET, GPIO_VER2_PCH_LP_GPIO_GPP_D_PAD_MAX}, //TGL PCH-LP GPP_D
+ {PID_GPIOCOM1, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, 0},
+ {PID_GPIOCOM1, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, 0},
+ {PID_GPIOCOM4, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_PAD_OWN, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_HOSTSW_OWN, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_GPI_IS, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_GPI_IE, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_GPI_GPE_STS, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_GPI_GPE_EN, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_SMI_STS, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_SMI_EN, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_NMI_STS, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_NMI_EN, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_PADCFGLOCK, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_PADCFGLOCKTX, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_PADCFG_OFFSET, GPIO_VER2_PCH_LP_GPIO_GPP_C_PAD_MAX}, //TGL PCH-LP GPP_C
+ {PID_GPIOCOM4, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_F_PAD_OWN, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_F_HOSTSW_OWN, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_F_GPI_IS, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_F_GPI_IE, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_F_GPI_GPE_STS, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_F_GPI_GPE_EN, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_F_PADCFGLOCK, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_F_PADCFGLOCKTX, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_F_PADCFG_OFFSET, GPIO_VER2_PCH_LP_GPIO_GPP_F_PAD_MAX}, //TGL PCH-LP GPP_F
+ {PID_GPIOCOM4, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, 0},
+ {PID_GPIOCOM4, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_PAD_OWN, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_HOSTSW_OWN, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_GPI_IS, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_GPI_IE, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_GPI_GPE_STS, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_GPI_GPE_EN, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_SMI_STS, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_SMI_EN, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_NMI_STS, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_NMI_EN, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_PADCFGLOCK, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_PADCFGLOCKTX, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_PADCFG_OFFSET, GPIO_VER2_PCH_LP_GPIO_GPP_E_PAD_MAX}, //TGL PCH-LP GPP_E
+};
+
+/**
+ This procedure will retrieve address and length of GPIO info table
+
+ @param[out] GpioGroupInfoTableLength Length of GPIO group table
+
+ @retval Pointer to GPIO group table
+
+**/
+CONST GPIO_GROUP_INFO*
+GpioGetGroupInfoTable (
+ OUT UINT32 *GpioGroupInfoTableLength
+ )
+{
+ *GpioGroupInfoTableLength = ARRAY_SIZE (mPchLpGpioGroupInfo);
+ return mPchLpGpioGroupInfo;
+}
+
+/**
+ Get GPIO Chipset ID specific to PCH generation and series
+**/
+UINT32
+GpioGetThisChipsetId (
+ VOID
+ )
+{
+ return GPIO_VER2_LP_CHIPSET_ID;
+}
+
+/**
+ Check if 0x13 opcode supported for writing to GPIO lock unlock register
+
+ @retval TRUE It's supported
+ @retval FALSE It's not supported
+**/
+BOOLEAN
+IsGpioLockOpcodeSupported (
+ VOID
+ )
+{
+ return TRUE;
+}
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiDxeSmmGpioPrivateLib/PeiDxeSmmGpioPrivateLibVer2.inf b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiDxeSmmGpioPrivateLib/PeiDxeSmmGpioPrivateLibVer2.inf
new file mode 100644
index 0000000000..2e9a6b7336
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiDxeSmmGpioPrivateLib/PeiDxeSmmGpioPrivateLibVer2.inf
@@ -0,0 +1,40 @@
+## @file
+# Component description file for the PeiDxeSmmGpioPrivateLib
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+[Defines]
+INF_VERSION = 0x00010017
+BASE_NAME = PeiDxeSmmGpioPrivateLibVer2
+FILE_GUID = 680A81B0-A087-4687-B5B4-146DA30042D6
+VERSION_STRING = 1.0
+MODULE_TYPE = BASE
+LIBRARY_CLASS = GpioPrivateLib
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = IA32 X64 IPF EBC
+#
+
+
+[LibraryClasses]
+ BaseLib
+ IoLib
+ DebugLib
+ PmcLib
+ PchInfoLib
+ GpioLib
+ GpioHelpersLib
+
+
+[Packages]
+ MdePkg/MdePkg.dec
+ AlderlakeSiliconPkg/SiPkg.dec
+
+
+[Sources]
+ GpioPrivateLib.c
+ GpioPrivateLibVer2.c
+ GpioPrivateLibPch.c
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiGpioHelpersLib/PeiGpioHelpersLib.c b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiGpioHelpersLib/PeiGpioHelpersLib.c
new file mode 100644
index 0000000000..9d47e6bfd5
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiGpioHelpersLib/PeiGpioHelpersLib.c
@@ -0,0 +1,218 @@
+/** @file
+ This file contains routines for PEI GPIO Helpers Lib
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#include <Library/HobLib.h>
+#include <Base.h>
+#include <Uefi/UefiBaseType.h>
+#include <Library/IoLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/GpioNativeLib.h>
+#include <Library/GpioPrivateLib.h>
+#include <Library/GpioHelpersLib.h>
+#include <Library/PeiServicesLib.h>
+#include <Library/ConfigBlockLib.h>
+#include <Ppi/SiPolicy.h>
+
+extern EFI_GUID gGpioLibUnlockHobGuid;
+
+//
+// GPIO Lock HOB
+// Stores information on GPIO pads that should be left unlocked
+//
+typedef struct {
+ //
+ // GPIO PadConfig unlock data
+ //
+ UINT32 PadConfig;
+ //
+ // GPIO Output unlock data
+ //
+ UINT32 OutputState;
+} GPIO_UNLOCK_HOB_DATA;
+
+/**
+ This procedure will get index of GPIO Unlock HOB structure for selected GroupIndex and DwNum.
+
+ @param[in] GroupIndex GPIO group index
+ @param[in] DwNum DWORD index for a group.
+ For group which has less then 32 pads per group DwNum must be 0.
+
+ @retval GpioUnlockHobIndex
+**/
+STATIC
+UINT32
+GpioUnlockDataIndex (
+ IN UINT32 GroupIndex,
+ IN UINT32 DwNum
+ )
+{
+ UINT32 GpioUnlockDataIndex;
+ UINT32 Index;
+
+ GpioUnlockDataIndex = 0;
+
+ for (Index = 0; Index < GroupIndex; Index++) {
+ GpioUnlockDataIndex += GPIO_GET_DW_NUM (GpioGetPadPerGroup (GpioGetGroupFromGroupIndex (Index))) + 1;
+ }
+
+ GpioUnlockDataIndex += DwNum;
+ return GpioUnlockDataIndex;
+}
+
+/**
+ This procedure will create GPIO HOB for storing unlock data
+
+ @retval Pointer to GPIO Unlock data structure
+**/
+STATIC
+GPIO_UNLOCK_HOB_DATA*
+GpioCreateUnlockData (
+ VOID
+ )
+{
+ VOID *HobData;
+ GPIO_GROUP Group;
+ GPIO_GROUP GroupMin;
+ GPIO_GROUP GroupMax;
+ UINT32 GpioUnlockDataRecords;
+
+ GroupMin = GpioGetLowestGroup ();
+ GroupMax = GpioGetHighestGroup ();
+ GpioUnlockDataRecords = 0;
+
+ for (Group = GroupMin; Group <= GroupMax; Group++) {
+ GpioUnlockDataRecords += GPIO_GET_DW_NUM (GpioGetPadPerGroup (Group)) + 1;
+ }
+
+ HobData = BuildGuidHob (&gGpioLibUnlockHobGuid, GpioUnlockDataRecords * sizeof (GPIO_UNLOCK_HOB_DATA));
+ if (HobData == NULL) {
+ return NULL;
+ }
+
+ ZeroMem (HobData, GpioUnlockDataRecords * sizeof (GPIO_UNLOCK_HOB_DATA));
+
+ return (GPIO_UNLOCK_HOB_DATA*)HobData;
+}
+
+/**
+ This procedure will Get GPIO Unlock data structure for storing unlock data.
+ If HOB doesn't exist it will be created.
+
+ @param[out] GpioUnlockData pointer to GPIO Unlock data structure
+
+ @retval Length number of GPIO unlock data records
+**/
+STATIC
+UINT32
+GpioGetUnlockData (
+ GPIO_UNLOCK_HOB_DATA **GpioUnlockData
+ )
+{
+ VOID *Hob;
+
+ Hob = GetFirstGuidHob (&gGpioLibUnlockHobGuid);
+ if (Hob == NULL) {
+ //
+ // It is the first time this function is used so create the HOB
+ //
+ *GpioUnlockData = GpioCreateUnlockData ();
+ if (*GpioUnlockData == NULL) {
+ return 0;
+ }
+ Hob = GetFirstGuidHob (&gGpioLibUnlockHobGuid);
+ } else {
+ *GpioUnlockData = (GPIO_UNLOCK_HOB_DATA*) GET_GUID_HOB_DATA (Hob);
+ }
+ return GET_GUID_HOB_DATA_SIZE (Hob) / sizeof (GPIO_UNLOCK_HOB_DATA);
+}
+
+/**
+ This procedure stores GPIO group data about pads which PadConfig needs to be unlocked.
+
+ @param[in] GroupIndex GPIO group index
+ @param[in] DwNum DWORD index for a group.
+ For group which has less then 32 pads per group DwNum must be 0.
+ @param[in] UnlockedPads DWORD bitmask for pads which are going to be left unlocked
+ Bit position - PadNumber
+ Bit value - 0: Skip, 1: Leave unlocked
+
+ @retval Status
+**/
+EFI_STATUS
+GpioStoreGroupDwUnlockPadConfigData (
+ IN UINT32 GroupIndex,
+ IN UINT32 DwNum,
+ IN UINT32 UnlockedPads
+ )
+{
+ GPIO_UNLOCK_HOB_DATA *GpioUnlockData;
+ UINT32 Length;
+ UINT32 Index;
+
+ if (UnlockedPads == 0) {
+ //
+ // No pads to be left unlocked
+ //
+ return EFI_SUCCESS;
+ }
+
+ Length = GpioGetUnlockData (&GpioUnlockData);
+ if (Length == 0) {
+ return EFI_NOT_FOUND;
+ }
+
+ Index = GpioUnlockDataIndex (GroupIndex, DwNum);
+ if (Index >= Length) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ GpioUnlockData[Index].PadConfig |= UnlockedPads;
+ return EFI_SUCCESS;
+}
+
+/**
+ This procedure stores GPIO group data about pads which Output state needs to be unlocked.
+
+ @param[in] GroupIndex GPIO group index
+ @param[in] DwNum DWORD index for a group.
+ For group which has less then 32 pads per group DwNum must be 0.
+ @param[in] UnlockedPads DWORD bitmask for pads which are going to be left unlocked
+ Bit position - PadNumber
+ Bit value - 0: Skip, 1: Leave unlocked
+ @retval Status
+**/
+EFI_STATUS
+GpioStoreGroupDwUnlockOutputData (
+ IN UINT32 GroupIndex,
+ IN UINT32 DwNum,
+ IN UINT32 UnlockedPads
+ )
+{
+ GPIO_UNLOCK_HOB_DATA *GpioUnlockData;
+ UINT32 Length;
+ UINT32 Index;
+
+ if (UnlockedPads == 0) {
+ //
+ // No pads to be left unlocked
+ //
+ return EFI_SUCCESS;
+ }
+
+ Length = GpioGetUnlockData (&GpioUnlockData);
+ if (Length == 0) {
+ return EFI_NOT_FOUND;
+ }
+
+ Index = GpioUnlockDataIndex (GroupIndex, DwNum);
+ if (Index >= Length) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ GpioUnlockData[Index].OutputState |= UnlockedPads;
+ return EFI_SUCCESS;
+}
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiGpioHelpersLib/PeiGpioHelpersLib.inf b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiGpioHelpersLib/PeiGpioHelpersLib.inf
new file mode 100644
index 0000000000..c1886b22f9
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiGpioHelpersLib/PeiGpioHelpersLib.inf
@@ -0,0 +1,46 @@
+## @file
+# Component description file for the PeiGpioHelpersLib
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+
+[Defines]
+INF_VERSION = 0x00010017
+BASE_NAME = PeiGpioHelpersLib
+FILE_GUID = 1838E1E7-3CC4-4A74-90D9-B421EF2A579F
+VERSION_STRING = 1.0
+MODULE_TYPE = PEIM
+LIBRARY_CLASS = GpioHelpersLib
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = IA32 X64 IPF EBC
+#
+
+
+[LibraryClasses]
+BaseLib
+IoLib
+DebugLib
+HobLib
+GpioLib
+ConfigBlockLib
+PeiServicesLib
+
+
+[Packages]
+MdePkg/MdePkg.dec
+AlderlakeSiliconPkg/SiPkg.dec
+
+
+[Sources]
+PeiGpioHelpersLib.c
+
+
+[Guids]
+gGpioLibUnlockHobGuid
+
+[Ppis]
+gSiPreMemPolicyPpiGuid
--
2.36.1.windows.1
-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#108719): https://edk2.groups.io/g/devel/message/108719
Mute This Topic: https://groups.io/mt/101373944/7686176
Group Owner: devel+owner@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [rebecca@openfw.io]
-=-=-=-=-=-=-=-=-=-=-=-
^ permalink raw reply related [flat|nested] 41+ messages in thread
* Re: [edk2-devel] [PATCH v2 02/10] AlderlakeSiliconPkg/IpBlock: Add Graphics, HostBridge, PcieRp components
2023-09-15 5:42 ` Chaganty, Rangasai V
@ 2023-09-15 13:27 ` Chuang, Rosen
0 siblings, 0 replies; 41+ messages in thread
From: Chuang, Rosen @ 2023-09-15 13:27 UTC (permalink / raw)
To: Chaganty, Rangasai V, Kasbekar, Saloni, devel@edk2.groups.io
Cc: Desimone, Nathaniel L
Reviewed-by: Rosen Chuang <rosen.chuang@intel.com>
-----Original Message-----
From: Chaganty, Rangasai V <rangasai.v.chaganty@intel.com>
Sent: Friday, September 15, 2023 1:42 PM
To: Kasbekar, Saloni <saloni.kasbekar@intel.com>; devel@edk2.groups.io
Cc: Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>; Chuang, Rosen <rosen.chuang@intel.com>
Subject: RE: [PATCH v2 02/10] AlderlakeSiliconPkg/IpBlock: Add Graphics, HostBridge, PcieRp components
Reviewed-by: Sai Chaganty <rangasai.v.chaganty@intel.com>
-----Original Message-----
From: Kasbekar, Saloni <saloni.kasbekar@intel.com>
Sent: Thursday, September 14, 2023 9:46 PM
To: devel@edk2.groups.io
Cc: Kasbekar, Saloni <saloni.kasbekar@intel.com>; Chaganty, Rangasai V <rangasai.v.chaganty@intel.com>; Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>; Chuang, Rosen <rosen.chuang@intel.com>
Subject: [PATCH v2 02/10] AlderlakeSiliconPkg/IpBlock: Add Graphics, HostBridge, PcieRp components
Adds the following modules:
- IpBlock/Graphics/Include
- IpBlock/Graphics/IncludePrivate
- IpBlock/Graphics/Library
- IpBlock/Graphics/LibraryPrivate
- IpBlock/HostBridge/IncludePrivate
- IpBlock/PcieRp/Library
Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Rosen Chuang <rosen.chuang@intel.com>
Signed-off-by: Saloni Kasbekar <saloni.kasbekar@intel.com>
---
.../Include/Ppi/GraphicsPlatformPolicyPpi.h | 76 +++++++++++
.../Library/DxeGraphicsPolicyLib.h | 71 +++++++++++
.../Library/DxeIgdOpRegionInitLib.h | 115 +++++++++++++++++
.../GraphicsInfoLibVer1.c | 52 ++++++++
.../GraphicsInfoLibVer1.inf | 33 +++++
.../DxeGraphicsPolicyLib.c | 116 +++++++++++++++++
.../DxeGraphicsPolicyLib.inf | 36 ++++++
.../DxeIgdOpRegionInit.c | 119 ++++++++++++++++++
.../DxeIgdOpRegionInitLib.inf | 47 +++++++
.../IncludePrivate/HostBridgeDataHob.h | 25 ++++
.../PchPcieRpLibInternal.h | 20 +++
.../PeiDxeSmmPchPcieRpLib/PchPcieRpLibVer2.c | 71 +++++++++++
.../PeiDxeSmmPchPcieRpLibVer2.inf | 37 ++++++
13 files changed, 818 insertions(+)
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/Include/Ppi/GraphicsPlatformPolicyPpi.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/IncludePrivate/Library/DxeGraphicsPolicyLib.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/IncludePrivate/Library/DxeIgdOpRegionInitLib.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/Library/PeiDxeSmmGraphicsInfoLib/GraphicsInfoLibVer1.c
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/Library/PeiDxeSmmGraphicsInfoLib/GraphicsInfoLibVer1.inf
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/LibraryPrivate/DxeGraphicsPolicyLib/DxeGraphicsPolicyLib.c
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/LibraryPrivate/DxeGraphicsPolicyLib/DxeGraphicsPolicyLib.inf
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/LibraryPrivate/DxeIgdOpRegionInitLib/DxeIgdOpRegionInit.c
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/LibraryPrivate/DxeIgdOpRegionInitLib/DxeIgdOpRegionInitLib.inf
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/HostBridge/IncludePrivate/HostBridgeDataHob.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PcieRp/Library/PeiDxeSmmPchPcieRpLib/PchPcieRpLibInternal.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PcieRp/Library/PeiDxeSmmPchPcieRpLib/PchPcieRpLibVer2.c
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PcieRp/Library/PeiDxeSmmPchPcieRpLib/PeiDxeSmmPchPcieRpLibVer2.inf
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/Include/Ppi/GraphicsPlatformPolicyPpi.h b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/Include/Ppi/GraphicsPlatformPolicyPpi.h
new file mode 100644
index 0000000000..a8f67061a5
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/Include/Ppi/Gra
+++ phicsPlatformPolicyPpi.h
@@ -0,0 +1,76 @@
+/** @file
+ The PEI_GRAPHICS_PLATFORM_POLICY_PPI provides platform information to PEI Graphics PEIM.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/
+
+#ifndef _PEI_GRAPHICS_PLATFORM_POLICY_PPI_H_
+#define _PEI_GRAPHICS_PLATFORM_POLICY_PPI_H_
+
+/**
+ Globally unique identifier for PEI platform policy PPI.
+**/
+#define PEI_GRAPHICS_PLATFORM_POLICY_PPI_GUID \ { \
+ 0x4eabcd09, 0x43d3, 0x4b4d, { 0xb7, 0x3d, 0x43, 0xc8, 0xd9, 0x89,
+0x99, 0x5 } \ }
+
+#define PEI_GRAPHICS_PLATFORM_POLICY_REVISION 1
+
+/**
+Pre-declaration of PEI graphics platform policy PPI.
+**/
+typedef struct _PEI_GRAPHICS_PLATFORM_POLICY_PPI
+PEI_GRAPHICS_PLATFORM_POLICY_PPI;
+
+/**
+ Enum defining the different lid status values **/ typedef enum {
+ LidClosed,
+ LidOpen,
+ LidStatusMax
+} LID_STATUS;
+
+/**
+ This function gets the platform lid status for LFP displays.
+
+ @param[out] CurrentLidStatus Output variable to store the lid status.
+
+ @retval EFI_SUCCESS Correct lid status is returned.
+ @retval EFI_UNSUPPORTED Platform does not support lid.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *GET_PLATFORM_LID_STATUS) (
+ OUT LID_STATUS *CurrentLidStatus
+ );
+
+/**
+ This function gets the base address of loaded VBT.
+
+ @param[out] VbtAddress Starting address of the VBT is returned in this parameter.
+ @param[out] VbtSize Size of the VBT is returned in this parameter.
+
+ @retval EFI_SUCCESS If the VBT is loaded and parameters contain valid values.
+ @return Other error codes meaning VBT is not loaded and parameters contain invalid values.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *GET_VBT_DATA) (
+ OUT EFI_PHYSICAL_ADDRESS *VbtAddress,
+ OUT UINT32 *VbtSize
+ );
+
+/**
+ This defines the PEI Graphics Platform Policy PPI structure.
+**/
+struct _PEI_GRAPHICS_PLATFORM_POLICY_PPI {
+ UINT32 Revision; ///< Revision of current implementation.
+ GET_PLATFORM_LID_STATUS GetPlatformLidStatus; ///< Function Pointer for get platform lid status.
+ GET_VBT_DATA GetVbtData; ///< Function pointer for get vbt data.
+};
+
+extern EFI_GUID gPeiGraphicsPlatformPpiGuid;
+
+#endif
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/IncludePrivate/Library/DxeGraphicsPolicyLib.h b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/IncludePrivate/Library/DxeGraphicsPolicyLib.h
new file mode 100644
index 0000000000..0347d4c94c
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/IncludePrivate/
+++ Library/DxeGraphicsPolicyLib.h
@@ -0,0 +1,71 @@
+/** @file
+ Header file for the DXE Graphics Policy Init library.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/ #ifndef
+_DXE_GRAPHICS_POLICY_LIB_H_ #define _DXE_GRAPHICS_POLICY_LIB_H_
+
+#include <Uefi.h>
+#include <Library/DebugLib.h>
+#include <Library/UefiLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/MemoryAllocationLib.h> #include <Protocol/SaPolicy.h>
+#include <ConfigBlock.h> #include <GraphicsConfig.h> #include
+<Library/SiConfigBlockLib.h>
+
+#define WORD_FIELD_VALID_BIT BIT15
+
+extern EFI_GUID gGraphicsDxeConfigGuid;
+
+/**
+ This function prints the Graphics DXE phase policy.
+
+ @param[in] SaPolicy - SA DXE Policy protocol **/ VOID
+GraphicsDxePolicyPrint (
+ IN SA_POLICY_PROTOCOL *SaPolicy
+ );
+
+/**
+ This function Load default Graphics DXE policy.
+
+ @param[in] ConfigBlockPointer The pointer to add Graphics config block
+**/
+VOID
+LoadIgdDxeDefault (
+ IN VOID *ConfigBlockPointer
+ );
+
+
+/**
+ Get DXE Graphics config block table total size.
+
+ @retval Size of DXE Graphics config block table
+**/
+UINT16
+EFIAPI
+GraphicsGetConfigBlockTotalSizeDxe (
+ VOID
+ );
+
+/**
+ GraphicsAddConfigBlocksDxe add all DXE Graphics config block.
+
+ @param[in] ConfigBlockTableAddress The pointer to add SA config blocks
+
+ @retval EFI_SUCCESS The policy default is initialized.
+ @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer
+**/
+EFI_STATUS
+EFIAPI
+GraphicsAddConfigBlocksDxe (
+ IN VOID *ConfigBlockTableAddress
+ );
+
+#endif // _DXE_GRAPHICs_POLICY_LIBRARY_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/IncludePrivate/Library/DxeIgdOpRegionInitLib.h b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/IncludePrivate/Library/DxeIgdOpRegionInitLib.h
new file mode 100644
index 0000000000..02e4988b2b
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/IncludePrivate/
+++ Library/DxeIgdOpRegionInitLib.h
@@ -0,0 +1,115 @@
+/** @file
+ This is part of the implementation of an Intel Graphics drivers
+OpRegion /
+ Software SCI interface between system BIOS, ASL code, and Graphics drivers.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/ #ifndef
+_DXE_IGD_OPREGION_INIT_LIB_H_ #define _DXE_IGD_OPREGION_INIT_LIB_H_
+
+///
+/// Statements that include other header files.
+///
+#include <Uefi.h>
+#include <Uefi/UefiBaseType.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <IndustryStandard/Pci.h>
+#include <Library/ConfigBlockLib.h>
+#include <Library/PciSegmentLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/MemoryAllocationLib.h> #include <Library/IoLib.h>
+#include <Library/DebugLib.h> #include <Library/HobLib.h> #include
+<Library/UefiLib.h> #include <Library/S3BootScriptLib.h> #include
+<Register/IgdRegs.h> #include <SiConfigHob.h> #include
+<Register/SaRegsHostBridge.h> /// /// Driver Consumed Protocol
+Prototypes /// #include <Protocol/PciIo.h> #include
+<Protocol/PciRootBridgeIo.h> #include <Protocol/SaPolicy.h> /// ///
+Driver Produced Protocol Prototypes /// #include
+<Protocol/IgdOpRegion.h>
+
+#pragma pack(push, 1)
+///
+///
+/// OpRegion (Miscellaneous) defines.
+///
+/// OpRegion Header defines.
+///
+typedef UINT16 STRING_REF;
+///
+/// Typedef stuctures
+///
+typedef struct {
+ UINT16 Signature; /// 0xAA55
+ UINT8 Size512;
+ UINT8 Reserved[21];
+ UINT16 PcirOffset;
+ UINT16 VbtOffset;
+} INTEL_VBIOS_OPTION_ROM_HEADER;
+
+typedef struct {
+ UINT32 Signature; /// "PCIR"
+ UINT16 VendorId; /// 0x8086
+ UINT16 DeviceId;
+ UINT16 Reserved0;
+ UINT16 Length;
+ UINT8 Revision;
+ UINT8 ClassCode[3];
+ UINT16 ImageLength;
+ UINT16 CodeRevision;
+ UINT8 CodeType;
+ UINT8 Indicator;
+ UINT16 Reserved1;
+} INTEL_VBIOS_PCIR_STRUCTURE;
+
+typedef struct {
+ UINT8 HeaderSignature[20];
+ UINT16 HeaderVersion;
+ UINT16 HeaderSize;
+ UINT16 HeaderVbtSize;
+ UINT8 HeaderVbtCheckSum;
+ UINT8 HeaderReserved;
+ UINT32 HeaderOffsetVbtDataBlock;
+ UINT32 HeaderOffsetAim1;
+ UINT32 HeaderOffsetAim2;
+ UINT32 HeaderOffsetAim3;
+ UINT32 HeaderOffsetAim4;
+ UINT8 DataHeaderSignature[16];
+ UINT16 DataHeaderVersion;
+ UINT16 DataHeaderSize;
+ UINT16 DataHeaderDataBlockSize;
+ UINT8 CoreBlockId;
+ UINT16 CoreBlockSize;
+ UINT16 CoreBlockBiosSize;
+ UINT8 CoreBlockBiosType;
+ UINT8 CoreBlockReleaseStatus;
+ UINT8 CoreBlockHWSupported;
+ UINT8 CoreBlockIntegratedHW;
+ UINT8 CoreBlockBiosBuild[4];
+ UINT8 CoreBlockBiosSignOn[155];
+} VBIOS_VBT_STRUCTURE;
+#pragma pack(pop)
+///
+/// Driver Private Function definitions ///
+
+/**
+ Update Graphics OpRegion after PCI enumeration.
+
+ @retval EFI_SUCCESS - The function completed successfully.
+**/
+EFI_STATUS
+UpdateIgdOpRegionEndOfDxe (
+ VOID
+ );
+#endif
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/Library/PeiDxeSmmGraphicsInfoLib/GraphicsInfoLibVer1.c b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/Library/PeiDxeSmmGraphicsInfoLib/GraphicsInfoLibVer1.c
new file mode 100644
index 0000000000..9dd9b33a49
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/Library/PeiDxeS
+++ mmGraphicsInfoLib/GraphicsInfoLibVer1.c
@@ -0,0 +1,52 @@
+/** @file
+ Source file for common Graphics Info Lib.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/ #include
+<Library/GraphicsInfoLib.h> #include <Register/IgdRegs.h> #include
+<Library/TimerLib.h> #include <Base.h>
+
+/**
+ GetIgdBusNumber: Get IGD Bus Number
+
+ @retval PCI bus number for IGD
+**/
+UINT8
+GetIgdBusNumber (
+ VOID
+ )
+{
+ return (UINT8) IGD_BUS_NUM;
+}
+
+/**
+ GetIgdDevNumber: Get IGD Dev Number
+
+ @retval PCI dev number for IGD
+**/
+UINT8
+GetIgdDevNumber (
+ VOID
+ )
+{
+ return (UINT8) IGD_DEV_NUM;
+}
+
+/**
+ GetIgdFunNumber: Get IGD Fun Number
+
+ @retval PCI fun number for IGD
+**/
+UINT8
+GetIgdFuncNumber (
+ VOID
+ )
+{
+ return (UINT8) IGD_FUN_NUM;
+}
+
+
+
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/Library/PeiDxeSmmGraphicsInfoLib/GraphicsInfoLibVer1.inf b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/Library/PeiDxeSmmGraphicsInfoLib/GraphicsInfoLibVer1.inf
new file mode 100644
index 0000000000..ca363ce105
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/Library/PeiDxeS
+++ mmGraphicsInfoLib/GraphicsInfoLibVer1.inf
@@ -0,0 +1,33 @@
+## @file
+# Graphics information library.
+#
+# All function in this library is available for PEI, DXE, and SMM, #
+But do not support UEFI RUNTIME environment call.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+
+[Defines]
+INF_VERSION = 0x00010017
+BASE_NAME = PeiDxeSmmGraphicsInfoLib
+FILE_GUID = AE4D5DE8-F092-4B2A-8003-F1A4CCBDC3E4
+VERSION_STRING = 1.0
+MODULE_TYPE = BASE
+LIBRARY_CLASS = GraphicsInfoLib
+
+[LibraryClasses]
+BaseLib
+IoLib
+DebugLib
+BaseMemoryLib
+PciSegmentLib
+TimerLib
+
+[Packages]
+MdePkg/MdePkg.dec
+AlderlakeSiliconPkg/SiPkg.dec
+
+[Sources]
+GraphicsInfoLibVer1.c
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/LibraryPrivate/DxeGraphicsPolicyLib/DxeGraphicsPolicyLib.c b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/LibraryPrivate/DxeGraphicsPolicyLib/DxeGraphicsPolicyLib.c
new file mode 100644
index 0000000000..a9344b424d
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/LibraryPrivate/
+++ DxeGraphicsPolicyLib/DxeGraphicsPolicyLib.c
@@ -0,0 +1,116 @@
+/** @file
+ This file provide services for DXE phase Graphics policy default initialization.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/
+
+#include <Library/DxeGraphicsPolicyLib.h>
+
+/**
+ This function prints the Graphics DXE phase policy.
+
+ @param[in] SaPolicy - SA DXE Policy protocol **/ VOID
+GraphicsDxePolicyPrint (
+ IN SA_POLICY_PROTOCOL *SaPolicy
+ )
+{
+ EFI_STATUS Status;
+ GRAPHICS_DXE_CONFIG *GraphicsDxeConfig;
+
+ //
+ // Get requisite IP Config Blocks which needs to be used here //
+ Status = GetConfigBlock ((VOID *) SaPolicy, &gGraphicsDxeConfigGuid,
+ (VOID *)&GraphicsDxeConfig); ASSERT_EFI_ERROR (Status);
+
+
+ DEBUG_CODE_BEGIN ();
+ DEBUG ((DEBUG_INFO, "\n------------------------ Graphics Policy (DXE)
+ print BEGIN -----------------\n")); DEBUG ((DEBUG_INFO, " Revision :
+ %d\n", GraphicsDxeConfig->Header.Revision));
+ ASSERT (GraphicsDxeConfig->Header.Revision ==
+ GRAPHICS_DXE_CONFIG_REVISION); DEBUG ((DEBUG_INFO,
+ "\n------------------------ Graphics Policy (DXE) print END
+ -----------------\n")); DEBUG_CODE_END ();
+
+ return;
+}
+
+
+/**
+ This function Load default Graphics DXE policy.
+
+ @param[in] ConfigBlockPointer The pointer to add Graphics config block
+**/
+VOID
+LoadIgdDxeDefault (
+ IN VOID *ConfigBlockPointer
+ )
+{
+ GRAPHICS_DXE_CONFIG *GraphicsDxeConfig;
+
+ GraphicsDxeConfig = ConfigBlockPointer;
+
+ ///
+ /// Initialize the Graphics configuration
+ ///
+ GraphicsDxeConfig->PlatformConfig = 1;
+ GraphicsDxeConfig->AlsEnable = 2;
+ GraphicsDxeConfig->BacklightControlSupport = 2;
+ GraphicsDxeConfig->IgdBlcConfig = 2;
+ GraphicsDxeConfig->GfxTurboIMON = 31;
+ ///
+ /// <EXAMPLE> Create a static Backlight Brightness Level Duty cycle
+Mapping Table
+ /// Possible 20 entries (example used 11), each 16 bits as follows:
+ /// [15] = Field Valid bit, [14:08] = Level in Percentage (0-64h), [07:00] = Desired duty cycle (0 - FFh).
+ ///
+ GraphicsDxeConfig->BCLM[0] = (0x0000 + WORD_FIELD_VALID_BIT); ///<
+0%
+ GraphicsDxeConfig->BCLM[1] = (0x0A19 + WORD_FIELD_VALID_BIT); ///<
+10%
+ GraphicsDxeConfig->BCLM[2] = (0x1433 + WORD_FIELD_VALID_BIT); ///<
+20%
+ GraphicsDxeConfig->BCLM[3] = (0x1E4C + WORD_FIELD_VALID_BIT); ///<
+30%
+ GraphicsDxeConfig->BCLM[4] = (0x2866 + WORD_FIELD_VALID_BIT); ///<
+40%
+ GraphicsDxeConfig->BCLM[5] = (0x327F + WORD_FIELD_VALID_BIT); ///<
+50%
+ GraphicsDxeConfig->BCLM[6] = (0x3C99 + WORD_FIELD_VALID_BIT); ///<
+60%
+ GraphicsDxeConfig->BCLM[7] = (0x46B2 + WORD_FIELD_VALID_BIT); ///<
+70%
+ GraphicsDxeConfig->BCLM[8] = (0x50CC + WORD_FIELD_VALID_BIT); ///<
+80%
+ GraphicsDxeConfig->BCLM[9] = (0x5AE5 + WORD_FIELD_VALID_BIT); ///<
+90%
+ GraphicsDxeConfig->BCLM[10] = (0x64FF + WORD_FIELD_VALID_BIT); ///<
+100% }
+
+static COMPONENT_BLOCK_ENTRY mGraphicsDxeIpBlocks = {
+ &gGraphicsDxeConfigGuid, sizeof (GRAPHICS_DXE_CONFIG),
+GRAPHICS_DXE_CONFIG_REVISION, LoadIgdDxeDefault};
+
+
+/**
+ Get DXE Graphics config block table total size.
+
+ @retval Size of DXE Graphics config block table
+**/
+UINT16
+EFIAPI
+GraphicsGetConfigBlockTotalSizeDxe (
+ VOID
+ )
+{
+ return mGraphicsDxeIpBlocks.Size;
+}
+
+/**
+ GraphicsAddConfigBlocksDxe add all DXE Graphics config block.
+
+ @param[in] ConfigBlockTableAddress The pointer to add SA config blocks
+
+ @retval EFI_SUCCESS The policy default is initialized.
+ @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer
+**/
+EFI_STATUS
+EFIAPI
+GraphicsAddConfigBlocksDxe (
+ IN VOID *ConfigBlockTableAddress
+ )
+{
+ EFI_STATUS Status;
+ Status = AddComponentConfigBlocks (ConfigBlockTableAddress,
+&mGraphicsDxeIpBlocks, 1);
+ return Status;
+}
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/LibraryPrivate/DxeGraphicsPolicyLib/DxeGraphicsPolicyLib.inf b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/LibraryPrivate/DxeGraphicsPolicyLib/DxeGraphicsPolicyLib.inf
new file mode 100644
index 0000000000..0fd6aba0bb
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/LibraryPrivate/
+++ DxeGraphicsPolicyLib/DxeGraphicsPolicyLib.inf
@@ -0,0 +1,36 @@
+## @file
+# Component description file for the DXE Graphics Policy Init library.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+[Defines]
+INF_VERSION = 0x00010017
+BASE_NAME = DxeGraphicsPolicyLib
+FILE_GUID = C6190599-287E-40F9-9B46-EE112A322EBF
+VERSION_STRING = 1.0
+MODULE_TYPE = BASE
+LIBRARY_CLASS = DxeGraphicsPolicyLib
+
+[LibraryClasses]
+BaseMemoryLib
+UefiRuntimeServicesTableLib
+UefiBootServicesTableLib
+DebugLib
+PostCodeLib
+ConfigBlockLib
+HobLib
+SiConfigBlockLib
+
+[Packages]
+MdePkg/MdePkg.dec
+AlderlakeSiliconPkg/SiPkg.dec
+
+[Sources]
+DxeGraphicsPolicyLib.c
+
+[Guids]
+gGraphicsDxeConfigGuid
+
+[Pcd]
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/LibraryPrivate/DxeIgdOpRegionInitLib/DxeIgdOpRegionInit.c b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/LibraryPrivate/DxeIgdOpRegionInitLib/DxeIgdOpRegionInit.c
new file mode 100644
index 0000000000..b3c9d28078
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/LibraryPrivate/
+++ DxeIgdOpRegionInitLib/DxeIgdOpRegionInit.c
@@ -0,0 +1,119 @@
+/** @file
+ This is part of the implementation of an Intel Graphics drivers
+OpRegion /
+ Software SCI interface between system BIOS, ASL code, and Graphics drivers.
+ The code in this file will load the driver and initialize the
+interface
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/
+
+#include <Library/DxeIgdOpRegionInitLib.h>
+
+
+
+GLOBAL_REMOVE_IF_UNREFERENCED IGD_OPREGION_PROTOCOL mIgdOpRegion;
+
+
+/**
+ Update Graphics OpRegion after PCI enumeration.
+
+ @param[in] void - None
+ @retval EFI_SUCCESS - The function completed successfully.
+**/
+EFI_STATUS
+UpdateIgdOpRegionEndOfDxe (
+ VOID
+)
+{
+ EFI_STATUS Status;
+ UINTN HandleCount;
+ EFI_HANDLE *HandleBuffer;
+ UINTN Index;
+ EFI_PCI_IO_PROTOCOL *PciIo;
+ PCI_TYPE00 Pci;
+ UINTN Segment;
+ UINTN Bus;
+ UINTN Device;
+ UINTN Function;
+
+ Bus = 0;
+ Device = 0;
+ Function = 0;
+
+ DEBUG ((DEBUG_INFO, "UpdateIgdOpRegionEndOfDxe\n"));
+
+ mIgdOpRegion.OpRegion->Header.PCON |= BIT8; //Set External Gfx
+ Adapter field is valid mIgdOpRegion.OpRegion->Header.PCON &= (UINT32)
+ (~BIT7); //Assume No External Gfx Adapter
+
+ ///
+ /// Get all PCI IO protocols handles
+ ///
+ Status = gBS->LocateHandleBuffer (
+ ByProtocol,
+ &gEfiPciIoProtocolGuid,
+ NULL,
+ &HandleCount,
+ &HandleBuffer
+ );
+
+ if (!EFI_ERROR (Status)) {
+ for (Index = 0; Index < HandleCount; Index++) {
+ ///
+ /// Get the PCI IO Protocol Interface corresponding to each handle
+ ///
+ Status = gBS->HandleProtocol (
+ HandleBuffer[Index],
+ &gEfiPciIoProtocolGuid,
+ (VOID **) &PciIo
+ );
+
+ if (!EFI_ERROR (Status)) {
+ ///
+ /// Read the PCI configuration space
+ ///
+ Status = PciIo->Pci.Read (
+ PciIo,
+ EfiPciIoWidthUint32,
+ 0,
+ sizeof (Pci) / sizeof (UINT32),
+ &Pci
+ );
+
+ ///
+ /// Find the display controllers devices
+ ///
+ if (!EFI_ERROR (Status) && IS_PCI_DISPLAY (&Pci)) {
+ Status = PciIo->GetLocation (
+ PciIo,
+ &Segment,
+ &Bus,
+ &Device,
+ &Function
+ );
+
+ //
+ // Assumption: Onboard devices will be sits on Bus no 0, while external devices will be sits on Bus no > 0
+ //
+ if (!EFI_ERROR (Status) && (Bus > 0)) {
+ //External Gfx Adapter Detected and Available
+ DEBUG ((DEBUG_INFO, "PCON - External Gfx Adapter Detected and Available\n"));
+ mIgdOpRegion.OpRegion->Header.PCON |= BIT7;
+ break;
+ }
+ }
+ }
+ }
+ }
+
+ ///
+ /// Free any allocated buffers
+ ///
+ if (HandleBuffer != NULL) {
+ FreePool (HandleBuffer);
+ }
+
+ ///
+ /// Return final status
+ ///
+ return Status;
+}
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/LibraryPrivate/DxeIgdOpRegionInitLib/DxeIgdOpRegionInitLib.inf b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/LibraryPrivate/DxeIgdOpRegionInitLib/DxeIgdOpRegionInitLib.inf
new file mode 100644
index 0000000000..e3a56d5563
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/LibraryPrivate/
+++ DxeIgdOpRegionInitLib/DxeIgdOpRegionInitLib.inf
@@ -0,0 +1,47 @@
+## @file
+# Component description file for the Dxe IGD OpRegion library.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+[Defines]
+INF_VERSION = 0x00010017
+BASE_NAME = DxeIgdOpRegionInitLib
+FILE_GUID = 18D47D72-555E-475B-A4E4-AD20C3BD8B15
+VERSION_STRING = 1.0
+MODULE_TYPE = DXE_DRIVER
+UEFI_SPECIFICATION_VERSION = 2.00
+LIBRARY_CLASS = DxeIgdOpRegionInitLib
+
+[LibraryClasses]
+UefiLib
+UefiRuntimeServicesTableLib
+UefiBootServicesTableLib
+DebugLib
+PostCodeLib
+ConfigBlockLib
+PciSegmentLib
+BaseMemoryLib
+MemoryAllocationLib
+IoLib
+S3BootScriptLib
+
+[Packages]
+MdePkg/MdePkg.dec
+AlderlakeSiliconPkg/SiPkg.dec
+IntelSiliconPkg/IntelSiliconPkg.dec
+
+[Pcd]
+gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress
+
+[Sources]
+DxeIgdOpRegionInit.c
+
+[Guids]
+gGraphicsDxeConfigGuid ## CONSUMES
+
+[Protocols]
+gIgdOpRegionProtocolGuid ## PRODUCES
+gSaPolicyProtocolGuid ## CONSUMES
+gEfiPciIoProtocolGuid ## CONSUMES
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/HostBridge/IncludePrivate/HostBridgeDataHob.h b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/HostBridge/IncludePrivate/HostBridgeDataHob.h
new file mode 100644
index 0000000000..671e821342
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/HostBridge/IncludePrivat
+++ e/HostBridgeDataHob.h
@@ -0,0 +1,25 @@
+/** @file
+ The GUID definition for Host Bridge Data Hob
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/ #ifndef
+_HOST_BRIDGE_DATA_HOB_H_ #define _HOST_BRIDGE_DATA_HOB_H_
+
+#include <Base.h>
+
+extern EFI_GUID gHostBridgeDataHobGuid; #pragma pack (push,1)
+
+///
+/// Host Bridge Data Hob
+///
+typedef struct {
+ EFI_HOB_GUID_TYPE EfiHobGuidType; ///< GUID Hob type structure for gSaDataHobGuid
+ UINT8 EnableAbove4GBMmio; ///< 0=Disable above 4GB MMIO resource support, 1=Enable above 4GB MMIO resource support
+ BOOLEAN SkipPamLock; ///< 0=All PAM registers will be locked in System Agent code, 1=Do not lock PAM registers in System Agent code.
+ UINT8 Rsvd1[2]; ///< Reserved for future use
+} HOST_BRIDGE_DATA_HOB;
+#pragma pack (pop)
+#endif
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PcieRp/Library/PeiDxeSmmPchPcieRpLib/PchPcieRpLibInternal.h b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PcieRp/Library/PeiDxeSmmPchPcieRpLib/PchPcieRpLibInternal.h
new file mode 100644
index 0000000000..e2be00fae7
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PcieRp/Library/PeiDxeSmm
+++ PchPcieRpLib/PchPcieRpLibInternal.h
@@ -0,0 +1,20 @@
+/** @file
+ PCIE root port library.
+ All function in this library is available for PEI, DXE, and SMM,
+ But do not support UEFI RUNTIME environment call.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/
+
+#ifndef _PCH_PCIE_RP_LIB_INTERNAL_H_
+#define _PCH_PCIE_RP_LIB_INTERNAL_H_
+
+typedef struct {
+ UINT8 DevNum;
+ UINT8 Pid;
+ UINT8 RpNumBase;
+} PCH_PCIE_CONTROLLER_INFO;
+
+#endif
+
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PcieRp/Library/PeiDxeSmmPchPcieRpLib/PchPcieRpLibVer2.c b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PcieRp/Library/PeiDxeSmmPchPcieRpLib/PchPcieRpLibVer2.c
new file mode 100644
index 0000000000..0702792597
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PcieRp/Library/PeiDxeSmm
+++ PchPcieRpLib/PchPcieRpLibVer2.c
@@ -0,0 +1,71 @@
+/** @file
+ PCIE root port library.
+ All function in this library is available for PEI, DXE, and SMM,
+ But do not support UEFI RUNTIME environment call.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/
+
+#include <Base.h>
+#include <Uefi/UefiBaseType.h>
+#include <Library/IoLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseLib.h>
+#include <Library/PciSegmentLib.h>
+#include <Library/PchInfoLib.h>
+#include <Library/PchPcrLib.h>
+#include <Library/PchPcieRpLib.h>
+#include <Register/PchRegs.h>
+#include <PchBdfAssignment.h>
+#include <PchPcieRpInfo.h>
+#include <Register/PchPcieRpRegs.h>
+#include <Register/PchPcrRegs.h>
+
+#include "PchPcieRpLibInternal.h"
+
+GLOBAL_REMOVE_IF_UNREFERENCED PCH_PCIE_CONTROLLER_INFO
+mPchPcieControllerInfo[] = {
+ { PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_1, PID_SPA, 0 },
+ { PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_5, PID_SPB, 4 },
+ { PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_9, PID_SPC, 8 },
+ { PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_13, PID_SPD, 12 },
+ { PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_17, PID_SPE, 16 }, // PCH-H
+only
+ { PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_21, PID_SPF, 20 } // PCH-H
+only };
+
+/**
+ Get Pch Pcie Root Port Device and Function Number by Root Port
+physical Number
+
+ @param[in] RpNumber Root port physical number. (0-based)
+ @param[out] RpDev Return corresponding root port device number.
+ @param[out] RpFun Return corresponding root port function number.
+
+ @retval EFI_SUCCESS Root port device and function is retrieved
+ @retval EFI_INVALID_PARAMETER RpNumber is invalid
+**/
+EFI_STATUS
+EFIAPI
+GetPchPcieRpDevFun (
+ IN UINTN RpNumber,
+ OUT UINTN *RpDev,
+ OUT UINTN *RpFun
+ )
+{
+ UINTN Index;
+ UINTN FuncIndex;
+ UINT32 PciePcd;
+
+ if (RpNumber >= GetPchMaxPciePortNum ()) {
+ DEBUG ((DEBUG_ERROR, "GetPchPcieRpDevFun invalid RpNumber %x", RpNumber));
+ ASSERT (FALSE);
+ return EFI_INVALID_PARAMETER;
+ }
+
+ Index = RpNumber / PCH_PCIE_CONTROLLER_PORTS; FuncIndex = RpNumber -
+ mPchPcieControllerInfo[Index].RpNumBase;
+ *RpDev = mPchPcieControllerInfo[Index].DevNum;
+ PciePcd = PchPcrRead32 (mPchPcieControllerInfo[Index].Pid,
+ R_SPX_PCR_PCD); *RpFun = (PciePcd >> (FuncIndex *
+ S_SPX_PCR_PCD_RP_FIELD)) & B_SPX_PCR_PCD_RP1FN;
+
+ return EFI_SUCCESS;
+}
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PcieRp/Library/PeiDxeSmmPchPcieRpLib/PeiDxeSmmPchPcieRpLibVer2.inf b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PcieRp/Library/PeiDxeSmmPchPcieRpLib/PeiDxeSmmPchPcieRpLibVer2.inf
new file mode 100644
index 0000000000..0acafbfc43
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PcieRp/Library/PeiDxeSmm
+++ PchPcieRpLib/PeiDxeSmmPchPcieRpLibVer2.inf
@@ -0,0 +1,37 @@
+## @file
+# PCIE root port Library.
+#
+# All function in this library is available for PEI, DXE, and SMM, #
+But do not support UEFI RUNTIME environment call.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+
+[Defines]
+INF_VERSION = 0x00010017
+BASE_NAME = PeiDxeSmmPchPcieRpLib
+FILE_GUID = B522981C-E0C5-4E04-A82A-C61D4F0B2C75
+VERSION_STRING = 1.0
+MODULE_TYPE = BASE
+LIBRARY_CLASS = PchPcieRpLib
+
+
+[LibraryClasses]
+BaseLib
+IoLib
+DebugLib
+PciSegmentLib
+PchInfoLib
+PchPcrLib
+
+
+[Packages]
+MdePkg/MdePkg.dec
+AlderlakeSiliconPkg/SiPkg.dec
+
+
+[Sources]
+PchPcieRpLibVer2.c
+
--
2.36.1.windows.1
-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#108720): https://edk2.groups.io/g/devel/message/108720
Mute This Topic: https://groups.io/mt/101373945/7686176
Group Owner: devel+owner@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [rebecca@openfw.io]
-=-=-=-=-=-=-=-=-=-=-=-
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [edk2-devel] [PATCH v2 03/10] AlderlakeSiliconPkg/IpBlock: Add P2sb, PchDmi components
2023-09-15 5:42 ` Chaganty, Rangasai V
@ 2023-09-15 13:28 ` Chuang, Rosen
0 siblings, 0 replies; 41+ messages in thread
From: Chuang, Rosen @ 2023-09-15 13:28 UTC (permalink / raw)
To: Chaganty, Rangasai V, Kasbekar, Saloni, devel@edk2.groups.io
Cc: Desimone, Nathaniel L
Reviewed-by: Rosen Chuang <rosen.chuang@intel.com>
-----Original Message-----
From: Chaganty, Rangasai V <rangasai.v.chaganty@intel.com>
Sent: Friday, September 15, 2023 1:43 PM
To: Kasbekar, Saloni <saloni.kasbekar@intel.com>; devel@edk2.groups.io
Cc: Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>; Chuang, Rosen <rosen.chuang@intel.com>
Subject: RE: [PATCH v2 03/10] AlderlakeSiliconPkg/IpBlock: Add P2sb, PchDmi components
Reviewed-by: Sai Chaganty <rangasai.v.chaganty@intel.com>
-----Original Message-----
From: Kasbekar, Saloni <saloni.kasbekar@intel.com>
Sent: Thursday, September 14, 2023 9:46 PM
To: devel@edk2.groups.io
Cc: Kasbekar, Saloni <saloni.kasbekar@intel.com>; Chaganty, Rangasai V <rangasai.v.chaganty@intel.com>; Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>; Chuang, Rosen <rosen.chuang@intel.com>
Subject: [PATCH v2 03/10] AlderlakeSiliconPkg/IpBlock: Add P2sb, PchDmi components
Adds the following modules:
- IpBlock/P2sb/IncludePrivate
- IpBlock/P2sb/Library
- IpBlock/P2sb/LibraryPrivate
- IpBlock/PchDmi/IncludePrivate
- IpBlock/PchDmi/LibraryPrivate
Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Rosen Chuang <rosen.chuang@intel.com>
Signed-off-by: Saloni Kasbekar <saloni.kasbekar@intel.com>
---
.../Library/P2SbSidebandAccessLib.h | 105 +++++++
.../IncludePrivate/Library/PchSbiAccessLib.h | 58 ++++
.../P2sb/IncludePrivate/P2SbController.h | 32 +++
.../P2sb/IncludePrivate/Register/P2sbRegs.h | 53 ++++
.../Library/PeiDxeSmmPchPcrLib/PchPcrLib.c | 266 ++++++++++++++++++
.../PeiDxeSmmPchPcrLib/PeiDxeSmmPchPcrLib.inf | 35 +++
.../PeiDxeSmmP2SbSidebandAccessLib.c | 208 ++++++++++++++
.../PeiDxeSmmP2SbSidebandAccessLib.inf | 30 ++
.../PchSbiAccessLib.c | 72 +++++
.../PeiDxeSmmPchSbiAccessLib.inf | 35 +++
.../PchDmi/IncludePrivate/Library/PchDmiLib.h | 60 ++++
.../PeiDxeSmmPchDmiLib/PchDmi14.c | 34 +++
.../PeiDxeSmmPchDmiLib/PchDmi14.h | 22 ++
.../PeiDxeSmmPchDmiLib/PchDmiLib.c | 110 ++++++++
.../PeiDxeSmmPchDmiLib/PeiDxeSmmPchDmiLib.inf | 43 +++
15 files changed, 1163 insertions(+)
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/IncludePrivate/Library/P2SbSidebandAccessLib.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/IncludePrivate/Library/PchSbiAccessLib.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/IncludePrivate/P2SbController.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/IncludePrivate/Register/P2sbRegs.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/Library/PeiDxeSmmPchPcrLib/PchPcrLib.c
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/Library/PeiDxeSmmPchPcrLib/PeiDxeSmmPchPcrLib.inf
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/LibraryPrivate/PeiDxeSmmP2SbSidebandAccessLib/PeiDxeSmmP2SbSidebandAccessLib.c
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/LibraryPrivate/PeiDxeSmmP2SbSidebandAccessLib/PeiDxeSmmP2SbSidebandAccessLib.inf
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/LibraryPrivate/PeiDxeSmmPchSbiAccessLib/PchSbiAccessLib.c
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/LibraryPrivate/PeiDxeSmmPchSbiAccessLib/PeiDxeSmmPchSbiAccessLib.inf
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PchDmi/IncludePrivate/Library/PchDmiLib.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivate/PeiDxeSmmPchDmiLib/PchDmi14.c
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivate/PeiDxeSmmPchDmiLib/PchDmi14.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivate/PeiDxeSmmPchDmiLib/PchDmiLib.c
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivate/PeiDxeSmmPchDmiLib/PeiDxeSmmPchDmiLib.inf
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/IncludePrivate/Library/P2SbSidebandAccessLib.h b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/IncludePrivate/Library/P2SbSidebandAccessLib.h
new file mode 100644
index 0000000000..e364508eb4
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/IncludePrivate/Libr
+++ ary/P2SbSidebandAccessLib.h
@@ -0,0 +1,105 @@
+/** @file
+ Header for P2SbSidebandAccessLib
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/
+
+#ifndef _P2SB_SIDEBAND_ACCESS_LIB_H_
+#define _P2SB_SIDEBAND_ACCESS_LIB_H_
+
+#include <RegisterAccess.h>
+#include <P2SbController.h>
+#include <Library/PchPcrLib.h> // For PCH_SBI_PID definition
+
+typedef PCH_SBI_PID P2SB_PID;
+
+typedef enum {
+ P2SbMemory = 0,
+ P2SbPciConfig,
+ P2SbPrivateConfig
+} P2SB_REGISTER_SPACE;
+
+typedef enum {
+ MemoryRead = 0x0,
+ MemoryWrite = 0x1,
+ PciConfigRead = 0x4,
+ PciConfigWrite = 0x5,
+ PrivateControlRead = 0x6,
+ PrivateControlWrite = 0x7,
+ GpioLockUnlock = 0x13
+} P2SB_SBI_OPCODE;
+
+typedef enum {
+ SBI_SUCCESSFUL = 0,
+ SBI_UNSUCCESSFUL = 1,
+ SBI_POWERDOWN = 2,
+ SBI_MIXED = 3,
+ SBI_INVALID_RESPONSE
+} P2SB_SBI_RESPONSE;
+
+typedef enum {
+ P2SbMmioAccess = 0,
+ P2SbMsgAccess
+} P2SB_SIDEBAND_ACCESS_METHOD;
+
+/**
+ REGISTER_ACCESS for P2SB device to support access to sideband registers.
+ Be sure to keep first member of this structure as REGISTER_ACCESS to
+allow
+ for correct casting between caller who sees this structure as
+REGISTER_ACCESS
+ and calle who will cast it to P2SB_SIDEBAND_REGISTER_ACCESS.
+**/
+typedef struct {
+ REGISTER_ACCESS Access;
+ P2SB_SIDEBAND_ACCESS_METHOD AccessMethod;
+ P2SB_PID P2SbPid;
+ UINT16 Fid;
+ P2SB_REGISTER_SPACE RegisterSpace;
+ BOOLEAN PostedWrites;
+ P2SB_CONTROLLER *P2SbCtrl;
+} P2SB_SIDEBAND_REGISTER_ACCESS;
+
+/**
+ Full function for executing P2SB SBI message
+ Take care of that there is no lock protection when using SBI programming in both POST time and SMI.
+ It will clash with POST time SBI programming when SMI happen.
+ Programmer MUST do the save and restore opration while using the
+PchSbiExecution inside SMI
+ to prevent from racing condition.
+ This function will reveal P2SB and hide P2SB if it's originally
+hidden. If more than one SBI access
+ needed, it's better to unhide the P2SB before calling and hide it back after done.
+
+ When the return value is "EFI_SUCCESS", the "Response" do not need to
+ be checked as it would have been SBI_SUCCESS. If the return value is
+ "EFI_DEVICE_ERROR", then this would provide additional information when needed.
+
+ @param[in] P2sbBase P2SB PCI config base
+ @param[in] Pid Port ID of the SBI message
+ @param[in] Offset Offset of the SBI message
+ @param[in] Opcode Opcode
+ @param[in] Posted Posted message
+ @param[in] Fbe First byte enable
+ @param[in] Bar Bar
+ @param[in] Fid Function ID
+ @param[in, out] Data32 Read/Write data
+ @param[out] Response Response
+
+ @retval EFI_SUCCESS Successfully completed.
+ @retval EFI_DEVICE_ERROR Transaction fail
+ @retval EFI_INVALID_PARAMETER Invalid parameter
+ @retval EFI_TIMEOUT Timeout while waiting for response
+**/
+EFI_STATUS
+P2SbSbiExecutionEx (
+ IN UINT64 P2sbBase,
+ IN P2SB_PID Pid,
+ IN UINT64 Offset,
+ IN P2SB_SBI_OPCODE Opcode,
+ IN BOOLEAN Posted,
+ IN UINT16 Fbe,
+ IN UINT16 Bar,
+ IN UINT16 Fid,
+ IN OUT UINT32 *Data32,
+ OUT UINT8 *Response
+ );
+
+#endif
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/IncludePrivate/Library/PchSbiAccessLib.h b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/IncludePrivate/Library/PchSbiAccessLib.h
new file mode 100644
index 0000000000..a46d8fb649
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/IncludePrivate/Libr
+++ ary/PchSbiAccessLib.h
@@ -0,0 +1,58 @@
+/** @file
+ Header file for PchSbiAccessLib.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/ #ifndef
+_PCH_SBI_ACCESS_LIB_H_ #define _PCH_SBI_ACCESS_LIB_H_
+
+#include <Library/PchPcrLib.h>
+#include <Library/P2SbSidebandAccessLib.h>
+
+typedef P2SB_SBI_OPCODE PCH_SBI_OPCODE ;
+
+typedef P2SB_SBI_RESPONSE PCH_SBI_RESPONSE;
+
+/**
+ Full function for executing PCH SBI message
+ Take care of that there is no lock protection when using SBI programming in both POST time and SMI.
+ It will clash with POST time SBI programming when SMI happen.
+ Programmer MUST do the save and restore opration while using the
+PchSbiExecution inside SMI
+ to prevent from racing condition.
+ This function will reveal P2SB and hide P2SB if it's originally
+hidden. If more than one SBI access
+ needed, it's better to unhide the P2SB before calling and hide it back after done.
+
+ When the return value is "EFI_SUCCESS", the "Response" do not need to
+ be checked as it would have been SBI_SUCCESS. If the return value is
+ "EFI_DEVICE_ERROR", then this would provide additional information when needed.
+
+ @param[in] Pid Port ID of the SBI message
+ @param[in] Offset Offset of the SBI message
+ @param[in] Opcode Opcode
+ @param[in] Posted Posted message
+ @param[in] Fbe First byte enable
+ @param[in] Bar Bar
+ @param[in] Fid Function ID
+ @param[in, out] Data32 Read/Write data
+ @param[out] Response Response
+
+ @retval EFI_SUCCESS Successfully completed.
+ @retval EFI_DEVICE_ERROR Transaction fail
+ @retval EFI_INVALID_PARAMETER Invalid parameter
+ @retval EFI_TIMEOUT Timeout while waiting for response
+**/
+EFI_STATUS
+PchSbiExecutionEx (
+ IN PCH_SBI_PID Pid,
+ IN UINT64 Offset,
+ IN PCH_SBI_OPCODE Opcode,
+ IN BOOLEAN Posted,
+ IN UINT16 Fbe,
+ IN UINT16 Bar,
+ IN UINT16 Fid,
+ IN OUT UINT32 *Data32,
+ OUT UINT8 *Response
+ );
+
+#endif // _PCH_SBI_ACCESS_LIB_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/IncludePrivate/P2SbController.h b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/IncludePrivate/P2SbController.h
new file mode 100644
index 0000000000..51c67d4624
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/IncludePrivate/P2Sb
+++ Controller.h
@@ -0,0 +1,32 @@
+/** @file
+ P2SB controller
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/ #ifndef
+_P2SB_CONTROLLER_H_ #define _P2SB_CONTROLLER_H_
+
+/**
+ P2SB structure
+ Stores information required to access to registers
+ like base address, S:B:D:F etc.
+ and definitions specific to P2SB.
+**/
+typedef struct {
+ /**
+ P2SB controller PCI config space address
+ in PCI Segment Library representation.
+ **/
+ UINT64 PciCfgBaseAddr;
+ /**
+ P2SB controller MMIO base address
+ **/
+ UINT64 Mmio;
+ /**
+ HPET MMIO base address
+ **/
+ UINT64 HpetMmio;
+} P2SB_CONTROLLER;
+
+#endif // _P2SB_CONTROLLER_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/IncludePrivate/Register/P2sbRegs.h b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/IncludePrivate/Register/P2sbRegs.h
new file mode 100644
index 0000000000..ffe35411f7
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/IncludePrivate/Regi
+++ ster/P2sbRegs.h
@@ -0,0 +1,53 @@
+/** @file
+ Register names for PCH P2SB device
+
+ Conventions:
+
+ - Register definition format:
+
+ Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_Re
+ gisterName
+ - Prefix:
+ Definitions beginning with "R_" are registers
+ Definitions beginning with "B_" are bits within registers
+ Definitions beginning with "V_" are meaningful values within the bits
+ Definitions beginning with "S_" are register size
+ Definitions beginning with "N_" are the bit position
+ - [GenerationName]:
+ Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc.).
+ Register name without GenerationName applies to all generations.
+ - [ComponentName]:
+ This field indicates the component name that the register belongs to (e.g. PCH, SA etc.)
+ Register name without ComponentName applies to all components.
+ Register that is specific to -H denoted by "_PCH_H_" in component name.
+ Register that is specific to -LP denoted by "_PCH_LP_" in component name.
+ - SubsystemName:
+ This field indicates the subsystem name of the component that the register belongs to
+ (e.g. PCIE, USB, SATA, GPIO, PMC etc.).
+ - RegisterSpace:
+ MEM - MMIO space register of subsystem.
+ IO - IO space register of subsystem.
+ PCR - Private configuration register of subsystem.
+ CFG - PCI configuration space register of subsystem.
+ - RegisterName:
+ Full register name.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/ #ifndef
+_P2SB_REGS_H_ #define _P2SB_REGS_H_
+
+//
+// Definition for SBI
+//
+#define R_P2SB_CFG_SBIADDR 0xD0
+#define R_P2SB_CFG_SBIDATA 0xD4
+#define R_P2SB_CFG_SBISTAT 0xD8
+#define B_P2SB_CFG_SBISTAT_OPCODE 0xFF00
+#define B_P2SB_CFG_SBISTAT_POSTED BIT7
+#define B_P2SB_CFG_SBISTAT_RESPONSE 0x0006
+#define N_P2SB_CFG_SBISTAT_RESPONSE 1
+#define B_P2SB_CFG_SBISTAT_INITRDY BIT0
+#define R_P2SB_CFG_SBIRID 0xDA
+#define R_P2SB_CFG_SBIEXTADDR 0xDC
+
+#endif
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/Library/PeiDxeSmmPchPcrLib/PchPcrLib.c b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/Library/PeiDxeSmmPchPcrLib/PchPcrLib.c
new file mode 100644
index 0000000000..a5b18613bc
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/Library/PeiDxeSmmPc
+++ hPcrLib/PchPcrLib.c
@@ -0,0 +1,266 @@
+/** @file
+ PCH PCR library.
+ All function in this library is available for PEI, DXE, and SMM,
+ But do not support UEFI RUNTIME environment call.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/
+
+#include <Base.h>
+#include <Uefi/UefiBaseType.h>
+#include <Library/IoLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseLib.h>
+#include <Library/PchInfoLib.h>
+#include <Library/PchPcrLib.h>
+#include <Library/PchSbiAccessLib.h>
+#include <Library/PciSegmentLib.h>
+#include <Register/PchPcrRegs.h>
+
+#ifndef MDEPKG_NDEBUG
+/**
+ Checks if the offset is valid for a given memory access width. Offset must align to width size.
+
+ @param[in] Offset Offset of a register
+ @param[in] Size Size of memory access in bytes
+
+ @retval FALSE Offset is not valid for a given memory access
+ @retval TRUE Offset is valid
+**/
+STATIC
+BOOLEAN
+PchIsPcrOffsetValid (
+ IN UINT32 Offset,
+ IN UINTN Size
+ )
+{
+ if (!IsP2sb20bPcrSupported ()) {
+ if (((Offset & (Size - 1)) != 0) || (Offset > 0xFFFF)) {
+ DEBUG ((DEBUG_ERROR, "PCR offset error. Invalid Offset: %x Size: %x", Offset, Size));
+ return FALSE;
+ } else {
+ return TRUE;
+ }
+ } else {
+ if (((Offset & (Size - 1)) != 0) || (Offset > 0xFFFFF)) {
+ DEBUG ((DEBUG_ERROR, "PCR offset error. Invalid Offset: %x Size: %x", Offset, Size));
+ return FALSE;
+ } else {
+ return TRUE;
+ }
+ }
+}
+#endif
+
+/**
+ Read PCR register.
+ It returns PCR register and size in 4bytes.
+ The Offset should not exceed 0xFFFF and must be aligned with size.
+
+ @param[in] Pid Port ID
+ @param[in] Offset Register offset of this Port ID
+
+ @retval UINT32 PCR register value.
+**/
+UINT32
+PchPcrRead32 (
+ IN PCH_SBI_PID Pid,
+ IN UINT32 Offset
+ )
+{
+#ifndef MDEPKG_NDEBUG
+ ASSERT (PchIsPcrOffsetValid (Offset, 4)); #endif
+ return MmioRead32 (PCH_PCR_ADDRESS (Pid, Offset)); }
+
+/**
+ Read PCR register.
+ It returns PCR register and size in 2bytes.
+ The Offset should not exceed 0xFFFF and must be aligned with size.
+
+ @param[in] Pid Port ID
+ @param[in] Offset Register offset of this Port ID
+
+ @retval UINT16 PCR register value.
+**/
+UINT16
+PchPcrRead16 (
+ IN PCH_SBI_PID Pid,
+ IN UINT32 Offset
+ )
+{
+#ifndef MDEPKG_NDEBUG
+ ASSERT (PchIsPcrOffsetValid (Offset, 2)); #endif
+ return MmioRead16 (PCH_PCR_ADDRESS (Pid, Offset)); }
+
+/**
+ Read PCR register.
+ It returns PCR register and size in 1bytes.
+ The Offset should not exceed 0xFFFF and must be aligned with size.
+
+ @param[in] Pid Port ID
+ @param[in] Offset Register offset of this Port ID
+
+ @retval UINT8 PCR register value
+**/
+UINT8
+PchPcrRead8 (
+ IN PCH_SBI_PID Pid,
+ IN UINT32 Offset
+ )
+{
+ return MmioRead8 (PCH_PCR_ADDRESS (Pid, Offset)); }
+
+/**
+ Write PCR register.
+ It programs PCR register and size in 4bytes.
+ The Offset should not exceed 0xFFFF and must be aligned with size.
+
+ @param[in] Pid Port ID
+ @param[in] Offset Register offset of Port ID.
+ @param[in] Data Input Data. Must be the same size as Size parameter.
+
+ @retval UINT32 Value written to register
+**/
+UINT32
+PchPcrWrite32 (
+ IN PCH_SBI_PID Pid,
+ IN UINT32 Offset,
+ IN UINT32 Data
+ )
+{
+#ifndef MDEPKG_NDEBUG
+ ASSERT (PchIsPcrOffsetValid (Offset, 4)); #endif
+ MmioWrite32 (PCH_PCR_ADDRESS (Pid, Offset), Data);
+
+ return Data;
+
+}
+
+/**
+ Write PCR register.
+ It programs PCR register and size in 2bytes.
+ The Offset should not exceed 0xFFFF and must be aligned with size.
+
+ @param[in] Pid Port ID
+ @param[in] Offset Register offset of Port ID.
+ @param[in] Data Input Data. Must be the same size as Size parameter.
+
+ @retval UINT16 Value written to register
+**/
+UINT16
+PchPcrWrite16 (
+ IN PCH_SBI_PID Pid,
+ IN UINT32 Offset,
+ IN UINT16 Data
+ )
+{
+#ifndef MDEPKG_NDEBUG
+ ASSERT (PchIsPcrOffsetValid (Offset, 2)); #endif
+ MmioWrite16 (PCH_PCR_ADDRESS (Pid, Offset), Data);
+
+ return Data;
+}
+
+/**
+ Write PCR register.
+ It programs PCR register and size in 1bytes.
+ The Offset should not exceed 0xFFFF and must be aligned with size.
+
+ @param[in] Pid Port ID
+ @param[in] Offset Register offset of Port ID.
+ @param[in] Data Input Data. Must be the same size as Size parameter.
+
+ @retval UINT8 Value written to register
+**/
+UINT8
+PchPcrWrite8 (
+ IN PCH_SBI_PID Pid,
+ IN UINT32 Offset,
+ IN UINT8 Data
+ )
+{
+
+ MmioWrite8 (PCH_PCR_ADDRESS (Pid, Offset), Data);
+
+ return Data;
+}
+
+/**
+ Write PCR register.
+ It programs PCR register and size in 4bytes.
+ The Offset should not exceed 0xFFFF and must be aligned with size.
+
+ @param[in] Pid Port ID
+ @param[in] Offset Register offset of Port ID.
+ @param[in] AndData AND Data. Must be the same size as Size parameter.
+ @param[in] OrData OR Data. Must be the same size as Size parameter.
+
+ @retval UINT32 Value written to register
+
+**/
+UINT32
+PchPcrAndThenOr32 (
+ IN PCH_SBI_PID Pid,
+ IN UINT32 Offset,
+ IN UINT32 AndData,
+ IN UINT32 OrData
+ )
+{
+ return PchPcrWrite32 (Pid, Offset, (PchPcrRead32 (Pid, Offset) &
+AndData) | OrData); }
+
+/**
+ Write PCR register.
+ It programs PCR register and size in 2bytes.
+ The Offset should not exceed 0xFFFF and must be aligned with size.
+
+ @param[in] Pid Port ID
+ @param[in] Offset Register offset of Port ID.
+ @param[in] AndData AND Data. Must be the same size as Size parameter.
+ @param[in] OrData OR Data. Must be the same size as Size parameter.
+
+ @retval UINT16 Value written to register
+
+**/
+UINT16
+PchPcrAndThenOr16 (
+ IN PCH_SBI_PID Pid,
+ IN UINT32 Offset,
+ IN UINT16 AndData,
+ IN UINT16 OrData
+ )
+{
+ return PchPcrWrite16 (Pid, Offset, (PchPcrRead16 (Pid, Offset) &
+AndData) | OrData); }
+
+/**
+ Write PCR register.
+ It programs PCR register and size in 1bytes.
+ The Offset should not exceed 0xFFFF and must be aligned with size.
+
+ @param[in] Pid Port ID
+ @param[in] Offset Register offset of Port ID.
+ @param[in] AndData AND Data. Must be the same size as Size parameter.
+ @param[in] OrData OR Data. Must be the same size as Size parameter.
+
+ @retval UINT8 Value written to register
+
+**/
+UINT8
+PchPcrAndThenOr8 (
+ IN PCH_SBI_PID Pid,
+ IN UINT32 Offset,
+ IN UINT8 AndData,
+ IN UINT8 OrData
+ )
+{
+ return PchPcrWrite8 (Pid, Offset, (PchPcrRead8 (Pid, Offset) &
+AndData) | OrData); }
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/Library/PeiDxeSmmPchPcrLib/PeiDxeSmmPchPcrLib.inf b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/Library/PeiDxeSmmPchPcrLib/PeiDxeSmmPchPcrLib.inf
new file mode 100644
index 0000000000..5e1b4914d8
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/Library/PeiDxeSmmPc
+++ hPcrLib/PeiDxeSmmPchPcrLib.inf
@@ -0,0 +1,35 @@
+## @file
+# PCH PCR Library.
+#
+# All function in this library is available for PEI, DXE, and SMM, #
+But do not support UEFI RUNTIME environment call.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+
+[Defines]
+INF_VERSION = 0x00010017
+BASE_NAME = PeiDxeSmmPchPcrLib
+FILE_GUID = 117C8D19-445B-46BF-B624-109F63709375
+VERSION_STRING = 1.0
+MODULE_TYPE = BASE
+LIBRARY_CLASS = PchPcrLib
+
+
+[LibraryClasses]
+BaseLib
+IoLib
+DebugLib
+PchInfoLib
+PchSbiAccessLib
+PciSegmentLib
+
+[Packages]
+MdePkg/MdePkg.dec
+AlderlakeSiliconPkg/SiPkg.dec
+
+
+[Sources]
+PchPcrLib.c
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/LibraryPrivate/PeiDxeSmmP2SbSidebandAccessLib/PeiDxeSmmP2SbSidebandAccessLib.c b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/LibraryPrivate/PeiDxeSmmP2SbSidebandAccessLib/PeiDxeSmmP2SbSidebandAccessLib.c
new file mode 100644
index 0000000000..52ec8fd9e1
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/LibraryPrivate/PeiD
+++ xeSmmP2SbSidebandAccessLib/PeiDxeSmmP2SbSidebandAccessLib.c
@@ -0,0 +1,208 @@
+/** @file
+ P2SB sideband access lib
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/
+
+#include <Base.h>
+#include <Uefi/UefiBaseType.h>
+#include <Library/IoLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseLib.h>
+#include <Library/PchInfoLib.h>
+#include <Library/P2SbSidebandAccessLib.h> #include
+<Library/PciSegmentLib.h> #include <Library/PchSbiAccessLib.h> #include
+<Register/P2sbRegs.h> #include <IndustryStandard/Pci30.h>
+
+#define P2SB_PCR_ADDRESS(MmioBase, Pid, Offset) ((UINTN) MmioBase |
+(UINT32) (((Offset) & 0x0F0000) << 8) | ((UINT8)(Pid) << 16) | (UINT16)
+((Offset) & 0xFFFF))
+
+/**
+ Full function for executing P2SB SBI message
+ Take care of that there is no lock protection when using SBI programming in both POST time and SMI.
+ It will clash with POST time SBI programming when SMI happen.
+ Programmer MUST do the save and restore opration while using the
+PchSbiExecution inside SMI
+ to prevent from racing condition.
+ This function will reveal P2SB and hide P2SB if it's originally
+hidden. If more than one SBI access
+ needed, it's better to unhide the P2SB before calling and hide it back after done.
+
+ When the return value is "EFI_SUCCESS", the "Response" do not need to
+ be checked as it would have been SBI_SUCCESS. If the return value is
+ "EFI_DEVICE_ERROR", then this would provide additional information when needed.
+
+ @param[in] P2sbBase P2SB PCI config base
+ @param[in] Pid Port ID of the SBI message
+ @param[in] Offset Offset of the SBI message
+ @param[in] Opcode Opcode
+ @param[in] Posted Posted message
+ @param[in] Fbe First byte enable
+ @param[in] Bar Bar
+ @param[in] Fid Function ID
+ @param[in, out] Data32 Read/Write data
+ @param[out] Response Response
+
+ @retval EFI_SUCCESS Successfully completed.
+ @retval EFI_DEVICE_ERROR Transaction fail
+ @retval EFI_INVALID_PARAMETER Invalid parameter
+ @retval EFI_TIMEOUT Timeout while waiting for response
+**/
+EFI_STATUS
+P2SbSbiExecutionEx (
+ IN UINT64 P2sbBase,
+ IN P2SB_PID Pid,
+ IN UINT64 Offset,
+ IN P2SB_SBI_OPCODE Opcode,
+ IN BOOLEAN Posted,
+ IN UINT16 Fbe,
+ IN UINT16 Bar,
+ IN UINT16 Fid,
+ IN OUT UINT32 *Data32,
+ OUT UINT8 *Response
+ )
+{
+ INT32 Timeout;
+ UINT16 SbiStat;
+
+ //
+ // Check opcode valid
+ //
+ switch (Opcode) {
+ case MemoryRead:
+ case MemoryWrite:
+ case PciConfigRead:
+ case PciConfigWrite:
+ case PrivateControlRead:
+ case PrivateControlWrite:
+ case GpioLockUnlock:
+ break;
+ default:
+ return EFI_INVALID_PARAMETER;
+ break;
+ }
+
+ if (PciSegmentRead16 (P2sbBase + PCI_VENDOR_ID_OFFSET) == 0xFFFF) {
+ ASSERT (FALSE);
+ return EFI_DEVICE_ERROR;
+ }
+ ///
+ /// BWG Section 2.2.1
+ /// 1. Poll P2SB PCI offset D8h[0] = 0b /// Make sure the previous
+ opeartion is completed.
+ ///
+ Timeout = 0xFFFFFFF;
+ while (Timeout > 0) {
+ SbiStat = PciSegmentRead16 (P2sbBase + R_P2SB_CFG_SBISTAT);
+ if ((SbiStat & B_P2SB_CFG_SBISTAT_INITRDY) == 0) {
+ break;
+ }
+ Timeout--;
+ }
+ if (Timeout == 0) {
+ return EFI_TIMEOUT;
+ }
+ //
+ // Initial Response status
+ //
+ *Response = SBI_INVALID_RESPONSE;
+ SbiStat = 0;
+ ///
+ /// 2. Write P2SB PCI offset D0h[31:0] with Address and Destination
+ Port ID ///
+ PciSegmentWrite32 (P2sbBase + R_P2SB_CFG_SBIADDR, (UINT32) ((Pid <<
+ 24) | (UINT16) Offset)); /// /// 3. Write P2SB PCI offset DCh[31:0]
+ with extended address, which is expected to be 0 in CNL PCH.
+ ///
+ PciSegmentWrite32 (P2sbBase + R_P2SB_CFG_SBIEXTADDR, (UINT32)
+ RShiftU64 (Offset, 16)); /// /// 5. Set P2SB PCI offset D8h[15:8] =
+ 00000110b for read
+ /// Set P2SB PCI offset D8h[15:8] = 00000111b for write
+ //
+ // Set SBISTAT[15:8] to the opcode passed in // Set SBISTAT[7] to
+ the posted passed in //
+ PciSegmentAndThenOr16 (
+ (P2sbBase + R_P2SB_CFG_SBISTAT),
+ (UINT16) ~(B_P2SB_CFG_SBISTAT_OPCODE | B_P2SB_CFG_SBISTAT_POSTED),
+ (UINT16) ((Opcode << 8) | (Posted << 7))
+ );
+ ///
+ /// 6. Write P2SB PCI offset DAh[15:0] = F000h /// // // Set
+ RID[15:0] = Fbe << 12 | Bar << 8 | Fid //
+ PciSegmentWrite16 (
+ (P2sbBase + R_P2SB_CFG_SBIRID),
+ (((Fbe & 0x000F) << 12) | ((Bar & 0x0007) << 8) | (Fid & 0x00FF))
+ );
+
+ switch (Opcode) {
+ case MemoryWrite:
+ case PciConfigWrite:
+ case PrivateControlWrite:
+ case GpioLockUnlock:
+ ///
+ /// 4. Write P2SB PCI offset D4h[31:0] with the intended data accordingly
+ ///
+ PciSegmentWrite32 ((P2sbBase + R_P2SB_CFG_SBIDATA), *Data32);
+ break;
+ default:
+ ///
+ /// 4. Write P2SB PCI offset D4h[31:0] with dummy data such as 0,
+ /// because all D0-DFh register range must be touched in CNL PCH
+ /// for a successful SBI transaction.
+ ///
+ PciSegmentWrite32 ((P2sbBase + R_P2SB_CFG_SBIDATA), 0);
+ break;
+ }
+ ///
+ /// 7. Set P2SB PCI offset D8h[0] = 1b, Poll P2SB PCI offset D8h[0] =
+0b
+ ///
+ //
+ // Set SBISTAT[0] = 1b, trigger the SBI operation
+ //
+ PciSegmentOr16 (P2sbBase + R_P2SB_CFG_SBISTAT, (UINT16)
+B_P2SB_CFG_SBISTAT_INITRDY);
+ //
+ // Poll SBISTAT[0] = 0b, Polling for Busy bit
+ //
+ Timeout = 0xFFFFFFF;
+ while (Timeout > 0) {
+ SbiStat = PciSegmentRead16 (P2sbBase + R_P2SB_CFG_SBISTAT);
+ if ((SbiStat & B_P2SB_CFG_SBISTAT_INITRDY) == 0) {
+ break;
+ }
+ Timeout--;
+ }
+ if (Timeout == 0) {
+ //
+ // If timeout, it's fatal error.
+ //
+ return EFI_TIMEOUT;
+ } else {
+ ///
+ /// 8. Check if P2SB PCI offset D8h[2:1] = 00b for successful transaction
+ ///
+ *Response = (UINT8) ((SbiStat & B_P2SB_CFG_SBISTAT_RESPONSE) >> N_P2SB_CFG_SBISTAT_RESPONSE);
+ if (*Response == SBI_SUCCESSFUL) {
+ switch (Opcode) {
+ case MemoryRead:
+ case PciConfigRead:
+ case PrivateControlRead:
+ ///
+ /// 9. Read P2SB PCI offset D4h[31:0] for SBI data
+ ///
+ *Data32 = PciSegmentRead32 (P2sbBase + R_P2SB_CFG_SBIDATA);
+ break;
+ default:
+ break;
+ }
+ return EFI_SUCCESS;
+ } else if (*Response == SBI_POWERDOWN) {
+ return EFI_NO_RESPONSE;
+ } else {
+ return EFI_DEVICE_ERROR;
+ }
+ }
+}
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/LibraryPrivate/PeiDxeSmmP2SbSidebandAccessLib/PeiDxeSmmP2SbSidebandAccessLib.inf b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/LibraryPrivate/PeiDxeSmmP2SbSidebandAccessLib/PeiDxeSmmP2SbSidebandAccessLib.inf
new file mode 100644
index 0000000000..9530e56940
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/LibraryPrivate/PeiD
+++ xeSmmP2SbSidebandAccessLib/PeiDxeSmmP2SbSidebandAccessLib.inf
@@ -0,0 +1,30 @@
+## @file
+# Library for accessing sideband register banks via the P2SB router.
+#
+# All function in this library is available for PEI, DXE, and SMM, #
+But do not support UEFI RUNTIME environment call.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+
+[Defines]
+INF_VERSION = 0x00010017
+BASE_NAME = PeiDxeSmmP2SbSidebandAccessLib FILE_GUID =
+425C479D-A489-4382-8C28-59A3521A24FF
+VERSION_STRING = 1.0
+MODULE_TYPE = BASE
+LIBRARY_CLASS = P2SbSidebandAccessLib
+
+[LibraryClasses]
+BaseLib
+IoLib
+DebugLib
+
+[Packages]
+MdePkg/MdePkg.dec
+AlderlakeSiliconPkg/SiPkg.dec
+
+[Sources]
+PeiDxeSmmP2SbSidebandAccessLib.c
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/LibraryPrivate/PeiDxeSmmPchSbiAccessLib/PchSbiAccessLib.c b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/LibraryPrivate/PeiDxeSmmPchSbiAccessLib/PchSbiAccessLib.c
new file mode 100644
index 0000000000..1f7bb82692
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/LibraryPrivate/PeiD
+++ xeSmmPchSbiAccessLib/PchSbiAccessLib.c
@@ -0,0 +1,72 @@
+/** @file
+ PCH SBI access library.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/
+
+#include <Base.h>
+#include <Uefi/UefiBaseType.h>
+#include <Library/IoLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseLib.h>
+#include <Library/PchSbiAccessLib.h>
+#include <Library/P2SbSidebandAccessLib.h> #include
+<Library/PchPciBdfLib.h> #include <Register/PchRegs.h> #include
+<Register/P2sbRegs.h>
+
+/**
+ Full function for executing PCH SBI message
+ Take care of that there is no lock protection when using SBI programming in both POST time and SMI.
+ It will clash with POST time SBI programming when SMI happen.
+ Programmer MUST do the save and restore opration while using the
+PchSbiExecution inside SMI
+ to prevent from racing condition.
+ This function will reveal P2SB and hide P2SB if it's originally
+hidden. If more than one SBI access
+ needed, it's better to unhide the P2SB before calling and hide it back after done.
+
+ When the return value is "EFI_SUCCESS", the "Response" do not need to
+ be checked as it would have been SBI_SUCCESS. If the return value is
+ "EFI_DEVICE_ERROR", then this would provide additional information when needed.
+
+ @param[in] Pid Port ID of the SBI message
+ @param[in] Offset Offset of the SBI message
+ @param[in] Opcode Opcode
+ @param[in] Posted Posted message
+ @param[in] Fbe First byte enable
+ @param[in] Bar Bar
+ @param[in] Fid Function ID
+ @param[in, out] Data32 Read/Write data
+ @param[out] Response Response
+
+ @retval EFI_SUCCESS Successfully completed.
+ @retval EFI_DEVICE_ERROR Transaction fail
+ @retval EFI_INVALID_PARAMETER Invalid parameter
+ @retval EFI_TIMEOUT Timeout while waiting for response
+**/
+EFI_STATUS
+PchSbiExecutionEx (
+ IN PCH_SBI_PID Pid,
+ IN UINT64 Offset,
+ IN PCH_SBI_OPCODE Opcode,
+ IN BOOLEAN Posted,
+ IN UINT16 Fbe,
+ IN UINT16 Bar,
+ IN UINT16 Fid,
+ IN OUT UINT32 *Data32,
+ OUT UINT8 *Response
+ )
+{
+ return P2SbSbiExecutionEx (
+ P2sbPciCfgBase (),
+ Pid,
+ Offset,
+ Opcode,
+ Posted,
+ Fbe,
+ Bar,
+ Fid,
+ Data32,
+ Response
+ );
+}
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/LibraryPrivate/PeiDxeSmmPchSbiAccessLib/PeiDxeSmmPchSbiAccessLib.inf b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/LibraryPrivate/PeiDxeSmmPchSbiAccessLib/PeiDxeSmmPchSbiAccessLib.inf
new file mode 100644
index 0000000000..a28a90c74b
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/LibraryPrivate/PeiD
+++ xeSmmPchSbiAccessLib/PeiDxeSmmPchSbiAccessLib.inf
@@ -0,0 +1,35 @@
+## @file
+# PCH SBI access library.
+#
+# All function in this library is available for PEI, DXE, and SMM, #
+But do not support UEFI RUNTIME environment call.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+
+[Defines]
+INF_VERSION = 0x00010017
+BASE_NAME = PeiDxeSmmPchSbiAccessLib
+FILE_GUID = 96ECB0FB-A975-4DC8-B88A-D90C3378CE87
+VERSION_STRING = 1.0
+MODULE_TYPE = BASE
+LIBRARY_CLASS = PchSbiAccessLib
+
+
+[LibraryClasses]
+BaseLib
+IoLib
+DebugLib
+PchPciBdfLib
+P2SbSidebandAccessLib
+
+
+[Packages]
+MdePkg/MdePkg.dec
+AlderlakeSiliconPkg/SiPkg.dec
+
+
+[Sources]
+PchSbiAccessLib.c
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PchDmi/IncludePrivate/Library/PchDmiLib.h b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PchDmi/IncludePrivate/Library/PchDmiLib.h
new file mode 100644
index 0000000000..efbb76f6be
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PchDmi/IncludePrivate/Li
+++ brary/PchDmiLib.h
@@ -0,0 +1,60 @@
+/** @file
+ Header file for PchDmiLib.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/ #ifndef
+_PCH_DMI_LIB_H_ #define _PCH_DMI_LIB_H_
+
+/**
+ This function checks if DMI Secured Register Lock (SRL) is set
+
+ @retval SRL state
+**/
+BOOLEAN
+IsPchDmiLocked (
+ VOID
+ );
+
+/**
+ Get PCH TCO base address.
+
+ @retval Address Address of TCO base address.
+**/
+UINT16
+PchDmiGetTcoBase (
+ VOID
+ );
+
+/**
+ Set PCH LPC/eSPI IO decode ranges in DMI
+ Please check EDS for detail of LPC/eSPI IO decode ranges bit definition.
+ Bit 12: FDD range
+ Bit 9:8: LPT range
+ Bit 6:4: ComB range
+ Bit 2:0: ComA range
+
+ @param[in] LpcIoDecodeRanges LPC/eSPI IO decode ranges bit settings.
+
+ @retval EFI_SUCCESS Successfully completed.
+ @retval EFI_UNSUPPORTED DMIC.SRL is set.
+**/
+EFI_STATUS
+PchDmiSetLpcIoDecodeRanges (
+ IN UINT16 LpcIoDecodeRanges
+ );
+
+/**
+ Set PCH LPC/eSPI IO enable decoding in DMI
+
+ @param[in] LpcIoEnableDecoding LPC/eSPI IO enable decoding bit settings.
+
+ @retval EFI_SUCCESS Successfully completed.
+ @retval EFI_UNSUPPORTED DMIC.SRL is set.
+**/
+EFI_STATUS
+PchDmiSetLpcIoEnable (
+ IN UINT16 LpcIoEnableDecoding
+ );
+#endif // _PCH_DMI_LIB_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivate/PeiDxeSmmPchDmiLib/PchDmi14.c b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivate/PeiDxeSmmPchDmiLib/PchDmi14.c
new file mode 100644
index 0000000000..9f49790372
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivate/Pe
+++ iDxeSmmPchDmiLib/PchDmi14.c
@@ -0,0 +1,34 @@
+/** @file
+ This file contains functions for PCH DMI SIP14
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/
+
+#include <Base.h>
+#include <Uefi/UefiBaseType.h>
+#include <Library/IoLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseLib.h>
+#include <Library/PchInfoLib.h>
+#include <Library/PchPcrLib.h>
+#include <Library/PchDmiLib.h>
+#include <Library/PchCycleDecodingLib.h> #include <Library/PchPcrLib.h>
+#include <Library/PchInfoLib.h> #include <Register/PchDmiRegs.h>
+#include <Register/PchDmi14Regs.h> #include <Register/PchPcrRegs.h>
+
+/**
+ This function checks if DMI SIP14 Secured Register Lock (SRL) is set
+
+ @retval SRL state
+**/
+BOOLEAN
+IsPchDmi14Locked (
+ VOID
+ )
+{
+ return ((PchPcrRead32 (PID_DMI, R_PCH_DMI14_PCR_DMIC) &
+B_PCH_DMI14_PCR_DMIC_SRL) != 0); }
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivate/PeiDxeSmmPchDmiLib/PchDmi14.h b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivate/PeiDxeSmmPchDmiLib/PchDmi14.h
new file mode 100644
index 0000000000..494caebb4a
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivate/Pe
+++ iDxeSmmPchDmiLib/PchDmi14.h
@@ -0,0 +1,22 @@
+/** @file
+ Internal header file for PCH DMI library for SIP14
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/ #ifndef
+__PCH_DMI_14_H__ #define __PCH_DMI_14_H__
+
+#include <Library/PchDmiLib.h>
+
+/**
+ This function checks if DMI SIP14 Secured Register Lock (SRL) is set
+
+ @retval SRL state
+**/
+BOOLEAN
+IsPchDmi14Locked (
+ VOID
+ );
+
+#endif
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivate/PeiDxeSmmPchDmiLib/PchDmiLib.c b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivate/PeiDxeSmmPchDmiLib/PchDmiLib.c
new file mode 100644
index 0000000000..3d5436f1a3
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivate/Pe
+++ iDxeSmmPchDmiLib/PchDmiLib.c
@@ -0,0 +1,110 @@
+/** @file
+ PCH DMI library.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/ #include <Base.h>
+#include <Uefi/UefiBaseType.h> #include <Library/IoLib.h> #include
+<Library/DebugLib.h> #include <Library/BaseLib.h> #include
+<Library/PchInfoLib.h> #include <Library/PchPcrLib.h> #include
+<Library/PchDmiLib.h> #include <Library/PchCycleDecodingLib.h> #include
+<Register/PchPcrRegs.h> #include <Register/PchDmiRegs.h> #include
+<Register/PchRegsLpc.h>
+
+#include "PchDmi14.h"
+
+/**
+ This function checks if DMI Secured Register Lock (SRL) is set
+
+ @retval SRL state
+**/
+BOOLEAN
+IsPchDmiLocked (
+ VOID
+ )
+{
+ return IsPchDmi14Locked ();
+}
+
+/**
+ Get PCH TCO base address.
+
+ @retval Address Address of TCO base address.
+**/
+UINT16
+PchDmiGetTcoBase (
+ VOID
+ )
+{
+ //
+ // Read "TCO Base Address" PCR[DMI] + 2778h[15:5]
+ //
+ return (PchPcrRead16 (PID_DMI, R_PCH_DMI_PCR_TCOBASE) &
+B_PCH_DMI_PCR_TCOBASE_TCOBA); }
+
+/**
+ Set PCH LPC/eSPI IO decode ranges in DMI
+ Please check EDS for detail of LPC/eSPI IO decode ranges bit definition.
+ Bit 12: FDD range
+ Bit 9:8: LPT range
+ Bit 6:4: ComB range
+ Bit 2:0: ComA range
+
+ @param[in] LpcIoDecodeRanges LPC/eSPI IO decode ranges bit settings.
+
+ @retval EFI_SUCCESS Successfully completed.
+ @retval EFI_UNSUPPORTED DMIC.SRL is set.
+**/
+EFI_STATUS
+PchDmiSetLpcIoDecodeRanges (
+ IN UINT16 LpcIoDecodeRanges
+ )
+{
+ //
+ // This cycle decoding is only allowed to set when DMI is not locked.
+ //
+ if (IsPchDmiLocked ()) {
+ ASSERT (FALSE);
+ return EFI_UNSUPPORTED;
+ }
+
+ //
+ // program LPC I/O Decode Ranges, PCR[DMI] + 2770h[15:0] to the same value programmed in LPC/eSPI PCI offset 80h.
+ //
+ PchPcrWrite16 (PID_DMI, R_PCH_DMI_PCR_LPCIOD, LpcIoDecodeRanges);
+ return EFI_SUCCESS;
+}
+
+/**
+ Set PCH LPC/eSPI IO enable decoding in DMI
+
+ @param[in] LpcIoEnableDecoding LPC/eSPI IO enable decoding bit settings.
+
+ @retval EFI_SUCCESS Successfully completed.
+ @retval EFI_UNSUPPORTED DMIC.SRL is set.
+**/
+EFI_STATUS
+PchDmiSetLpcIoEnable (
+ IN UINT16 LpcIoEnableDecoding
+ )
+{
+ //
+ // This cycle decoding is only allowed to set when DMI is not locked.
+ //
+ if (IsPchDmiLocked ()) {
+ ASSERT (FALSE);
+ return EFI_UNSUPPORTED;
+ }
+
+ //
+ // program LPC I/O Decode Ranges, PCR[DMI] + 2774h[15:0] to the same value programmed in LPC/eSPI PCI offset 82h.
+ //
+ PchPcrWrite16 (PID_DMI, R_PCH_DMI_PCR_LPCIOE, LpcIoEnableDecoding);
+ return EFI_SUCCESS;
+}
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivate/PeiDxeSmmPchDmiLib/PeiDxeSmmPchDmiLib.inf b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivate/PeiDxeSmmPchDmiLib/PeiDxeSmmPchDmiLib.inf
new file mode 100644
index 0000000000..4e92117be3
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivate/Pe
+++ iDxeSmmPchDmiLib/PeiDxeSmmPchDmiLib.inf
@@ -0,0 +1,43 @@
+## @file
+# Component description file for the PeiDxeSmmPchDmiLib #
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+[Defines]
+INF_VERSION = 0x00010017
+BASE_NAME = PeiDxeSmmPchDmiLib
+FILE_GUID = 067DC1C4-2668-4F06-9921-307514B66B34
+VERSION_STRING = 1.0
+MODULE_TYPE = BASE
+LIBRARY_CLASS = PchDmiLib
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = IA32 X64
+#
+
+[LibraryClasses]
+ BaseLib
+ IoLib
+ DebugLib
+ PchInfoLib
+ PchPcrLib
+
+
+[Packages]
+ MdePkg/MdePkg.dec
+ AlderlakeSiliconPkg/SiPkg.dec
+
+
+[Sources]
+ PchDmiLib.c
+ PchDmi14.c
+ PchDmi14.h
+
+[Guids]
+ gPchDmiConfigGuid ## CONSUMES
+ gPchDmiPreMemConfigGuid ## CONSUMES
+
+[Pcd]
--
2.36.1.windows.1
-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#108721): https://edk2.groups.io/g/devel/message/108721
Mute This Topic: https://groups.io/mt/101373946/7686176
Group Owner: devel+owner@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [rebecca@openfw.io]
-=-=-=-=-=-=-=-=-=-=-=-
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [edk2-devel] [PATCH v2 04/10] AlderlakeSiliconPkg/IpBlock: Add Pmc, Spi components
2023-09-15 5:42 ` Chaganty, Rangasai V
@ 2023-09-15 13:28 ` Chuang, Rosen
0 siblings, 0 replies; 41+ messages in thread
From: Chuang, Rosen @ 2023-09-15 13:28 UTC (permalink / raw)
To: Chaganty, Rangasai V, Kasbekar, Saloni, devel@edk2.groups.io
Cc: Desimone, Nathaniel L
Reviewed-by: Rosen Chuang <rosen.chuang@intel.com>
-----Original Message-----
From: Chaganty, Rangasai V <rangasai.v.chaganty@intel.com>
Sent: Friday, September 15, 2023 1:43 PM
To: Kasbekar, Saloni <saloni.kasbekar@intel.com>; devel@edk2.groups.io
Cc: Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>; Chuang, Rosen <rosen.chuang@intel.com>
Subject: RE: [PATCH v2 04/10] AlderlakeSiliconPkg/IpBlock: Add Pmc, Spi components
Reviewed-by: Sai Chaganty <rangasai.v.chaganty@intel.com>
-----Original Message-----
From: Kasbekar, Saloni <saloni.kasbekar@intel.com>
Sent: Thursday, September 14, 2023 9:46 PM
To: devel@edk2.groups.io
Cc: Kasbekar, Saloni <saloni.kasbekar@intel.com>; Chaganty, Rangasai V <rangasai.v.chaganty@intel.com>; Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>; Chuang, Rosen <rosen.chuang@intel.com>
Subject: [PATCH v2 04/10] AlderlakeSiliconPkg/IpBlock: Add Pmc, Spi components
Adds the following modules:
- IpBlock/Pmc/IncludePrivate
- IpBlock/Pmc/Library
- IpBlock/Pmc/LibraryPrivate
- IpBlock/Spi/IncludePrivate
- IpBlock/Spi/Library
- IpBlock/Spi/LibraryPrivate
- IpBlock/Spi/Smm
Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Rosen Chuang <rosen.chuang@intel.com>
Signed-off-by: Saloni Kasbekar <saloni.kasbekar@intel.com>
---
.../IncludePrivate/Library/PmcPrivateLib.h | 47 +
.../IpBlock/Pmc/IncludePrivate/PmcSocConfig.h | 67 +
.../PeiDxeSmmPmcLib/PeiDxeSmmPmcLib.inf | 38 +
.../Pmc/Library/PeiDxeSmmPmcLib/PmcLib.c | 50 +
.../PeiDxeSmmPmcPrivateLib.inf | 43 +
.../PeiDxeSmmPmcPrivateLib/PmcPrivateLib.c | 86 ++
.../Spi/IncludePrivate/Library/SpiCommonLib.h | 376 ++++++
.../Spi/IncludePrivate/Register/SpiRegs.h | 116 ++
.../IpBlock/Spi/Library/PeiSpiLib/PchSpi.c | 209 +++
.../Spi/Library/PeiSpiLib/PeiSpiLib.inf | 41 +
.../BaseSpiCommonLib/BaseSpiCommonLib.inf | 29 +
.../BaseSpiCommonLib/SpiCommon.c | 1127 +++++++++++++++++
.../AlderlakeSiliconPkg/IpBlock/Spi/Smm/Spi.c | 387 ++++++
.../IpBlock/Spi/Smm/SpiSmm.inf | 46 +
14 files changed, 2662 insertions(+)
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Pmc/IncludePrivate/Library/PmcPrivateLib.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Pmc/IncludePrivate/PmcSocConfig.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Pmc/Library/PeiDxeSmmPmcLib/PeiDxeSmmPmcLib.inf
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Pmc/Library/PeiDxeSmmPmcLib/PmcLib.c
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Pmc/LibraryPrivate/PeiDxeSmmPmcPrivateLib/PeiDxeSmmPmcPrivateLib.inf
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Pmc/LibraryPrivate/PeiDxeSmmPmcPrivateLib/PmcPrivateLib.c
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/IncludePrivate/Library/SpiCommonLib.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/IncludePrivate/Register/SpiRegs.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/Library/PeiSpiLib/PchSpi.c
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/Library/PeiSpiLib/PeiSpiLib.inf
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/LibraryPrivate/BaseSpiCommonLib/BaseSpiCommonLib.inf
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/LibraryPrivate/BaseSpiCommonLib/SpiCommon.c
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/Smm/Spi.c
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/Smm/SpiSmm.inf
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Pmc/IncludePrivate/Library/PmcPrivateLib.h b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Pmc/IncludePrivate/Library/PmcPrivateLib.h
new file mode 100644
index 0000000000..6ec244b127
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Pmc/IncludePrivate/Library/PmcPrivateLib.h
@@ -0,0 +1,47 @@
+/** @file
+ Header file for private PmcLib.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _PMC_PRIVATE_LIB_H_
+#define _PMC_PRIVATE_LIB_H_
+
+#include <Library/PmcLib.h>
+#include "Register/PmcRegs.h"
+
+typedef enum {
+ PmcSwSmiRate1p5ms = 0,
+ PmcSwSmiRate16ms,
+ PmcSwSmiRate32ms,
+ PmcSwSmiRate64ms
+} PMC_SWSMI_RATE;
+
+/**
+ This function sets SW SMI Rate.
+
+ @param[in] SwSmiRate Refer to PMC_SWSMI_RATE for possible values
+**/
+VOID
+PmcSetSwSmiRate (
+ IN PMC_SWSMI_RATE SwSmiRate
+ );
+
+typedef enum {
+ PmcPeriodicSmiRate8s = 0,
+ PmcPeriodicSmiRate16s,
+ PmcPeriodicSmiRate32s,
+ PmcPeriodicSmiRate64s
+} PMC_PERIODIC_SMI_RATE;
+
+/**
+ This function sets Periodic SMI Rate.
+
+ @param[in] PeriodicSmiRate Refer to PMC_PERIODIC_SMI_RATE for possible values
+**/
+VOID
+PmcSetPeriodicSmiRate (
+ IN PMC_PERIODIC_SMI_RATE PeriodicSmiRate
+ );
+
+#endif // _PMC_PRIVATE_LIB_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Pmc/IncludePrivate/PmcSocConfig.h b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Pmc/IncludePrivate/PmcSocConfig.h
new file mode 100644
index 0000000000..523a84a180
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Pmc/IncludePrivate/PmcSocConfig.h
@@ -0,0 +1,67 @@
+/** @file
+ PMC SoC configuration
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PMC_SOC_CONFIGURATION_H_
+#define _PMC_SOC_CONFIGURATION_H_
+
+typedef enum {
+ AdrSinglePhase = 0,
+ AdrDualPhase
+} ADR_PHASE_TYPE;
+
+typedef enum {
+ AdrGpioB = 0,
+ AdrGpioC
+} ADR_GPIO;
+
+typedef enum {
+ AdrOverPmSync = 0,
+ AdrOverDmi
+} ADR_MSG_INTERFACE;
+
+typedef struct {
+ BOOLEAN Supported;
+ ADR_PHASE_TYPE AdrPhaseType;
+ ADR_GPIO AdrGpio;
+ ADR_MSG_INTERFACE AdrMsgInterface;
+ //
+ // On some designs ADR_GEN_CFG has been moved in the HW.
+ // Set this to if ADR_GEN_CFG is located at 0x1908
+ //
+ BOOLEAN AdrGenCfgMoved;
+} PMC_ADR_SOC_CONFIG;
+
+typedef struct {
+ BOOLEAN CppmCgInterfaceVersion;
+ BOOLEAN LpmSupported;
+ UINT8 LpmInterfaceVersion;
+ BOOLEAN OsIdleSupported;
+ BOOLEAN TimedGpioSupported;
+ UINT32 CpuIovrRampTime;
+ BOOLEAN PsOnSupported;
+ BOOLEAN ModPhySusPgSupported;
+ UINT8 SciIrq;
+ BOOLEAN FabricPowerGatingCppmQualificationEnable;
+ BOOLEAN EspiBoot;
+ BOOLEAN UsbDbcConnected;
+ UINT32 Usb3LanesConnectedBitmask;
+ BOOLEAN DisableIosfSbClockGating;
+ BOOLEAN SkipModPhyGatingPolicy;
+ PMC_ADR_SOC_CONFIG AdrSocConfig;
+ BOOLEAN AllSbrIdleQualifierEnable;
+ UINT32 LpmPriVal; ///< Low Power Mode Priority
+
+} PMC_SOC_CONFIG;
+
+typedef struct {
+ BOOLEAN OverrideFetRampTime;
+ UINT8 FetRampTime;
+ UINT8 IsFetRampTime;
+ UINT16 FuseDownloadDelayUs;
+} PMC_FIVR_SOC_CONFIG;
+
+#endif
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Pmc/Library/PeiDxeSmmPmcLib/PeiDxeSmmPmcLib.inf b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Pmc/Library/PeiDxeSmmPmcLib/PeiDxeSmmPmcLib.inf
new file mode 100644
index 0000000000..e9784ceb9c
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Pmc/Library/PeiDxeSmmPmcLib/PeiDxeSmmPmcLib.inf
@@ -0,0 +1,38 @@
+## @file
+# PEI/DXE/SMM PCH PMC Lib.
+#
+# All function in this library is available for PEI, DXE, and SMM,
+# But do not support UEFI RUNTIME environment call.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+[Defines]
+ INF_VERSION = 0x00010017
+ BASE_NAME = PeiDxeSmmPmcLib
+ FILE_GUID = 9D60C364-5086-41E3-BC9D-C62AB7233DBF
+ VERSION_STRING = 1.0
+ MODULE_TYPE = BASE
+ LIBRARY_CLASS = PmcLib
+
+[LibraryClasses]
+ BaseLib
+ IoLib
+ DebugLib
+ PciSegmentLib
+ PchCycleDecodingLib
+ PchPcrLib
+ PchInfoLib
+ PmcPrivateLib
+ BaseMemoryLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ AlderlakeSiliconPkg/SiPkg.dec
+
+[Pcd]
+ gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress
+
+[Sources]
+ PmcLib.c
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Pmc/Library/PeiDxeSmmPmcLib/PmcLib.c b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Pmc/Library/PeiDxeSmmPmcLib/PmcLib.c
new file mode 100644
index 0000000000..91e741a294
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Pmc/Library/PeiDxeSmmPmcLib/PmcLib.c
@@ -0,0 +1,50 @@
+/** @file
+ PCH PMC Library.
+ All function in this library is available for PEI, DXE, and SMM,
+ But do not support UEFI RUNTIME environment call.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <Base.h>
+#include <Uefi/UefiBaseType.h>
+#include <Library/IoLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/PciSegmentLib.h>
+#include <Library/PchCycleDecodingLib.h>
+#include <Library/PmcLib.h>
+#include <Library/PchPcrLib.h>
+#include <Library/PchInfoLib.h>
+#include <Library/PmcPrivateLib.h>
+#include <PchReservedResources.h>
+#include <Register/PmcRegs.h>
+#include <Register/PchRegs.h>
+
+/**
+ Get PCH ACPI base address.
+
+ @retval Address Address of PWRM base address.
+**/
+UINT16
+PmcGetAcpiBase (
+ VOID
+ )
+{
+ return PcdGet16 (PcdAcpiBaseAddress);
+}
+
+/**
+ Get PCH PWRM base address.
+
+ @retval Address Address of PWRM base address.
+**/
+UINT32
+PmcGetPwrmBase (
+ VOID
+ )
+{
+ return PCH_PWRM_BASE_ADDRESS;
+}
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Pmc/LibraryPrivate/PeiDxeSmmPmcPrivateLib/PeiDxeSmmPmcPrivateLib.inf b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Pmc/LibraryPrivate/PeiDxeSmmPmcPrivateLib/PeiDxeSmmPmcPrivateLib.inf
new file mode 100644
index 0000000000..e6693f767d
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Pmc/LibraryPrivate/PeiDxeSmmPmcPrivateLib/PeiDxeSmmPmcPrivateLib.inf
@@ -0,0 +1,43 @@
+## @file
+# PEI/DXE/SMM PCH PMC Private Lib.
+#
+# All function in this library is available for PEI, DXE, and SMM,
+# But do not support UEFI RUNTIME environment call.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+
+[Defines]
+INF_VERSION = 0x00010017
+BASE_NAME = PeiDxeSmmPmcPrivateLib
+FILE_GUID = EB69B12B-6D4C-4B12-BB31-66CBCC4C1DC7
+VERSION_STRING = 1.0
+MODULE_TYPE = BASE
+LIBRARY_CLASS = PmcPrivateLib
+
+
+[LibraryClasses]
+BaseLib
+IoLib
+DebugLib
+TimerLib
+PciSegmentLib
+PmcLib
+BaseMemoryLib
+PchPciBdfLib
+
+[Packages]
+MdePkg/MdePkg.dec
+AlderlakeSiliconPkg/SiPkg.dec
+
+
+[Pcd]
+gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress
+
+[FixedPcd]
+
+[Sources]
+PmcPrivateLib.c
+
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Pmc/LibraryPrivate/PeiDxeSmmPmcPrivateLib/PmcPrivateLib.c b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Pmc/LibraryPrivate/PeiDxeSmmPmcPrivateLib/PmcPrivateLib.c
new file mode 100644
index 0000000000..b720305d15
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Pmc/LibraryPrivate/PeiDxeSmmPmcPrivateLib/PmcPrivateLib.c
@@ -0,0 +1,86 @@
+/** @file
+ PCH private PMC Library for all PCH generations.
+ All function in this library is available for PEI, DXE, and SMM,
+ But do not support UEFI RUNTIME environment call.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <Base.h>
+#include <Uefi/UefiBaseType.h>
+#include <Library/IoLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/PmcLib.h>
+#include <Library/PciSegmentLib.h>
+#include <Library/TimerLib.h>
+#include <Library/PmcPrivateLib.h>
+#include <PchReservedResources.h>
+#include <Register/PchRegs.h>
+#include <Register/PmcRegs.h>
+#include <IndustryStandard/Pci30.h>
+#include <Library/PchPciBdfLib.h>
+
+
+/**
+ This function sets SW SMI Rate.
+
+ @param[in] SwSmiRate Refer to PMC_SWSMI_RATE for possible values
+**/
+VOID
+PmcSetSwSmiRate (
+ IN PMC_SWSMI_RATE SwSmiRate
+ )
+{
+ UINT32 PchPwrmBase;
+ STATIC UINT8 SwSmiRateRegVal[4] = {
+ V_PMC_PWRM_GEN_PMCON_A_SWSMI_RTSL_1_5MS,
+ V_PMC_PWRM_GEN_PMCON_A_SWSMI_RTSL_16MS,
+ V_PMC_PWRM_GEN_PMCON_A_SWSMI_RTSL_32MS,
+ V_PMC_PWRM_GEN_PMCON_A_SWSMI_RTSL_64MS
+ };
+
+ ASSERT (SwSmiRate <= PmcSwSmiRate64ms);
+
+ PchPwrmBase = PmcGetPwrmBase ();
+
+ //
+ // SWSMI_RATE_SEL BIT (PWRMBASE offset 1020h[7:6]) bits are in RTC well
+ //
+ MmioAndThenOr8 (
+ PchPwrmBase + R_PMC_PWRM_GEN_PMCON_A,
+ (UINT8)~B_PMC_PWRM_GEN_PMCON_A_SWSMI_RTSL,
+ SwSmiRateRegVal[SwSmiRate]
+ );
+}
+
+/**
+ This function sets Periodic SMI Rate.
+
+ @param[in] PeriodicSmiRate Refer to PMC_PERIODIC_SMI_RATE for possible values
+**/
+VOID
+PmcSetPeriodicSmiRate (
+ IN PMC_PERIODIC_SMI_RATE PeriodicSmiRate
+ )
+{
+ UINT32 PchPwrmBase;
+ STATIC UINT8 PeriodicSmiRateRegVal[4] = {
+ V_PMC_PWRM_GEN_PMCON_A_PER_SMI_8S,
+ V_PMC_PWRM_GEN_PMCON_A_PER_SMI_16S,
+ V_PMC_PWRM_GEN_PMCON_A_PER_SMI_32S,
+ V_PMC_PWRM_GEN_PMCON_A_PER_SMI_64S
+ };
+
+ ASSERT (PeriodicSmiRate <= PmcPeriodicSmiRate64s);
+
+ PchPwrmBase = PmcGetPwrmBase ();
+
+ MmioAndThenOr8 (
+ PchPwrmBase + R_PMC_PWRM_GEN_PMCON_A,
+ (UINT8)~B_PMC_PWRM_GEN_PMCON_A_PER_SMI_SEL,
+ PeriodicSmiRateRegVal[PeriodicSmiRate]
+ );
+}
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/IncludePrivate/Library/SpiCommonLib.h b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/IncludePrivate/Library/SpiCommonLib.h
new file mode 100644
index 0000000000..e13718c9e9
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/IncludePrivate/Library/SpiCommonLib.h
@@ -0,0 +1,376 @@
+/** @file
+ Header file for the PCH SPI Common Driver.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _SPI_COMMON_LIB_H_
+#define _SPI_COMMON_LIB_H_
+
+#include <Protocol/Spi.h>
+
+//
+// Maximum time allowed while waiting the SPI cycle to complete
+// Wait Time = 6 seconds = 6000000 microseconds
+// Wait Period = 10 microseconds
+//
+#define SPI_WAIT_TIME 6000000 ///< Wait Time = 6 seconds = 6000000 microseconds
+
+#define SPI_WAIT_PERIOD 10 ///< Wait Period = 10 microseconds
+
+///
+/// Flash cycle Type
+///
+typedef enum {
+ FlashCycleRead,
+ FlashCycleWrite,
+ FlashCycleErase,
+ FlashCycleReadSfdp,
+ FlashCycleReadJedecId,
+ FlashCycleWriteStatus,
+ FlashCycleReadStatus,
+ FlashCycleMax
+} FLASH_CYCLE_TYPE;
+
+///
+/// Flash Component Number
+///
+typedef enum {
+ FlashComponent0,
+ FlashComponent1,
+ FlashComponentMax
+} FLASH_COMPONENT_NUM;
+
+///
+/// Private data structure definitions for the driver
+///
+#define PCH_SPI_PRIVATE_DATA_SIGNATURE SIGNATURE_32 ('P', 'S', 'P', 'I')
+
+typedef struct {
+ UINT32 Signature;
+ EFI_HANDLE Handle;
+ PCH_SPI_PROTOCOL SpiProtocol;
+ UINT16 PchAcpiBase;
+ UINT64 PchSpiBase;
+ UINT8 ReadPermission;
+ UINT8 WritePermission;
+ UINT32 SfdpVscc0Value;
+ UINT32 SfdpVscc1Value;
+ UINT16 PchStrapBaseAddr;
+ UINT16 PchStrapSize;
+ UINT16 CpuStrapBaseAddr;
+ UINT16 CpuStrapSize;
+ UINT8 NumberOfComponents;
+ UINT32 Component1StartAddr;
+ UINT32 TotalFlashSize;
+} SPI_INSTANCE;
+
+#define SPI_INSTANCE_FROM_SPIPROTOCOL(a) CR (a, SPI_INSTANCE, SpiProtocol, PCH_SPI_PRIVATE_DATA_SIGNATURE)
+
+//
+// Function prototypes used by the SPI protocol.
+//
+
+/**
+ Initialize an SPI protocol instance.
+
+ @param[in] SpiInstance Pointer to SpiInstance to initialize
+
+ @retval EFI_SUCCESS The protocol instance was properly initialized
+ @exception EFI_UNSUPPORTED The PCH is not supported by this module
+**/
+EFI_STATUS
+SpiProtocolConstructor (
+ IN SPI_INSTANCE *SpiInstance
+ );
+
+/**
+ This function is a hook for Spi to disable BIOS Write Protect
+
+ @retval EFI_SUCCESS The protocol instance was properly initialized
+ @retval EFI_ACCESS_DENIED The BIOS Region can only be updated in SMM phase
+
+**/
+EFI_STATUS
+EFIAPI
+DisableBiosWriteProtect (
+ VOID
+ );
+
+/**
+ This function is a hook for Spi to enable BIOS Write Protect
+
+
+**/
+VOID
+EFIAPI
+EnableBiosWriteProtect (
+ VOID
+ );
+
+/**
+ Acquire pch spi mmio address.
+
+ @param[in] SpiInstance Pointer to SpiInstance to initialize
+
+ @retval PchSpiBar0 return SPI MMIO address
+**/
+UINTN
+AcquireSpiBar0 (
+ IN SPI_INSTANCE *SpiInstance
+ );
+
+/**
+ Release pch spi mmio address.
+
+ @param[in] SpiInstance Pointer to SpiInstance to initialize
+
+ @retval None
+**/
+VOID
+ReleaseSpiBar0 (
+ IN SPI_INSTANCE *SpiInstance
+ );
+
+/**
+ Check if it's granted to do flash write.
+
+ @retval TRUE It's secure to do flash write.
+ @retval FALSE It's not secure to do flash write.
+**/
+BOOLEAN
+IsSpiFlashWriteGranted (
+ VOID
+ );
+
+/**
+ Check if a save and restore of the SPI controller state is necessary
+
+ @retval TRUE It's necessary to save and restore SPI controller state
+ @retval FALSE It's not necessary to save and restore SPI controller state
+**/
+BOOLEAN
+IsSpiControllerSaveRestoreEnabled (
+ VOID
+ );
+
+/**
+ Read data from the flash part.
+
+ @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
+ @param[in] FlashRegionType The Flash Region type for flash cycle which is listed in the Descriptor.
+ @param[in] Address The Flash Linear Address must fall within a region for which BIOS has access permissions.
+ @param[in] ByteCount Number of bytes in the data portion of the SPI cycle.
+ @param[out] Buffer The Pointer to caller-allocated buffer containing the dada received.
+ It is the caller's responsibility to make sure Buffer is large enough for the total number of bytes read.
+
+ @retval EFI_SUCCESS Command succeed.
+ @retval EFI_INVALID_PARAMETER The parameters specified are not valid.
+ @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
+**/
+EFI_STATUS
+EFIAPI
+SpiProtocolFlashRead (
+ IN PCH_SPI_PROTOCOL *This,
+ IN FLASH_REGION_TYPE FlashRegionType,
+ IN UINT32 Address,
+ IN UINT32 ByteCount,
+ OUT UINT8 *Buffer
+ );
+
+/**
+ Write data to the flash part.
+
+ @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
+ @param[in] FlashRegionType The Flash Region type for flash cycle which is listed in the Descriptor.
+ @param[in] Address The Flash Linear Address must fall within a region for which BIOS has access permissions.
+ @param[in] ByteCount Number of bytes in the data portion of the SPI cycle.
+ @param[in] Buffer Pointer to caller-allocated buffer containing the data sent during the SPI cycle.
+
+ @retval EFI_SUCCESS Command succeed.
+ @retval EFI_INVALID_PARAMETER The parameters specified are not valid.
+ @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
+**/
+EFI_STATUS
+EFIAPI
+SpiProtocolFlashWrite (
+ IN PCH_SPI_PROTOCOL *This,
+ IN FLASH_REGION_TYPE FlashRegionType,
+ IN UINT32 Address,
+ IN UINT32 ByteCount,
+ IN UINT8 *Buffer
+ );
+
+/**
+ Erase some area on the flash part.
+
+ @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
+ @param[in] FlashRegionType The Flash Region type for flash cycle which is listed in the Descriptor.
+ @param[in] Address The Flash Linear Address must fall within a region for which BIOS has access permissions.
+ @param[in] ByteCount Number of bytes in the data portion of the SPI cycle.
+
+ @retval EFI_SUCCESS Command succeed.
+ @retval EFI_INVALID_PARAMETER The parameters specified are not valid.
+ @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
+**/
+EFI_STATUS
+EFIAPI
+SpiProtocolFlashErase (
+ IN PCH_SPI_PROTOCOL *This,
+ IN FLASH_REGION_TYPE FlashRegionType,
+ IN UINT32 Address,
+ IN UINT32 ByteCount
+ );
+
+/**
+ Read SFDP data from the flash part.
+
+ @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
+ @param[in] ComponentNumber The Componen Number for chip select
+ @param[in] Address The starting byte address for SFDP data read.
+ @param[in] ByteCount Number of bytes in SFDP data portion of the SPI cycle
+ @param[out] SfdpData The Pointer to caller-allocated buffer containing the SFDP data received
+ It is the caller's responsibility to make sure Buffer is large enough for the total number of bytes read
+
+ @retval EFI_SUCCESS Command succeed.
+ @retval EFI_INVALID_PARAMETER The parameters specified are not valid.
+ @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
+**/
+EFI_STATUS
+EFIAPI
+SpiProtocolFlashReadSfdp (
+ IN PCH_SPI_PROTOCOL *This,
+ IN UINT8 ComponentNumber,
+ IN UINT32 Address,
+ IN UINT32 ByteCount,
+ OUT UINT8 *SfdpData
+ );
+
+/**
+ Read Jedec Id from the flash part.
+
+ @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
+ @param[in] ComponentNumber The Componen Number for chip select
+ @param[in] ByteCount Number of bytes in JedecId data portion of the SPI cycle, the data size is 3 typically
+ @param[out] JedecId The Pointer to caller-allocated buffer containing JEDEC ID received
+ It is the caller's responsibility to make sure Buffer is large enough for the total number of bytes read.
+
+ @retval EFI_SUCCESS Command succeed.
+ @retval EFI_INVALID_PARAMETER The parameters specified are not valid.
+ @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
+**/
+EFI_STATUS
+EFIAPI
+SpiProtocolFlashReadJedecId (
+ IN PCH_SPI_PROTOCOL *This,
+ IN UINT8 ComponentNumber,
+ IN UINT32 ByteCount,
+ OUT UINT8 *JedecId
+ );
+
+/**
+ Write the status register in the flash part.
+
+ @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
+ @param[in] ByteCount Number of bytes in Status data portion of the SPI cycle, the data size is 1 typically
+ @param[in] StatusValue The Pointer to caller-allocated buffer containing the value of Status register writing
+
+ @retval EFI_SUCCESS Command succeed.
+ @retval EFI_INVALID_PARAMETER The parameters specified are not valid.
+ @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
+**/
+EFI_STATUS
+EFIAPI
+SpiProtocolFlashWriteStatus (
+ IN PCH_SPI_PROTOCOL *This,
+ IN UINT32 ByteCount,
+ IN UINT8 *StatusValue
+ );
+
+/**
+ Read status register in the flash part.
+
+ @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
+ @param[in] ByteCount Number of bytes in Status data portion of the SPI cycle, the data size is 1 typically
+ @param[out] StatusValue The Pointer to caller-allocated buffer containing the value of Status register received.
+
+ @retval EFI_SUCCESS Command succeed.
+ @retval EFI_INVALID_PARAMETER The parameters specified are not valid.
+ @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
+**/
+EFI_STATUS
+EFIAPI
+SpiProtocolFlashReadStatus (
+ IN PCH_SPI_PROTOCOL *This,
+ IN UINT32 ByteCount,
+ OUT UINT8 *StatusValue
+ );
+
+/**
+ Get the SPI region base and size, based on the enum type
+
+ @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
+ @param[in] FlashRegionType The Flash Region type for for the base address which is listed in the Descriptor.
+ @param[out] BaseAddress The Flash Linear Address for the Region 'n' Base
+ @param[out] RegionSize The size for the Region 'n'
+
+ @retval EFI_SUCCESS Read success
+ @retval EFI_INVALID_PARAMETER Invalid region type given
+ @retval EFI_DEVICE_ERROR The region is not used
+**/
+EFI_STATUS
+EFIAPI
+SpiProtocolGetRegionAddress (
+ IN PCH_SPI_PROTOCOL *This,
+ IN FLASH_REGION_TYPE FlashRegionType,
+ OUT UINT32 *BaseAddress,
+ OUT UINT32 *RegionSize
+ );
+
+/**
+ Read PCH Soft Strap Values
+
+ @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
+ @param[in] SoftStrapAddr PCH Soft Strap address offset from FPSBA.
+ @param[in] ByteCount Number of bytes in SoftStrap data portion of the SPI cycle
+ @param[out] SoftStrapValue The Pointer to caller-allocated buffer containing PCH Soft Strap Value.
+ If the value of ByteCount is 0, the data type of SoftStrapValue should be UINT16 and SoftStrapValue will be PCH Soft Strap Length
+ It is the caller's responsibility to make sure Buffer is large enough for the total number of bytes read.
+
+ @retval EFI_SUCCESS Command succeed.
+ @retval EFI_INVALID_PARAMETER The parameters specified are not valid.
+ @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
+**/
+EFI_STATUS
+EFIAPI
+SpiProtocolReadPchSoftStrap (
+ IN PCH_SPI_PROTOCOL *This,
+ IN UINT32 SoftStrapAddr,
+ IN UINT32 ByteCount,
+ OUT VOID *SoftStrapValue
+ );
+
+/**
+ Read CPU Soft Strap Values
+
+ @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
+ @param[in] SoftStrapAddr CPU Soft Strap address offset from FCPUSBA.
+ @param[in] ByteCount Number of bytes in SoftStrap data portion of the SPI cycle.
+ @param[out] SoftStrapValue The Pointer to caller-allocated buffer containing CPU Soft Strap Value.
+ If the value of ByteCount is 0, the data type of SoftStrapValue should be UINT16 and SoftStrapValue will be PCH Soft Strap Length
+ It is the caller's responsibility to make sure Buffer is large enough for the total number of bytes read.
+
+ @retval EFI_SUCCESS Command succeed.
+ @retval EFI_INVALID_PARAMETER The parameters specified are not valid.
+ @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
+**/
+EFI_STATUS
+EFIAPI
+SpiProtocolReadCpuSoftStrap (
+ IN PCH_SPI_PROTOCOL *This,
+ IN UINT32 SoftStrapAddr,
+ IN UINT32 ByteCount,
+ OUT VOID *SoftStrapValue
+ );
+
+#endif
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/IncludePrivate/Register/SpiRegs.h b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/IncludePrivate/Register/SpiRegs.h
new file mode 100644
index 0000000000..5cb4791142
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/IncludePrivate/Register/SpiRegs.h
@@ -0,0 +1,116 @@
+/** @file
+ Register names for PCH SPI device.
+
+ Conventions:
+
+ - Register definition format:
+ Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_RegisterName
+ - Prefix:
+ Definitions beginning with "R_" are registers
+ Definitions beginning with "B_" are bits within registers
+ Definitions beginning with "V_" are meaningful values within the bits
+ Definitions beginning with "S_" are register size
+ Definitions beginning with "N_" are the bit position
+ - [GenerationName]:
+ Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc.).
+ Register name without GenerationName applies to all generations.
+ - [ComponentName]:
+ This field indicates the component name that the register belongs to (e.g. PCH, SA etc.)
+ Register name without ComponentName applies to all components.
+ Register that is specific to -H denoted by "_PCH_H_" in component name.
+ Register that is specific to -LP denoted by "_PCH_LP_" in component name.
+ - SubsystemName:
+ This field indicates the subsystem name of the component that the register belongs to
+ (e.g. PCIE, USB, SATA, GPIO, PMC etc.).
+ - RegisterSpace:
+ MEM - MMIO space register of subsystem.
+ IO - IO space register of subsystem.
+ PCR - Private configuration register of subsystem.
+ CFG - PCI configuration space register of subsystem.
+ - RegisterName:
+ Full register name.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _SPI_REGS_H_
+#define _SPI_REGS_H_
+
+//
+// SPI Registers
+//
+#define R_SPI_CFG_BAR0 0x10
+#define B_SPI_CFG_BAR0_MASK 0x0FFF
+
+
+#define R_SPI_CFG_BC 0xDC
+#define S_SPI_CFG_BC 4
+#define N_SPI_CFG_BC_ASE_BWP 11
+#define B_SPI_CFG_BC_ASE_BWP BIT11
+#define N_SPI_CFG_BC_ASYNC_SS 10
+#define B_SPI_CFG_BC_ASYNC_SS BIT10
+#define N_SPI_CFG_BC_SYNC_SS 8
+#define B_SPI_CFG_BC_SYNC_SS BIT8
+#define B_SPI_CFG_BC_BILD BIT7
+#define B_SPI_CFG_BC_EISS BIT5 ///< Enable InSMM.STS
+#define B_SPI_CFG_BC_SRC (BIT3 | BIT2)
+#define N_SPI_CFG_BC_SRC 2
+#define V_SPI_CFG_BC_SRC_PREF_DIS_CACHE_DIS 0x01 ///< No prefetching and no caching
+#define N_SPI_CFG_BC_BLE 1
+#define B_SPI_CFG_BC_WPD BIT0 ///< Write Protect Disable
+
+//
+// BIOS Flash Program Registers (based on SPI_BAR0)
+//
+#define R_SPI_MEM_HSFSC 0x04 ///< Hardware Sequencing Flash Status and Control Register(32bits)
+#define B_SPI_MEM_HSFSC_FDBC_MASK 0x3F000000 ///< Flash Data Byte Count ( <= 64), Count = (Value in this field) + 1.
+#define N_SPI_MEM_HSFSC_FDBC 24
+#define B_SPI_MEM_HSFSC_CYCLE_MASK 0x001E0000 ///< Flash Cycle.
+#define N_SPI_MEM_HSFSC_CYCLE 17
+#define V_SPI_MEM_HSFSC_CYCLE_READ 0 ///< Flash Cycle Read
+#define V_SPI_MEM_HSFSC_CYCLE_WRITE 2 ///< Flash Cycle Write
+#define V_SPI_MEM_HSFSC_CYCLE_4K_ERASE 3 ///< Flash Cycle 4K Block Erase
+#define V_SPI_MEM_HSFSC_CYCLE_64K_ERASE 4 ///< Flash Cycle 64K Sector Erase
+#define V_SPI_MEM_HSFSC_CYCLE_READ_SFDP 5 ///< Flash Cycle Read SFDP
+#define V_SPI_MEM_HSFSC_CYCLE_READ_JEDEC_ID 6 ///< Flash Cycle Read JEDEC ID
+#define V_SPI_MEM_HSFSC_CYCLE_WRITE_STATUS 7 ///< Flash Cycle Write Status
+#define V_SPI_MEM_HSFSC_CYCLE_READ_STATUS 8 ///< Flash Cycle Read Status
+#define B_SPI_MEM_HSFSC_CYCLE_FGO BIT16 ///< Flash Cycle Go.
+#define B_SPI_MEM_HSFSC_FDV BIT14 ///< Flash Descriptor Valid, once valid software can use hareware sequencing regs
+#define B_SPI_MEM_HSFSC_WRSDIS BIT11 ///< Write Status Disable
+#define B_SPI_MEM_HSFSC_SAF_CE BIT8 ///< SAF ctype error
+#define B_SPI_MEM_HSFSC_SAF_LE BIT6 ///< SAF link error
+#define B_SPI_MEM_HSFSC_SCIP BIT5 ///< SPI cycle in progress
+#define B_SPI_MEM_HSFSC_SAF_DLE BIT4 ///< SAF Data length error
+#define B_SPI_MEM_HSFSC_SAF_ERROR BIT3 ///< SAF Error
+#define B_SPI_MEM_HSFSC_AEL BIT2 ///< Access Error Log
+#define B_SPI_MEM_HSFSC_FCERR BIT1 ///< Flash Cycle Error
+#define B_SPI_MEM_HSFSC_FDONE BIT0 ///< Flash Cycle Done
+#define R_SPI_MEM_FADDR 0x08 ///< SPI Flash Address
+#define B_SPI_MEM_FADDR_MASK 0x07FFFFFF ///< SPI Flash Address Mask (0~26bit)
+#define R_SPI_MEM_FDATA00 0x10 ///< SPI Data 00 (32 bits)
+#define R_SPI_MEM_FRAP 0x50 ///< Flash Region Access Permissions Register
+#define B_SPI_MEM_FRAP_BRWA_MASK 0x0000FF00 ///< BIOS Region Write Access MASK, Region0~7 - 0: Flash Descriptor; 1: BIOS; 2: ME; 3: GbE; 4: PlatformData
+#define N_SPI_MEM_FRAP_BRWA 8 ///< BIOS Region Write Access bit position
+#define B_SPI_MEM_FRAP_BRRA_MASK 0x000000FF ///< BIOS Region Read Access MASK, Region0~7 - 0: Flash Descriptor; 1: BIOS; 2: ME; 3: GbE; 4: PlatformData
+#define R_SPI_MEM_FREG0_FLASHD 0x54 ///< Flash Region 0(Flash Descriptor)(32bits)
+#define S_SPI_MEM_FREGX 4 ///< Size of Flash Region register
+#define B_SPI_MEM_FREGX_LIMIT_MASK 0x7FFF0000 ///< Flash Region Limit [30:16] represents [26:12], [11:0] are assumed to be FFFh
+#define N_SPI_MEM_FREGX_LIMIT 16 ///< Region limit bit position
+#define N_SPI_MEM_FREGX_LIMIT_REPR 12 ///< Region limit bit represents position
+#define B_SPI_MEM_FREGX_BASE_MASK 0x00007FFF ///< Flash Region Base, [14:0] represents [26:12]
+#define N_SPI_MEM_FREGX_BASE 0 ///< Region base bit position
+#define N_SPI_MEM_FREGX_BASE_REPR 12 ///< Region base bit represents position
+#define R_SPI_MEM_FDOC 0xB4 ///< Flash Descriptor Observability Control Register(32 bits)
+#define B_SPI_MEM_FDOC_FDSS_MASK (BIT14 | BIT13 | BIT12) ///< Flash Descritor Section Select
+#define V_SPI_MEM_FDOC_FDSS_FSDM 0x0000 ///< Flash Signature and Descriptor Map
+#define V_SPI_MEM_FDOC_FDSS_COMP 0x1000 ///< Component
+
+#define B_SPI_MEM_FDOC_FDSI_MASK 0x0FFC ///< Flash Descriptor Section Index
+#define R_SPI_MEM_FDOD 0xB8 ///< Flash Descriptor Observability Data Register(32 bits)
+#define R_SPI_MEM_SFDP0_VSCC0 0xC4 ///< Vendor Specific Component Capabilities Register(32 bits)
+
+#define B_SPI_MEM_SFDPX_VSCCX_EO_64K BIT29 ///< 64k Erase valid (EO_64k_valid)
+#define R_SPI_MEM_SFDP1_VSCC1 0xC8 ///< Vendor Specific Component Capabilities Register(32 bits)
+
+#endif
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/Library/PeiSpiLib/PchSpi.c b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/Library/PeiSpiLib/PchSpi.c
new file mode 100644
index 0000000000..aaf4e1790f
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/Library/PeiSpiLib/PchSpi.c
@@ -0,0 +1,209 @@
+/** @file
+ PCH SPI PEI Library implements the SPI Host Controller Compatibility Interface.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#include <Library/IoLib.h>
+#include <Library/DebugLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/PeiServicesLib.h>
+#include <Library/PciSegmentLib.h>
+#include <Ppi/Spi.h>
+#include <Library/SpiCommonLib.h>
+#include <PchReservedResources.h>
+#include <IndustryStandard/Pci30.h>
+#include <Register/PchRegs.h>
+#include <Register/PchRegsLpc.h>
+#include <Register/SpiRegs.h>
+#include <Library/PchPciBdfLib.h>
+
+typedef struct {
+ EFI_PEI_PPI_DESCRIPTOR PpiDescriptor;
+ SPI_INSTANCE SpiInstance;
+} PEI_SPI_INSTANCE;
+
+/**
+ PCI Enumeratuion is not done till later in DXE
+ Initlialize SPI BAR0 to a default value till enumeration is done
+ also enable memory space decoding for SPI
+
+**/
+VOID
+InitSpiBar0 (
+ VOID
+ )
+{
+ UINT64 PchSpiBase;
+ PchSpiBase = SpiPciCfgBase ();
+ PciSegmentWrite32 (PchSpiBase + R_SPI_CFG_BAR0, PCH_SPI_BASE_ADDRESS);
+ PciSegmentOr32 (PchSpiBase + PCI_COMMAND_OFFSET, EFI_PCI_COMMAND_MEMORY_SPACE);
+}
+
+/**
+ This function Initial SPI services
+
+ @retval EFI_STATUS Results of the installation of the SPI services
+**/
+EFI_STATUS
+EFIAPI
+SpiServiceInit (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+ PEI_SPI_INSTANCE *PeiSpiInstance;
+ SPI_INSTANCE *SpiInstance;
+ PCH_SPI_PPI *SpiPpi;
+
+ Status = PeiServicesLocatePpi (
+ &gPchSpiPpiGuid,
+ 0,
+ NULL,
+ (VOID **)&SpiPpi
+ );
+
+ if (Status != EFI_SUCCESS) {
+ DEBUG ((DEBUG_INFO, "SpiServiceInit() Start\n"));
+
+ //
+ // PCI Enumeratuion is not done till later in DXE
+ // Initlialize SPI BAR0 to a default value till enumeration is done
+ // also enable memory space decoding for SPI
+ //
+ InitSpiBar0 ();
+
+ PeiSpiInstance = (PEI_SPI_INSTANCE *) AllocateZeroPool (sizeof (PEI_SPI_INSTANCE));
+ if (NULL == PeiSpiInstance) {
+ return EFI_OUT_OF_RESOURCES;
+ }
+
+ SpiInstance = &(PeiSpiInstance->SpiInstance);
+ SpiProtocolConstructor (SpiInstance);
+
+ PeiSpiInstance->PpiDescriptor.Flags = EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST;
+ PeiSpiInstance->PpiDescriptor.Guid = &gPchSpiPpiGuid;
+ PeiSpiInstance->PpiDescriptor.Ppi = &(SpiInstance->SpiProtocol);
+
+ ///
+ /// Install the SPI PPI
+ ///
+ DEBUG ((DEBUG_INFO, "SPI PPI Installed\n"));
+ Status = PeiServicesInstallPpi (&PeiSpiInstance->PpiDescriptor);
+ ASSERT_EFI_ERROR (Status);
+
+ DEBUG ((DEBUG_INFO, "SpiServiceInit() End\n"));
+ }
+ else {
+ DEBUG ((DEBUG_INFO, "SPI PPI already installed\n"));
+ }
+ return Status;
+}
+
+/**
+ Acquire pch spi mmio address.
+
+ @param[in] SpiInstance Pointer to SpiInstance to initialize
+
+ @retval PchSpiBar0 return SPI MMIO address
+**/
+UINTN
+AcquireSpiBar0 (
+ IN SPI_INSTANCE *SpiInstance
+ )
+{
+ return PciSegmentRead32 (SpiInstance->PchSpiBase + R_SPI_CFG_BAR0) & ~(B_SPI_CFG_BAR0_MASK);
+}
+
+/**
+ Release pch spi mmio address. Do nothing.
+
+ @param[in] SpiInstance Pointer to SpiInstance to initialize
+
+ @retval None
+**/
+VOID
+ReleaseSpiBar0 (
+ IN SPI_INSTANCE *SpiInstance
+ )
+{
+}
+
+/**
+ This function is a hook for Spi to disable BIOS Write Protect
+
+ @retval EFI_SUCCESS The protocol instance was properly initialized
+ @retval EFI_ACCESS_DENIED The BIOS Region can only be updated in SMM phase
+
+**/
+EFI_STATUS
+EFIAPI
+DisableBiosWriteProtect (
+ VOID
+ )
+{
+ UINT64 SpiBaseAddress;
+
+ SpiBaseAddress = SpiPciCfgBase ();
+ if ((PciSegmentRead8 (SpiBaseAddress + R_SPI_CFG_BC) & B_SPI_CFG_BC_EISS) != 0) {
+ return EFI_ACCESS_DENIED;
+ }
+ ///
+ /// Enable the access to the BIOS space for both read and write cycles
+ ///
+ PciSegmentOr8 (
+ SpiBaseAddress + R_SPI_CFG_BC,
+ B_SPI_CFG_BC_WPD
+ );
+
+ return EFI_SUCCESS;
+}
+
+/**
+ This function is a hook for Spi to enable BIOS Write Protect
+**/
+VOID
+EFIAPI
+EnableBiosWriteProtect (
+ VOID
+ )
+{
+ UINT64 SpiBaseAddress;
+
+ SpiBaseAddress = SpiPciCfgBase ();
+ ///
+ /// Disable the access to the BIOS space for write cycles
+ ///
+ PciSegmentAnd8 (
+ SpiBaseAddress + R_SPI_CFG_BC,
+ (UINT8) (~B_SPI_CFG_BC_WPD)
+ );
+}
+
+/**
+ Check if it's granted to do flash write.
+
+ @retval TRUE It's secure to do flash write.
+ @retval FALSE It's not secure to do flash write.
+**/
+BOOLEAN
+IsSpiFlashWriteGranted (
+ VOID
+ )
+{
+ return TRUE;
+}
+
+/**
+ Check if a save and restore of the SPI controller state is necessary
+
+ @retval TRUE It's necessary to save and restore SPI controller state
+ @retval FALSE It's not necessary to save and restore SPI controller state
+**/
+BOOLEAN
+IsSpiControllerSaveRestoreEnabled (
+ VOID
+ )
+{
+ return FALSE;
+}
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/Library/PeiSpiLib/PeiSpiLib.inf b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/Library/PeiSpiLib/PeiSpiLib.inf
new file mode 100644
index 0000000000..c3bf6d02a1
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/Library/PeiSpiLib/PeiSpiLib.inf
@@ -0,0 +1,41 @@
+## @file
+# Component description file for PCH Reset Lib Pei Phase
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+[Defines]
+INF_VERSION = 0x00010017
+BASE_NAME = PeiSpiLib
+FILE_GUID = 4998447D-7948-448F-AB75-96E24E18FF23
+VERSION_STRING = 1.0
+MODULE_TYPE = PEIM
+LIBRARY_CLASS = SpiLib
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = IA32 X64 IPF
+#
+
+[LibraryClasses]
+DebugLib
+PeiServicesLib
+PeiServicesTablePointerLib
+MemoryAllocationLib
+PciSegmentLib
+SpiCommonLib
+PchPciBdfLib
+
+[Packages]
+MdePkg/MdePkg.dec
+AlderlakeSiliconPkg/SiPkg.dec
+
+
+[Sources]
+PchSpi.c
+
+
+[Ppis]
+gPchSpiPpiGuid ## PRODUCES
+
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/LibraryPrivate/BaseSpiCommonLib/BaseSpiCommonLib.inf b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/LibraryPrivate/BaseSpiCommonLib/BaseSpiCommonLib.inf
new file mode 100644
index 0000000000..25ab91940c
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/LibraryPrivate/BaseSpiCommonLib/BaseSpiCommonLib.inf
@@ -0,0 +1,29 @@
+## @file
+# Component description file for the PchSpiCommonLib
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = BaseSpiCommonLib
+ FILE_GUID = A37CB67E-7D85-45B3-B07E-BF65BDB603E8
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = SpiCommonLib
+
+[Sources]
+ SpiCommon.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ AlderlakeSiliconPkg/SiPkg.dec
+
+[LibraryClasses]
+ IoLib
+ DebugLib
+ PmcLib
+ PchPciBdfLib
+
+[Pcd]
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/LibraryPrivate/BaseSpiCommonLib/SpiCommon.c b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/LibraryPrivate/BaseSpiCommonLib/SpiCommon.c
new file mode 100644
index 0000000000..ab51521f14
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/LibraryPrivate/BaseSpiCommonLib/SpiCommon.c
@@ -0,0 +1,1127 @@
+/** @file
+ PCH SPI Common Driver implements the SPI Host Controller Compatibility Interface.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#include <Uefi/UefiBaseType.h>
+#include <Library/BaseLib.h>
+#include <Library/IoLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <IndustryStandard/Pci30.h>
+#include <Library/PmcLib.h>
+#include <Library/PciSegmentLib.h>
+#include <Protocol/Spi.h>
+#include <Library/SpiCommonLib.h>
+#include <Register/PchRegs.h>
+#include <Register/SpiRegs.h>
+#include <Register/FlashRegs.h>
+#include <Register/PmcRegs.h>
+#include <Library/PchPciBdfLib.h>
+
+#define DEFAULT_CPU_STRAP_BASE_OFFSET 0x300 // Default CPU Straps base offset
+#define B_SPI_MEM_HSFSC_SAVE_MASK (B_SPI_MEM_HSFSC_FDBC_MASK | B_SPI_MEM_HSFSC_CYCLE_MASK)
+
+/**
+ Initialize an SPI protocol instance.
+
+ @param[in] SpiInstance Pointer to SpiInstance to initialize
+
+ @retval EFI_SUCCESS The protocol instance was properly initialized
+ @exception EFI_UNSUPPORTED The PCH is not supported by this module
+**/
+EFI_STATUS
+SpiProtocolConstructor (
+ IN SPI_INSTANCE *SpiInstance
+ )
+{
+ UINTN PchSpiBar0;
+ UINT32 Data32;
+ UINT16 Mdtba;
+ EFI_STATUS Status;
+
+ //
+ // Initialize the SPI protocol instance
+ //
+ SpiInstance->Signature = PCH_SPI_PRIVATE_DATA_SIGNATURE;
+ SpiInstance->Handle = NULL;
+ SpiInstance->SpiProtocol.Revision = PCH_SPI_SERVICES_REVISION;
+ SpiInstance->SpiProtocol.FlashRead = SpiProtocolFlashRead;
+ SpiInstance->SpiProtocol.FlashWrite = SpiProtocolFlashWrite;
+ SpiInstance->SpiProtocol.FlashErase = SpiProtocolFlashErase;
+ SpiInstance->SpiProtocol.FlashReadSfdp = SpiProtocolFlashReadSfdp;
+ SpiInstance->SpiProtocol.FlashReadJedecId = SpiProtocolFlashReadJedecId;
+ SpiInstance->SpiProtocol.FlashWriteStatus = SpiProtocolFlashWriteStatus;
+ SpiInstance->SpiProtocol.FlashReadStatus = SpiProtocolFlashReadStatus;
+ SpiInstance->SpiProtocol.GetRegionAddress = SpiProtocolGetRegionAddress;
+ SpiInstance->SpiProtocol.ReadPchSoftStrap = SpiProtocolReadPchSoftStrap;
+ SpiInstance->SpiProtocol.ReadCpuSoftStrap = SpiProtocolReadCpuSoftStrap;
+
+ SpiInstance->PchSpiBase = SpiPciCfgBase ();
+
+ SpiInstance->PchAcpiBase = PmcGetAcpiBase ();
+ ASSERT (SpiInstance->PchAcpiBase != 0);
+
+ PchSpiBar0 = PciSegmentRead32 (SpiInstance->PchSpiBase + R_SPI_CFG_BAR0) & ~(B_SPI_CFG_BAR0_MASK);
+ if (PchSpiBar0 == 0) {
+ DEBUG ((DEBUG_ERROR, "ERROR : PchSpiBar0 is invalid!\n"));
+ ASSERT (FALSE);
+ }
+
+ if ((MmioRead32 (PchSpiBar0 + R_SPI_MEM_HSFSC) & B_SPI_MEM_HSFSC_FDV) == 0) {
+ DEBUG ((DEBUG_ERROR, "ERROR : SPI Flash Signature invalid, cannot use the Hardware Sequencing registers!\n"));
+ ASSERT (FALSE);
+ }
+
+ //
+ // Get Region 0 - 7 read Permission bits, region 8 and above are not permitted.
+ //
+ SpiInstance->ReadPermission = MmioRead8 (PchSpiBar0 + R_SPI_MEM_FRAP) & B_SPI_MEM_FRAP_BRRA_MASK;
+ DEBUG ((DEBUG_INFO, "Flash Region read Permission : %0x\n", SpiInstance->ReadPermission));
+ //
+ // Get Region 0 - 7 write Permission bits, region 8 and above are not permitted.
+ //
+ SpiInstance->WritePermission = (UINT8) ((MmioRead16 (PchSpiBar0 + R_SPI_MEM_FRAP) &
+ B_SPI_MEM_FRAP_BRWA_MASK) >> N_SPI_MEM_FRAP_BRWA);
+ DEBUG ((DEBUG_INFO, "Flash Region write Permission : %0x\n", SpiInstance->WritePermission));
+
+ SpiInstance->SfdpVscc0Value = MmioRead32 (PchSpiBar0 + R_SPI_MEM_SFDP0_VSCC0);
+ DEBUG ((DEBUG_INFO, "Component 0 SFDP VSCC value : %0x\n", SpiInstance->SfdpVscc0Value));
+ SpiInstance->SfdpVscc1Value = MmioRead32 (PchSpiBar0 + R_SPI_MEM_SFDP1_VSCC1);
+ DEBUG ((DEBUG_INFO, "Component 1 SFDP VSCC value : %0x\n", SpiInstance->SfdpVscc1Value));
+
+ //
+ // Select to Flash Map 0 Register to get the number of flash Component
+ //
+ MmioAndThenOr32 (
+ PchSpiBar0 + R_SPI_MEM_FDOC,
+ (UINT32) (~(B_SPI_MEM_FDOC_FDSS_MASK | B_SPI_MEM_FDOC_FDSI_MASK)),
+ (UINT32) (V_SPI_MEM_FDOC_FDSS_FSDM | R_FLASH_FDBAR_FLASH_MAP0)
+ );
+
+ //
+ // Copy Zero based Number Of Components
+ //
+ SpiInstance->NumberOfComponents = (UINT8) ((MmioRead16 (PchSpiBar0 + R_SPI_MEM_FDOD) & B_FLASH_FDBAR_NC) >> N_FLASH_FDBAR_NC);
+ DEBUG ((DEBUG_INFO, "Component Number : %0x\n", SpiInstance->NumberOfComponents + 1));
+
+ MmioAndThenOr32 (
+ PchSpiBar0 + R_SPI_MEM_FDOC,
+ (UINT32) (~(B_SPI_MEM_FDOC_FDSS_MASK | B_SPI_MEM_FDOC_FDSI_MASK)),
+ (UINT32) (V_SPI_MEM_FDOC_FDSS_COMP | R_FLASH_FCBA_FLCOMP)
+ );
+
+ //
+ // Copy Component 0 Density
+ //
+ Data32 = MmioRead32 (PchSpiBar0 + R_SPI_MEM_FDOD);
+ if (SpiInstance->NumberOfComponents > 0) {
+ SpiInstance->Component1StartAddr = V_FLASH_FLCOMP_COMP_512KB <<
+ (Data32 & B_FLASH_FLCOMP_COMP0_MASK);
+ DEBUG ((DEBUG_INFO, "Component 1 StartAddr : %0x\n", SpiInstance->Component1StartAddr));
+ SpiInstance->TotalFlashSize = SpiInstance->Component1StartAddr +
+ (V_FLASH_FLCOMP_COMP_512KB <<
+ ((Data32 & B_FLASH_FLCOMP_COMP1_MASK) >>
+ N_FLASH_FLCOMP_COMP1));
+ } else {
+ SpiInstance->TotalFlashSize = V_FLASH_FLCOMP_COMP_512KB <<
+ (Data32 & B_FLASH_FLCOMP_COMP0_MASK);
+ }
+ DEBUG ((DEBUG_INFO, "Total Flash Size : %0x\n", SpiInstance->TotalFlashSize));
+
+ //
+ // Select FLASH_MAP1 to get Flash PCH Strap Base Address
+ //
+ MmioAndThenOr32 (
+ (PchSpiBar0 + R_SPI_MEM_FDOC),
+ (UINT32) (~(B_SPI_MEM_FDOC_FDSS_MASK | B_SPI_MEM_FDOC_FDSI_MASK)),
+ (UINT32) (V_SPI_MEM_FDOC_FDSS_FSDM | R_FLASH_FDBAR_FLASH_MAP1)
+ );
+ //
+ // Align FPSBA with address bits for the PCH Strap portion of flash descriptor
+ //
+ Data32 = MmioRead32 (PchSpiBar0 + R_SPI_MEM_FDOD);
+ SpiInstance->PchStrapBaseAddr = (UINT16) (((Data32 & B_FLASH_FDBAR_FPSBA)
+ >> N_FLASH_FDBAR_FPSBA)
+ << N_FLASH_FDBAR_FPSBA_REPR);
+ DEBUG ((DEBUG_INFO, "PchStrapBaseAddr : %0x\n", SpiInstance->PchStrapBaseAddr));
+ ASSERT (SpiInstance->PchStrapBaseAddr != 0);
+ //
+ // PCH Strap Length, [31:24] represents number of Dwords
+ //
+ SpiInstance->PchStrapSize = (UINT16) (((Data32 & B_FLASH_FDBAR_PCHSL)
+ >> N_FLASH_FDBAR_PCHSL)
+ * sizeof (UINT32));
+ DEBUG ((DEBUG_INFO, "PchStrapSize : %0x\n", SpiInstance->PchStrapSize));
+
+ //
+ // Select FLASH_MAP2 to get Flash CPU Strap Base Address
+ //
+ MmioAndThenOr32 (
+ (PchSpiBar0 + R_SPI_MEM_FDOC),
+ (UINT32) (~(B_SPI_MEM_FDOC_FDSS_MASK | B_SPI_MEM_FDOC_FDSI_MASK)),
+ (UINT32) (V_SPI_MEM_FDOC_FDSS_FSDM | R_FLASH_FDBAR_FLASH_MAP2)
+ );
+ //
+ // Align FPSBA with address bits for the CPU Strap portion of flash descriptor
+ //
+ Data32 = MmioRead32 (PchSpiBar0 + R_SPI_MEM_FDOD);
+ //
+ // CPU Strap Length, [23:16] represents number of Dwords
+ //
+ SpiInstance->CpuStrapSize = (UINT16) (((Data32 & B_FLASH_FDBAR_CPUSL)
+ >> N_FLASH_FDBAR_CPUSL)
+ * sizeof (UINT32));
+
+ //
+ // CPU Strap Address [11:2] represent offset from MDTBA
+ //
+ SpiInstance->CpuStrapBaseAddr = (UINT16) ((Data32 & B_FLASH_FDBAR_FCPUSBA) >> N_FLASH_FDBAR_FCPUSBA);
+ ASSERT (SpiInstance->CpuStrapBaseAddr != 0);
+
+ //
+ // If CPU Strap base address is different than 0x300 need to add MDTBA value for final location
+ //
+ if (SpiInstance->CpuStrapBaseAddr != DEFAULT_CPU_STRAP_BASE_OFFSET) {
+ Status = SpiProtocolFlashRead (&(SpiInstance->SpiProtocol), FlashRegionAll, R_FLASH_UMAP1, sizeof (Data32), (UINT8 *) (&Data32));
+ ASSERT_EFI_ERROR (Status);
+ Mdtba = (UINT16)(((Data32 & B_FLASH_UMAP1_MDTBA) >> N_FLASH_UMAP1_MDTBA) << N_FLASH_UMAP1_MDTBA_REPR);
+ DEBUG ((DEBUG_INFO, "Mdtba : %0x\n", Mdtba));
+ // Add MDTBA offset for final address of CPU Straps
+ SpiInstance->CpuStrapBaseAddr += Mdtba;
+ }
+
+ DEBUG ((DEBUG_INFO, "CpuStrapBaseAddr : %0x\n", SpiInstance->CpuStrapBaseAddr));
+ DEBUG ((DEBUG_INFO, "CpuStrapSize : %0x\n", SpiInstance->CpuStrapSize));
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Delay for at least the request number of microseconds for Runtime usage.
+
+ @param[in] ABase Acpi base address
+ @param[in] Microseconds Number of microseconds to delay.
+
+**/
+VOID
+EFIAPI
+PchPmTimerStallRuntimeSafe (
+ IN UINT16 ABase,
+ IN UINTN Microseconds
+ )
+{
+ UINTN Ticks;
+ UINTN Counts;
+ UINTN CurrentTick;
+ UINTN OriginalTick;
+ UINTN RemainingTick;
+
+ if (Microseconds == 0) {
+ return;
+ }
+
+ OriginalTick = IoRead32 ((UINTN) (ABase + R_ACPI_IO_PM1_TMR)) & B_ACPI_IO_PM1_TMR_TMR_VAL;
+ CurrentTick = OriginalTick;
+
+ //
+ // The timer frequency is 3.579545 MHz, so 1 ms corresponds 3.58 clocks
+ //
+ Ticks = Microseconds * 358 / 100 + OriginalTick + 1;
+
+ //
+ // The loops needed by timer overflow
+ //
+ Counts = Ticks / V_ACPI_IO_PM1_TMR_MAX_VAL;
+
+ //
+ // Remaining clocks within one loop
+ //
+ RemainingTick = Ticks % V_ACPI_IO_PM1_TMR_MAX_VAL;
+
+ //
+ // not intend to use TMROF_STS bit of register PM1_STS, because this adds extra
+ // one I/O operation, and maybe generate SMI
+ //
+ while ((Counts != 0) || (RemainingTick > CurrentTick)) {
+ CurrentTick = IoRead32 ((UINTN) (ABase + R_ACPI_IO_PM1_TMR)) & B_ACPI_IO_PM1_TMR_TMR_VAL;
+ //
+ // Check if timer overflow
+ //
+ if ((CurrentTick < OriginalTick)) {
+ if (Counts != 0) {
+ Counts--;
+ } else {
+ //
+ // If timer overflow and Counts equ to 0, that means we already stalled more than
+ // RemainingTick, break the loop here
+ //
+ break;
+ }
+ }
+
+ OriginalTick = CurrentTick;
+ }
+}
+
+/**
+ Wait execution cycle to complete on the SPI interface.
+
+ @param[in] This The SPI protocol instance
+ @param[in] PchSpiBar0 Spi MMIO base address
+ @param[in] ErrorCheck TRUE if the SpiCycle needs to do the error check
+
+ @retval TRUE SPI cycle completed on the interface.
+ @retval FALSE Time out while waiting the SPI cycle to complete.
+ It's not safe to program the next command on the SPI interface.
+**/
+STATIC
+BOOLEAN
+WaitForSpiCycleComplete (
+ IN PCH_SPI_PROTOCOL *This,
+ IN UINTN PchSpiBar0,
+ IN BOOLEAN ErrorCheck
+ )
+{
+ UINT64 WaitTicks;
+ UINT64 WaitCount;
+ UINT32 Data32;
+ SPI_INSTANCE *SpiInstance;
+
+ SpiInstance = SPI_INSTANCE_FROM_SPIPROTOCOL (This);
+
+ //
+ // Convert the wait period allowed into to tick count
+ //
+ WaitCount = SPI_WAIT_TIME / SPI_WAIT_PERIOD;
+ //
+ // Wait for the SPI cycle to complete.
+ //
+ for (WaitTicks = 0; WaitTicks < WaitCount; WaitTicks++) {
+ Data32 = MmioRead32 (PchSpiBar0 + R_SPI_MEM_HSFSC);
+ if ((Data32 & B_SPI_MEM_HSFSC_SCIP) == 0) {
+ MmioWrite8 (PchSpiBar0 + R_SPI_MEM_HSFSC, B_SPI_MEM_HSFSC_FCERR | B_SPI_MEM_HSFSC_FDONE);
+ if (((Data32 & B_SPI_MEM_HSFSC_FCERR) != 0) && (ErrorCheck == TRUE)) {
+ return FALSE;
+ } else {
+ return TRUE;
+ }
+ }
+ PchPmTimerStallRuntimeSafe (SpiInstance->PchAcpiBase, SPI_WAIT_PERIOD);
+ }
+ return FALSE;
+}
+
+/**
+ This function waits for a pending SPI transaction to complete without clearing
+ status fields
+
+ @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
+ @param[in] PchSpiBar0 SPI MMIO address
+
+ @retval TRUE SPI cycle completed on the interface.
+ @retval FALSE Time out while waiting the SPI cycle to complete.
+ It's not safe to program the next command on the SPI interface.
+**/
+BOOLEAN
+STATIC
+WaitForScipNoClear (
+ IN PCH_SPI_PROTOCOL *This,
+ IN UINTN PchSpiBar0
+ )
+{
+ UINT64 WaitTicks;
+ UINT64 WaitCount;
+ SPI_INSTANCE *SpiInstance;
+ UINT32 Data32;
+
+ SpiInstance = SPI_INSTANCE_FROM_SPIPROTOCOL (This);
+
+ //
+ // Wait for the SPI cycle to complete.
+ //
+ WaitCount = SPI_WAIT_TIME / SPI_WAIT_PERIOD;
+ for (WaitTicks = 0; WaitTicks < WaitCount; WaitTicks++) {
+ Data32 = MmioRead32 (PchSpiBar0 + R_SPI_MEM_HSFSC);
+ if ((Data32 & B_SPI_MEM_HSFSC_SCIP) == 0) {
+ return TRUE;
+ }
+ PchPmTimerStallRuntimeSafe (SpiInstance->PchAcpiBase, SPI_WAIT_PERIOD);
+ }
+ return FALSE;
+}
+
+/**
+ This function sets the FDONE and optionally FCERR bits in the HSFS_CTL register
+
+ @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
+ @param[in] PchSpiBar0 SPI MMIO address
+ @param[in] SetErrorBit Set to TRUE to set the FCERR bit
+
+**/
+VOID
+STATIC
+SetHsfscFdone (
+ IN PCH_SPI_PROTOCOL *This,
+ IN UINTN PchSpiBar0,
+ IN BOOLEAN SetFcErrorBit
+ )
+{
+ EFI_STATUS Status;
+ UINT32 HardwareSpiAddr;
+ UINT32 FlashRegionSize;
+ UINT32 Index;
+ UINT8 DataCount;
+
+ Status = SpiProtocolGetRegionAddress (This, FlashRegionBios, &HardwareSpiAddr, &FlashRegionSize);
+ if (EFI_ERROR (Status)) {
+ return;
+ }
+
+ //
+ // Clear FDONE and FCERR
+ //
+ MmioWrite8 (PchSpiBar0 + R_SPI_MEM_HSFSC, B_SPI_MEM_HSFSC_FCERR | B_SPI_MEM_HSFSC_FDONE);
+
+ //
+ // Fill data buffer
+ //
+ if (SetFcErrorBit) {
+ for (Index = 0; Index < 64; Index += sizeof (UINT32)) {
+ MmioWrite32 (PchSpiBar0 + R_SPI_MEM_FDATA00 + Index, 0xFFFFFFFF);
+ }
+ }
+
+ //
+ // Set the Flash Address
+ //
+ MmioWrite32 (
+ (PchSpiBar0 + R_SPI_MEM_FADDR),
+ (UINT32) (HardwareSpiAddr & B_SPI_MEM_FADDR_MASK)
+ );
+ //
+ // Set Data count, Flash cycle, and Set Go bit to start a cycle
+ //
+ if (SetFcErrorBit) {
+ DataCount = 0x3F;
+ } else {
+ DataCount = 0;
+ }
+ MmioAndThenOr32 (
+ PchSpiBar0 + R_SPI_MEM_HSFSC,
+ (UINT32) (~(B_SPI_MEM_HSFSC_FDBC_MASK | B_SPI_MEM_HSFSC_CYCLE_MASK)),
+ (UINT32) (((DataCount << N_SPI_MEM_HSFSC_FDBC) & B_SPI_MEM_HSFSC_FDBC_MASK) |
+ (V_SPI_MEM_HSFSC_CYCLE_READ << N_SPI_MEM_HSFSC_CYCLE) |
+ B_SPI_MEM_HSFSC_CYCLE_FGO)
+ );
+
+ if (SetFcErrorBit) {
+ //
+ // Intentionally write to FDATA while a cycle is in progress to generate an error
+ //
+ for (Index = 0; Index < 64; Index += sizeof (UINT32)) {
+ MmioWrite32 (PchSpiBar0 + R_SPI_MEM_FDATA00 + Index, 0x0);
+ }
+ }
+
+ WaitForScipNoClear (This, PchSpiBar0);
+}
+
+/**
+ This function sends the programmed SPI command to the device.
+
+ @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
+ @param[in] SpiRegionType The SPI Region type for flash cycle which is listed in the Descriptor
+ @param[in] FlashCycleType The Flash SPI cycle type list in HSFC (Hardware Sequencing Flash Control Register) register
+ @param[in] Address The Flash Linear Address must fall within a region for which BIOS has access permissions.
+ @param[in] ByteCount Number of bytes in the data portion of the SPI cycle.
+ @param[in,out] Buffer Pointer to caller-allocated buffer containing the dada received or sent during the SPI cycle.
+
+ @retval EFI_SUCCESS SPI command completes successfully.
+ @retval EFI_DEVICE_ERROR Device error, the command aborts abnormally.
+ @retval EFI_ACCESS_DENIED Some unrecognized or blocked command encountered in hardware sequencing mode
+ @retval EFI_INVALID_PARAMETER The parameters specified are not valid.
+**/
+STATIC
+EFI_STATUS
+SendSpiCmd (
+ IN PCH_SPI_PROTOCOL *This,
+ IN FLASH_REGION_TYPE FlashRegionType,
+ IN FLASH_CYCLE_TYPE FlashCycleType,
+ IN UINT32 Address,
+ IN UINT32 ByteCount,
+ IN OUT UINT8 *Buffer
+ )
+{
+ UINT32 FdataSave[16];
+ EFI_STATUS Status;
+ UINT32 Index;
+ SPI_INSTANCE *SpiInstance;
+ UINT64 SpiBaseAddress;
+ UINTN PchSpiBar0;
+ UINT32 HardwareSpiAddr;
+ UINT32 FlashRegionSize;
+ UINT32 SpiDataCount;
+ UINT32 FlashCycle;
+ UINT8 BiosCtlSave;
+ UINT32 SmiEnSave;
+ UINT16 ABase;
+ UINT32 HsfstsCtl;
+ UINT32 FaddrSave;
+ UINT32 HsfscSave;
+ BOOLEAN HsfscFdoneSave;
+ BOOLEAN HsfscFcerrSave;
+ BOOLEAN RestoreState;
+
+ //
+ // For flash write, there is a requirement that all CPU threads are in SMM
+ // before the flash protection is disabled.
+ //
+ if ((FlashCycleType == FlashCycleWrite) || (FlashCycleType == FlashCycleErase)) {
+ if (!IsSpiFlashWriteGranted ()) {
+ return EFI_ACCESS_DENIED;
+ }
+ }
+
+ Status = EFI_SUCCESS;
+ SpiInstance = SPI_INSTANCE_FROM_SPIPROTOCOL (This);
+ SpiBaseAddress = SpiInstance->PchSpiBase;
+ ABase = SpiInstance->PchAcpiBase;
+ RestoreState = FALSE;
+
+ //
+ // Disable SMIs to make sure normal mode flash access is not interrupted by an SMI
+ // whose SMI handler accesses flash (e.g. for error logging)
+ //
+ // *** NOTE: if the SMI_LOCK bit is set (i.e., PMC PCI Offset A0h [4]='1'),
+ // clearing B_GBL_SMI_EN will not have effect. In this situation, some other
+ // synchronization methods must be applied here or in the consumer of the
+ // SendSpiCmd. An example method is disabling the specific SMI sources
+ // whose SMI handlers access flash before flash cycle and re-enabling the SMI
+ // sources after the flash cycle .
+ //
+ SmiEnSave = IoRead32 ((UINTN) (ABase + R_ACPI_IO_SMI_EN));
+ IoWrite32 ((UINTN) (ABase + R_ACPI_IO_SMI_EN), SmiEnSave & (UINT32) (~B_ACPI_IO_SMI_EN_GBL_SMI));
+ BiosCtlSave = PciSegmentRead8 (SpiBaseAddress + R_SPI_CFG_BC) & B_SPI_CFG_BC_SRC;
+
+ //
+ // Acquire SPI BAR0
+ //
+ PchSpiBar0 = AcquireSpiBar0 (SpiInstance);
+
+ //
+ // If it's write cycle, disable Prefetching, Caching and disable BIOS Write Protect
+ //
+ if ((FlashCycleType == FlashCycleWrite) ||
+ (FlashCycleType == FlashCycleErase)) {
+ Status = DisableBiosWriteProtect ();
+ if (EFI_ERROR (Status)) {
+ goto SendSpiCmdEnd;
+ }
+ PciSegmentAndThenOr8 (
+ SpiBaseAddress + R_SPI_CFG_BC,
+ (UINT8) (~B_SPI_CFG_BC_SRC),
+ (UINT8) (V_SPI_CFG_BC_SRC_PREF_DIS_CACHE_DIS << N_SPI_CFG_BC_SRC)
+ );
+ }
+
+ //
+ // Save current SPI controller state
+ //
+ if (IsSpiControllerSaveRestoreEnabled ()) {
+ if (!WaitForScipNoClear (This, PchSpiBar0)) {
+ Status = EFI_DEVICE_ERROR;
+ goto SendSpiCmdEnd;
+ }
+ HsfscSave = MmioRead32 (PchSpiBar0 + R_SPI_MEM_HSFSC);
+ HsfscFdoneSave = ((HsfscSave & B_SPI_MEM_HSFSC_FDONE) != 0) ? TRUE : FALSE;
+ HsfscFcerrSave = ((HsfscSave & B_SPI_MEM_HSFSC_FCERR) != 0) ? TRUE : FALSE;
+ HsfscSave &= B_SPI_MEM_HSFSC_SAVE_MASK;
+ FaddrSave = MmioRead32 (PchSpiBar0 + R_SPI_MEM_FADDR);
+ for (Index = 0; Index < 64; Index += sizeof (UINT32)) {
+ FdataSave[Index >> 2] = MmioRead32 (PchSpiBar0 + R_SPI_MEM_FDATA00 + Index);
+ }
+ RestoreState = TRUE;
+ }
+
+ //
+ // Make sure it's safe to program the command.
+ //
+ if (!WaitForSpiCycleComplete (This, PchSpiBar0, FALSE)) {
+ Status = EFI_DEVICE_ERROR;
+ goto SendSpiCmdEnd;
+ }
+
+ //
+ // Check if Write Status isn't disabled in HW Sequencing
+ //
+ if (FlashCycleType == FlashCycleWriteStatus) {
+ HsfstsCtl = MmioRead32 (PchSpiBar0 + R_SPI_MEM_HSFSC);
+ if ((HsfstsCtl & B_SPI_MEM_HSFSC_WRSDIS) != 0) {
+ Status = EFI_ACCESS_DENIED;
+ goto SendSpiCmdEnd;
+ }
+ }
+
+ Status = SpiProtocolGetRegionAddress (This, FlashRegionType, &HardwareSpiAddr, &FlashRegionSize);
+ if (EFI_ERROR (Status)) {
+ goto SendSpiCmdEnd;
+ }
+ HardwareSpiAddr += Address;
+ if ((Address + ByteCount) > FlashRegionSize) {
+ Status = EFI_INVALID_PARAMETER;
+ goto SendSpiCmdEnd;
+ }
+
+ //
+ // Check for PCH SPI hardware sequencing required commands
+ //
+ FlashCycle = 0;
+ switch (FlashCycleType) {
+ case FlashCycleRead:
+ FlashCycle = (UINT32) (V_SPI_MEM_HSFSC_CYCLE_READ << N_SPI_MEM_HSFSC_CYCLE);
+ break;
+ case FlashCycleWrite:
+ FlashCycle = (UINT32) (V_SPI_MEM_HSFSC_CYCLE_WRITE << N_SPI_MEM_HSFSC_CYCLE);
+ break;
+ case FlashCycleErase:
+ if (((ByteCount % SIZE_4KB) != 0) ||
+ ((HardwareSpiAddr % SIZE_4KB) != 0)) {
+ ASSERT (FALSE);
+ Status = EFI_INVALID_PARAMETER;
+ goto SendSpiCmdEnd;
+ }
+ break;
+ case FlashCycleReadSfdp:
+ FlashCycle = (UINT32) (V_SPI_MEM_HSFSC_CYCLE_READ_SFDP << N_SPI_MEM_HSFSC_CYCLE);
+ break;
+ case FlashCycleReadJedecId:
+ FlashCycle = (UINT32) (V_SPI_MEM_HSFSC_CYCLE_READ_JEDEC_ID << N_SPI_MEM_HSFSC_CYCLE);
+ break;
+ case FlashCycleWriteStatus:
+ FlashCycle = (UINT32) (V_SPI_MEM_HSFSC_CYCLE_WRITE_STATUS << N_SPI_MEM_HSFSC_CYCLE);
+ break;
+ case FlashCycleReadStatus:
+ FlashCycle = (UINT32) (V_SPI_MEM_HSFSC_CYCLE_READ_STATUS << N_SPI_MEM_HSFSC_CYCLE);
+ break;
+ default:
+ //
+ // Unrecognized Operation
+ //
+ ASSERT (FALSE);
+ Status = EFI_INVALID_PARAMETER;
+ goto SendSpiCmdEnd;
+ break;
+ }
+
+ do {
+ SpiDataCount = ByteCount;
+ if ((FlashCycleType == FlashCycleRead) ||
+ (FlashCycleType == FlashCycleWrite) ||
+ (FlashCycleType == FlashCycleReadSfdp)) {
+ //
+ // Trim at 256 byte boundary per operation,
+ // - PCH SPI controller requires trimming at 4KB boundary
+ // - Some SPI chips require trimming at 256 byte boundary for write operation
+ // - Trimming has limited performance impact as we can read / write at most 64 bytes
+ // per operation
+ //
+ if (HardwareSpiAddr + ByteCount > ((HardwareSpiAddr + BIT8) &~(BIT8 - 1))) {
+ SpiDataCount = (((UINT32) (HardwareSpiAddr) + BIT8) &~(BIT8 - 1)) - (UINT32) (HardwareSpiAddr);
+ }
+ //
+ // Calculate the number of bytes to shift in/out during the SPI data cycle.
+ // Valid settings for the number of bytes during each data portion of the
+ // PCH SPI cycles are: 0, 1, 2, 3, 4, 5, 6, 7, 8, 16, 24, 32, 40, 48, 56, 64
+ //
+ if (SpiDataCount >= 64) {
+ SpiDataCount = 64;
+ } else if ((SpiDataCount &~0x07) != 0) {
+ SpiDataCount = SpiDataCount &~0x07;
+ }
+ }
+ if (FlashCycleType == FlashCycleErase) {
+ if (((ByteCount / SIZE_64KB) != 0) &&
+ ((ByteCount % SIZE_64KB) == 0) &&
+ ((HardwareSpiAddr % SIZE_64KB) == 0)) {
+ if ((SpiInstance->NumberOfComponents == 0) ||
+ (HardwareSpiAddr < SpiInstance->Component1StartAddr)) {
+ //
+ // Check whether Component0 support 64k Erase
+ //
+ if ((SpiInstance->SfdpVscc0Value & B_SPI_MEM_SFDPX_VSCCX_EO_64K) != 0) {
+ SpiDataCount = SIZE_64KB;
+ } else {
+ SpiDataCount = SIZE_4KB;
+ }
+ } else {
+ //
+ // Check whether Component1 support 64k Erase
+ //
+ if ((SpiInstance->SfdpVscc1Value & B_SPI_MEM_SFDPX_VSCCX_EO_64K) != 0) {
+ SpiDataCount = SIZE_64KB;
+ } else {
+ SpiDataCount = SIZE_4KB;
+ }
+ }
+ } else {
+ SpiDataCount = SIZE_4KB;
+ }
+ if (SpiDataCount == SIZE_4KB) {
+ FlashCycle = (UINT32) (V_SPI_MEM_HSFSC_CYCLE_4K_ERASE << N_SPI_MEM_HSFSC_CYCLE);
+ } else {
+ FlashCycle = (UINT32) (V_SPI_MEM_HSFSC_CYCLE_64K_ERASE << N_SPI_MEM_HSFSC_CYCLE);
+ }
+ }
+ //
+ // If it's write cycle, load data into the SPI data buffer.
+ //
+ if ((FlashCycleType == FlashCycleWrite) || (FlashCycleType == FlashCycleWriteStatus)) {
+ if ((SpiDataCount & 0x07) != 0) {
+ //
+ // Use Byte write if Data Count is 0, 1, 2, 3, 4, 5, 6, 7
+ //
+ for (Index = 0; Index < SpiDataCount; Index++) {
+ MmioWrite8 (PchSpiBar0 + R_SPI_MEM_FDATA00 + Index, Buffer[Index]);
+ }
+ } else {
+ //
+ // Use Dword write if Data Count is 8, 16, 24, 32, 40, 48, 56, 64
+ //
+ for (Index = 0; Index < SpiDataCount; Index += sizeof (UINT32)) {
+ MmioWrite32 (PchSpiBar0 + R_SPI_MEM_FDATA00 + Index, *(UINT32 *) (Buffer + Index));
+ }
+ }
+ }
+
+ //
+ // Set the Flash Address
+ //
+ MmioWrite32 (
+ (PchSpiBar0 + R_SPI_MEM_FADDR),
+ (UINT32) (HardwareSpiAddr & B_SPI_MEM_FADDR_MASK)
+ );
+
+ //
+ // Set Data count, Flash cycle, and Set Go bit to start a cycle
+ //
+ MmioAndThenOr32 (
+ PchSpiBar0 + R_SPI_MEM_HSFSC,
+ (UINT32) (~(B_SPI_MEM_HSFSC_FDBC_MASK | B_SPI_MEM_HSFSC_CYCLE_MASK)),
+ (UINT32) ((((SpiDataCount - 1) << N_SPI_MEM_HSFSC_FDBC) & B_SPI_MEM_HSFSC_FDBC_MASK) | FlashCycle | B_SPI_MEM_HSFSC_CYCLE_FGO)
+ );
+ //
+ // end of command execution
+ //
+ // Wait the SPI cycle to complete.
+ //
+ if (!WaitForSpiCycleComplete (This, PchSpiBar0, TRUE)) {
+ ASSERT (FALSE);
+ Status = EFI_DEVICE_ERROR;
+ goto SendSpiCmdEnd;
+ }
+ //
+ // If it's read cycle, load data into the call's buffer.
+ //
+ if ((FlashCycleType == FlashCycleRead) ||
+ (FlashCycleType == FlashCycleReadSfdp) ||
+ (FlashCycleType == FlashCycleReadJedecId) ||
+ (FlashCycleType == FlashCycleReadStatus)) {
+ if ((SpiDataCount & 0x07) != 0) {
+ //
+ // Use Byte read if Data Count is 0, 1, 2, 3, 4, 5, 6, 7
+ //
+ for (Index = 0; Index < SpiDataCount; Index++) {
+ Buffer[Index] = MmioRead8 (PchSpiBar0 + R_SPI_MEM_FDATA00 + Index);
+ }
+ } else {
+ //
+ // Use Dword read if Data Count is 8, 16, 24, 32, 40, 48, 56, 64
+ //
+ for (Index = 0; Index < SpiDataCount; Index += sizeof (UINT32)) {
+ *(UINT32 *) (Buffer + Index) = MmioRead32 (PchSpiBar0 + R_SPI_MEM_FDATA00 + Index);
+ }
+ }
+ }
+
+ HardwareSpiAddr += SpiDataCount;
+ Buffer += SpiDataCount;
+ ByteCount -= SpiDataCount;
+ } while (ByteCount > 0);
+
+SendSpiCmdEnd:
+ //
+ // Restore SPI controller state
+ //
+ if (RestoreState) {
+ if (HsfscFdoneSave) {
+ SetHsfscFdone (This, PchSpiBar0, HsfscFcerrSave);
+ }
+ MmioAndThenOr32 (
+ PchSpiBar0 + R_SPI_MEM_HSFSC,
+ (UINT32) ~(B_SPI_MEM_HSFSC_SAVE_MASK |
+ B_SPI_MEM_HSFSC_SAF_CE | // This bit clears when set to 1, ensure 0 is written
+ B_SPI_MEM_HSFSC_SAF_LE | // This bit clears when set to 1, ensure 0 is written
+ B_SPI_MEM_HSFSC_SAF_DLE | // This bit clears when set to 1, ensure 0 is written
+ B_SPI_MEM_HSFSC_SAF_ERROR | // This bit clears when set to 1, ensure 0 is written
+ B_SPI_MEM_HSFSC_AEL | // This bit clears when set to 1, ensure 0 is written
+ B_SPI_MEM_HSFSC_FCERR | // This bit clears when set to 1, ensure 0 is written
+ B_SPI_MEM_HSFSC_FDONE), // This bit clears when set to 1, ensure 0 is written
+ HsfscSave
+ );
+ MmioWrite32 (PchSpiBar0 + R_SPI_MEM_FADDR, FaddrSave);
+ for (Index = 0; Index < 64; Index += sizeof (UINT32)) {
+ MmioWrite32 (PchSpiBar0 + R_SPI_MEM_FDATA00 + Index, FdataSave[Index >> 2]);
+ }
+ }
+
+ //
+ // Restore the settings for SPI Prefetching and Caching and enable BIOS Write Protect
+ //
+ if ((FlashCycleType == FlashCycleWrite) ||
+ (FlashCycleType == FlashCycleErase)) {
+ EnableBiosWriteProtect ();
+ PciSegmentAndThenOr8 (
+ SpiBaseAddress + R_SPI_CFG_BC,
+ (UINT8) ~B_SPI_CFG_BC_SRC,
+ BiosCtlSave
+ );
+ }
+ ReleaseSpiBar0 (SpiInstance);
+
+ //
+ // Restore SMIs.
+ //
+ IoWrite32 ((UINTN) (ABase + R_ACPI_IO_SMI_EN), SmiEnSave);
+
+ return Status;
+}
+
+/**
+ Read data from the flash part.
+
+ @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
+ @param[in] FlashRegionType The Flash Region type for flash cycle which is listed in the Descriptor.
+ @param[in] Address The Flash Linear Address must fall within a region for which BIOS has access permissions.
+ @param[in] ByteCount Number of bytes in the data portion of the SPI cycle.
+ @param[out] Buffer The Pointer to caller-allocated buffer containing the dada received.
+ It is the caller's responsibility to make sure Buffer is large enough for the total number of bytes read.
+
+ @retval EFI_SUCCESS Command succeed.
+ @retval EFI_INVALID_PARAMETER The parameters specified are not valid.
+ @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
+**/
+EFI_STATUS
+EFIAPI
+SpiProtocolFlashRead (
+ IN PCH_SPI_PROTOCOL *This,
+ IN FLASH_REGION_TYPE FlashRegionType,
+ IN UINT32 Address,
+ IN UINT32 ByteCount,
+ OUT UINT8 *Buffer
+ )
+{
+ EFI_STATUS Status;
+
+ //
+ // Sends the command to the SPI interface to execute.
+ //
+ Status = SendSpiCmd (
+ This,
+ FlashRegionType,
+ FlashCycleRead,
+ Address,
+ ByteCount,
+ Buffer
+ );
+ return Status;
+}
+
+/**
+ Write data to the flash part.
+
+ @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
+ @param[in] FlashRegionType The Flash Region type for flash cycle which is listed in the Descriptor.
+ @param[in] Address The Flash Linear Address must fall within a region for which BIOS has access permissions.
+ @param[in] ByteCount Number of bytes in the data portion of the SPI cycle.
+ @param[in] Buffer Pointer to caller-allocated buffer containing the data sent during the SPI cycle.
+
+ @retval EFI_SUCCESS Command succeed.
+ @retval EFI_INVALID_PARAMETER The parameters specified are not valid.
+ @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
+**/
+EFI_STATUS
+EFIAPI
+SpiProtocolFlashWrite (
+ IN PCH_SPI_PROTOCOL *This,
+ IN FLASH_REGION_TYPE FlashRegionType,
+ IN UINT32 Address,
+ IN UINT32 ByteCount,
+ IN UINT8 *Buffer
+ )
+{
+ EFI_STATUS Status;
+
+ //
+ // Sends the command to the SPI interface to execute.
+ //
+ Status = SendSpiCmd (
+ This,
+ FlashRegionType,
+ FlashCycleWrite,
+ Address,
+ ByteCount,
+ Buffer
+ );
+ return Status;
+}
+
+/**
+ Erase some area on the flash part.
+
+ @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
+ @param[in] FlashRegionType The Flash Region type for flash cycle which is listed in the Descriptor.
+ @param[in] Address The Flash Linear Address must fall within a region for which BIOS has access permissions.
+ @param[in] ByteCount Number of bytes in the data portion of the SPI cycle.
+
+ @retval EFI_SUCCESS Command succeed.
+ @retval EFI_INVALID_PARAMETER The parameters specified are not valid.
+ @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
+**/
+EFI_STATUS
+EFIAPI
+SpiProtocolFlashErase (
+ IN PCH_SPI_PROTOCOL *This,
+ IN FLASH_REGION_TYPE FlashRegionType,
+ IN UINT32 Address,
+ IN UINT32 ByteCount
+ )
+{
+ EFI_STATUS Status;
+
+ //
+ // Sends the command to the SPI interface to execute.
+ //
+ Status = SendSpiCmd (
+ This,
+ FlashRegionType,
+ FlashCycleErase,
+ Address,
+ ByteCount,
+ NULL
+ );
+ return Status;
+}
+
+/**
+ Read SFDP data from the flash part.
+
+ @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
+ @param[in] ComponentNumber The Componen Number for chip select
+ @param[in] Address The starting byte address for SFDP data read.
+ @param[in] ByteCount Number of bytes in SFDP data portion of the SPI cycle
+ @param[out] SfdpData The Pointer to caller-allocated buffer containing the SFDP data received
+ It is the caller's responsibility to make sure Buffer is large enough for the total number of bytes read
+
+ @retval EFI_SUCCESS Command succeed.
+ @retval EFI_INVALID_PARAMETER The parameters specified are not valid.
+ @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
+ @retval EFI_UNSUPPORTED Unsupported operation with SAF Mode enabled
+**/
+EFI_STATUS
+EFIAPI
+SpiProtocolFlashReadSfdp (
+ IN PCH_SPI_PROTOCOL *This,
+ IN UINT8 ComponentNumber,
+ IN UINT32 Address,
+ IN UINT32 ByteCount,
+ OUT UINT8 *SfdpData
+ )
+{
+ return EFI_SUCCESS;
+}
+
+/**
+ Read Jedec Id from the flash part.
+
+ @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
+ @param[in] ComponentNumber The Componen Number for chip select
+ @param[in] ByteCount Number of bytes in JedecId data portion of the SPI cycle, the data size is 3 typically
+ @param[out] JedecId The Pointer to caller-allocated buffer containing JEDEC ID received
+ It is the caller's responsibility to make sure Buffer is large enough for the total number of bytes read.
+
+ @retval EFI_SUCCESS Command succeed.
+ @retval EFI_INVALID_PARAMETER The parameters specified are not valid.
+ @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
+ @retval EFI_UNSUPPORTED Unsupported operation with SAF Mode enabled
+**/
+EFI_STATUS
+EFIAPI
+SpiProtocolFlashReadJedecId (
+ IN PCH_SPI_PROTOCOL *This,
+ IN UINT8 ComponentNumber,
+ IN UINT32 ByteCount,
+ OUT UINT8 *JedecId
+ )
+{
+ return EFI_SUCCESS;
+}
+
+/**
+ Write the status register in the flash part.
+
+ @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
+ @param[in] ByteCount Number of bytes in Status data portion of the SPI cycle, the data size is 1 typically
+ @param[in] StatusValue The Pointer to caller-allocated buffer containing the value of Status register writing
+
+ @retval EFI_SUCCESS Command succeed.
+ @retval EFI_INVALID_PARAMETER The parameters specified are not valid.
+ @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
+ @retval EFI_UNSUPPORTED Unsupported operation with SAF Mode enabled
+**/
+EFI_STATUS
+EFIAPI
+SpiProtocolFlashWriteStatus (
+ IN PCH_SPI_PROTOCOL *This,
+ IN UINT32 ByteCount,
+ IN UINT8 *StatusValue
+ )
+{
+ return EFI_SUCCESS;
+}
+
+/**
+ Read status register in the flash part.
+
+ @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
+ @param[in] ByteCount Number of bytes in Status data portion of the SPI cycle, the data size is 1 typically
+ @param[out] StatusValue The Pointer to caller-allocated buffer containing the value of Status register received.
+
+ @retval EFI_SUCCESS Command succeed.
+ @retval EFI_INVALID_PARAMETER The parameters specified are not valid.
+ @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
+ @retval EFI_UNSUPPORTED Unsupported operation with SAF Mode enabled
+**/
+EFI_STATUS
+EFIAPI
+SpiProtocolFlashReadStatus (
+ IN PCH_SPI_PROTOCOL *This,
+ IN UINT32 ByteCount,
+ OUT UINT8 *StatusValue
+ )
+{
+ return EFI_SUCCESS;
+}
+
+/**
+ Get the SPI region base and size, based on the enum type
+
+ @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
+ @param[in] FlashRegionType The Flash Region type for for the base address which is listed in the Descriptor.
+ @param[out] BaseAddress The Flash Linear Address for the Region 'n' Base
+ @param[out] RegionSize The size for the Region 'n'
+
+ @retval EFI_SUCCESS Read success
+ @retval EFI_INVALID_PARAMETER Invalid region type given
+ @retval EFI_DEVICE_ERROR The region is not used
+**/
+EFI_STATUS
+EFIAPI
+SpiProtocolGetRegionAddress (
+ IN PCH_SPI_PROTOCOL *This,
+ IN FLASH_REGION_TYPE FlashRegionType,
+ OUT UINT32 *BaseAddress,
+ OUT UINT32 *RegionSize
+ )
+{
+ SPI_INSTANCE *SpiInstance;
+ UINTN PchSpiBar0;
+ UINT32 ReadValue;
+
+ SpiInstance = SPI_INSTANCE_FROM_SPIPROTOCOL (This);
+
+ if (FlashRegionType >= FlashRegionMax) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ if (FlashRegionType == FlashRegionAll) {
+ *BaseAddress = 0;
+ *RegionSize = SpiInstance->TotalFlashSize;
+ return EFI_SUCCESS;
+ }
+
+ PchSpiBar0 = AcquireSpiBar0 (SpiInstance);
+
+ ReadValue = MmioRead32 (PchSpiBar0 + (R_SPI_MEM_FREG0_FLASHD + (S_SPI_MEM_FREGX * ((UINT32) FlashRegionType))));
+
+ ReleaseSpiBar0 (SpiInstance);
+
+ //
+ // If the region is not used, the Region Base is 7FFFh and Region Limit is 0000h
+ //
+ if (ReadValue == B_SPI_MEM_FREGX_BASE_MASK) {
+ return EFI_DEVICE_ERROR;
+ }
+ *BaseAddress = ((ReadValue & B_SPI_MEM_FREGX_BASE_MASK) >> N_SPI_MEM_FREGX_BASE) <<
+ N_SPI_MEM_FREGX_BASE_REPR;
+ //
+ // Region limit address Bits[11:0] are assumed to be FFFh
+ //
+ *RegionSize = ((((ReadValue & B_SPI_MEM_FREGX_LIMIT_MASK) >> N_SPI_MEM_FREGX_LIMIT) + 1) <<
+ N_SPI_MEM_FREGX_LIMIT_REPR) - *BaseAddress;
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Read PCH Soft Strap Values
+
+ @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
+ @param[in] SoftStrapAddr PCH Soft Strap address offset from FPSBA.
+ @param[in] ByteCount Number of bytes in SoftStrap data portion of the SPI cycle
+ @param[out] SoftStrapValue The Pointer to caller-allocated buffer containing PCH Soft Strap Value.
+ If the value of ByteCount is 0, the data type of SoftStrapValue should be UINT16 and SoftStrapValue will be PCH Soft Strap Length
+ It is the caller's responsibility to make sure Buffer is large enough for the total number of bytes read.
+
+ @retval EFI_SUCCESS Command succeed.
+ @retval EFI_INVALID_PARAMETER The parameters specified are not valid.
+ @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
+**/
+EFI_STATUS
+EFIAPI
+SpiProtocolReadPchSoftStrap (
+ IN PCH_SPI_PROTOCOL *This,
+ IN UINT32 SoftStrapAddr,
+ IN UINT32 ByteCount,
+ OUT VOID *SoftStrapValue
+ )
+{
+ return EFI_SUCCESS;
+}
+
+/**
+ Read CPU Soft Strap Values
+
+ @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
+ @param[in] SoftStrapAddr CPU Soft Strap address offset from FCPUSBA.
+ @param[in] ByteCount Number of bytes in SoftStrap data portion of the SPI cycle.
+ @param[out] SoftStrapValue The Pointer to caller-allocated buffer containing CPU Soft Strap Value.
+ If the value of ByteCount is 0, the data type of SoftStrapValue should be UINT16 and SoftStrapValue will be PCH Soft Strap Length
+ It is the caller's responsibility to make sure Buffer is large enough for the total number of bytes read.
+
+ @retval EFI_SUCCESS Command succeed.
+ @retval EFI_INVALID_PARAMETER The parameters specified are not valid.
+ @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
+**/
+EFI_STATUS
+EFIAPI
+SpiProtocolReadCpuSoftStrap (
+ IN PCH_SPI_PROTOCOL *This,
+ IN UINT32 SoftStrapAddr,
+ IN UINT32 ByteCount,
+ OUT VOID *SoftStrapValue
+ )
+{
+ return EFI_SUCCESS;
+}
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/Smm/Spi.c b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/Smm/Spi.c
new file mode 100644
index 0000000000..2dd80eba7c
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/Smm/Spi.c
@@ -0,0 +1,387 @@
+/** @file
+ PCH SPI SMM Driver implements the SPI Host Controller Compatibility Interface.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <Library/IoLib.h>
+#include <Library/DebugLib.h>
+#include <Library/UefiDriverEntryPoint.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/BaseLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/SmmServicesTableLib.h>
+#include <Library/PciSegmentLib.h>
+#include <Protocol/Spi.h>
+#include <Protocol/SmmCpu.h>
+#include <Library/SpiCommonLib.h>
+#include <PchReservedResources.h>
+#include <Library/PchPciBdfLib.h>
+#include <IndustryStandard/Pci30.h>
+#include <Register/PchRegs.h>
+#include <Register/SpiRegs.h>
+
+//
+// Global variables
+//
+GLOBAL_REMOVE_IF_UNREFERENCED SPI_INSTANCE *mSpiInstance;
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_SMM_CPU_PROTOCOL *mSmmCpuProtocol;
+//
+// mPchSpiResvMmioAddr keeps the reserved MMIO range assigned to SPI.
+// In SMM it always set back the reserved MMIO address to SPI BAR0 to ensure the MMIO range
+// won't overlap with SMRAM range, and trusted.
+//
+GLOBAL_REMOVE_IF_UNREFERENCED UINT32 mSpiResvMmioAddr;
+//
+// mPchSpiSavedMmioAddr keeps the MMIO range assigned to SPI by PCI enumeration.
+// In SMM this is used to restore the original value for SPI BAR0 after finishing
+// commands to the SPI controller.
+//
+GLOBAL_REMOVE_IF_UNREFERENCED UINT32 mSpiSavedMmioAddr;
+//
+// mPchSpiBar0RefCount stores the reference count for SPI BAR0.
+//
+GLOBAL_REMOVE_IF_UNREFERENCED UINT32 mPchSpiBar0RefCount;
+//
+// mPchSpiSavedPciCmdReg stores the PCI command register state at the start of the
+// SPI transaction. This is used to restore the original PCI command register
+// state after finishing commands to the SPI controller.
+//
+GLOBAL_REMOVE_IF_UNREFERENCED UINT8 mPchSpiSavedPciCmdReg;
+GLOBAL_REMOVE_IF_UNREFERENCED BOOLEAN mBootServiceExited;
+
+/**
+ This function is invoked at ExitBootServices()
+
+ @param[in] Protocol Protocol unique ID.
+ @param[in] Interface Interface instance.
+ @param[in] Handle The handle on which the interface is installed..
+
+ @retval Status.
+**/
+EFI_STATUS
+EFIAPI
+SpiExitBootServicesCallback (
+ IN CONST EFI_GUID *Protocol,
+ IN VOID *Interface,
+ IN EFI_HANDLE Handle
+ )
+{
+ mBootServiceExited = TRUE;
+ return EFI_SUCCESS;
+}
+
+/**
+ <b>SPI Runtime SMM Module Entry Point</b>\n
+ - <b>Introduction</b>\n
+ The SPI SMM module provide a standard way for other modules to use the PCH SPI Interface in SMM.
+
+ - @pre
+ - EFI_SMM_BASE2_PROTOCOL
+ - Documented in System Management Mode Core Interface Specification .
+
+ - @result
+ The SPI SMM driver produces @link _PCH_SPI_PROTOCOL PCH_SPI_PROTOCOL @endlink with GUID
+ gPchSmmSpiProtocolGuid which is different from SPI RUNTIME driver.
+
+ - <b>Integration Check List</b>\n
+ - This driver supports Descriptor Mode only.
+ - This driver supports Hardware Sequence only.
+ - When using SMM SPI Protocol to perform flash access in an SMI handler,
+ and the SMI occurrence is asynchronous to normal mode code execution,
+ proper synchronization mechanism must be applied, e.g. disable SMI before
+ the normal mode SendSpiCmd() starts and re-enable SMI after
+ the normal mode SendSpiCmd() completes.
+ @note The implementation of SendSpiCmd() uses GBL_SMI_EN in
+ SMI_EN register (ABase + 30h) to disable and enable SMIs. But this may
+ not be effective as platform may well set the SMI_LOCK bit (i.e., PMC PCI Offset A0h [4]).
+ So the synchronization at caller level is likely needed.
+
+ @param[in] ImageHandle Image handle of this driver.
+ @param[in] SystemTable Global system service table.
+
+ @retval EFI_SUCCESS Initialization complete.
+ @exception EFI_UNSUPPORTED The chipset is unsupported by this driver.
+ @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize the driver.
+ @retval EFI_DEVICE_ERROR Device error, driver exits abnormally.
+**/
+EFI_STATUS
+EFIAPI
+InstallPchSpi (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUS Status;
+ VOID *Registration;
+
+ //
+ // Init PCH spi reserved MMIO address.
+ //
+ mSpiResvMmioAddr = PCH_SPI_BASE_ADDRESS;
+ mSpiSavedMmioAddr = 0;
+ mPchSpiBar0RefCount = 0;
+ mPchSpiSavedPciCmdReg = 0;
+ mBootServiceExited = FALSE;
+
+ ///
+ /// Allocate pool for SPI protocol instance
+ ///
+ Status = gSmst->SmmAllocatePool (
+ EfiRuntimeServicesData, /// MemoryType don't care
+ sizeof (SPI_INSTANCE),
+ (VOID **) &mSpiInstance
+ );
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ if (mSpiInstance == NULL) {
+ return EFI_OUT_OF_RESOURCES;
+ }
+
+ ZeroMem ((VOID *) mSpiInstance, sizeof (SPI_INSTANCE));
+ ///
+ /// Initialize the SPI protocol instance
+ ///
+ Status = SpiProtocolConstructor (mSpiInstance);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ //
+ // Register ExitBootServices callback
+ //
+ Status = gSmst->SmmRegisterProtocolNotify (
+ &gEdkiiSmmExitBootServicesProtocolGuid,
+ SpiExitBootServicesCallback,
+ &Registration
+ );
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ //
+ // Install the SMM PCH_SPI_PROTOCOL interface
+ //
+ Status = gSmst->SmmInstallProtocolInterface (
+ &(mSpiInstance->Handle),
+ &gPchSmmSpiProtocolGuid,
+ EFI_NATIVE_INTERFACE,
+ &(mSpiInstance->SpiProtocol)
+ );
+ if (EFI_ERROR (Status)) {
+ gSmst->SmmFreePool (mSpiInstance);
+ return EFI_DEVICE_ERROR;
+ }
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Acquire PCH SPI MMIO address.
+ It is not expected for this BAR0 to change because the SPI device is usually
+ hidden from the OS. But if it is ever different from the preallocated address,
+ reassign it back. In SMM, BAR0 will always be overwritten and the reserved
+ MMIO range for SPI will be returned.
+
+ @param[in] SpiInstance Pointer to SpiInstance to initialize
+
+ @retval PchSpiBar0 return SPI MMIO address
+**/
+UINTN
+AcquireSpiBar0 (
+ IN SPI_INSTANCE *SpiInstance
+ )
+{
+ UINT32 SpiBar0;
+ UINT8 PciCmdReg;
+
+ //
+ // Save original SPI physical MMIO address
+ //
+ SpiBar0 = PciSegmentRead32 (SpiInstance->PchSpiBase + R_SPI_CFG_BAR0) & ~(B_SPI_CFG_BAR0_MASK);
+ PciCmdReg = PciSegmentRead8 (SpiInstance->PchSpiBase + PCI_COMMAND_OFFSET);
+
+ if ((SpiBar0 != mSpiResvMmioAddr) || ((PciCmdReg & EFI_PCI_COMMAND_MEMORY_SPACE) == 0)) {
+ //
+ // Save PCI command register state and BAR value assigned by PCI enumeration
+ //
+ mPchSpiSavedPciCmdReg = PciCmdReg;
+ mSpiSavedMmioAddr = SpiBar0;
+
+ //
+ // Temporary disable MSE, and override with SPI reserved MMIO address, then enable MSE.
+ //
+ PciSegmentAnd8 (SpiInstance->PchSpiBase + PCI_COMMAND_OFFSET, (UINT8) ~EFI_PCI_COMMAND_MEMORY_SPACE);
+ PciSegmentWrite32 (SpiInstance->PchSpiBase + R_SPI_CFG_BAR0, mSpiResvMmioAddr);
+ PciSegmentOr8 (SpiInstance->PchSpiBase + PCI_COMMAND_OFFSET, EFI_PCI_COMMAND_MEMORY_SPACE);
+ } else if (mPchSpiBar0RefCount == 0) {
+ mSpiSavedMmioAddr = 0;
+ mPchSpiSavedPciCmdReg = 0;
+ }
+ mPchSpiBar0RefCount++;
+
+ //
+ // SPIBAR0 will be different before and after PCI enum so need to get it from SPI BAR0 reg.
+ //
+ return mSpiResvMmioAddr;
+}
+
+/**
+ Release PCH SPI MMIO address. If AcquireSpiBar0() previously overwrote the
+ value of BAR0, this function will restore the original value assigned by PCI
+ enumeration
+
+ @param[in] SpiInstance Pointer to SpiInstance to initialize
+
+ @retval None
+**/
+VOID
+ReleaseSpiBar0 (
+ IN SPI_INSTANCE *SpiInstance
+ )
+{
+ //
+ // Reference counting is used here because multiple nested calls to
+ // AcquireSpiBar0()/ReleaseSpiBar0() will cause SpiBar0 to be reprogrammed
+ // back to the original value before access to the SPI controller is done.
+ // Reference counting ensures that the BAR is not restored until after access
+ // is complete.
+ //
+ if (mPchSpiBar0RefCount <= 1) {
+ mPchSpiBar0RefCount = 0;
+ if (mSpiSavedMmioAddr != 0) {
+ //
+ // Temporary disable MSE, restore the original SPI MMIO address, then
+ // restore PCI command register state
+ //
+ PciSegmentAnd8 (SpiInstance->PchSpiBase + PCI_COMMAND_OFFSET, (UINT8)~EFI_PCI_COMMAND_MEMORY_SPACE);
+ PciSegmentWrite32 (SpiInstance->PchSpiBase + R_SPI_CFG_BAR0, mSpiSavedMmioAddr);
+ PciSegmentWrite8 (SpiInstance->PchSpiBase + PCI_COMMAND_OFFSET, mPchSpiSavedPciCmdReg);
+
+ //
+ // Clear saved state
+ //
+ mSpiSavedMmioAddr = 0;
+ mPchSpiSavedPciCmdReg = 0;
+ }
+ } else {
+ mPchSpiBar0RefCount--;
+ }
+}
+
+/**
+ This function is a hook for Spi to disable BIOS Write Protect
+
+ @retval EFI_SUCCESS The protocol instance was properly initialized
+ @retval EFI_ACCESS_DENIED The BIOS Region can only be updated in SMM phase
+
+**/
+EFI_STATUS
+EFIAPI
+DisableBiosWriteProtect (
+ VOID
+ )
+{
+ UINT64 SpiBaseAddress;
+
+ SpiBaseAddress = SpiPciCfgBase ();
+ // Write clear BC_SYNC_SS prior to change WPD from 0 to 1.
+ //
+ PciSegmentOr8 (
+ SpiBaseAddress + R_SPI_CFG_BC + 1,
+ (B_SPI_CFG_BC_SYNC_SS >> 8)
+ );
+ ///
+ /// Set BIOSWE bit (SPI PCI Offset DCh [0]) = 1b
+ /// Enable the access to the BIOS space for both read and write cycles
+ ///
+ PciSegmentOr8 (
+ SpiBaseAddress + R_SPI_CFG_BC,
+ B_SPI_CFG_BC_WPD
+ );
+
+ return EFI_SUCCESS;
+}
+
+/**
+ This function is a hook for Spi to enable BIOS Write Protect
+**/
+VOID
+EFIAPI
+EnableBiosWriteProtect (
+ VOID
+ )
+{
+ UINT64 SpiBaseAddress;
+
+ SpiBaseAddress = SpiPciCfgBase ();
+ ///
+ /// Clear BIOSWE bit (SPI PCI Offset DCh [0]) = 0b
+ /// Disable the access to the BIOS space for write cycles
+ ///
+ PciSegmentAnd8 (
+ SpiBaseAddress + R_SPI_CFG_BC,
+ (UINT8) (~B_SPI_CFG_BC_WPD)
+ );
+
+}
+
+/**
+ Check if it's granted to do flash write.
+
+ @retval TRUE It's secure to do flash write.
+ @retval FALSE It's not secure to do flash write.
+**/
+BOOLEAN
+IsSpiFlashWriteGranted (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+ UINT32 CpuIndex;
+ UINT64 ProcessorId;
+
+ if (mSmmCpuProtocol == NULL) {
+ Status = gSmst->SmmLocateProtocol (&gEfiSmmCpuProtocolGuid, NULL, (VOID **)&mSmmCpuProtocol);
+ ASSERT_EFI_ERROR (Status);
+ if (mSmmCpuProtocol == NULL) {
+ return TRUE;
+ }
+ }
+
+ for (CpuIndex = 0; CpuIndex < gSmst->NumberOfCpus; CpuIndex++) {
+ Status = mSmmCpuProtocol->ReadSaveState (
+ mSmmCpuProtocol,
+ sizeof (ProcessorId),
+ EFI_SMM_SAVE_STATE_REGISTER_PROCESSOR_ID,
+ CpuIndex,
+ &ProcessorId
+ );
+ //
+ // If the processor is in SMM at the time the SMI occurred,
+ // it will return success. Otherwise, EFI_NOT_FOUND is returned.
+ //
+ if (EFI_ERROR (Status)) {
+ return FALSE;
+ }
+ }
+
+ return TRUE;
+}
+
+/**
+ Check if a save and restore of the SPI controller state is necessary
+
+ @retval TRUE It's necessary to save and restore SPI controller state
+ @retval FALSE It's not necessary to save and restore SPI controller state
+**/
+BOOLEAN
+IsSpiControllerSaveRestoreEnabled (
+ VOID
+ )
+{
+ return mBootServiceExited;
+}
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/Smm/SpiSmm.inf b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/Smm/SpiSmm.inf
new file mode 100644
index 0000000000..78913423fb
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/Smm/SpiSmm.inf
@@ -0,0 +1,46 @@
+## @file
+# Component description file for the SPI SMM driver.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+
+[Defines]
+INF_VERSION = 0x00010017
+BASE_NAME = SpiSmm
+FILE_GUID = 27F4917B-A707-4aad-9676-26DF168CBF0D
+VERSION_STRING = 1.0
+MODULE_TYPE = DXE_SMM_DRIVER
+PI_SPECIFICATION_VERSION = 1.10
+ENTRY_POINT = InstallPchSpi
+
+
+[LibraryClasses]
+DebugLib
+IoLib
+UefiDriverEntryPoint
+UefiBootServicesTableLib
+BaseLib
+SmmServicesTableLib
+SpiCommonLib
+PchPciBdfLib
+
+[Packages]
+MdePkg/MdePkg.dec
+AlderlakeSiliconPkg/SiPkg.dec
+
+
+[Sources]
+Spi.c
+
+
+[Protocols]
+gPchSmmSpiProtocolGuid ## PRODUCES
+gEfiSmmCpuProtocolGuid ## CONSUMES
+gEdkiiSmmExitBootServicesProtocolGuid ## CONSUMES
+
+
+[Depex]
+gEfiSmmBase2ProtocolGuid AND # This is for SmmServicesTableLib
+gEfiSmmCpuProtocolGuid
--
2.36.1.windows.1
-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#108722): https://edk2.groups.io/g/devel/message/108722
Mute This Topic: https://groups.io/mt/101373948/7686176
Group Owner: devel+owner@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [rebecca@openfw.io]
-=-=-=-=-=-=-=-=-=-=-=-
^ permalink raw reply related [flat|nested] 41+ messages in thread
* Re: [edk2-devel] [PATCH v2 05/10] AlderlakeSiliconPkg/Include: Add ConfigBlock headers
2023-09-15 5:42 ` Chaganty, Rangasai V
@ 2023-09-15 13:28 ` Chuang, Rosen
0 siblings, 0 replies; 41+ messages in thread
From: Chuang, Rosen @ 2023-09-15 13:28 UTC (permalink / raw)
To: Chaganty, Rangasai V, Kasbekar, Saloni, devel@edk2.groups.io
Cc: Desimone, Nathaniel L
Reviewed-by: Rosen Chuang <rosen.chuang@intel.com>
-----Original Message-----
From: Chaganty, Rangasai V <rangasai.v.chaganty@intel.com>
Sent: Friday, September 15, 2023 1:43 PM
To: Kasbekar, Saloni <saloni.kasbekar@intel.com>; devel@edk2.groups.io
Cc: Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>; Chuang, Rosen <rosen.chuang@intel.com>
Subject: RE: [PATCH v2 05/10] AlderlakeSiliconPkg/Include: Add ConfigBlock headers
Reviewed-by: Sai Chaganty <rangasai.v.chaganty@intel.com>
-----Original Message-----
From: Kasbekar, Saloni <saloni.kasbekar@intel.com>
Sent: Thursday, September 14, 2023 9:46 PM
To: devel@edk2.groups.io
Cc: Kasbekar, Saloni <saloni.kasbekar@intel.com>; Chaganty, Rangasai V <rangasai.v.chaganty@intel.com>; Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>; Chuang, Rosen <rosen.chuang@intel.com>
Subject: [PATCH v2 05/10] AlderlakeSiliconPkg/Include: Add ConfigBlock headers
Adds the header includes for the ConfigBlocks
Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Rosen Chuang <rosen.chuang@intel.com>
Signed-off-by: Saloni Kasbekar <saloni.kasbekar@intel.com>
---
.../CpuPcieRp/Gen3/CpuPcieConfigGen3.h | 48 ++
.../CpuPcieRp/Gen4/CpuPcieConfig.h | 240 ++++++++
.../Include/ConfigBlock/Espi/LpcConfig.h | 38 ++
.../Include/ConfigBlock/Fivr/FivrConfig.h | 183 ++++++
.../Include/ConfigBlock/Gpio/GpioDevConfig.h | 37 ++
.../Graphics/Gen12/GraphicsConfig.h | 212 +++++++
.../HostBridge/Ver1/HostBridgeConfig.h | 58 ++
.../ConfigBlock/Itss/InterruptConfig.h | 38 ++
.../ConfigBlock/Memory/Ver2/MemoryConfig.h | 551 ++++++++++++++++++
.../Include/ConfigBlock/PchDmi/PchDmiConfig.h | 65 +++
.../PcieRp/PchPcieRp/PchPcieRpConfig.h | 180 ++++++
.../Include/ConfigBlock/PcieRp/PcieConfig.h | 408 +++++++++++++
.../ConfigBlock/PcieRp/PciePreMemConfig.h | 36 ++
.../Include/ConfigBlock/Pmc/AdrConfig.h | 76 +++
.../Include/ConfigBlock/Pmc/PmConfig.h | 86 +++
.../Include/ConfigBlock/Rtc/RtcConfig.h | 37 ++
.../ConfigBlock/SerialIo/SerialIoConfig.h | 33 ++
.../Include/ConfigBlock/SiConfig.h | 105 ++++
.../Include/ConfigBlock/SiPreMemConfig.h | 63 ++
.../Include/ConfigBlock/Smbus/SmbusConfig.h | 49 ++
.../ConfigBlock/Spi/FlashProtectionConfig.h | 54 ++
.../Include/ConfigBlock/Tcss/TcssPeiConfig.h | 71 +++
.../Include/ConfigBlock/Vmd/VmdPeiConfig.h | 60 ++
.../Include/ConfigBlock/Wdt/WatchDogConfig.h | 30 +
24 files changed, 2758 insertions(+)
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/CpuPcieRp/Gen3/CpuPcieConfigGen3.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/CpuPcieRp/Gen4/CpuPcieConfig.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Espi/LpcConfig.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Fivr/FivrConfig.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Gpio/GpioDevConfig.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Graphics/Gen12/GraphicsConfig.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/HostBridge/Ver1/HostBridgeConfig.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Itss/InterruptConfig.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Memory/Ver2/MemoryConfig.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/PchDmi/PchDmiConfig.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/PcieRp/PchPcieRp/PchPcieRpConfig.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/PcieRp/PcieConfig.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/PcieRp/PciePreMemConfig.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Pmc/AdrConfig.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Pmc/PmConfig.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Rtc/RtcConfig.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/SerialIo/SerialIoConfig.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/SiConfig.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/SiPreMemConfig.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Smbus/SmbusConfig.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Spi/FlashProtectionConfig.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Tcss/TcssPeiConfig.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Vmd/VmdPeiConfig.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Wdt/WatchDogConfig.h
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/CpuPcieRp/Gen3/CpuPcieConfigGen3.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/CpuPcieRp/Gen3/CpuPcieConfigGen3.h
new file mode 100644
index 0000000000..5b437c8311
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/CpuPcieRp/Gen3/CpuPcieConfigGen3.h
@@ -0,0 +1,48 @@
+/** @file
+Pcie root port policy
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _CPU_PCIE_CONFIG_GEN3_H_
+#define _CPU_PCIE_CONFIG_GEN3_H_
+
+#include <Library/GpioLib.h>
+#include <Library/CpuPcieInfoFruLib.h>
+#include <PcieConfig.h>
+#include <ConfigBlock.h>
+#include <Register/SaRegsHostBridge.h>
+
+#pragma pack(push, 1)
+
+
+#define L0_SET BIT0
+#define L1_SET BIT1
+
+
+///
+/// SA GPIO Data Structure
+///
+typedef struct {
+ GPIO_PAD GpioPad; ///< Offset 0: GPIO Pad
+ UINT8 Value; ///< Offset 4: GPIO Value
+ UINT8 Rsvd0[3]; ///< Offset 5: Reserved for 4 bytes alignment
+ UINT32 Active : 1; ///< Offset 8: 0=Active Low; 1=Active High
+ UINT32 RsvdBits0 : 31;
+} SA_GPIO_INFO_PCIE;
+
+///
+/// SA Board PEG GPIO Info
+///
+typedef struct {
+ SA_GPIO_INFO_PCIE SaPeg0ResetGpio; ///< Offset 0: PEG0 PERST# GPIO assigned, must be a PCH GPIO pin
+ SA_GPIO_INFO_PCIE SaPeg3ResetGpio; ///< Offset 12: PEG3 PERST# GPIO assigned, must be a PCH GPIO pin
+ BOOLEAN GpioSupport; ///< Offset 24: 1=Supported; 0=Not Supported
+ UINT8 Rsvd0[3]; ///< Offset 25: Reserved for 4 bytes alignment
+} PEG_GPIO_DATA;
+
+
+#pragma pack (pop)
+
+#endif // _CPU_PCIE_CONFIG_GEN3_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/CpuPcieRp/Gen4/CpuPcieConfig.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/CpuPcieRp/Gen4/CpuPcieConfig.h
new file mode 100644
index 0000000000..999748d711
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/CpuPcieRp/Gen4/CpuPcieConfig.h
@@ -0,0 +1,240 @@
+/** @file
+ Pcie root port policy
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _CPU_PCIE_CONFIG_H_
+#define _CPU_PCIE_CONFIG_H_
+
+#include <Library/GpioLib.h>
+#include <Library/CpuPcieInfoFruLib.h>
+#include <PcieConfig.h>
+#include <ConfigBlock.h>
+#include <Register/SaRegsHostBridge.h>
+
+#pragma pack(push, 1)
+
+#define CPU_PCIE_RP_PREMEM_CONFIG_REVISION 1
+
+/**
+ Making any setup structure change after code frozen
+ will need to maintain backward compatibility, bump up
+ structure revision and update below history table\n
+ <b>Revision 1</b>: - Initial version.
+**/
+
+#define CPU_PCIE_CONFIG_REVISION 10
+
+#define L0_SET BIT0
+#define L1_SET BIT1
+
+/**
+ CPU PCIe Root Port Pre-Memory Configuration
+ Contains Root Port settings and capabilities
+ <b>Revision 1</b>: - Initial version.
+ <b>Revision 2</b>: - Adding Dekel Suqelch Workaround Setup Variable
+ <b>Revision 3</b>: - Deprecate Dekel Suqelch Workaround Setup Variable
+ <b>Revision 4</b>: - Adding New FOM Setup Variable
+ <b>Revision 5</b>: - Add CdrRelock Policy to CPU_PCIE_RP_PREMEM_CONFIG.
+**/
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Config Block Header
+ /**
+ Root Port enabling mask.
+ Bit0 presents RP1, Bit1 presents RP2, and so on.
+ 0: Disable; <b>1: Enable</b>.
+ **/
+ UINT32 RpEnabledMask;
+ /**
+ Assertion on Link Down GPIOs
+ - <b>Disabled</b> (0x0) : Disable assertion on Link Down GPIOs(Default)
+ - Enabled (0x1) : Enable assertion on Link Down GPIOs
+ **/
+ UINT8 LinkDownGpios;
+ /**
+ Enable ClockReq Messaging
+ - <b>Disabled</> (0x0) : Disable ClockReq Messaging(Default)
+ - Enabled (0x1) : Enable ClockReq Messaging
+ **/
+ UINT8 ClkReqMsgEnable;
+ /**
+ Dekel Recipe Workaround
+ <b>2</b>
+ 1=Minimal, 9=Maximum,
+ **/
+ UINT8 DekelSquelchWa; // Deprecated variable
+ UINT8 Rsvd0[1];
+ /**
+ Determines each PCIE Port speed capability.
+ <b>0: Auto</b>; 1: Gen1; 2: Gen2; 3: Gen3; 4: Gen4 (see: CPU_PCIE_SPEED)
+ **/
+ UINT8 PcieSpeed[CPU_PCIE_MAX_ROOT_PORTS];
+
+ /**
+ Enable ClockReq Messaging Policy is for all Rootports
+ - <b>Disabled</> (0x0) : Disable ClockReq Messaging(Default)
+ - Enabled (0x1) : Enable ClockReq Messaging
+ **/
+ UINT8 ClkReqMsgEnableRp[CPU_PCIE_MAX_ROOT_PORTS];
+ /**
+ To Enable/Disable New FOM
+ <b>0: Disable</b>; 1: Enable
+ **/
+ UINT8 NewFom[CPU_PCIE_MAX_ROOT_PORTS];
+ /**
+ To Enable/Disable CDR Relock
+ <b>0: Disable</b>; 1: Enable
+ **/
+ UINT8 CdrRelock[CPU_PCIE_MAX_ROOT_PORTS];
+} CPU_PCIE_RP_PREMEM_CONFIG;
+
+/**
+ Represent lane specific PCIe Gen3 equalization parameters.
+**/
+typedef struct {
+ UINT8 Cm; ///< Coefficient C-1
+ UINT8 Cp; ///< Coefficient C+1
+ UINT8 PegGen3RootPortPreset; ///< <b>(Test)</b> Used for programming PEG Gen3 preset values per lane. Range: 0-9, 8 is default for each lane
+ UINT8 PegGen3EndPointPreset; ///< <b>(Test)</b> Used for programming PEG Gen3 preset values per lane. Range: 0-9, 7 is default for each lane
+ UINT8 PegGen3EndPointHint; ///< <b>(Test)</b> Hint value per lane for the PEG Gen3 End Point. Range: 0-6, 2 is default for each lane
+ UINT8 PegGen4RootPortPreset; ///< <b>(Test)</b> Used for programming PEG Gen4 preset values per lane. Range: 0-9, 8 is default for each lane
+ UINT8 PegGen4EndPointPreset; ///< <b>(Test)</b> Used for programming PEG Gen4 preset values per lane. Range: 0-9, 7 is default for each lane
+ UINT8 PegGen4EndPointHint; ///< <b>(Test)</b> Hint value per lane for the PEG Gen4 End Point. Range: 0-6, 2 is default for each lane
+} CPU_PCIE_EQ_LANE_PARAM;
+
+/**
+ The CPU_PCI_ROOT_PORT_CONFIG describe the feature and capability of each CPU PCIe root port.
+**/
+typedef struct {
+
+ UINT32 ExtSync : 1; ///< Indicate whether the extended synch is enabled. <b>0: Disable</b>; 1: Enable.
+ UINT32 MultiVcEnabled : 1; ///< Multiple Virtual Channel. 0: Disable; <b>1: Enable</b>
+ UINT32 RsvdBits0 : 30; ///< Reserved bits
+ /**
+ PCIe Gen4 Equalization Method
+ - HwEq (0x1) : Hardware Equalization (Default)
+ - StaticEq (0x2) : Static Equalization
+ **/
+ UINT8 Gen4EqPh3Method;
+ UINT8 FomsCp; ///< FOM Score Board Control Policy
+ UINT8 RsvdBytes0[2]; ///< Reserved bytes
+
+ //
+ // Gen3 Equalization settings
+ //
+ UINT32 Gen3Uptp : 4; ///< <b>(Test)</b> Upstream Port Transmitter Preset used during Gen3 Link Equalization. Used for all lanes. Default is <b>7</b>.
+ UINT32 Gen3Dptp : 4; ///< <b>(Test)</b> Downstream Port Transmiter Preset used during Gen3 Link Equalization. Used for all lanes. Default is <b>7</b>.
+ //
+ // Gen4 Equalization settings
+ //
+ UINT32 Gen4Uptp : 4; ///< <b>(Test)</b> Upstream Port Transmitter Preset used during Gen4 Link Equalization. Used for all lanes. Default is <b>7</b>.
+ UINT32 Gen4Dptp : 4; ///< <b>(Test)</b> Downstream Port Transmiter Preset used during Gen4 Link Equalization. Used for all lanes. Default is <b>7</b>.
+ //
+ // Gen5 Equalization settings
+ //
+ UINT32 Gen5Uptp : 4; ///< <b>(Test)</b> Upstream Port Transmitter Preset used during Gen5 Link Equalization. Used for all lanes. Default is <b>5</b>.
+ UINT32 Gen5Dptp : 4; ///< <b>(Test)</b> Downstream Port Transmiter Preset used during Gen5 Link Equalization. Used for all lanes. Default is <b>7</b>.
+ UINT32 RsvdBits1 : 8; ///< Reserved Bits
+
+ PCIE_ROOT_PORT_COMMON_CONFIG PcieRpCommonConfig; ///< <b>(Test)</b> Includes policies which are common to both SA and PCH RootPort
+
+} CPU_PCIE_ROOT_PORT_CONFIG;
+
+typedef struct {
+ UINT8 PcieGen3PresetCoeffSelection; ///<Gen3 Preset or Coefficient Selection
+ UINT8 PcieGen4PresetCoeffSelection; ///<Gen4 Preset or Coefficient Selection
+ UINT8 PcieGen5PresetCoeffSelection; ///<Gen5 Preset or Coefficient Selection
+ UINT8 Func0LinkDisable; ///< Disable Func0 Port
+} CPU_PCIE_ROOT_PORT_CONFIG2;
+
+/**
+ The CPU_PCIE_CONFIG block describes the expected configuration of the CPU PCI Express controllers
+ <b>Revision 1< / b>:
+ -Initial version.
+ <b>Revision 2</b>:
+ - SlotSelection policy added
+ <b>Revision 3</b>
+ - Deprecate PegGen3ProgramStaticEq and PegGen4ProgramStaticEq
+ <b>Revision 4</b>:
+ - Deprecating SetSecuredRegisterLock
+ <b>Revision 5</b>:
+ - Moved ClockGating policy to PCIE_ROOT_PORT_COMMON_CONFIG
+ - Moved PowerGating policy to PCIE_ROOT_PORT_COMMON_CONFIG
+ - Deprecate VcEnabled policy
+ <b>Revision 7</b>:
+ - Deprecating Gen3PresetCoeffSelection and Gen4PresetCoeffSelection
+ <b>Revision 8</b>:
+ - Added Serl policy
+ <b>Revision 9</b>:
+ - Align revision with CPU_PCIE_CONFIG_REVISION value
+ <b>Revision 10</b>:
+ - Deprecate EqPh3LaneParam.Cm and EqPh3LaneParam.Cp
+**/
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Config Block Header
+ ///
+ /// These members describe the configuration of each SA PCIe root port.
+ ///
+ CPU_PCIE_ROOT_PORT_CONFIG RootPort[CPU_PCIE_MAX_ROOT_PORTS];
+ ///
+ /// Gen3 Equalization settings for physical PCIe lane, index 0 represents PCIe lane 1, etc.
+ /// Corresponding entries are used when root port EqPh3Method is PchPcieEqStaticCoeff (default).
+ ///
+ CPU_PCIE_EQ_LANE_PARAM EqPh3LaneParam[SA_PEG_MAX_LANE]; //@ Deprecated Policy
+ ///
+ /// List of coefficients used during equalization (applicable to both software and hardware EQ)
+ ///
+ PCIE_EQ_PARAM HwEqGen4CoeffList[PCIE_HWEQ_COEFFS_MAX]; //@ Deprecated Policy
+
+ PCIE_COMMON_CONFIG PcieCommonConfig; /// < <b>(Test)</b> Includes policies which are common to both SA and PCH PCIe
+
+ UINT32 FiaProgramming : 1; /// < Skip Fia Configuration and lock if enable
+ // Deprecated Policy
+ /**
+ <b>(Test)</b> Program PEG Gen3 EQ Phase1 Static Presets
+ - Disabled (0x0) : Disable EQ Phase1 Static Presets Programming
+ - <b>Enabled</b> (0x1) : Enable EQ Phase1 Static Presets Programming (Default)
+ **/
+ UINT32 PegGen3ProgramStaticEq : 1;
+
+ // Deprecated Policy
+ /**
+ <b>(Test)</b> Program PEG Gen4 EQ Phase1 Static Presets
+ - Disabled (0x0) : Disable EQ Phase1 Static Presets Programming
+ - <b>Enabled</b> (0x1) : Enable EQ Phase1 Static Presets Programming (Default)
+ **/
+ UINT32 PegGen4ProgramStaticEq : 1;
+ /**
+ <b>(Test)</b> Cpu Pcie Secure Register Lock
+ - Disabled (0x0)
+ - <b>Enabled</b> (0x1)
+ **/
+ UINT32 SetSecuredRegisterLock : 1; // Deprecated Policy
+ ///
+ /// This member allows to select between the PCI Express M2 or CEMx4 slot <b>1: PCIe M2</b>; 0: CEMx4 slot.
+ ///
+ UINT32 SlotSelection : 1;
+
+ UINT32 Serl : 1;
+
+ UINT32 RsvdBits0 : 26;
+
+ /**
+ PCIe device override table
+ The PCIe device table is being used to override PCIe device ASPM settings.
+ This is a pointer points to a 32bit address. And it's only used in PostMem phase.
+ Please refer to PCIE_DEVICE_OVERRIDE structure for the table.
+ Last entry VendorId must be 0.
+ The prototype of this policy is:
+ PCIE_DEVICE_OVERRIDE *PcieDeviceOverrideTablePtr;
+ **/
+ UINT32 PcieDeviceOverrideTablePtr;
+ CPU_PCIE_ROOT_PORT_CONFIG2 RootPort2[CPU_PCIE_MAX_ROOT_PORTS];
+ PCIE_COMMON_CONFIG2 PcieCommonConfig2;
+ } CPU_PCIE_CONFIG;
+
+#pragma pack (pop)
+
+#endif // _CPU_PCIE_CONFIG_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Espi/LpcConfig.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Espi/LpcConfig.h
new file mode 100644
index 0000000000..324facde78
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Espi/LpcConfig.h
@@ -0,0 +1,38 @@
+/** @file
+ Lpc policy
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _LPC_CONFIG_H_
+#define _LPC_CONFIG_H_
+
+#define PCH_LPC_PREMEM_CONFIG_REVISION 1
+extern EFI_GUID gLpcPreMemConfigGuid;
+
+#pragma pack (push,1)
+
+/**
+ This structure contains the policies which are related to LPC.
+**/
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Config Block Header
+ /**
+ Enhance the port 8xh decoding.
+ Original LPC only decodes one byte of port 80h, with this enhancement LPC can decode word or dword of port 80h-83h.
+ @note: this will occupy one LPC generic IO range register. While this is enabled, read from port 80h always return 0x00.
+ 0: Disable, <b>1: Enable</b>
+ **/
+ UINT32 EnhancePort8xhDecoding : 1;
+ /**
+ Hardware Autonomous Enable.
+ When enabled, LPC will automatically engage power gating when it has reached its idle condition.
+ 0: Disable, <b>1: Enable</b>
+ **/
+ UINT32 LpcPmHAE : 1;
+ UINT32 RsvdBits : 30; ///< Reserved bits
+} PCH_LPC_PREMEM_CONFIG;
+
+#pragma pack (pop)
+
+#endif // _LPC_CONFIG_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Fivr/FivrConfig.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Fivr/FivrConfig.h
new file mode 100644
index 0000000000..501e00c0e1
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Fivr/FivrConfig.h
@@ -0,0 +1,183 @@
+/** @file
+ PCH FIVR policy
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _FIVR_CONFIG_H_
+#define _FIVR_CONFIG_H_
+
+/**
+ <b>Revision 1</b>: - Initial version.
+**/
+#define PCH_FIVR_CONFIG_REVISION 1
+extern EFI_GUID gFivrConfigGuid;
+
+#pragma pack (push,1)
+
+/**
+ Rail support in S0ix and Sx
+ Settings other than FivrRailDisabled can be OR'ed
+**/
+typedef enum {
+ FivrRailDisabled = 0,
+ FivrRailInS0i1S0i2 = BIT0,
+ FivrRailInS0i3 = BIT1,
+ FivrRailInS3 = BIT2,
+ FivrRailInS4 = BIT3,
+ FivrRailInS5 = BIT4,
+ FivrRailInS0ix = FivrRailInS0i1S0i2 | FivrRailInS0i3,
+ FivrRailInSx = FivrRailInS3 | FivrRailInS4 | FivrRailInS5,
+ FivrRailAlwaysOn = FivrRailInS0ix | FivrRailInSx
+} FIVR_RAIL_SX_STATE;
+
+typedef enum {
+ FivrRetentionActive = BIT0,
+ FivrNormActive = BIT1,
+ FivrMinActive = BIT2,
+ FivrMinRetention = BIT3
+} FIVR_RAIL_SUPPORTED_VOLTAGE;
+
+/**
+ Structure for V1p05/Vnn VR rail configuration
+**/
+typedef struct {
+ /**
+ Mask to enable the usage of external VR rail in specific S0ix or Sx states
+ Use values from FIVR_RAIL_SX_STATE
+ The default is <b>FivrRailDisabled</b>.
+ **/
+ UINT32 EnabledStates : 6;
+
+ /**
+ VR rail voltage value that will be used in S0i2/S0i3 states.
+ This value is given in 2.5mV increments (0=0mV, 1=2.5mV, 2=5mV...)
+ The default for Vnn is set to <b>420 - 1050 mV</b>.
+ **/
+ UINT32 Voltage : 11;
+ /**
+ @deprecated
+ THIS POLICY IS DEPRECATED, PLEASE USE IccMaximum INSTEAD
+ VR rail Icc Max Value
+ Granularity of this setting is 1mA and maximal possible value is 500mA
+ The default is <b> 0mA </b>.
+ **/
+ UINT32 IccMax : 8;
+ /**
+ UINT32 Alignement
+ **/
+ UINT32 RsvdBits1 : 7;
+ /**
+ This register holds the control hold off values to be used when
+ changing the rail control for external bypass value in us
+ **/
+ UINT32 CtrlRampTmr : 8;
+
+ /**
+ Mask to set the supported configuration in VR rail.
+ Use values from FIVR_RAIL_SUPPORTED_VOLTAGE
+ **/
+ UINT32 SupportedVoltageStates : 4;
+
+ /**
+ VR rail Icc Maximum Value
+ Granularity of this setting is 1mA and maximal possible value is 500mA
+ The default is <b> 0mA </b>.
+ **/
+ UINT32 IccMaximum : 16;
+ /**
+ UINT32 Alignment
+ **/
+ UINT32 RsvdBits2 : 4;
+
+} FIVR_EXT_RAIL_CONFIG;
+
+
+/**
+ Structure for VCCIN_AUX voltage rail configuration
+**/
+typedef struct {
+ /**
+ Transition time in microseconds from Low Current Mode Voltage to High Current Mode Voltage.
+ Voltage transition time required by motherboard voltage regulator when PCH changes
+ the VCCIN_AUX regulator set point from the low current mode voltage and high current mode voltage.
+ This field has 1us resolution.
+ When value is 0 PCH will not transition VCCIN_AUX to low current mode voltage.
+ The default is <b> 0xC </b>.
+ **/
+ UINT8 LowToHighCurModeVolTranTime;
+
+ /**
+ Transition time in microseconds from Retention Mode Voltage to High Current Mode Voltage.
+ Voltage transition time required by motherboard voltage regulator when PCH changes
+ the VCCIN_AUX regulator set point from the retention mode voltage to high current mode voltage.
+ This field has 1us resolution.
+ When value is 0 PCH will not transition VCCIN_AUX to retention voltage.
+ The default is <b> 0x36 </b>.
+ **/
+ UINT8 RetToHighCurModeVolTranTime;
+
+ /**
+ Transition time in microseconds from Retention Mode Voltage to Low Current Mode Voltage.
+ Voltage transition time required by motherboard voltage regulator when PCH changes
+ the VCCIN_AUX regulator set point from the retention mode voltage to low current mode voltage.
+ This field has 1us resolution.
+ When value is 0 PCH will not transition VCCIN_AUX to retention voltage.
+ The default is <b> 0x2B </b>.
+ **/
+ UINT8 RetToLowCurModeVolTranTime;
+ UINT8 RsvdByte1;
+ /**
+ Transition time in microseconds from Off (0V) to High Current Mode Voltage.
+ Voltage transition time required by motherboard voltage regulator when PCH changes
+ the VCCIN_AUX regulator set point from 0V to the high current mode voltage.
+ This field has 1us resolution.
+ 0 = Transition to 0V is disabled
+ Setting this field to 0 sets VCCIN_AUX as a fixed rail that stays on
+ in all S0 & Sx power states after initial start up on G3 exit
+ The default is <b> 0x96 </b>.
+ **/
+ UINT32 OffToHighCurModeVolTranTime : 11;
+ UINT32 RsvdBits1 : 21;
+} FIVR_VCCIN_AUX_CONFIG;
+
+/**
+ The PCH_FIVR_CONFIG block describes FIVR settings.
+**/
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Config Block Header
+ /**
+ External V1P05 VR rail configuration.
+ **/
+ FIVR_EXT_RAIL_CONFIG ExtV1p05Rail;
+ /**
+ External Vnn VR rail configuration.
+ **/
+ FIVR_EXT_RAIL_CONFIG ExtVnnRail;
+ /**
+ Additional External Vnn VR rail configuration that will get applied
+ in Sx entry SMI callback. Required only if External Vnn VR
+ needs different settings for Sx than those specified in ExtVnnRail.
+ **/
+ FIVR_EXT_RAIL_CONFIG ExtVnnRailSx;
+ /**
+ VCCIN_AUX voltage rail configuration.
+ **/
+ FIVR_VCCIN_AUX_CONFIG VccinAux;
+
+ /**
+ Enable/Disable FIVR Dynamic Power Management
+ Default is <b> 1 </b>.
+ **/
+ UINT32 FivrDynPm : 1;
+ /**
+ Enable/Disable Bypass of FIVR configuration
+ Default is <b> 0 </b>.
+ **/
+ UINT32 BypassFivrConfig : 1;
+ UINT32 RsvdBits2 : 30;
+} PCH_FIVR_CONFIG;
+
+#pragma pack (pop)
+
+#endif // _FIVR_CONFIG_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Gpio/GpioDevConfig.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Gpio/GpioDevConfig.h
new file mode 100644
index 0000000000..5652df0259
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Gpio/GpioDevConfig.h
@@ -0,0 +1,37 @@
+/** @file
+ GPIO device policy
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _GPIO_DEV_CONFIG_H_
+#define _GPIO_DEV_CONFIG_H_
+
+extern EFI_GUID gGpioDxeConfigGuid;
+
+#define GPIO_DXE_CONFIG_REVISION 1
+
+#pragma pack (push,1)
+
+/**
+ This structure contains the DXE policies which are related to GPIO device.
+
+ <b>Revision 1:</b>
+ - Inital version.
+**/
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Config Block Header
+ /**
+ If GPIO ACPI device is not used by OS it can be hidden. In such case
+ no other device exposed to the system can reference GPIO device in one
+ of its resources through GpioIo(..) or GpioInt(..) ACPI descriptors.
+ <b>0: Disable</b>; 1: Enable
+ **/
+ UINT32 HideGpioAcpiDevice : 1;
+ UINT32 RsvdBits : 31; ///< Reserved bits
+
+} GPIO_DXE_CONFIG;
+
+#pragma pack (pop)
+
+#endif // _GPIO_DEV_CONFIG_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Graphics/Gen12/GraphicsConfig.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Graphics/Gen12/GraphicsConfig.h
new file mode 100644
index 0000000000..c6a2f36612
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Graphics/Gen12/GraphicsConfig.h
@@ -0,0 +1,212 @@
+/** @file
+ Policy definition for Internal Graphics Config Block.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _GRAPHICS_CONFIG_H_
+#define _GRAPHICS_CONFIG_H_
+#pragma pack(push, 1)
+
+#define GRAPHICS_DXE_CONFIG_REVISION 2
+
+#define MAX_BCLM_ENTRIES 20
+
+
+//
+// DDI defines
+//
+typedef enum {
+ DdiDisable = 0x00,
+ DdiDdcEnable = 0x01,
+} DDI_DDC_TBT_VAL;
+
+typedef enum {
+ DdiHpdDisable = 0x00,
+ DdiHpdEnable = 0x01,
+} DDI_HPD_VAL;
+
+typedef enum {
+ DdiPortDisabled = 0x00,
+ DdiPortEdp = 0x01,
+ DdiPortMipiDsi = 0x02,
+} DDI_PORT_SETTINGS;
+
+/**
+ This structure configures the Native GPIOs for DDI port per VBT settings.
+**/
+typedef struct {
+ UINT8 DdiPortAConfig; /// The Configuration of DDI port A, this settings must match VBT's settings. DdiPortDisabled - No LFP is connected on DdiPortA, <b>DdiPortEdp - Set DdiPortA to eDP</b>, DdiPortMipiDsi - Set DdiPortA to MIPI DSI
+ UINT8 DdiPortBConfig; /// The Configuration of DDI port B, this settings must match VBT's settings. DdiPortDisabled - No LFP is connected on DdiPortB, <b>DdiPortEdp - Set DdiPortB to eDP</b>, DdiPortMipiDsi - Set DdiPortB to MIPI DSI
+ UINT8 DdiPortAHpd; /// The HPD setting of DDI Port A, this settings must match VBT's settings. <b>DdiHpdDisable - Disable HPD</b>, DdiHpdEnable - Enable HPD
+ UINT8 DdiPortBHpd; /// The HPD setting of DDI Port B, this settings must match VBT's settings. DdiHpdDisable - Disable HPD, <b>DdiHpdEnable - Enable HPD</b>
+ UINT8 DdiPortCHpd; /// The HPD setting of DDI Port C, this settings must match VBT's settings. <b>DdiHpdDisable - Disable HPD</b>, DdiHpdEnable - Enable HPD
+ UINT8 DdiPort1Hpd; /// The HPD setting of DDI Port 1, this settings must match VBT's settings. <b>DdiHpdDisable - Disable HPD</b>, DdiHpdEnable - Enable HPD
+ UINT8 DdiPort2Hpd; /// The HPD setting of DDI Port 2, this settings must match VBT's settings. <b>DdiHpdDisable - Disable HPD</b>, DdiHpdEnable - Enable HPD
+ UINT8 DdiPort3Hpd; /// The HPD setting of DDI Port 3, this settings must match VBT's settings. <b>DdiHpdDisable - Disable HPD</b>, DdiHpdEnable - Enable HPD
+ UINT8 DdiPort4Hpd; /// The HPD setting of DDI Port 4, this settings must match VBT's settings. <b>DdiHpdDisable - Disable HPD</b>, DdiHpdEnable - Enable HPD
+ UINT8 DdiPortADdc; /// The DDC setting of DDI Port A, this settings must match VBT's settings. <b>DdiDisable - Disable DDC</b>, DdiDdcEnable - Enable DDC
+ UINT8 DdiPortBDdc; /// The DDC setting of DDI Port B, this settings must match VBT's settings. DdiDisable - Disable DDC, <b>DdiDdcEnable - Enable DDC </b>
+ UINT8 DdiPortCDdc; /// The DDC setting of DDI Port C, this settings must match VBT's settings. <b>DdiDisable - Disable DDC</b>, DdiDdcEnable - Enable DDC
+ UINT8 DdiPort1Ddc; /// The DDC setting of DDI Port 1, this settings must match VBT's settings. <b>DdiDisable - Disable DDC</b>, DdiDdcEnable - Enable DDC
+ UINT8 DdiPort2Ddc; /// The DDC setting of DDI Port 2, this settings must match VBT's settings. <b>DdiDisable - Disable DDC</b>, DdiDdcEnable - Enable DDC
+ UINT8 DdiPort3Ddc; /// The DDC setting of DDI Port 3, this settings must match VBT's settings. <b>DdiDisable - Disable DDC</b>, DdiDdcEnable - Enable DDC
+ UINT8 DdiPort4Ddc; /// The DDC setting of DDI Port 4, this settings must match VBT's settings. <b>DdiDisable - Disable DDC</b>, DdiDdcEnable - Enable DDC
+} DDI_CONFIGURATION;
+
+/**
+ This Configuration block is to configure GT related PreMem data/variables.\n
+ <b>Revision 1</b>:
+ - Initial version.
+**/
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Block Header
+ /**
+ Offset 28
+ Selection of the primary display device: 0=iGFX, 1=PEG, 2=PCIe Graphics on PCH, <b>3=AUTO</b>, 4=Switchable Graphics\n
+ When AUTO mode selected, the priority of display devices is: PCIe Graphics on PCH > PEG > iGFX
+ **/
+ UINT8 PrimaryDisplay;
+ /**
+ Offset 29
+ Intel Gfx Support. It controls enabling/disabling iGfx device.
+ When AUTO mode selected, iGFX will be turned off when external graphics detected.
+ If FALSE, all other polices can be ignored.
+ <b>2 = AUTO</b>;
+ 0 = FALSE;
+ 1 = TRUE.
+ **/
+ UINT8 InternalGraphics;
+ /**
+ Offset 30
+ Pre-allocated memory for iGFX\n
+ 0 = 0MB,1 or 247 = 32MB,\n
+ 2 = 64MB,\n
+ 240 = 4MB, 241 = 8MB,\n
+ 242 = 12MB, 243 = 16MB,\n
+ 244 = 20MB, 245 = 24MB,\n
+ 246 = 28MB, 248 = 36MB,\n
+ 249 = 40MB, 250 = 44MB,\n
+ 251 = 48MB, 252 = 52MB,\n
+ 253 = 56MB,<b> 254 = 60MB</b>,\n
+ <b>Note: enlarging pre-allocated memory for iGFX may need to reduce MmioSize because of 4GB boundary limitation</b>
+ **/
+ UINT16 IgdDvmt50PreAlloc;
+ UINT8 PanelPowerEnable; ///< Offset 32 :<b>(Test)</b> Control for enabling/disabling VDD force bit (Required only for early enabling of eDP panel): 0=FALSE, <b>1=TRUE</b>
+ UINT8 ApertureSize; ///< Offset 33 :Graphics aperture size (256MB is the recommended size as per BWG) : 0=128MB, <b>1=256MB</b>, 3=512MB, 7=1024MB, 15=2048MB.
+ UINT8 GtPsmiSupport; ///< Offset 34 :PSMI support On/Off: <b>0=FALSE</b>, 1=TRUE
+ UINT8 PsmiRegionSize; ///< Offset 35 :Psmi region size: <b>0=32MB</b>, 1=288MB, 2=544MB, 3=800MB, 4=1056MB
+ UINT8 DismSize; ///< Offset 36 :DiSM Size for 2LM Sku: <b>0=0GB</b>, 1=1GB, 2=2GB, 3=3GB, 4=4GB, 5=5GB, 6=6GB, 7=7GB
+ UINT8 DfdRestoreEnable; ///< Offset 37 :(Deprecated) Display memory map programming for DFD Restore <b>0- Disable</b>, 1- Enable
+ UINT16 GttSize; ///< Offset 38 :Selection of iGFX GTT Memory size: 1=2MB, 2=4MB, <b>3=8MB</b>
+ /**
+ Offset 40
+ Temp Address of System Agent GTTMMADR: Default is <b>0xAF000000</b>
+ **/
+ UINT32 GttMmAdr;
+ UINT32 GmAdr; ///< Offset 44 Obsolete not to be used, use GmAdr64
+ DDI_CONFIGURATION DdiConfiguration; ///< Offset 48 DDI configuration, need to match with VBT settings.
+
+ UINT8 GtClosEnable; ///< Offset 50 Gt ClOS
+ UINT8 Rsvd0[7]; ///< Offset 51 Reserved for 4 bytes of alignment
+ /**
+ Offset 58
+ Temp Address of System Agent GMADR: Default is <b>0xB0000000</b>
+ **/
+ UINT64 GmAdr64;
+ UINT16 DeltaT12PowerCycleDelay; ///< Offset 66 Power Cycle Delay required for eDP as per VESA standard.0 - 0 ms, <b>0xFFFF - Auto calculate to max 500 ms<\b>
+ UINT8 DisplayAudioLink; ///< Offset 68 Enable/Disable Display Audio Links in Pre-OS.<b>0- Disable</b>, 1- Enable
+ UINT8 OemT12DelayOverride; ///< Offset 69 :Oem T12 Delay Override <b> Disable<\b>,Enable-Enable T12 Time.
+ UINT8 Rsvd2[4]; ///< Offset 70 Reserved for 4 bytes of alignment
+} GRAPHICS_PEI_PREMEM_CONFIG;
+
+/**
+ This configuration block is to configure IGD related variables used in PostMem PEI.
+ If Intel Gfx Device is not supported, all policies can be ignored.
+ <b>Revision 1</b>:
+ - Initial version.
+ <b>Revision 2</b>:
+ - Removed DfdRestoreEnable.
+ <b>Revision 3</b>:
+ - Removed DdiConfiguration.
+ <b>Revision 4</b>:
+ - Added new CdClock frequency
+ <b>Revision 5</b>:
+ - Added GT Chicket bits
+ <b>Revision 6</b>:
+ - Added LogoPixelHeight and LogoPixelWidth
+ <b>Revision 7</b>:
+ - Added SkipFspGop
+ <b>Revision 8</b>:
+ - Added VerticalResolution and HorizontalResolution
+
+**/
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Block Header
+ UINT8 RenderStandby; ///< Offset 28 :<b>(Test)</b> This field is used to enable or disable RC6 (Render Standby): 0=FALSE, <b>1=TRUE</b>
+ UINT8 PmSupport; ///< Offset 29 :<b>(Test)</b> Configure GT to use along with PM Support TRUE/FALSE: 0=FALSE, <b>1=TRUE</b>
+ /**
+ Offset 30
+ CdClock Frequency select\n
+ <b>0xFF = Auto. Max CdClock freq based on Reference Clk</b> \n
+ 0: 192 Mhz, 1: 307.2 Mhz, 2: 312 Mhz, 3: 324 Mhz, 4: 326.4 Mhz, 5: 552 Mhz, 6: 556.8 Mhz, 7: 648 Mhz, 8: 652.8 Mhz
+
+ **/
+ UINT16 CdClock;
+ UINT8 PeiGraphicsPeimInit; ///< Offset 32 : This policy is used to enable/disable Intel Gfx PEIM.<b>0- Disable</b>, 1- Enable
+ UINT8 CdynmaxClampEnable; ///< Offset 33 : This policy is used to enable/disable CDynmax Clamping Feature (CCF) <b>1- Enable</b>, 0- Disable
+ UINT16 GtFreqMax; ///< Offset 34 : <b>(Test)</b> Max GT frequency limited by user in multiples of 50MHz: Default value which indicates normal frequency is <b>0xFF</b>
+ UINT8 DisableTurboGt; ///< Offset 36 : This policy is used to enable/disable DisableTurboGt <b>0- Disable</b>, 1- Enable
+ UINT8 SkipCdClockInit; ///< Offset 37 : SKip full CD clock initialization. <b>0- Disable</b>, 1- Enable
+ UINT8 RC1pFreqEnable; ///< Offset 38 : This policy is used to enable/disable RC1p Frequency. <b>0- Disable</b>, 1- Enable
+ UINT8 PavpEnable; ///< Offset 39 :IGD PAVP TRUE/FALSE: 0=FALSE, <b>1=TRUE</b>
+ VOID* LogoPtr; ///< Offset 40 Address of Intel Gfx PEIM Logo to be displayed
+ UINT32 LogoSize; ///< Offset 44 Intel Gfx PEIM Logo Size
+ VOID* GraphicsConfigPtr; ///< Offset 48 Address of the Graphics Configuration Table
+ VOID* BltBufferAddress; ///< Offset 52 Address of Blt buffer for PEIM Logo use
+ UINT32 BltBufferSize; ///< Offset 56 The size for Blt Buffer, calculating by PixelWidth * PixelHeight * 4 bytes (the size of EFI_GRAPHICS_OUTPUT_BLT_PIXEL)
+ UINT8 ProgramGtChickenBits; ///< Offset 60 Program GT Chicket bits in GTTMMADR + 0xD00 BITS [3:1].
+ UINT8 SkipFspGop; ///< Offset 61 This policy is used to skip PEIM GOP in FSP.<b>0- Use FSP provided GOP driver</b>, 1- Skip FSP provided GOP driver
+ UINT8 Rsvd1[2]; ///< Offset 62 Reserved for 4 bytes alignment
+ UINT32 LogoPixelHeight; ///< Offset 64 Address of LogoPixelHeight for PEIM Logo use
+ UINT32 LogoPixelWidth; ///< Offset 68 Address of LogoPixelWidth for PEIM Logo use
+ UINT32 VerticalResolution; ///< Offset 72 Address of VerticalResolution for PEIM Logo use
+ UINT32 HorizontalResolution; ///< Offset 76 Address of HorizontalResolution for PEIM Logo use
+} GRAPHICS_PEI_CONFIG;
+
+/**
+ This configuration block is to configure IGD related variables used in DXE.
+ If Intel Gfx Device is not supported or disabled, all policies will be ignored.
+ The data elements should be initialized by a Platform Module.\n
+ <b>Revision 1</b>:
+ - Initial version.
+ <b>Revision 2</b>:
+ - Removed IgdDvmtMemSize.
+**/
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Offset 0-27: Config Block Header
+ UINT32 Size; ///< Offset 28 - 31: This field gives the size of the GOP VBT Data buffer
+ EFI_PHYSICAL_ADDRESS VbtAddress; ///< Offset 32 - 39: This field points to the GOP VBT data buffer
+ UINT8 PlatformConfig; ///< Offset 40: This field gives the Platform Configuration Information (0=Platform is S0ix Capable for ULT SKUs only, <b>1=Platform is not S0ix Capable</b>, 2=Force Platform is S0ix Capable for All SKUs)
+ UINT8 AlsEnable; ///< Offset 41: Ambient Light Sensor Enable: <b>0=Disable</b>, 2=Enable
+ UINT8 BacklightControlSupport; ///< Offset 42: Backlight Control Support: 0=PWM Inverted, <b>2=PWM Normal</b>
+ UINT8 IgdBootType; ///< Offset 43: IGD Boot Type CMOS option: <b>0=Default</b>, 0x01=CRT, 0x04=EFP, 0x08=LFP, 0x20=EFP3, 0x40=EFP2, 0x80=LFP2
+ UINT32 IuerStatusVal; ///< Offset 44 - 47: Offset 16 This field holds the current status of all the supported Ultrabook events (Intel(R) Ultrabook Event Status bits)
+ CHAR16 GopVersion[0x10]; ///< Offset 48 - 79:This field holds the GOP Driver Version. It is an Output Protocol and updated by the Silicon code
+ /**
+ Offset 80: IGD Panel Type CMOS option\n
+ <b>0=Default</b>, 1=640X480LVDS, 2=800X600LVDS, 3=1024X768LVDS, 4=1280X1024LVDS, 5=1400X1050LVDS1\n
+ 6=1400X1050LVDS2, 7=1600X1200LVDS, 8=1280X768LVDS, 9=1680X1050LVDS, 10=1920X1200LVDS, 13=1600X900LVDS\n
+ 14=1280X800LVDS, 15=1280X600LVDS, 16=2048X1536LVDS, 17=1366X768LVDS
+ **/
+ UINT8 IgdPanelType;
+ UINT8 IgdPanelScaling; ///< Offset 81: IGD Panel Scaling: <b>0=AUTO</b>, 1=OFF, 6=Force scaling
+ UINT8 IgdBlcConfig; ///< Offset 82: Backlight Control Support: 0=PWM Inverted, <b>2=PWM Normal</b>
+ UINT8 IgdDvmtMemSize; ///< Offset 83: @deprecated IGD DVMT Memory Size: 1=128MB, <b>2=256MB</b>, 3=MAX
+ UINT8 GfxTurboIMON; ///< Offset 84: IMON Current Value: 14=Minimal, <b>31=Maximum</b>
+ UINT8 Reserved[3]; ///< Offset 85: Reserved for DWORD alignment.
+ UINT16 BCLM[MAX_BCLM_ENTRIES]; ///< Offset 88: IGD Backlight Brightness Level Duty cycle Mapping Table.
+} GRAPHICS_DXE_CONFIG;
+#pragma pack(pop)
+
+#endif // _GRAPHICS_CONFIG_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/HostBridge/Ver1/HostBridgeConfig.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/HostBridge/Ver1/HostBridgeConfig.h
new file mode 100644
index 0000000000..11ef7b119c
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/HostBridge/Ver1/HostBridgeConfig.h
@@ -0,0 +1,58 @@
+/** @file
+ Configurations for HostBridge
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _HOST_BRIDGE_CONFIG_H_
+#define _HOST_BRIDGE_CONFIG_H_
+
+#include <ConfigBlock.h>
+
+
+extern EFI_GUID gHostBridgePeiPreMemConfigGuid;
+extern EFI_GUID gHostBridgePeiConfigGuid;
+
+#pragma pack (push,1)
+
+/**
+ This configuration block describes HostBridge settings in PreMem.\n
+ <b>Revision 1</b>:
+ - Initial version.
+**/
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Block Header
+ UINT32 MchBar; ///< Offset 28 Address of System Agent MCHBAR: <b>0xFEDC0000(TGL)/0xFEA80000(JSL)<b>
+ UINT32 DmiBar; ///< Offset 32 Address of System Agent DMIBAR: <b>0xFEDA0000</b>
+ UINT32 EpBar; ///< Offset 36 Address of System Agent EPBAR: <b>0xFEDA1000</b>
+ UINT32 GdxcBar; ///< Offset 40 Address of System Agent GDXCBAR: <b>0xFED84000</b>
+ UINT32 RegBar; ///< Offset 44 Address of System Agent REGBAR: <b>0xFB000000</b>
+ UINT32 EdramBar; ///< Offset 48 Address of System Agent EDRAMBAR: <b>0xFED80000</b>
+ /**
+ Offset 52 :
+ Size of reserved MMIO space for PCI devices\n
+ <b>0=AUTO</b>, 512=512MB, 768=768MB, 1024=1024MB, 1280=1280MB, 1536=1536MB, 1792=1792MB,
+ 2048=2048MB, 2304=2304MB, 2560=2560MB, 2816=2816MB, 3072=3072MB\n
+ When AUTO mode selected, the MMIO size will be calculated by required MMIO size from PCIe devices detected.
+ **/
+ UINT32 MmioSize;
+ UINT32 MmioSizeAdjustment; ///< Offset 56 Increase (given positive value) or Decrease (given negative value) the Reserved MMIO size when Dynamic Tolud/AUTO mode enabled (in MBs): <b>0=no adjustment</b>
+ UINT8 EnableAbove4GBMmio; ///< Offset 60 Enable/disable above 4GB MMIO resource support: 0=Disable, <b>1=Enable</b>
+ UINT8 Reserved[3]; ///< Offset 61 Reserved for future use.
+} HOST_BRIDGE_PREMEM_CONFIG;
+
+
+/**
+ This configuration block describes HostBridge settings in Post-Mem.\n
+ <b>Revision 1</b>:
+ - Initial version.
+**/
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Block Header
+ UINT8 SkipPamLock; ///< Offset 28 :To skip PAM register locking. @note It is still recommended to set PCI Config space B0: D0: F0: Offset 80h[0]=1 in platform code even Silicon code skipped this.\n <b>0=All PAM registers will be locked in Silicon code</b>, 1=Skip lock PAM registers in Silicon code.
+ UINT8 Reserved[3]; ///< Offset 29 Reserved for future use.
+} HOST_BRIDGE_PEI_CONFIG;
+
+#pragma pack (pop)
+
+#endif
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Itss/InterruptConfig.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Itss/InterruptConfig.h
new file mode 100644
index 0000000000..926c7ab6ab
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Itss/InterruptConfig.h
@@ -0,0 +1,38 @@
+/** @file
+ Interrupt policy
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _INTERRUPT_CONFIG_H_
+#define _INTERRUPT_CONFIG_H_
+
+extern EFI_GUID gInterruptConfigGuid;
+
+#pragma pack (push,1)
+
+//
+// --------------------- Interrupts Config ------------------------------
+//
+typedef enum {
+ PchNoInt, ///< No Interrupt Pin
+ PchIntA,
+ PchIntB,
+ PchIntC,
+ PchIntD
+} PCH_INT_PIN;
+
+///
+/// The PCH_DEVICE_INTERRUPT_CONFIG block describes interrupt pin, IRQ and interrupt mode for PCH device.
+///
+typedef struct {
+ UINT8 Device; ///< Device number
+ UINT8 Function; ///< Device function
+ UINT8 IntX; ///< Interrupt pin: INTA-INTD (see PCH_INT_PIN)
+ UINT8 Irq; ///< IRQ to be set for device.
+} PCH_DEVICE_INTERRUPT_CONFIG;
+
+
+#pragma pack (pop)
+
+#endif // _INTERRUPT_CONFIG_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Memory/Ver2/MemoryConfig.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Memory/Ver2/MemoryConfig.h
new file mode 100644
index 0000000000..2be85da5a8
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Memory/Ver2/MemoryConfig.h
@@ -0,0 +1,551 @@
+/** @file
+ Policy definition of Memory Config Block
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _MEMORY_CONFIG_H_
+#define _MEMORY_CONFIG_H_
+
+
+#pragma pack(push, 1)
+
+// MEMORY_CONFIGURATION_REVISION:
+// 3 - Adds DDR5 PDA Enumeration training
+// 4 - Adds LPDDR4 Command Mirroring
+// 5 - Adds PprEnableType
+// 6 - Removed IbeccParity
+// 7 - Adds MarginLimitCheck training within MEMORY_CONFIGURATION
+// 8 - Adds LpddrRttCa, LpddrRttWr
+// 9 - Adds VddqVoltage, VppVoltage
+// 10 - Changes PprEnableType to PprEnable
+// 11 - Changes DisableDimmChannel to DisableChannel
+// 12 - Added DIMMDFE
+// 13 - Added ExtendedBankHashing
+// 14 - Added IBECC Error Injection knobs: IbeccErrInjControl, IbeccErrInjAddress, IbeccErrInjMask, IbeccErrInjCount
+// 15 - Added DynamicMemoryBoost
+// 16 - Added ReuseAdlDdr5Board
+// 17 - Added RefreshWm; Deprecated RefreshPanicWm and RefreshHpWm
+// 18 - Added DebugValue
+// 19 - Added McRefreshRate; Deprecated McRefresh2X
+// 20 - Added RealtimeMemoryFrequency
+// 21 - Added PeriodicDcc and LpMode
+// 22 - Added Tx Dqs Dcc Training
+// 23 - Added tRFCpb, tRFC2, tRFC4, tRRD_L, tRRD_S, tWTR_L, tCCD_L, tWTR_S
+// 24 - Added EccErrInjAddress, EccErrInjMask, EccErrInjCount
+// 25 - Added FreqLimitMixedConfig, FirstDimmBitMask, UserBd
+// 26 - Added SagvSwitchFactorIA/GT/IO/Stall, SagvHeuristicsDownControl, SagvHeuristicsUpControl
+// 27 - Added DRAMDCA
+// 28 - Added FreqLimitMixedConfig_1R1R_8GB, FreqLimitMixedConfig_1R1R_16GB, FreqLimitMixedConfig_1R1R_8GB_16GB, FreqLimitMixedConfig_2R2R
+// 29 - Added LctCmdEyeWidth
+// 30 - Added FirstDimmBitMaskEcc
+// 31 - Added Lp5BankMode
+// 32 - Added WRDS
+// 33 - Added EARLYDIMMDFE for Early DIMM DFE Training
+// 34 - Added OverloadSAM
+#define MEMORY_CONFIGURATION_REVISION 34
+
+// MEMORY_CONFIG_NO_CRC_REVISION:
+// 3 - adds DDR5 SetMemoryPmicVoltage in SA_FUNCTION_CALLS
+#define MEMORY_CONFIG_NO_CRC_REVISION 3
+
+///
+/// MEMORY_CONFIGURATION interface definitions
+///
+#define MRC_MAX_RCOMP_TARGETS 5
+///
+/// Memory SubSystem Definitions
+///
+#define MEM_CFG_MAX_CONTROLLERS 2
+#define MEM_CFG_MAX_CHANNELS 4
+#define MEM_CFG_MAX_DIMMS 2
+#define MEM_CFG_NUM_BYTES_MAPPED 2
+#define MEM_CFG_MAX_SPD_SIZE 1024
+#define MEM_CFG_MAX_SOCKETS (MEM_CFG_MAX_CONTROLLERS * MEM_CFG_MAX_CHANNELS * MEM_CFG_MAX_DIMMS)
+#ifndef MEM_MAX_SAGV_POINTS
+#define MEM_MAX_SAGV_POINTS 4
+#endif
+#define MEM_MAX_IBECC_REGIONS 8
+
+///
+/// SA SPD profile selections.
+///
+typedef enum {
+ DEFAULT_SPD, ///< Standard DIMM profile select.
+ CUSTOM_PROFILE, ///< XMP enthusiast settings: User specifies various override values
+ XMP_PROFILE_1, ///< XMP enthusiast settings: XMP profile #1
+ XMP_PROFILE_2, ///< XMP enthusiast settings: XMP profile #2
+ XMP_PROFILE_3, ///< XMP enthusiast settings: XMP profile #3
+ XMP_USER_PROFILE_4, ///< XMP enthusiast settings: XMP user profile #4
+ XMP_USER_PROFILE_5, ///< XMP enthusiast settings: XMP user profile #5
+ SPDProfileMax = 0xFF ///< Ensures SA_SPD is UINT8
+} SA_SPD;
+
+///
+/// Define the boot modes used by the SPD read function.
+///
+typedef enum {
+ SpdCold, ///< Cold boot
+ SpdWarm, ///< Warm boot
+ SpdS3, ///< S3 resume
+ SpdFast, ///< Fast boot
+ SpdBootModeMax ///< Delimiter
+} SPD_BOOT_MODE;
+
+/**
+ SPD Data Buffer
+**/
+typedef struct {
+ UINT8 SpdData[MEM_CFG_MAX_CONTROLLERS][MEM_CFG_MAX_CHANNELS][MEM_CFG_MAX_DIMMS][MEM_CFG_MAX_SPD_SIZE]; ///< SpdData
+//Next Field Offset 2048
+} SPD_DATA_BUFFER;
+
+/**
+ DqDqs Mapping
+**/
+typedef struct {
+ UINT8 DqsMapCpu2Dram[MEM_CFG_MAX_CONTROLLERS][MEM_CFG_MAX_CHANNELS][MEM_CFG_NUM_BYTES_MAPPED]; ///< DqsMapCpu2Dram
+ UINT8 DqMapCpu2Dram[MEM_CFG_MAX_CONTROLLERS][MEM_CFG_MAX_CHANNELS][MEM_CFG_NUM_BYTES_MAPPED][8]; ///< DqMapCpu2Dram
+//Next Field Offset 16
+} SA_MEMORY_DQDQS_MAPPING;
+
+/**
+ Rcomp Policies
+**/
+typedef struct {
+ UINT16 RcompResistor; ///< Offset 0: Reference RCOMP resistors on motherboard ~ 100 ohms
+ UINT16 RcompTarget[MRC_MAX_RCOMP_TARGETS]; ///< Offset 1: RCOMP target values for DqOdt, DqDrv, CmdDrv, CtlDrv, ClkDrv
+//Next Field Offset 16
+} SA_MEMORY_RCOMP;
+
+/**
+ SPD Offset Table
+**/
+typedef struct {
+ UINT16 Start; ///< Offset 0
+ UINT16 End; ///< Offset 2
+ UINT8 BootMode; ///< Offset 4
+ UINT8 Reserved3[3]; ///< Offset 5 Reserved for future use
+} SPD_OFFSET_TABLE;
+
+///
+/// SA memory address decode.
+///
+typedef struct
+{
+ UINT8 Controller; ///< Offset 0 Zero based Controller number
+ UINT8 Channel; ///< Offset 1 Zero based Channel number
+ UINT8 Dimm; ///< Offset 2 Zero based DIMM number
+ UINT8 Rank; ///< Offset 3 Zero based Rank number
+ UINT8 BankGroup; ///< Offset 4 Zero based Bank Group number
+ UINT8 Bank; ///< Offset 5 Zero based Bank number
+ UINT16 Cas; ///< Offset 6 Zero based CAS number
+ UINT32 Ras; ///< Offset 8 Zero based RAS number
+} SA_ADDRESS_DECODE;
+
+typedef UINT8 (EFIAPI * SA_IO_READ_8) (UINTN IoAddress); ///< CPU I/O port 8-bit read.
+typedef UINT16 (EFIAPI * SA_IO_READ_16) (UINTN IoAddress); ///< CPU I/O port 16-bit read.
+typedef UINT32 (EFIAPI * SA_IO_READ_32) (UINTN IoAddress); ///< CPU I/O port 32-bit read.
+typedef UINT8 (EFIAPI * SA_IO_WRITE_8) (UINTN IoAddress, UINT8 Value); ///< CPU I/O port 8-bit write.
+typedef UINT16 (EFIAPI * SA_IO_WRITE_16) (UINTN IoAddress, UINT16 Value); ///< CPU I/O port 16-bit write.
+typedef UINT32 (EFIAPI * SA_IO_WRITE_32) (UINTN IoAddress, UINT32 Value); ///< CPU I/O port 32-bit write.
+typedef UINT8 (EFIAPI * SA_MMIO_READ_8) (UINTN Address); ///< Memory Mapped I/O port 8-bit read.
+typedef UINT16 (EFIAPI * SA_MMIO_READ_16) (UINTN Address); ///< Memory Mapped I/O port 16-bit read.
+typedef UINT32 (EFIAPI * SA_MMIO_READ_32) (UINTN Address); ///< Memory Mapped I/O port 32-bit read.
+typedef UINT64 (EFIAPI * SA_MMIO_READ_64) (UINTN Address); ///< Memory Mapped I/O port 64-bit read.
+typedef UINT8 (EFIAPI * SA_MMIO_WRITE_8) (UINTN Address, UINT8 Value); ///< Memory Mapped I/O port 8-bit write.
+typedef UINT16 (EFIAPI * SA_MMIO_WRITE_16) (UINTN Address, UINT16 Value); ///< Memory Mapped I/O port 16-bit write.
+typedef UINT32 (EFIAPI * SA_MMIO_WRITE_32) (UINTN Address, UINT32 Value); ///< Memory Mapped I/O port 32-bit write.
+typedef UINT64 (EFIAPI * SA_MMIO_WRITE_64) (UINTN Address, UINT64 Value); ///< Memory Mapped I/O port 64-bit write.
+typedef UINT8 (EFIAPI * SA_SMBUS_READ_8) (UINTN Address, RETURN_STATUS *Status); ///< Smbus 8-bit read.
+typedef UINT16 (EFIAPI * SA_SMBUS_READ_16) (UINTN Address, RETURN_STATUS *Status); ///< Smbus 16-bit read.
+typedef UINT8 (EFIAPI * SA_SMBUS_WRITE_8) (UINTN Address, UINT8 Value, RETURN_STATUS *Status); ///< Smbus 8-bit write.
+typedef UINT16 (EFIAPI * SA_SMBUS_WRITE_16) (UINTN Address, UINT16 Value, RETURN_STATUS *Status); ///< Smbus 16-bit write.
+typedef UINT32 (EFIAPI * SA_GET_PCI_DEVICE_ADDRESS) (UINT8 Bus, UINT8 Device, UINT8 Function, UINT8 Offset); ///< Get PCI device address.
+typedef UINT32 (EFIAPI * SA_GET_PCIE_DEVICE_ADDRESS) (UINT8 Bus, UINT8 Device, UINT8 Function, UINT8 Offset); ///< Get PCI express device address.
+typedef VOID (EFIAPI * SA_GET_RTC_TIME) (UINT8 *Second, UINT8 *Minute, UINT8 *Hour, UINT8 *Day, UINT8 *Month, UINT16 *Year); ///< Get the current time value.
+typedef UINT64 (EFIAPI * SA_GET_CPU_TIME) (VOID); ///< The current CPU time in milliseconds.
+typedef VOID * (EFIAPI * SA_MEMORY_COPY) (VOID *Destination, CONST VOID *Source, UINTN NumBytes); ///< Perform byte copy operation.
+typedef VOID * (EFIAPI * SA_MEMORY_SET_BYTE) (VOID *Buffer, UINTN NumBytes, UINT8 Value); ///< Perform byte initialization operation.
+typedef VOID * (EFIAPI * SA_MEMORY_SET_WORD) (VOID *Buffer, UINTN NumWords, UINT16 Value); ///< Perform word initialization operation.
+typedef VOID * (EFIAPI * SA_MEMORY_SET_DWORD) (VOID *Buffer, UINTN NumDwords, UINT32 Value); ///< Perform dword initialization operation.
+typedef UINT64 (EFIAPI * SA_LEFT_SHIFT_64) (UINT64 Data, UINTN NumBits); ///< Left shift the 64-bit data value by specified number of bits.
+typedef UINT64 (EFIAPI * SA_RIGHT_SHIFT_64) (UINT64 Data, UINTN NumBits); ///< Right shift the 64-bit data value by specified number of bits.
+typedef UINT64 (EFIAPI * SA_MULT_U64_U32) (UINT64 Multiplicand, UINT32 Multiplier); ///< Multiply a 64-bit data value by a 32-bit data value.
+typedef UINT64 (EFIAPI * SA_DIV_U64_U64) (UINT64 Dividend, UINT64 Divisor, UINT64 *Remainder); ///< Divide a 64-bit data value by a 64-bit data value.
+typedef BOOLEAN (EFIAPI * SA_GET_SPD_DATA) (SPD_BOOT_MODE BootMode, UINT8 SpdAddress, UINT8 *Buffer, UINT8 *Ddr3Table, UINT32 Ddr3TableSize, UINT8 *Ddr4Table, UINT32 Ddr4TableSize, UINT8 *LpddrTable, UINT32 LpddrTableSize); ///< Read the SPD data over the SMBus, at the given SmBus SPD address and copy the data to the data structure.
+typedef UINT8 (EFIAPI * SA_GET_MC_ADDRESS_DECODE) (UINT64 Address, SA_ADDRESS_DECODE *DramAddress);
+typedef UINT8 (EFIAPI * SA_GET_MC_ADDRESS_ENCODE) (SA_ADDRESS_DECODE *DramAddress, UINT64 Address);
+typedef BOOLEAN (EFIAPI * SA_GET_RANDOM_NUMBER) (UINT32 *Rand); ///< Get the next random 32-bit number.
+typedef EFI_STATUS (EFIAPI * SA_CPU_MAILBOX_READ) (UINT32 Type, UINT32 Command, UINT32 *Value, UINT32 *Status); ///< Perform a CPU mailbox read.
+typedef EFI_STATUS (EFIAPI * SA_CPU_MAILBOX_WRITE) (UINT32 Type, UINT32 Command, UINT32 Value, UINT32 *Status); ///< Perform a CPU mailbox write.
+typedef UINT32 (EFIAPI * SA_GET_MEMORY_VDD) (VOID *GlobalData, UINT32 DefaultVdd); ///< Get the current memory voltage (VDD).
+typedef UINT32 (EFIAPI * SA_SET_MEMORY_VDD) (VOID *GlobalData, UINT32 DefaultVdd, UINT32 Value); ///< Set the memory voltage (VDD) to the given value.
+typedef UINT32 (EFIAPI * SA_SET_MEMORY_PMIC_VOLTAGE) (VOID *GlobalData, UINT8 SpdAddress, UINT32 Vdd, UINT32 Vddq, UINT32 Vpp); ///< Set DDR5 memory voltages (VDD, VDDQ, VPP) to the given values.
+typedef UINT32 (EFIAPI * SA_CHECKPOINT) (VOID *GlobalData, UINT32 CheckPoint, VOID *Scratch); ///< Check point that is called at various points in the MRC.
+typedef VOID (EFIAPI * SA_DEBUG_HOOK) (VOID *GlobalData, UINT16 DisplayDebugNumber); ///< Typically used to display to the I/O port 80h.
+typedef UINT8 (EFIAPI * SA_CHANNEL_EXIST) (VOID *Outputs, UINT8 Channel); ///< Returns whether Channel is or is not present.
+typedef INT32 (EFIAPI * SA_PRINTF) (VOID *Debug, UINT32 Level, char *Format, ...); ///< Print to output stream/device.
+typedef VOID (EFIAPI * SA_DEBUG_PRINT) (VOID *String); ///< Output a string to the debug stream/device.
+typedef UINT32 (EFIAPI * SA_CHANGE_MARGIN) (VOID *GlobalData, UINT8 Param, INT32 Value0, INT32 Value1, UINT8 EnMultiCast, UINT8 Channel, UINT8 RankIn, UINT8 Byte, UINT8 BitIn, UINT8 UpdateMrcData, UINT8 SkipWait, UINT32 RegFileParam); ///< Change the margin.
+typedef UINT8 (EFIAPI * SA_SIGN_EXTEND) (UINT8 Value, UINT8 OldMsb, UINT8 NewMsb); ///< Sign extends OldMSB to NewMSB Bits (Eg: Bit 6 to Bit 7).
+typedef VOID (EFIAPI * SA_SHIFT_PI_COMMAND_TRAIN) (VOID *GlobalData, UINT8 Channel, UINT8 Iteration, UINT8 RankMask, UINT8 GroupMask, INT32 NewValue, UINT8 UpdateHost); ///< Move CMD/CTL/CLK/CKE PIs during training.
+typedef VOID (EFIAPI * SA_UPDATE_VREF) (VOID *GlobalData, UINT8 Channel, UINT8 RankMask, UINT16 DeviceMask, UINT8 VrefType, INT32 Offset, BOOLEAN UpdateMrcData, BOOLEAN PDAmode, BOOLEAN SkipWait); ///< Update the Vref value and wait until it is stable.
+typedef UINT8 (EFIAPI * SA_GET_RTC_CMOS) (UINT8 Location); ///< Get the current value of the specified RTC CMOS location.
+typedef UINT64 (EFIAPI * SA_MSR_READ_64) (UINT32 Location); ///< Get the current value of the specified MSR location.
+typedef UINT64 (EFIAPI * SA_MSR_WRITE_64) (UINT32 Location, UINT64 Data); ///< Set the current value of the specified MSR location.
+typedef VOID (EFIAPI * SA_MRC_RETURN_FROM_SMC) (VOID *GlobalData, UINT32 MrcStatus); ///< Hook function after returning from MrcStartMemoryConfiguration()
+typedef VOID (EFIAPI * SA_MRC_DRAM_RESET) (UINT32 PciEBaseAddress, UINT32 ResetValue); ///< Assert or deassert DRAM_RESET# pin; this is used in JEDEC Reset.
+typedef VOID (EFIAPI * SA_DELAY_NS) (VOID *GlobalData, UINT32 DelayNs); ///< Delay (stall) for the given amount of nanoseconds.
+typedef VOID (EFIAPI * SA_SET_LOCK_PRMRR) (UINT64 PrmrrBaseAddress, UINT32 PrmrrSize);
+
+
+///
+/// Function calls into the SA.
+///
+typedef struct {
+ SA_IO_READ_8 IoRead8; ///< Offset 0: - CPU I/O port 8-bit read.
+ SA_IO_READ_16 IoRead16; ///< Offset 4: - CPU I/O port 16-bit read.
+ SA_IO_READ_32 IoRead32; ///< Offset 8: - CPU I/O port 32-bit read.
+ SA_IO_WRITE_8 IoWrite8; ///< Offset 12: - CPU I/O port 8-bit write.
+ SA_IO_WRITE_16 IoWrite16; ///< Offset 16: - CPU I/O port 16-bit write.
+ SA_IO_WRITE_32 IoWrite32; ///< Offset 20: - CPU I/O port 32-bit write.
+ SA_MMIO_READ_8 MmioRead8; ///< Offset 24: - Memory Mapped I/O port 8-bit read.
+ SA_MMIO_READ_16 MmioRead16; ///< Offset 28: - Memory Mapped I/O port 16-bit read.
+ SA_MMIO_READ_32 MmioRead32; ///< Offset 32: - Memory Mapped I/O port 32-bit read.
+ SA_MMIO_READ_64 MmioRead64; ///< Offset 36: - Memory Mapped I/O port 64-bit read.
+ SA_MMIO_WRITE_8 MmioWrite8; ///< Offset 40: - Memory Mapped I/O port 8-bit write.
+ SA_MMIO_WRITE_16 MmioWrite16; ///< Offset 44: - Memory Mapped I/O port 16-bit write.
+ SA_MMIO_WRITE_32 MmioWrite32; ///< Offset 48: - Memory Mapped I/O port 32-bit write.
+ SA_MMIO_WRITE_64 MmioWrite64; ///< Offset 52: - Memory Mapped I/O port 64-bit write.
+ SA_SMBUS_READ_8 SmbusRead8; ///< Offset 56: - Smbus 8-bit read.
+ SA_SMBUS_READ_16 SmbusRead16; ///< Offset 60: - Smbus 16-bit read.
+ SA_SMBUS_WRITE_8 SmbusWrite8; ///< Offset 64: - Smbus 8-bit write.
+ SA_SMBUS_WRITE_16 SmbusWrite16; ///< Offset 68: - Smbus 16-bit write.
+ SA_GET_PCI_DEVICE_ADDRESS GetPciDeviceAddress; ///< Offset 72: - Get PCI device address.
+ SA_GET_PCIE_DEVICE_ADDRESS GetPcieDeviceAddress; ///< Offset 76: - Get PCI express device address.
+ SA_GET_RTC_TIME GetRtcTime; ///< Offset 80: - Get the current time value.
+ SA_GET_CPU_TIME GetCpuTime; ///< Offset 84: - The current CPU time in milliseconds.
+ SA_MEMORY_COPY CopyMem; ///< Offset 88: - Perform byte copy operation.
+ SA_MEMORY_SET_BYTE SetMem; ///< Offset 92: - Perform byte initialization operation.
+ SA_MEMORY_SET_WORD SetMemWord; ///< Offset 96: - Perform word initialization operation.
+ SA_MEMORY_SET_DWORD SetMemDword; ///< Offset 100: - Perform dword initialization operation.
+ SA_LEFT_SHIFT_64 LeftShift64; ///< Offset 104: - Left shift the 64-bit data value by specified number of bits.
+ SA_RIGHT_SHIFT_64 RightShift64; ///< Offset 108: - Right shift the 64-bit data value by specified number of bits.
+ SA_MULT_U64_U32 MultU64x32; ///< Offset 112: - Multiply a 64-bit data value by a 32-bit data value.
+ SA_DIV_U64_U64 DivU64x64; ///< Offset 116: - Divide a 64-bit data value by a 64-bit data value.
+ SA_GET_SPD_DATA GetSpdData; ///< Offset 120: - Read the SPD data over the SMBus, at the given SmBus SPD address and copy the data to the data structure.
+ SA_GET_RANDOM_NUMBER GetRandomNumber; ///< Offset 124: - Get the next random 32-bit number.
+ SA_CPU_MAILBOX_READ CpuMailboxRead; ///< Offset 128: - Perform a CPU mailbox read.
+ SA_CPU_MAILBOX_WRITE CpuMailboxWrite; ///< Offset 132: - Perform a CPU mailbox write.
+ SA_GET_MEMORY_VDD GetMemoryVdd; ///< Offset 136: - Get the current memory voltage (VDD).
+ SA_SET_MEMORY_VDD SetMemoryVdd; ///< Offset 140: - Set the memory voltage (VDD) to the given value.
+ SA_CHECKPOINT CheckPoint; ///< Offset 144: - Check point that is called at various points in the MRC.
+ SA_DEBUG_HOOK DebugHook; ///< Offset 148: - Typically used to display to the I/O port 80h.
+ SA_DEBUG_PRINT DebugPrint; ///< Offset 152: - Output a string to the debug stream/device.
+ SA_GET_RTC_CMOS GetRtcCmos; ///< Offset 156: - Get the current value of the specified RTC CMOS location.
+ SA_MSR_READ_64 ReadMsr64; ///< Offset 160: - Get the current value of the specified MSR location.
+ SA_MSR_WRITE_64 WriteMsr64; ///< Offset 164 - Set the current value of the specified MSR location.
+ SA_MRC_RETURN_FROM_SMC MrcReturnFromSmc; ///< Offset 168 - Hook function after returning from MrcStartMemoryConfiguration()
+ SA_MRC_DRAM_RESET MrcDramReset; ///< Offset 172 - Assert or deassert DRAM_RESET# pin; this is used in JEDEC Reset.
+ SA_DELAY_NS MrcDelayNs; ///< Offset 176 - Delay (stall) for the given amount of nanoseconds.
+ SA_SET_MEMORY_PMIC_VOLTAGE SetMemoryPmicVoltage; ///< Offset 180: - Set the memory voltage (VDD/VDDQ/VPP) by PMIC for DDR5.
+} SA_FUNCTION_CALLS;
+
+///
+/// Function calls into the MRC.
+///
+typedef struct {
+ SA_CHANNEL_EXIST MrcChannelExist; ///< Offset 0: - Returns whether Channel is or is not present.
+ SA_PRINTF MrcPrintf; ///< Offset 4: - Print to output stream/device.
+ SA_CHANGE_MARGIN MrcChangeMargin; ///< Offset 8: - Change the margin.
+ SA_SIGN_EXTEND MrcSignExtend; ///< Offset 12: - Sign extends OldMSB to NewMSB Bits (Eg: Bit 6 to Bit 7).
+ SA_SHIFT_PI_COMMAND_TRAIN ShiftPiCommandTrain; ///< Offset 16: - Move CMD/CTL/CLK/CKE PIs during training.
+ SA_UPDATE_VREF MrcUpdateVref; ///< Offset 20: - Update the Vref value and wait until it is stable.
+} SA_MEMORY_FUNCTIONS;
+
+/**
+ Memory Configuration
+ The contents of this structure are CRC'd by the MRC for option change detection.
+ This structure is copied en mass to the MrcInput structure. If you add fields here, you must update the MrcInput structure.
+ Revision history is at the top of this file
+**/
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Block Header
+ UINT16 Size; ///< Offset 28 The size of this structure, in bytes. Must be the first entry in this structure.
+ UINT8 HobBufferSize; ///< Offset 30 Size of HOB buffer for MRC
+
+ UINT8 SpdProfileSelected; ///< Offset 31 SPD XMP profile selection - for XMP supported DIMM: <b>0=Default DIMM profile</b>, 1=Custom Profile, 2=XMP Profile 1, 3=XMP Profile 2, 4=XMP Profile 3, 5=XMP User Profile 4, 6=XMP User Profile 5
+
+ // The following parameters are used only when SpdProfileSelected is User Defined (CUSTOM_PROFILE)
+ UINT16 tCL; ///< Offset 32 User defined Memory Timing tCL value, valid when SpdProfileSelected is CUSTOM_PROFILE: <b>0=AUTO</b>, 31=Maximum.
+ UINT16 tRCDtRP; ///< Offset 34 User defined Memory Timing tRCD value (same as tRP), valid when SpdProfileSelected is CUSTOM_PROFILE: <b>0=AUTO</b>, 63=Maximum
+ UINT16 tRAS; ///< Offset 36 User defined Memory Timing tRAS value, valid when SpdProfileSelected is CUSTOM_PROFILE: <b>0=AUTO</b>, 64=Maximum.
+ UINT16 tWR; ///< Offset 38 User defined Memory Timing tWR value, valid when SpdProfileSelected is CUSTOM_PROFILE: <b>0=AUTO</b>, legal values: 5, 6, 7, 8, 10, 12, 14, 16, 18, 20, 24.
+ UINT16 tRFC; ///< Offset 40 User defined Memory Timing tRFC value, valid when SpdProfileSelected is CUSTOM_PROFILE: <b>0=AUTO</b>, 1023=Maximum.
+ UINT16 tRRD; ///< Offset 42 User defined Memory Timing tRRD value, valid when SpdProfileSelected is CUSTOM_PROFILE: <b>0=AUTO</b>, 15=Maximum.
+ UINT16 tWTR; ///< Offset 44 User defined Memory Timing tWTR value, valid when SpdProfileSelected is CUSTOM_PROFILE: <b>0=AUTO</b>, 28=Maximum.
+ UINT16 tRTP; ///< Offset 46 User defined Memory Timing tRTP value, valid when SpdProfileSelected is CUSTOM_PROFILE: <b>0=AUTO</b>, 15=Maximum. DDR4 legal values: 5, 6, 7, 8, 9, 10, 12
+ UINT16 tFAW; ///< Offset 48 User defined Memory Timing tFAW value, valid when SpdProfileSelected is CUSTOM_PROFILE: <b>0=AUTO</b>, 63=Maximum.
+ UINT16 tCWL; ///< Offset 50 User defined Memory Timing tCWL value, valid when SpdProfileSelected is CUSTOM_PROFILE: <b>0=AUTO</b>, 20=Maximum.
+ UINT16 tREFI; ///< Offset 52 User defined Memory Timing tREFI value, valid when SpdProfileSelected is CUSTOM_PROFILE: <b>0=AUTO</b>, 65535=Maximum.
+ UINT16 PciIndex; ///< Offset 54 Pci index register address: <b>0xCF8=Default</b>
+ UINT16 PciData; ///< Offset 56 Pci data register address: <b>0xCFC=Default</b>
+ UINT16 VddVoltage; ///< Offset 58 DRAM voltage (Vdd) in millivolts: <b>0=Platform Default (no override)</b>, 1200=1.2V, 1350=1.35V etc.
+ UINT16 Idd3n; ///< Offset 60 EPG Active standby current (Idd3N) in milliamps from DIMM datasheet.
+ UINT16 Idd3p; ///< Offset 62 EPG Active power-down current (Idd3P) in milliamps from DIMM datasheet.
+
+ UINT32 EccSupport:1; ///< Offset 64 Bit 0 - DIMM Ecc Support option - for Desktop only: 0=Disable, <b>1=Enable</b>
+ UINT32 MrcSafeConfig:1; ///< Bit 1 - MRC Safe Mode: <b>0=Disable</b>, 1=Enable
+ UINT32 RemapEnable:1; ///< Bit 2 - This option is used to control whether to enable/disable memory remap above 4GB: 0=Disable, <b>1=Enable</b>.
+ UINT32 ScramblerSupport:1; ///< Bit 3 - Memory scrambler support: 0=Disable, <b>1=Enable</b>
+ UINT32 Vc1ReadMeter:1; ///< Bit 4 - VC1 Read Metering Enable: 0=Disable, <b>1=Enable</b>
+ UINT32 ForceSingleSubchannel:1; ///< Bit 5 - TRUE means use SubChannel0 only (for LPDDR4): <b>0=Disable</b>, 1=Enable
+ UINT32 SimicsFlag:1; ///< Bit 6 - Option to Enable SIMICS: 0=Disable, <b>1=Enable</b>
+ UINT32 Ddr4DdpSharedClock:1; ///< Bit 7 - Select if CLK0 is shared between Rank0 and Rank1 in DDR4 DDP package. <b>0=Not shared</b>, 1=Shared
+ UINT32 SharedZqPin:1; ///< Bit 8 - Select if the ZQ resistor is shared between Ranks in DDR4/LPDDR4 DRAM Packages <b>0=Not Shared</b>, 1=Shared
+ UINT32 LpDqsOscEn:1; ///< Bit 9 - LPDDR Write DQ/DQS Retraining: 0=Disable, <b>1=Enable</b>
+ UINT32 RmtPerTask:1; ///< Bit 10 - Rank Margin Tool Per Task. <b>0 = Disabled</b>, 1 = Enabled
+ UINT32 TrainTrace:1; ///< Bit 11 - Trained state tracing debug. <b>0 = Disabled</b>, 1 = Enabled
+ UINT32 SafeMode:1; ///< Bit 12 - Define if safe mode is enabled for MC/IO
+ UINT32 MsHashEnable:1; ///< Bit 13 - Controller Hash Enable: 0=Disable, <b>1=Enable</b>
+ UINT32 DisPgCloseIdleTimeout:1; ///< Bit 14 - Disable Page Close Idle Timeout: 0=Enable, <b>1=Disable</b>
+ UINT32 Ibecc:1; ///< Bit 15 - In-band ECC: <b>0=Disable</b>, 1=Enable
+ UINT32 IbeccOperationMode:2; ///< Bits 16:17 - In-band ECC Operation Mode: 0=Functional Mode protects requests based on the address range, 1=Makes all requests non protected and ignore range checks, <b>2=Makes all requests protected and ignore range checks</b>
+ UINT32 ChHashOverride:1; ///< Bit 18 - Select if Channel Hash setting values will be taken from input parameters or automatically taken from POR values depending on DRAM type detected.
+ UINT32 EccDftEn:1; ///< Bit 19 - ECC DFT support option
+ UINT32 Write0:1; ///< Bit 20 - Write0 feature (LP5/DDR5): 0=Disable, <b>1=Enable</b>
+ UINT32 ReuseAdlSDdr5Board:1; ///< Bit 21 - Indicate whether adl ddr5 board is reused.
+ UINT32 PeriodicDcc:1; ///< Bit 22 - Periodic DCC: <b>0=Disable</b>, 1=Enable
+ UINT32 LpMode:2; ///< Bit 23:24 - LPMode: <b>0=Auto</b>, 1=Enabled, 2=Disabled, 3=Reserved
+ UINT32 RsvdO64B25to31:7; ///< Bits 25:31 reserved
+ UINT8 DisableChannel[MEM_CFG_MAX_CONTROLLERS][MEM_CFG_MAX_CHANNELS]; ///< Offset 68-75
+ UINT8 Ratio; ///< Offset 76 DDR Frequency ratio, to multiply by 133 or 100 MHz depending on RefClk. <b>0 = Auto</b>
+ UINT8 ProbelessTrace; ///< Offset 77 Probeless Trace: <b>0=Disabled</b>, <b>1=Enabled</b>
+ /**
+ Channel Hash Enable.\n
+ NOTE: BIT7 will interleave the channels at a 2 cache-line granularity, BIT8 at 4 and BIT9 at 8\n
+ 0=BIT6, <B>1=BIT7</B>, 2=BIT8, 3=BIT9
+ **/
+ UINT8 ChHashInterleaveBit; ///< Offset 78 Option to select interleave Address bit. Valid values are 0 - 3 for BITS 6 - 9 (Valid values for BDW are 0-7 for BITS 6 - 13)
+ UINT8 SmramMask; ///< Offset 79 Reserved memory ranges for SMRAM
+ UINT32 BClkFrequency; ///< Offset 80 Base reference clock value, in Hertz: <b>100000000 = 100Hz</b>, 125000000=125Hz, 167000000=167Hz, 250000000=250Hz
+
+ /// Training Algorithms 1 Offset 84
+ UINT32 ECT:1; ///< Bit 0 - Enable/Disable Early Command Training. Note it is not recommended to change this setting from the default value: <b>0=Disable</b>, 1=Enable.
+ UINT32 SOT:1; ///< Bit 1 - Enable/Disable Sense Amp Offset Training. Note it is not recommended to change this setting from the default value: 0=Disable, <b>1=Enable</b>.
+ UINT32 ERDMPRTC2D:1; ///< Bit 2 - Enable/Disable Early ReadMPR Timing Centering 2D. Note it is not recommended to change this setting from the default value: 0=Disable, <b>1=Enable</b>.
+ UINT32 RDMPRT:1; ///< Bit 3 - Enable/Disable Read MPR Training. Note it is not recommended to change this setting from the default value: 0=Disable, <b>1=Enable</b>.
+ UINT32 RCVET:1; ///< Bit 4 - Enable/Disable Receive Enable Training. Note it is not recommended to change this setting from the default value: 0=Disable, <b>1=Enable</b>.
+ UINT32 JWRL:1; ///< Bit 5 - Enable/Disable JEDEC Write Leveling Training. Note it is not recommended to change this setting from the default value: 0=Disable, <b>1=Enable</b>.
+ UINT32 EWRTC2D:1; ///< Bit 6 - Enable/Disable Early Write Time Centering 2D Training. Note it is not recommended to change this setting from the default value: 0=Disable, <b>1=Enable</b>.
+ UINT32 ERDTC2D:1; ///< Bit 7 - Enable/Disable Early Read Time Centering 2D Training. Note it is not recommended to change this setting from the default value: 0=Disable, <b>1=Enable</b>.
+ UINT32 WRTC1D:1; ///< Bit 8 - Enable/Disable 1D Write Timing Centering Training. Note it is not recommended to change this setting from the default value: 0=Disable, <b>1=Enable</b>.
+ UINT32 WRVC1D:1; ///< Bit 9 - Enable/Disable 1D Write Voltage Centering Training. Note it is not recommended to change this setting from the default value: 0=Disable, <b>1=Enable</b>.
+ UINT32 RDTC1D:1; ///< Bit 10 - Enable/Disable 1D Read Timing Centering Training. Note it is not recommended to change this setting from the default value: 0=Disable, <b>1=Enable</b>.
+ UINT32 DIMMODTT:1; ///< Bit 11 - Enable/Disable DIMM ODT Training. Note it is not recommended to change this setting from the default value: <b>0=Disable</b>, 1=Enable.
+ UINT32 DIMMRONT:1; ///< Bit 12 - Enable/Disable DIMM RON training. Note it is not recommended to change this setting from the default value: 0=Disable, <b>1=Enable</b>.
+ UINT32 WRDSEQT:1; ///< Bit 13 - Enable/Disable Write Drive Strength / Equalization Training 2D. Note it is not recommended to change this setting from the default value: <b>0=Disable</b>, 1=Enable.
+ UINT32 WRSRT:1; ///< Bit 14 - Enable/Disable Write Slew Rate traning. Note it is not recommended to change this setting from the default value: 0=Disable, <b>1=Enable.</b>
+ UINT32 RDODTT:1; ///< Bit 15 - Enable/Disable Read ODT Training. Note it is not recommended to change this setting from the default value: <b>0=Disable</b>, 1=Enable.
+ UINT32 RDEQT:1; ///< Bit 16 - Enable/Disable Read Equalization Training. Note it is not recommended to change this setting from the default value: <b>0=Disable</b>, 1=Enable.
+ UINT32 RDAPT:1; ///< Bit 17 - Enable/Disable Read Amplifier Power Training. Note it is not recommended to change this setting from the default value: <b>0=Disable</b>, 1=Enable.
+ UINT32 WRTC2D:1; ///< Bit 18 - Enable/Disable 2D Write Timing Centering Training. Note it is not recommended to change this setting from the default value: 0=Disable, <b>1=Enable</b>.
+ UINT32 RDTC2D:1; ///< Bit 19 - Enable/Disable 2D Read Timing Centering Training. Note it is not recommended to change this setting from the default value: 0=Disable, <b>1=Enable</b>.
+ UINT32 WRVC2D:1; ///< Bit 20 - Enable/Disable 2D Write Voltage Centering Training. Note it is not recommended to change this setting from the default value: 0=Disable, <b>1=Enable</b>.
+ UINT32 RDVC2D:1; ///< Bit 21 - Enable/Disable 2D Read Voltage Centering Training. Note it is not recommended to change this setting from the default value: 0=Disable, <b>1=Enable</b>.
+ UINT32 CMDVC:1; ///< Bit 22 - Enable/Disable Command Vref Centering Training. Note it is not recommended to change this setting from the default value 0=Disable, <b>1=Enable</b>.
+ UINT32 LCT:1; ///< Bit 23 - Enable/Disable Late Command Training. Note it is not recommended to change this setting from the default value: 0=Disable, <b>1=Enable</b>.
+ UINT32 RTL:1; ///< Bit 24 - Enable/Disable Round Trip Latency function. Note it is not recommended to change this setting from the default value: 0=Disable, <b>1=Enable</b>.
+ UINT32 TAT:1; ///< Bit 25 - Enable/Disable Turn Around Time function. Note it is not recommended to change this setting from the default value: <b>0=Disable</b>, 1=Enable.
+ UINT32 RMT:1; ///< Bit 26 - Enable/Disable Rank Margin Tool function: <b>0=Disable</b>, 1=Enable.
+ UINT32 MEMTST:1; ///< Bit 27 - Enable/Disable Memory Test function: <b>0=Disable</b>, 1=Enable.
+ UINT32 ALIASCHK:1; ///< Bit 28 - Enable/Disable DIMM SPD Alias Check: 0=Disable, <b>1=Enable</b>
+ UINT32 RCVENC1D:1; ///< Bit 29 - Enable/Disable Receive Enable Centering Training (LPDDR Only). Note it is not recommended to change this setting from the default value: <b>0=Disable</b>, 1=Enable
+ UINT32 RMC:1; ///< Bit 30 - Enable/Disable Retrain Margin Check. Note it is not recommended to change this setting from the default value: <b>0=Disable</b>, 1=Enable
+ UINT32 WRDSUDT:1; ///< Bit 31 - Enable/Disable Write Drive Strength Up/Dn independently. Note it is not recommended to change this setting from the default value: <b>0=Disable</b>, 1=Enable
+ /// Training Algorithms 2 Offset 88
+ UINT32 DCC : 1; ///< Bit 0 - Enable/Disable Duty Cycle Correction: 0=Disable, 1=Enable.
+ UINT32 RDVC1D : 1; ///< Bit 1 - Enable/Disable Read Voltage Centering 1D: 0=Disable, 1=Enable.
+ UINT32 TXTCO : 1; ///< Bit 2 - Enable/Disable Write TCO Comp Training: 0=Disable, 1=Enable.
+ UINT32 CLKTCO : 1; ///< Bit 3 - Enable/Disable Clock TCO Comp Training: 0=Disable, 1=Enable.
+ UINT32 CMDSR : 1; ///< Bit 4 - Enable/Disable CMD Slew Rate Training: 0=Disable, 1=Enable.
+ UINT32 CMDDSEQ : 1; ///< Bit 5 - Enable/Disable CMD Drive Strength and Tx Equalization: 0=Disable, 1=Enable.
+ UINT32 DIMMODTCA : 1; ///< Bit 6 - Enable/Disable Dimm ODT CA Training: 0=Disable, 1=Enable.
+ UINT32 TXTCODQS : 1; ///< Bit 7 - Enable/Disable Write TCO Dqs Training: 0=Disable, 1=Enable.
+ UINT32 CMDDRUD : 1; ///< Bit 8 - Enable/Disable CMD/CTL Drive Strength Up/Dn 2D: 0=Disable, 1=Enable.
+ UINT32 VCCDLLBP : 1; ///< Bit 9 - Enable/Disable VccDLL bypass to VccIOG training: 0=Disable, 1=Enable.
+ UINT32 PVTTDNLP : 1; ///< Bit 10 - Enable/Disable PanicVttDnLp Training: 0=Disable, 1=Enable.
+ UINT32 RDVREFDC : 1; ///< Bit 11 - Enable/Disable Read Vref Decap Training: 0=Disable, 1=Enable.
+ UINT32 VDDQT : 1; ///< Bit 12 - Enable/Disable Vddq Training: 0=Disable, 1=Enable.
+ UINT32 RMTBIT : 1; ///< Bit 13 - Enable/Disable Rank Margin Tool Per Bit: 0=Disable, 1=Enable.
+ UINT32 PDA : 1; ///< BIT 14 - Enable/Disable PDA Enumeration Training. Note it is not recommended to change this setting from the default value: 0=Disable, <b>1=Enable</b>.
+ UINT32 DIMMDFE : 1; ///< BIT 15 - Enable/Disable DIMM DFE Training: 0=Disable, <b>1=Enable</b>.
+ UINT32 TXDQSDCC : 1; ///< BIT 16 - Enable/Disable TX DQS DCC Training: 0=Disable, <b>1=Enable</b>.
+ UINT32 DRAMDCA : 1; ///< BIT 17 - Enable/Disable DRAM DCA Training: 0=Disable, <b>1=Enable</b>.
+ UINT32 WRDS : 1; ///< BIT 18 - Enable/Disable Write Driver Strength Training: 0=Disable, <b>1=Enable</b>.
+ UINT32 EARLYDIMMDFE : 1; ///< BIT 19 - Enable/Disable EARLY DIMM DFE Training: 0=Disable, <b>1=Enable</b>.
+ UINT32 ReservedBits2 :12; ///< Bits 20:31 - Reserved
+
+ UINT32 MrcTimeMeasure:1; ///< Offset 92 Bit 0 - Enables serial debug level to display the MRC execution times only: <b>0=Disable</b>, 1=Enable
+ UINT32 MrcFastBoot:1; ///< Bit 1 - Enables the MRC fast boot path for faster cold boot execution: 0=Disable, <b>1=Enable</b>
+ UINT32 DqPinsInterleaved:1; ///< Bit 2 - Interleaving mode of DQ/DQS pins which depends on board routing: <b>0=Disable</b>, 1=Enable
+ UINT32 RankInterleave:1; ///< Bit 3 - Rank Interleave Mode: 0=Disable, <b>1=Enable</b>
+ UINT32 EnhancedInterleave:1; ///< Bit 4 - Enhanced Interleave Mode: 0=Disable, <b>1=Enable</b>
+ UINT32 WeaklockEn:1; ///< Bit 5 - Weak Lock Enable: 0=Disable, <b>1=Enable</b>
+ UINT32 ChHashEnable:1; ///< Bit 6 - Channel Hash Enable: 0=Disable, <b>1=Enable</b>
+ UINT32 EnablePwrDn:1; ///< Bit 7 - Enable Power Down control for DDR: 0=PCODE control, <b>1=BIOS control</b>
+ UINT32 EnablePwrDnLpddr:1; ///< Bit 8 - Enable Power Down for LPDDR: 0=PCODE control, <b>1=BIOS control</b>
+ UINT32 SrefCfgEna:1; ///< Bit 9 - Enable Self Refresh: 0=Disable, <b>1=Enable</b>
+ UINT32 ThrtCkeMinDefeatLpddr:1; ///< Bit 10 - Throttler CKE min defeature for LPDDR: 0=Disable, <b>1=Enable</b>
+ UINT32 ThrtCkeMinDefeat:1; ///< Bit 11 - Throttler CKE min defeature: <b>0=Disable</b>, 1=Enable
+ UINT32 AutoSelfRefreshSupport:1; ///< Bit 12 - FALSE = No auto self refresh support, <b>TRUE = auto self refresh support</b>
+ UINT32 ExtTemperatureSupport:1; ///< Bit 13 - FALSE = No extended temperature support, <b>TRUE = extended temperature support</b>
+ UINT32 MobilePlatform:1; ///< Bit 14 - Memory controller device id indicates: <b>TRUE if mobile</b>, FALSE if not. Note: This will be auto-detected and updated.
+ UINT32 Force1Dpc:1; ///< Bit 15 - TRUE means force one DIMM per channel, <b>FALSE means no limit</b>
+ UINT32 ForceSingleRank:1; ///< Bit 16 - TRUE means use Rank0 only (in each DIMM): <b>0=Disable</b>, 1=Enable
+ UINT32 VttTermination:1; ///< Bit 17 - Vtt Termination for Data ODT: <b>0=Disable</b>, 1=Enable
+ UINT32 VttCompForVsshi:1; ///< Bit 18 - Enable/Disable Vtt Comparator For Vsshi: <b>0=Disable</b>, 1=Enable
+ UINT32 ExitOnFailure:1; ///< Bit 19 - MRC option for exit on failure or continue on failure: 0=Disable, <b>1=Enable</b>
+ UINT32 NewFeatureEnable1:1; ///< Bit 20 - Generic enable knob for new feature set 1 <b>0: Disable </b>; 1: Enable
+ UINT32 NewFeatureEnable2:1; ///< Bit 21 - Generic enable knob for new feature set 2 <b>0: Disable </b>; 1: Enable
+ UINT32 RhSelect:2; ///< Bit 22-23 - RH Select: <b>0=Disable</b>, 1=RFM, 2=pTRR
+ UINT32 RefreshPanicWm:4; ///< Bit 24-27 - Deprecated from revision 17. Use RefreshWm instead.
+ UINT32 RefreshHpWm:4; ///< Bit 28-31 - Deprecated from revision 17. Use RefreshWm instead.
+ UINT32 VddSettleWaitTime; ///< Offset 96 Amount of time in microseconds to wait for Vdd to settle on top of 200us required by JEDEC spec: <b>Default=0</b>
+ UINT16 SrefCfgIdleTmr; ///< Offset 100 Self Refresh idle timer: <b>512=Minimal</b>, 65535=Maximum
+ UINT16 ChHashMask; ///< Offset 102 Channel Hash Mask: 0x0001=BIT6 set(Minimal), 0x3FFF=BIT[19:6] set(Maximum), <b>0x30CE= BIT[19:18, 13:12 ,9:7] set</b>
+ UINT16 DdrFreqLimit; ///< Offset 104 Memory Frequency limit: <b>0 = Auto</b>, or memory speed value in MT/s: 1067, 1333, 1600 etc. See the possible values in MrcInterface.h
+ UINT8 MaxRttWr; ///< Offset 106 Maximum DIMM RTT_WR to use in power training: <b>0=ODT Off</b>, 1 = 120 ohms
+ UINT8 ThrtCkeMinTmr; ///< Offset 107 Throttler CKE min timer: 0=Minimal, 0xFF=Maximum, <b>0x00=Default</b>
+ UINT8 ThrtCkeMinTmrLpddr; ///< Offset 108 Throttler CKE min timer for LPDDR: 0=Minimal, 0xFF=Maximum, <b>0x00=Default</b>
+ BOOLEAN PerBankRefresh; ///< Offset 109 Enables and Disables the per bank refresh. This only impacts memory technologies that support PBR: LPDDR4, LPDDR5 and DDR5. FALSE=Disabled, <b>TRUE=Enabled</b>
+ UINT8 SaGv; ///< Offset 110 SA GV: <b>0=Disabled</b>, 1=Point1, 2=Point2, 3=Point3, 4=Point4, 5=Enabled
+ UINT8 NModeSupport; ///< Offset 111 Memory N Mode Support - Enable user to select Auto, 1N or 2N: <b>0=AUTO</b>, 1=1N, 2=2N.
+ UINT8 RefClk; ///< Offset 112 Selects the DDR base reference clock. 0x01 = 100MHz, <b>0x00 = 133MHz</b>
+ UINT8 EnCmdRate; ///< Offset 113 CMD Rate Enable: 0=Disable, 5=2 CMDs, <b>7=3 CMDs</b>, 9=4 CMDs, 11=5 CMDs, 13=6 CMDs, 15=7 CMDs
+ UINT8 Refresh2X; ///< Offset 114 Refresh 2x: <b>0=Disable</b>, 1=Enable for WARM or HOT, 2=Enable for HOT only
+ UINT8 EpgEnable; ///< Offset 115 Enable Energy Performance Gain.
+ UINT8 UserThresholdEnable; ///< Offset 116 Flag to manually select the DIMM CLTM Thermal Threshold, 0=Disable, 1=Enable, <b>0=Default</b>
+ UINT8 UserBudgetEnable; ///< Offset 117 Flag to manually select the Budget Registers for CLTM Memory Dimms , 0=Disable, 1=Enable, <b>0=Default</b>
+ UINT8 RetrainOnFastFail; ///< Offset 118 Restart MRC in Cold mode if SW MemTest fails during Fast flow. 0 = Disabled, <b>1 = Enabled</b>
+ UINT8 PowerDownMode; ///< Offset 119 CKE Power Down Mode: <b>0xFF=AUTO</b>, 0=No Power Down, 1= APD mode, 6=PPD-DLL Off mode
+ UINT8 PwdwnIdleCounter; ///< Offset 120 CKE Power Down Mode Idle Counter: 0=Minimal, 255=Maximum, <b>0x80=0x80 DCLK</b>
+ UINT8 CmdRanksTerminated; ///< Offset 121 LPDDR: Bitmask of ranks that have CA bus terminated. <b>0x01=Default, Rank0 is terminating and Rank1 is non-terminating</b>
+ UINT16 MsHashMask; ///< Offset 122 Controller Hash Mask: 0x0001=BIT6 set(Minimal), 0x3FFF=BIT[19:6] set(Maximum), <b>0x30CE= BIT[19:18, 13:12 ,9:7] set</b>
+ UINT32 Lp5CccConfig; ///< Offset 124 BitMask where bits [3:0] are controller 0 Channel [3:0] and [7:4] are Controller 1 Channel [3:0]. 0 selects Ascending mapping and 1 selects Descending mapping.
+ UINT8 RMTLoopCount; ///< Offset 128 Indicates the Loop Count to be used for Rank Margin Tool Testing: 1=Minimal, 32=Maximum, 0=AUTO, <b>0=Default</b>
+ UINT8 MsHashInterleaveBit; ///< Offset 129 Option to select interleave Address bit. Valid values are 0 - 3 for BITS 6 - 9
+ UINT8 GearRatio; ///< Offset 130 Gear mode when SAGV is disabled: <b>0=Auto</b>, 1 - Gear1, 2 - Gear2, 4 - Gear4.
+ UINT8 Ddr4OneDpc; ///< Offset 131 DDR4 1DPC performance feature: 0 - Disabled; 1 - Enabled on DIMM0 only, 2 - Enabled on DIMM1 only; 3 - Enabled on both DIMMs. (bit [0] - DIMM0, bit [1] - DIMM1)
+ UINT32 BclkRfiFreq[MEM_MAX_SAGV_POINTS]; ///< Offset 132 Bclk RFI Frequency for each SAGV point in Hz units. 98000000Hz = 98MHz <b>0 - No RFI Tuning</b>. Range is 98Mhz-100Mhz.
+ UINT16 SaGvFreq[MEM_MAX_SAGV_POINTS]; ///< Offset 148 Frequency per SAGV point. 0 is Auto, otherwise holds the frequency value expressed as an integer: <b>0=Default</b>, 1067, 1333, 1600, 1800, 1867, etc.
+ UINT8 SaGvGear[MEM_MAX_SAGV_POINTS]; ///< Offset 156 Gear ratio per SAGV point. 0 is Auto, otherwise holds the Gear ratio expressed as an integer: <b>0=Auto</b>, 1, 2, 4
+ UINT8 IbeccProtectedRangeEnable[MEM_MAX_IBECC_REGIONS]; ///< Offset 160 Enable use of address range for ECC Protection: <b>0=Disabled</b>, 1=Enabled
+ UINT32 IbeccProtectedRangeBase[MEM_MAX_IBECC_REGIONS]; ///< Offset 168 Base address for address range of ECC Protection: [0..0x3FFFFFF]
+ UINT32 IbeccProtectedRangeMask[MEM_MAX_IBECC_REGIONS]; ///< Offset 200 Mask address for address range of ECC Protection: [1..0x3FFFFFF]
+
+ UINT8 McRefresh2X; ///< Offset 232 Deprecated from revision 19, use McRefreshRate instead
+ UINT8 Lfsr0Mask; ///< Offset 233 RH pTRR LFSR0 Mask
+ UINT8 Lfsr1Mask; ///< Offset 234 RH pTRR LFSR1 Mask
+ UINT8 CmdMirror; ///< Offset 235 BitMask where bits [3:0] are controller 0 Channel [3:0] and [7:4] are Controller 1 Channel [3:0]. 0 = No Command Mirror and 1 = Command Mirror.
+ UINT8 AllowOppRefBelowWriteThrehold; ///< Offset 236 Option to allow opportunistic refreshes while we don't exit power down.
+ UINT8 WriteThreshold; ///< Offset 237 Option to set number of writes that can be accumulated while CKE is low before CKE is asserted.
+ UINT8 PprEnable; ///< Offset 238 Post-Package Repair: 0: Disabled, 2: Hard PPR
+ UINT8 MarginLimitCheck; ///< Offset 239 Margin limit check enable: <b>0=Disable</b>, 1=L1 only, 2=L2 only, 3=Both L1 and L2
+ UINT16 MarginLimitL2; ///< Offset 240 Margin limit check L2 threshold: <b>100=Default</b>
+ UINT8 LpddrRttWr; ///< Offset 242 Initial RttWr for LP4/5 in Ohms, 0 means Auto
+ UINT8 LpddrRttCa; ///< Offset 243 Initial RttCa for LP4/5 in Ohms, 0 means Auto
+ UINT16 VddqVoltage; ///< Offset 244 DRAM voltage (Vddq) in millivolts: <b>0=Platform Default (no override)</b>, 1200=1.2V, 1350=1.35V etc.
+ UINT16 VppVoltage; ///< Offset 246 DRAM voltage (Vpp) in millivolts: <b>0=Platform Default (no override)</b>, 1800=1.8V, 2050=2.05V etc.
+ UINT8 ExtendedBankHashing; ///< Offset 248 Enable EBH (Extended Bank Hashing): 0=Disabled; <b>1 = Enabled</b>
+ UINT8 DynamicMemoryBoost; ///< Offset 249 Enable/Disable Dynamic Memory Boost Feature. Only valid if SpdProfileSelected is an XMP Profile; otherwise ignored. <b>0=Disabled</b>, 1=Enabled.
+ UINT8 IbeccErrInjControl; ///< Offset 250 In-band ECC: Error Injection Control 0: No Error Injection, 1:Inject Correctable Error Address match, 3:Inject Correctable Error on insertion counter, 5: Inject Uncorrectable Error Address match, 7:Inject Uncorrectable Error on insertion counter
+ UINT8 RealtimeMemoryFrequency; ///< Offset 251 Enable/Disable Realtime Memory Frequency feature. Only valid if SpdProfileSelected is an XMP Profile; otherwise ignored. <b>0=Disabled</b>, 1=Enabled.
+ UINT32 IbeccErrInjCount; ///< Offset 252 Number of transactions between ECC error injection
+ UINT64 IbeccErrInjAddress; ///< Offset 256 Address to match against for ECC error injection
+ UINT64 IbeccErrInjMask; ///< Offset 264 Mask to match against for ECC error injection
+ UINT8 RefreshWm; ///< Offset 272 Refresh Watermarks, 0 = Low, <b>1 = High</b>
+ UINT8 McRefreshRate; ///< Offset 273 Type of solution to be used for RHP - 0/1/2/3 = RefreshNORMAL/Refresh1x/Refresh2x/Refresh4x
+ UINT8 Reserved274[2]; ///< Offset 274-275 Reserved for natural alignment
+ UINT32 DebugValue; ///< Offset 276 Debug Value for general use
+ UINT16 tRFCpb; ///< Offset 280 User defined Memory Timing tRFCpb value, valid when SpdProfileSelected is CUSTOM_PROFILE: <b>0=AUTO</b>, 28=Maximum.
+ UINT16 tRFC2; ///< Offset 282 User defined Memory Timing tRFC2 value, valid when SpdProfileSelected is CUSTOM_PROFILE: <b>0=AUTO</b>, 28=Maximum.
+ UINT16 tRFC4; ///< Offset 284 User defined Memory Timing tRFC4 value, valid when SpdProfileSelected is CUSTOM_PROFILE: <b>0=AUTO</b>, 28=Maximum.
+ UINT16 tRRD_L; ///< Offset 286 User defined Memory Timing tRRD_L value, valid when SpdProfileSelected is CUSTOM_PROFILE: <b>0=AUTO</b>, 28=Maximum.
+ UINT16 tRRD_S; ///< Offset 288 User defined Memory Timing tRRD_S value, valid when SpdProfileSelected is CUSTOM_PROFILE: <b>0=AUTO</b>, 28=Maximum.
+ UINT16 tWTR_L; ///< Offset 290 User defined Memory Timing tWTR_L value, valid when SpdProfileSelected is CUSTOM_PROFILE: <b>0=AUTO</b>, 28=Maximum.
+ UINT16 tCCD_L; ///< Offset 292 User defined Memory Timing tCCD_L value, valid when SpdProfileSelected is CUSTOM_PROFILE: <b>0=AUTO</b>, 28=Maximum.
+ UINT16 tWTR_S; ///< Offset 294 User defined Memory Timing tWTR_S value, valid when SpdProfileSelected is CUSTOM_PROFILE: <b>0=AUTO</b>, 28=Maximum.
+ UINT64 EccErrInjAddress; ///< Offset 296 Address to match against for ECC error injection
+ UINT64 EccErrInjMask; ///< Offset 304 Mask to match against for ECC error injection
+ UINT32 EccErrInjCount; ///< Offset 312 Number of transactions between ECC error injection
+
+
+ UINT16 FreqLimitMixedConfig; ///< Offset 316 Override the reduced speed in mixed 2DPC config or non-POR 2DPC config. <b>0=Auto</b>, otherwise speed in MT/s: 1067, 1333 etc. See the possible values in MrcInterface.h
+ UINT8 FirstDimmBitMask; ///< Offset 318 Defines which DIMM should be populated first on a 2DPC board.
+ ///< 4 bit mask: Bit[0]: MC0 DIMM0, Bit[1]: MC0 DIMM1, Bit[2]: MC1 DIMM0, Bit[3]: MC1 DIMM1.
+ ///< For each MC, the first DIMM to be populated should be set to '1'.
+ ///< Note: this mask is only for non-ECC DIMM.
+ UINT8 UserBd; ///< Offset 319 MrcBoardType
+ ///< 1 - Desktop 1DPC
+ ///< 2 - Desktop 2DPC, Daisy Chain, far DIMM should be populated first
+ ///< 3 - Desktop 2DPC, T-topology with asymmetrical DIMM0/1 routing, has particular DIMM population order
+ ///< 4 - Desktop 2DPC, T-topology with symmetrical DIMM0/1 routing, no particular DIMM population order
+ ///< 5 - ULT Mobile
+ UINT8 SagvSwitchFactorIA; ///< Offset 320 Sagv Switch Factor: <b>1 </b>, 50=Maximum, default 30.
+ UINT8 SagvSwitchFactorGT; ///< Offset 321 Sagv Switch Factor: <b>1 </b>, 50=Maximum, default 30.
+ UINT8 SagvSwitchFactorIO; ///< Offset 322 Sagv Switch Factor: <b>1 </b>, 50=Maximum, default 30.
+ UINT8 SagvSwitchFactorStall; ///< Offset 323 Sagv Switch Factor: <b>1 </b>, 50=Maximum, default 30.
+ UINT8 SagvHeuristicsUpControl;///< Offset 324 Sagv duration in ms before heuristics up: <b>1 </b>, 50=Maximum, default 1ms.
+ UINT8 SagvHeuristicsDownControl; ///< Offset 325 Sagv duration in ms before heuristics down: <b>1 </b>, 50=Maximum, default 1ms.
+ UINT16 FreqLimitMixedConfig_1R1R_8GB; ///< Offset 326 The frequency limit for mixed DIMM configuration 1R1R_8GB (1R 8GB and 1R 8GB in one channel).
+ ///< It's to be set by customer. Customer can connect it to a setup option, or an UPD, etc. By default, the value will be 2000.
+ UINT16 FreqLimitMixedConfig_1R1R_16GB; ///< Offset 328 The frequency limit for mixed DIMM configuration 1R1R_16GB (1R 16GB and 1R 16GB in one channel).
+ ///< It's to be set by customer. Customer can connect it to a setup option, or an UPD, etc. By default, the value will be 2000.
+ UINT16 FreqLimitMixedConfig_1R1R_8GB_16GB; ///< Offset 330 The frequency limit for mixed DIMM configuration 1R1R_8GB_16GB (1R 8GB and 1R 16GB in one channel).
+ ///< It's to be set by customer. Customer can connect it to a setup option, or an UPD, etc. By default, the value will be 2000.
+ UINT16 FreqLimitMixedConfig_2R2R; ///< Offset 332 The frequency limit for mixed DIMM configuration 2R_2R (2R 32GB and 2R 32GB in one channel).
+ ///< It's to be set by customer. Customer can connect it to a setup option, or an UPD, etc. By default, the value will be 2000.
+ UINT16 LctCmdEyeWidth; ///< Offset 334 LCT Command eyewidth
+ UINT8 FirstDimmBitMaskEcc; ///< Offset 336 Defines which ECC DIMM should be populated first on a 2DPC board.
+ ///< 4 bit mask: Bit[0]: MC0 DIMM0, Bit[1]: MC0 DIMM1, Bit[2]: MC1 DIMM0, Bit[3]: MC1 DIMM1.
+ ///< For each MC, the first DIMM to be populated should be set to '1'.
+ ///< For example, if one MC is T-topology, there is no special population rule, can put it as 11 for this MC and it means either D0 or D1 can be
+ ///< be populated firstly.
+ ///< Note: this mask is only for ECC DIMM, not for non-ECC DIMM.
+ UINT8 Lp5BankMode; ///< Offset 337 LP5 Bank Mode
+ UINT8 OverloadSAM; ///< Offset 338 Overload SAM to copy the sagv frquency point.
+ UINT8 Reserved339[5]; ///< Offset 339-343 Reserved for natural alignment
+} MEMORY_CONFIGURATION;
+
+/// Memory Configuration
+/// The contents of this structure are not CRC'd by the MRC for option change detection.
+/// <b>Revision 1</b>: - Initial version.
+/// <b>Revision 2</b>: - Added MemTestOnWarmBoot
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Block Header
+ SA_FUNCTION_CALLS SaCall; ///< Offset 28 Function calls into the SA.
+ SA_MEMORY_FUNCTIONS MrcCall; ///< Offset 212 Function calls into the MRC.
+ SPD_DATA_BUFFER *SpdData; ///< Offset 236 Memory SPD data, will be used by the MRC when SPD SmBus address is zero.
+ SA_MEMORY_DQDQS_MAPPING *DqDqsMap; ///< Offset 240 LPDDR DQ bit and DQS byte swizzling between CPU and DRAM.
+ SA_MEMORY_RCOMP *RcompData; ///< Offset 244 DDR RCOMP resistors and target values.
+ UINT64 PlatformMemorySize; ///< Offset 248 The minimum platform memory size required to pass control into DXE
+ UINT32 CleanMemory:1; ///< Offset 256 Ask MRC to clear memory content: <b>FALSE=Do not Clear Memory</b>; TRUE=Clear Memory
+ UINT32 ReservedBits5:31;
+ /**
+ Sets the serial debug message level\n
+ 0x00 = Disabled\n
+ 0x01 = Errors only\n
+ 0x02 = Errors and Warnings\n
+ <b>0x03 = Errors, Warnings, and Info</b>\n
+ 0x04 = Errors, Warnings, Info, and Events\n
+ 0x05 = Displays Memory Init Execution Time Summary only\n
+ **/
+ UINT8 SerialDebugLevel; ///< Offset 260
+ UINT8 MemTestOnWarmBoot; ///< Offset 261 Run Base Memory Test On WarmBoot: 0=Disabled, <b>1=Enabled</b>
+ UINT8 Reserved11[2]; ///< Offset 262 - 263 Reserved
+} MEMORY_CONFIG_NO_CRC;
+#pragma pack(pop)
+
+#endif // _MEMORY_CONFIG_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/PchDmi/PchDmiConfig.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/PchDmi/PchDmiConfig.h
new file mode 100644
index 0000000000..84cc21091f
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/PchDmi/PchDmiConfig.h
@@ -0,0 +1,65 @@
+/** @file
+ DMI policy
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _PCH_DMI_CONFIG_H_
+#define _PCH_DMI_CONFIG_H_
+
+extern EFI_GUID gPchDmiConfigGuid;
+
+/*
+<b>Revision 1</b>: - Initial version.
+*/
+#define PCH_DMI_PREMEM_CONFIG_REVISION 1
+extern EFI_GUID gPchDmiPreMemConfigGuid;
+
+#pragma pack (push,1)
+
+#define PCH_DMI_HWEQ_COEFFS_MAX 8
+/**
+ Lane specific Dmi Gen3, Gen4 equalization parameters.
+**/
+typedef struct {
+ UINT8 Cm; ///< Coefficient C-1
+ UINT8 Cp; ///< Coefficient C+1
+ UINT8 Rsvd0[2]; ///< Reserved bytes
+} PCH_DMI_EQ_PARAM;
+
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Config Block
+ PCH_DMI_EQ_PARAM DmiHwEqGen3CoeffList[PCH_DMI_HWEQ_COEFFS_MAX];
+ UINT8 DmiHweq;
+ UINT8 Reserved[3];
+} PCH_DMI_PREMEM_CONFIG;
+
+
+/**
+ The PCH_DMI_CONFIG block describes the expected configuration of the PCH for DMI.
+ <b>Revision 1</b>:
+ - Initial version.
+**/
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Config Block Header
+
+ UINT32 PwrOptEnable : 1; ///< <b>0: Disable</b>; 1: Enable DMI Power Optimizer on PCH side.
+ UINT32 DmiAspmCtrl : 8; ///< ASPM configuration on the PCH side of the DMI/OPI Link. Default is <b>PchPcieAspmAutoConfig</b>
+ UINT32 CwbEnable : 1; ///< 0: Disable; <b>1: Enable</b> Central Write Buffer feature configurable and enabled by default
+ UINT32 L1RpCtl : 1; ///< 0: Disable; <b>1: Enable</b> Allow DMI enter L1 when all root ports are in L1, L0s or link down. Disabled by default.
+ /**
+ When set to TRUE turns on:
+ - L1 State Controller Power Gating
+ - L1 State PHY Data Lane Power Gating
+ - PHY Common Lane Power Gating
+ - Hardware Autonomous Enable
+ - PMC Request Enable and Sleep Enable
+ **/
+ UINT32 DmiPowerReduction : 1;
+ UINT32 ClockGating : 1; ///< 0: Disable; 1: Enable clock gating.
+ UINT32 Rsvdbits : 19; ///< Reserved bits
+} PCH_DMI_CONFIG;
+
+#pragma pack (pop)
+
+#endif // _PCH_DMI_CONFIG_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/PcieRp/PchPcieRp/PchPcieRpConfig.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/PcieRp/PchPcieRp/PchPcieRpConfig.h
new file mode 100644
index 0000000000..d97f3b878a
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/PcieRp/PchPcieRp/PchPcieRpConfig.h
@@ -0,0 +1,180 @@
+/** @file
+ PCH Pcie root port policy
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _PCH_PCIERP_CONFIG_H_
+#define _PCH_PCIERP_CONFIG_H_
+
+#include <PchLimits.h>
+#include <PcieConfig.h>
+#include <ConfigBlock.h>
+
+
+
+
+
+/*
+ Making any setup structure change after code frozen
+ will need to maintain backward compatibility, bump up
+ structure revision and update below history table\n
+
+<b>Revision 1</b>: - Initial version.
+*/
+#define PCIE_RP_DXE_CONFIG_REVISION 1
+
+extern EFI_GUID gPchPcieConfigGuid;
+extern EFI_GUID gPcieRpPreMemConfigGuid;
+
+#pragma pack (push,1)
+
+typedef enum {
+ PchPcieOverrideDisabled = 0,
+ PchPcieL1L2Override = 0x01,
+ PchPcieL1SubstatesOverride = 0x02,
+ PchPcieL1L2AndL1SubstatesOverride = 0x03,
+ PchPcieLtrOverride = 0x04
+} PCH_PCIE_OVERRIDE_CONFIG;
+
+///
+/// The values before AutoConfig match the setting of PCI Express Base Specification 1.1, please be careful for adding new feature
+///
+typedef enum {
+ PchPcieAspmDisabled,
+ PchPcieAspmL0s,
+ PchPcieAspmL1,
+ PchPcieAspmL0sL1,
+ PchPcieAspmAutoConfig,
+ PchPcieAspmMax
+} PCH_PCIE_ASPM_CONTROL;
+
+/**
+ Refer to PCH EDS for the PCH implementation values corresponding
+ to below PCI-E spec defined ranges
+**/
+typedef enum {
+ PchPcieL1SubstatesDisabled,
+ PchPcieL1SubstatesL1_1,
+ PchPcieL1SubstatesL1_1_2,
+ PchPcieL1SubstatesMax
+} PCH_PCIE_L1SUBSTATES_CONTROL;
+
+enum PCH_PCIE_MAX_PAYLOAD {
+ PchPcieMaxPayload128 = 0,
+ PchPcieMaxPayload256,
+ PchPcieMaxPayloadMax
+};
+
+
+/**
+ PCH_PCIE_CLOCK describes PCIe source clock generated by PCH.
+**/
+typedef struct {
+ UINT8 Usage; ///< Purpose of given clock (see PCH_PCIE_CLOCK_USAGE). Default: Unused, 0xFF
+ UINT8 ClkReq; ///< ClkSrc - ClkReq mapping. Default: 1:1 mapping with Clock numbers
+ UINT8 RsvdBytes[2]; ///< Reserved byte
+ UINT32 ClkReqGpioPinMux; /// Muxed GPIO details. Refer GPIO_*_MUXING_SRC_CLKREQ_x*
+} PCH_PCIE_CLOCK;
+
+
+/**
+ The PCH_PCI_EXPRESS_ROOT_PORT_CONFIG describe the feature and capability of each PCH PCIe root port.
+**/
+typedef struct {
+ PCIE_ROOT_PORT_COMMON_CONFIG PcieRpCommonConfig; ///an instance of Pcie Common Config
+ UINT8 ExtSync; ///< Indicate whether the extended synch is enabled. <b>0: Disable</b>; 1: Enable.
+ //
+ // Error handlings
+ //
+ UINT8 SystemErrorEnable; ///< Indicate whether the System Error is enabled. <b>0: Disable</b>; 1: Enable.
+ /**
+ The Multiple VC (MVC) supports hardware to avoid HoQ block for latency sensitive TC.
+ Currently it is only applicable to Root Ports with 2pX4 port configuration with 2 VCs,or
+ DMI port configuration with 3 VCs. For Root Ports 2pX4 configuration, two RPs (RP0,
+ RP2) shall support two PCIe VCs (VC0 & VC1) and the other RPs (RP1, RP3) shall be
+ disabled.
+ <b>0: Disable</b>; 1: Enable
+ **/
+ UINT8 MvcEnabled;
+ /**
+ Virtual Pin Port is industry standard introduced to PCIe Hot Plug support in systems
+ when GPIO pins expansion is needed. It is server specific feature.
+ <b>0x00: Default</b>; 0xFF: Disabled
+ **/
+ UINT8 VppPort;
+ UINT8 VppAddress; ///< PCIe Hot Plug VPP SMBus Address. Default is zero.
+ UINT8 RsvdBytes0[3]; ///< Reserved bytes
+} PCH_PCIE_ROOT_PORT_CONFIG;
+
+/**
+ The PCH_PCIE_CONFIG block describes the expected configuration of the PCH PCI Express controllers
+ <b>Revision 1</b>:
+ - Initial version.
+ <b>Revision 2</b>:
+ - Moved EnablePort8xhDecode policy to PCIE_COMMON_CONFIG
+**/
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Config Block Header
+ ///
+ /// These members describe the configuration of each PCH PCIe root port.
+ ///
+ PCIE_COMMON_CONFIG PcieCommonConfig;
+ PCH_PCIE_ROOT_PORT_CONFIG RootPort[PCH_MAX_PCIE_ROOT_PORTS];
+ PCH_PCIE_ROOT_PORT_CONFIG DmiPort;
+
+ ///
+ /// <b>(Test)</b> The Index of PCIe Port that is selected for Port8xh Decode (0 Based)
+ ///
+ UINT8 PchPciePort8xhDecodePortIndex;
+ UINT8 DmiPowerReduction;
+ UINT8 RsvdBytes0[2];
+} PCH_PCIE_CONFIG;
+
+/**
+ The PCH_PCIE_RP_PREMEM_CONFIG block describes early configuration of the PCH PCI Express controllers
+ <b>Revision 1</b>:
+ - Initial version.
+**/
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Config Block Header
+ /**
+ Root Port enabling mask.
+ Bit0 presents RP1, Bit1 presents RP2, and so on.
+ 0: Disable; <b>1: Enable</b>.
+ **/
+ UINT32 RpEnabledMask;
+ /// Configuration of PCIe source clocks
+ ///
+ PCH_PCIE_CLOCK PcieClock[PCH_MAX_PCIE_CLOCKS];
+
+ /**
+ Per Controller Bifurcation Configuration
+ <b>0: Disabled</b>; 1: 4x1; 2: 1x2_2x1; 3: 2x2; 4: 1x4; 5: 4x2; 6: 1x4_2x2; 7: 2x2_1x4; 8: 2x4; 9: 1x8 (see: PCIE_BIFURCATION_CONFIG)
+ **/
+ UINT8 Bifurcation[PCH_MAX_PCIE_CONTROLLERS];
+ UINT8 Rsvd4[(4 - PCH_MAX_PCIE_CONTROLLERS % 4) % 4];
+} PCH_PCIE_RP_PREMEM_CONFIG;
+
+/**
+ The PCIE_RP_DXE_CONFIG block describes the expected configuration of the PCH PCI Express controllers in DXE phase
+
+ <b>Revision 1</b>:
+ - Init version
+**/
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Config Block Header
+
+ /**
+ PCIe device override table
+ The PCIe device table is being used to override PCIe device ASPM settings.
+ And it's only used in DXE phase.
+ Please refer to PCIE_DEVICE_OVERRIDE structure for the table.
+ Last entry VendorId must be 0.
+ **/
+ PCIE_DEVICE_OVERRIDE *PcieDeviceOverrideTablePtr;
+} PCIE_RP_DXE_CONFIG;
+
+#pragma pack (pop)
+
+#endif // _PCH_PCIERP_CONFIG_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/PcieRp/PcieConfig.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/PcieRp/PcieConfig.h
new file mode 100644
index 0000000000..07a5644f43
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/PcieRp/PcieConfig.h
@@ -0,0 +1,408 @@
+/** @file
+ PCIe Config Block
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _PCIE_CONFIG_H_
+#define _PCIE_CONFIG_H_
+#include <CpuPcieInfo.h>
+
+#define PCIE_LINK_EQ_COEFFICIENTS_MAX 10
+#define PCIE_LINK_EQ_PRESETS_MAX 11
+extern EFI_GUID gPcieConfigGuid;
+
+#pragma pack (push,1)
+
+enum PCIE_COMPLETION_TIMEOUT {
+ PcieCompletionTO_Default,
+ PcieCompletionTO_50_100us,
+ PcieCompletionTO_1_10ms,
+ PcieCompletionTO_16_55ms,
+ PcieCompletionTO_65_210ms,
+ PcieCompletionTO_260_900ms,
+ PcieCompletionTO_1_3P5s,
+ PcieCompletionTO_4_13s,
+ PcieCompletionTO_17_64s,
+ PcieCompletionTO_Disabled
+};
+
+typedef enum {
+ PcieAuto,
+ PcieGen1,
+ PcieGen2,
+ PcieGen3,
+ PcieGen4,
+ PcieGen5
+} PCIE_SPEED;
+
+typedef enum {
+ PcieDisabled,
+ PcieL1SUB_1,
+ PcieL1SUB_1_2
+}L1_SUBSTATES;
+
+/**
+ Represent lane specific PCIe Gen3 equalization parameters.
+**/
+typedef struct {
+ UINT8 Cm; ///< Coefficient C-1
+ UINT8 Cp; ///< Coefficient C+1
+ UINT8 Rsvd0[2]; ///< Reserved bytes
+} PCIE_EQ_PARAM;
+
+typedef struct {
+ UINT16 LtrMaxSnoopLatency; ///< <b>(Test)</b> Latency Tolerance Reporting, Max Snoop Latency.
+ UINT16 LtrMaxNoSnoopLatency; ///< <b>(Test)</b> Latency Tolerance Reporting, Max Non-Snoop Latency.
+ UINT8 SnoopLatencyOverrideMode; ///< <b>(Test)</b> Latency Tolerance Reporting, Snoop Latency Override Mode.
+ UINT8 SnoopLatencyOverrideMultiplier; ///< <b>(Test)</b> Latency Tolerance Reporting, Snoop Latency Override Multiplier.
+ UINT16 SnoopLatencyOverrideValue; ///< <b>(Test)</b> Latency Tolerance Reporting, Snoop Latency Override Value.
+ UINT8 NonSnoopLatencyOverrideMode; ///< <b>(Test)</b> Latency Tolerance Reporting, Non-Snoop Latency Override Mode.
+ UINT8 NonSnoopLatencyOverrideMultiplier; ///< <b>(Test)</b> Latency Tolerance Reporting, Non-Snoop Latency Override Multiplier.
+ UINT16 NonSnoopLatencyOverrideValue; ///< <b>(Test)</b> Latency Tolerance Reporting, Non-Snoop Latency Override Value.
+ UINT8 LtrConfigLock; ///< <b>0: Disable</b>; 1: Enable.
+ UINT8 ForceLtrOverride;
+ UINT16 RsvdByte1;
+} PCIE_LTR_CONFIG;
+
+
+/**
+ Specifies the form factor that the slot
+ implements. For custom form factors that
+ do not require any special handling please
+ set PcieFormFactorOther.
+**/
+typedef enum {
+ PcieFormFactorOther = 0,
+ PcieFormFactorCem,
+ PcieFormFactorMiniPci,
+ PcieFormFactorM2,
+ PcieFormFactorOcuLink,
+ PcieFormFactorExpressModule, // Also known as Server IO module(SIOM)
+ PcieFormFactorExpressCard,
+ PcieFormFactorU2 // Also known as SF-8639
+} PCIE_FORM_FACTOR;
+
+typedef enum {
+ PcieLinkHardwareEq = 0, ///< Hardware is responsible for performing coefficient/preset search.
+ PcieLinkFixedEq ///< No coefficient/preset search is performed. Fixed values are used.
+} PCIE_LINK_EQ_METHOD;
+
+typedef enum {
+ PcieLinkEqPresetMode = 0, ///< Use presets during PCIe link equalization
+ PcieLinkEqCoefficientMode ///< Use coefficients during PCIe link equalization
+} PCIE_LINK_EQ_MODE;
+
+typedef struct {
+ UINT32 PreCursor; ///< Pre-cursor coefficient
+ UINT32 PostCursor; ///< Post-cursor coefficient
+} PCIE_LINK_EQ_COEFFICIENTS;
+
+/**
+ PCIe Link EQ Platform Settings
+**/
+typedef struct {
+ UINT8 PcieLinkEqMethod; ///< Tells BIOS which link EQ method should be used for this port. Please refer to PCIE_LINK_EQ_METHOD for details of supported methods. Default: PcieLinkHardwareEq
+ UINT8 PcieLinkEqMode; ///< Tells BIOS which mode should be used for PCIe link EQ. Please refer to PCIE_LINK_EQ_MODE for details of supported modes. Default: depends on SoC
+ /**
+ Specifies if BIOS should perform local transmitter override during phase 2 of EQ process.
+ If enabled value in Ph2LocalTransmitterOverridePreset must be valid.
+ <b>0: Disabled</b>; 1: Enabled
+ **/
+ UINT8 LocalTransmitterOverrideEnable;
+ /**
+ Tells BIOS how many presets/coefficients should be used during link EQ.
+ Entries in the Ph3CoefficientsList or Ph3PresetList(depending on chosen mode) need to be valid up to the number specified in this field.
+ **/
+ UINT8 Ph3NumberOfPresetsOrCoefficients;
+
+ PCIE_LINK_EQ_COEFFICIENTS Ph3CoefficientsList[PCIE_LINK_EQ_COEFFICIENTS_MAX]; ///< List of the PCIe coefficients to be used during equalization process. Only valid if PcieLinkEqMode is PcieLinkEqCoefficientMode
+ UINT32 Ph3PresetList[PCIE_LINK_EQ_PRESETS_MAX]; ///< List of the PCIe preset values to be used during equalization process. Only valid if PcieLinkEqMode is PcieLinkEqPresetMode
+ UINT32 Ph1DownstreamPortTransmitterPreset; ///< Specifies the value of the downstream port transmitter preset to be used during phase 1 of the equalization process. Will be applied to all lanes
+ UINT32 Ph1UpstreamPortTransmitterPreset; ///< Specifies the value of the upstream port transmitter preset to be used during phase 1 of the equalization process. Will be applied to all lanes
+ /**
+ Specifies the preset that should be used during local transmitter override during phase 2 of EQ process.
+ Used only if LocalTransmitterOverrideEnable is TRUE. Will be applied to all PCIe lanes of the root port.
+ Valid up to the PCIE_LINK_EQ_PRESET_MAX value. <b>Default: 0<\b>
+ **/
+ UINT32 Ph2LocalTransmitterOverridePreset;
+ UINT32 PCETTimer; ///< PCET Timer value for single PCIe speed.
+ UINT8 RemotePresetCoeffoverride; ///< Remote Transmitter Preset Coefficient Override for single PCIe speed.
+ /**
+ PCIe Equalization Phase 3 Enable Control
+ - <b>Disabled</b> (0x0) : Disable phase 3 (Default)
+ - Enabled (0x1) : Enable phase 3
+ **/
+ UINT8 EqPh3Bypass;
+ /**
+ PCIe Equalization Phase 2-3 Enable Control
+ - <b>Disabled</b> (0x0) : Disable Phase 2 - Phase 3 (Default)
+ - Enabled (0x1) : Enable Phase 2 - Phase 3
+ **/
+ UINT8 EqPh23Bypass;
+ UINT8 TsLockTimer; ///< 8.0GT/s Training Sequence Wait Latency For Presets / Coefficients Evaluation - Gen3 TS Lock Timer
+} PCIE_LINK_EQ_PLATFORM_SETTINGS;
+
+//Note: This structure will be expanded to hold all common PCIe policies between SA and PCH RootPort
+typedef struct {
+ UINT32 HotPlug : 1; ///< Indicate whether the root port is hot plug available. <b>0: Disable</b>; 1: Enable.
+ UINT32 PmSci : 1; ///< Indicate whether the root port power manager SCI is enabled. 0: Disable; <b>1: Enable</b>.
+ UINT32 TransmitterHalfSwing : 1; ///< Indicate whether the Transmitter Half Swing is enabled. <b>0: Disable</b>; 1: Enable.
+ UINT32 AcsEnabled : 1; ///< Indicate whether the ACS is enabled. 0: Disable; <b>1: Enable</b>.
+ //
+ // Error handlings
+ //
+ UINT32 AdvancedErrorReporting : 1; ///< Indicate whether the Advanced Error Reporting is enabled. <b>0: Disable</b>; 1: Enable.
+ UINT32 UnsupportedRequestReport : 1; ///< Indicate whether the Unsupported Request Report is enabled. <b>0: Disable</b>; 1: Enable.
+ UINT32 FatalErrorReport : 1; ///< Indicate whether the Fatal Error Report is enabled. <b>0: Disable</b>; 1: Enable.
+ UINT32 NoFatalErrorReport : 1; ///< Indicate whether the No Fatal Error Report is enabled. <b>0: Disable</b>; 1: Enable.
+ UINT32 CorrectableErrorReport : 1; ///< Indicate whether the Correctable Error Report is enabled. <b>0: Disable</b>; 1: Enable.
+ UINT32 SystemErrorOnFatalError : 1; ///< Indicate whether the System Error on Fatal Error is enabled. <b>0: Disable</b>; 1: Enable.
+ UINT32 SystemErrorOnNonFatalError : 1; ///< Indicate whether the System Error on Non Fatal Error is enabled. <b>0: Disable</b>; 1: Enable.
+ UINT32 SystemErrorOnCorrectableError : 1; ///< Indicate whether the System Error on Correctable Error is enabled. <b>0: Disable</b>; 1: Enable.
+ /**
+ Max Payload Size supported, Default <b>128B</b>, see enum CPU_PCIE_MAX_PAYLOAD
+ Changes Max Payload Size Supported field in Device Capabilities of the root port.
+ **/
+ UINT32 MaxPayload : 2;
+ UINT32 DpcEnabled : 1; ///< Downstream Port Containment. 0: Disable; <b>1: Enable</b>
+ UINT32 RpDpcExtensionsEnabled : 1; ///< RP Extensions for Downstream Port Containment. 0: Disable; <b>1: Enable</b>
+ /**
+ Indicates how this root port is connected to endpoint. 0: built-in device; <b>1: slot</b>
+ Built-in is incompatible with hotplug-capable ports.
+ **/
+ UINT32 SlotImplemented : 1;
+ UINT32 PtmEnabled : 1; ///< Enables PTM capability
+ UINT32 SlotPowerLimitScale : 2; ///< <b>(Test)</b> Specifies scale used for slot power limit value. Leave as 0 to set to default. Default is <b>zero</b>.
+ UINT32 SlotPowerLimitValue : 12; //< <b>(Test)</b> Specifies upper limit on power supplies by slot. Leave as 0 to set to default. Default is <b>zero</b>.
+ /**
+ Probe CLKREQ# signal before enabling CLKREQ# based power management.
+ Conforming device shall hold CLKREQ# low until CPM is enabled. This feature attempts
+ to verify CLKREQ# signal is connected by testing pad state before enabling CPM.
+ In particular this helps to avoid issues with open-ended PCIe slots.
+ This is only applicable to non hot-plug ports.
+ <b>0: Disable</b>; 1: Enable.
+ **/
+ UINT32 ClkReqDetect : 1;
+ /**
+ Set if the slot supports manually operated retention latch.
+ **/
+ UINT32 MrlSensorPresent : 1;
+ UINT32 RelaxedOrder : 1;
+ UINT32 NoSnoop : 1;
+ ///
+ /// This member describes whether Peer Memory Writes are enabled on the platform. <b>0: Disable</b>; 1: Enable.
+ ///
+ UINT32 EnablePeerMemoryWrite : 1;
+ ///
+ /// This member describes whether the PCI Express Clock Gating for each root port
+ /// is enabled by platform modules. <b>0: Disable</b>; 1: Enable.
+ ///
+ UINT32 ClockGating : 1;
+ ///
+ /// This member describes whether the PCI Express Power Gating for each root port
+ /// is enabled by platform modules. <b>0: Disable</b>; 1: Enable.
+ ///
+ UINT32 PowerGating : 1;
+ UINT32 RsvdBits0 : 25; ///< Reserved bits.
+ /**
+ PCIe Gen3 Equalization Phase 3 Method (see CPU_PCIE_EQ_METHOD).
+ 0: DEPRECATED, hardware equalization; <b>1: hardware equalization</b>; 4: Fixed Coefficients
+ **/
+ UINT8 Gen3EqPh3Method;
+ UINT8 PhysicalSlotNumber; ///< Indicates the slot number for the root port. Default is the value as root port index.
+ UINT8 CompletionTimeout; ///< The completion timeout configuration of the root port (see: CPU_PCIE_COMPLETION_TIMEOUT). Default is <b>PchPcieCompletionTO_Default</b>.
+ //
+ // Power Management
+ //
+ UINT8 Aspm; ///< The ASPM configuration of the root port (see: CPU_PCIE_ASPM_CONTROL). Default is <b>PchPcieAspmAutoConfig</b>.
+ UINT8 L1Substates; ///< The L1 Substates configuration of the root port (see: CPU_PCIE_L1SUBSTATES_CONTROL). Default is <b>PchPcieL1SubstatesL1_1_2</b>.
+ UINT8 LtrEnable; ///< Latency Tolerance Reporting Mechanism. <b>0: Disable</b>; 1: Enable.
+ UINT8 EnableCpm; ///< Enables Clock Power Management; even if disabled, CLKREQ# signal can still be controlled by L1 PM substates mechanism
+ UINT8 PcieSpeed; ///< Contains speed of PCIe bus (see: PCIE_SPEED)
+ /**
+ <b>(Test)</b>
+ Forces LTR override to be permanent
+ The default way LTR override works is:
+ rootport uses LTR override values provided by BIOS until connected device sends an LTR message, then it will use values from the message
+ This settings allows force override of LTR mechanism. If it's enabled, then:
+ rootport will use LTR override values provided by BIOS forever; LTR messages sent from connected device will be ignored
+ **/
+ PCIE_LTR_CONFIG PcieRpLtrConfig; ///< <b>(Test)</b> Latency Tolerance Reporting Policies including LTR limit and Override
+ /**
+ The number of milliseconds reference code will wait for link to exit Detect state for enabled ports
+ before assuming there is no device and potentially disabling the port.
+ It's assumed that the link will exit detect state before root port initialization (sufficient time
+ elapsed since PLTRST de-assertion) therefore default timeout is zero. However this might be useful
+ if device power-up seqence is controlled by BIOS or a specific device requires more time to detect.
+ In case of non-common clock enabled the default timout is 15ms.
+ <b>Default: 0</b>
+ **/
+ UINT16 DetectTimeoutMs;
+ UINT8 FormFactor; // Please check PCIE_FORM_FACTOR for supported values
+ UINT8 L1Low; ///< L1.LOW enable/disable. <b>0: Disable</b>; 1: Enable.
+ UINT8 LinkDownGpios;
+ ///
+ /// <b>0: Use project default equalization settings</b>; 1: Use equalization settings from PcieLinkEqPlatformSettings
+ ///
+ UINT8 OverrideEqualizationDefaults;
+ UINT8 Reserved[2];
+ PCIE_LINK_EQ_PLATFORM_SETTINGS PcieGen3LinkEqPlatformSettings; ///< Global PCIe Gen3 link EQ settings that BIOS will use during PCIe link EQ for every port.
+ PCIE_LINK_EQ_PLATFORM_SETTINGS PcieGen4LinkEqPlatformSettings; ///< Global PCIe Gen4 link EQ settings that BIOS will use during PCIe link EQ for every port.
+ PCIE_LINK_EQ_PLATFORM_SETTINGS PcieGen5LinkEqPlatformSettings; ///< Global PCIe Gen5 link EQ settings that BIOS will use during PCIe link EQ for every port.
+} PCIE_ROOT_PORT_COMMON_CONFIG;
+
+/**
+ PCIe Common Config
+ @note This structure will be expanded to hold all common PCIe policies between SA and PCH
+**/
+typedef struct {
+ /**
+ RpFunctionSwap allows BIOS to use root port function number swapping when root port of function 0 is disabled.
+ A PCIE device can have higher functions only when Function0 exists. To satisfy this requirement,
+ BIOS will always enable Function0 of a device that contains more than 0 enabled root ports.
+ - <b>Enabled: One of enabled root ports get assigned to Function0.</b>
+ This offers no guarantee that any particular root port will be available at a specific DevNr:FuncNr location
+ - Disabled: Root port that corresponds to Function0 will be kept visible even though it might be not used.
+ That way rootport - to - DevNr:FuncNr assignment is constant. This option will impact ports 1, 9, 17.
+ NOTE: This option will not work if ports 1, 9, 17 are fused or configured for RST PCIe storage or disabled through policy
+ In other words, it only affects ports that would become hidden because they have no device connected.
+ NOTE: Disabling function swap may have adverse impact on power management. This option should ONLY
+ be used when each one of root ports 1, 9, 17:
+ - is configured as PCIe and has correctly configured ClkReq signal, or
+ - does not own any mPhy lanes (they are configured as SATA or USB)
+ **/
+ UINT32 RpFunctionSwap : 1;
+ /**
+ Compliance Test Mode shall be enabled when using Compliance Load Board.
+ <b>0: Disable</b>, 1: Enable
+ **/
+ UINT32 ComplianceTestMode : 1;
+ UINT32 RsvdBits0 : 30; ///< Reserved bits
+ ///
+ /// <b>(Test)</b> This member describes whether PCIE root port Port 8xh Decode is enabled. <b>0: Disable</b>; 1: Enable.
+ ///
+ UINT8 EnablePort8xhDecode;
+ UINT8 RsvdBytes0[3];
+ ///
+ /// List of coefficients used during equalization (applicable to both software and hardware EQ)
+ /// Deprecated Policy
+ ///
+ PCIE_EQ_PARAM HwEqGen3CoeffList[PCIE_HWEQ_COEFFS_MAX];
+} PCIE_COMMON_CONFIG;
+
+typedef struct {
+ PCIE_EQ_PARAM HwEqGen3CoeffList[CPU_PCIE_MAX_ROOT_PORTS][PCIE_HWEQ_COEFFS_MAX];
+ PCIE_EQ_PARAM HwEqGen4CoeffList[CPU_PCIE_MAX_ROOT_PORTS][PCIE_HWEQ_COEFFS_MAX];
+ PCIE_EQ_PARAM HwEqGen5CoeffList[CPU_PCIE_MAX_ROOT_PORTS][PCIE_HWEQ_COEFFS_MAX];
+} PCIE_COMMON_CONFIG2;
+
+
+/**
+ PCIe device table entry entry
+
+ The PCIe device table is being used to override PCIe device ASPM settings.
+ To take effect table consisting of such entries must be instelled as PPI
+ on gPchPcieDeviceTablePpiGuid.
+ Last entry VendorId must be 0.
+**/
+typedef struct {
+ UINT16 VendorId; ///< The vendor Id of Pci Express card ASPM setting override, 0xFFFF means any Vendor ID
+ UINT16 DeviceId; ///< The Device Id of Pci Express card ASPM setting override, 0xFFFF means any Device ID
+ UINT8 RevId; ///< The Rev Id of Pci Express card ASPM setting override, 0xFF means all steppings
+ UINT8 BaseClassCode; ///< The Base Class Code of Pci Express card ASPM setting override, 0xFF means all base class
+ UINT8 SubClassCode; ///< The Sub Class Code of Pci Express card ASPM setting override, 0xFF means all sub class
+ UINT8 EndPointAspm; ///< Override device ASPM (see: PCH_PCIE_ASPM_CONTROL)
+ ///< Bit 1 must be set in OverrideConfig for this field to take effect
+ UINT16 OverrideConfig; ///< The override config bitmap (see: PCH_PCIE_OVERRIDE_CONFIG).
+ /**
+ The L1Substates Capability Offset Override. (applicable if bit 2 is set in OverrideConfig)
+ This field can be zero if only the L1 Substate value is going to be override.
+ **/
+ UINT16 L1SubstatesCapOffset;
+ /**
+ L1 Substate Capability Mask. (applicable if bit 2 is set in OverrideConfig)
+ Set to zero then the L1 Substate Capability [3:0] is ignored, and only L1s values are override.
+ Only bit [3:0] are applicable. Other bits are ignored.
+ **/
+ UINT8 L1SubstatesCapMask;
+ /**
+ L1 Substate Port Common Mode Restore Time Override. (applicable if bit 2 is set in OverrideConfig)
+ L1sCommonModeRestoreTime and L1sTpowerOnScale can have a valid value of 0, but not the L1sTpowerOnValue.
+ If L1sTpowerOnValue is zero, all L1sCommonModeRestoreTime, L1sTpowerOnScale, and L1sTpowerOnValue are ignored,
+ and only L1SubstatesCapOffset is override.
+ **/
+ UINT8 L1sCommonModeRestoreTime;
+ /**
+ L1 Substate Port Tpower_on Scale Override. (applicable if bit 2 is set in OverrideConfig)
+ L1sCommonModeRestoreTime and L1sTpowerOnScale can have a valid value of 0, but not the L1sTpowerOnValue.
+ If L1sTpowerOnValue is zero, all L1sCommonModeRestoreTime, L1sTpowerOnScale, and L1sTpowerOnValue are ignored,
+ and only L1SubstatesCapOffset is override.
+ **/
+ UINT8 L1sTpowerOnScale;
+ /**
+ L1 Substate Port Tpower_on Value Override. (applicable if bit 2 is set in OverrideConfig)
+ L1sCommonModeRestoreTime and L1sTpowerOnScale can have a valid value of 0, but not the L1sTpowerOnValue.
+ If L1sTpowerOnValue is zero, all L1sCommonModeRestoreTime, L1sTpowerOnScale, and L1sTpowerOnValue are ignored,
+ and only L1SubstatesCapOffset is override.
+ **/
+ UINT8 L1sTpowerOnValue;
+
+ /**
+ SnoopLatency bit definition
+ Note: All Reserved bits must be set to 0
+
+ BIT[15] - When set to 1b, indicates that the values in bits 9:0 are valid
+ When clear values in bits 9:0 will be ignored
+ BITS[14:13] - Reserved
+ BITS[12:10] - Value in bits 9:0 will be multiplied with the scale in these bits
+ 000b - 1 ns
+ 001b - 32 ns
+ 010b - 1024 ns
+ 011b - 32,768 ns
+ 100b - 1,048,576 ns
+ 101b - 33,554,432 ns
+ 110b - Reserved
+ 111b - Reserved
+ BITS[9:0] - Snoop Latency Value. The value in these bits will be multiplied with
+ the scale in bits 12:10
+
+ This field takes effect only if bit 3 is set in OverrideConfig.
+ **/
+ UINT16 SnoopLatency;
+ /**
+ NonSnoopLatency bit definition
+ Note: All Reserved bits must be set to 0
+
+ BIT[15] - When set to 1b, indicates that the values in bits 9:0 are valid
+ When clear values in bits 9:0 will be ignored
+ BITS[14:13] - Reserved
+ BITS[12:10] - Value in bits 9:0 will be multiplied with the scale in these bits
+ 000b - 1 ns
+ 001b - 32 ns
+ 010b - 1024 ns
+ 011b - 32,768 ns
+ 100b - 1,048,576 ns
+ 101b - 33,554,432 ns
+ 110b - Reserved
+ 111b - Reserved
+ BITS[9:0] - Non Snoop Latency Value. The value in these bits will be multiplied with
+ the scale in bits 12:10
+
+ This field takes effect only if bit 3 is set in OverrideConfig.
+ **/
+ UINT16 NonSnoopLatency;
+
+ /**
+ Forces LTR override to be permanent
+ The default way LTR override works is:
+ rootport uses LTR override values provided by BIOS until connected device sends an LTR message, then it will use values from the message
+ This settings allows force override of LTR mechanism. If it's enabled, then:
+ rootport will use LTR override values provided by BIOS forever; LTR messages sent from connected device will be ignored
+ **/
+ UINT8 ForceLtrOverride;
+ UINT8 Reserved[3];
+} PCIE_DEVICE_OVERRIDE;
+
+#pragma pack (pop)
+#endif // _PCIE_CONFIG_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/PcieRp/PciePreMemConfig.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/PcieRp/PciePreMemConfig.h
new file mode 100644
index 0000000000..fe0be3ec12
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/PcieRp/PciePreMemConfig.h
@@ -0,0 +1,36 @@
+/** @file
+ PCIe Config Block PreMem
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _PCIE_PREMEM_CONFIG_H_
+#define _PCIE_PREMEM_CONFIG_H_
+
+
+extern EFI_GUID gPciePreMemConfigGuid;
+
+#pragma pack (push,1)
+
+/**
+ PCIe IMR Config
+**/
+typedef struct {
+ UINT8 ImrEnabled; ///< PCIe IMR. <b>0: Disable</b>; 1: Enable.
+ UINT8 ImrRpLocation; ///< 0: PCH_PCIe; 1: CPU_PCIe. If PCIeImrEnabled is TRUE then this will use to select the Root port location from PCH PCIe or CPU PCIe.Refer PCIE_IMR_ROOT_PORT_LOCATION above
+ UINT16 ImrSize; ///< PCIe IMR size in megabytes
+ UINT8 ImrRpSelection; ///< Index of root port that is selected for PCIe IMR (0 based)
+ UINT8 Rsvd0[3];
+} PCIE_IMR_CONFIG;
+
+/**
+ PCIe Pre-Memory Configuration
+ <b>Revision 1</b>: - Initial version.
+**/
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Offset 0 - 27 Config Block Header
+ PCIE_IMR_CONFIG PcieImr; ///< IMR Configuration
+} PCIE_PREMEM_CONFIG;
+
+#pragma pack (pop)
+#endif // _PCIE_PREMEM_CONFIG_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Pmc/AdrConfig.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Pmc/AdrConfig.h
new file mode 100644
index 0000000000..35ecb53ed2
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Pmc/AdrConfig.h
@@ -0,0 +1,76 @@
+/** @file
+ ADR policy
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _ADR_CONFIG_H_
+#define _ADR_CONFIG_H_
+
+#include <ConfigBlock.h>
+
+extern EFI_GUID gAdrConfigGuid;
+
+#pragma pack (push,1)
+
+
+/**
+ ADR Source Enable
+**/
+typedef union {
+ struct {
+ UINT32 Reserved1 : 1;
+ UINT32 AdrSrcPbo : 1;
+ UINT32 AdrSrcPmcUncErr : 1;
+ UINT32 AdrSrcPchThrm : 1;
+ UINT32 AdrSrcMePbo : 1;
+ UINT32 AdrSrcCpuThrm : 1;
+ UINT32 AdrSrcMegbl : 1;
+ UINT32 AdrSrcLtReset : 1;
+ UINT32 AdrSrcPmcWdt : 1;
+ UINT32 AdrSrcMeWdt : 1;
+ UINT32 AdrSrcPmcFw : 1;
+ UINT32 AdrSrcPchpwrFlr : 1;
+ UINT32 AdrSrcSyspwrFlr : 1;
+ UINT32 Reserved2 : 1;
+ UINT32 AdrSrcMiaUxsErr : 1;
+ UINT32 AdrSrcMiaUxErr : 1;
+ UINT32 AdrSrcCpuThrmWdt : 1;
+ UINT32 AdrSrcMeUncErr : 1;
+ UINT32 AdrSrcAdrGpio : 1;
+ UINT32 AdrSrcOcwdtNoicc : 1;
+ UINT32 AdrSrcOcwdtIcc : 1;
+ UINT32 AdrSrcCseHecUncErr : 1;
+ UINT32 AdrSrcPmcSramUncErr : 1;
+ UINT32 AdrSrcPmcIromParity : 1;
+ UINT32 AdrSrcPmcRfFusaErr : 1;
+ UINT32 Reserved3 : 4;
+ UINT32 AdrSrcPpbrParityErr : 1;
+ UINT32 Reserved4 : 2;
+ } Field;
+ UINT32 Value;
+} ADR_SOURCE_ENABLE;
+
+/**
+ ADR Configuration
+ <b>Revision 1</b>: - Initial version.
+**/
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Config Block Header
+ UINT32 AdrEn : 2; ///< Determine if Adr is enabled - 0: PLATFORM_POR, 1: FORCE_ENABLE, 2: FORCE_DISABLE
+ UINT32 AdrTimerEn : 2; ///< Determine if Adr timer options are enabled - 0: PLATFORM_POR, 1: FORCE_ENABLE, 2: FORCE_DISABLE
+ UINT32 AdrTimer1Val : 8; ///< Determines the Timeout value used for the ADR timer 1. A value of zero bypasses the timer
+ UINT32 AdrMultiplier1Val : 3; ///< Specifies the tick frequency upon which the timer 1 will increment. ADR_TIMER_SCALE should be used to encode values
+ UINT32 AdrTimer2Val : 8; ///< Determines the Timeout value used for the ADR timer 2. A value of zero bypasses the timer
+ UINT32 AdrMultiplier2Val : 3; ///< Specifies the tick frequency upon which the timer 2 will increment. ADR_TIMER_SCALE should be used to encode values
+ UINT32 AdrHostPartitionReset : 2; ///< Determine if Host Partition Reset is enabled - 0: PLATFORM_POR, 1: FORCE_ENABLE, 2: FORCE_DISABLE
+ UINT32 AdrSrcOverride : 1; ///< Check if default ADR sources will be overriten with custom 0: Not overwritten, 1: Overwritten
+ UINT32 AdrPlatAckEn : 2; ///< Determine if Platform Acknowledge is enabled - 0: PLATFORM_POR, 1: FORCE_ENABLE, 2: FORCE_DISABLE
+ UINT32 ReservedBits : 1;
+ ADR_SOURCE_ENABLE AdrSrcSel; ///< Determine which ADR sources are enabled - 0: Enabled, 1: Disabled
+} ADR_CONFIG;
+
+#pragma pack (pop)
+
+#endif // _ADR_CONFIG_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Pmc/PmConfig.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Pmc/PmConfig.h
new file mode 100644
index 0000000000..0a2ae50e6a
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Pmc/PmConfig.h
@@ -0,0 +1,86 @@
+/** @file
+ Power Management policy
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _PM_CONFIG_H_
+#define _PM_CONFIG_H_
+
+#include <ConfigBlock.h>
+
+extern EFI_GUID gPmConfigGuid;
+
+#pragma pack (push,1)
+
+/**
+ Description of Global Reset Trigger/Event Mask register
+**/
+typedef union {
+ struct {
+ UINT32 Reserved1 : 1;
+ UINT32 Pbo : 1;
+ UINT32 PmcUncErr : 1;
+ UINT32 PchThrm : 1;
+ UINT32 MePbo : 1;
+ UINT32 CpuThrm : 1;
+ UINT32 Megbl : 1;
+ UINT32 LtReset : 1;
+ UINT32 PmcWdt : 1;
+ UINT32 MeWdt : 1;
+ UINT32 PmcFw : 1;
+ UINT32 PchpwrFlr : 1;
+ UINT32 SyspwrFlr : 1;
+ UINT32 Reserved2 : 1;
+ UINT32 MiaUxsErr : 1;
+ UINT32 MiaUxErr : 1;
+ UINT32 CpuThrmWdt : 1;
+ UINT32 MeUncErr : 1;
+ UINT32 AdrGpio : 1;
+ UINT32 OcwdtNoicc : 1;
+ UINT32 OcwdtIcc : 1;
+ UINT32 CseHecUncErr : 1;
+ UINT32 PmcSramUncErr : 1;
+ UINT32 PmcIromParity : 1;
+ UINT32 PmcRfFusaErr : 1;
+ UINT32 Reserved3 : 4;
+ UINT32 PpbrParityErr : 1;
+ UINT32 Reserved4 : 2;
+ } Field;
+ UINT32 Value;
+} PMC_GLOBAL_RESET_MASK;
+
+typedef union {
+ struct {
+ UINT32 HostResetTimeout : 1;
+ UINT32 SxEntryTimeout : 1;
+ UINT32 HostRstProm : 1;
+ UINT32 HsmbMsg : 1;
+ UINT32 Pmc3Strike : 1;
+ UINT32 FwGblrstScratch5 : 1;
+ UINT32 PmcDmaTimeout : 1;
+ UINT32 EspiType7 : 1;
+ UINT32 EspiType8 : 1;
+ UINT32 FwGblRstScratch10 : 1;
+ UINT32 FwGblRstScratch11 : 1;
+ UINT32 LpmFwErr : 1;
+ UINT32 BscanMode : 1;
+ UINT32 SlpLvlRspErr : 1;
+ UINT32 FwGblrstScratch15 : 1;
+ UINT32 FwGblrstScratch16 : 1;
+ UINT32 FwGblrstScratch17 : 1;
+ UINT32 FwGblrstScratch18 : 1;
+ UINT32 FwGblrstScratch19 : 1;
+ UINT32 FwGblrstScratch20 : 1;
+ UINT32 FwGblrstScratch21 : 1;
+ UINT32 FwGblrstScratch22 : 1;
+ UINT32 FwGblrstScratch23 : 1;
+ UINT32 Rsvd : 9;
+ } Field;
+ UINT32 Value;
+} PMC_GLOBAL_RESET_MASK1;
+
+
+#pragma pack (pop)
+
+#endif // _PM_CONFIG_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Rtc/RtcConfig.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Rtc/RtcConfig.h
new file mode 100644
index 0000000000..62f8303558
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Rtc/RtcConfig.h
@@ -0,0 +1,37 @@
+/** @file
+ RTC policy
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _RTC_CONFIG_H_
+#define _RTC_CONFIG_H_
+
+extern EFI_GUID gRtcConfigGuid;
+
+#pragma pack (push,1)
+
+/**
+ The RTC_CONFIG block describes the expected configuration of RTC configuration.
+**/
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Config Block Header
+ /**
+ When set, prevents RTC TS (BUC.TS) from being changed.
+ This BILD bit has different function compared to LPC/eSPI, SPI.
+ 0: Disabled; <b>1: Enabled</b>
+ **/
+ UINT32 BiosInterfaceLock : 1;
+ /**
+ When set, bytes 38h-3Fh in the upper 128bytes bank of RTC RAM are locked
+ and cannot be accessed.
+ Writes will be droipped and reads will not return any guaranteed data.
+ 0: Disabled; <b>1: Enabled</b>
+ **/
+ UINT32 MemoryLock : 1;
+ UINT32 RsvdBits0 : 30;
+} RTC_CONFIG;
+
+#pragma pack (pop)
+
+#endif // _RTC_CONFIG_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/SerialIo/SerialIoConfig.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/SerialIo/SerialIoConfig.h
new file mode 100644
index 0000000000..b5c3b21606
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/SerialIo/SerialIoConfig.h
@@ -0,0 +1,33 @@
+/** @file
+ Serial IO policy
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _SERIAL_IO_CONFIG_H_
+#define _SERIAL_IO_CONFIG_H_
+
+extern EFI_GUID gSerialIoConfigGuid;
+
+#include <SerialIoDevices.h>
+
+#pragma pack (push,1)
+
+/**
+ The SERIAL_IO_CONFIG block provides the configurations to set the Serial IO controllers
+
+ <b>Revision 1:</b>
+ - Inital version.
+ <b>Revision 2:</b>
+ - Modified SPI Config to support pinmux functionality.
+**/
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Config Block Header
+ SERIAL_IO_SPI_CONFIG SpiDeviceConfig[PCH_MAX_SERIALIO_SPI_CONTROLLERS]; ///< SPI Configuration
+ SERIAL_IO_I2C_CONFIG I2cDeviceConfig[PCH_MAX_SERIALIO_I2C_CONTROLLERS]; ///< I2C Configuration
+ SERIAL_IO_UART_CONFIG UartDeviceConfig[PCH_MAX_SERIALIO_UART_CONTROLLERS]; ///< UART Configuration
+} SERIAL_IO_CONFIG;
+
+#pragma pack (pop)
+
+#endif // _SERIAL_IO_CONFIG_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/SiConfig.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/SiConfig.h
new file mode 100644
index 0000000000..5b59f08df2
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/SiConfig.h
@@ -0,0 +1,105 @@
+/** @file
+ Si Config Block
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _SI_CONFIG_H_
+#define _SI_CONFIG_H_
+
+#define SI_CONFIG_REVISION 1
+
+extern EFI_GUID gSiConfigGuid;
+
+
+#pragma pack (push,1)
+
+/**
+ The Silicon Policy allows the platform code to publish a set of configuration
+ information that the RC drivers will use to configure the silicon hardware.
+
+ <b>Revision 1</b>: - Initial version.
+**/
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Offset 0 - 27 Config Block Header
+ //
+ // Platform specific common policies that used by several silicon components.
+ //
+ UINT8 CsmFlag; ///< offset 28 CSM status flag.@deprecated.
+ /**
+ This is used to skip the SSID programming in silicon code.
+ When set to TRUE, silicon code will not do any SSID programming and platform code
+ needs to handle that by itself properly.
+ <b>0: FALSE</b>, 1: TRUE
+ **/
+ UINT8 SkipSsidProgramming; ///< offset 29
+ UINT8 RsvdBytes0[2]; ///< offset 30 - 31
+ /**
+ When SkipSsidProgramming is FALSE, silicon code will use this as default value
+ to program the SVID for all internal devices.
+ <b>0: use silicon default SVID 0x8086 </b>, Non-zero: use customized SVID.
+ **/
+ UINT16 CustomizedSvid; ///< offset 32 - 33
+ /**
+ When SkipSsidProgramming is FALSE, silicon code will use this as default value
+ to program the Sid for all internal devices.
+ <b>0: use silicon default SSID 0x7270 </b>, Non-zero: use customized SSID.
+ **/
+ UINT16 CustomizedSsid; ///< offset 34 - 35
+ UINT32 *SsidTablePtr; ///< offset 36 - 39
+ /**
+ Number of valid enties in SsidTablePtr.
+ This is valid when SkipSsidProgramming is FALSE;
+ <b>Default is 0.</b>
+ **/
+ UINT16 NumberOfSsidTableEntry; ///< offset 40 - 41
+ UINT8 RsvdBytes1[2]; ///< offset 42 - 43
+ /**
+ This is used to skip setting BIOS_DONE MSR during firmware update boot mode.
+ When set to TRUE and boot mode is BOOT_ON_FLASH_UPDATE,
+ skip setting BIOS_DONE MSR at EndofPei.
+ <b>0: FALSE</b>, 1: TRUE
+ **/
+ UINT8 SkipBiosDoneWhenFwUpdate; ///< Offset 44
+ UINT8 RsvdBytes2[3]; ///< Offset 45 - 47
+} SI_CONFIG;
+
+#pragma pack (pop)
+
+
+///
+/// Subsystem Vendor ID / Subsystem ID
+///
+typedef struct {
+ UINT16 SubSystemVendorId;
+ UINT16 SubSystemId;
+} SVID_SID_VALUE;
+
+//
+// Below is to match PCI_SEGMENT_LIB_ADDRESS () which can directly send to PciSegmentRead/Write functions.
+//
+typedef struct {
+ union {
+ struct {
+ UINT32 Register:12;
+ UINT32 Function:3;
+ UINT32 Device:5;
+ UINT32 Bus:8;
+ UINT32 Reserved1:4;
+ UINT32 Segment:16;
+ UINT32 Reserved2:16;
+ } Bits;
+ UINT64 SegBusDevFuncRegister;
+ } Address;
+ SVID_SID_VALUE SvidSidValue;
+ UINT32 Reserved;
+} SVID_SID_INIT_ENTRY;
+
+
+typedef struct {
+ UINT32 SkipBus;
+ UINT32 SkipDevice;
+ UINT32 SkipFunction;
+} SVID_SID_SKIP_TABLE;
+
+#endif // _SI_CONFIG_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/SiPreMemConfig.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/SiPreMemConfig.h
new file mode 100644
index 0000000000..584a0d4169
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/SiPreMemConfig.h
@@ -0,0 +1,63 @@
+/** @file
+ Si Config Block PreMem
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _SI_PREMEM_CONFIG_H_
+#define _SI_PREMEM_CONFIG_H_
+
+#define SI_PREMEM_CONFIG_REVISION 1
+
+extern EFI_GUID gSiPreMemConfigGuid;
+
+typedef enum {
+ ProbeTypeDisabled = 0x00,
+ ProbeTypeDciOob = 0x02,
+ ProbeType2WireDciOob = 0x06,
+ ProbeTypeManual = 0x07,
+ ProbeTypeMax
+} PLATFORM_DEBUG_CONSENT_PROBE_TYPE;
+
+#pragma pack (push,1)
+/**
+ The Silicon PreMem Policy allows the platform code to publish a set of configuration
+ information that the RC drivers will use to configure the silicon hardware.
+
+ <b>Revision 1</b>:
+ - Initial version.
+**/
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Offset 0 - 27 Config Block Header
+ /**
+ Platform Debug Consent
+ As a main switch to enable platform debug capability and relevant settings with specified probe type.
+ Manual: Do not use Platform Debug Consent to override other debug-relevant policies, but the user must set each debug option manually, aimed at advanced users.
+
+ PDC-dependent policies are listed:
+ DciPreMemConfig->DciEn
+ CpuTraceHubConfig->EnableMode
+ CpuTraceHubConfig->CpuTraceHubMemReg0Size
+ CpuTraceHubConfig->CpuTraceHubMemReg1Size
+ PchTraceHubPreMemConfig->EnableMode
+ PchTraceHubPreMemConfig->MemReg0Size
+ PchTraceHubPreMemConfig->MemReg1Size
+
+ Note: DCI OOB (aka BSSB) uses CCA probe.
+ Refer to definition of PLATFORM_DEBUG_CONSENT_PROBE_TYPE
+ <b>0:Disabled</b>; 2:DCI OOB (All + TraceHubs); 6:2-wire DCI OOB (Low power); 7:Manual
+ **/
+ UINT32 PlatformDebugConsent : 4; /// offset 28 - 31
+ UINT32 RsvdBits : 28;
+ /**
+ This is used to skip override boot mode during firmware update boot mode.
+ When set to TRUE and boot mode is BOOT_ON_FLASH_UPDATE,
+ skip setting boot mode to BOOT_WITH_FULL_CONFIGURATION in PEI memory init.
+ <b>0: FALSE</b>, 1: TRUE
+ **/
+ UINT8 SkipOverrideBootModeWhenFwUpdate; /// offset 32
+ UINT8 RsvdBytes[3]; /// offset 33 - 35
+} SI_PREMEM_CONFIG;
+
+#pragma pack (pop)
+#endif // _SI_PREMEM_CONFIG_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Smbus/SmbusConfig.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Smbus/SmbusConfig.h
new file mode 100644
index 0000000000..2fc724552b
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Smbus/SmbusConfig.h
@@ -0,0 +1,49 @@
+/** @file
+ Smbus policy
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _SMBUS_CONFIG_H_
+#define _SMBUS_CONFIG_H_
+
+extern EFI_GUID gSmbusPreMemConfigGuid;
+
+#pragma pack (push,1)
+
+#define PCH_MAX_SMBUS_RESERVED_ADDRESS 128
+
+///
+/// The SMBUS_CONFIG block lists the reserved addresses for non-ARP capable devices in the platform.
+///
+typedef struct {
+ /**
+ Revision 1: Init version
+ **/
+ CONFIG_BLOCK_HEADER Header; ///< Config Block Header
+ /**
+ This member describes whether or not the SMBus controller of PCH should be enabled.
+ 0: Disable; <b>1: Enable</b>.
+ **/
+ UINT32 Enable : 1;
+ UINT32 ArpEnable : 1; ///< Enable SMBus ARP support, <b>0: Disable</b>; 1: Enable.
+ UINT32 DynamicPowerGating : 1; ///< <b>(Test)</b> <b>Disable</b> or Enable Smbus dynamic power gating.
+ ///
+ /// <b>(Test)</b> SPD Write Disable, 0: leave SPD Write Disable bit; <b>1: set SPD Write Disable bit.</b>
+ /// For security recommendations, SPD write disable bit must be set.
+ ///
+ UINT32 SpdWriteDisable : 1;
+ UINT32 SmbAlertEnable : 1; ///< Enable SMBus Alert pin (SMBALERT#). 0: <b>Disabled<b>, 1: Enabled.
+ UINT32 RsvdBits0 : 27; ///< Reserved bits
+ UINT16 SmbusIoBase; ///< SMBUS Base Address (IO space). Default is <b>0xEFA0</b>.
+ UINT8 Rsvd0; ///< Reserved bytes
+ UINT8 NumRsvdSmbusAddresses; ///< The number of elements in the RsvdSmbusAddressTable.
+ /**
+ Array of addresses reserved for non-ARP-capable SMBus devices.
+ **/
+ UINT8 RsvdSmbusAddressTable[PCH_MAX_SMBUS_RESERVED_ADDRESS];
+} PCH_SMBUS_PREMEM_CONFIG;
+
+#pragma pack (pop)
+
+#endif // _SMBUS_CONFIG_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Spi/FlashProtectionConfig.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Spi/FlashProtectionConfig.h
new file mode 100644
index 0000000000..45dc538064
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Spi/FlashProtectionConfig.h
@@ -0,0 +1,54 @@
+/** @file
+ FlashProtection policy
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _FLASH_PROTECTION_CONFIG_H_
+#define _FLASH_PROTECTION_CONFIG_H_
+
+extern EFI_GUID gFlashProtectionConfigGuid;
+
+#pragma pack (push,1)
+
+//
+// Flash Protection Range Register
+//
+#define PCH_FLASH_PROTECTED_RANGES 5
+
+/**
+ Protected Flash Range
+**/
+typedef struct {
+ UINT32 WriteProtectionEnable : 1; ///< Write or erase is blocked by hardware. <b>0: Disable</b>; 1: Enable.
+ UINT32 ReadProtectionEnable : 1; ///< Read is blocked by hardware. <b>0: Disable</b>; 1: Enable.
+ UINT32 RsvdBits : 30; ///< Reserved
+ /**
+ The address of the upper limit of protection
+ This is a left shifted address by 12 bits with address bits 11:0 are assumed to be FFFh for limit comparison
+ **/
+ UINT16 ProtectedRangeLimit;
+ /**
+ The address of the upper limit of protection
+ This is a left shifted address by 12 bits with address bits 11:0 are assumed to be 0
+ **/
+ UINT16 ProtectedRangeBase;
+} PROTECTED_RANGE;
+
+/**
+ The PCH provides a method for blocking writes and reads to specific ranges
+ in the SPI flash when the Protected Ranges are enabled.
+ PROTECTED_RANGE is used to specify if flash protection are enabled,
+ the write protection enable bit and the read protection enable bit,
+ and to specify the upper limit and lower base for each register
+ Platform code is responsible to get the range base by PchGetSpiRegionAddresses routine,
+ and set the limit and base accordingly.
+**/
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Config Block Header
+ PROTECTED_RANGE ProtectRange[PCH_FLASH_PROTECTED_RANGES]; ///< Protected Flash Ranges
+} PCH_FLASH_PROTECTION_CONFIG;
+
+#pragma pack (pop)
+
+#endif // _FLASH_PROTECTION_CONFIG_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Tcss/TcssPeiConfig.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Tcss/TcssPeiConfig.h
new file mode 100644
index 0000000000..95bcaaa951
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Tcss/TcssPeiConfig.h
@@ -0,0 +1,71 @@
+/** @file
+ TCSS PEI policy
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _TCSS_PEI_CONFIG_H_
+#define _TCSS_PEI_CONFIG_H_
+
+#include <ConfigBlock.h>
+
+extern EFI_GUID gTcssPeiConfigGuid;
+
+#pragma pack (push,1)
+
+
+#define MAX_IOM_AUX_BIAS_COUNT 4
+
+///
+/// The IOM_AUX_ORI_PAD_CONFIG describes IOM TypeC port map GPIO pin.
+/// Those GPIO setting for DP Aux Orientation Bias Control when the TypeC port didn't have re-timer.
+/// IOM needs know Pull-Up and Pull-Down pin for Bias control
+///
+typedef struct {
+ UINT32 GpioPullN; ///< GPIO Pull Up Ping number that is for IOM indecate the pull up pin from TypeC port.
+ UINT32 GpioPullP; ///< GPIO Pull Down Ping number that is for IOM indecate the pull down pin from TypeC port.
+} IOM_AUX_ORI_PAD_CONFIG;
+
+///
+/// The IOM_EC_INTERFACE_CONFIG block describes interaction between BIOS and IOM-EC.
+///
+
+typedef struct {
+ UINT32 VccSt; ///< IOM VCCST request. (Not equal to actual VCCST value)
+ UINT32 UsbOverride; ///< IOM to override USB connection.
+ UINT32 D3ColdEnable; ///< Enable/disable D3 Cold support in TCSS
+ UINT32 D3HotEnable; ///< Enable/disable D3 Hot support in TCSS
+} IOM_INTERFACE_CONFIG;
+
+///
+/// The PMC_INTERFACE_CONFIG block describes interaction between BIOS and PMC
+///
+typedef struct {
+ UINT8 PmcPdEnable; ///< PMC PD Solution Enable
+ UINT8 Rsvd[3];
+} PMC_INTERFACE_CONFIG;
+
+///
+/// The TCSS_IOM_PEI_CONFIG block describes IOM Aux/HSL override settings for TCSS.
+///
+typedef struct {
+ UINT16 AuxOri; ///< Bits defining value for IOM Aux Orientation Register
+ UINT16 HslOri; ///< Bits defining value for IOM HSL Orientation Register
+} TCSS_IOM_ORI_OVERRIDE;
+
+///
+/// The TCSS_IOM_PEI_CONFIG block describes IOM settings for TCSS.
+///
+typedef struct {
+ IOM_AUX_ORI_PAD_CONFIG IomAuxPortPad[MAX_IOM_AUX_BIAS_COUNT]; ///< The IOM_AUX_ORI_BIAS_CTRL port config setting.
+ TCSS_IOM_ORI_OVERRIDE IomOverrides;
+ IOM_INTERFACE_CONFIG IomInterface; ///< Config settings are BIOS <-> IOM interface.
+ PMC_INTERFACE_CONFIG PmcInterface; ///< Config settings for BIOS <-> PMC interface
+ UINT8 TcStateLimit; ///< Tcss C-State deep stage
+ UINT8 Reserved[3]; ///< Reserved bytes for future use
+} TCSS_IOM_PEI_CONFIG;
+
+
+#pragma pack (pop)
+
+#endif /* _TCSS_PEI_CONFIG_H_ */
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Vmd/VmdPeiConfig.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Vmd/VmdPeiConfig.h
new file mode 100644
index 0000000000..37e6439abb
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Vmd/VmdPeiConfig.h
@@ -0,0 +1,60 @@
+/** @file
+ VMD PEI policy
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _VMD_PEI_CONFIG_H_
+#define _VMD_PEI_CONFIG_H_
+
+#include <ConfigBlock.h>
+
+#pragma pack (push,1)
+
+#define VMD_MAX_DEVICES 31
+
+typedef struct {
+ UINT8 RpBus;
+ UINT8 RpDevice;
+ UINT8 RpFunction;
+ UINT8 RpEnable;
+} RP_BDF_DATA;
+
+/**
+ This configuration block is to configure VMD related variables used in PostMem PEI.
+ If VMD Device is not supported, all policies can be ignored.
+ <b>Revision 1</b>:
+ - Initial version.
+ <b>Revision 2</b>:
+ - Deprecated VmdPortAEnable, VmdPortBEnable, VmdPortCEnable, VmdPortDEnable.
+ - Added VmdPortEnable[VMD_MAX_DEVICES] and structure to hold Vmd EFI Variable details.
+ (Added B/D/F fields along with Port Enable for up to max 31 devices).
+ <b>Revision 3</b>:
+ Added policy to get the Bar values from platform PCD.
+ <b>Revision 4</b>: Added VmdGlobalMapping to map all the storage devices under VMD
+**/
+
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Block Header
+ UINT8 VmdEnable; ///< Offset 28 This field used to enable VMD controller 1=Enable <b>0=Disable(default)</b>
+ UINT8 VmdPortAEnable; /// Deprecated < Offset 29 This field used to enable VMD portA Support 1=Enable and 0=Disable (default)
+ UINT8 VmdPortBEnable; /// Deprecated < Offset 30 This field used to enable VMD portB Support 1=Enable and 0=Disable (default)
+ UINT8 VmdPortCEnable; /// Deprecated < Offset 31 This field used to enable VMD portC Support 1=Enable and 0=Disable (default)
+ UINT8 VmdPortDEnable; /// Deprecated < Offset 32 This field used to enable VMD portD Support 1=Enable and 0=Disable (default)
+ UINT8 VmdCfgBarSize; ///< Offset 33 This is used to set the VMD Config Bar Size. <b>25(32MB)</b>
+ UINT8 VmdCfgBarAttr; ///< Offset 34 This is used to set VMD Config Bar Attributes 0: VMD_32BIT_NONPREFETCH, 1: VMD_64BIT_PREFETCH, <b>2: VMD_64BIT_NONPREFETCH(Default)</b>
+ UINT8 VmdMemBarSize1; ///< Offset 35 This is used to set the VMD Mem Bar1 size. <b>25 (32MB)</b>.
+ UINT8 VmdMemBar1Attr; ///< Offset 36 This is used to set VMD Mem Bar1 Attributes <b>0: VMD_32BIT_NONPREFETCH(Default) </b> 1: VMD_64BIT_NONPREFETCH, 2: VMD_64BIT_PREFETCH
+ UINT8 VmdMemBarSize2; ///< Offset 37 This is used to set the VMD Mem Bar2 size. <b>20(1MB)</b>.
+ UINT8 VmdMemBar2Attr; ///< Offset 38 This is used to set VMD Mem Bar2 Attributes 0: VMD_32BIT_NONPREFETCH <b>1: VMD_64BIT_NONPREFETCH(Default)</b>, 2: VMD_64BIT_PREFETCH
+ UINT8 VmdGlobalMapping; ///< Offset 39 This field used to enable Global Mapping 1=Enable <b>0=Disable(default)</b>
+ RP_BDF_DATA VmdPortEnable[VMD_MAX_DEVICES]; ///< Offset 40 to 163 This field used to to store b/d/f for each root port along with enable Support 1=Enable <b>0=Disable (default)</b>
+ VOID *VmdVariablePtr; /// This config block will be updated as per the EFI variable.
+ UINT32 VmdCfgBarBase; /// Temp Address VMD CFG BAR Default is <b>0xA0000000</b>
+ UINT32 VmdMemBar1Base; /// Temp Address VMD CFG BAR Default is <b>0xA2000000</b>
+ UINT32 VmdMemBar2Base; /// Temp Address VMD CFG BAR Default is <b>0xA4000000</b>
+} VMD_PEI_CONFIG;
+
+#pragma pack (pop)
+
+#endif /* _VMD_PEI_PREMEM_CONFIG_H_ */
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Wdt/WatchDogConfig.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Wdt/WatchDogConfig.h
new file mode 100644
index 0000000000..ad17488ecc
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Wdt/WatchDogConfig.h
@@ -0,0 +1,30 @@
+/** @file
+ WatchDog policy
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _WATCH_DOG_CONFIG_H_
+#define _WATCH_DOG_CONFIG_H_
+
+extern EFI_GUID gWatchDogPreMemConfigGuid;
+
+#pragma pack (push,1)
+
+/**
+ This policy clears status bits and disable watchdog, then lock the
+ WDT registers.
+ while WDT is designed to be disabled and locked by Policy,
+ bios should not enable WDT by WDT PPI. In such case, bios shows the
+ warning message but not disable and lock WDT register to make sure
+ WDT event trigger correctly.
+**/
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Config Block Header
+ UINT32 DisableAndLock : 1; ///< <b>(Test)</b> Set 1 to clear WDT status, then disable and lock WDT registers. <b>0: Disable</b>; 1: Enable.
+ UINT32 RsvdBits : 31;
+} PCH_WDT_PREMEM_CONFIG;
+
+#pragma pack (pop)
+
+#endif // _WATCH_DOG_CONFIG_H_
--
2.36.1.windows.1
-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#108723): https://edk2.groups.io/g/devel/message/108723
Mute This Topic: https://groups.io/mt/101373949/7686176
Group Owner: devel+owner@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [rebecca@openfw.io]
-=-=-=-=-=-=-=-=-=-=-=-
^ permalink raw reply related [flat|nested] 41+ messages in thread
* Re: [edk2-devel] [PATCH v2 06/10] AlderlakeSiliconPkg/Include: Add Library, Pins, Ppi Includes
2023-09-15 5:43 ` Chaganty, Rangasai V
@ 2023-09-15 13:28 ` Chuang, Rosen
0 siblings, 0 replies; 41+ messages in thread
From: Chuang, Rosen @ 2023-09-15 13:28 UTC (permalink / raw)
To: Chaganty, Rangasai V, Kasbekar, Saloni, devel@edk2.groups.io
Cc: Desimone, Nathaniel L
Reviewed-by: Rosen Chuang <rosen.chuang@intel.com>
-----Original Message-----
From: Chaganty, Rangasai V <rangasai.v.chaganty@intel.com>
Sent: Friday, September 15, 2023 1:43 PM
To: Kasbekar, Saloni <saloni.kasbekar@intel.com>; devel@edk2.groups.io
Cc: Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>; Chuang, Rosen <rosen.chuang@intel.com>
Subject: RE: [PATCH v2 06/10] AlderlakeSiliconPkg/Include: Add Library, Pins, Ppi Includes
Reviewed-by: Sai Chaganty <rangasai.v.chaganty@intel.com>
-----Original Message-----
From: Kasbekar, Saloni <saloni.kasbekar@intel.com>
Sent: Thursday, September 14, 2023 9:46 PM
To: devel@edk2.groups.io
Cc: Kasbekar, Saloni <saloni.kasbekar@intel.com>; Chaganty, Rangasai V <rangasai.v.chaganty@intel.com>; Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>; Chuang, Rosen <rosen.chuang@intel.com>
Subject: [PATCH v2 06/10] AlderlakeSiliconPkg/Include: Add Library, Pins, Ppi Includes
Adds the following Includes:
- Include/Library
- Include/Pins
- Include/Ppi
Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Rosen Chuang <rosen.chuang@intel.com>
Signed-off-by: Saloni Kasbekar <saloni.kasbekar@intel.com>
---
.../Include/Library/ConfigBlockLib.h | 64 +++
.../Include/Library/EspiLib.h | 34 ++
.../Include/Library/GpioConfig.h | 372 ++++++++++++++++++
.../Include/Library/GpioLib.h | 174 ++++++++
.../Include/Library/GpioNativeLib.h | 135 +++++++
.../Include/Library/GraphicsInfoLib.h | 46 +++
.../Include/Library/MmPciLib.h | 27 ++
.../Include/Library/PchPcieRpLib.h | 41 ++
.../Include/Library/PchPcrLib.h | 221 +++++++++++
.../Library/PeiDxeSmmReserveMmio64SizeLib.h | 21 +
.../Include/Library/PeiSiPolicyUpdateLib.h | 154 ++++++++
.../Include/Library/PmcLib.h | 40 ++
.../Include/Library/ResetSystemLib.h | 68 ++++
.../Include/Library/SecPlatformLib.h | 81 ++++
.../Include/Library/SiConfigBlockLib.h | 56 +++
.../Include/Library/SiPolicyLib.h | 39 ++
.../Include/Library/SpiLib.h | 21 +
.../Include/Pins/GpioPinsVer2Lp.h | 36 ++
.../Include/Ppi/FspmArchConfigPpi.h | 32 ++
.../Include/Ppi/PeiPreMemSiDefaultPolicy.h | 33 ++
.../Include/Ppi/PeiSiDefaultPolicy.h | 33 ++
.../AlderlakeSiliconPkg/Include/Ppi/Spi.h | 29 ++
.../AlderlakeSiliconPkg/Include/Ppi/Wdt.h | 22 ++
23 files changed, 1779 insertions(+)
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Library/ConfigBlockLib.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Library/EspiLib.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Library/GpioConfig.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Library/GpioLib.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Library/GpioNativeLib.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Library/GraphicsInfoLib.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Library/MmPciLib.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Library/PchPcieRpLib.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Library/PchPcrLib.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Library/PeiDxeSmmReserveMmio64SizeLib.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Library/PeiSiPolicyUpdateLib.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Library/PmcLib.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Library/ResetSystemLib.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Library/SecPlatformLib.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Library/SiConfigBlockLib.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Library/SiPolicyLib.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Library/SpiLib.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Pins/GpioPinsVer2Lp.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Ppi/FspmArchConfigPpi.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Ppi/PeiPreMemSiDefaultPolicy.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Ppi/PeiSiDefaultPolicy.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Ppi/Spi.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Ppi/Wdt.h
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/ConfigBlockLib.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/ConfigBlockLib.h
new file mode 100644
index 0000000000..d9966c76e9
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/ConfigBlockLib.h
@@ -0,0 +1,64 @@
+/** @file
+ Header file for Config Block Lib implementation
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _CONFIG_BLOCK_LIB_H_
+#define _CONFIG_BLOCK_LIB_H_
+
+/**
+ Create config block table
+
+ @param[in] TotalSize - Max size to be allocated for the Config Block Table
+ @param[out] ConfigBlockTableAddress - On return, points to a pointer to the beginning of Config Block Table Address
+
+ @retval EFI_INVALID_PARAMETER - Invalid Parameter
+ @retval EFI_OUT_OF_RESOURCES - Out of resources
+ @retval EFI_SUCCESS - Successfully created Config Block Table at ConfigBlockTableAddress
+**/
+EFI_STATUS
+EFIAPI
+CreateConfigBlockTable (
+ IN UINT16 TotalSize,
+ OUT VOID **ConfigBlockTableAddress
+ );
+
+/**
+ Add config block into config block table structure
+
+ @param[in] ConfigBlockTableAddress - A pointer to the beginning of Config Block Table Address
+ @param[out] ConfigBlockAddress - On return, points to a pointer to the beginning of Config Block Address
+
+ @retval EFI_OUT_OF_RESOURCES - Config Block Table is full and cannot add new Config Block or
+ Config Block Offset Table is full and cannot add new Config Block.
+ @retval EFI_SUCCESS - Successfully added Config Block
+**/
+EFI_STATUS
+EFIAPI
+AddConfigBlock (
+ IN VOID *ConfigBlockTableAddress,
+ OUT VOID **ConfigBlockAddress
+ );
+
+/**
+ Retrieve a specific Config Block data by GUID
+
+ @param[in] ConfigBlockTableAddress - A pointer to the beginning of Config Block Table Address
+ @param[in] ConfigBlockGuid - A pointer to the GUID uses to search specific Config Block
+ @param[out] ConfigBlockAddress - On return, points to a pointer to the beginning of Config Block Address
+
+ @retval EFI_NOT_FOUND - Could not find the Config Block
+ @retval EFI_SUCCESS - Config Block found and return
+**/
+EFI_STATUS
+EFIAPI
+GetConfigBlock (
+ IN VOID *ConfigBlockTableAddress,
+ IN EFI_GUID *ConfigBlockGuid,
+ OUT VOID **ConfigBlockAddress
+ );
+
+#endif // _CONFIG_BLOCK_LIB_H_
+
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/EspiLib.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/EspiLib.h
new file mode 100644
index 0000000000..3c37def986
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/EspiLib.h
@@ -0,0 +1,34 @@
+/** @file
+ Header file for PchEspiLib.
+ All function in this library is available for PEI, DXE, and SMM,
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _ESPI_LIB_H_
+#define _ESPI_LIB_H_
+
+/**
+ Checks if there's second device connected under CS#1
+
+ @retval TRUE There's second device
+ @retval FALSE There's no second device
+**/
+BOOLEAN
+IsEspiSecondSlaveSupported (
+ VOID
+ );
+
+/**
+ Is eSPI enabled in strap.
+
+ @retval TRUE Espi is enabled in strap
+ @retval FALSE Espi is disabled in strap
+**/
+BOOLEAN
+IsEspiEnabled (
+ VOID
+ );
+
+#endif // _ESPI_LIB_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/GpioConfig.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/GpioConfig.h
new file mode 100644
index 0000000000..43c0da46d7
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/GpioConfig.h
@@ -0,0 +1,372 @@
+/** @file
+ Header file for GpioConfig structure used by GPIO library.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _GPIO_CONFIG_H_
+#define _GPIO_CONFIG_H_
+
+#pragma pack(push, 1)
+
+///
+/// For any GpioPad usage in code use GPIO_PAD type
+///
+typedef UINT32 GPIO_PAD;
+
+///
+/// GpioPad with additional native function information.
+/// This type is used to represent signal muxing alternatives. Platform will provide such value to
+/// identify muxing selection for given signal on a specific SOC.
+/// Please refer to the board layout
+///
+typedef UINT32 GPIO_NATIVE_PAD;
+
+
+///
+/// For any GpioGroup usage in code use GPIO_GROUP type
+///
+typedef UINT32 GPIO_GROUP;
+
+/**
+ GPIO configuration structure used for pin programming.
+ Structure contains fields that can be used to configure pad.
+**/
+typedef struct {
+ /**
+ Pad Mode
+ Pad can be set as GPIO or one of its native functions.
+ When in native mode setting Direction (except Inversion), OutputState,
+ InterruptConfig, Host Software Pad Ownership and OutputStateLock are unnecessary.
+ Refer to definition of GPIO_PAD_MODE.
+ Refer to EDS for each native mode according to the pad.
+ **/
+ UINT32 PadMode : 5;
+ /**
+ Host Software Pad Ownership
+ Set pad to ACPI mode or GPIO Driver Mode.
+ Refer to definition of GPIO_HOSTSW_OWN.
+ **/
+ UINT32 HostSoftPadOwn : 2;
+ /**
+ GPIO Direction
+ Can choose between In, In with inversion, Out, both In and Out, both In with inversion and out or disabling both.
+ Refer to definition of GPIO_DIRECTION for supported settings.
+ **/
+ UINT32 Direction : 6;
+ /**
+ Output State
+ Set Pad output value.
+ Refer to definition of GPIO_OUTPUT_STATE for supported settings.
+ This setting takes place when output is enabled.
+ **/
+ UINT32 OutputState : 2;
+ /**
+ GPIO Interrupt Configuration
+ Set Pad to cause one of interrupts (IOxAPIC/SCI/SMI/NMI).
+ This setting is applicable only if GPIO is in GpioMode with input enabled.
+ Refer to definition of GPIO_INT_CONFIG for supported settings.
+ **/
+ UINT32 InterruptConfig : 9;
+ /**
+ GPIO Power Configuration.
+ This setting controls Pad Reset Configuration.
+ Refer to definition of GPIO_RESET_CONFIG for supported settings.
+ **/
+ UINT32 PowerConfig : 8;
+ /**
+ GPIO Electrical Configuration
+ This setting controls pads termination.
+ Refer to definition of GPIO_ELECTRICAL_CONFIG for supported settings.
+ **/
+ UINT32 ElectricalConfig : 9;
+ /**
+ GPIO Lock Configuration
+ This setting controls pads lock.
+ Refer to definition of GPIO_LOCK_CONFIG for supported settings.
+ **/
+ UINT32 LockConfig : 4;
+ /**
+ Additional GPIO configuration
+ Refer to definition of GPIO_OTHER_CONFIG for supported settings.
+ **/
+ UINT32 OtherSettings : 9;
+
+ /**
+ Virtual GPIO eSPI Chip Select configuration
+ This setting selects between CS0 and CS1.
+ Refer to definition of VGPIO_CS_CONFIG for supported settings.
+ **/
+ UINT32 VgpioCs : 2;
+
+ UINT32 RsvdBits : 8; ///< Reserved bits for future extension
+} GPIO_CONFIG;
+
+
+typedef enum {
+ GpioHardwareDefault = 0x0 ///< Leave setting unmodified
+} GPIO_HARDWARE_DEFAULT;
+
+/**
+ GPIO Pad Mode
+ Refer to GPIO documentation on native functions available for certain pad.
+ If GPIO is set to one of NativeX modes then following settings are not applicable
+ and can be skipped:
+ - Interrupt related settings
+ - Host Software Ownership
+ - Output/Input enabling/disabling
+ - Output lock
+**/
+typedef enum {
+ GpioPadModeHwDefault = 0x0,
+ GpioPadModeGpio = 0x1,
+ GpioPadModeNative1 = 0x3,
+ GpioPadModeNative2 = 0x5,
+ GpioPadModeNative3 = 0x7,
+ GpioPadModeNative4 = 0x9,
+ GpioPadModeNative5 = 0xB,
+ GpioPadModeNative6 = 0xD,
+ GpioPadModeNative7 = 0xF
+} GPIO_PAD_MODE;
+
+/**
+ Host Software Pad Ownership modes
+ This setting affects GPIO interrupt status registers. Depending on chosen ownership
+ some GPIO Interrupt status register get updated and other masked.
+ Please refer to EDS for HOSTSW_OWN register description.
+**/
+typedef enum {
+ GpioHostOwnDefault = 0x0, ///< Leave ownership value unmodified
+ /**
+ Set HOST ownership to ACPI.
+ Use this setting if pad is not going to be used by GPIO OS driver.
+ If GPIO is configured to generate SCI/SMI/NMI then this setting must be
+ used for interrupts to work
+ **/
+ GpioHostOwnAcpi = 0x1,
+ /**
+ Set HOST ownership to GPIO Driver mode.
+ Use this setting only if GPIO pad should be controlled by GPIO OS Driver.
+ GPIO OS Driver will be able to control the pad if appropriate entry in
+ ACPI exists (refer to ACPI specification for GpioIo and GpioInt descriptors)
+ **/
+ GpioHostOwnGpio = 0x3
+} GPIO_HOSTSW_OWN;
+
+///
+/// GPIO Direction
+///
+typedef enum {
+ GpioDirDefault = 0x0, ///< Leave pad direction setting unmodified
+ GpioDirInOut = (0x1 | (0x1 << 3)), ///< Set pad for both output and input
+ GpioDirInInvOut = (0x1 | (0x3 << 3)), ///< Set pad for both output and input with inversion
+ GpioDirIn = (0x3 | (0x1 << 3)), ///< Set pad for input only
+ GpioDirInInv = (0x3 | (0x3 << 3)), ///< Set pad for input with inversion
+ GpioDirOut = 0x5, ///< Set pad for output only
+ GpioDirNone = 0x7 ///< Disable both output and input
+} GPIO_DIRECTION;
+
+/**
+ GPIO Output State
+ This field is relevant only if output is enabled
+**/
+typedef enum {
+ GpioOutDefault = 0x0, ///< Leave output value unmodified
+ GpioOutLow = 0x1, ///< Set output to low
+ GpioOutHigh = 0x3 ///< Set output to high
+} GPIO_OUTPUT_STATE;
+
+/**
+ GPIO interrupt configuration
+ This setting is applicable only if pad is in GPIO mode and has input enabled.
+ GPIO_INT_CONFIG allows to choose which interrupt is generated (IOxAPIC/SCI/SMI/NMI)
+ and how it is triggered (edge or level). Refer to PADCFG_DW0 register description in
+ EDS for details on this settings.
+ Field from GpioIntNmi to GpioIntApic can be OR'ed with GpioIntLevel to GpioIntBothEdge
+ to describe an interrupt e.g. GpioIntApic | GpioIntLevel
+ If GPIO is set to cause an SCI then also GPI_GPE_EN is enabled for this pad.
+ If GPIO is set to cause an NMI then also GPI_NMI_EN is enabled for this pad.
+ Not all GPIO are capable of generating an SMI or NMI interrupt.
+ When routing GPIO to cause an IOxAPIC interrupt care must be taken, as this
+ interrupt cannot be shared and its IRQn number is not configurable.
+ Refer to EDS for GPIO pads IRQ numbers (PADCFG_DW1.IntSel)
+ If GPIO is under GPIO OS driver control and appropriate ACPI GpioInt descriptor
+ exist then use only trigger type setting (from GpioIntLevel to GpioIntBothEdge).
+ This type of GPIO Driver interrupt doesn't have any additional routing setting
+ required to be set by BIOS. Interrupt is handled by GPIO OS Driver.
+**/
+
+typedef enum {
+ GpioIntDefault = 0x0, ///< Leave value of interrupt routing unmodified
+ GpioIntDis = 0x1, ///< Disable IOxAPIC/SCI/SMI/NMI interrupt generation
+ GpioIntNmi = 0x3, ///< Enable NMI interrupt only
+ GpioIntSmi = 0x5, ///< Enable SMI interrupt only
+ GpioIntSci = 0x9, ///< Enable SCI interrupt only
+ GpioIntApic = 0x11, ///< Enable IOxAPIC interrupt only
+ GpioIntLevel = (0x1 << 5), ///< Set interrupt as level triggered
+ GpioIntEdge = (0x3 << 5), ///< Set interrupt as edge triggered (type of edge depends on input inversion)
+ GpioIntLvlEdgDis = (0x5 << 5), ///< Disable interrupt trigger
+ GpioIntBothEdge = (0x7 << 5) ///< Set interrupt as both edge triggered
+} GPIO_INT_CONFIG;
+
+#define B_GPIO_INT_CONFIG_INT_SOURCE_MASK 0x1F ///< Mask for GPIO_INT_CONFIG for interrupt source
+#define B_GPIO_INT_CONFIG_INT_TYPE_MASK 0xE0 ///< Mask for GPIO_INT_CONFIG for interrupt type
+
+/**
+ GPIO Power Configuration
+ GPIO_RESET_CONFIG allows to set GPIO Reset type (PADCFG_DW0.PadRstCfg) which will
+ be used to reset certain GPIO settings.
+ Refer to EDS for settings that are controllable by PadRstCfg.
+**/
+typedef enum {
+ GpioResetDefault = 0x00, ///< Leave value of pad reset unmodified
+ /**
+ Resume Reset (RSMRST)
+ GPP: PadRstCfg = 00b = "Powergood"
+ GPD: PadRstCfg = 11b = "Resume Reset"
+ Pad setting will reset on:
+ - DeepSx transition
+ - G3
+ Pad settings will not reset on:
+ - S3/S4/S5 transition
+ - Warm/Cold/Global reset
+ **/
+ GpioResumeReset = 0x01,
+ /**
+ Host Deep Reset
+ PadRstCfg = 01b = "Deep GPIO Reset"
+ Pad settings will reset on:
+ - Warm/Cold/Global reset
+ - DeepSx transition
+ - G3
+ Pad settings will not reset on:
+ - S3/S4/S5 transition
+ **/
+ GpioHostDeepReset = 0x03,
+ /**
+ Platform Reset (PLTRST)
+ PadRstCfg = 10b = "GPIO Reset"
+ Pad settings will reset on:
+ - S3/S4/S5 transition
+ - Warm/Cold/Global reset
+ - DeepSx transition
+ - G3
+ **/
+ GpioPlatformReset = 0x05,
+ /**
+ Deep Sleep Well Reset (DSW_PWROK)
+ GPP: not applicable
+ GPD: PadRstCfg = 00b = "Powergood"
+ Pad settings will reset on:
+ - G3
+ Pad settings will not reset on:
+ - S3/S4/S5 transition
+ - Warm/Cold/Global reset
+ - DeepSx transition
+ **/
+ GpioDswReset = 0x07,
+ /**
+ Global reset. Server chipsets only.
+ PadRstCfg = 11b = "Global reset"
+ Pad settings will reset on:
+ - Global reset
+ - G3
+ Pad settings will not reset on:
+ - S3/S4/S5 transition
+ - Warm/Cold reset
+ - DeepSx transition
+ **/
+ GpioGlobalReset = 0x09
+} GPIO_RESET_CONFIG;
+
+/**
+ GPIO Electrical Configuration
+ Configuration options for GPIO termination setting
+**/
+typedef enum {
+ GpioTermDefault = 0x0, ///< Leave termination setting unmodified
+ GpioTermNone = 0x1, ///< none
+ GpioTermWpd5K = 0x5, ///< 5kOhm weak pull-down
+ GpioTermWpd20K = 0x9, ///< 20kOhm weak pull-down
+ GpioTermWpu1K = 0x13, ///< 1kOhm weak pull-up
+ GpioTermWpu2K = 0x17, ///< 2kOhm weak pull-up
+ GpioTermWpu5K = 0x15, ///< 5kOhm weak pull-up
+ GpioTermWpu20K = 0x19, ///< 20kOhm weak pull-up
+ GpioTermWpu1K2K = 0x1B, ///< 1kOhm & 2kOhm weak pull-up
+ /**
+ Native function controls pads termination
+ This setting is applicable only to some native modes.
+ Please check EDS to determine which native functionality
+ can control pads termination
+ **/
+ GpioTermNative = 0x1F
+} GPIO_ELECTRICAL_CONFIG;
+
+#define B_GPIO_ELECTRICAL_CONFIG_TERMINATION_MASK 0x1F ///< Mask for GPIO_ELECTRICAL_CONFIG for termination value
+
+/**
+ GPIO LockConfiguration
+ Set GPIO configuration lock and output state lock.
+ GpioPadConfigUnlock/Lock and GpioOutputStateUnlock can be OR'ed.
+ By default GPIO pads will be locked unless GPIO lib is explicitly
+ informed that certain pad is to be left unlocked.
+ Lock settings reset is in Powergood domain. Care must be taken when using this setting
+ as fields it locks may be reset by a different signal and can be controlled
+ by what is in GPIO_RESET_CONFIG (PADCFG_DW0.PadRstCfg). GPIO library provides
+ functions which allow to unlock a GPIO pad. If possible each GPIO lib function will try to unlock
+ an already locked pad upon request for reconfiguration
+**/
+typedef enum {
+ /**
+ Perform default action
+ - if pad is an GPO, lock configuration but leave output unlocked
+ - if pad is an GPI, lock everything
+ - if pad is in native, lock everything
+**/
+ GpioLockDefault = 0x0,
+ GpioPadConfigUnlock = 0x3, ///< Leave Pad configuration unlocked
+ GpioPadConfigLock = 0x1, ///< Lock Pad configuration
+ GpioOutputStateUnlock = 0xC, ///< Leave Pad output control unlocked
+ GpioPadUnlock = 0xF, ///< Leave both Pad configuration and output control unlocked
+ GpioPadLock = 0x5, ///< Lock both Pad configuration and output control
+ /**
+ Below statuses are used for
+ return from GpioGetPadConfig function
+ **/
+ GpioLockTxLockCfgUnLock = 0x7, ///< Tx State locked, Pad Configuration unlocked
+ GpioLockTxUnLockCfgLock = 0xD ///< Tx State unlocked, Pad Configuration locked
+} GPIO_LOCK_CONFIG;
+
+#define B_GPIO_LOCK_CONFIG_PAD_CONF_LOCK_MASK 0x3 ///< Mask for GPIO_LOCK_CONFIG for Pad Configuration Lock
+#define B_GPIO_LOCK_CONFIG_OUTPUT_LOCK_MASK 0xC ///< Mask for GPIO_LOCK_CONFIG for Pad Output Lock
+
+/**
+ Other GPIO Configuration
+ GPIO_OTHER_CONFIG is used for less often settings and for future extensions
+ Supported settings:
+ - RX raw override to '1' - allows to override input value to '1'
+ This setting is applicable only if in input mode (both in GPIO and native usage).
+ The override takes place at the internal pad state directly from buffer and before the RXINV.
+**/
+typedef enum {
+ GpioRxRaw1Default = 0x0, ///< Use default input override value
+ GpioRxRaw1Dis = 0x1, ///< Don't override input
+ GpioRxRaw1En = 0x3 ///< Override input to '1'
+} GPIO_OTHER_CONFIG;
+
+/**
+ Virtual GPIO eSPI Chip Select configuration
+ This setting selects between CS0 and CS1.
+ Supported settings:
+ - Chipselect CS0 and CS1
+**/
+typedef enum {
+ VgpioCs0 = 0x0, ///< Chipselect CS0
+ VgpioCs1 = 0x1, ///< Chipselect CS1
+} VGPIO_CS_CONFIG;
+
+#define B_GPIO_OTHER_CONFIG_RXRAW_MASK 0x3 ///< Mask for GPIO_OTHER_CONFIG for RxRaw1 setting
+
+#pragma pack(pop)
+
+#endif //_GPIO_CONFIG_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/GpioLib.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/GpioLib.h
new file mode 100644
index 0000000000..d787e13be4
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/GpioLib.h
@@ -0,0 +1,174 @@
+/** @file
+ Header file for GpioLib.
+ All function in this library is available for PEI, DXE, and SMM
+
+ @note: When GPIO pads are owned by ME Firmware, BIOS/host should not
+ attempt to access these GPIO Pads registers, registers value
+ returned in this case will be 0xFF.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _GPIO_LIB_H_
+#define _GPIO_LIB_H_
+
+#include <Library/GpioConfig.h>
+
+typedef struct {
+ GPIO_PAD GpioPad;
+ GPIO_CONFIG GpioConfig;
+} GPIO_INIT_CONFIG;
+
+/**
+ This procedure will initialize multiple GPIO pins. Use GPIO_INIT_CONFIG structure.
+ Structure contains fields that can be used to configure each pad.
+ Pad not configured using GPIO_INIT_CONFIG will be left with hardware default values.
+ Separate fields could be set to hardware default if it does not matter, except
+ GpioPad and PadMode.
+ Function will work in most efficient way if pads which belong to the same group are
+ placed in adjacent records of the table.
+ Although function can enable pads for Native mode, such programming is done
+ by reference code when enabling related silicon feature.
+
+ @param[in] NumberofItem Number of GPIO pads to be updated
+ @param[in] GpioInitTableAddress GPIO initialization table
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid group or pad number
+**/
+EFI_STATUS
+GpioConfigurePads (
+ IN UINT32 NumberOfItems,
+ IN GPIO_INIT_CONFIG *GpioInitTableAddress
+ );
+
+///
+/// Possible values of Pad Ownership
+/// If Pad is not under Host ownership then GPIO registers
+/// are not accessible by host (e.g. BIOS) and reading them
+/// will return 0xFFs.
+///
+typedef enum {
+ GpioPadOwnHost = 0x0,
+ GpioPadOwnCsme = 0x1,
+ GpioPadOwnIsh = 0x2,
+} GPIO_PAD_OWN;
+
+/**
+ This procedure will get Gpio Pad Ownership
+
+ @param[in] GpioPad GPIO pad
+ @param[out] PadOwnVal Value of Pad Ownership
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid GpioPad
+**/
+EFI_STATUS
+GpioGetPadOwnership (
+ IN GPIO_PAD GpioPad,
+ OUT GPIO_PAD_OWN *PadOwnVal
+ );
+
+/**
+ This procedure will check state of Pad Config Lock for pads within one group
+
+ @param[in] Group GPIO group
+ @param[in] DwNum PadCfgLock register number for current group.
+ For group which has less then 32 pads per group DwNum must be 0.
+ @param[out] PadCfgLockRegVal Value of PadCfgLock register
+ Bit position - PadNumber
+ Bit value - 0: NotLocked, 1: Locked
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid group or DwNum parameter number
+**/
+EFI_STATUS
+GpioGetPadCfgLockForGroupDw (
+ IN GPIO_GROUP Group,
+ IN UINT32 DwNum,
+ OUT UINT32 *PadCfgLockRegVal
+ );
+
+/**
+ This procedure will check state of Pad Config Tx Lock for pads within one group
+
+ @param[in] Group GPIO group
+ @param[in] DwNum PadCfgLockTx register number for current group.
+ For group which has less then 32 pads per group DwNum must be 0.
+ @param[out] PadCfgLockTxRegVal Value of PadCfgLockTx register
+ Bit position - PadNumber
+ Bit value - 0: NotLockedTx, 1: LockedTx
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid group or DwNum parameter number
+**/
+EFI_STATUS
+GpioGetPadCfgLockTxForGroupDw (
+ IN GPIO_GROUP Group,
+ IN UINT32 DwNum,
+ OUT UINT32 *PadCfgLockTxRegVal
+ );
+
+/**
+ This procedure will clear PadCfgLock for selected pads within one group.
+ Unlocking a pad will cause an SMI (if enabled)
+
+ @param[in] Group GPIO group
+ @param[in] DwNum PadCfgLock register number for current group.
+ For group which has less then 32 pads per group DwNum must be 0.
+ @param[in] PadsToUnlock Bitmask for pads which are going to be unlocked,
+ Bit position - PadNumber
+ Bit value - 0: DoNotUnlock, 1: Unlock
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid group or pad number
+**/
+EFI_STATUS
+GpioUnlockPadCfgForGroupDw (
+ IN GPIO_GROUP Group,
+ IN UINT32 DwNum,
+ IN UINT32 PadsToUnlock
+ );
+
+/**
+ This procedure will set PadCfgLock for selected pads within one group
+
+ @param[in] Group GPIO group
+ @param[in] DwNum PadCfgLock register number for current group.
+ For group which has less then 32 pads per group DwNum must be 0.
+ @param[in] PadsToLock Bitmask for pads which are going to be locked,
+ Bit position - PadNumber
+ Bit value - 0: DoNotLock, 1: Lock
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid group or DwNum parameter number
+**/
+EFI_STATUS
+GpioLockPadCfgForGroupDw (
+ IN GPIO_GROUP Group,
+ IN UINT32 DwNum,
+ IN UINT32 PadsToLock
+ );
+
+/**
+ This procedure will clear PadCfgLockTx for selected pads within one group.
+ Unlocking a pad will cause an SMI (if enabled)
+
+ @param[in] Group GPIO group
+ @param[in] DwNum PadCfgLockTx register number for current group.
+ For group which has less then 32 pads per group DwNum must be 0.
+ @param[in] PadsToUnlockTx Bitmask for pads which are going to be unlocked,
+ Bit position - PadNumber
+ Bit value - 0: DoNotUnLockTx, 1: LockTx
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid group or pad number
+**/
+EFI_STATUS
+GpioUnlockPadCfgTxForGroupDw (
+ IN GPIO_GROUP Group,
+ IN UINT32 DwNum,
+ IN UINT32 PadsToUnlockTx
+ );
+
+#endif // _GPIO_LIB_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/GpioNativeLib.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/GpioNativeLib.h
new file mode 100644
index 0000000000..971f931442
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/GpioNativeLib.h
@@ -0,0 +1,135 @@
+/** @file
+ Header file for GpioLib for native and Si specific usage.
+ All function in this library is available for PEI, DXE, and SMM,
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _GPIO_NATIVE_LIB_H_
+#define _GPIO_NATIVE_LIB_H_
+
+#include <Library/GpioConfig.h>
+
+/**
+ This procedure will get number of pads for certain GPIO group
+
+ @param[in] Group GPIO group number
+
+ @retval Value Pad number for group
+ If illegal group number then return 0
+**/
+UINT32
+GpioGetPadPerGroup (
+ IN GPIO_GROUP Group
+ );
+
+/**
+ This procedure will get number of groups
+
+ @param[in] none
+
+ @retval Value Group number
+**/
+UINT32
+GpioGetNumberOfGroups (
+ VOID
+ );
+/**
+ This procedure will get lowest group
+
+ @param[in] none
+
+ @retval Value Lowest Group
+**/
+GPIO_GROUP
+GpioGetLowestGroup (
+ VOID
+ );
+
+/**
+ This procedure will get highest group
+
+ @param[in] none
+
+ @retval Value Highest Group
+**/
+GPIO_GROUP
+GpioGetHighestGroup (
+ VOID
+ );
+
+/**
+ This procedure will get group
+
+ @param[in] GpioPad Gpio Pad
+
+ @retval Value Group
+**/
+GPIO_GROUP
+GpioGetGroupFromGpioPad (
+ IN GPIO_PAD GpioPad
+ );
+
+/**
+ This procedure will get group index (0 based) from GpioPad
+
+ @param[in] GpioPad Gpio Pad
+
+ @retval Value Group Index
+**/
+UINT32
+GpioGetGroupIndexFromGpioPad (
+ IN GPIO_PAD GpioPad
+ );
+
+/**
+ This procedure will get group index (0 based) from group
+
+ @param[in] GpioGroup Gpio Group
+
+ @retval Value Group Index
+**/
+UINT32
+GpioGetGroupIndexFromGroup (
+ IN GPIO_GROUP GpioGroup
+ );
+
+/**
+ This procedure will get group from group index (0 based)
+
+ @param[in] GroupIndex Group Index
+
+ @retval GpioGroup Gpio Group
+**/
+GPIO_GROUP
+GpioGetGroupFromGroupIndex (
+ IN UINT32 GroupIndex
+ );
+
+/**
+ This procedure will get pad number (0 based) from Gpio Pad
+
+ @param[in] GpioPad Gpio Pad
+
+ @retval Value Pad Number
+**/
+UINT32
+GpioGetPadNumberFromGpioPad (
+ IN GPIO_PAD GpioPad
+ );
+
+/**
+ This procedure will return GpioPad from Group and PadNumber
+
+ @param[in] Group GPIO group
+ @param[in] PadNumber GPIO PadNumber
+
+ @retval GpioPad GpioPad
+**/
+GPIO_PAD
+GpioGetGpioPadFromGroupAndPadNumber (
+ IN GPIO_GROUP Group,
+ IN UINT32 PadNumber
+ );
+
+#endif // _GPIO_NATIVE_LIB_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/GraphicsInfoLib.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/GraphicsInfoLib.h
new file mode 100644
index 0000000000..bd9a7734b1
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/GraphicsInfoLib.h
@@ -0,0 +1,46 @@
+/** @file
+ Header file for Graphics Private Info Lib implementation.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _GRAPHICS_INFO_LIB_H_
+#define _GRAPHICS_INFO_LIB_H_
+
+#include <Library/BaseLib.h>
+#include <Library/PciSegmentLib.h>
+#include <IndustryStandard/Pci22.h>
+#include <Register/SaRegsHostBridge.h>
+
+/**
+ GetIgdBusNumber: Get IGD Bus Number
+
+ @retval PCI bus number for IGD
+**/
+UINT8
+GetIgdBusNumber (
+ VOID
+ );
+
+/**
+ GetIgdDevNumber: Get IGD Dev Number
+
+ @retval PCI dev number for IGD
+**/
+UINT8
+GetIgdDevNumber (
+ VOID
+ );
+
+/**
+ GetIgdFunNumber: Get IGD Fun Number
+
+ @retval PCI fun number for IGD
+**/
+UINT8
+GetIgdFuncNumber (
+ VOID
+ );
+
+#endif
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/MmPciLib.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/MmPciLib.h
new file mode 100644
index 0000000000..04249eefdf
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/MmPciLib.h
@@ -0,0 +1,27 @@
+/** @file
+ Get Pci Express address library implementation.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _MM_PCI_LIB_H_
+#define _MM_PCI_LIB_H_
+
+/**
+ This procedure will get PCIE address
+
+ @param[in] Bus Pci Bus Number
+ @param[in] Device Pci Device Number
+ @param[in] Function Pci Function Number
+
+ @retval PCIE address
+**/
+UINTN
+EFIAPI
+MmPciBase (
+ IN UINT32 Bus,
+ IN UINT32 Device,
+ IN UINT32 Function
+);
+
+#endif // _PEI_DXE_SMM_MM_PCI_LIB_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/PchPcieRpLib.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/PchPcieRpLib.h
new file mode 100644
index 0000000000..d9ca215d85
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/PchPcieRpLib.h
@@ -0,0 +1,41 @@
+/** @file
+ Header file for PchPcieRpLib.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _PCH_PCIERP_LIB_H_
+#define _PCH_PCIERP_LIB_H_
+
+#include <Uefi.h>
+#include <Library/PchPcrLib.h>
+
+/**
+ Get Pch Pcie Root Port Device and Function Number by Root Port physical Number
+
+ @param[in] RpNumber Root port physical number. (0-based)
+ @param[out] RpDev Return corresponding root port device number.
+ @param[out] RpFun Return corresponding root port function number.
+
+ @retval EFI_SUCCESS
+**/
+EFI_STATUS
+EFIAPI
+GetPchPcieRpDevFun (
+ IN UINTN RpNumber,
+ OUT UINTN *RpDev,
+ OUT UINTN *RpFun
+ );
+
+/**
+ Gets pci segment base address of PCIe root port.
+
+ @param RpIndex Root Port Index (0 based)
+ @return PCIe port base address.
+**/
+UINT64
+PchPcieBase (
+ IN UINT32 RpIndex
+ );
+
+#endif // _PCH_PCIERP_LIB_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/PchPcrLib.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/PchPcrLib.h
new file mode 100644
index 0000000000..19a1a98639
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/PchPcrLib.h
@@ -0,0 +1,221 @@
+/** @file
+ Header file for PchPcrLib.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _PCH_PCR_LIB_H_
+#define _PCH_PCR_LIB_H_
+
+#include <PchReservedResources.h>
+
+/**
+ Definition for PCR address
+ The PCR address is used to the PCR MMIO programming
+
+ SBREG_BAR_20BITADDRESS is configured by SoC
+
+ SBREG_BAR_20BITADDRESS=1, the format has included 16b addressing.
+ +---------------------------------------------------------------------------------------------+
+ | Addr[63:28] | Addr[27:24] | Addr[23:16] | Addr[15:2] | Addr[1:0] |
+ +----------------+-----------------------+-----------------+----------------------------------+
+ | REG_BAR[63:28] | TargetRegister[19:16] | TargetPort[7:0] | TargetRegister[15:2] |
+ +---------------------------------------------------------------------------------------------+
+
+ SBREG_BAR_20BITADDRESS=0
+ +---------------------------------------------------------------------------------------------+
+ | Addr[63:24] | Addr[27:24] | Addr[23:16] | Addr[15:2] | Addr[1:0] |
+ +----------------+-----------------------+-----------------+----------------------------------+
+ | REG_BAR[63:24] | REG_BAR[27:24] | TargetPort[7:0] | TargetRegister[15:2] |
+ +---------------------------------------------------------------------------------------------+
+**/
+#define PCH_PCR_ADDRESS(Pid, Offset) (PCH_PCR_BASE_ADDRESS | (UINT32) (((Offset) & 0x0F0000) << 8) | ((UINT8)(Pid) << 16) | (UINT16) ((Offset) & 0xFFFF))
+
+/**
+ PCH PCR boot script accessing macro
+ Those macros are only available for DXE phase.
+**/
+#define PCH_PCR_BOOT_SCRIPT_WRITE(Width, Pid, Offset, Count, Buffer) \
+ S3BootScriptSaveMemWrite (Width, PCH_PCR_ADDRESS (Pid, Offset), Count, Buffer); \
+
+#define PCH_PCR_BOOT_SCRIPT_READ_WRITE(Width, Pid, Offset, DataOr, DataAnd) \
+ S3BootScriptSaveMemReadWrite (Width, PCH_PCR_ADDRESS (Pid, Offset), DataOr, DataAnd); \
+
+#define PCH_PCR_BOOT_SCRIPT_READ(Width, Pid, Offset, BitMask, BitValue) \
+ S3BootScriptSaveMemPoll (Width, PCH_PCR_ADDRESS (Pid, Offset), BitMask, BitValue, 1, 1);
+
+typedef UINT8 PCH_SBI_PID;
+
+/**
+ Read PCR register.
+ It returns PCR register and size in 4bytes.
+ The Offset should not exceed 0xFFFF and must be aligned with size.
+
+ @param[in] Pid Port ID
+ @param[in] Offset Register offset of this Port ID
+
+ @retval UINT32 PCR register value.
+**/
+UINT32
+PchPcrRead32 (
+ IN PCH_SBI_PID Pid,
+ IN UINT32 Offset
+ );
+
+/**
+ Read PCR register.
+ It returns PCR register and size in 2bytes.
+ The Offset should not exceed 0xFFFF and must be aligned with size.
+
+ @param[in] Pid Port ID
+ @param[in] Offset Register offset of this Port ID
+
+ @retval UINT16 PCR register value.
+**/
+UINT16
+PchPcrRead16 (
+ IN PCH_SBI_PID Pid,
+ IN UINT32 Offset
+ );
+
+/**
+ Read PCR register.
+ It returns PCR register and size in 1bytes.
+ The Offset should not exceed 0xFFFF and must be aligned with size.
+
+ @param[in] Pid Port ID
+ @param[in] Offset Register offset of this Port ID
+
+ @retval UINT8 PCR register value
+**/
+UINT8
+PchPcrRead8 (
+ IN PCH_SBI_PID Pid,
+ IN UINT32 Offset
+ );
+
+/**
+ Write PCR register.
+ It programs PCR register and size in 4bytes.
+ The Offset should not exceed 0xFFFF and must be aligned with size.
+
+ @param[in] Pid Port ID
+ @param[in] Offset Register offset of Port ID.
+ @param[in] Data Input Data. Must be the same size as Size parameter.
+
+ @retval UINT32 Value written to register
+**/
+UINT32
+PchPcrWrite32 (
+ IN PCH_SBI_PID Pid,
+ IN UINT32 Offset,
+ IN UINT32 InData
+ );
+
+/**
+ Write PCR register.
+ It programs PCR register and size in 2bytes.
+ The Offset should not exceed 0xFFFF and must be aligned with size.
+
+ @param[in] Pid Port ID
+ @param[in] Offset Register offset of Port ID.
+ @param[in] Data Input Data. Must be the same size as Size parameter.
+
+ @retval UINT16 Value written to register
+**/
+UINT16
+PchPcrWrite16 (
+ IN PCH_SBI_PID Pid,
+ IN UINT32 Offset,
+ IN UINT16 InData
+ );
+
+/**
+ Write PCR register.
+ It programs PCR register and size in 1bytes.
+ The Offset should not exceed 0xFFFF and must be aligned with size.
+
+ @param[in] Pid Port ID
+ @param[in] Offset Register offset of Port ID.
+ @param[in] Data Input Data. Must be the same size as Size parameter.
+
+ @retval UINT8 Value written to register
+**/
+UINT8
+PchPcrWrite8 (
+ IN PCH_SBI_PID Pid,
+ IN UINT32 Offset,
+ IN UINT8 InData
+ );
+
+/**
+ Write PCR register.
+ It programs PCR register and size in 4bytes.
+ The Offset should not exceed 0xFFFF and must be aligned with size.
+
+ @param[in] Pid Port ID
+ @param[in] Offset Register offset of Port ID.
+ @param[in] AndData AND Data. Must be the same size as Size parameter.
+ @param[in] OrData OR Data. Must be the same size as Size parameter.
+
+ @retval UINT32 Value written to register
+
+**/
+UINT32
+PchPcrAndThenOr32 (
+ IN PCH_SBI_PID Pid,
+ IN UINT32 Offset,
+ IN UINT32 AndData,
+ IN UINT32 OrData
+ );
+
+/**
+ Write PCR register.
+ It programs PCR register and size in 2bytes.
+ The Offset should not exceed 0xFFFF and must be aligned with size.
+
+ @param[in] Pid Port ID
+ @param[in] Offset Register offset of Port ID.
+ @param[in] AndData AND Data. Must be the same size as Size parameter.
+ @param[in] OrData OR Data. Must be the same size as Size parameter.
+
+ @retval UINT16 Value written to register
+
+**/
+UINT16
+PchPcrAndThenOr16 (
+ IN PCH_SBI_PID Pid,
+ IN UINT32 Offset,
+ IN UINT16 AndData,
+ IN UINT16 OrData
+ );
+
+/**
+ Write PCR register.
+ It programs PCR register and size in 1bytes.
+ The Offset should not exceed 0xFFFF and must be aligned with size.
+
+ @param[in] Pid Port ID
+ @param[in] Offset Register offset of Port ID.
+ @param[in] AndData AND Data. Must be the same size as Size parameter.
+ @param[in] OrData OR Data. Must be the same size as Size parameter.
+
+ @retval UINT8 Value written to register
+
+**/
+UINT8
+PchPcrAndThenOr8 (
+ IN PCH_SBI_PID Pid,
+ IN UINT32 Offset,
+ IN UINT8 AndData,
+ IN UINT8 OrData
+ );
+
+
+typedef enum {
+ PchIpDmi = 1,
+ PchIpIclk,
+} PCH_IP_PID_ENUM;
+
+
+#endif // _PCH_PCR_LIB_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/PeiDxeSmmReserveMmio64SizeLib.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/PeiDxeSmmReserveMmio64SizeLib.h
new file mode 100644
index 0000000000..d27f858892
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/PeiDxeSmmReserveMmio64SizeLib.h
@@ -0,0 +1,21 @@
+/** @file
+ PEI/DXE/SMM library for reserved 64-bit MMIO space.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PEI_DXE_SMM_RESERVE_MMIO_64_SIZE_LIB_H_
+#define _PEI_DXE_SMM_RESERVE_MMIO_64_SIZE_LIB_H_
+
+/**
+ The function return the 64 bit MMIO size to reserve.
+
+ @retval The 64-bit MMIO size
+**/
+UINT64
+ReserveMmio64Size (
+ VOID
+ );
+
+#endif // _PEI_DXE_SMM_RESERVE_MMIO_64_SIZE_LIB_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/PeiSiPolicyUpdateLib.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/PeiSiPolicyUpdateLib.h
new file mode 100644
index 0000000000..79e7752e4a
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/PeiSiPolicyUpdateLib.h
@@ -0,0 +1,154 @@
+/** @file
+ Header file for PEI SiPolicyUpdate Library.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PEI_SI_POLICY_UPDATE_LIB_H_
+#define _PEI_SI_POLICY_UPDATE_LIB_H_
+
+#include <Ppi/SiPolicy.h>
+
+/**
+ This function performs CPU PEI Policy initialization in Post-memory.
+
+ @retval EFI_SUCCESS The PPI is installed and initialized.
+ @retval EFI ERRORS The PPI is not successfully installed.
+ @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize the driver
+**/
+EFI_STATUS
+EFIAPI
+UpdatePeiCpuPolicy (
+ VOID
+ );
+
+/**
+ This function performs CPU PEI Policy initialization in PreMem.
+
+ @retval EFI_SUCCESS The PPI is installed and initialized.
+ @retval EFI ERRORS The PPI is not successfully installed.
+ @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize the driver
+**/
+EFI_STATUS
+EFIAPI
+UpdatePeiCpuPolicyPreMem (
+ VOID
+ );
+
+
+/**
+ This function performs SA PEI Policy initialization.
+
+ @retval EFI_SUCCESS The PPI is installed and initialized.
+**/
+EFI_STATUS
+EFIAPI
+UpdatePeiSaPolicy (
+ VOID
+ );
+
+/**
+ This function performs SA PEI Policy initialization for PreMem.
+
+ @retval EFI_SUCCESS Update complete.
+**/
+EFI_STATUS
+EFIAPI
+UpdatePeiSaPolicyPreMem (
+ VOID
+ );
+
+/**
+ This function performs PCH PEI Policy initialization.
+
+ @retval EFI_SUCCESS The PPI is installed and initialized.
+ @retval EFI ERRORS The PPI is not successfully installed.
+ @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize the driver
+**/
+EFI_STATUS
+EFIAPI
+UpdatePeiPchPolicy (
+ VOID
+ );
+
+/**
+ This function performs PCH PEI Policy initialization.
+
+ @retval EFI_SUCCESS The PPI is installed and initialized.
+ @retval EFI ERRORS The PPI is not successfully installed.
+ @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize the driver
+**/
+EFI_STATUS
+EFIAPI
+UpdatePeiPchPolicyPreMem (
+ VOID
+ );
+
+/**
+ Update the ME Policy Library
+
+ @retval EFI_SUCCESS Update complete.
+ @retval Others Update unsuccessful.
+**/
+EFI_STATUS
+EFIAPI
+UpdatePeiMePolicy (
+ VOID
+ );
+
+/**
+ Update the ME Policy Library
+
+ @retval EFI_SUCCESS Update complete.
+**/
+EFI_STATUS
+EFIAPI
+UpdatePeiMePolicyPreMem (
+ VOID
+ );
+
+
+
+/**
+ Update the TBT Policy Library
+
+ @retval EFI_SUCCESS Update complete.
+**/
+EFI_STATUS
+EFIAPI
+UpdatePeiTbtPolicy (
+ VOID
+ );
+
+/**
+ Update the ME Server Policy Ppi (pre mem)
+
+ @param[in, out] SiPreMemPolicyPpi PEI Pre Mem Si Policy
+
+ @retval EFI_SUCCESS Initialization complete.
+ @retval EFI_UNSUPPORTED The chipset is unsupported by this driver.
+ @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize the driver.
+ @retval EFI_DEVICE_ERROR Device error, driver exits abnormally.
+ @retval EFI_INVALID_PARAMETER Wrong pointer passed to the function
+**/
+EFI_STATUS
+UpdatePeiMeServerPreMemPolicy (
+ IN OUT SI_PREMEM_POLICY_PPI *SiPreMemPolicy
+ );
+
+/**
+ Update the ME Server Policy Ppi (post mem)
+
+ @param[in, out] SiPolicyPpi PEI Si Policy
+
+ @retval EFI_SUCCESS Initialization complete.
+ @retval EFI_UNSUPPORTED The chipset is unsupported by this driver.
+ @retval EFI_DEVICE_ERROR Device error, driver exits abnormally.
+ @retval EFI_INVALID_PARAMETER Wrong pointer passed to the function
+**/
+ EFI_STATUS
+UpdatePeiMeServerPolicy (
+ IN OUT SI_POLICY_PPI *SiPolicyPpi
+ );
+#endif
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/PmcLib.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/PmcLib.h
new file mode 100644
index 0000000000..7d49a14164
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/PmcLib.h
@@ -0,0 +1,40 @@
+/** @file
+ Header file for PmcLib.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _PMC_LIB_H_
+#define _PMC_LIB_H_
+
+#include <PmConfig.h>
+
+
+typedef struct {
+ UINT32 Buf0;
+ UINT32 Buf1;
+ UINT32 Buf2;
+ UINT32 Buf3;
+} PMC_IPC_COMMAND_BUFFER;
+
+/**
+ Get PCH ACPI base address.
+
+ @retval Address Address of PWRM base address.
+**/
+UINT16
+PmcGetAcpiBase (
+ VOID
+ );
+
+/**
+ Get PCH PWRM base address.
+
+ @retval Address Address of PWRM base address.
+**/
+UINT32
+PmcGetPwrmBase (
+ VOID
+ );
+
+#endif // _PMC_LIB_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/ResetSystemLib.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/ResetSystemLib.h
new file mode 100644
index 0000000000..6146e8610d
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/ResetSystemLib.h
@@ -0,0 +1,68 @@
+/** @file
+ System reset Library Services. This library class defines a set of
+ methods that reset the whole system.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef __RESET_SYSTEM_LIB_H__
+#define __RESET_SYSTEM_LIB_H__
+
+/**
+ This function causes a system-wide reset (cold reset), in which
+ all circuitry within the system returns to its initial state. This type of reset
+ is asynchronous to system operation and operates without regard to
+ cycle boundaries.
+
+ If this function returns, it means that the system does not support cold reset.
+**/
+VOID
+EFIAPI
+ResetCold (
+ VOID
+ );
+
+/**
+ This function causes a system-wide initialization (warm reset), in which all processors
+ are set to their initial state. Pending cycles are not corrupted.
+
+ If this function returns, it means that the system does not support warm reset.
+**/
+VOID
+EFIAPI
+ResetWarm (
+ VOID
+ );
+
+/**
+ This function causes the system to enter a power state equivalent
+ to the ACPI G2/S5 or G3 states.
+
+ If this function returns, it means that the system does not support shutdown reset.
+**/
+VOID
+EFIAPI
+ResetShutdown (
+ VOID
+ );
+
+/**
+ This function causes a systemwide reset. The exact type of the reset is
+ defined by the EFI_GUID that follows the Null-terminated Unicode string passed
+ into ResetData. If the platform does not recognize the EFI_GUID in ResetData
+ the platform must pick a supported reset type to perform.The platform may
+ optionally log the parameters from any non-normal reset that occurs.
+
+ @param[in] DataSize The size, in bytes, of ResetData.
+ @param[in] ResetData The data buffer starts with a Null-terminated string,
+ followed by the EFI_GUID.
+**/
+VOID
+EFIAPI
+ResetPlatformSpecific (
+ IN UINTN DataSize,
+ IN VOID *ResetData
+ );
+
+#endif
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/SecPlatformLib.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/SecPlatformLib.h
new file mode 100644
index 0000000000..7fa23b1a51
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/SecPlatformLib.h
@@ -0,0 +1,81 @@
+/** @file
+ Prototype of SEC Platform hook library.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _SEC_PLATFORM_LIB_H_
+#define _SEC_PLATFORM_LIB_H_
+
+#include <Ppi/SecPlatformInformation.h>
+#include <Ppi/SecPerformance.h>
+
+/**
+ A developer supplied function to perform platform specific operations.
+
+ It's a developer supplied function to perform any operations appropriate to a
+ given platform. It's invoked just before passing control to PEI core by SEC
+ core. Platform developer may modify the SecCoreData passed to PEI Core.
+ It returns a platform specific PPI list that platform wishes to pass to PEI core.
+ The Generic SEC core module will merge this list to join the final list passed to
+ PEI core.
+
+ @param SecCoreData The same parameter as passing to PEI core. It
+ could be overridden by this function.
+
+ @return The platform specific PPI list to be passed to PEI core or
+ NULL if there is no need of such platform specific PPI list.
+
+**/
+EFI_PEI_PPI_DESCRIPTOR *
+EFIAPI
+SecPlatformMain (
+ IN OUT EFI_SEC_PEI_HAND_OFF *SecCoreData
+ );
+
+
+/**
+ This interface conveys state information out of the Security (SEC) phase into PEI.
+
+ @param PeiServices Pointer to the PEI Services Table.
+ @param StructureSize Pointer to the variable describing size of the input buffer.
+ @param PlatformInformationRecord Pointer to the EFI_SEC_PLATFORM_INFORMATION_RECORD.
+
+ @retval EFI_SUCCESS The data was successfully returned.
+ @retval EFI_BUFFER_TOO_SMALL The buffer was too small.
+
+**/
+EFI_STATUS
+EFIAPI
+SecPlatformInformation (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN OUT UINT64 *StructureSize,
+ OUT EFI_SEC_PLATFORM_INFORMATION_RECORD *PlatformInformationRecord
+ );
+
+/**
+ This interface conveys performance information out of the Security (SEC) phase into PEI.
+
+ This service is published by the SEC phase. The SEC phase handoff has an optional
+ EFI_PEI_PPI_DESCRIPTOR list as its final argument when control is passed from SEC into the
+ PEI Foundation. As such, if the platform supports collecting performance data in SEC,
+ this information is encapsulated into the data structure abstracted by this service.
+ This information is collected for the boot-strap processor (BSP) on IA-32.
+
+ @param[in] PeiServices The pointer to the PEI Services Table.
+ @param[in] This The pointer to this instance of the PEI_SEC_PERFORMANCE_PPI.
+ @param[out] Performance The pointer to performance data collected in SEC phase.
+
+ @retval EFI_SUCCESS The data was successfully returned.
+**/
+EFI_STATUS
+EFIAPI
+SecGetPerformance (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN PEI_SEC_PERFORMANCE_PPI *This,
+ OUT FIRMWARE_SEC_PERFORMANCE *Performance
+ );
+
+#endif
+
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/SiConfigBlockLib.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/SiConfigBlockLib.h
new file mode 100644
index 0000000000..7bb111a932
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/SiConfigBlockLib.h
@@ -0,0 +1,56 @@
+/** @file
+ Prototype of the SiConfigBlockLib library.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _SI_CONFIG_BLOCK_LIB_H_
+#define _SI_CONFIG_BLOCK_LIB_H_
+
+
+typedef
+VOID
+(*LOAD_DEFAULT_FUNCTION) (
+ IN VOID *ConfigBlockPointer
+ );
+
+typedef struct {
+ EFI_GUID *Guid;
+ UINT16 Size;
+ UINT8 Revision;
+ LOAD_DEFAULT_FUNCTION LoadDefault;
+} COMPONENT_BLOCK_ENTRY;
+
+/**
+ GetComponentConfigBlockTotalSize get config block table total size.
+
+ @param[in] ComponentBlocks Component blocks array
+ @param[in] TotalBlockCount Number of blocks
+
+ @retval Size of config block table
+**/
+UINT16
+EFIAPI
+GetComponentConfigBlockTotalSize (
+ IN COMPONENT_BLOCK_ENTRY *ComponentBlocks,
+ IN UINT16 TotalBlockCount
+ );
+
+/**
+ AddComponentConfigBlocks add all config blocks.
+
+ @param[in] ConfigBlockTableAddress The pointer to add config blocks
+ @param[in] ComponentBlocks Config blocks array
+ @param[in] TotalBlockCount Number of blocks
+
+ @retval EFI_SUCCESS The policy default is initialized.
+ @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer
+**/
+EFI_STATUS
+EFIAPI
+AddComponentConfigBlocks (
+ IN VOID *ConfigBlockTableAddress,
+ IN COMPONENT_BLOCK_ENTRY *ComponentBlocks,
+ IN UINT16 TotalBlockCount
+ );
+#endif // _SI_CONFIG_BLOCK_LIB_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/SiPolicyLib.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/SiPolicyLib.h
new file mode 100644
index 0000000000..f821ea2fdf
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/SiPolicyLib.h
@@ -0,0 +1,39 @@
+/** @file
+ Prototype of the SiPolicyLib library.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _SI_POLICY_LIB_H_
+#define _SI_POLICY_LIB_H_
+
+#include <Ppi/SiPolicy.h>
+
+/**
+ SiPreMemInstallPolicyReadyPpi installs SiPreMemPolicyReadyPpi.
+ While installed, RC assumes the Policy is ready and finalized. So please update and override
+ any setting before calling this function.
+
+ @retval EFI_SUCCESS The policy is installed.
+ @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer
+**/
+EFI_STATUS
+EFIAPI
+SiPreMemInstallPolicyReadyPpi (
+ VOID
+ );
+
+/**
+ SiInstallPolicyReadyPpi installs SiPolicyReadyPpi.
+ While installed, RC assumes the Policy is ready and finalized. So please update and override
+ any setting before calling this function.
+
+ @retval EFI_SUCCESS The policy is installed.
+ @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer
+**/
+EFI_STATUS
+EFIAPI
+SiInstallPolicyReadyPpi (
+ VOID
+ );
+#endif // _SI_POLICY_LIB_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/SpiLib.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/SpiLib.h
new file mode 100644
index 0000000000..ca56e74e0f
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/SpiLib.h
@@ -0,0 +1,21 @@
+/** @file
+ Header file for Spi Library.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _SPI_LIB_H_
+#define _SPI_LIB_H_
+
+/**
+ This function Initial SPI services
+
+ @retval EFI_STATUS Results of the installation of the SPI services
+**/
+EFI_STATUS
+EFIAPI
+SpiServiceInit (
+ VOID
+ );
+
+#endif
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Pins/GpioPinsVer2Lp.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Pins/GpioPinsVer2Lp.h
new file mode 100644
index 0000000000..2f58de78f6
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Pins/GpioPinsVer2Lp.h
@@ -0,0 +1,36 @@
+/** @file
+ GPIO pins for TGL-PCH-LP,
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _GPIO_PINS_VER2_LP_H_
+#define _GPIO_PINS_VER2_LP_H_
+///
+/// This header file should be used together with
+/// PCH GPIO lib in C and ASL. All defines used
+/// must match both ASL/C syntax
+///
+
+///
+/// Unique ID used in GpioPad defines
+///
+#define GPIO_VER2_LP_CHIPSET_ID 0x9
+
+///
+/// TGL LP GPIO pins
+/// Use below for functions from PCH GPIO Lib which
+/// require GpioPad as argument. Encoding used here
+/// has all information required by library functions
+///
+#define GPIO_VER2_LP_GPP_H0 0x09070000
+#define GPIO_VER2_LP_GPP_H1 0x09070001
+#define GPIO_VER2_LP_GPP_D16 0x09080010
+#define GPIO_VER2_LP_GPP_C2 0x090B0002
+
+#define GPIO_VER2_LP_GPP_F9 0x090C0009
+#define GPIO_VER2_LP_GPP_F10 0x090C000A
+#define GPIO_VER2_LP_GPP_F20 0x090C0014
+
+#define GPIO_VER2_LP_GPP_E7 0x090E0007
+#endif // _GPIO_PINS_VER2_LP_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Ppi/FspmArchConfigPpi.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Ppi/FspmArchConfigPpi.h
new file mode 100644
index 0000000000..7ed834b9f5
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Ppi/FspmArchConfigPpi.h
@@ -0,0 +1,32 @@
+/** @file
+ Header file for FSP-M Arch Config PPI
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _FSPM_ARCH_CONFIG_PPI_H_
+#define _FSPM_ARCH_CONFIG_PPI_H_
+
+///
+/// Global ID for the FSPM_ARCH_CONFIG_PPI.
+///
+#define FSPM_ARCH_CONFIG_GUID \
+ { \
+ 0x824d5a3a, 0xaf92, 0x4c0c, { 0x9f, 0x19, 0x19, 0x52, 0x6d, 0xca, 0x4a, 0xbb } \
+ }
+
+///
+/// This PPI provides FSP-M Arch Config PPI.
+///
+typedef struct {
+ UINT8 Revision;
+ UINT8 Reserved[3];
+ VOID *NvsBufferPtr;
+ UINT32 BootLoaderTolumSize;
+ UINT8 Reserved1[4];
+} FSPM_ARCH_CONFIG_PPI;
+
+extern EFI_GUID gFspmArchConfigPpiGuid;
+
+#endif // _FSPM_ARCH_CONFIG_PPI_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Ppi/PeiPreMemSiDefaultPolicy.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Ppi/PeiPreMemSiDefaultPolicy.h
new file mode 100644
index 0000000000..0713dbd55b
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Ppi/PeiPreMemSiDefaultPolicy.h
@@ -0,0 +1,33 @@
+/** @file
+ This file defines the function to initialize default silicon policy PPI.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI_H_
+#define _PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI_H_
+
+//
+// Forward declaration for the PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI.
+//
+typedef struct _PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI;
+
+/**
+ Initialize and install default silicon policy PPI
+**/
+typedef
+EFI_STATUS
+(EFIAPI *PEI_PREMEM_POLICY_INIT) (
+ VOID
+ );
+
+///
+/// This PPI provides function to install default silicon policy
+///
+struct _PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI {
+ PEI_PREMEM_POLICY_INIT PeiPreMemPolicyInit; ///< PeiPreMemPolicyInit()
+};
+
+extern EFI_GUID gSiPreMemDefaultPolicyInitPpiGuid;
+
+#endif // _PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Ppi/PeiSiDefaultPolicy.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Ppi/PeiSiDefaultPolicy.h
new file mode 100644
index 0000000000..83bdbe0f6e
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Ppi/PeiSiDefaultPolicy.h
@@ -0,0 +1,33 @@
+/** @file
+ This file defines the function to initialize default silicon policy PPI.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _PEI_SI_DEFAULT_POLICY_INIT_PPI_H_
+#define _PEI_SI_DEFAULT_POLICY_INIT_PPI_H_
+
+//
+// Forward declaration for the PEI_SI_DEFAULT_POLICY_INIT_PPI.
+//
+typedef struct _PEI_SI_DEFAULT_POLICY_INIT_PPI PEI_SI_DEFAULT_POLICY_INIT_PPI;
+
+/**
+ Initialize and install default silicon policy PPI
+**/
+typedef
+EFI_STATUS
+(EFIAPI *PEI_POLICY_INIT) (
+ VOID
+ );
+
+///
+/// This PPI provides function to install default silicon policy
+///
+struct _PEI_SI_DEFAULT_POLICY_INIT_PPI {
+ PEI_POLICY_INIT PeiPolicyInit; ///< PeiPolicyInit()
+};
+
+extern EFI_GUID gSiDefaultPolicyInitPpiGuid;
+
+#endif // _PEI_SI_DEFAULT_POLICY_INIT_PPI_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Ppi/Spi.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Ppi/Spi.h
new file mode 100644
index 0000000000..0faf1e3443
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Ppi/Spi.h
@@ -0,0 +1,29 @@
+/** @file
+ This file defines the PCH SPI PPI which implements the
+ Intel(R) PCH SPI Host Controller Compatibility Interface.
+
+ @note The APIs in this file are designed to be backward compatible with
+ previous versions. Any change in behavior of these APIs will result in
+ newer version of the API.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _PCH_SPI_PPI_H_
+#define _PCH_SPI_PPI_H_
+
+#include <Protocol/Spi.h>
+
+//
+// Extern the GUID for PPI users.
+//
+extern EFI_GUID gPchSpiPpiGuid;
+
+/**
+ Reuse the PCH_SPI_PROTOCOL definitions
+ This is possible becaues the PPI implementation does not rely on a PeiService pointer,
+ as it uses EDKII Glue Lib to do IO accesses
+**/
+typedef PCH_SPI_PROTOCOL PCH_SPI_PPI;
+
+#endif
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Ppi/Wdt.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Ppi/Wdt.h
new file mode 100644
index 0000000000..bd8163fea0
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Ppi/Wdt.h
@@ -0,0 +1,22 @@
+/** @file
+ Watchdog Timer PPI
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _PEI_WDT_H_
+#define _PEI_WDT_H_
+
+#include <Protocol/Wdt.h>
+
+//
+// Extern the GUID for PPI users.
+//
+extern EFI_GUID gWdtPpiGuid;
+
+///
+/// Reuse WDT_PROTOCOL definition
+///
+typedef WDT_PROTOCOL WDT_PPI;
+
+#endif
--
2.36.1.windows.1
-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#108724): https://edk2.groups.io/g/devel/message/108724
Mute This Topic: https://groups.io/mt/101373950/7686176
Group Owner: devel+owner@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [rebecca@openfw.io]
-=-=-=-=-=-=-=-=-=-=-=-
^ permalink raw reply related [flat|nested] 41+ messages in thread
* Re: [edk2-devel] [PATCH v2 07/10] AlderlakeSiliconPkg/Include: Add Protocol, Register, Other Includes
2023-09-15 5:43 ` Chaganty, Rangasai V
@ 2023-09-15 13:28 ` Chuang, Rosen
0 siblings, 0 replies; 41+ messages in thread
From: Chuang, Rosen @ 2023-09-15 13:28 UTC (permalink / raw)
To: Chaganty, Rangasai V, Kasbekar, Saloni, devel@edk2.groups.io
Cc: Desimone, Nathaniel L
Reviewed-by: Rosen Chuang <rosen.chuang@intel.com>
-----Original Message-----
From: Chaganty, Rangasai V <rangasai.v.chaganty@intel.com>
Sent: Friday, September 15, 2023 1:43 PM
To: Kasbekar, Saloni <saloni.kasbekar@intel.com>; devel@edk2.groups.io
Cc: Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>; Chuang, Rosen <rosen.chuang@intel.com>
Subject: RE: [PATCH v2 07/10] AlderlakeSiliconPkg/Include: Add Protocol, Register, Other Includes
Reviewed-by: Sai Chaganty <rangasai.v.chaganty@intel.com>
-----Original Message-----
From: Kasbekar, Saloni <saloni.kasbekar@intel.com>
Sent: Thursday, September 14, 2023 9:46 PM
To: devel@edk2.groups.io
Cc: Kasbekar, Saloni <saloni.kasbekar@intel.com>; Chaganty, Rangasai V <rangasai.v.chaganty@intel.com>; Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>; Chuang, Rosen <rosen.chuang@intel.com>
Subject: [PATCH v2 07/10] AlderlakeSiliconPkg/Include: Add Protocol, Register, Other Includes
Adds the following Includes:
- Include/
- Include/Protocol
- Include/Register
Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Rosen Chuang <rosen.chuang@intel.com>
Signed-off-by: Saloni Kasbekar <saloni.kasbekar@intel.com>
---
.../AlderlakeSiliconPkg/Include/ConfigBlock.h | 53 +++
.../AlderlakeSiliconPkg/Include/CpuPcieHob.h | 48 +++
.../Include/Protocol/IgdOpRegion.h | 22 ++
.../Include/Protocol/Spi.h | 346 ++++++++++++++++++
.../Include/Protocol/Wdt.h | 111 ++++++
.../Include/Register/FlashRegs.h | 73 ++++
.../Include/Register/GpioRegs.h | 103 ++++++
.../Include/Register/GpioRegsVer2.h | 211 +++++++++++
.../Include/Register/PchDmi14Regs.h | 49 +++
.../Include/Register/PchDmiRegs.h | 51 +++
.../Include/Register/PchPcieRpRegs.h | 45 +++
.../Include/Register/PchRegsLpc.h | 77 ++++
.../Include/Register/PmcRegs.h | 134 +++++++
.../Include/Register/RtcRegs.h | 44 +++
.../Include/Register/TcoRegs.h | 71 ++++
.../Include/SerialIoDevices.h | 226 ++++++++++++
.../AlderlakeSiliconPkg/Include/SiConfigHob.h | 17 +
.../Include/SiPolicyStruct.h | 64 ++++
18 files changed, 1745 insertions(+)
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/CpuPcieHob.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Protocol/IgdOpRegion.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Protocol/Spi.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Protocol/Wdt.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Register/FlashRegs.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Register/GpioRegs.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Register/GpioRegsVer2.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Register/PchDmi14Regs.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Register/PchDmiRegs.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Register/PchPcieRpRegs.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Register/PchRegsLpc.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Register/PmcRegs.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Register/RtcRegs.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Register/TcoRegs.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/SerialIoDevices.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/SiConfigHob.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/SiPolicyStruct.h
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock.h
new file mode 100644
index 0000000000..2e609bc8d9
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock.h
@@ -0,0 +1,53 @@
+/** @file
+ Header file for Config Block Lib implementation
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _CONFIG_BLOCK_H_
+#define _CONFIG_BLOCK_H_
+
+#include <Uefi/UefiBaseType.h>
+#include <Uefi/UefiMultiPhase.h>
+#include <Pi/PiBootMode.h>
+#include <Pi/PiHob.h>
+
+#pragma pack (push,1)
+
+///
+/// Config Block Header
+///
+typedef struct _CONFIG_BLOCK_HEADER {
+ EFI_HOB_GUID_TYPE GuidHob; ///< Offset 0-23 GUID extension HOB header
+ UINT8 Revision; ///< Offset 24 Revision of this config block
+ UINT8 Attributes; ///< Offset 25 The main revision for config block
+ UINT8 Reserved[2]; ///< Offset 26-27 Reserved for future use
+} CONFIG_BLOCK_HEADER;
+
+///
+/// Config Block
+///
+typedef struct _CONFIG_BLOCK {
+ CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Header of config block
+ //
+ // Config Block Data
+ //
+} CONFIG_BLOCK;
+
+///
+/// Config Block Table Header
+///
+typedef struct _CONFIG_BLOCK_TABLE_STRUCT {
+ CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 GUID number for main entry of config block
+ UINT8 Rsvd0[2]; ///< Offset 28-29 Reserved for future use
+ UINT16 NumberOfBlocks; ///< Offset 30-31 Number of config blocks (N)
+ UINT32 AvailableSize; ///< Offset 32-35 Current config block table size
+///
+/// Individual Config Block Structures are added here in memory as part of AddConfigBlock()
+///
+} CONFIG_BLOCK_TABLE_HEADER;
+#pragma pack (pop)
+
+#endif // _CONFIG_BLOCK_H_
+
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/CpuPcieHob.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/CpuPcieHob.h
new file mode 100644
index 0000000000..dccd6e7d7a
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/CpuPcieHob.h
@@ -0,0 +1,48 @@
+/** @file
+ The GUID definition for CpuPcieHob
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _CPU_PCIE_HOB_H_
+#define _CPU_PCIE_HOB_H_
+
+#include <Base.h>
+#include <CpuPcieInfo.h>
+#include <CpuPcieConfig.h>
+
+extern EFI_GUID gCpuPcieHobGuid;
+#pragma pack (push,1)
+
+
+/**
+ The CPU_PCIE_HOB block describes the expected configuration of the CpuPcie controllers
+**/
+typedef struct {
+ ///
+ /// These members describe the configuration of each CPU PCIe root port.
+ ///
+ EFI_HOB_GUID_TYPE EfiHobGuidType; ///< Offset 0 - 23: GUID Hob type structure for gCpuPcieHobGuid
+ CPU_PCIE_ROOT_PORT_CONFIG RootPort[CPU_PCIE_MAX_ROOT_PORTS];
+ UINT8 L1SubStates[CPU_PCIE_MAX_ROOT_PORTS]; ///< The L1 Substates configuration of the root port
+
+ UINT32 DekelFwVersionMinor; ///< Dekel Firmware Minor Version
+ UINT32 DekelFwVersionMajor; ///< Dekel Firmware Major Version
+ BOOLEAN InitPcieAspmAfterOprom; ///< 1=initialize PCIe ASPM after Oprom; 0=before (This will be set basing on policy)
+ UINT32 RpEnabledMask; ///< Rootport enabled mask based on DEVEN register
+ UINT32 RpEnMaskFromDevEn; ///< Rootport enabled mask based on Device Id
+ UINT8 DisableClkReqMsg[CPU_PCIE_MAX_ROOT_PORTS]; ///< 1=ClkReqMsg disabled, 0=ClkReqMsg enabled
+ UINT8 SlotSelection; ///< 1=M2 slot, 0=CEMx4 slot
+ BOOLEAN ComplianceTest; ///< Compliance Test based on policy
+ UINT32 HsPhyRecipeVersionMajor; ///< HS-Phy Recipe Major Version
+ UINT32 HsPhyRecipeVersionMinor; ///< HS-Phy Recipe Minor Version
+ UINT32 HsPhyFwProdMajor; ///< HS-Phy Firmware Product Major Verison
+ UINT32 HsPhyFwProdMinor; ///< HS-Phy Firmware Product Minor Verison
+ UINT32 HsPhyFwHotFix; ///< HS-Phy Firmware Hot Fix Version
+ UINT32 HsPhyFwBuild; ///< HS-Phy Firmware Build version
+ UINT32 HsPhyFwEvBitProgMajor; ///< HS-Phy Firmware EV Bit Prog Major
+ UINT32 HsPhyFwEvBitProgMinor; ///< HS-Phy Firmware EV Bit Prog Minor
+ UINT32 HsPhyMap; ///< HS-Phy Mapping Based on HS-Py supported ports
+} CPU_PCIE_HOB;
+#pragma pack (pop)
+#endif
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Protocol/IgdOpRegion.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Protocol/IgdOpRegion.h
new file mode 100644
index 0000000000..9f69671f35
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Protocol/IgdOpRegion.h
@@ -0,0 +1,22 @@
+/** @file
+ This file is part of the IGD OpRegion Implementation. The IGD OpRegion is
+ an interface between system BIOS, ASL code, and Graphics drivers.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _IGD_OPREGION_PROTOCOL_H_
+#define _IGD_OPREGION_PROTOCOL_H_
+
+#include <IndustryStandard/IgdOpRegion.h>
+
+extern EFI_GUID gIgdOpRegionProtocolGuid;
+
+///
+/// IGD OpRegion Protocol
+///
+typedef struct {
+ IGD_OPREGION_STRUCTURE *OpRegion; ///< IGD Operation Region Structure
+} IGD_OPREGION_PROTOCOL;
+
+#endif
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Protocol/Spi.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Protocol/Spi.h
new file mode 100644
index 0000000000..cbf2883fa4
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Protocol/Spi.h
@@ -0,0 +1,346 @@
+/** @file
+ This file defines the PCH SPI Protocol which implements the
+ Intel(R) PCH SPI Host Controller Compatibility Interface.
+
+ @note The APIs in this file are designed to be backward compatible with
+ previous versions. Any change in behavior of these APIs will result in
+ newer version of the API.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _PCH_SPI_PROTOCOL_H_
+#define _PCH_SPI_PROTOCOL_H_
+
+//
+// Extern the GUID for protocol users.
+//
+extern EFI_GUID gPchSpiProtocolGuid;
+extern EFI_GUID gPchSmmSpiProtocolGuid;
+
+//
+// Forward reference for ANSI C compatibility
+//
+typedef struct _PCH_SPI_PROTOCOL PCH_SPI_PROTOCOL;
+
+//
+// SPI protocol data structures and definitions
+//
+
+/**
+ Flash Region Type
+**/
+typedef enum {
+ FlashRegionDescriptor,
+ FlashRegionBios,
+ FlashRegionMe,
+ FlashRegionGbE,
+ FlashRegionPlatformData,
+ FlashRegionDer,
+ FlashRegionSecondaryBios,
+ FlashRegionuCodePatch,
+ FlashRegionEC,
+ FlashRegionDeviceExpansion2,
+ FlashRegionIE,
+ FlashRegion10Gbe_A,
+ FlashRegion10Gbe_B,
+ FlashRegion13,
+ FlashRegion14,
+ FlashRegion15,
+ FlashRegionAll,
+ FlashRegionMax
+} FLASH_REGION_TYPE;
+
+//
+// Protocol member functions
+//
+
+/**
+ Read data from the flash part.
+
+ @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
+ @param[in] FlashRegionType The Flash Region type for flash cycle which
+ is listed in the Descriptor.
+ @param[in] Address The Flash Linear Address must fall within a
+ region for which BIOS has access permissions.
+ @param[in] ByteCount Number of bytes in the data portion of the
+ SPI cycle.
+ @param[out] Buffer The Pointer to caller-allocated buffer
+ containing the dada received.
+ It is the caller's responsibility to make
+ sure Buffer is large enough for the total
+ number of bytes read.
+
+ @retval EFI_SUCCESS Command succeed.
+ @retval EFI_INVALID_PARAMETER The parameters specified are not valid.
+ @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *PCH_SPI_FLASH_READ) (
+ IN PCH_SPI_PROTOCOL *This,
+ IN FLASH_REGION_TYPE FlashRegionType,
+ IN UINT32 Address,
+ IN UINT32 ByteCount,
+ OUT UINT8 *Buffer
+ );
+
+/**
+ Write data to the flash part. Remark: Erase may be needed before write to the
+ flash part.
+
+ @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
+ @param[in] FlashRegionType The Flash Region type for flash cycle which
+ is listed in the Descriptor.
+ @param[in] Address The Flash Linear Address must fall within a
+ region for which BIOS has access permissions.
+ @param[in] ByteCount Number of bytes in the data portion of the
+ SPI cycle.
+ @param[in] Buffer Pointer to caller-allocated buffer containing
+ the data sent during the SPI cycle.
+
+ @retval EFI_SUCCESS Command succeed.
+ @retval EFI_INVALID_PARAMETER The parameters specified are not valid.
+ @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *PCH_SPI_FLASH_WRITE) (
+ IN PCH_SPI_PROTOCOL *This,
+ IN FLASH_REGION_TYPE FlashRegionType,
+ IN UINT32 Address,
+ IN UINT32 ByteCount,
+ IN UINT8 *Buffer
+ );
+
+/**
+ Erase area on the flash part.
+
+ @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
+ @param[in] FlashRegionType The Flash Region type for flash cycle which
+ is listed in the Descriptor.
+ @param[in] Address The Flash Linear Address must fall within a
+ region for which BIOS has access permissions.
+ @param[in] ByteCount Number of bytes in the data portion of the
+ SPI cycle.
+
+ @retval EFI_SUCCESS Command succeed.
+ @retval EFI_INVALID_PARAMETER The parameters specified are not valid.
+ @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *PCH_SPI_FLASH_ERASE) (
+ IN PCH_SPI_PROTOCOL *This,
+ IN FLASH_REGION_TYPE FlashRegionType,
+ IN UINT32 Address,
+ IN UINT32 ByteCount
+ );
+
+/**
+ Read SFDP data from the flash part.
+
+ @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
+ @param[in] ComponentNumber The Componen Number for chip select
+ @param[in] Address The starting byte address for SFDP data read.
+ @param[in] ByteCount Number of bytes in SFDP data portion of the
+ SPI cycle
+ @param[out] SfdpData The Pointer to caller-allocated buffer
+ containing the SFDP data received
+ It is the caller's responsibility to make
+ sure Buffer is large enough for the total
+ number of bytes read
+
+ @retval EFI_SUCCESS Command succeed.
+ @retval EFI_INVALID_PARAMETER The parameters specified are not valid.
+ @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *PCH_SPI_FLASH_READ_SFDP) (
+ IN PCH_SPI_PROTOCOL *This,
+ IN UINT8 ComponentNumber,
+ IN UINT32 Address,
+ IN UINT32 ByteCount,
+ OUT UINT8 *SfdpData
+ );
+
+/**
+ Read Jedec Id from the flash part.
+
+ @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
+ @param[in] ComponentNumber The Componen Number for chip select
+ @param[in] ByteCount Number of bytes in JedecId data portion of
+ the SPI cycle, the data size is 3 typically
+ @param[out] JedecId The Pointer to caller-allocated buffer
+ containing JEDEC ID received.
+ It is the caller's responsibility to make
+ sure Buffer is large enough for the total
+ number of bytes read.
+
+ @retval EFI_SUCCESS Command succeed.
+ @retval EFI_INVALID_PARAMETER The parameters specified are not valid.
+ @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *PCH_SPI_FLASH_READ_JEDEC_ID) (
+ IN PCH_SPI_PROTOCOL *This,
+ IN UINT8 ComponentNumber,
+ IN UINT32 ByteCount,
+ OUT UINT8 *JedecId
+ );
+
+/**
+ Write the status register in the flash part.
+
+ @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
+ @param[in] ByteCount Number of bytes in Status data portion of the
+ SPI cycle, the data size is 1 typically
+ @param[in] StatusValue The Pointer to caller-allocated buffer
+ containing the value of Status register writing
+
+ @retval EFI_SUCCESS Command succeed.
+ @retval EFI_INVALID_PARAMETER The parameters specified are not valid.
+ @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *PCH_SPI_FLASH_WRITE_STATUS) (
+ IN PCH_SPI_PROTOCOL *This,
+ IN UINT32 ByteCount,
+ IN UINT8 *StatusValue
+ );
+
+/**
+ Read status register in the flash part.
+
+ @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
+ @param[in] ByteCount Number of bytes in Status data portion of the
+ SPI cycle, the data size is 1 typically
+ @param[out] StatusValue The Pointer to caller-allocated buffer
+ containing the value of Status register received.
+
+ @retval EFI_SUCCESS Command succeed.
+ @retval EFI_INVALID_PARAMETER The parameters specified are not valid.
+ @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *PCH_SPI_FLASH_READ_STATUS) (
+ IN PCH_SPI_PROTOCOL *This,
+ IN UINT32 ByteCount,
+ OUT UINT8 *StatusValue
+ );
+
+/**
+ Get the SPI region base and size, based on the enum type
+
+ @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
+ @param[in] FlashRegionType The Flash Region type for for the base address
+ which is listed in the Descriptor.
+ @param[out] BaseAddress The Flash Linear Address for the Region 'n'
+ Base
+ @param[out] RegionSize The size for the Region 'n'
+
+ @retval EFI_SUCCESS Read success
+ @retval EFI_INVALID_PARAMETER Invalid region type given
+ @retval EFI_DEVICE_ERROR The region is not used
+**/
+typedef
+EFI_STATUS
+(EFIAPI *PCH_SPI_GET_REGION_ADDRESS) (
+ IN PCH_SPI_PROTOCOL *This,
+ IN FLASH_REGION_TYPE FlashRegionType,
+ OUT UINT32 *BaseAddress,
+ OUT UINT32 *RegionSize
+ );
+
+/**
+ Read PCH Soft Strap Values
+
+ @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
+ @param[in] SoftStrapAddr PCH Soft Strap address offset from FPSBA.
+ @param[in] ByteCount Number of bytes in SoftStrap data portion of
+ the SPI cycle
+ @param[out] SoftStrapValue The Pointer to caller-allocated buffer
+ containing PCH Soft Strap Value.
+ If the value of ByteCount is 0, the data type
+ of SoftStrapValue should be UINT16 and
+ SoftStrapValue will be PCH Soft Strap Length.
+ It is the caller's responsibility to make sure
+ Buffer is large enough for the total number of
+ bytes read.
+
+ @retval EFI_SUCCESS Command succeed.
+ @retval EFI_INVALID_PARAMETER The parameters specified are not valid.
+ @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *PCH_SPI_READ_PCH_SOFTSTRAP) (
+ IN PCH_SPI_PROTOCOL *This,
+ IN UINT32 SoftStrapAddr,
+ IN UINT32 ByteCount,
+ OUT VOID *SoftStrapValue
+ );
+
+/**
+ Read CPU Soft Strap Values
+
+ @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
+ @param[in] SoftStrapAddr CPU Soft Strap address offset from FCPUSBA.
+ @param[in] ByteCount Number of bytes in SoftStrap data portion of
+ the SPI cycle.
+ @param[out] SoftStrapValue The Pointer to caller-allocated buffer
+ containing CPU Soft Strap Value.
+ If the value of ByteCount is 0, the data type
+ of SoftStrapValue should be UINT16 and
+ SoftStrapValue will be PCH Soft Strap Length
+ It is the caller's responsibility to make sure
+ Buffer is large enough for the total number
+ of bytes read.
+
+ @retval EFI_SUCCESS Command succeed.
+ @retval EFI_INVALID_PARAMETER The parameters specified are not valid.
+ @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *PCH_SPI_READ_CPU_SOFTSTRAP) (
+ IN PCH_SPI_PROTOCOL *This,
+ IN UINT32 SoftStrapAddr,
+ IN UINT32 ByteCount,
+ OUT VOID *SoftStrapValue
+ );
+
+/**
+ These protocols/PPI allows a platform module to perform SPI operations
+ through the Intel PCH SPI Host Controller Interface.
+**/
+struct _PCH_SPI_PROTOCOL {
+ /**
+ This member specifies the revision of this structure. This field is
+ used to indicate backwards compatible changes to the protocol.
+ **/
+ UINT8 Revision;
+ PCH_SPI_FLASH_READ FlashRead; ///< Read data from the flash part.
+ PCH_SPI_FLASH_WRITE FlashWrite; ///< Write data to the flash part. Remark: Erase may be needed before write to the flash part.
+ PCH_SPI_FLASH_ERASE FlashErase; ///< Erase some area on the flash part.
+ PCH_SPI_FLASH_READ_SFDP FlashReadSfdp; ///< Read SFDP data from the flash part.
+ PCH_SPI_FLASH_READ_JEDEC_ID FlashReadJedecId; ///< Read Jedec Id from the flash part.
+ PCH_SPI_FLASH_WRITE_STATUS FlashWriteStatus; ///< Write the status register in the flash part.
+ PCH_SPI_FLASH_READ_STATUS FlashReadStatus; ///< Read status register in the flash part.
+ PCH_SPI_GET_REGION_ADDRESS GetRegionAddress; ///< Get the SPI region base and size
+ PCH_SPI_READ_PCH_SOFTSTRAP ReadPchSoftStrap; ///< Read PCH Soft Strap Values
+ PCH_SPI_READ_CPU_SOFTSTRAP ReadCpuSoftStrap; ///< Read CPU Soft Strap Values
+};
+
+/**
+ PCH SPI PPI/PROTOCOL revision number
+
+ Revision 1: Initial version
+**/
+#define PCH_SPI_SERVICES_REVISION 1
+
+#endif
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Protocol/Wdt.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Protocol/Wdt.h
new file mode 100644
index 0000000000..a68085fa54
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Protocol/Wdt.h
@@ -0,0 +1,111 @@
+/** @file
+ Watchdog Timer protocol
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _DXE_WDT_H_
+#define _DXE_WDT_H_
+
+//
+// Extern the GUID for protocol users.
+//
+extern EFI_GUID gWdtProtocolGuid;
+//
+// Forward reference for ANSI C compatibility
+//
+typedef struct _WDT_PROTOCOL WDT_PROTOCOL;
+
+/**
+ Reloads WDT with new timeout value and starts it. Also sets Unexpected Reset bit, which
+ causes the next reset to be treated as watchdog expiration - unless AllowKnownReset()
+ function was called too.
+
+ @param[in] TimeoutValue Time in seconds before WDT times out. Supported range = 1 - 1024.
+
+ @retval EFI_SUCCESS if everything's OK
+ @retval EFI_INVALID_PARAMETER if TimeoutValue parameter is wrong
+**/
+typedef
+EFI_STATUS
+(EFIAPI *WDT_RELOAD_AND_START) (
+ UINT32 TimeoutValue
+ );
+
+/**
+ Returns WDT failure status.
+
+ @retval V_PCH_OC_WDT_CTL_STATUS_FAILURE If there was WDT expiration or unexpected reset
+ @retval V_PCH_OC_WDT_CTL_STATUS_OK Otherwise
+**/
+typedef
+UINT8
+(EFIAPI *WDT_CHECK_STATUS) (
+ VOID
+ );
+
+/**
+ Returns information if WDT coverage for the duration of BIOS execution
+ was requested by an OS application.
+
+ @retval TRUE if WDT was requested
+ @retval FALSE if WDT was not requested
+**/
+typedef
+UINT8
+(EFIAPI *IS_WDT_REQUIRED) (
+ VOID
+ );
+
+/**
+ Returns WDT enabled/disabled status.
+
+ @retval TRUE if WDT is enabled
+ @retval FALSE if WDT is disabled
+**/
+typedef
+UINT8
+(EFIAPI *IS_WDT_ENABLED) (
+ VOID
+ );
+
+/**
+ Disables WDT timer.
+**/
+typedef
+VOID
+(EFIAPI *WDT_DISABLE) (
+ VOID
+ );
+
+/**
+ Normally, each reboot performed while watchdog runs is considered a failure.
+ This function allows platform to perform expected reboots with WDT running,
+ without being interpreted as failures.
+ In DXE phase, it is enough to call this function any time before reset.
+ In PEI phase, between calling this function and performing reset, ReloadAndStart()
+ must not be called.
+**/
+typedef
+VOID
+(EFIAPI *WDT_ALLOW_KNOWN_RESET) (
+ VOID
+ );
+
+/**
+ These protocols and PPI allow a platform module to perform watch dog timer operations
+ through the Intel PCH LPC Host Controller Interface. The WDT protocol and WDT PPI
+ implement the Intel (R) Watch Dog timer for DXE, and PEI environments, respectively.
+ WDT_PROTOCOL referenced hereafter represents both WDT_PROTOCOL and WDT_PPI, as they
+ share the identical data structure.
+**/
+struct _WDT_PROTOCOL {
+ WDT_RELOAD_AND_START ReloadAndStart; ///< Reloads WDT with new timeout value and starts it.
+ WDT_CHECK_STATUS CheckStatus; ///< Returns WDT failure status.
+ WDT_DISABLE Disable; ///< Disables WDT timer.
+ WDT_ALLOW_KNOWN_RESET AllowKnownReset; ///< Perform expected reboots with WDT running, without being interpreted as failures.
+ IS_WDT_REQUIRED IsWdtRequired; ///< Returns information if WDT coverage for the duration of BIOS execution was requested by an OS application.
+ IS_WDT_ENABLED IsWdtEnabled; ///< Returns WDT enabled/disabled status.
+};
+
+#endif
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/FlashRegs.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/FlashRegs.h
new file mode 100644
index 0000000000..860f823655
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/FlashRegs.h
@@ -0,0 +1,73 @@
+/** @file
+ Register names for Flash registers
+
+ Conventions:
+
+ - Register definition format:
+ Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_RegisterName
+ - Prefix:
+ Definitions beginning with "R_" are registers
+ Definitions beginning with "B_" are bits within registers
+ Definitions beginning with "V_" are meaningful values within the bits
+ Definitions beginning with "S_" are register size
+ Definitions beginning with "N_" are the bit position
+ - [GenerationName]:
+ Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc.).
+ Register name without GenerationName applies to all generations.
+ - [ComponentName]:
+ This field indicates the component name that the register belongs to (e.g. PCH, SA etc.)
+ Register name without ComponentName applies to all components.
+ Register that is specific to -H denoted by "_PCH_H_" in component name.
+ Register that is specific to -LP denoted by "_PCH_LP_" in component name.
+ - SubsystemName:
+ This field indicates the subsystem name of the component that the register belongs to
+ (e.g. PCIE, USB, SATA, GPIO, PMC etc.).
+ - RegisterSpace:
+ MEM - MMIO space register of subsystem.
+ IO - IO space register of subsystem.
+ PCR - Private configuration register of subsystem.
+ CFG - PCI configuration space register of subsystem.
+ - RegisterName:
+ Full register name.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _FLASH_REGS_H_
+#define _FLASH_REGS_H_
+
+
+//
+// Flash Descriptor Base Address Region (FDBAR) from Flash Region 0
+//
+#define R_FLASH_FDBAR_FLASH_MAP0 0x04
+#define B_FLASH_FDBAR_NC 0x00000300 ///< Number Of Components
+#define N_FLASH_FDBAR_NC 8 ///< Number Of Components
+#define R_FLASH_FDBAR_FLASH_MAP1 0x08
+#define B_FLASH_FDBAR_FPSBA 0x00FF0000 ///< PCH Strap Base Address, [23:16] represents [11:4]
+#define N_FLASH_FDBAR_FPSBA 16 ///< PCH Strap base Address bit position
+#define N_FLASH_FDBAR_FPSBA_REPR 4 ///< PCH Strap base Address bit represents position
+#define B_FLASH_FDBAR_PCHSL 0xFF000000 ///< PCH Strap Length, [31:24] represents number of Dwords
+#define N_FLASH_FDBAR_PCHSL 24 ///< PCH Strap Length bit position
+#define R_FLASH_FDBAR_FLASH_MAP2 0x0C
+#define B_FLASH_FDBAR_FCPUSBA 0x00000FFC ///< CPU Strap Base Address [11:2]
+#define N_FLASH_FDBAR_FCPUSBA 2 ///< CPU Strap Base Address bit position
+#define B_FLASH_FDBAR_CPUSL 0x00FF0000 ///< CPU Strap Length, [23:16] represents number of Dwords
+#define N_FLASH_FDBAR_CPUSL 16 ///< CPU Strap Length bit position
+
+//
+// Flash Component Base Address (FCBA) from Flash Region 0
+//
+#define R_FLASH_FCBA_FLCOMP 0x00 ///< Flash Components Register
+#define B_FLASH_FLCOMP_COMP1_MASK 0xF0 ///< Flash Component 1 Size MASK
+#define N_FLASH_FLCOMP_COMP1 4 ///< Flash Component 1 Size bit position
+#define B_FLASH_FLCOMP_COMP0_MASK 0x0F ///< Flash Component 0 Size MASK
+#define V_FLASH_FLCOMP_COMP_512KB 0x80000
+//
+// Descriptor Upper Map Section from Flash Region 0
+//
+#define R_FLASH_UMAP1 0xEFC ///< Flash Upper Map 1
+#define B_FLASH_UMAP1_MDTBA 0xFF000000 ///< MIP Descriptor Table Base Address
+#define N_FLASH_UMAP1_MDTBA 24 ///< MDTBA bits position
+#define N_FLASH_UMAP1_MDTBA_REPR 4 ///< MDTBA address representation position
+#endif
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/GpioRegs.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/GpioRegs.h
new file mode 100644
index 0000000000..c89dccb7bd
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/GpioRegs.h
@@ -0,0 +1,103 @@
+/** @file
+ Register names for PCH GPIO
+
+Conventions:
+
+ - Register definition format:
+ Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_RegisterName
+ - Prefix:
+ Definitions beginning with "R_" are registers
+ Definitions beginning with "B_" are bits within registers
+ Definitions beginning with "V_" are meaningful values within the bits
+ Definitions beginning with "S_" are register size
+ Definitions beginning with "N_" are the bit position
+ - [GenerationName]:
+ Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc.).
+ Register name without GenerationName applies to all generations.
+ - [ComponentName]:
+ This field indicates the component name that the register belongs to (e.g. PCH, SA etc.)
+ Register name without ComponentName applies to all components.
+ Register that is specific to -H denoted by "_PCH_H_" in component name.
+ Register that is specific to -LP denoted by "_PCH_LP_" in component name.
+ - SubsystemName:
+ This field indicates the subsystem name of the component that the register belongs to
+ (e.g. PCIE, USB, SATA, GPIO, PMC etc.).
+ - RegisterSpace:
+ MEM - MMIO space register of subsystem.
+ IO - IO space register of subsystem.
+ PCR - Private configuration register of subsystem.
+ CFG - PCI configuration space register of subsystem.
+ - RegisterName:
+ Full register name.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _GPIO_REGS_H_
+#define _GPIO_REGS_H_
+
+//
+// PADCFG register is split into multiple DW registers
+// S_GPIO_PCR_PADCFG refers to number of bytes used by all those registers for one pad
+//
+#define S_GPIO_PCR_PADCFG 0x10
+
+//
+// Pad Configuration Register DW0
+//
+
+
+//RX Raw Override to 1
+#define B_GPIO_PCR_RX_RAW1 BIT28
+#define N_GPIO_PCR_RX_RAW1 28
+
+//RX Level/Edge Configuration
+#define B_GPIO_PCR_RX_LVL_EDG (BIT26 | BIT25)
+#define N_GPIO_PCR_RX_LVL_EDG 25
+
+//RX Invert
+#define B_GPIO_PCR_RXINV BIT23
+#define N_GPIO_PCR_RXINV 23
+
+//GPIO Input Route IOxAPIC
+#define B_GPIO_PCR_RX_APIC_ROUTE BIT20
+
+//GPIO Input Route SCI
+#define B_GPIO_PCR_RX_SCI_ROUTE BIT19
+
+//GPIO Input Route SMI
+#define B_GPIO_PCR_RX_SMI_ROUTE BIT18
+
+//GPIO Input Route NMI
+#define B_GPIO_PCR_RX_NMI_ROUTE BIT17
+#define N_GPIO_PCR_RX_NMI_ROUTE 17
+
+//GPIO Pad Mode
+#define B_GPIO_PCR_PAD_MODE (BIT12 | BIT11 | BIT10)
+#define N_GPIO_PCR_PAD_MODE 10
+
+//GPIO RX Disable
+#define B_GPIO_PCR_RXDIS BIT9
+
+//GPIO TX Disable
+#define B_GPIO_PCR_TXDIS BIT8
+#define N_GPIO_PCR_TXDIS 8
+
+//GPIO TX State
+#define B_GPIO_PCR_TX_STATE BIT0
+#define N_GPIO_PCR_TX_STATE 0
+
+//Termination
+#define B_GPIO_PCR_TERM (BIT13 | BIT12 | BIT11 | BIT10)
+#define N_GPIO_PCR_TERM 10
+
+
+///
+/// GPIO SMI data used for EFI_SMM_GPI_DISPATCH2_PROTOCOL
+/// Below defines are to be used internally by PCH SMI dispatcher only
+///
+#define PCH_GPIO_NUM_SUPPORTED_GPIS 512
+#define S_GPIO_PCR_GP_SMI_STS 4
+
+#endif // _GPIO_REGS_H_
+
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/GpioRegsVer2.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/GpioRegsVer2.h
new file mode 100644
index 0000000000..7789236b5e
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/GpioRegsVer2.h
@@ -0,0 +1,211 @@
+/** @file
+ Register names for VER2 GPIO
+
+Conventions:
+
+ - Register definition format:
+ Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_RegisterName
+ - Prefix:
+ Definitions beginning with "R_" are registers
+ Definitions beginning with "B_" are bits within registers
+ Definitions beginning with "V_" are meaningful values within the bits
+ Definitions beginning with "S_" are register size
+ Definitions beginning with "N_" are the bit position
+ - [GenerationName]:
+ Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc.).
+ Register name without GenerationName applies to all generations.
+ - [ComponentName]:
+ This field indicates the component name that the register belongs to (e.g. PCH, SA etc.)
+ Register name without ComponentName applies to all components.
+ Register that is specific to -H denoted by "_PCH_H_" in component name.
+ Register that is specific to -LP denoted by "_PCH_LP_" in component name.
+ - SubsystemName:
+ This field indicates the subsystem name of the component that the register belongs to
+ (e.g. PCIE, USB, SATA, GPIO, PMC etc.).
+ - RegisterSpace:
+ MEM - MMIO space register of subsystem.
+ IO - IO space register of subsystem.
+ PCR - Private configuration register of subsystem.
+ CFG - PCI configuration space register of subsystem.
+ - RegisterName:
+ Full register name.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _GPIO_REGS_VER2_H_
+#define _GPIO_REGS_VER2_H_
+
+#define GPIO_VER2_PCH_LP_GPIO_GPP_B_PAD_MAX 26
+#define GPIO_VER2_PCH_LP_GPIO_GPP_A_PAD_MAX 25
+#define GPIO_VER2_PCH_LP_GPIO_GPP_R_PAD_MAX 8
+#define GPIO_VER2_PCH_LP_GPIO_GPD_PAD_MAX 17
+#define GPIO_VER2_PCH_LP_GPIO_GPP_S_PAD_MAX 8
+#define GPIO_VER2_PCH_LP_GPIO_GPP_H_PAD_MAX 24
+#define GPIO_VER2_PCH_LP_GPIO_GPP_D_PAD_MAX 21
+#define GPIO_VER2_PCH_LP_GPIO_GPP_F_PAD_MAX 25
+#define GPIO_VER2_PCH_LP_GPIO_GPP_C_PAD_MAX 24
+#define GPIO_VER2_PCH_LP_GPIO_GPP_E_PAD_MAX 25
+
+//
+// GPIO Community 0 Private Configuration Registers
+//
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_PAD_OWN 0x20
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_A_PAD_OWN 0x38
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_PADCFGLOCK 0x80
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_PADCFGLOCKTX 0x84
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_A_PADCFGLOCK 0x90
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_A_PADCFGLOCKTX 0x94
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_HOSTSW_OWN 0xB0
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_A_HOSTSW_OWN 0xB8
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_GPI_IS 0x0100
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_A_GPI_IS 0x0108
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_GPI_IE 0x0120
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_A_GPI_IE 0x0128
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_GPI_GPE_STS 0x0140
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_A_GPI_GPE_STS 0x0148
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_GPI_GPE_EN 0x0160
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_A_GPI_GPE_EN 0x0168
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_SMI_STS 0x0180
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_SMI_EN 0x01A0
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_NMI_STS 0x01C0
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_NMI_EN 0x01E0
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_PADCFG_OFFSET 0x700
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_A_PADCFG_OFFSET 0x9A0
+
+//
+// GPIO Community 1 Private Configuration Registers
+//
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_S_PAD_OWN 0x20
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_H_PAD_OWN 0x24
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_PAD_OWN 0x30
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_S_PADCFGLOCK 0x80
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_S_PADCFGLOCKTX 0x84
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_H_PADCFGLOCK 0x88
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_H_PADCFGLOCKTX 0x8C
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_PADCFGLOCK 0x90
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_PADCFGLOCKTX 0x94
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_S_HOSTSW_OWN 0xB0
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_H_HOSTSW_OWN 0xB4
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_HOSTSW_OWN 0xB8
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_S_GPI_IS 0x0100
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_H_GPI_IS 0x0104
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_GPI_IS 0x0108
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_S_GPI_IE 0x0120
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_H_GPI_IE 0x0124
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_GPI_IE 0x0128
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_S_GPI_GPE_STS 0x0140
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_H_GPI_GPE_STS 0x0144
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_GPI_GPE_STS 0x0148
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_S_GPI_GPE_EN 0x0160
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_H_GPI_GPE_EN 0x0164
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_GPI_GPE_EN 0x0168
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_SMI_STS 0x0188
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_SMI_EN 0x01A8
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_NMI_STS 0x01C8
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_NMI_EN 0x01E8
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_S_PADCFG_OFFSET 0x700
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_H_PADCFG_OFFSET 0x780
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_PADCFG_OFFSET 0x900
+//
+// GPIO Community 2 Private Configuration Registers
+//
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPD_PAD_OWN 0x20
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPD_PADCFGLOCK 0x80
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPD_PADCFGLOCKTX 0x84
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPD_HOSTSW_OWN 0xB0
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPD_GPI_IS 0x0100
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPD_GPI_IE 0x0120
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPD_GPI_GPE_STS 0x0140
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPD_GPI_GPE_EN 0x0160
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPD_PADCFG_OFFSET 0x700
+
+//
+// GPIO Community 4 Private Configuration Registers
+//
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_PAD_OWN 0x20
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_F_PAD_OWN 0x2C
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_PAD_OWN 0x40
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_PADCFGLOCK 0x80
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_PADCFGLOCKTX 0x84
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_F_PADCFGLOCK 0x88
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_F_PADCFGLOCKTX 0x8C
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_PADCFGLOCK 0x98
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_PADCFGLOCKTX 0x9C
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_HOSTSW_OWN 0xB0
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_F_HOSTSW_OWN 0xB4
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_HOSTSW_OWN 0xBC
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_GPI_IS 0x0100
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_F_GPI_IS 0x0104
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_GPI_IS 0x010C
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_GPI_IE 0x0120
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_F_GPI_IE 0x0124
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_GPI_IE 0x012C
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_GPI_GPE_STS 0x0140
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_F_GPI_GPE_STS 0x0144
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_GPI_GPE_STS 0x014C
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_GPI_GPE_EN 0x0160
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_F_GPI_GPE_EN 0x0164
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_GPI_GPE_EN 0x016C
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_SMI_STS 0x0180
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_SMI_STS 0x018C
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_SMI_EN 0x01A0
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_SMI_EN 0x01AC
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_NMI_STS 0x01C0
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_NMI_STS 0x01CC
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_NMI_EN 0x01E0
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_NMI_EN 0x01EC
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_PADCFG_OFFSET 0x700
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_F_PADCFG_OFFSET 0x880
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_PADCFG_OFFSET 0xA70
+
+//
+// GPIO Community 5 Private Configuration Registers
+//
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_R_PAD_OWN 0x20
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_R_PADCFGLOCK 0x80
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_R_PADCFGLOCKTX 0x84
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_R_HOSTSW_OWN 0xB0
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_R_GPI_IS 0x0100
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_R_GPI_IE 0x0120
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_R_GPI_GPE_STS 0x0140
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_R_GPI_GPE_EN 0x0160
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_R_PADCFG_OFFSET 0x700
+
+#endif // _GPIO_REGS_VER2_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/PchDmi14Regs.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/PchDmi14Regs.h
new file mode 100644
index 0000000000..f30bf62614
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/PchDmi14Regs.h
@@ -0,0 +1,49 @@
+/** @file
+ Register names for PCH DMI SIP14
+
+Conventions:
+
+ - Register definition format:
+ Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_RegisterName
+ - Prefix:
+ Definitions beginning with "R_" are registers
+ Definitions beginning with "B_" are bits within registers
+ Definitions beginning with "V_" are meaningful values within the bits
+ Definitions beginning with "S_" are register size
+ Definitions beginning with "N_" are the bit position
+ - [GenerationName]:
+ Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc.).
+ Register name without GenerationName applies to all generations.
+ - [ComponentName]:
+ This field indicates the component name that the register belongs to (e.g. PCH, SA etc.)
+ Register name without ComponentName applies to all components.
+ Register that is specific to -H denoted by "_PCH_H_" in component name.
+ Register that is specific to -LP denoted by "_PCH_LP_" in component name.
+ - SubsystemName:
+ This field indicates the subsystem name of the component that the register belongs to
+ (e.g. PCIE, USB, SATA, GPIO, PMC etc.).
+ - RegisterSpace:
+ MEM - MMIO space register of subsystem.
+ IO - IO space register of subsystem.
+ PCR - Private configuration register of subsystem.
+ CFG - PCI configuration space register of subsystem.
+ - RegisterName:
+ Full register name.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _PCH_DMI14_REGS_H_
+#define _PCH_DMI14_REGS_H_
+
+//
+// DMI Chipset Configuration Registers (PID:DMI)
+//
+
+//
+// DMI Control
+//
+#define R_PCH_DMI14_PCR_DMIC 0x2234 ///< DMI Control
+#define B_PCH_DMI14_PCR_DMIC_SRL BIT31 ///< Secured register lock
+
+#endif
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/PchDmiRegs.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/PchDmiRegs.h
new file mode 100644
index 0000000000..649e8dd17b
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/PchDmiRegs.h
@@ -0,0 +1,51 @@
+/** @file
+ Register names for PCH DMI and OP-DMI
+
+Conventions:
+
+ - Register definition format:
+ Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_RegisterName
+ - Prefix:
+ Definitions beginning with "R_" are registers
+ Definitions beginning with "B_" are bits within registers
+ Definitions beginning with "V_" are meaningful values within the bits
+ Definitions beginning with "S_" are register size
+ Definitions beginning with "N_" are the bit position
+ - [GenerationName]:
+ Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc.).
+ Register name without GenerationName applies to all generations.
+ - [ComponentName]:
+ This field indicates the component name that the register belongs to (e.g. PCH, SA etc.)
+ Register name without ComponentName applies to all components.
+ Register that is specific to -H denoted by "_PCH_H_" in component name.
+ Register that is specific to -LP denoted by "_PCH_LP_" in component name.
+ - SubsystemName:
+ This field indicates the subsystem name of the component that the register belongs to
+ (e.g. PCIE, USB, SATA, GPIO, PMC etc.).
+ - RegisterSpace:
+ MEM - MMIO space register of subsystem.
+ IO - IO space register of subsystem.
+ PCR - Private configuration register of subsystem.
+ CFG - PCI configuration space register of subsystem.
+ - RegisterName:
+ Full register name.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _PCH_DMI_REGS_H_
+#define _PCH_DMI_REGS_H_
+
+//
+// PCH DMI Chipset Configuration Registers (PID:DMI)
+//
+
+//
+// PCH DMI Source Decode PCRs (Common)
+//
+#define R_PCH_DMI_PCR_LPCIOD 0x2770 ///< LPC I/O Decode Ranges
+#define R_PCH_DMI_PCR_LPCIOE 0x2774 ///< LPC I/O Enables
+#define R_PCH_DMI_PCR_TCOBASE 0x2778 ///< TCO Base Address
+#define B_PCH_DMI_PCR_TCOBASE_TCOBA 0xFFE0 ///< TCO Base Address Mask
+
+#endif
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/PchPcieRpRegs.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/PchPcieRpRegs.h
new file mode 100644
index 0000000000..17c68cbaaa
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/PchPcieRpRegs.h
@@ -0,0 +1,45 @@
+/** @file
+ Register names for PCH PCI-E root port devices
+
+ Conventions:
+
+ - Register definition format:
+ Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_RegisterName
+ - Prefix:
+ Definitions beginning with "R_" are registers
+ Definitions beginning with "B_" are bits within registers
+ Definitions beginning with "V_" are meaningful values within the bits
+ Definitions beginning with "S_" are register size
+ Definitions beginning with "N_" are the bit position
+ - [GenerationName]:
+ Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc.).
+ Register name without GenerationName applies to all generations.
+ - [ComponentName]:
+ This field indicates the component name that the register belongs to (e.g. PCH, SA etc.)
+ Register name without ComponentName applies to all components.
+ Register that is specific to -H denoted by "_PCH_H_" in component name.
+ Register that is specific to -LP denoted by "_PCH_LP_" in component name.
+ - SubsystemName:
+ This field indicates the subsystem name of the component that the register belongs to
+ (e.g. PCIE, USB, SATA, GPIO, PMC etc.).
+ - RegisterSpace:
+ MEM - MMIO space register of subsystem.
+ IO - IO space register of subsystem.
+ PCR - Private configuration register of subsystem.
+ CFG - PCI configuration space register of subsystem.
+ - RegisterName:
+ Full register name.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _PCH_REGS_PCIE_H_
+#define _PCH_REGS_PCIE_H_
+
+//
+// PCIE PCRs (PID:SPA SPB SPC SPD SPE SPF)
+//
+#define R_SPX_PCR_PCD 0 ///< Port configuration and disable
+#define B_SPX_PCR_PCD_RP1FN (BIT2 | BIT1 | BIT0) ///< Port 1 Function Number
+#define S_SPX_PCR_PCD_RP_FIELD 4 ///< 4 bits for each RP FN
+#endif
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/PchRegsLpc.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/PchRegsLpc.h
new file mode 100644
index 0000000000..326b266352
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/PchRegsLpc.h
@@ -0,0 +1,77 @@
+/** @file
+ Register names for PCH LPC/eSPI device
+
+Conventions:
+
+ - Register definition format:
+ Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_RegisterName
+ - Prefix:
+ Definitions beginning with "R_" are registers
+ Definitions beginning with "B_" are bits within registers
+ Definitions beginning with "V_" are meaningful values within the bits
+ Definitions beginning with "S_" are register size
+ Definitions beginning with "N_" are the bit position
+ - [GenerationName]:
+ Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc.).
+ Register name without GenerationName applies to all generations.
+ - [ComponentName]:
+ This field indicates the component name that the register belongs to (e.g. PCH, SA etc.)
+ Register name without ComponentName applies to all components.
+ Register that is specific to -H denoted by "_PCH_H_" in component name.
+ Register that is specific to -LP denoted by "_PCH_LP_" in component name.
+ - SubsystemName:
+ This field indicates the subsystem name of the component that the register belongs to
+ (e.g. PCIE, USB, SATA, GPIO, PMC etc.).
+ - RegisterSpace:
+ MEM - MMIO space register of subsystem.
+ IO - IO space register of subsystem.
+ PCR - Private configuration register of subsystem.
+ CFG - PCI configuration space register of subsystem.
+ - RegisterName:
+ Full register name.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _PCH_REGS_LPC_H_
+#define _PCH_REGS_LPC_H_
+
+//
+// PCI to LPC Bridge Registers
+//
+
+#define R_LPC_CFG_IOD 0x80
+#define R_LPC_CFG_IOE 0x82
+#define R_ESPI_CFG_CS1IORE 0xA0
+
+#define R_LPC_CFG_ULKMC 0x94
+#define B_LPC_CFG_ULKMC_A20PASSEN BIT5
+#define B_LPC_CFG_ULKMC_64WEN BIT3
+#define B_LPC_CFG_ULKMC_64REN BIT2
+#define B_LPC_CFG_ULKMC_60WEN BIT1
+#define B_LPC_CFG_ULKMC_60REN BIT0
+
+//
+// APM Registers
+//
+#define R_PCH_IO_APM_CNT 0xB2
+#define R_PCH_IO_APM_STS 0xB3
+#define R_LPC_CFG_BC 0xDC ///< Bios Control
+#define S_LPC_CFG_BC 1
+#define N_LPC_CFG_BC_LE 1
+
+//
+// Reset Generator I/O Port
+//
+#define R_PCH_IO_RST_CNT 0xCF9
+#define V_PCH_IO_RST_CNT_FULLRESET 0x0E
+#define V_PCH_IO_RST_CNT_HARDRESET 0x06
+//
+// eSPI PCR Registers
+//
+#define R_ESPI_PCR_CFG_VAL 0xC00C ///< ESPI Enabled Strap
+#define B_ESPI_PCR_CFG_VAL_ESPI_EN BIT0 ///< ESPI Enabled Strap bit position
+#define R_ESPI_PCR_SOFTSTRAPS 0xC210 ///< eSPI Sofstraps Register 0
+#define B_ESPI_PCR_SOFTSTRAPS_CS1_EN BIT12 ///< CS1# Enable
+
+#endif
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/PmcRegs.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/PmcRegs.h
new file mode 100644
index 0000000000..f7153b931c
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/PmcRegs.h
@@ -0,0 +1,134 @@
+/** @file
+ Register names for PCH PMC device
+
+ Conventions:
+
+ - Register definition format:
+ Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_RegisterName
+ - Prefix:
+ Definitions beginning with "R_" are registers
+ Definitions beginning with "B_" are bits within registers
+ Definitions beginning with "V_" are meaningful values within the bits
+ Definitions beginning with "S_" are register size
+ Definitions beginning with "N_" are the bit position
+ - [GenerationName]:
+ Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc.).
+ Register name without GenerationName applies to all generations.
+ - [ComponentName]:
+ This field indicates the component name that the register belongs to (e.g. PCH, SA etc.)
+ Register name without ComponentName applies to all components.
+ Register that is specific to -H denoted by "_PCH_H_" in component name.
+ Register that is specific to -LP denoted by "_PCH_LP_" in component name.
+ - SubsystemName:
+ This field indicates the subsystem name of the component that the register belongs to
+ (e.g. PCIE, USB, SATA, GPIO, PMC etc.).
+ - RegisterSpace:
+ MEM - MMIO space register of subsystem.
+ IO - IO space register of subsystem.
+ PCR - Private configuration register of subsystem.
+ CFG - PCI configuration space register of subsystem.
+ - RegisterName:
+ Full register name.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _PCH_REGS_PMC_H_
+#define _PCH_REGS_PMC_H_
+
+//
+// ACPI and legacy I/O register offsets from ACPIBASE
+//
+#define R_ACPI_IO_PM1_STS 0x00
+#define S_ACPI_IO_PM1_STS 2
+#define B_ACPI_IO_PM1_STS_PRBTNOR BIT11
+#define B_ACPI_IO_PM1_STS_PWRBTN BIT8
+#define N_ACPI_IO_PM1_STS_RTC 10
+#define N_ACPI_IO_PM1_STS_PWRBTN 8
+#define N_ACPI_IO_PM1_STS_TMROF 0
+
+#define R_ACPI_IO_PM1_EN 0x02
+#define S_ACPI_IO_PM1_EN 2
+#define B_ACPI_IO_PM1_EN_PWRBTN BIT8
+#define N_ACPI_IO_PM1_EN_RTC 10
+#define N_ACPI_IO_PM1_EN_PWRBTN 8
+#define N_ACPI_IO_PM1_EN_TMROF 0
+
+#define R_ACPI_IO_PM1_CNT 0x04 ///< Power Management 1 Control
+#define B_ACPI_IO_PM1_CNT_SLP_EN BIT13 ///< Sleep Enable
+#define B_ACPI_IO_PM1_CNT_SLP_TYP (BIT12 | BIT11 | BIT10) ///< Sleep Type
+#define V_ACPI_IO_PM1_CNT_S0 0
+#define V_ACPI_IO_PM1_CNT_S1 BIT10
+#define V_ACPI_IO_PM1_CNT_S3 (BIT12 | BIT10)
+#define V_ACPI_IO_PM1_CNT_S4 (BIT12 | BIT11)
+#define V_ACPI_IO_PM1_CNT_S5 (BIT12 | BIT11 | BIT10)
+#define B_ACPI_IO_PM1_CNT_SCI_EN BIT0 ///< SCI Enable
+
+#define R_ACPI_IO_PM1_TMR 0x08 ///< Power Management 1 Timer
+#define B_ACPI_IO_PM1_TMR_TMR_VAL 0xFFFFFF ///< Timer Value
+#define V_ACPI_IO_PM1_TMR_MAX_VAL 0x1000000 ///< The timer is 24 bit overflow
+
+#define R_ACPI_IO_SMI_EN 0x30 ///< SMI Control and Enable
+#define S_ACPI_IO_SMI_EN 4
+#define B_ACPI_IO_SMI_EN_LEGACY_USB2 BIT17
+#define B_ACPI_IO_SMI_EN_TCO BIT13
+#define B_ACPI_IO_SMI_EN_SWSMI_TMR BIT6
+#define B_ACPI_IO_SMI_EN_APMC BIT5
+#define B_ACPI_IO_SMI_EN_LEGACY_USB BIT3
+#define B_ACPI_IO_SMI_EN_EOS BIT1 ///< End of SMI
+#define B_ACPI_IO_SMI_EN_GBL_SMI BIT0
+#define N_ACPI_IO_SMI_EN_LEGACY_USB3 31
+#define N_ACPI_IO_SMI_EN_PERIODIC 14
+#define N_ACPI_IO_SMI_EN_TCO 13
+#define N_ACPI_IO_SMI_EN_MCSMI 11
+#define N_ACPI_IO_SMI_EN_SWSMI_TMR 6
+#define N_ACPI_IO_SMI_EN_APMC 5
+#define N_ACPI_IO_SMI_EN_ON_SLP_EN 4
+#define N_ACPI_IO_SMI_EN_LEGACY_USB 3
+
+#define R_ACPI_IO_SMI_STS 0x34 ///< SMI Status Register
+#define S_ACPI_IO_SMI_STS 4
+#define B_ACPI_IO_SMI_STS_GPIO_UNLOCK BIT27
+#define B_ACPI_IO_SMI_STS_TCO BIT13
+#define B_ACPI_IO_SMI_STS_APM BIT5
+#define N_ACPI_IO_SMI_STS_LEGACY_USB3 31
+#define N_ACPI_IO_SMI_STS_SPI 26
+#define N_ACPI_IO_SMI_STS_SMBUS 16
+#define N_ACPI_IO_SMI_STS_SERIRQ 15
+#define N_ACPI_IO_SMI_STS_PERIODIC 14
+#define N_ACPI_IO_SMI_STS_TCO 13
+#define N_ACPI_IO_SMI_STS_MCSMI 11
+#define N_ACPI_IO_SMI_STS_GPIO_SMI 10
+#define N_ACPI_IO_SMI_STS_GPE0 9
+#define N_ACPI_IO_SMI_STS_PM1_STS_REG 8
+#define N_ACPI_IO_SMI_STS_SWSMI_TMR 6
+#define N_ACPI_IO_SMI_STS_APM 5
+#define N_ACPI_IO_SMI_STS_ON_SLP_EN 4
+#define N_ACPI_IO_SMI_STS_LEGACY_USB 3
+
+#define R_ACPI_IO_GPE0_STS_127_96 0x6C ///< General Purpose Event 0 Status [127:96]
+#define S_ACPI_IO_GPE0_STS_127_96 4
+#define B_ACPI_IO_GPE0_STS_127_96_WADT BIT18
+#define N_ACPI_IO_GPE0_STS_127_96_PME_B0 13
+#define N_ACPI_IO_GPE0_STS_127_96_PME 11
+#define R_ACPI_IO_GPE0_EN_127_96 0x7C ///< General Purpose Event 0 Enable [127:96]
+#define S_ACPI_IO_GPE0_EN_127_96 4
+#define B_ACPI_IO_GPE0_EN_127_96_WADT BIT18
+#define N_ACPI_IO_GPE0_EN_127_96_PME_B0 13
+#define N_ACPI_IO_GPE0_EN_127_96_PME 11
+
+//
+// PWRM Registers
+//
+#define R_PMC_PWRM_GEN_PMCON_A 0x1020 ///< General PM Configuration A
+#define B_PMC_PWRM_GEN_PMCON_A_SWSMI_RTSL 0xC0
+#define V_PMC_PWRM_GEN_PMCON_A_SWSMI_RTSL_64MS 0xC0
+#define V_PMC_PWRM_GEN_PMCON_A_SWSMI_RTSL_32MS 0x80
+#define V_PMC_PWRM_GEN_PMCON_A_SWSMI_RTSL_16MS 0x40
+#define V_PMC_PWRM_GEN_PMCON_A_SWSMI_RTSL_1_5MS 0x00
+#define B_PMC_PWRM_GEN_PMCON_A_PER_SMI_SEL (BIT2|BIT1) ///< Period SMI Select
+#define V_PMC_PWRM_GEN_PMCON_A_PER_SMI_64S 0x0000
+#define V_PMC_PWRM_GEN_PMCON_A_PER_SMI_32S 0x0002
+#define V_PMC_PWRM_GEN_PMCON_A_PER_SMI_16S 0x0004
+#define V_PMC_PWRM_GEN_PMCON_A_PER_SMI_8S 0x0006
+#endif
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/RtcRegs.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/RtcRegs.h
new file mode 100644
index 0000000000..8424ef5897
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/RtcRegs.h
@@ -0,0 +1,44 @@
+/** @file
+ Register names for RTC device
+
+Conventions:
+
+ - Register definition format:
+ Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_RegisterName
+ - Prefix:
+ Definitions beginning with "R_" are registers
+ Definitions beginning with "B_" are bits within registers
+ Definitions beginning with "V_" are meaningful values within the bits
+ Definitions beginning with "S_" are register size
+ Definitions beginning with "N_" are the bit position
+ - [GenerationName]:
+ Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc.).
+ Register name without GenerationName applies to all generations.
+ - [ComponentName]:
+ This field indicates the component name that the register belongs to (e.g. PCH, SA etc.)
+ Register name without ComponentName applies to all components.
+ Register that is specific to -H denoted by "_PCH_H_" in component name.
+ Register that is specific to -LP denoted by "_PCH_LP_" in component name.
+ - SubsystemName:
+ This field indicates the subsystem name of the component that the register belongs to
+ (e.g. PCIE, USB, SATA, GPIO, PMC etc.).
+ - RegisterSpace:
+ MEM - MMIO space register of subsystem.
+ IO - IO space register of subsystem.
+ PCR - Private configuration register of subsystem.
+ CFG - PCI configuration space register of subsystem.
+ - RegisterName:
+ Full register name.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _REGS_RTC_H_
+#define _REGS_RTC_H_
+
+#define R_RTC_IO_INDEX_ALT 0x74
+#define R_RTC_IO_TARGET_ALT 0x75
+#define R_RTC_IO_EXT_INDEX_ALT 0x76
+#define R_RTC_IO_REGD 0x0D
+
+#endif
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/TcoRegs.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/TcoRegs.h
new file mode 100644
index 0000000000..c3afcd5079
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/TcoRegs.h
@@ -0,0 +1,71 @@
+/** @file
+ Register names for PCH TCO device
+
+ Conventions:
+
+ - Register definition format:
+ Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_RegisterName
+ - Prefix:
+ Definitions beginning with "R_" are registers
+ Definitions beginning with "B_" are bits within registers
+ Definitions beginning with "V_" are meaningful values within the bits
+ Definitions beginning with "S_" are register size
+ Definitions beginning with "N_" are the bit position
+ - [GenerationName]:
+ Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc.).
+ Register name without GenerationName applies to all generations.
+ - [ComponentName]:
+ This field indicates the component name that the register belongs to (e.g. PCH, SA etc.)
+ Register name without ComponentName applies to all components.
+ Register that is specific to -H denoted by "_PCH_H_" in component name.
+ Register that is specific to -LP denoted by "_PCH_LP_" in component name.
+ - SubsystemName:
+ This field indicates the subsystem name of the component that the register belongs to
+ (e.g. PCIE, USB, SATA, GPIO, PMC etc.).
+ - RegisterSpace:
+ MEM - MMIO space register of subsystem.
+ IO - IO space register of subsystem.
+ PCR - Private configuration register of subsystem.
+ CFG - PCI configuration space register of subsystem.
+ - RegisterName:
+ Full register name.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _TCO_REGS_H_
+#define _TCO_REGS_H_
+
+//
+// TCO register I/O map
+//
+#define R_TCO_IO_TCO1_STS 0x04
+#define S_TCO_IO_TCO1_STS 2
+#define B_TCO_IO_TCO1_STS_DMISERR BIT12
+#define B_TCO_IO_TCO1_STS_DMISMI BIT10
+#define B_TCO_IO_TCO1_STS_DMISCI BIT9
+#define B_TCO_IO_TCO1_STS_BIOSWR BIT8
+#define B_TCO_IO_TCO1_STS_NEWCENTURY BIT7
+#define B_TCO_IO_TCO1_STS_TIMEOUT BIT3
+#define B_TCO_IO_TCO1_STS_TCO_INT BIT2
+#define B_TCO_IO_TCO1_STS_SW_TCO_SMI BIT1
+#define N_TCO_IO_TCO1_STS_DMISMI 10
+#define N_TCO_IO_TCO1_STS_BIOSWR 8
+#define N_TCO_IO_TCO1_STS_NEWCENTURY 7
+#define N_TCO_IO_TCO1_STS_TIMEOUT 3
+#define N_TCO_IO_TCO1_STS_SW_TCO_SMI 1
+#define N_TCO_IO_TCO1_STS_NMI2SMI 0
+
+#define R_TCO_IO_TCO2_STS 0x06
+#define S_TCO_IO_TCO2_STS 2
+#define N_TCO_IO_TCO2_STS_INTRD_DET 0
+
+#define R_TCO_IO_TCO1_CNT 0x08
+#define S_TCO_IO_TCO1_CNT 2
+#define N_TCO_IO_TCO1_CNT_NMI2SMI_EN 9
+
+#define R_TCO_IO_TCO2_CNT 0x0A
+#define S_TCO_IO_TCO2_CNT 2
+#define N_TCO_IO_TCO2_CNT_INTRD_SEL 2
+
+#endif
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/SerialIoDevices.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/SerialIoDevices.h
new file mode 100644
index 0000000000..1829fb90ff
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/SerialIoDevices.h
@@ -0,0 +1,226 @@
+/** @file
+ Serial IO policy
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _SERIAL_IO_DEVICES_H_
+#define _SERIAL_IO_DEVICES_H_
+
+#include <Protocol/SerialIo.h>
+#include <PchLimits.h>
+
+#pragma pack (push,1)
+
+/**
+ Available working modes for SerialIo SPI Host Controller
+
+ 0: SerialIoSpiDisabled;
+ - Device is placed in D3
+ - Gpio configuration is skipped
+ - PSF:
+ !important! If given device is Function 0 and other higher functions on given device
+ are enabled, PSF disabling is skipped. PSF default will remain and device PCI CFG Space will still be visible.
+ This is needed to allow PCI enumerator access functions above 0 in a multifunction device.
+ <b>1: SerialIoSpiPci;</b>
+ - Gpio pin configuration in native mode for each assigned pin
+ - Device will be enabled in PSF
+ - Only BAR0 will be enabled
+ 2: SerialIoSpiHidden;
+ - Gpio pin configuration in native mode for each assigned pin
+ - Device disabled in the PSF
+ - Both BARs are enabled, BAR1 becomes devices Pci Config Space
+ - BAR0 assigned from the global PCH reserved memory range, reported as motherboard resource by SIRC
+ @note
+ If this controller is located at function 0 and it's mode is set to hidden it will not be visible in the PCI space.
+**/
+typedef enum {
+ SerialIoSpiDisabled,
+ SerialIoSpiPci,
+ SerialIoSpiHidden
+} SERIAL_IO_SPI_MODE;
+
+/**
+ Used to set Inactive/Idle polarity of Spi Chip Select
+**/
+typedef enum {
+ SerialIoSpiCsActiveLow = 0,
+ SerialIoSpiCsActiveHigh = 1
+} SERIAL_IO_CS_POLARITY;
+
+/**
+ SPI signals pin muxing settings. If signal can be enable only on a single pin
+ then this parameter is ignored by RC. Refer to GPIO_*_MUXING_SERIALIO_SPIx_* in GpioPins*.h
+ for supported settings on a given platform
+**/
+typedef struct {
+ UINT32 Cs[PCH_MAX_SERIALIO_SPI_CHIP_SELECTS]; ///< CS Pin mux configuration. Refer to GPIO_*_MUXING_SERIALIO_SPIx_CS_*
+ UINT32 Clk; ///< CLK Pin mux configuration. Refer to GPIO_*_MUXING_SERIALIO_SPIx_CLK_*
+ UINT32 Miso; ///< MISO Pin mux configuration. Refer to GPIO_*_MUXING_SERIALIO_SPIx_MISO_*
+ UINT32 Mosi; ///< MOSI Pin mux configuration. Refer to GPIO_*_MUXING_SERIALIO_SPIx_MOSI_*
+} SPI_PIN_MUX;
+
+/**
+ The SERIAL_IO_SPI_CONFIG provides the configurations to set the Serial IO SPI controller
+**/
+typedef struct {
+ UINT8 Mode; ///< <b>SerialIoSpiPci </b> see SERIAL_IO_SPI_MODE
+ UINT8 DefaultCsOutput; ///< <b>0 = CS0</b> CS1, CS2, CS3. Default CS used by the SPI HC
+ UINT8 CsPolarity[PCH_MAX_SERIALIO_SPI_CHIP_SELECTS]; ///< Selects SPI ChipSelect signal polarity, 0 = low <b>1 = High</b>
+ UINT8 CsEnable[PCH_MAX_SERIALIO_SPI_CHIP_SELECTS]; ///< <b>0 = Enable</b> 1 = Disable. Based on this setting GPIO for given SPIx CSx will be configured in Native mode
+ UINT8 CsMode; ///< <b>0 = HW Control</b> 1 = SW Control. Sets Chip Select Control mode Hardware or Software.
+ UINT8 CsState; ///< <b>0 = CS is set to low</b> 1 = CS is set to high
+ SPI_PIN_MUX PinMux; ///< SPI Pinmux configuration
+} SERIAL_IO_SPI_CONFIG;
+
+/**
+ Available working modes for SerialIo UART Host Controller
+
+ 0: SerialIoUartDisabled;
+ - Device is placed in D3
+ - Gpio configuration is skipped
+ - PSF:
+ !important! If given device is Function 0 and other higher functions on given device
+ are enabled, PSF disabling is skipped. PSF default will remain and device PCI CFG Space will still be visible.
+ This is needed to allow PCI enumerator access functions above 0 in a multifunction device.
+ <b>1: SerialIoUartPci;</b>
+ - Designated for Serial IO UART OS driver usage
+ - Gpio pin configuration in native mode for each assigned pin
+ - Device will be enabled in PSF
+ - Only BAR0 will be enabled
+ 2: SerialIoUartHidden;
+ - Designated for BIOS and/or DBG2 OS kernel debug
+ - Gpio pin configuration in native mode for each assigned pin
+ - Device disabled in the PSF
+ - Both BARs are enabled, BAR1 becomes devices Pci Config Space
+ - BAR0 assigned from the global PCH reserved memory range, reported as motherboard resource by SIRC
+ @note
+ If this controller is located at function 0 and it's mode is set to hidden it will not be visible in the PCI space.
+ 3: SerialIoUartCom;
+ - Designated for 16550/PNP0501 compatible COM device
+ - Gpio pin configuration in native mode for each assigned pin
+ - Device disabled in the PSF
+ - Both BARs are enabled, BAR1 becomes devices Pci Config Space
+ - BAR0 assigned from the global PCH reserved memory range, reported as motherboard resource by SIRC
+ 4: SerialIoUartSkipInit;
+ - Gpio configuration is skipped
+ - PSF configuration is skipped
+ - BAR assignemnt is skipped
+ - D-satate setting is skipped
+
+**/
+typedef enum {
+ SerialIoUartDisabled,
+ SerialIoUartPci,
+ SerialIoUartHidden,
+ SerialIoUartCom,
+ SerialIoUartSkipInit
+} SERIAL_IO_UART_MODE;
+
+/**
+ UART Settings
+**/
+typedef struct {
+ UINT32 BaudRate; ///< <b> 115200 </b> Max 6000000 MdePkg.dec PcdUartDefaultBaudRate
+ UINT8 Parity; ///< <b> 1 - No Parity</b> see EFI_PARITY_TYPE MdePkg.dec PcdUartDefaultParity
+ UINT8 DataBits; ///< <b>8</b> MdePkg.dec PcdUartDefaultDataBits
+ UINT8 StopBits; ///< <b>1 - One Stop Bit</b> see EFI_STOP_BITS_TYPE MdePkg.dec PcdUartDefaultStopBits
+ UINT8 AutoFlow; ///< <b>FALSE</b> IntelFrameworkModulePkg.dsc PcdIsaBusSerialUseHalfHandshake
+} SERIAL_IO_UART_ATTRIBUTES;
+
+/**
+ UART signals pin muxing settings. If signal can be enable only on a single pin
+ then this parameter is ignored by RC. Refer to GPIO_*_MUXING_SERIALIO_UARTx_* in GpioPins*.h
+ for supported settings on a given platform
+**/
+typedef struct {
+ UINT32 Rx; ///< RXD Pin mux configuration. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RXD_*
+ UINT32 Tx; ///< TXD Pin mux configuration. Refer to GPIO_*_MUXING_SERIALIO_UARTx_TXD_*
+ UINT32 Rts; ///< RTS Pin mux configuration. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RTS_*
+ UINT32 Cts; ///< CTS Pin mux configuration. Refer to GPIO_*_MUXING_SERIALIO_UARTx_CTS_*
+} UART_PIN_MUX;
+
+/**
+ Serial IO UART Controller Configuration
+**/
+typedef struct {
+ SERIAL_IO_UART_ATTRIBUTES Attributes; ///< see SERIAL_IO_UART_ATTRIBUTES
+ UART_PIN_MUX PinMux; ///< UART pin mux configuration
+ UINT8 Mode; ///< <b> SerialIoUartPci </b> see SERIAL_IO_UART_MODE
+ UINT8 DBG2; ///< <b> FALSE </b> If TRUE adds UART to DBG2 table and overrides UartPg to SerialIoUartPgDisabled
+ UINT8 PowerGating; ///< <b> SerialIoUartPgAuto </b> Applies to Hidden/COM/SkipInit see SERIAL_IO_UART_PG
+ UINT8 DmaEnable; ///< <b> TRUE </b> Applies to SerialIoUartPci only. Informs OS driver to use DMA, if false it will run in PIO mode
+} SERIAL_IO_UART_CONFIG;
+
+typedef enum {
+ SerialIoUartPgDisabled, ///< No _PS0/_PS3 support, device left in D0, after initialization
+/**
+ In mode: SerialIoUartCom;
+ _PS0/_PS3 that supports getting device out of reset
+ In mode: SerialIoUartPci
+ Keeps UART in D0 and assigns Fixed MMIO for SEC/PEI usage only
+**/
+ SerialIoUartPgEnabled,
+ SerialIoUartPgAuto ///< _PS0 and _PS3, detection through ACPI if device was initialized prior to first PG. If it was used (DBG2) PG is disabled,
+} SERIAL_IO_UART_PG;
+
+/**
+ Available working modes for SerialIo I2C Host Controller
+
+ 0: SerialIoI2cDisabled;
+ - Device is placed in D3
+ - Gpio configuration is skipped
+ - PSF:
+ !important! If given device is Function 0 and other higher functions on given device
+ are enabled, PSF disabling is skipped. PSF default will remain and device PCI CFG Space will still be visible.
+ This is needed to allow PCI enumerator access functions above 0 in a multifunction device.
+ <b>1: SerialIoI2cPci;</b>
+ - Gpio pin configuration in native mode for each assigned pin
+ - Device will be enabled in PSF
+ - Only BAR0 will be enabled
+ 2: SerialIoI2cHidden;
+ - Gpio pin configuration in native mode for each assigned pin
+ - Device disabled in the PSF
+ - Both BARs are enabled, BAR1 becomes devices Pci Config Space
+ - BAR0 assigned from the global PCH reserved memory range, reported as motherboard resource by SIRC
+ @note
+ If this controller is located at function 0 and it's mode is set to hidden it will not be visible in the PCI space.
+**/
+typedef enum {
+ SerialIoI2cDisabled,
+ SerialIoI2cPci,
+ SerialIoI2cHidden
+} SERIAL_IO_I2C_MODE;
+
+/**
+ I2C signals pin muxing settings. If signal can be enable only on a single pin
+ then this parameter is ignored by RC. Refer to GPIO_*_MUXING_SERIALIO_I2Cx_* in GpioPins*.h
+ for supported settings on a given platform
+**/
+typedef struct {
+ UINT32 Sda; ///< SDA Pin mux configuration. Refer to GPIO_*_MUXING_SERIALIO_I2Cx_SDA_*
+ UINT32 Scl; ///< SCL Pin mux configuration. Refer to GPIO_*_MUXING_SERIALIO_I2Cx_SCL_*
+} I2C_PIN_MUX;
+
+/**
+ Serial IO I2C Controller Configuration
+**/
+typedef struct {
+ UINT8 Mode; /// <b>SerialIoI2cPci <b> see SERIAL_IO_I2C_MODE
+ /**
+ I2C Pads Internal Termination.
+ For more information please see Platform Design Guide.
+ Supported values (check GPIO_ELECTRICAL_CONFIG for reference):
+ <b>GpioTermNone: No termination</b>,
+ GpioTermWpu1K: 1kOhm weak pull-up,
+ GpioTermWpu5K: 5kOhm weak pull-up,
+ GpioTermWpu20K: 20kOhm weak pull-up
+ **/
+ UINT8 PadTermination;
+ UINT8 Reserved[2];
+ I2C_PIN_MUX PinMux; ///< I2C pin mux configuration
+} SERIAL_IO_I2C_CONFIG;
+
+#pragma pack (pop)
+
+#endif // _SERIAL_IO_DEVICES_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/SiConfigHob.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/SiConfigHob.h
new file mode 100644
index 0000000000..089141d143
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/SiConfigHob.h
@@ -0,0 +1,17 @@
+/** @file
+ Silicon Config HOB is used for gathering platform
+ related Intel silicon information and config setting.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _SI_CONFIG_HOB_H_
+#define _SI_CONFIG_HOB_H_
+
+#include <SiPolicyStruct.h>
+
+extern EFI_GUID gSiConfigHobGuid;
+
+// Rename SI_CONFIG_HOB into SI_CONFIG_HOB_DATA for it does not follow HOB structure.
+typedef CONST SI_CONFIG SI_CONFIG_HOB_DATA;
+#endif
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/SiPolicyStruct.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/SiPolicyStruct.h
new file mode 100644
index 0000000000..4dacba242e
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/SiPolicyStruct.h
@@ -0,0 +1,64 @@
+/** @file
+ Intel reference code configuration policies.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _SI_POLICY_STRUCT_H_
+#define _SI_POLICY_STRUCT_H_
+
+#include <ConfigBlock.h>
+#include <ConfigBlock/SiPreMemConfig.h>
+#include <ConfigBlock/SiConfig.h>
+
+/**
+ Silicon Policy revision number
+ Any change to this structure will result in an update in the revision number
+
+ This member specifies the revision of the Silicon Policy. This field is used to indicate change
+ to the policy structure.
+
+ <b>Revision 1</b>:
+ - Initial version.
+**/
+#define SI_POLICY_REVISION 1
+
+/**
+ Silicon pre-memory Policy revision number
+ Any change to this structure will result in an update in the revision number
+
+ <b>Revision 1</b>:
+ - Initial version.
+**/
+#define SI_PREMEM_POLICY_REVISION 1
+
+
+/**
+ SI Policy PPI in Pre-Mem\n
+ All SI config block change history will be listed here\n\n
+
+ - <b>Revision 1</b>:
+ - Initial version.\n
+**/
+struct _SI_PREMEM_POLICY_STRUCT {
+ CONFIG_BLOCK_TABLE_HEADER TableHeader; ///< Config Block Table Header
+/*
+ Individual Config Block Structures are added here in memory as part of AddConfigBlock()
+*/
+};
+
+/**
+ SI Policy PPI\n
+ All SI config block change history will be listed here\n\n
+
+ - <b>Revision 1</b>:
+ - Initial version.\n
+**/
+struct _SI_POLICY_STRUCT {
+ CONFIG_BLOCK_TABLE_HEADER TableHeader; ///< Config Block Table Header
+/*
+ Individual Config Block Structures are added here in memory as part of AddConfigBlock()
+*/
+};
+
+#endif
--
2.36.1.windows.1
-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#108725): https://edk2.groups.io/g/devel/message/108725
Mute This Topic: https://groups.io/mt/101373951/7686176
Group Owner: devel+owner@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [rebecca@openfw.io]
-=-=-=-=-=-=-=-=-=-=-=-
^ permalink raw reply related [flat|nested] 41+ messages in thread
* Re: [edk2-devel] [PATCH v2 08/10] AlderlakeSiliconPkg/Fru: Add AdlCpu Fru
2023-09-15 5:43 ` Chaganty, Rangasai V
@ 2023-09-15 13:29 ` Chuang, Rosen
0 siblings, 0 replies; 41+ messages in thread
From: Chuang, Rosen @ 2023-09-15 13:29 UTC (permalink / raw)
To: Chaganty, Rangasai V, Kasbekar, Saloni, devel@edk2.groups.io
Cc: Desimone, Nathaniel L
Reviewed-by: Rosen Chuang <rosen.chuang@intel.com>
-----Original Message-----
From: Chaganty, Rangasai V <rangasai.v.chaganty@intel.com>
Sent: Friday, September 15, 2023 1:43 PM
To: Kasbekar, Saloni <saloni.kasbekar@intel.com>; devel@edk2.groups.io
Cc: Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>; Chuang, Rosen <rosen.chuang@intel.com>
Subject: RE: [PATCH v2 08/10] AlderlakeSiliconPkg/Fru: Add AdlCpu Fru
Reviewed-by: Sai Chaganty <rangasai.v.chaganty@intel.com>
-----Original Message-----
From: Kasbekar, Saloni <saloni.kasbekar@intel.com>
Sent: Thursday, September 14, 2023 9:46 PM
To: devel@edk2.groups.io
Cc: Kasbekar, Saloni <saloni.kasbekar@intel.com>; Chaganty, Rangasai V <rangasai.v.chaganty@intel.com>; Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>; Chuang, Rosen <rosen.chuang@intel.com>
Subject: [PATCH v2 08/10] AlderlakeSiliconPkg/Fru: Add AdlCpu Fru
Adds the following modules:
- AdlCpu/CpuPcieRp
- AdlCpu/Include
- AdlCpu/IncludePrivate
- AdlCpu/LibraryPrivate
- AdlCpu/PeiReportCpuHob
- AdlCpu DSCs
Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Rosen Chuang <rosen.chuang@intel.com>
Signed-off-by: Saloni Kasbekar <saloni.kasbekar@intel.com>
---
.../Fru/AdlCpu/CommonLib.dsc | 9 +
.../CpuPcieInfoFruLib.c | 87 ++++++++++
.../PeiDxeSmmCpuPcieInfoFruLib.inf | 39 +++++
.../AlderlakeSiliconPkg/Fru/AdlCpu/DxeLib.dsc | 8 +
.../Fru/AdlCpu/Include/CpuGenInfo.h | 42 +++++
.../Include/Library/CpuPcieInfoFruLib.h | 45 +++++
.../Include/Register/SaRegsHostBridge.h | 64 +++++++
.../AdlCpu/IncludePrivate/CpuGenInfoFruLib.h | 44 +++++ .../AdlCpu/IncludePrivate/Register/IgdRegs.h | 34 ++++
.../BaseCpuInfoFruLib/BaseCpuInfoFruLib.c | 164 ++++++++++++++++++
.../BaseCpuInfoFruLib/BaseCpuInfoFruLib.inf | 29 ++++
.../PeiReportCpuHobLib/PeiReportCpuHobLib.c | 22 +++
.../PeiReportCpuHobLib/PeiReportCpuHobLib.inf | 26 +++
13 files changed, 613 insertions(+)
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/CommonLib.dsc
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/CpuPcieRp/Library/PeiDxeSmmCpuPcieInfoFruLib/CpuPcieInfoFruLib.c
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/CpuPcieRp/Library/PeiDxeSmmCpuPcieInfoFruLib/PeiDxeSmmCpuPcieInfoFruLib.inf
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/DxeLib.dsc
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/Include/CpuGenInfo.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/Include/Library/CpuPcieInfoFruLib.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/Include/Register/SaRegsHostBridge.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/IncludePrivate/CpuGenInfoFruLib.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/IncludePrivate/Register/IgdRegs.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/LibraryPrivate/BaseCpuInfoFruLib/BaseCpuInfoFruLib.c
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/LibraryPrivate/BaseCpuInfoFruLib/BaseCpuInfoFruLib.inf
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/PeiReportCpuHob/Library/PeiReportCpuHobLib/PeiReportCpuHobLib.c
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/PeiReportCpuHob/Library/PeiReportCpuHobLib/PeiReportCpuHobLib.inf
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/CommonLib.dsc b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/CommonLib.dsc
new file mode 100644
index 0000000000..35a3cce916
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/CommonLib.dsc
@@ -0,0 +1,9 @@
+## @file
+# Component description file for the AlderLake CPU Common FRU libraries.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+CpuPcieInfoFruLib|$(PLATFORM_SI_PACKAGE)/Fru/AdlCpu/CpuPcieRp/Library/P
+CpuPcieInfoFruLib|eiDxeSmmCpuPcieInfoFruLib/PeiDxeSmmCpuPcieInfoFruLib.
+CpuPcieInfoFruLib|inf
+CpuInfoFruLib|$(PLATFORM_SI_PACKAGE)/Fru/AdlCpu/LibraryPrivate/BaseCpuI
+CpuInfoFruLib|nfoFruLib/BaseCpuInfoFruLib.inf
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/CpuPcieRp/Library/PeiDxeSmmCpuPcieInfoFruLib/CpuPcieInfoFruLib.c b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/CpuPcieRp/Library/PeiDxeSmmCpuPcieInfoFruLib/CpuPcieInfoFruLib.c
new file mode 100644
index 0000000000..277b73fe67
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/CpuPcieRp/Library/Pei
+++ DxeSmmCpuPcieInfoFruLib/CpuPcieInfoFruLib.c
@@ -0,0 +1,87 @@
+/** @file
+ CPU PCIe information library.
+
+ All function in this library is available for PEI, DXE, and SMM, But
+ do not support UEFI RUNTIME environment call.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/ #include
+<Uefi/UefiBaseType.h> #include <Library/CpuPlatformLib.h> #include
+<Library/DebugLib.h> #include <Library/BaseLib.h> #include
+<Library/PciSegmentLib.h> #include <Register/SaRegsHostBridge.h>
+#include <Library/CpuPcieInfoFruLib.h> #include <CpuPcieInfo.h>
+
+/**
+ Get Maximum CPU Pcie Root Port Number
+
+ @retval Maximum CPU Pcie Root Port Number **/
+UINT8
+GetMaxCpuPciePortNum (
+ VOID
+ )
+{
+ switch (GetCpuSku ()) {
+ case EnumCpuUlt:
+ return CPU_PCIE_ULT_MAX_ROOT_PORT;
+ case EnumCpuUlx:
+ return CPU_PCIE_ULX_MAX_ROOT_PORT;
+ default:
+ return CPU_PCIE_ULT_MAX_ROOT_PORT;
+ }
+}
+
+/**
+ Get CPU Pcie Root Port Device and Function Number by Root Port
+physical Number
+
+ @param[in] RpNumber Root port physical number. (0-based)
+ @param[out] RpDev Return corresponding root port device number.
+ @param[out] RpFun Return corresponding root port function number.
+
+ @retval EFI_SUCCESS Root port device and function is retrieved
+ @retval EFI_INVALID_PARAMETER RpNumber is invalid
+**/
+EFI_STATUS
+EFIAPI
+GetCpuPcieRpDevFun (
+ IN UINTN RpNumber,
+ OUT UINTN *RpDev,
+ OUT UINTN *RpFun
+ )
+{
+ if (RpNumber > GetMaxCpuPciePortNum ()) {
+ DEBUG ((DEBUG_ERROR, "GetCpuPcieRpDevFun invalid RpNumber %x", RpNumber));
+ ASSERT (FALSE);
+ return EFI_INVALID_PARAMETER;
+ }
+
+ switch (RpNumber) {
+ case 0:
+ *RpDev = 6;
+ *RpFun = 0;
+ break;
+ case 1:
+ *RpDev = 1;
+ *RpFun = 0;
+ break;
+ case 2:
+ if (GetCpuSku () == EnumCpuTrad) {
+ *RpDev = 1;
+ *RpFun = 1;
+ } else {
+ *RpDev = 6;
+ *RpFun = 2;
+ }
+ break;
+ default:
+ *RpDev = 6;
+ *RpFun = 0;
+ break;
+ }
+ return EFI_SUCCESS;
+}
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/CpuPcieRp/Library/PeiDxeSmmCpuPcieInfoFruLib/PeiDxeSmmCpuPcieInfoFruLib.inf b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/CpuPcieRp/Library/PeiDxeSmmCpuPcieInfoFruLib/PeiDxeSmmCpuPcieInfoFruLib.inf
new file mode 100644
index 0000000000..f850f1a5f1
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/CpuPcieRp/Library/Pei
+++ DxeSmmCpuPcieInfoFruLib/PeiDxeSmmCpuPcieInfoFruLib.inf
@@ -0,0 +1,39 @@
+## @file
+# CPU PCIe information library for TigerLake PCH.
+#
+# All function in this library is available for PEI, DXE, and SMM, #
+But do not support UEFI RUNTIME environment call.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+
+[Defines]
+INF_VERSION = 0x00010017
+BASE_NAME = PeiDxeSmmCpuPcieInfoFruLib
+FILE_GUID = 59CA5352-ED46-4449-BF1C-0D0074C4D5B1
+VERSION_STRING = 1.0
+MODULE_TYPE = BASE
+LIBRARY_CLASS = CpuPcieInfoFruLib
+
+
+[LibraryClasses]
+IoLib
+BaseLib
+DebugLib
+PrintLib
+PciSegmentLib
+PchPcrLib
+PmcPrivateLib
+PcdLib
+ConfigBlockLib
+CpuPlatformLib
+
+[Packages]
+MdePkg/MdePkg.dec
+AlderlakeSiliconPkg/SiPkg.dec
+
+[Sources]
+CpuPcieInfoFruLib.c
+
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/DxeLib.dsc b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/DxeLib.dsc
new file mode 100644
index 0000000000..644230484e
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/DxeLib.dsc
@@ -0,0 +1,8 @@
+# @file
+# Component description file for the AlderLake CPU DXE FRU libraries.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+DxeGraphicsPolicyLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Graphics/LibraryPri
+DxeGraphicsPolicyLib|vate/DxeGraphicsPolicyLib/DxeGraphicsPolicyLib.inf
+DxeIgdOpRegionInitLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Graphics/LibraryPr
+DxeIgdOpRegionInitLib|ivate/DxeIgdOpRegionInitLib/DxeIgdOpRegionInitLib
+DxeIgdOpRegionInitLib|.inf
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/Include/CpuGenInfo.h b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/Include/CpuGenInfo.h
new file mode 100644
index 0000000000..482316829d
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/Include/CpuGenInfo.h
@@ -0,0 +1,42 @@
+/** @file
+ Header file for Cpu Information
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/ #ifndef
+_CPU_GEN_INFO_H_ #define _CPU_GEN_INFO_H_
+
+#include <CpuRegs.h>
+
+//
+// Processor Definitions
+//
+#define CPUID_FULL_FAMILY_MODEL_ALDERLAKE_MOBILE 0x000906A0
+
+///
+/// Enums for CPU Stepping IDs
+///
+typedef enum {
+
+ ///
+ /// AlderLake Mobile Steppings(ULT)
+ ///
+ EnumAdlJ0 = 0,
+ EnumAdlK0 = 2,
+ EnumAdlL0 = 3,
+
+ ///
+ /// AlderLake Mobile Steppings(ULX)
+ ///
+ EnumAdlQ0 = 1,
+ EnumAdlR0 = 4,
+ EnumAdlS0 = 5,
+
+
+ ///
+ /// Max Stepping
+ ///
+ EnumCpuSteppingMax = CPUID_FULL_STEPPING } CPU_STEPPING; #endif
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/Include/Library/CpuPcieInfoFruLib.h b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/Include/Library/CpuPcieInfoFruLib.h
new file mode 100644
index 0000000000..9dafa98631
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/Include/Library/CpuPc
+++ ieInfoFruLib.h
@@ -0,0 +1,45 @@
+/** @file
+ Header file for CpuPcieInfoFruLib.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/ #ifndef
+_CPU_PCIE_INFO_FRU_LIB_H_ #define _CPU_PCIE_INFO_FRU_LIB_H_
+
+#include <CpuPcieInfo.h>
+
+#define CPU_PCIE_MAX_ROOT_PORTS 4
+#define CPU_PCIE_MAX_CONTROLLERS 3
+
+#define CPU_PCIE_ULT_MAX_ROOT_PORT 3
+#define CPU_PCIE_ULX_MAX_ROOT_PORT 1
+
+/**
+ Get CPU Maximum Pcie Root Port Number
+
+ @retval PcieMaxRootPort Pch Maximum Pcie Root Port Number
+**/
+UINT8
+GetMaxCpuPciePortNum (
+ VOID
+ );
+
+/**
+ Get CPU Pcie Root Port Device and Function Number by Root Port
+physical Number
+
+ @param[in] RpNumber Root port physical number. (0-based)
+ @param[out] RpDev Return corresponding root port device number.
+ @param[out] RpFun Return corresponding root port function number.
+
+ @retval EFI_SUCCESS Root port device and function is retrieved
+ @retval EFI_INVALID_PARAMETER RpNumber is invalid
+**/
+EFI_STATUS
+EFIAPI
+GetCpuPcieRpDevFun (
+ IN UINTN RpNumber,
+ OUT UINTN *RpDev,
+ OUT UINTN *RpFun
+ );
+#endif // _CPU_PCIE_INFO_FRU_LIB_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/Include/Register/SaRegsHostBridge.h b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/Include/Register/SaRegsHostBridge.h
new file mode 100644
index 0000000000..be4bba3283
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/Include/Register/SaRe
+++ gsHostBridge.h
@@ -0,0 +1,64 @@
+/** @file
+ Register names for Host Bridge block
+ <b>Conventions</b>:
+ - Prefixes:
+ - Definitions beginning with "R_" are registers
+ - Definitions beginning with "B_" are bits within registers
+ - Definitions beginning with "V_" are meaningful values of bits within the registers
+ - Definitions beginning with "S_" are register sizes
+ - Definitions beginning with "N_" are the bit position
+ - In general, SA registers are denoted by "_SA_" in register names
+ - Registers / bits that are different between SA generations are denoted by
+ "_SA_[generation_name]_" in register/bit names. e.g., "_SA_HSW_"
+ - Registers / bits that are different between SKUs are denoted by "_[SKU_name]"
+ at the end of the register/bit names
+ - Registers / bits of new devices introduced in a SA generation will be just named
+ as "_SA_" without [generation_name] inserted.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/ #ifndef
+_SA_REGS_HOST_BRIDGE_H_ #define _SA_REGS_HOST_BRIDGE_H_
+
+#define SA_SEG_NUM 0x00
+//
+// DEVICE 0 (Memory Controller Hub)
+//
+#define SA_MC_BUS 0x00
+#define SA_MC_DEV 0x00
+#define SA_MC_FUN 0x00
+#define R_SA_MC_DEVICE_ID 0x02
+
+//
+// AlderLake CPU Mobile SA Device IDs B0:D0:F0 //
+#define V_SA_DEVICE_ID_MB_ULT_1 0x4641 ///< AlderLake P (6+8+GT) SA DID
+#define V_SA_DEVICE_ID_MB_ULT_2 0x4649 ///< AlderLake P (6+4(f)+GT) SA DID
+#define V_SA_DEVICE_ID_MB_ULT_3 0x4621 ///< AlderLake P (4(f)+8+GT) SA DID
+#define V_SA_DEVICE_ID_MB_ULT_4 0x4609 ///< AlderLake P (2(f)+4(f)+GT) SA DID
+#define V_SA_DEVICE_ID_MB_ULT_5 0x4601 ///< AlderLake P (2+8+GT) SA DID
+#define V_SA_DEVICE_ID_MB_ULT_6 0x4661 ///< AlderLake P (6+8+2) SA DID
+#define V_SA_DEVICE_ID_MB_ULT_7 0x4629 ///< AlderLake P (4+4+1) SA DID
+#define V_SA_DEVICE_ID_MB_ULT_8 0x4619 ///< AlderLake P (1+4+GT) SA DID
+#define V_SA_DEVICE_ID_MB_ULT_9 0x4659 ///< AlderLake P (1+8+GT) SA DID
+#define V_SA_DEVICE_ID_MB_ULT_10 0x4645 ///< AlderLake P (6+6+GT) SA DID
+///
+/// Description:
+/// The SMRAMC register controls how accesses to Compatible SMRAM spaces are treated. The Open, Close and Lock bits function only when G_SMRAME bit is set to 1. Also, the Open bit must be reset before the Lock bit is set.
+///
+#define R_SA_SMRAMC (0x88)
+
+///
+/// Description:
+/// This register contains the Top of low memory address.
+///
+#define R_SA_TOLUD (0xbc)
+///
+/// Description of TOLUD (20:31)
+/// This register contains bits 31 to 20 of an address one byte above the maximum DRAM memory below 4G that is usable by the operating system. Address bits 31 down to 20 programmed to 01h implies a minimum memory size of 1MB. Configuration software must set this value to the smaller of the following 2 choices: maximum amount memory in the system minus ME stolen memory plus one byte or the minimum address allocated for PCI memory. Address bits 19:0 are assumed to be 0_0000h for the purposes of address comparison. The Host interface positively decodes an address towards DRAM if the incoming address is less than the value programmed in this register.
+/// The Top of Low Usable DRAM is the lowest address above both Graphics Stolen memory and Tseg. BIOS determines the base of Graphics Stolen Memory by subtracting the Graphics Stolen Memory Size from TOLUD and further decrements by Tseg size to determine base of Tseg. All the Bits in this register are locked in LT mode.
+/// This register must be 1MB aligned when reclaim is enabled.
+///
+#define B_SA_TOLUD_TOLUD_MASK (0xfff00000)
+#endif
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/IncludePrivate/CpuGenInfoFruLib.h b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/IncludePrivate/CpuGenInfoFruLib.h
new file mode 100644
index 0000000000..5ad7bf4982
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/IncludePrivate/CpuGen
+++ InfoFruLib.h
@@ -0,0 +1,44 @@
+ /** @file
+ This file contains Cpu Information for specific generation.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/ #ifndef
+_CPU_GEN_INFO_FRU_LIB_H_ #define _CPU_GEN_INFO_FRU_LIB_H_ #include
+<CpuRegs.h> #include <CpuGenInfo.h> #include <Register/CommonMsr.h>
+
+///
+/// Used to identify the CPU used for programming with the VR override
+table /// typedef enum {
+ EnumUnknownCpuId = 0,
+ EnumMinCpuId = 1,
+
+ ///
+ /// ADL P
+ ///
+ EnumAdlP15Watt282fCpuId = 0x30,
+ EnumAdlP28Watt482fCpuId = 0x31,
+ EnumAdlP28Watt682fCpuId = 0x32,
+ EnumAdlP45Watt682fCpuId = 0x35,
+ EnumAdlP15Watt142fCpuId = 0x36,
+ EnumAdlP15Watt242fCpuId = 0x37,
+ EnumAdlP45Watt482fCpuId = 0x38,
+ EnumAdlP45Watt442fCpuId = 0x39,
+ EnumAdlP28Watt442fCpuId = 0x3A,
+ EnumAdlP28Watt282fCpuId = 0x3B,
+ EnumAdlP28Watt242fCpuId = 0x3C,
+ EnumAdlP28Watt142fCpuId = 0x3D,
+ EnumAdlP45Watt242fCpuId = 0x3E,
+ EnumAdlP28Watt182fCpuId = 0x3F,
+ EnumAdlP28Watt662fCpuId = 0x40,
+ EnumAdlP28Watt642fCpuId = 0x41,
+ EnumAdlP45Watt642fCpuId = 0x42,
+ EnumAdlPMaxCpuId = EnumAdlP45Watt642fCpuId,
+
+} CPU_IDENTIFIER;
+
+#endif // _CPU_GEN_INFO_FRU_LIB_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/IncludePrivate/Register/IgdRegs.h b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/IncludePrivate/Register/IgdRegs.h
new file mode 100644
index 0000000000..289b293b32
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/IncludePrivate/Regist
+++ er/IgdRegs.h
@@ -0,0 +1,34 @@
+/** @file
+ Register names for IGD block
+ <b>Conventions</b>:
+ - Prefixes:
+ - Definitions beginning with "R_" are registers
+ - Definitions beginning with "B_" are bits within registers
+ - Definitions beginning with "V_" are meaningful values of bits within the registers
+ - Definitions beginning with "S_" are register sizes
+ - Definitions beginning with "N_" are the bit position
+ - In general, SA registers are denoted by "_SA_" in register names
+ - Registers / bits that are different between SA generations are denoted by
+ "_SA_[generation_name]_" in register/bit names. e.g., "_SA_HSW_"
+ - Registers / bits that are different between SKUs are denoted by "_[SKU_name]"
+ at the end of the register/bit names
+ - Registers / bits of new devices introduced in a SA generation will be just named
+ as "_SA_" without [generation_name] inserted.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/ #ifndef
+_IGD_REGS_H_ #define _IGD_REGS_H_
+
+///
+/// Device 2 Register Equates
+///
+//
+// The following equates must be reviewed and revised when the specification is ready.
+//
+#define IGD_BUS_NUM 0x00
+#define IGD_DEV_NUM 0x02
+#define IGD_FUN_NUM 0x00
+
+#endif
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/LibraryPrivate/BaseCpuInfoFruLib/BaseCpuInfoFruLib.c b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/LibraryPrivate/BaseCpuInfoFruLib/BaseCpuInfoFruLib.c
new file mode 100644
index 0000000000..d93048eb6e
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/LibraryPrivate/BaseCp
+++ uInfoFruLib/BaseCpuInfoFruLib.c
@@ -0,0 +1,164 @@
+/** @file
+ This file contains the Cpu Information for specific generation.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/ #include
+<CpuGenInfoFruLib.h> #include <Library/BaseLib.h> #include
+<Library/DebugLib.h> #include <Register/Cpuid.h> #include
+<Library/CpuPlatformLib.h> #include <Library/CpuInfoFruLib.h> #include
+<Register/ArchitecturalMsr.h> #include <Library/MemoryAllocationLib.h>
+#include <Register/CommonMsr.h> #include <IndustryStandard/SmBios.h>
+#include <Library/PcdLib.h> #include <Library/PchInfoLib.h> #include
+<IndustryStandard/Pci22.h> #include <Register/IgdRegs.h>
+
+
+STATIC CONST CHAR8 mAdlCpuFamilyString[] = "AlderLake"; typedef struct
+{
+ UINT32 CPUID;
+ UINT8 CpuSku;
+ CHAR8 *String;
+} CPU_REV;
+
+typedef struct {
+ CPU_IDENTIFIER CpuIdentifier;
+ UINT8 SupportedCores;
+ UINT8 SupportedAtomCores;
+} CPU_CORE_COUNT;
+
+GLOBAL_REMOVE_IF_UNREFERENCED CONST CPU_REV mProcessorRevisionTable[] = {
+ {CPUID_FULL_FAMILY_MODEL_ALDERLAKE_MOBILE + EnumAdlJ0, EnumCpuUlt, "J0"},
+ {CPUID_FULL_FAMILY_MODEL_ALDERLAKE_MOBILE + EnumAdlK0, EnumCpuUlt, "K0"},
+ {CPUID_FULL_FAMILY_MODEL_ALDERLAKE_MOBILE + EnumAdlL0, EnumCpuUlt, "L0"},
+ {CPUID_FULL_FAMILY_MODEL_ALDERLAKE_MOBILE + EnumAdlQ0, EnumCpuUlt, "Q0"},
+ {CPUID_FULL_FAMILY_MODEL_ALDERLAKE_MOBILE + EnumAdlR0, EnumCpuUlt, "R0"},
+ {CPUID_FULL_FAMILY_MODEL_ALDERLAKE_MOBILE + EnumAdlQ0, EnumCpuUlx, "Q0"},
+ {CPUID_FULL_FAMILY_MODEL_ALDERLAKE_MOBILE + EnumAdlR0, EnumCpuUlx, "R0"},
+ {CPUID_FULL_FAMILY_MODEL_ALDERLAKE_MOBILE + EnumAdlS0, EnumCpuUlx, "S0"}
+};
+
+///
+/// PowerLimits Override table for all SKUs. Non-cTDP parts would have '0' data for TDP level information.
+///
+GLOBAL_REMOVE_IF_UNREFERENCED PPM_OVERRIDE_TABLE
+mPowerLimitsOverrideTable[] = { ///
+/// CpuIdentifier TDP MSR PL1 MSR PL2 TdpUp TdpUp TdpNominal TdpNominal TdpDown TdpDown MSR MSR Disablefvm
+/// PL1 PL2 PL1 PL2 PL1 PL2 PL1 PL2 PL4 PL4
+ {EnumAdlP15Watt282fCpuId, 1500, 1500, 5500, 0, 5500, 0, 5500, 0, 5500, 12300, 0}, /// 15W 282 ADL-P
+ {EnumAdlP15Watt142fCpuId, 1500, 1500, 5500, 0, 5500, 0, 5500, 0, 5500, 12300, 0}, /// 15W 142 ADL-P
+ {EnumAdlP15Watt242fCpuId, 1500, 1500, 5500, 0, 5500, 0, 5500, 0, 5500, 12300, 0}, /// 15W 242 ADL-P
+ {EnumAdlP28Watt282fCpuId, 2800, 2800, 6400, 0, 6400, 0, 6400, 0, 6400, 9000, 0}, /// 28W 282 ADL-P
+ {EnumAdlP28Watt482fCpuId, 2800, 2800, 6400, 0, 6400, 0, 6400, 0, 6400, 9000, 0}, /// 28W 482 ADL-P
+ {EnumAdlP28Watt682fCpuId, 2800, 2800, 6400, 0, 6400, 0, 6400, 0, 6400, 14000, 0}, /// 26W 682 ADL-P
+ {EnumAdlP28Watt142fCpuId, 2800, 2800, 6400, 0, 6400, 0, 6400, 0, 6400, 9000, 0}, /// 28W 142 ADL-P
+ {EnumAdlP28Watt242fCpuId, 2800, 2800, 6400, 0, 6400, 0, 6400, 0, 6400, 9000, 0}, /// 28W 242 ADL-P
+ {EnumAdlP28Watt442fCpuId, 2800, 2800, 6400, 0, 6400, 0, 6400, 0, 6400, 9000, 0}, /// 28W 442 ADL-P
+ {EnumAdlP28Watt182fCpuId, 2800, 2800, 6400, 0, 6400, 0, 6400, 0, 6400, 9000, 0}, /// 28W 182 ADL-P
+ {EnumAdlP28Watt642fCpuId, 2800, 2800, 6400, 0, 6400, 0, 6400, 0, 6400, 14000, 0}, /// 26W 682 ADL-P
+ {EnumAdlP28Watt662fCpuId, 2800, 2800, 6400, 0, 6400, 0, 6400, 0, 6400, 14000, 0}, /// 26W 682 ADL-P
+ {EnumAdlP45Watt682fCpuId, 4500, 4500, 11500, 0, 11500, 0, 11500, 0, 11500, 21500, 0}, /// 45W 682 ADL-P
+ {EnumAdlP45Watt242fCpuId, 4500, 4500, 9500, 0, 9500, 0, 9500, 0, 9500, 12500, 0}, /// 45W 242 ADL-P
+ {EnumAdlP45Watt482fCpuId, 4500, 4500, 9500, 0, 9500, 0, 9500, 0, 9500, 12500, 0}, /// 45W 482 ADL-P
+ {EnumAdlP45Watt442fCpuId, 4500, 4500, 9500, 0, 9500, 0, 9500, 0, 9500, 12500, 0}, /// 45W 442 ADL-P
+ {EnumAdlP45Watt642fCpuId, 4500, 4500, 11500, 0, 11500, 0, 11500, 0, 11500, 21500, 0}, /// 45W 642 ADL-P
+};
+
+GLOBAL_REMOVE_IF_UNREFERENCED CONST CPU_CORE_COUNT mCpuCoreCountMappingTable[] = {
+ { EnumAdlP15Watt282fCpuId, 2, 8},
+ { EnumAdlP28Watt282fCpuId, 2, 8},
+ { EnumAdlP28Watt482fCpuId, 4, 8},
+ { EnumAdlP28Watt682fCpuId, 6, 8},
+ { EnumAdlP45Watt682fCpuId, 6, 8},
+ { EnumAdlP45Watt482fCpuId, 4, 8},
+ { EnumAdlP45Watt442fCpuId, 4, 4},
+ { EnumAdlP28Watt442fCpuId, 4, 4},
+ { EnumAdlP15Watt142fCpuId, 1, 4},
+ { EnumAdlP28Watt142fCpuId, 1, 4},
+ { EnumAdlP15Watt242fCpuId, 2, 4},
+ { EnumAdlP28Watt242fCpuId, 2, 4},
+ { EnumAdlP45Watt242fCpuId, 2, 4},
+ { EnumAdlP45Watt642fCpuId, 6, 4},
+ { EnumAdlP28Watt182fCpuId, 1, 8},
+ { EnumAdlP28Watt642fCpuId, 6, 4},
+ { EnumAdlP28Watt662fCpuId, 6, 6},
+};
+
+/**
+ Return CPU Sku
+
+ @param[in] UINT32 CpuFamilyModel
+ @param[in] UINT16 CpuDid
+
+ @retval UINT8 CPU Sku
+**/
+UINT8
+GetCpuSkuInfo (
+ IN UINT32 CpuFamilyModel,
+ IN UINT16 CpuDid
+ )
+{
+ UINT8 CpuType;
+ BOOLEAN SkuFound;
+
+ SkuFound = TRUE;
+ CpuType = EnumCpuUnknown;
+
+ switch (CpuFamilyModel) {
+ case CPUID_FULL_FAMILY_MODEL_ALDERLAKE_MOBILE:
+ switch (CpuDid) {
+ case V_SA_DEVICE_ID_MB_ULT_1: // AlderLake P (6+8+GT)
+ case V_SA_DEVICE_ID_MB_ULT_2: // AlderLake P (6+4(f)+GT)
+ case V_SA_DEVICE_ID_MB_ULT_3: // AlderLake P (4(f)+8+GT)
+ case V_SA_DEVICE_ID_MB_ULT_4: // AlderLake P (2(f)+4(f)+GT)
+ case V_SA_DEVICE_ID_MB_ULT_5: // AlderLake P (2+8+GT)
+ case V_SA_DEVICE_ID_MB_ULT_6: // AlderLake P (2+4(f)+GT)
+ case V_SA_DEVICE_ID_MB_ULT_7: // AlderLake P (4+4(f)+GT)
+ case V_SA_DEVICE_ID_MB_ULT_8: // AlderLake P (1+4+GT) SA DID
+ case V_SA_DEVICE_ID_MB_ULT_9: // AlderLake P (1+8+GT) SA DID
+ case V_SA_DEVICE_ID_MB_ULT_10: // AlderLake P (6+6+GT) SA DID
+ CpuType = EnumCpuUlt;
+ break;
+ default:
+ SkuFound = FALSE;
+ break;
+ }
+ break;
+ default:
+ SkuFound = FALSE;
+ break;
+ }
+
+ if (!SkuFound) {
+ DEBUG ((DEBUG_ERROR, "Unsupported CPU SKU, Device ID: 0x%02X, CPUID: 0x%08X!\n", CpuDid, CpuFamilyModel));
+ ASSERT (FALSE);
+ }
+
+ return CpuType;
+}
+
+
+/**
+ This function returns the supported Physical Address Size
+
+ @retval returns the supported Physical Address Size.
+**/
+UINT8
+GetMaxPhysicalAddressSizeFru (
+ VOID
+ )
+{
+ //
+ // Even though CPUID Leaf CPUID_VIR_PHY_ADDRESS_SIZE (0x80000008) MAX_PA will report 46.
+ // For ADL BIOS will return Memory expansion 39 bit (0 - 38) + MKTME (Bits 39-41 must be zero - 3 bit hole in the middle) 42-45 bit is MKTME Keys.
+ //
+ return 39;
+}
+
+
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/LibraryPrivate/BaseCpuInfoFruLib/BaseCpuInfoFruLib.inf b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/LibraryPrivate/BaseCpuInfoFruLib/BaseCpuInfoFruLib.inf
new file mode 100644
index 0000000000..22bcbdf43c
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/LibraryPrivate/BaseCp
+++ uInfoFruLib/BaseCpuInfoFruLib.inf
@@ -0,0 +1,29 @@
+## @file
+# This file contains the Cpu Information for specific generation.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+
+[Defines]
+INF_VERSION = 0x00010017
+BASE_NAME = BaseCpuInfoFruLib
+FILE_GUID = 72E44627-C719-4B2D-8C5D-963E167E5AAC
+VERSION_STRING = 1.0
+MODULE_TYPE = BASE
+LIBRARY_CLASS = CpuInfoFruLib
+
+[LibraryClasses]
+BaseLib
+DebugLib
+PchInfoLib
+
+[Packages]
+MdePkg/MdePkg.dec
+UefiCpuPkg/UefiCpuPkg.dec
+AlderlakeSiliconPkg/SiPkg.dec
+
+[Sources]
+BaseCpuInfoFruLib.c
+
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/PeiReportCpuHob/Library/PeiReportCpuHobLib/PeiReportCpuHobLib.c b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/PeiReportCpuHob/Library/PeiReportCpuHobLib/PeiReportCpuHobLib.c
new file mode 100644
index 0000000000..7ea605a05b
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/PeiReportCpuHob/Libra
+++ ry/PeiReportCpuHobLib/PeiReportCpuHobLib.c
@@ -0,0 +1,22 @@
+/** @file
+
+ Source code file for Report CPU HOB library.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/
+
+#include <Base.h>
+#include <Library/HobLib.h>
+#include <Library/CpuPlatformLib.h>
+
+VOID
+ReportCpuHob (
+ VOID
+ )
+{
+ ///
+ /// Create a CPU hand-off information
+ ///
+ BuildCpuHob (GetMaxPhysicalAddressSize (), 16); }
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/PeiReportCpuHob/Library/PeiReportCpuHobLib/PeiReportCpuHobLib.inf b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/PeiReportCpuHob/Library/PeiReportCpuHobLib/PeiReportCpuHobLib.inf
new file mode 100644
index 0000000000..0ba4744eea
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/PeiReportCpuHob/Libra
+++ ry/PeiReportCpuHobLib/PeiReportCpuHobLib.inf
@@ -0,0 +1,26 @@
+### @file
+# Component information file for the Report CPU HOB library.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+[Defines]
+ INF_VERSION = 0x00010017
+ BASE_NAME = PeiReportCpuHobLib
+ FILE_GUID = F19AA754-CE24-448D-B755-1F939B00C23D
+ VERSION_STRING = 1.0
+ MODULE_TYPE = PEIM
+ LIBRARY_CLASS = ReportCpuHobLib
+
+[LibraryClasses]
+ BaseLib
+ HobLib
+ CpuPlatformLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ AlderlakeSiliconPkg/SiPkg.dec
+
+[Sources]
+ PeiReportCpuHobLib.c
--
2.36.1.windows.1
-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#108726): https://edk2.groups.io/g/devel/message/108726
Mute This Topic: https://groups.io/mt/101373952/7686176
Group Owner: devel+owner@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [rebecca@openfw.io]
-=-=-=-=-=-=-=-=-=-=-=-
^ permalink raw reply related [flat|nested] 41+ messages in thread
* Re: [edk2-devel] [PATCH v2 09/10] AlderlakeSiliconPkg: Add AdlPch Fru and IncludePrivate modules
2023-09-15 5:43 ` Chaganty, Rangasai V
@ 2023-09-15 13:29 ` Chuang, Rosen
0 siblings, 0 replies; 41+ messages in thread
From: Chuang, Rosen @ 2023-09-15 13:29 UTC (permalink / raw)
To: Chaganty, Rangasai V, Kasbekar, Saloni, devel@edk2.groups.io
Cc: Desimone, Nathaniel L
Reviewed-by: Rosen Chuang <rosen.chuang@intel.com>
-----Original Message-----
From: Chaganty, Rangasai V <rangasai.v.chaganty@intel.com>
Sent: Friday, September 15, 2023 1:44 PM
To: Kasbekar, Saloni <saloni.kasbekar@intel.com>; devel@edk2.groups.io
Cc: Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>; Chuang, Rosen <rosen.chuang@intel.com>
Subject: RE: [PATCH v2 09/10] AlderlakeSiliconPkg: Add AdlPch Fru and IncludePrivate modules
Reviewed-by: Sai Chaganty <rangasai.v.chaganty@intel.com>
-----Original Message-----
From: Kasbekar, Saloni <saloni.kasbekar@intel.com>
Sent: Thursday, September 14, 2023 9:46 PM
To: devel@edk2.groups.io
Cc: Kasbekar, Saloni <saloni.kasbekar@intel.com>; Chaganty, Rangasai V <rangasai.v.chaganty@intel.com>; Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>; Chuang, Rosen <rosen.chuang@intel.com>
Subject: [PATCH v2 09/10] AlderlakeSiliconPkg: Add AdlPch Fru and IncludePrivate modules
Adds the following modules:
- AdlPch/Include
- AdlPch/IncludePrivate
- AdlPch/Library
- AdlPch DSCs
- IncludePrivate
Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Rosen Chuang <rosen.chuang@intel.com>
Signed-off-by: Saloni Kasbekar <saloni.kasbekar@intel.com>
---
.../Fru/AdlPch/CommonLib.dsc | 29 ++
.../AlderlakeSiliconPkg/Fru/AdlPch/Dxe.dsc | 10 +
.../AlderlakeSiliconPkg/Fru/AdlPch/DxeLib.dsc | 7 +
.../Fru/AdlPch/Include/PchBdfAssignment.h | 81 +++++
.../Fru/AdlPch/Include/PchLimits.h | 47 +++
.../Fru/AdlPch/Include/PchPcieRpInfo.h | 17 ++
.../Fru/AdlPch/Include/PchReservedResources.h | 13 + .../AdlPch/Include/PchReservedResourcesAdpP.h | 36 +++
.../IncludePrivate/Register/PchPcrRegs.h | 59 ++++
.../IncludePrivate/Register/PchRegsLpcAdl.h | 30 ++
.../PeiDxeSmmPchInfoLib/PchInfoLibAdl.c | 223 ++++++++++++++
.../PeiDxeSmmPchInfoLib/PchInfoLibPrivate.h | 44 +++
.../PeiDxeSmmPchInfoLibAdl.inf | 37 +++
.../AlderlakeSiliconPkg/Fru/AdlPch/Pei.dsc | 7 +
.../AlderlakeSiliconPkg/Fru/AdlPch/PeiLib.dsc | 12 +
.../IncludePrivate/RegisterAccess.h | 288 ++++++++++++++++++
16 files changed, 940 insertions(+)
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/CommonLib.dsc
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Dxe.dsc
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/DxeLib.dsc
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Include/PchBdfAssignment.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Include/PchLimits.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Include/PchPcieRpInfo.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Include/PchReservedResources.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Include/PchReservedResourcesAdpP.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/IncludePrivate/Register/PchPcrRegs.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/IncludePrivate/Register/PchRegsLpcAdl.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Library/PeiDxeSmmPchInfoLib/PchInfoLibAdl.c
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Library/PeiDxeSmmPchInfoLib/PchInfoLibPrivate.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Library/PeiDxeSmmPchInfoLib/PeiDxeSmmPchInfoLibAdl.inf
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Pei.dsc
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/PeiLib.dsc
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IncludePrivate/RegisterAccess.h
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/CommonLib.dsc b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/CommonLib.dsc
new file mode 100644
index 0000000000..3f508f83a1
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/CommonLib.dsc
@@ -0,0 +1,29 @@
+## @file
+# Component description file for the AlderLake PCH Common FRU libraries.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+
+ PchPcrLib|$(PLATFORM_SI_PACKAGE)/IpBlock/P2sb/Library/PeiDxeSmmPchPcrL
+ ib/PeiDxeSmmPchPcrLib.inf
+ PchSbiAccessLib|$(PLATFORM_SI_PACKAGE)/IpBlock/P2sb/LibraryPrivate/Pei
+ DxeSmmPchSbiAccessLib/PeiDxeSmmPchSbiAccessLib.inf
+
+ P2SbSidebandAccessLib|$(PLATFORM_SI_PACKAGE)/IpBlock/P2sb/LibraryPriva
+ te/PeiDxeSmmP2SbSidebandAccessLib/PeiDxeSmmP2SbSidebandAccessLib.inf
+
+
+ EspiLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Espi/Library/PeiDxeSmmEspiLib/P
+ eiDxeSmmEspiLib.inf
+
+
+
+ PmcLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Pmc/Library/PeiDxeSmmPmcLib/PeiD
+ xeSmmPmcLib.inf
+ PmcPrivateLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Pmc/LibraryPrivate/PeiDxe
+ SmmPmcPrivateLib/PeiDxeSmmPmcPrivateLib.inf
+
+ SpiCommonLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Spi/LibraryPrivate/BaseSpi
+ CommonLib/BaseSpiCommonLib.inf
+ GpioLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Gpio/Library/PeiDxeSmmGpioLib/P
+ eiDxeSmmGpioLib.inf
+ PchDmiLib|$(PLATFORM_SI_PACKAGE)/IpBlock/PchDmi/LibraryPrivate/PeiDxeS
+ mmPchDmiLib/PeiDxeSmmPchDmiLib.inf
+
+
+ GpioPrivateLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Gpio/LibraryPrivate/PeiD
+ xeSmmGpioPrivateLib/PeiDxeSmmGpioPrivateLibVer2.inf
+
+ PchPcieRpLib|$(PLATFORM_SI_PACKAGE)/IpBlock/PcieRp/Library/PeiDxeSmmPc
+ hPcieRpLib/PeiDxeSmmPchPcieRpLibVer2.inf
+
+
+ #
+ # Common FRU Libraries
+ #
+
+ PchInfoLib|$(PLATFORM_SI_PACKAGE)/Fru/AdlPch/Library/PeiDxeSmmPchInfoL
+ ib/PeiDxeSmmPchInfoLibAdl.inf
+
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Dxe.dsc b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Dxe.dsc
new file mode 100644
index 0000000000..b443611d9a
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Dxe.dsc
@@ -0,0 +1,10 @@
+## @file
+# Component description file for the AlderLake PCH DXE FRU drivers.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+ $(PLATFORM_SI_PACKAGE)/IpBlock/Spi/Smm/SpiSmm.inf
+
+
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/DxeLib.dsc b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/DxeLib.dsc
new file mode 100644
index 0000000000..e350b8e643
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/DxeLib.dsc
@@ -0,0 +1,7 @@
+# @file
+# Component description file for the AlderLake PCH DXE FRU libraries.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+GpioHelpersLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Gpio/LibraryPrivate/BaseG
+pioHelpersLibNull/BaseGpioHelpersLibNull.inf
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Include/PchBdfAssignment.h b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Include/PchBdfAssignment.h
new file mode 100644
index 0000000000..b8af6d7624
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Include/PchBdfAssignm
+++ ent.h
@@ -0,0 +1,81 @@
+/** @file
+ Header file for AlderLake PCH devices PCI Bus Device Function map.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/ #ifndef
+_PCH_BDF_ASSIGNMENT_H_ #define _PCH_BDF_ASSIGNMENT_H_
+
+#define NOT_PRESENT 0xFF
+
+//
+// PCH PCIe Controllers
+//
+#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_1 28
+#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_2 28
+#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_3 28
+#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_4 28
+#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_5 28
+#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_6 28
+#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_7 28
+#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_8 28
+#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_9 29
+#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_10 29
+#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_11 29
+#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_12 29
+#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_13 29
+#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_14 29
+#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_15 29
+#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_16 29
+#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_17 27
+#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_18 27
+#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_19 27
+#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_20 27
+#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_21 27
+#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_22 27
+#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_23 27
+#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_24 27
+#ifdef PCH_ADPP
+#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_25 NOT_PRESENT
+#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_26 NOT_PRESENT
+#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_27 NOT_PRESENT
+#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_28 NOT_PRESENT
+#else
+#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_25 26
+#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_26 26
+#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_27 26
+#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_28 26
+#endif
+
+//
+// USB3 (XHCI) Controller PCI config
+//
+#define PCI_DEVICE_NUMBER_PCH_XHCI 20
+#define PCI_FUNCTION_NUMBER_PCH_XHCI 0
+
+
+
+
+//
+// LPC Controller (D31:F0)
+//
+#define PCI_DEVICE_NUMBER_PCH_LPC 31
+#define PCI_FUNCTION_NUMBER_PCH_LPC 0
+
+//
+// Primary to Sideband (P2SB) Bridge (D31:F1) //
+#define PCI_DEVICE_NUMBER_PCH_P2SB 31
+#define PCI_FUNCTION_NUMBER_PCH_P2SB 1
+
+
+
+//
+// SPI Controller (D31:F5)
+//
+#define PCI_DEVICE_NUMBER_PCH_SPI 31
+#define PCI_FUNCTION_NUMBER_PCH_SPI 5
+
+
+#endif // _PCH_BDF_ASSIGNMENT_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Include/PchLimits.h b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Include/PchLimits.h
new file mode 100644
index 0000000000..dad3a9a073
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Include/PchLimits.h
@@ -0,0 +1,47 @@
+/** @file
+ Build time limits of PCH resources.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/ #ifndef
+_PCH_LIMITS_H_ #define _PCH_LIMITS_H_
+/*
+ * Defines povided in this file are indended to be used only where
+static value
+ * is needed. They are set to values which allow to accomodate multiple
+projects
+ * needs. Where runtime usage is possible please used dedicated
+functions from
+ * PchInfoLib to retrieve accurate values */
+
+
+
+//
+// PCIe limits
+//
+#define PCH_MAX_PCIE_ROOT_PORTS 28
+#define PCH_MAX_PCIE_CONTROLLERS 7
+
+//
+// PCIe clocks limits
+//
+#define PCH_MAX_PCIE_CLOCKS 18
+
+//
+// DMI lanes
+//
+#define PCH_MAX_DMI_LANES 8
+
+//
+// SerialIo limits
+//
+#define PCH_MAX_SERIALIO_I2C_CONTROLLERS 8
+#define PCH_MAX_SERIALIO_SPI_CONTROLLERS 7
+#define PCH_MAX_SERIALIO_SPI_CHIP_SELECTS 2
+#define PCH_MAX_SERIALIO_UART_CONTROLLERS 7
+
+//
+// Number of eSPI slaves
+//
+#define PCH_MAX_ESPI_SLAVES 2
+
+#endif // _PCH_LIMITS_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Include/PchPcieRpInfo.h b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Include/PchPcieRpInfo.h
new file mode 100644
index 0000000000..9276b61e1f
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Include/PchPcieRpInfo
+++ .h
@@ -0,0 +1,17 @@
+/** @file
+ Pcie Root Port info header
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/
+
+#ifndef _PCH_PCIERP_INFO_H_
+#define _PCH_PCIERP_INFO_H_
+
+//
+// Number of PCIe ports per PCIe controller //
+#define PCH_PCIE_CONTROLLER_PORTS 4u
+
+
+#endif
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Include/PchReservedResources.h b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Include/PchReservedResources.h
new file mode 100644
index 0000000000..f4adfab74f
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Include/PchReservedRe
+++ sources.h
@@ -0,0 +1,13 @@
+/** @file
+ PCH preserved MMIO resource definitions.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/
+
+#ifndef _PCH_PRESERVED_RESOURCES_H_
+#define _PCH_PRESERVED_RESOURCES_H_
+#include "PchReservedResourcesAdpP.h"
+
+#endif // _PCH_PRESERVED_RESOURCES_H_
+
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Include/PchReservedResourcesAdpP.h b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Include/PchReservedResourcesAdpP.h
new file mode 100644
index 0000000000..69aac29cea
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Include/PchReservedRe
+++ sourcesAdpP.h
@@ -0,0 +1,36 @@
+/** @file
+ PCH preserved MMIO resource definitions.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/ #ifndef
+_PCH_PRESERVED_RESOURCES_ADP_P_H_
+#define _PCH_PRESERVED_RESOURCES_ADP_P_H_
+
+/**
+ Detailed recommended static allocation
+ +-------------------------------------------------------------------------+
+ | PCH preserved MMIO range, 32 MB, from 0xFC800000 to 0xFE7FFFFF |
+ +-------------------------------------------------------------------------+
+ | Size | Start | End | Usage |
+ | 8 MB | 0xFC800000 | 0xFCFFFFFF | TraceHub SW BAR |
+ | 16 MB | 0xFD000000 | 0xFDFFFFFF | SBREG |
+ | 64 KB | 0xFE000000 | 0xFE00FFFF | PMC MBAR |
+ | 4 KB | 0xFE010000 | 0xFE010FFF | SPI BAR0 |
+ | 176 KB | 0xFE020000 | 0xFE04BFFF | SerialIo BAR in ACPI mode |
+ | 400 KB | 0xFE04C000 | 0xFE0AFFFF | Unused |
+ | 64 KB | 0xFE0B0000 | 0xFE0BFFFF | eSPI LGMR BAR |
+ | 64 KB | 0xFE0C0000 | 0xFE0CFFFF | eSPI2 SEGMR BAR |
+ | 192 KB | 0xFE0D0000 | 0xFE0FFFFF | Unused |
+ | 1 MB | 0xFE100000 | 0xFE1FFFFF | TraceHub MTB BAR |
+ | 2 MB | 0xFE200000 | 0xFE3FFFFF | TraceHub FW BAR |
+ | 2 MB | 0xFE400000 | 0xFE5FFFFF | Unused |
+ | 2 MB | 0xFE600000 | 0xFE7FFFFF | Temp address |
+
++----------------------------------------------------------------------
+---+
+**/
+#define PCH_PCR_BASE_ADDRESS 0xFD000000 ///< SBREG MMIO base address
+#define PCH_PWRM_BASE_ADDRESS 0xFE000000 ///< PMC MBAR MMIO base address
+#define PCH_SPI_BASE_ADDRESS 0xFE010000 ///< SPI BAR0 MMIO base address
+
+#endif // _PCH_PRESERVED_RESOURCES_ADP_P_H_
+
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/IncludePrivate/Register/PchPcrRegs.h b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/IncludePrivate/Register/PchPcrRegs.h
new file mode 100644
index 0000000000..fe548dae4b
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/IncludePrivate/Regist
+++ er/PchPcrRegs.h
@@ -0,0 +1,59 @@
+/** @file
+ Register names for PCH private chipset register
+
+Conventions:
+
+ - Register definition format:
+
+ Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_Re
+ gisterName
+ - Prefix:
+ Definitions beginning with "R_" are registers
+ Definitions beginning with "B_" are bits within registers
+ Definitions beginning with "V_" are meaningful values within the bits
+ Definitions beginning with "S_" are register size
+ Definitions beginning with "N_" are the bit position
+ - [GenerationName]:
+ Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc.).
+ Register name without GenerationName applies to all generations.
+ - [ComponentName]:
+ This field indicates the component name that the register belongs to (e.g. PCH, SA etc.)
+ Register name without ComponentName applies to all components.
+ Register that is specific to -H denoted by "_PCH_H_" in component name.
+ Register that is specific to -LP denoted by "_PCH_LP_" in component name.
+ - SubsystemName:
+ This field indicates the subsystem name of the component that the register belongs to
+ (e.g. PCIE, USB, SATA, GPIO, PMC etc.).
+ - RegisterSpace:
+ MEM - MMIO space register of subsystem.
+ IO - IO space register of subsystem.
+ PCR - Private configuration register of subsystem.
+ CFG - PCI configuration space register of subsystem.
+ - RegisterName:
+ Full register name.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/
+
+#ifndef _PCH_REGS_PCR_H_
+#define _PCH_REGS_PCR_H_
+
+
+/**
+ Definition for SBI PID
+ The PCH_SBI_PID defines the PID for PCR MMIO programming and PCH SBI programming as well.
+**/
+#define PID_DMI 0x88
+#define PID_ESPISPI 0x72
+#define PID_SPF 0x85
+#define PID_SPE 0x84
+#define PID_SPD 0x83
+#define PID_SPC 0x82
+#define PID_SPB 0x81
+#define PID_SPA 0x80
+#define PID_GPIOCOM0 0x6E
+#define PID_GPIOCOM1 0x6D
+#define PID_GPIOCOM2 0x6C
+#define PID_GPIOCOM4 0x6A
+#define PID_GPIOCOM5 0x69
+
+#endif
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/IncludePrivate/Register/PchRegsLpcAdl.h b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/IncludePrivate/Register/PchRegsLpcAdl.h
new file mode 100644
index 0000000000..8b1a01036e
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/IncludePrivate/Regist
+++ er/PchRegsLpcAdl.h
@@ -0,0 +1,30 @@
+/** @file
+ Register names for ADL PCH LPC/eSPI device
+
+ Conventions:
+
+ - Prefixes:
+ Definitions beginning with "R_" are registers
+ Definitions beginning with "B_" are bits within registers
+ Definitions beginning with "V_" are meaningful values within the bits
+ Definitions beginning with "S_" are register sizes
+ Definitions beginning with "N_" are the bit position
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/ #ifndef
+_PCH_REGS_LPC_ADL_H_ #define _PCH_REGS_LPC_ADL_H_
+
+//
+// ADL PCH-P/M LPC Device IDs
+//
+#define V_ADL_PCH_P_LPC_CFG_DEVICE_ID_MB_0 0x5180 ///< LPC/eSPI Controller
+#define V_ADL_PCH_P_LPC_CFG_DEVICE_ID_MB_1 0x5181 ///< LPC/eSPI Controller P SuperSKU
+#define V_ADL_PCH_P_LPC_CFG_DEVICE_ID_MB_2 0x5182 ///< LPC/eSPI Controller P Premium
+#define V_ADL_PCH_P_LPC_CFG_DEVICE_ID_MB_3 0x5183 ///< LPC/eSPI Controller Placeholder
+#define V_ADL_PCH_P_LPC_CFG_DEVICE_ID_MB_4 0x5184 ///< LPC/eSPI Controller
+#define V_ADL_PCH_P_LPC_CFG_DEVICE_ID_MB_5 0x5185 ///< LPC/eSPI Controller
+
+
+#endif
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Library/PeiDxeSmmPchInfoLib/PchInfoLibAdl.c b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Library/PeiDxeSmmPchInfoLib/PchInfoLibAdl.c
new file mode 100644
index 0000000000..c74d665533
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Library/PeiDxeSmmPchI
+++ nfoLib/PchInfoLibAdl.c
@@ -0,0 +1,223 @@
+/** @file
+ Pch information library for ADL.
+
+ All function in this library is available for PEI, DXE, and SMM, But
+ do not support UEFI RUNTIME environment call.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/ #include <Base.h>
+#include <PchPcieRpInfo.h> #include <Uefi/UefiBaseType.h> #include
+<Library/PchInfoLib.h> #include <Library/PmcPrivateLib.h> #include
+<Library/PrintLib.h> #include <Library/IoLib.h> #include
+<Library/DebugLib.h> #include <Library/BaseLib.h> #include
+<Library/PciSegmentLib.h> #include <Library/PcdLib.h> #include
+<Library/PchPciBdfLib.h> #include <Register/PchRegsLpcAdl.h> #include
+<Register/PchRegs.h> #include <Register/PchRegsLpc.h> #include
+<IndustryStandard/Pci30.h> #include "PchInfoLibPrivate.h"
+
+
+/**
+ Return LPC Device Id
+
+ @retval PCH_LPC_DEVICE_ID PCH Lpc Device ID
+**/
+UINT16
+PchGetLpcDid (
+ VOID
+ )
+{
+ UINT64 LpcBaseAddress;
+
+ LpcBaseAddress = LpcPciCfgBase ();
+
+ return PciSegmentRead16 (LpcBaseAddress + PCI_DEVICE_ID_OFFSET); }
+
+/**
+ Return Pch Series
+
+ @retval PCH_SERIES Pch Series
+**/
+PCH_SERIES
+PchSeries (
+ VOID
+ )
+{
+ PCH_SERIES PchSer;
+ static PCH_SERIES PchSeries = PCH_UNKNOWN_SERIES;
+
+ if (PchSeries != PCH_UNKNOWN_SERIES) {
+ return PchSeries;
+ }
+
+ PchSer = PchSeriesFromLpcDid (PchGetLpcDid ());
+
+ PchSeries = PchSer;
+
+ return PchSer;
+}
+
+/**
+ Return Pch stepping type
+
+ @retval PCH_STEPPING Pch stepping type
+**/
+PCH_STEPPING
+PchStepping (
+ VOID
+ )
+{
+ UINT8 RevId;
+ UINT64 LpcBaseAddress;
+ static PCH_STEPPING PchStepping = PCH_STEPPING_MAX;
+
+ if (PchStepping != PCH_STEPPING_MAX) {
+ return PchStepping;
+ }
+
+ LpcBaseAddress = LpcPciCfgBase ();
+ RevId = PciSegmentRead8 (LpcBaseAddress + PCI_REVISION_ID_OFFSET);
+
+ RevId = PchSteppingFromRevId (RevId);
+
+ PchStepping = RevId;
+
+ return RevId;
+}
+
+/**
+ Check if this is PCH P series
+
+ @retval TRUE It's PCH P series
+ @retval FALSE It's not PCH P series
+**/
+BOOLEAN
+IsPchP (
+ VOID
+ )
+{
+ return (PchSeries () == PCH_P);
+}
+
+/**
+ return support status for P2SB PCR 20-bit addressing
+
+ @retval TRUE
+ @retval FALSE
+**/
+BOOLEAN
+IsP2sb20bPcrSupported (
+ VOID
+ )
+{
+ return FALSE;
+}
+
+/**
+ Determine Pch Series based on Device Id
+
+ @param[in] LpcDeviceId Lpc Device Id
+
+ @retval PCH_SERIES Pch Series
+**/
+PCH_SERIES
+PchSeriesFromLpcDid (
+ IN UINT16 LpcDeviceId
+ )
+{
+ return PCH_P;
+}
+
+/**
+ Determine Pch Stepping based on Revision ID
+
+ @param[in] RevId Pch Revision Id
+
+ @retval PCH_STEPPING Pch Stepping
+**/
+PCH_STEPPING
+PchSteppingFromRevId (
+ IN UINT8 RevId
+ )
+{
+ return RevId;
+}
+
+
+/**
+ Check if this is PCH LP series
+
+ @retval TRUE It's PCH LP series
+ @retval FALSE It's not PCH LP series
+**/
+BOOLEAN
+IsPchLp (
+ VOID
+ )
+{
+ return (PchSeries () == PCH_LP || PchSeries () == PCH_P || PchSeries
+() == PCH_M || PchSeries () == PCH_N ); }
+/**
+ Get RST mode supported by the silicon
+
+ @retval RST_MODE RST mode supported by silicon
+**/
+
+GLOBAL_REMOVE_IF_UNREFERENCED
+struct PCH_SKU_STRING mSkuStrs[] = {
+ //
+ // ADL PCH LPC Device IDs
+ //
+ {V_ADL_PCH_P_LPC_CFG_DEVICE_ID_MB_0, "ADL SKU 0"},
+ {V_ADL_PCH_P_LPC_CFG_DEVICE_ID_MB_1, "P Super SKU (SSKU)"},
+ {V_ADL_PCH_P_LPC_CFG_DEVICE_ID_MB_2, "P Premium"},
+ {V_ADL_PCH_P_LPC_CFG_DEVICE_ID_MB_3, "ADL No UFS"},
+ {V_ADL_PCH_P_LPC_CFG_DEVICE_ID_MB_4, "ADL SKU 4"},
+ {V_ADL_PCH_P_LPC_CFG_DEVICE_ID_MB_5, "ADL SKU 5"},
+
+ {0xFFFF, NULL}
+};
+
+/**
+ Get Pch Maximum Pcie Root Port Number
+
+ @retval Pch Maximum Pcie Root Port Number **/
+UINT8
+GetPchMaxPciePortNum (
+ VOID
+ )
+{
+ switch (PchSeries ()) {
+ case PCH_P:
+ case PCH_N:
+ return 12;
+ case PCH_S:
+ return 28;
+ default:
+ return 0;
+ }
+}
+
+/**
+ Get Pch Maximum Serial IO I2C controllers number
+
+ @retval Pch Maximum Serial IO I2C controllers number **/
+UINT8
+GetPchMaxSerialIoI2cControllersNum (
+ VOID
+ )
+{
+ return 8;
+}
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Library/PeiDxeSmmPchInfoLib/PchInfoLibPrivate.h b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Library/PeiDxeSmmPchInfoLib/PchInfoLibPrivate.h
new file mode 100644
index 0000000000..a4bd4d5aa7
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Library/PeiDxeSmmPchI
+++ nfoLib/PchInfoLibPrivate.h
@@ -0,0 +1,44 @@
+/** @file
+ Private header for PCH Info Lib.
+
+ All function in this library is available for PEI, DXE, and SMM, But
+ do not support UEFI RUNTIME environment call.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/
+
+/**
+ Structure for PCH SKU string mapping
+**/
+struct PCH_SKU_STRING {
+ UINT16 Id;
+ CHAR8 *String;
+};
+
+extern struct PCH_SKU_STRING mSkuStrs[];
+
+/**
+ Determine Pch Series based on Device Id
+
+ @param[in] LpcDeviceId Lpc Device Id
+
+ @retval PCH_SERIES Pch Series
+**/
+PCH_SERIES
+PchSeriesFromLpcDid (
+ IN UINT16 LpcDeviceId
+ );
+
+/**
+ Determine Pch Stepping based on Revision ID
+
+ @param[in] RevId Pch Revision Id
+
+ @retval PCH_STEPPING Pch Stepping
+**/
+PCH_STEPPING
+PchSteppingFromRevId (
+ IN UINT8 RevId
+ );
+
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Library/PeiDxeSmmPchInfoLib/PeiDxeSmmPchInfoLibAdl.inf b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Library/PeiDxeSmmPchInfoLib/PeiDxeSmmPchInfoLibAdl.inf
new file mode 100644
index 0000000000..28a6863aed
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Library/PeiDxeSmmPchI
+++ nfoLib/PeiDxeSmmPchInfoLibAdl.inf
@@ -0,0 +1,37 @@
+## @file
+# PCH information library for Alderlake PCH.
+#
+# All function in this library is available for PEI, DXE, and SMM, #
+But do not support UEFI RUNTIME environment call.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+
+[Defines]
+INF_VERSION = 0x00010017
+BASE_NAME = PeiDxeSmmPchInfoLibAdl
+FILE_GUID = F5B0CBB7-4AFC-4535-A5EC-D9ECEDA24DC5
+VERSION_STRING = 1.0
+MODULE_TYPE = BASE
+LIBRARY_CLASS = PchInfoLib
+
+
+[LibraryClasses]
+BaseLib
+IoLib
+DebugLib
+PrintLib
+PciSegmentLib
+PmcPrivateLib
+PcdLib
+
+
+[Packages]
+MdePkg/MdePkg.dec
+AlderlakeSiliconPkg/SiPkg.dec
+
+
+[Sources]
+PchInfoLibAdl.c
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Pei.dsc b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Pei.dsc
new file mode 100644
index 0000000000..8a923554dd
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Pei.dsc
@@ -0,0 +1,7 @@
+## @file
+# Component description file for the AlderLake PCH PEI FRU drivers.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/PeiLib.dsc b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/PeiLib.dsc
new file mode 100644
index 0000000000..ebe2bbfda0
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/PeiLib.dsc
@@ -0,0 +1,12 @@
+## @file
+# Component description file for the AlderLake PCH PEI FRU libraries.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+
+ SpiLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Spi/Library/PeiSpiLib/PeiSpiLib.
+ inf
+
+
+ GpioHelpersLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Gpio/LibraryPrivate/PeiG
+ pioHelpersLib/PeiGpioHelpersLib.inf
+
+
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IncludePrivate/RegisterAccess.h b/Silicon/Intel/AlderlakeSiliconPkg/IncludePrivate/RegisterAccess.h
new file mode 100644
index 0000000000..25a0ba49d2
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IncludePrivate/RegisterAccess.h
@@ -0,0 +1,288 @@
+/** @file
+ Header file for register access.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/
+
+#ifndef _REGISTER_ACCESS_H_
+#define _REGISTER_ACCESS_H_
+
+typedef struct _REGISTER_ACCESS REGISTER_ACCESS;
+
+/**
+ Reads an 8-bit register
+
+ @param[in] This Pointer to REGISTER_ACCESS
+ @param[in] Offset Offset of the register in the register bank
+
+ @return The 8-bit register value specified by Offset **/ typedef
+UINT8
+(*REG_READ8) (
+ IN REGISTER_ACCESS *This,
+ IN UINT32 Offset
+ );
+
+/**
+ Writes an 8-bit register
+
+ @param[in] This Pointer to REGISTER_ACCESS
+ @param[in] Offset Offset of the register in the register bank
+ @param[in] Value Value to write to register
+
+ @return The 8-bit register value written to register **/ typedef
+UINT8
+(*REG_WRITE8) (
+ IN REGISTER_ACCESS *This,
+ IN UINT32 Offset,
+ IN UINT8 Value
+ );
+
+/**
+ Performs an 8-bit or on the register
+
+ @param[in] This Pointer to REGISTER_ACCESS
+ @param[in] Offset Offset of the register in the register bank
+ @param[in] OrData Data with which register should be OR-ed
+
+ @return The 8-bit register value written to register **/ typedef
+UINT8
+(*REG_OR8) (
+ IN REGISTER_ACCESS *This,
+ IN UINT32 Offset,
+ IN UINT8 OrData
+ );
+
+/**
+ Performs an 8-bit and on the register
+
+ @param[in] This Pointer to REGISTER_ACCESS
+ @param[in] Offset Offset of the register in the register bank
+ @param[in] AndData Data with which register should be AND-ed
+
+ @return The 8-bit register value written to register **/ typedef
+UINT8
+(*REG_AND8) (
+ IN REGISTER_ACCESS *This,
+ IN UINT32 Offset,
+ IN UINT8 AndData
+ );
+
+/**
+ Performs an 8-bit and then or on the register
+
+ @param[in] This Pointer to REGISTER_ACCESS
+ @param[in] Offset Offset of the register in the register bank
+ @param[in] AndData Data with which register should be AND-ed
+ @param[in] OrData Data with which register should be OR-ed
+
+ @return The 8-bit register value written to register **/ typedef
+UINT8
+(*REG_AND_THEN_OR8) (
+ IN REGISTER_ACCESS *This,
+ IN UINT32 Offset,
+ IN UINT8 AndData,
+ IN UINT8 OrData
+ );
+
+/**
+ Reads a 16-bit register
+
+ @param[in] This Pointer to REGISTER_ACCESS
+ @param[in] Offset Offset of the register in the register bank
+
+ @return The 16-bit register value specified by Offset **/ typedef
+UINT16
+(*REG_READ16) (
+ IN REGISTER_ACCESS *This,
+ IN UINT32 Offset
+ );
+
+/**
+ Writes a 16-bit register
+
+ @param[in] This Pointer to REGISTER_ACCESS
+ @param[in] Offset Offset of the register in the register bank
+ @param[in] Value Value to write to register
+
+ @return The 16-bit register value written to register **/ typedef
+UINT16
+(*REG_WRITE16) (
+ IN REGISTER_ACCESS *This,
+ IN UINT32 Offset,
+ IN UINT16 Value
+ );
+
+/**
+ Performs a 16-bit or on the register
+
+ @param[in] This Pointer to REGISTER_ACCESS
+ @param[in] Offset Offset of the register in the register bank
+ @param[in] OrData Data with which register should be OR-ed
+
+ @return The 16-bit register value written to register **/ typedef
+UINT16
+(*REG_OR16) (
+ IN REGISTER_ACCESS *This,
+ IN UINT32 Offset,
+ IN UINT16 OrData
+ );
+
+/**
+ Performs a 16-bit and on the register
+
+ @param[in] This Pointer to REGISTER_ACCESS
+ @param[in] Offset Offset of the register in the register bank
+ @param[in] AndData Data with which register should be AND-ed
+
+ @return The 16-bit register value written to register **/ typedef
+UINT16
+(*REG_AND16) (
+ IN REGISTER_ACCESS *This,
+ IN UINT32 Offset,
+ IN UINT16 AndData
+ );
+
+/**
+ Performs a 16-bit and then or on the register
+
+ @param[in] This Pointer to REGISTER_ACCESS
+ @param[in] Offset Offset of the register in the register bank
+ @param[in] AndData Data with which register should be AND-ed
+ @param[in] OrData Data with which register should be OR-ed
+
+ @return The 16-bit register value written to register **/ typedef
+UINT16
+(*REG_AND_THEN_OR16) (
+ IN REGISTER_ACCESS *This,
+ IN UINT32 Offset,
+ IN UINT16 AndData,
+ IN UINT16 OrData
+ );
+
+/**
+ Reads a 32-bit register
+
+ @param[in] This Pointer to REGISTER_ACCESS
+ @param[in] Offset Offset of the register in the register bank
+
+ @return The 32-bit register value specified by Offset **/ typedef
+UINT32
+(*REG_READ32) (
+ IN REGISTER_ACCESS *This,
+ IN UINT32 Offset
+ );
+
+/**
+ Writes a 32-bit register
+
+ @param[in] This Pointer to REGISTER_ACCESS
+ @param[in] Offset Offset of the register in the register bank
+ @param[in] Value Value to write to register
+
+ @return The 32-bit register value written to register **/ typedef
+UINT32
+(*REG_WRITE32) (
+ IN REGISTER_ACCESS *This,
+ IN UINT32 Offset,
+ IN UINT32 Value
+ );
+
+/**
+ Performs a 32-bit or on the register
+
+ @param[in] This Pointer to REGISTER_ACCESS
+ @param[in] Offset Offset of the register in the register bank
+ @param[in] OrData Data with which register should be OR-ed
+
+ @return The 32-bit register value written to register **/ typedef
+UINT32
+(*REG_OR32) (
+ IN REGISTER_ACCESS *This,
+ IN UINT32 Offset,
+ IN UINT32 OrData
+ );
+
+/**
+ Performs a 32-bit and on the register
+
+ @param[in] This Pointer to REGISTER_ACCESS
+ @param[in] Offset Offset of the register in the register bank
+ @param[in] AndData Data with which register should be AND-ed
+
+ @return The 32-bit register value written to register **/ typedef
+UINT32
+(*REG_AND32) (
+ IN REGISTER_ACCESS *This,
+ IN UINT32 Offset,
+ IN UINT32 AndData
+ );
+
+/**
+ Performs a 32-bit and then or on the register
+
+ @param[in] This Pointer to REGISTER_ACCESS
+ @param[in] Offset Offset of the register in the register bank
+ @param[in] AndData Data with which register should be AND-ed
+ @param[in] OrData Data with which register should be OR-ed
+
+ @return The 32-bit register value written to register **/ typedef
+UINT32
+(*REG_AND_THEN_OR32) (
+ IN REGISTER_ACCESS *This,
+ IN UINT32 Offset,
+ IN UINT32 AndData,
+ IN UINT32 OrData
+ );
+
+struct _REGISTER_ACCESS {
+ REG_READ8 Read8;
+ REG_WRITE8 Write8;
+ REG_OR8 Or8;
+ REG_AND8 And8;
+ REG_AND_THEN_OR8 AndThenOr8;
+
+ REG_READ16 Read16;
+ REG_WRITE16 Write16;
+ REG_OR16 Or16;
+ REG_AND16 And16;
+ REG_AND_THEN_OR16 AndThenOr16;
+
+ REG_READ32 Read32;
+ REG_WRITE32 Write32;
+ REG_OR32 Or32;
+ REG_AND32 And32;
+ REG_AND_THEN_OR32 AndThenOr32;
+};
+
+#endif
--
2.36.1.windows.1
-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#108727): https://edk2.groups.io/g/devel/message/108727
Mute This Topic: https://groups.io/mt/101373953/7686176
Group Owner: devel+owner@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [rebecca@openfw.io]
-=-=-=-=-=-=-=-=-=-=-=-
^ permalink raw reply related [flat|nested] 41+ messages in thread
* Re: [edk2-devel] [PATCH v2 10/10] AlderlakeSiliconPkg: Add Alderlake Product and SiPkg.dec
2023-09-15 5:43 ` Chaganty, Rangasai V
@ 2023-09-15 13:29 ` Chuang, Rosen
0 siblings, 0 replies; 41+ messages in thread
From: Chuang, Rosen @ 2023-09-15 13:29 UTC (permalink / raw)
To: Chaganty, Rangasai V, Kasbekar, Saloni, devel@edk2.groups.io
Cc: Desimone, Nathaniel L
Reviewed-by: Rosen Chuang <rosen.chuang@intel.com>
-----Original Message-----
From: Chaganty, Rangasai V <rangasai.v.chaganty@intel.com>
Sent: Friday, September 15, 2023 1:44 PM
To: Kasbekar, Saloni <saloni.kasbekar@intel.com>; devel@edk2.groups.io
Cc: Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>; Chuang, Rosen <rosen.chuang@intel.com>
Subject: RE: [PATCH v2 10/10] AlderlakeSiliconPkg: Add Alderlake Product and SiPkg.dec
Reviewed-by: Sai Chaganty <rangasai.v.chaganty@intel.com>
-----Original Message-----
From: Kasbekar, Saloni <saloni.kasbekar@intel.com>
Sent: Thursday, September 14, 2023 9:46 PM
To: devel@edk2.groups.io
Cc: Kasbekar, Saloni <saloni.kasbekar@intel.com>; Chaganty, Rangasai V <rangasai.v.chaganty@intel.com>; Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>; Chuang, Rosen <rosen.chuang@intel.com>
Subject: [PATCH v2 10/10] AlderlakeSiliconPkg: Add Alderlake Product and SiPkg.dec
Adds the following modules:
- Product/Alderlake/Include
- Product/Alderlake/Library
- Product/Alderlake DSCs
- SiPkg.dec
Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Rosen Chuang <rosen.chuang@intel.com>
Signed-off-by: Saloni Kasbekar <saloni.kasbekar@intel.com>
---
.../Product/Alderlake/Include/Ppi/SiPolicy.h | 55 ++
.../Library/PeiSiPolicyLib/PeiSiPolicyLib.c | 47 ++
.../Library/PeiSiPolicyLib/PeiSiPolicyLib.inf | 47 ++
.../PeiSiPolicyLib/PeiSiPolicyLibPreMem.c | 47 ++
.../PeiSiPolicyLib/PeiSiPolicyLibrary.h | 21 +
.../Product/Alderlake/SiPkgBuildOption.dsc | 122 ++++
.../Product/Alderlake/SiPkgCommonLib.dsc | 36 +
.../Product/Alderlake/SiPkgDxe.dsc | 32 +
.../Product/Alderlake/SiPkgDxeLib.dsc | 23 +
.../Product/Alderlake/SiPkgPeiLib.dsc | 19 +
Silicon/Intel/AlderlakeSiliconPkg/SiPkg.dec | 625 ++++++++++++++++++
11 files changed, 1074 insertions(+)
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/Include/Ppi/SiPolicy.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/Library/PeiSiPolicyLib/PeiSiPolicyLib.c
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/Library/PeiSiPolicyLib/PeiSiPolicyLib.inf
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/Library/PeiSiPolicyLib/PeiSiPolicyLibPreMem.c
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/Library/PeiSiPolicyLib/PeiSiPolicyLibrary.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/SiPkgBuildOption.dsc
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/SiPkgCommonLib.dsc
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/SiPkgDxe.dsc
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/SiPkgDxeLib.dsc
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/SiPkgPeiLib.dsc
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/SiPkg.dec
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/Include/Ppi/SiPolicy.h b/Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/Include/Ppi/SiPolicy.h
new file mode 100644
index 0000000000..703f0221bd
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/Include/Ppi/Si
+++ Policy.h
@@ -0,0 +1,55 @@
+/** @file
+ Silicon Policy PPI is used for specifying platform
+ related Intel silicon information and policy setting.
+ This PPI is consumed by the silicon PEI modules and carried
+ over to silicon DXE modules.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/
+
+#ifndef _SI_POLICY_PPI_H_
+#define _SI_POLICY_PPI_H_
+
+#include <SiPolicyStruct.h>
+#include <PchPolicyCommon.h>
+#include <PchPreMemPolicyCommon.h>
+#include <Uefi.h>
+#include <ConfigBlock/CpuConfig.h>
+#include <ConfigBlock/CpuConfigLibPreMemConfig.h>
+#include <ConfigBlock/CpuSecurityPreMemConfig.h>
+
+#ifndef DISABLED
+#define DISABLED 0
+#endif
+#ifndef ENABLED
+#define ENABLED 1
+#endif
+
+extern EFI_GUID gSiPreMemPolicyPpiGuid; extern EFI_GUID
+gSiPolicyPpiGuid;
+
+
+#include <GraphicsConfig.h>
+
+
+#include <CpuPcieConfigGen3.h>
+#include <CpuPcieConfig.h>
+extern EFI_GUID gCpuPciePeiPreMemConfigGuid; extern EFI_GUID
+gCpuPcieRpConfigGuid;
+
+#include <MemoryConfig.h>
+extern EFI_GUID gMemoryConfigGuid;
+extern EFI_GUID gMemoryConfigNoCrcGuid;
+
+#include <ConfigBlock/SaMiscPeiPreMemConfig.h>
+extern EFI_GUID gSaMiscPeiPreMemConfigGuid;
+
+#include <HostBridgeConfig.h>
+extern EFI_GUID gHostBridgePeiPreMemConfigGuid; extern EFI_GUID
+gHostBridgePeiConfigGuid;
+
+typedef struct _SI_PREMEM_POLICY_STRUCT SI_PREMEM_POLICY_PPI; typedef
+struct _SI_POLICY_STRUCT SI_POLICY_PPI;
+
+#endif // _SI_POLICY_PPI_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/Library/PeiSiPolicyLib/PeiSiPolicyLib.c b/Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/Library/PeiSiPolicyLib/PeiSiPolicyLib.c
new file mode 100644
index 0000000000..886415bdaa
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/Library/PeiSiP
+++ olicyLib/PeiSiPolicyLib.c
@@ -0,0 +1,47 @@
+/** @file
+ This file is PeiSiPolicyLib library creates default settings of RC
+ Policy and installs RC Policy PPI.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/ #include
+"PeiSiPolicyLibrary.h"
+#include <Library/PcdLib.h>
+#include <Library/PchInfoLib.h>
+
+
+/**
+ SiInstallPolicyReadyPpi installs SiPolicyReadyPpi.
+ While installed, RC assumes the Policy is ready and finalized. So
+please update and override
+ any setting before calling this function.
+
+ @retval EFI_SUCCESS The policy is installed.
+ @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer
+**/
+EFI_STATUS
+EFIAPI
+SiInstallPolicyReadyPpi (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+ EFI_PEI_PPI_DESCRIPTOR *SiPolicyReadyPpiDesc;
+
+ SiPolicyReadyPpiDesc = (EFI_PEI_PPI_DESCRIPTOR *) AllocateZeroPool
+ (sizeof (EFI_PEI_PPI_DESCRIPTOR)); if (SiPolicyReadyPpiDesc == NULL) {
+ ASSERT (FALSE);
+ return EFI_OUT_OF_RESOURCES;
+ }
+
+ SiPolicyReadyPpiDesc->Flags = EFI_PEI_PPI_DESCRIPTOR_PPI |
+ EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST;
+ SiPolicyReadyPpiDesc->Guid = &gSiPolicyReadyPpiGuid;
+ SiPolicyReadyPpiDesc->Ppi = NULL;
+
+ //
+ // Install Silicon Policy Ready PPI
+ //
+ Status = PeiServicesInstallPpi (SiPolicyReadyPpiDesc);
+ ASSERT_EFI_ERROR (Status);
+ return Status;
+}
+
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/Library/PeiSiPolicyLib/PeiSiPolicyLib.inf b/Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/Library/PeiSiPolicyLib/PeiSiPolicyLib.inf
new file mode 100644
index 0000000000..7dab1ff510
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/Library/PeiSiP
+++ olicyLib/PeiSiPolicyLib.inf
@@ -0,0 +1,47 @@
+## @file
+# Component description file for the PeiSiPolicyLib library.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+
+[Defines]
+INF_VERSION = 0x00010017
+BASE_NAME = PeiSiPolicyLib
+FILE_GUID = 97584FAE-9299-4202-9889-2D339E4BFA5B
+VERSION_STRING = 1.0
+MODULE_TYPE = PEIM
+LIBRARY_CLASS = SiPolicyLib
+
+
+[LibraryClasses]
+DebugLib
+IoLib
+PeiServicesLib
+BaseMemoryLib
+MemoryAllocationLib
+ConfigBlockLib
+PcdLib
+CpuPlatformLib
+
+[Packages]
+MdePkg/MdePkg.dec
+AlderlakeSiliconPkg/SiPkg.dec
+
+[Sources]
+PeiSiPolicyLib.c
+PeiSiPolicyLibrary.h
+PeiSiPolicyLibPreMem.c
+
+
+[Guids]
+gSiConfigGuid ## CONSUMES
+gSiPreMemConfigGuid ## CONSUMES
+gPciePreMemConfigGuid ## CONSUMES
+
+[Ppis]
+gSiPolicyPpiGuid ## PRODUCES
+gSiPreMemPolicyPpiGuid ## PRODUCES
+gSiPolicyReadyPpiGuid ## CONSUMES
+gSiPreMemPolicyReadyPpiGuid ## CONSUMES
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/Library/PeiSiPolicyLib/PeiSiPolicyLibPreMem.c b/Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/Library/PeiSiPolicyLib/PeiSiPolicyLibPreMem.c
new file mode 100644
index 0000000000..93bffac2b0
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/Library/PeiSiP
+++ olicyLib/PeiSiPolicyLibPreMem.c
@@ -0,0 +1,47 @@
+/** @file
+ This file is PeiSiPolicyLib library creates default settings of RC
+ Policy and installs RC Policy PPI.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/ #include
+"PeiSiPolicyLibrary.h"
+#include <Base.h>
+#include <PciePreMemConfig.h>
+#include <Library/PchInfoLib.h>
+#include <Library/CpuPlatformLib.h>
+
+/**
+ SiPreMemInstallPolicyReadyPpi installs SiPreMemPolicyReadyPpi.
+ While installed, RC assumes the Policy is ready and finalized. So
+please update and override
+ any setting before calling this function.
+
+ @retval EFI_SUCCESS The policy is installed.
+ @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer
+**/
+EFI_STATUS
+EFIAPI
+SiPreMemInstallPolicyReadyPpi (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+ EFI_PEI_PPI_DESCRIPTOR *SiPolicyReadyPreMemPpiDesc;
+
+ SiPolicyReadyPreMemPpiDesc = (EFI_PEI_PPI_DESCRIPTOR *)
+ AllocateZeroPool (sizeof (EFI_PEI_PPI_DESCRIPTOR)); if (SiPolicyReadyPreMemPpiDesc == NULL) {
+ ASSERT (FALSE);
+ return EFI_OUT_OF_RESOURCES;
+ }
+
+ SiPolicyReadyPreMemPpiDesc->Flags = EFI_PEI_PPI_DESCRIPTOR_PPI |
+ EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST;
+ SiPolicyReadyPreMemPpiDesc->Guid = &gSiPreMemPolicyReadyPpiGuid;
+ SiPolicyReadyPreMemPpiDesc->Ppi = NULL;
+
+ //
+ // Install PreMem Silicon Policy Ready PPI
+ //
+ Status = PeiServicesInstallPpi (SiPolicyReadyPreMemPpiDesc);
+ ASSERT_EFI_ERROR (Status);
+ return Status;
+}
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/Library/PeiSiPolicyLib/PeiSiPolicyLibrary.h b/Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/Library/PeiSiPolicyLib/PeiSiPolicyLibrary.h
new file mode 100644
index 0000000000..aac24cf187
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/Library/PeiSiP
+++ olicyLib/PeiSiPolicyLibrary.h
@@ -0,0 +1,21 @@
+/** @file
+ Header file for the PeiSiPolicyLib library.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/ #ifndef
+_PEI_SI_POLICY_LIBRARY_H_ #define _PEI_SI_POLICY_LIBRARY_H_
+
+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/PeiServicesLib.h>
+#include <Library/MemoryAllocationLib.h> #include
+<Library/ConfigBlockLib.h> #include <Ppi/SiPolicy.h> #include
+<Library/SiPolicyLib.h>
+
+
+
+#endif // _PEI_SI_POLICY_LIBRARY_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/SiPkgBuildOption.dsc b/Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/SiPkgBuildOption.dsc
new file mode 100644
index 0000000000..290d6eb885
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/SiPkgBuildOpti
+++ on.dsc
@@ -0,0 +1,122 @@
+## @file
+# Silicon build option configuration file.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+[BuildOptions]
+# Define Build Options both for EDK and EDKII drivers.
+
+# SA
+!if gSiPkgTokenSpaceGuid.PcdAdlLpSupport == TRUE DEFINE
+PCH_BUILD_OPTIONS = -DPCH_ADPP !else DEFINE PCH_BUILD_OPTIONS =
+-DPCH_ADL !endif # # SA # !if gSiPkgTokenSpaceGuid.PcdBdatEnable ==
+TRUE
+ DEFINE BDAT_BUILD_OPTION = -DBDAT_SUPPORT=1 !else
+ DEFINE BDAT_BUILD_OPTION =
+!endif
+
+ DEFINE SLE_BUILD_OPTIONS =
+!if $(TARGET) == RELEASE
+!if gSiPkgTokenSpaceGuid.PcdSiCatalogDebugEnable == TRUE
+ DEFINE DEBUG_BUILD_OPTIONS =
+!else
+ # MDEPKG_NDEBUG is introduced for the intention
+ # of size reduction when compiler optimization is disabled. If
+MDEPKG_NDEBUG is
+ # defined, then debug and assert related macros wrapped by it are the NULL implementations.
+ DEFINE DEBUG_BUILD_OPTIONS = -DMDEPKG_NDEBUG !endif !else
+ DEFINE DEBUG_BUILD_OPTIONS =
+!endif
+
+!if ($(TARGET) == RELEASE) AND
+(gSiPkgTokenSpaceGuid.PcdSiCatalogDebugEnable == TRUE)
+ DEFINE RELEASE_CATALOG_BUILD_OPTIONS = -DRELEASE_CATALOG !else
+ DEFINE RELEASE_CATALOG_BUILD_OPTIONS = !endif
+
+!if gSiPkgTokenSpaceGuid.PcdOptimizeCompilerEnable == FALSE
+ DEFINE OPTIMIZE_DISABLE_OPTIONS = -Od -GL- !else
+ DEFINE OPTIMIZE_DISABLE_OPTIONS =
+!endif
+
+ DEFINE HSLE_BUILD_OPTIONS =
+
+
+DEFINE CPU_FLAGS = -DCPU_ADL
+
+
+DEFINE DSC_SIPKG_FEATURE_BUILD_OPTIONS = $(BDAT_BUILD_OPTION)
+$(DEBUG_BUILD_OPTIONS) DEFINE DSC_SIPKG_FEATURE_BUILD_OPTIONS =
+$(DSC_SIPKG_FEATURE_BUILD_OPTIONS) $(PCH_BUILD_OPTIONS) $(CPU_FLAGS)
+$(HSLE_BUILD_OPTIONS)
+
+!if gSiPkgTokenSpaceGuid.PcdSourceDebugEnable == TRUE
+ *_*_X64_GENFW_FLAGS = --keepexceptiontable !endif
+
+[BuildOptions.Common.EDKII]
+
+#
+# For IA32 Global Build Flag
+#
+ *_*_IA32_CC_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) -D PI_SPECIFICATION_VERSION=0x00010015 -DASF_PEI
+ *_*_IA32_VFRPP_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS)
+ *_*_IA32_APP_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS)
+ *_*_IA32_ASLPP_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS)
+ *_*_IA32_ASLCC_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS)
+
+#
+# For IA32 Specific Build Flag
+#
+CLANGPDB:*_*_IA32_CC_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) -D PI_SPECIFICATION_VERSION=0x00010015 -DASF_PEI -Wno-enum-conversion -Wno-incompatible-pointer-types-discards-qualifiers -Wno-sometimes-uninitialized -Wno-braced-scalar-init -Wno-nonportable-include-path -Wno-misleading-indentation
+GCC: *_*_IA32_PP_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS)
+MSFT: *_*_IA32_ASM_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS)
+MSFT: *_*_IA32_CC_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) $(OPTIMIZE_DISABLE_OPTIONS) -D PI_SPECIFICATION_VERSION=0x00010015 -DASF_PEI /w34668
+MSFT: *_*_IA32_VFRPP_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) $(OPTIMIZE_DISABLE_OPTIONS)
+MSFT: *_*_IA32_APP_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) $(OPTIMIZE_DISABLE_OPTIONS)
+MSFT: *_*_IA32_ASLPP_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) $(OPTIMIZE_DISABLE_OPTIONS)
+MSFT: *_*_IA32_ASLCC_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) $(OPTIMIZE_DISABLE_OPTIONS)
+
+#
+# For X64 Global Build Flag
+#
+ *_*_X64_CC_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) -D PI_SPECIFICATION_VERSION=0x00010015
+ *_*_X64_VFRPP_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS)
+ *_*_X64_APP_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS)
+ *_*_X64_ASLPP_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS)
+ *_*_X64_ASLCC_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS)
+
+#
+# For X64 Specific Build Flag
+#
+CLANGPDB:*_*_X64_CC_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) -D PI_SPECIFICATION_VERSION=0x00010015 -Wno-enum-conversion -Wno-main-return-type -Wno-incompatible-pointer-types -Wno-implicit-function-declaration -Wno-unused-variable -Wno-incompatible-pointer-types-discards-qualifiers -Wno-ignored-pragma-optimize -Wno-bitwise-op-parentheses -Wno-sometimes-uninitialized -Wno-unused-function -Wno-misleading-indentation
+GCC: *_*_X64_PP_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS)
+MSFT: *_*_X64_ASM_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS)
+MSFT: *_*_X64_CC_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) $(OPTIMIZE_DISABLE_OPTIONS) -D PI_SPECIFICATION_VERSION=0x00010015 /w34668
+MSFT: *_*_X64_VFRPP_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) $(OPTIMIZE_DISABLE_OPTIONS)
+MSFT: *_*_X64_APP_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) $(OPTIMIZE_DISABLE_OPTIONS)
+MSFT: *_*_X64_ASLPP_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS)
+MSFT: *_*_X64_ASLCC_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS)
+
+#
+# For Xcode Specific Build Flag
+#
+# Override assembly code build order
+*_XCODE5_*_*_BUILDRULEORDER = nasm S s
+# Align 47bfbd7f8069e523798ef973c8eb0abd5c6b0746 to fix the usage of
+VA_START in undefined way *_XCODE5_*_CC_FLAGS = -Wno-varargs
+
+# Force PE/COFF sections to be aligned at 4KB boundaries to support
+page level protection of runtime modules [BuildOptions.common.EDKII.DXE_RUNTIME_DRIVER]
+ MSFT: *_*_*_DLINK_FLAGS = /ALIGN:4096
+ GCC: *_GCC*_*_DLINK_FLAGS = -z common-page-size=0x1000
+
+
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/SiPkgCommonLib.dsc b/Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/SiPkgCommonLib.dsc
new file mode 100644
index 0000000000..69eca2ecc1
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/SiPkgCommonLib
+++ .dsc
@@ -0,0 +1,36 @@
+## @file
+# Component description file for the AlderLake SiPkg both Pei and Dxe libraries DSC file.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+#
+#
+# FRUs
+#
+!include $(PLATFORM_SI_PACKAGE)/Fru/AdlCpu/CommonLib.dsc
+!include $(PLATFORM_SI_PACKAGE)/Fru/AdlPch/CommonLib.dsc
+#
+# Common
+#
+ PciSegmentLib|$(PLATFORM_SI_PACKAGE)/Library/BasePciSegmentMultiSegLib
+ PciSegmentLib|Pci/BasePciSegmentMultiSegLibPci.inf
+
+#
+# Cpu
+#
+ CpuPlatformLib|$(PLATFORM_SI_PACKAGE)/Cpu/Library/PeiDxeSmmCpuPlatform
+ CpuPlatformLib|Lib/PeiDxeSmmCpuPlatformLib.inf
+
+#
+# Pch
+#
+ PchCycleDecodingLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/PeiDxeSmmPchCyc
+ PchCycleDecodingLib|leDecodingLib/PeiDxeSmmPchCycleDecodingLib.inf
+
+ ResetSystemLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/BaseResetSystemLib/B
+ ResetSystemLib|aseResetSystemLib.inf
+#private
+ GpioPrivateLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Gpio/LibraryPrivate/PeiD
+ GpioPrivateLib|xeSmmGpioPrivateLib/PeiDxeSmmGpioPrivateLibVer2.inf
+ PchPciBdfLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/BasePchPciBdfLib/BaseP
+ PchPciBdfLib|chPciBdfLib.inf
+
+#
+# SA
+#
+ GraphicsInfoLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Graphics/Library/PeiDxe
+ GraphicsInfoLib|SmmGraphicsInfoLib/GraphicsInfoLibVer1.inf
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/SiPkgDxe.dsc b/Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/SiPkgDxe.dsc
new file mode 100644
index 0000000000..97e63dcc96
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/SiPkgDxe.dsc
@@ -0,0 +1,32 @@
+## @file
+# Component description file for the AlderLake SiPkg DXE drivers.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+#
+# FRUs
+#
+!include $(PLATFORM_SI_PACKAGE)/Fru/AdlPch/Dxe.dsc
+#
+# Common
+#
+
+#
+# Pch
+#
+ $(PLATFORM_SI_PACKAGE)/Pch/SmmControl/RuntimeDxe/SmmControl.inf
+
+ $(PLATFORM_SI_PACKAGE)/Pch/PchSmiDispatcher/Smm/PchSmiDispatcher.inf{
+ <LibraryClasses>
+
+ SmiHandlerProfileLib|MdePkg/Library/SmiHandlerProfileLibNull/SmiHandle
+ rProfileLibNull.inf
+ }
+
+#
+# SystemAgent
+#
+ $(PLATFORM_SI_PACKAGE)/SystemAgent/SaInit/Dxe/SaInitDxe.inf
+
+
+
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/SiPkgDxeLib.dsc b/Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/SiPkgDxeLib.dsc
new file mode 100644
index 0000000000..37876cbfc4
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/SiPkgDxeLib.ds
+++ c
@@ -0,0 +1,23 @@
+# @file
+# Component description file for the AlderLake SiPkg DXE libraries.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+#
+# FRUs
+#
+!include $(PLATFORM_SI_PACKAGE)/Fru/AdlCpu/DxeLib.dsc
+!include $(PLATFORM_SI_PACKAGE)/Fru/AdlPch/DxeLib.dsc
+
+#
+# Common
+#
+ AslUpdateLib|IntelSiliconPkg/Library/DxeAslUpdateLib/DxeAslUpdateLib.i
+ AslUpdateLib|nf
+ SiConfigBlockLib|$(PLATFORM_SI_PACKAGE)/Library/BaseSiConfigBlockLib/B
+ SiConfigBlockLib|aseSiConfigBlockLib.inf
+
+#
+# SystemAgent
+#
+ DxeSaPolicyLib|$(PLATFORM_SI_PACKAGE)/SystemAgent/Library/DxeSaPolicyL
+ DxeSaPolicyLib|ib/DxeSaPolicyLib.inf
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/SiPkgPeiLib.dsc b/Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/SiPkgPeiLib.dsc
new file mode 100644
index 0000000000..21e6ff3851
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/SiPkgPeiLib.ds
+++ c
@@ -0,0 +1,19 @@
+## @file
+# Component description file for the AlderLake SiPkg PEI libraries.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+#
+# FRUs
+#
+!include $(PLATFORM_SI_PACKAGE)/Fru/AdlPch/PeiLib.dsc
+
+
+ SiPolicyLib|$(PLATFORM_SI_PACKAGE)/Product/Alderlake/Library/PeiSiPoli
+ SiPolicyLib|cyLib/PeiSiPolicyLib.inf
+ SiConfigBlockLib|$(PLATFORM_SI_PACKAGE)/Library/BaseSiConfigBlockLib/B
+ SiConfigBlockLib|aseSiConfigBlockLib.inf
+
+
+
+
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/SiPkg.dec b/Silicon/Intel/AlderlakeSiliconPkg/SiPkg.dec
new file mode 100644
index 0000000000..ce9cfe599a
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/SiPkg.dec
@@ -0,0 +1,625 @@
+## @file
+# Component description file for the Silicon Reference Code.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+
+[Defines]
+DEC_SPECIFICATION = 0x00010017
+PACKAGE_NAME = SiPkg
+PACKAGE_VERSION = 0.1
+PACKAGE_GUID = F245E276-44A0-46b3-AEB5-9898BBCF008D
+
+[Includes.Common.Private]
+
+#
+# AlderLake Fru
+#
+Fru/AdlCpu/IncludePrivate
+Fru/AdlPch/IncludePrivate
+
+##
+# IpBlock IncludePrivate
+#
+IpBlock/Pmc/IncludePrivate
+IpBlock/Graphics/IncludePrivate
+IpBlock/PchDmi/IncludePrivate
+IpBlock/P2sb/IncludePrivate
+IpBlock/Spi/IncludePrivate
+IpBlock/Gpio/IncludePrivate
+IpBlock/HostBridge/IncludePrivate
+
+# Cpu
+Cpu/IncludePrivate
+
+IncludePrivate
+
+[Includes]
+Product/Alderlake/Include
+#
+# AlderLake
+#
+Fru/AdlCpu/Include
+Fru/AdlPch/Include
+
+
+# CPU PCIe
+IpBlock/CpuPcieRp/Include
+
+#
+# - Memory
+Include/ConfigBlock/Memory/Ver2
+#
+# - Graphics
+Include/ConfigBlock/Graphics/Gen12
+IpBlock/Graphics/Include
+
+#
+# - CPU PCIe
+Include/ConfigBlock/CpuPcieRp/Gen4
+
+#
+# HostBridge
+#
+Include/ConfigBlock/HostBridge/Ver1
+
+Include
+#
+# SystemAgent
+#
+SystemAgent/Include
+Include/ConfigBlock/PcieRp
+Include/ConfigBlock/Vmd
+Include/ConfigBlock/CpuPcieRp/Gen4
+Include/ConfigBlock/CpuPcieRp/Gen3
+
+#
+# Cpu
+#
+Cpu/Include
+
+
+#
+# Pch
+#
+Pch/Include
+Include/ConfigBlock/Espi
+Include/ConfigBlock/Smbus
+Include/ConfigBlock/Pmc
+Include/ConfigBlock/PchDmi
+Include/ConfigBlock/Wdt
+Include/ConfigBlock/PcieRp/PchPcieRp
+Include/ConfigBlock/PcieRp
+Include/ConfigBlock/SerialIo
+
+[Guids.common.Private]
+#
+# PCH
+#
+gGpioLibUnlockHobGuid = { 0xA7892E49, 0x0F9F, 0x4166, { 0xB8, 0xD6, 0x8A, 0x9B, 0xD9, 0x8B, 0x17, 0x38 }}
+
+[Guids]
+gSmbiosProcessorInfoHobGuid = {0xe6d73d92, 0xff56, 0x4146, {0xaf, 0xac, 0x1c, 0x18, 0x81, 0x7d, 0x68, 0x71}}
+gSmbiosCacheInfoHobGuid = {0xd805b74e, 0x1460, 0x4755, {0xbb, 0x36, 0x1e, 0x8c, 0x8a, 0xd6, 0x78, 0xd7}}
+
+##
+## MdeModulePkg
+##
+gEfiMemoryTypeInformationGuid = {0x4c19049f, 0x4137, 0x4dd3, {0x9c,
+0x10, 0x8b, 0x97, 0xa8, 0x3f, 0xfd, 0xfa}} gEfiCapsuleVendorGuid =
+{0x711c703f, 0xc285, 0x4b10, {0xa3, 0xb0, 0x36, 0xec, 0xbd, 0x3c, 0x8b,
+0xe2}} gEfiConsoleOutDeviceGuid = { 0xd3b36f2c, 0xd551, 0x11d4, { 0x9a,
+0x46, 0x0, 0x90, 0x27, 0x3f, 0xc1, 0x4d}} ## ## Common ## ##
+Include/ConfigBlock/SiConfig.h gSiConfigGuid = {0x4ed6d282, 0x22f3,
+0x4fe1, {0xa6, 0x61, 0x6, 0x1a, 0x97, 0x38, 0x59, 0xd8}} ##
+gSiPreMemConfigGuid = {0xb94c004c, 0xa0ab, 0x40f0, {0x9b, 0x61, 0x0b,
+0x25, 0x88, 0xbe, 0xfd, 0xc6}} ## ## gPciePreMemConfigGuid =
+{0xd0f9c2a9, 0x7332, 0x4733, {0x8d, 0xb1, 0x98, 0x79, 0x27, 0x60, 0xda,
+0xe6}} ## gSiPkgTokenSpaceGuid = {0x977c97c1, 0x47e1, 0x4b6b, {0x96,
+0x69, 0x43, 0x66, 0x99, 0xcb, 0xe4, 0x5b}}
+
+gSiConfigHobGuid = {0xb3903068, 0x7482, 0x4424, {0xba, 0x4b, 0x40,
+0x5f, 0x8f, 0xd7, 0x65, 0x4e}}
+
+##
+##
+## SystemAgent
+##
+gSaDataHobGuid = {0xe07d0bda, 0xbf90, 0x46a9, { 0xb0, 0x0e, 0xb2,
+0xc4, 0x4a, 0x0e, 0xd6, 0xd0}} gSaConfigHobGuid = {0x762fa2e6, 0xea3b,
+0x41c8, { 0x8c, 0x52, 0x63, 0x76, 0x6d, 0x70, 0x39, 0xe0}}
+gSaMiscPeiPreMemConfigGuid = {0x4a525577, 0x3469, 0x4f11, { 0x99,
+0xcf, 0xfb, 0xcd, 0x5e, 0xf1, 0x84, 0xe4}} gCpuPciePeiPreMemConfigGuid = { 0x81baf3c9, 0xf295, 0x4572, { 0x8b, 0x21, 0x79, 0x3f, 0xa3, 0x1b, 0xa5, 0xdb}} gVmdPeiConfigGuid = { 0x79b52c74, 0xb9ba, 0x4f36, {0xa2, 0x40, 0xf2, 0x41, 0x0d, 0x20, 0x84, 0x8a}}
+gVmdInfoHobGuid = { 0xccd0306e, 0x7fa1, 0x4df5, {0x99, 0x99, 0xc1, 0xf8, 0x9a, 0x1d, 0x1b, 0xa9}}
+gMemoryConfigGuid = { 0x26cf084c, 0xc9db, 0x41bb, { 0x92, 0xc6, 0xd1,
+0x97, 0xb8, 0xa1, 0xe4, 0xbf}} gMemoryConfigNoCrcGuid = { 0xc56c73d0,
+0x1cdb, 0x4c0c, { 0xa9, 0x57, 0xea, 0x62, 0xa9, 0xe6, 0xf5, 0x0c}}
+gMemoryDxeConfigGuid = {0xa5c7dda8, 0x686b, 0x404f, {0x86, 0x40,
+0xf8, 0x2, 0xd, 0x84, 0x4c, 0x94}} gCpuPcieRpPrememConfigGuid = {
+0x41aef892, 0xc800, 0x4ac0, {0xa9, 0x30, 0x84, 0xac, 0x47, 0xca, 0xca, 0x7e}} gCpuPcieRpConfigGuid = { 0x9749a5fb, 0x9130, 0x44f0, {0x8f, 0x61, 0xdb, 0xff, 0x8e, 0xf2, 0xca, 0xc7}} ## IntelFsp2Pkg/IntelFsp2Pkg.dec gSiMemoryS3DataGuid is the same as gFspNonVolatileStorageHobGuid
+gSiMemoryS3DataGuid = { 0x721acf02, 0x4d77, 0x4c2a, { 0xb3, 0xdc, 0x27, 0x0b, 0x7b, 0xa9, 0xe4, 0xb0 } }
+gSiMemoryInfoDataGuid = { 0x9b2071d4, 0xb054, 0x4e0c, { 0x8d, 0x09, 0x11, 0xcf, 0x8b, 0x9f, 0x03, 0x23 } }
+gSiMemoryPlatformDataGuid = { 0x6210d62f, 0x418d, 0x4999, { 0xa2, 0x45,
+0x22, 0x10, 0x0a, 0x5d, 0xea, 0x44 } } gSaPciePeiConfigGuid = {
+0xdaa929a9, 0x5ec9, 0x486a, { 0xb0, 0xf7, 0x82, 0x3a, 0x55, 0xc7, 0xb5,
+0xb3}} gSaPciePeiPreMemConfigGuid = { 0xfc5e01a3, 0x69f6, 0x4e35, {
+0x9f, 0xcf, 0x6, 0x68, 0x7b, 0xab, 0x31, 0xd7}}
+
+#
+# Host Bridge
+#
+gHostBridgePeiPreMemConfigGuid = {0xbdef6805, 0x2080, 0x44ad, { 0x93,
+0x2e, 0x00, 0x04, 0xf5, 0x2c, 0xb7, 0xa1}} gHostBridgePeiConfigGuid =
+{0x3b6d998e, 0x8b6e, 0x4f53, { 0xbe, 0x41, 0x7, 0x41, 0x95, 0x53, 0x8a,
+0xaf}} gHostBridgeDataHobGuid = {0x3b682d57, 0xd402, 0x40a6, { 0xb1,
+0x34, 0xa0, 0xc4, 0xf6, 0x31, 0x1d, 0x9}}
+
+#
+# Graphics
+#
+gGraphicsPeiConfigGuid = {0x04249ac0, 0x0088, 0x439f, { 0xa7, 0x4e,
+0xa7, 0x04, 0x2a, 0x06, 0x2f, 0x5d}} gGraphicsDxeConfigGuid =
+{0x34d93161, 0xf78e, 0x4915, {0xad, 0xc4, 0xdb, 0x67, 0x16, 0x42, 0x39,
+0x24}}
+
+## Include/SsaCommonConfig.h
+gSsaPostcodeHookGuid = {0xADF0A27B, 0x61A6, 0x4F18, {0x9E, 0xAC, 0x46,
+0x87, 0xE7, 0x9E, 0x6F, 0xBB}} gSsaBiosVariablesGuid = {0x43eeffe8,
+0xa978, 0x41dc, {0x9d, 0xb6, 0x54, 0xc4, 0x27, 0xf2, 0x7e, 0x2a}}
+gSsaBiosResultsGuid = {0x8f4e928, 0xf5f, 0x46d4, {0x84, 0x10, 0x47,
+0x9f, 0xda, 0x27, 0x9d, 0xb6}} gHobUsageDataGuid = {0xc764a821, 0xec41,
+0x450d, { 0x9c, 0x99, 0x27, 0x20, 0xfc, 0x7c, 0xe1, 0xf6 }}
+
+##
+## Cpu
+##
+gCpuAcpiTableStorageGuid = {0xc38fb0e2, 0x0c43, 0x49c9, {0xb5, 0x44,
+0x9b, 0x17, 0xaa, 0x4d, 0xcb, 0xa3}} gCpuSecurityPreMemConfigGuid =
+{0xfd5c346, 0x8260, 0x4067, {0x94, 0x69, 0xcf, 0x91, 0x68, 0xa3, 0x42,
+0x90}} gCpuConfigLibPreMemConfigGuid = {0xfc1c0ec2, 0xc6b4, 0x4f05,
+{0xbb, 0x85, 0xc8, 0x0, 0x8d, 0x5b, 0x4a, 0xb7}} gCpuConfigGuid =
+{0x48c3aac9, 0xd66c, 0x42e4, {0x9b, 0x1d, 0x39, 0x4, 0x5f, 0x46, 0x53,
+0x41}} gCpuDataHobGuid = {0x1eec629f, 0xf3cf, 0x4b02, { 0xa9, 0xa5,
+0x27, 0xa2, 0x33, 0x20, 0xbe, 0x5d}} ## ## Me ## gPciImrHobGuid =
+{0x49b1eac3, 0x0cd6, 0x451e, {0x96, 0x30, 0x92, 0x4b, 0xc2, 0x69, 0x35,
+0x86}} gTpm2AcpiTableStorageGuid = {0x7d279373, 0xeecc, 0x4d4f,
+{0xae, 0x2f, 0xce, 0xc4, 0xb7, 0x06, 0xb0, 0x6a}} gEdkiiTouchPanelGuid
+= {0x91b1d27b, 0xe126, 0x48d1, {0x82, 0x34, 0xd2, 0x8b, 0x81, 0xc8,
+0x83, 0x62}} gMeDidSentHobGuid = {0x4c3d3af1, 0x1720, 0x4c3f, {0xab,
+0x7c, 0x36, 0x50, 0xbb, 0x5b, 0x85, 0x7e}}
+
+##
+## PCH
+##
+gPchGlobalResetGuid = { 0x9db31b4c, 0xf5ef, 0x48bb, { 0x94, 0x2b,
+0x18, 0x1f, 0x7e, 0x3a, 0x3e, 0x40 }}
+
+gPchGeneralPreMemConfigGuid = {0xC65F62FA, 0x52B9, 0x4837, {0x86,
+0xEB, 0x1A, 0xFB, 0xD4, 0xAD, 0xBB, 0x3E}} gWatchDogPreMemConfigGuid =
+{0xFBCE08CC, 0x60F2, 0x4BDF, {0xB7, 0x88, 0x09, 0xBB, 0x81, 0x65, 0x52,
+0x2B}} gPcieRpPreMemConfigGuid = {0x8377AB38, 0xF8B0, 0x476A, { 0x9C,
+0xA1, 0x68, 0xEA, 0x78, 0x57, 0xD8, 0x2A}} gSmbusPreMemConfigGuid =
+{0x77A6E62C, 0x716B, 0x4386, {0x9E, 0x9C, 0x23, 0xA0, 0x2E, 0x13, 0x7B,
+0x3A}} gLpcPreMemConfigGuid = {0xA6E6032F, 0x1E58, 0x407E, {0x9A,
+0xB8, 0xC6, 0x30, 0xC6, 0xC4, 0x11, 0x8E}} gPchDmiPreMemConfigGuid =
+{0x4DA4AA22, 0xB54A, 0x43D7, {0x87, 0xC8, 0xA3, 0xCF, 0x53, 0xE6, 0xC1,
+0x8A}}
+
+gPchGeneralConfigGuid = {0x6ED94C8C, 0x25F7, 0x4686, {0xB2, 0x46,
+0xCA, 0x4D, 0xE2, 0x95, 0x4B, 0x5D}} gPchPcieConfigGuid =
+{0x0A53B507, 0x988B, 0x475C, {0xBF, 0x76, 0x33, 0xDE, 0x10, 0x6D, 0x94,
+0x84}} gPchPcieRpDxeConfigGuid = {0x475530EA, 0xBD72, 0x416F, {0x98,
+0x9F,0x48, 0x70, 0x5F, 0x14, 0x4E, 0xD9}} gIoApicConfigGuid =
+{0x2873D0F1, 0x00F6, 0x40AB, {0xAC, 0x36, 0x9A, 0x68, 0xBA, 0x87, 0x3E,
+0x6C}} gPchDmiConfigGuid = {0xB3A61210, 0x1CD3, 0x4797, {0x8E, 0xE6,
+0xD3, 0x42, 0x9C, 0x4F, 0x17, 0xBD}} gSerialIoConfigGuid =
+{0x6CC06EBF, 0x0D34, 0x4340, {0xBC, 0x16, 0xDA, 0x09, 0xE5, 0x78, 0x3A,
+0xDB}}
+
+##
+## SecurityPkg
+##
+## GUID used to "Tcg2PhysicalPresence" variable and "Tcg2PhysicalPresenceFlags" variable for TPM2 request and response.
+# Include/Guid/Tcg2PhysicalPresenceData.h
+gEfiTcg2PhysicalPresenceGuid = { 0xaeb9c5c1, 0x94f1, 0x4d02, { 0xbf, 0xd9, 0x46, 0x2, 0xdb, 0x2d, 0x3c, 0x54 }}
+
+##
+## FSP
+##
+gFspSiliconFvGuid = { 0x1b5c27fe, 0xf01c, 0x4fbc, { 0xae, 0xae, 0x34, 0x1b, 0x2e, 0x99, 0x2a, 0x17 }}
+gFspTscFrequencyGuid = { 0x0e3b622a, 0xedbb, 0x4e30, { 0x93, 0x60, 0x69, 0x5c, 0xd4, 0xb3, 0x20, 0xc9 }}
+gFspInfoGuid = { 0x067e0f25, 0x374f, 0x47c2, { 0x17, 0x92, 0x86, 0xdc, 0xdb, 0xc4, 0x8a, 0xc9 }}
+
+[Protocols]
+##
+## MdeModulePkg
+##
+gEdkiiSmmExitBootServicesProtocolGuid = { 0x296eb418, 0xc4c8, 0x4e05, {
+0xab, 0x59, 0x39, 0xe8, 0xaf, 0x56, 0xf0, 0xa } }
+
+##
+## SystemAgent
+##
+gIgdOpRegionProtocolGuid = {0x9e67aecf, 0x4fbb, 0x4c84, {0x99, 0xa5, 0x10, 0x73, 0x40, 0x7, 0x6d, 0xb4}}
+gSaPolicyProtocolGuid = {0xc6aa1f27, 0x5597, 0x4802, {0x9f, 0x63, 0xd6, 0x28, 0x36, 0x59, 0x86, 0x35}}
+gGopPolicyProtocolGuid = {0xec2e931b, 0x3281, 0x48a5, {0x81, 0x07, 0xdf, 0x8a, 0x8b, 0xed, 0x3c, 0x5d}}
+
+##
+## PCH
+##
+gPchSpiProtocolGuid = { 0xc7d289, 0x1347, 0x4de0, {0xbf, 0x42, 0xe, 0x26, 0x9d, 0xe, 0xf3, 0x4a}}
+gWdtProtocolGuid = {0xb42b8d12, 0x2acb, 0x499a, {0xa9, 0x20, 0xdd, 0x5b, 0xe6, 0xcf, 0x09, 0xb1}}
+gEfiSmmSmbusProtocolGuid = {0x72e40094, 0x2ee1, 0x497a, {0x8f, 0x33, 0x4c, 0x93, 0x4a, 0x9e, 0x9c, 0x0c}}
+gPchSmmSpiProtocolGuid = {0x56521f06, 0xa62, 0x4822, {0x99, 0x63, 0xdf, 0x1, 0x9d, 0x72, 0xc7, 0xe1}}
+gPchSmmIoTrapControlGuid = {0x514d2afd, 0x2096, 0x4283, {0x9d, 0xa6, 0x70, 0x0c, 0xd2, 0x7d, 0xc7, 0xa5}}
+gPchTcoSmiDispatchProtocolGuid = {0x9e71d609, 0x6d24, 0x47fd, {0xb5, 0x72, 0x61, 0x40, 0xf8, 0xd9, 0xc2, 0xa4}}
+gPchPcieSmiDispatchProtocolGuid = {0x3e7d2b56, 0x3f47, 0x42aa, {0x8f, 0x6b, 0x22, 0xf5, 0x19, 0x81, 0x8d, 0xab}}
+gPchAcpiSmiDispatchProtocolGuid = {0xd52bb262, 0xf022, 0x49ec, {0x86, 0xd2, 0x7a, 0x29, 0x3a, 0x7a, 0x05, 0x4b}}
+gPchSmiDispatchProtocolGuid = {0xE6A81BBF, 0x873D, 0x47FD, {0xB6, 0xBE, 0x61, 0xB3, 0xE5, 0x72, 0x09, 0x93}}
+gPchEspiSmiDispatchProtocolGuid = {0xB3C14FF3, 0xBAE8, 0x456C, {0x86, 0x31, 0x27, 0xFE, 0x0C, 0xEB, 0x34, 0x0C}}
+gPchSmmPeriodicTimerControlGuid = {0x6906E93B, 0x603B, 0x4A0F, {0x86, 0x92, 0x83, 0x20, 0x04, 0xAA, 0xF2, 0xDB}}
+##
+## Silicon Policy
+##
+## Include/Protocol/SiPolicyProtocol.h
+gDxeSiPolicyProtocolGuid = { 0xeca27516, 0x306c, 0x4e28, { 0x8c, 0x94,
+0x4e, 0x52, 0x10, 0x96, 0x69, 0x5e }}
+
+[Ppis.common.Private]
+
+[Ppis]
+##
+## MdeModulePkg
+##
+gEdkiiPlatformSpecificResetFilterPpiGuid = { 0x8c9f4de3, 0x7b90,
+0x47ef, { 0x93, 0x8, 0x28, 0x7c, 0xec, 0xd6, 0x6d, 0xe8 } }
+
+##
+## SecurityPkg
+##
+gPeiTpmInitializationDonePpiGuid = {0xa030d115, 0x54dd, 0x447b, { 0x90,
+0x64, 0xf2, 0x6, 0x88, 0x3d, 0x7c, 0xcc}} ## ## Common ## ##
+Include/Ppi/SiPolicy.h gSiPolicyPpiGuid = {0xaebffa01, 0x7edc,
+0x49ff, {0x8d, 0x88, 0xcb, 0x84, 0x8c, 0x5e, 0x86, 0x70}} ##
+Include/Ppi/SiPolicy.h gSiPreMemPolicyPpiGuid = {0xc133fe57, 0x17c7,
+0x4b09, {0x8b, 0x3c, 0x97, 0xc1, 0x89, 0xd0, 0xab, 0x8d}} ## Silicon
+Initialization PPI is used to export End of Silicon init.
+gEndOfSiInitPpiGuid = {0xE2E3D5D1, 0x8356, 0x4F96, {0x9C, 0x9E, 0x2E, 0xC3, 0x48, 0x1D, 0xEA, 0x88}}
+gEfiEndOfPeiSignal2PpiGuid = {0x22918381, 0xd018, 0x4d7c, {0x9d, 0x62, 0xf5, 0xa5, 0x70, 0x1c, 0x66, 0x80}}
+gFspTempRamExitPpiGuid = {0xbc1cfbdb, 0x7e50, 0x42be, {0xb4, 0x87, 0x22, 0xe0, 0xa9, 0x0c, 0xb0, 0x52}}
+gFspmArchConfigPpiGuid = {0x824d5a3a, 0xaf92, 0x4c0c, {0x9f, 0x19, 0x19, 0x52, 0x6d, 0xca, 0x4a, 0xbb}}
+gSiPreMemDefaultPolicyInitPpiGuid = {0xfec36242, 0xf8d8, 0x4b43,
+{0x87, 0x94, 0x4f, 0x1f, 0x9f, 0x63, 0x8d, 0xdc}}
+gSiPreMemPolicyReadyPpiGuid = {0x85270bef, 0x6984, 0x4375, {0xa6, 0xea, 0xb5, 0xaa, 0x90, 0x6e, 0xdd, 0x4a}} gSiDefaultPolicyInitPpiGuid = {0xf69abf86, 0x4048, 0x44ef, { 0xa8, 0xef, 0x6c, 0x7f, 0x20, 0x4a, 0xc8, 0xda}}
+gSiPolicyReadyPpiGuid = {0xd570de8c, 0xb9c4, 0x4ffa, {0xad, 0xee, 0xa5, 0x82, 0x7c, 0xe3, 0x17, 0x79}}
+gPeiBeforeGraphicsDetectionPpiGuid = {0xa494060d, 0x98c5, 0x4948,
+{0x84, 0x57, 0x74, 0xd7, 0x1a, 0x3d, 0x0e, 0x85}}
+
+##
+## UEFI Variable Support (Override Until BP1.5) ##
+gEdkiiVariableStoragePpiGuid = { 0x90d915c5, 0xe4c1, 0x4da8, {0xa7,
+0x6f, 0x9, 0xe5, 0x78, 0x91, 0x65, 0x48}}
+gEdkiiVariableStorageSelectorPpiGuid = { 0x782546d1, 0x03ab, 0x41e4,
+{0xa0, 0x1d, 0x7a, 0x9b, 0x22, 0xba, 0x2e, 0x1e}}
+gReadOnlyVariablePreMemoryDescriptorPpiGuid = { 0xbe136fc9, 0xc277,
+0x4dd1, {0xbe, 0x42, 0xce, 0xf0, 0x9f, 0xf4, 0x3f, 0x55}}
+gEfiReadyToInstallEndOfPei2PpiGuid = {0xeef72924, 0x2db2, 0x4569, {
+0x86, 0x3f, 0xd4, 0x86, 0xae, 0x7a, 0xe4, 0x12}}
+
+##
+## SystemAgent
+##
+gEnablePeiGraphicsPpiGuid = {0x8e3bb474, 0x545, 0x4902, {0x86, 0xb0,
+0x6c, 0xb5, 0xe2, 0x64, 0xb4, 0xa5}}
+gPeiGraphicsFramebufferReadyPpiGuid = {0x590ad868, 0xb0b1, 0x4d20,
+{0x91, 0xff, 0xc2, 0xa9, 0xd6, 0x88, 0x81, 0x94}}
+gPeiGraphicsPlatformPpiGuid = {0x4eabcd09, 0x43d3, 0x4b4d, {0xb7, 0x3d, 0x43, 0xc8, 0xd9, 0x89, 0x99, 0x05}} ## X Compatibility support PPI gCompatibleMemoryInitPpiGuid = {0xca311f82, 0xf490, 0x4b12, {0x9e, 0xe1, 0x2b, 0x66, 0xa3, 0x6c, 0x3e, 0xa}}
+gVmdInitDonePpiGuid = {0x42a187c8, 0xca0a, 0x4750, {0x82, 0xfd, 0xc9, 0xa0, 0xd5, 0x9, 0xfe, 0xd1}}
+
+##
+## Cpu
+##
+gPeiCachePpiGuid = {0xC153205A, 0xE898, 0x4C24, {0x86, 0x89, 0xA4,
+0xB4, 0xBC, 0xC5, 0xC8, 0xA2}} gPeiTxtMemoryUnlockedPpiGuid =
+{0x38cdd10b, 0x767d, 0x4f6e, {0xa7, 0x44, 0x67, 0xee, 0x1d, 0xfe, 0x2f,
+0xa5}} gPeiTxtReadyToRunMemoryInitPpiGuid = {0x9ecafd30, 0x29e2,
+0x42f6, {0xba, 0xf3, 0x8b, 0x7d, 0xb8, 0xfe, 0x1f, 0x22}}
+gPeiReadyToInstallMpPpiGuid = { 0x1a266768, 0xfd43, 0x4e18, { 0xa8,
+0x8a, 0x35, 0xc7, 0x94, 0xc3, 0x91, 0x0e }}
+
+##
+## PCH
+##
+gWdtPpiGuid = {0xf38d1338, 0xaf7a, 0x4fb6, {0x91, 0xdb, 0x1a, 0x9c,
+0x21, 0x83, 0x57, 0x0d}} gPchSpiPpiGuid = {0xdade7ce3, 0x6971,
+0x4b75, {0x82, 0x5e, 0xe, 0xe0, 0xeb, 0x17, 0x72, 0x2d}}
+gPeiSmbusPolicyPpiGuid = {0x63b6e435, 0x32bc, 0x49c6, {0x81, 0xbd,
+0xb7, 0xa1, 0xa0, 0xfe, 0x1a, 0x6c}} gPchIoExpanderInfoPpiGuid = {
+0xf4a29776, 0x0ff9, 0x4b5c, { 0xb6, 0x9d, 0x88, 0x45, 0x09, 0x9b, 0x8d,
+0xa5 }}
+
+##
+## TCSS
+##
+gTcssPeiInitDonePpiGuid = {0x5ad291b8, 0xace4, 0x416a, {0xb7, 0x50,
+0x7, 0x63, 0x59, 0xfc, 0xc1, 0x5b}}
+
+##
+## ExtendedBiosDecodeReady PPI
+##
+gExtendedBiosDecodeReadyPpiGuid = {0x54b522bc, 0xbef2, 0x419b, {0xa9,
+0x66, 0x7e, 0xc4, 0xf0, 0x15, 0xe8, 0x21}}
+
+##
+## FSP##
+gFsptUpdLocationPpiGuid = { 0xfc4dd4f2, 0x179e, 0x41f8, { 0x9d, 0x6d, 0xfa, 0xd6, 0xf9, 0xd7, 0xb8, 0xb9 }}
+
+[LibraryClasses]
+## @libraryclass
+## Common
+##
+SiPolicyLib|Include/Library/SiPolicyLib.h
+PeiPolicyUpdateLib|Include/Library/PeiSiPolicyUpdateLib.h
+ProcessorTraceMemoryAllocationLib|Include/Library/ProcessorTraceMemoryA
+ProcessorTraceMemoryAllocationLib|llocationLib.h
+PlatformSecLib|Include/Library/SecPlatformLib.h
+SiAssertErrorHandlerLib|Include/Library/SiAssertErrorHandlerLib.h
+SiConfigBlockLib|Include/Library/SiConfigBlockLib.h
+## @libraryclass
+## SampleCode
+##
+## CPU
+##
+CpuPlatformLib|Cpu/Include/Library/CpuPlatformLib.h
+
+
+## @libraryclass
+## Pch
+##
+GpioLib|Include/Library/GpioLib.h
+GpioLib|Include/Library/GpioNativeLib.h
+PchCycleDecodingLib|Pch/Include/Library/PchCycleDecodingLib.h
+EspiLib|Include/Library/EspiLib.h
+PchInfoLib|Pch/Include/Library/PchInfoLib.h
+PchPcieRpLib|Include/Library/PchPcieRpLib.h
+PchPcrLib|Include/Library/PchPcrLib.h
+PchSbiAccessLib|IpBlock/P2sb/IncludePrivate/Library/PchSbiAccessLib.h
+PchPciBdfLib|Pch/Include/Library/PchPciBdfLib.h
+PchRasLib|Pch/Include/Library/PchRasLib.h
+PchRtcLib|Pch/Include/Library/PchRtcLib.h
+ResetSystemLib|Include/Library/ResetSystemLib.h
+## @libraryclass
+## Sa
+##
+DxeSaPolicyLib|SystemAgent/Include/Library/DxeSaPolicyLib.h
+## @libraryclass
+## Fru
+##
+CpuInfoFruLib|Cpu/IncludePrivate/Library/CpuInfoFruLib.h
+## @libraryclass
+## IpBlock
+##
+PmcPrivateLib|IpBlock/Pmc/IncludePrivate/Library/PmcPrivateLib.h
+IehInitLib|IpBlock/Ieh/IncludePrivate/Library/PeiIehInitLib.h
+PeiIehPolicyLib|IpBlock/Ieh/IncludePrivate/Library/PeiIehPolicyLib.h
+DxeGraphicsPolicyLib|IpBlock/Graphics/IncludePrivate/Library/DxeGraphic
+DxeGraphicsPolicyLib|sPolicyLib.h
+DxeIgdOpRegionInitLib|IpBlock/Graphics/IncludePrivate/Library/DxeIgdOpR
+DxeIgdOpRegionInitLib|egionInitLib.h
+PchDmiLib|IpBlock/PchDmi/IncludePrivate/Library/PchDmiLib.h
+P2SbSidebandAccessLib|IpBlock/P2sb/IncludePrivate/Library/P2SbSidebandA
+P2SbSidebandAccessLib|ccessLib.h
+SpiCommonLib|IpBlock/Spi/IncludePrivate/Library/SpiCommonLib.h
+GpioHelpersLib|IpBlock/Gpio/IncludePrivate/Library/GpioHelpersLib.h
+GpioPrivateLib|IpBlock/Gpio/IncludePrivate/Library/GpioPrivateLib.h
+PeiDmiSipInitLib|IpBlock/PcieRp/IncludePrivate/Library/PeiDmiSipInitLib
+PeiDmiSipInitLib|.h
+PeiEnterprisePcieRpInitLib|IpBlock/PcieRp/IncludePrivate/Library/PeiEnt
+PeiEnterprisePcieRpInitLib|erprisePcieRpInitLib.h
+PeiDpInInitLib|IpBlock/Tcss/IncludePrivate/Library/PeiDpInInitLib.h
+CpuPcieRpLib|IpBlock/CpuPcieRp/Include/Library/CpuPcieRpLib.h
+GpioGsxLib|Include/Library/GpioGsxLib.h
+GraphicsInfoLib|Include/Library/GraphicsInfoLib.h
+HeciCommonLib|Include/Library/HeciCommonLib.h
+HeciConfigureLib|Include/Library/HeciConfigureLib.h
+HeciTraceLib|Include/Library/HeciTraceLib.h
+HeciTransportCoreLib|Include/Library/HeciTransportCoreLib.h
+OcPlatformLib|Include/Library/OcPlatformLib.h
+PeiSpsPreMemPolicyLib|Include/Library/PeiSpsPreMemPolicyLib.h
+PmcLib|Include/Library/PmcLib.h
+PmcSsramLib|Include/Library/PmcSsramLib.h
+SpiLib|Include/Library/SpiLib.h
+SpsDxeLib|Include/Library/SpsDxeLib.h
+SpsGetDxeConfigBlockLib|Include/Library/SpsGetDxeConfigBlock.h
+MeGetPeiConfigBlock|Include/Library/MeGetConfigBlock.h
+## @libraryclass
+## Fsp
+##
+FspHelperLib|Fsp/Include/Library/FspHelperLib.h
+FspInfoLib|Fsp/Include/Library/FspInfoLib.h
+FspSerialIoUartDebugHelperLib|Fsp/Include/Library/FspSerialIoUartDebugH
+FspSerialIoUartDebugHelperLib|elperLib.h
+
+
+CpuPcieInfoFruLib|Fru/AdlCpu/Include/Library/CpuPcieInfoFruLib.h
+
+[PcdsFixedAtBuild]
+## From MdeModulePkg.dec
+## Progress Code for S3 Suspend start.
+## PROGRESS_CODE_S3_SUSPEND_START = (EFI_SOFTWARE_SMM_DRIVER | (EFI_OEM_SPECIFIC | 0x00000000)) = 0x03078000
+gSiPkgTokenSpaceGuid.PcdProgressCodeS3SuspendStart|0x03078000|UINT32|0x
+30001032
+## Progress Code for S3 Suspend end.
+## PROGRESS_CODE_S3_SUSPEND_END = (EFI_SOFTWARE_SMM_DRIVER | (EFI_OEM_SPECIFIC | 0x00000001)) = 0x03078001
+gSiPkgTokenSpaceGuid.PcdProgressCodeS3SuspendEnd|0x03078001|UINT32|0x30
+001033
+##
+## PcdNemCodeCacheBase is usally the same as PEI FV Base address, ##
+FLASH_BASE+FLASH_REGION_FV_RECOVERY_OFFSET from PlatformPkg.fdf.
+##
+## Restriction:
+## 1) PcdNemCodeCacheBase - (PcdTemporaryRamBase + PcdTemporaryRamSize)
+>= 4K ## 2) PcdTemporaryRamBase >= 4G - 64M ##
+gSiPkgTokenSpaceGuid.PcdNemCodeCacheBase|0xFFF80000|UINT32|0x20000009
+##
+## NemCodeCacheSize is usally the same as PEI FV Size, ##
+FLASH_REGION_FV_RECOVERY_SIZE from PlatformPkg.fdf.
+##
+## Restriction:
+## 1) PcdNemTotalCacheSize = NemCodeCacheSize + PcdTemporaryRamSize ##
+<= Maximun CPU NEM total size (Code + Data) ## = LLC size - 0.5M ## 2)
+PcdTemporaryRamSize <= Maximum CPU NEM data size ## = MLC size ##
+NOTE: The size restriction may be changed in next generation processor.
+## Please refer to Processor BWG for detail.
+##
+gSiPkgTokenSpaceGuid.PcdBiosAreaBaseAddress|0xFF800000|UINT32|0x1000000
+1
+gSiPkgTokenSpaceGuid.PcdBiosSize|0x00800000|UINT32|0x10000002
+gSiPkgTokenSpaceGuid.PcdTemporaryRamBase|0xfef00000|UINT32|0x00010028
+gSiPkgTokenSpaceGuid.PcdTemporaryRamSize|0x2000|UINT32|0x00010029
+gSiPkgTokenSpaceGuid.PcdTopMemoryCacheSize|0x0|UINT32|0x0001002A
+gSiPkgTokenSpaceGuid.PcdFlashMicrocodeOffset|0x00000060|UINT32|0x300000
+13
+
+gSiPkgTokenSpaceGuid.PcdFspWrapperEnable |FALSE|BOOLEAN|0x3000000F
+
+
+#
+# PCD is using for SOC core boot
+#
+
+#
+# PCD is using for AlderLakeL P/M/S
+# True: ADL-P/M
+# False: ADL-S
+#
+gSiPkgTokenSpaceGuid.PcdAdlLpSupport|TRUE|BOOLEAN|0x30000014
+
+#
+# PCD is using for AlderLakeL S
+#
+gSiPkgTokenSpaceGuid.PcdAdlSSupport|FALSE|BOOLEAN|0x30000015
+
+##
+## PcdEfiGcdAllocateType is using for EFI_GCD_ALLOCATE_TYPE selection
+## value of the struct ## 0x00 EfiGcdAllocateAnySearchBottomUp ##
+0x01 EfiGcdAllocateMaxAddressSearchBottomUp
+## 0x03 EfiGcdAllocateAnySearchTopDown ## 0x04
+EfiGcdAllocateMaxAddressSearchTopDown
+##
+## below value should not using in this situation ## 0x05
+EfiGcdMaxAllocateType : design for max value of struct ## 0x02
+EfiGcdAllocateAddress : design for speccification address allocate ##
+gSiPkgTokenSpaceGuid.PcdEfiGcdAllocateType|0x01|UINT8|0x40000000
+
+
+##
+## Those PCDs are used to control build process.
+##
+gSiPkgTokenSpaceGuid.PcdSmmVariableEnable |TRUE |BOOLEAN|0xF0000002
+gSiPkgTokenSpaceGuid.PcdAcpiEnable |TRUE |BOOLEAN|0xF0000009
+gSiPkgTokenSpaceGuid.PcdSourceDebugEnable |FALSE|BOOLEAN|0xF000000B
+gSiPkgTokenSpaceGuid.PcdTxtEnable |FALSE|BOOLEAN|0xF000000D
+
+gSiPkgTokenSpaceGuid.PcdSmbiosEnable |TRUE |BOOLEAN|0xF0000014
+gSiPkgTokenSpaceGuid.PcdIgdEnable |TRUE |BOOLEAN|0xF000001A
+gSiPkgTokenSpaceGuid.PcdSaDmiEnable |TRUE |BOOLEAN|0xF000001C
+gSiPkgTokenSpaceGuid.PcdBdatEnable |TRUE |BOOLEAN|0xF0000023
+gSiPkgTokenSpaceGuid.PcdOptimizeCompilerEnable |TRUE |BOOLEAN|0xF0000024
+gSiPkgTokenSpaceGuid.PcdPeiDisplayEnable |TRUE |BOOLEAN|0xF0000025
+gSiPkgTokenSpaceGuid.PcdSerialIoUartEnable |TRUE |BOOLEAN|0xF0000033
+gSiPkgTokenSpaceGuid.PcdSiCatalogDebugEnable |FALSE|BOOLEAN|0xF0000037
+
+gSiPkgTokenSpaceGuid.PcdCpuPcieEnable |TRUE |BOOLEAN|0xF0000043
+gSiPkgTokenSpaceGuid.PcdMrcTraceMessageSupported |TRUE |BOOLEAN|0xF0000045
+
+[PcdsDynamic, PcdsPatchableInModule]
+## Default OEM Table ID for ACPI table creation, it is "EDK2 ".
+gSiPkgTokenSpaceGuid.PcdAcpiDefaultOemTableId|0x20202020324B4445|UINT64
+|0x30001035
+
+[PcdsFixedAtBuild, PcdsPatchableInModule] ## This value is used to set
+the base address of PCH devices
+gSiPkgTokenSpaceGuid.PcdSmbusBaseAddress|0x0000EFA0|UINT16|0x00010031
+gSiPkgTokenSpaceGuid.PcdTcoBaseAddress|0x0400|UINT16|0x00010033
+gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress|0x1800|UINT16|0x00010035
+
+##
+## FSP
+##
+## The PCD value here are either dummy or generic for all platforms ##
+Some of them are expected to have different value in platform FSP package DSC.
+##
+## Examples:
+## PcdFspImageIdString, PcdFspVersionRevision, PcdFspVersionBuild, PcdFspVersionMinor
+##
+gSiPkgTokenSpaceGuid.PcdFspImageIdString |0x0|UINT64|0x0001005A
+gSiPkgTokenSpaceGuid.PcdFspVersionRevision |0x00|UINT8|0x0001005C
+gSiPkgTokenSpaceGuid.PcdFspVersionBuild |0x00|UINT8|0x0001005D
+gSiPkgTokenSpaceGuid.PcdFspVersionMinor |0x00|UINT8|0x0001005E
+
+
+## This value is used to set the base address of MCH
+gSiPkgTokenSpaceGuid.PcdMchBaseAddress|0xFEDC0000|UINT64|0x00010030
+
+##
+## Allocate 56 KB [0x2000..0xFFFF] of I/O space for Pci Devices ## If
+PcdPciReservedMemLimit =0 Pci Reserved default MMIO Limit is 0xE0000000 else use PcdPciReservedMemLimit .
+##
+gSiPkgTokenSpaceGuid.PcdPciReservedMemLimit |0x0000 |UINT32|0x00010043
+
+##
+## Default 8MB TSEG for Release build BIOS when IED disabled (Also a
+default) ##
+gSiPkgTokenSpaceGuid.PcdTsegSize|0x00800000|UINT32|0x00010046
+
+##
+## Silicon Reference Code versions
+##
+gSiPkgTokenSpaceGuid.PcdSiliconInitVersionMajor |0x0C|UINT8|0x00010049
+
+##Minor:the program that supported by same core generation.
+gSiPkgTokenSpaceGuid.PcdSiliconInitVersionMinor |0x00|UINT8|0x00010050
+
+##Revision:Weekly build number
+gSiPkgTokenSpaceGuid.PcdSiliconInitVersionRevision|0x82|UINT8|0x0001005
+1
+
+##Build[7:4]:Daily build number.
+##Build[3:0]:Patch build number.
+
+gSiPkgTokenSpaceGuid.PcdSiliconInitVersionBuild |0x30|UINT8|0x00010052
+
+
+
+##
+## This PCD specifies the base address of the HPET timer.
+## The acceptable values are 0xFED00000, 0xFED01000, 0xFED02000, and
+0xFED03000 ##
+gSiPkgTokenSpaceGuid.PcdSiHpetBaseAddress |0xFED00000|UINT32|0x00010057
+##
+## This PCD specifies the base address of the IO APIC.
+## The acceptable values are 0xFECxx000.
+##
+gSiPkgTokenSpaceGuid.PcdSiIoApicBaseAddress
+|0xFEC00000|UINT32|0x00010058
+
+[PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx]
+## ## SerialIo Uart Configuration ##
+gSiPkgTokenSpaceGuid.PcdSerialIoUartDebugEnable |0 |UINT8 |0x00210001 # 0:Disable, 1:Enable and Initialize, 2:Enable without Initializing
+gSiPkgTokenSpaceGuid.PcdSerialIoUartNumber |2 |UINT8 |0x00210002
+gSiPkgTokenSpaceGuid.PcdSerialIoUartMode |2 |UINT8 |0x00210003 # 0:Disabled, 1:Enabled, 2:Hidden, 3:COM, 4:SkipInit
+gSiPkgTokenSpaceGuid.PcdSerialIoUartBaudRate |115200 |UINT32|0x00210004 # 0:Default, Max:6000000
+gSiPkgTokenSpaceGuid.PcdSerialIoUartParity |1 |UINT8 |0x00210008 # 0:DefaultParity, 1:NoParity, 2:EvenParity, 3:OddParity
+gSiPkgTokenSpaceGuid.PcdSerialIoUartDataBits |8 |UINT8 |0x00210009 # 0:Default, 5,6,7,8
+gSiPkgTokenSpaceGuid.PcdSerialIoUartStopBits |1 |UINT8 |0x0021000A # 0:DefaultStopBits, 1:OneStopBit, 2:OneFiveStopBits, 3:TwoStopBits
+gSiPkgTokenSpaceGuid.PcdSerialIoUartAutoFlow |0 |UINT8 |0x0021000B # 0:No HW flow control, Only RX/TX Enabled; 1:HW Flow Control On, Rts/Cts lines enabled;
+gSiPkgTokenSpaceGuid.PcdSerialIoUartRxPinMux |0x0 |UINT32|0x0021000C # Pin muxing config for UART Rx pin
+gSiPkgTokenSpaceGuid.PcdSerialIoUartTxPinMux |0x0 |UINT32|0x00210010 # Pin muxing config for UART Tx pin
+gSiPkgTokenSpaceGuid.PcdSerialIoUartRtsPinMux |0x0 |UINT32|0x00210014 # Pin muxing config for UART Rts pin
+gSiPkgTokenSpaceGuid.PcdSerialIoUartCtsPinMux |0x0 |UINT32|0x00210018 # Pin muxing config for UART Cts pin
+gSiPkgTokenSpaceGuid.PcdSerialIoUartDebugMmioBase |0xFE036000
+|UINT32|0x0021001C # PcdSerialIoUartMode = Enabled, need to assign MMIO
+Resource in SEC/PEI Phase
+
+gSiPkgTokenSpaceGuid.PcdLpcUartDebugEnable |0x1 |UINT8 |0x00210026 # 0:Disable, 1:Enable
+gSiPkgTokenSpaceGuid.PcdDebugInterfaceFlags |0x12 |UINT8 |0x00210027 # BIT0-RAM, BIT1-UART, BIT3-USB3, BIT4-Serial IO, BIT5-TraceHub, BIT2 - Not used.
+gSiPkgTokenSpaceGuid.PcdSerialDebugLevel |0x3 |UINT8 |0x00210028 # {0:Disable, 1:Error Only, 2:Error and Warnings, 3:Load Error Warnings and Info, 4:Load Error Warnings and Info, 5:Load Error Warnings Info and Verbose
+gSiPkgTokenSpaceGuid.PcdIsaSerialUartBase |0x0 |UINT8 |0x00210029 # 0:0x3F8, 1:0x2F8
+
+
+##
+## SerialIo 2nd Uart Configuration
+##
+gSiPkgTokenSpaceGuid.PcdSerialIo2ndUartEnable |0 |UINT8 |0x0021002A # 0:Disable, 1:Enable and Initialize, 2:Enable without Initializing
+gSiPkgTokenSpaceGuid.PcdSerialIo2ndUartNumber |2 |UINT8 |0x0021002B
+gSiPkgTokenSpaceGuid.PcdSerialIo2ndUartMode |2 |UINT8 |0x0021002C # 0:Disabled, 1:Enabled, 2:Hidden, 3:COM, 4:SkipInit
+gSiPkgTokenSpaceGuid.PcdSerialIo2ndUartBaudRate |115200 |UINT32|0x0021002D # 0:Default, Max:6000000
+gSiPkgTokenSpaceGuid.PcdSerialIo2ndUartParity |1 |UINT8 |0x00210031 # 0:DefaultParity, 1:NoParity, 2:EvenParity, 3:OddParity
+gSiPkgTokenSpaceGuid.PcdSerialIo2ndUartDataBits |8 |UINT8 |0x00210032 # 0:Default, 5,6,7,8
+gSiPkgTokenSpaceGuid.PcdSerialIo2ndUartStopBits |1 |UINT8 |0x00210033 # 0:DefaultStopBits, 1:OneStopBit, 2:OneFiveStopBits, 3:TwoStopBits
+gSiPkgTokenSpaceGuid.PcdSerialIo2ndUartAutoFlow |0 |UINT8 |0x00210034 # 0:No HW flow control, Only RX/TX Enabled; 1:HW Flow Control On, Rts/Cts lines enabled;
+gSiPkgTokenSpaceGuid.PcdSerialIo2ndUartRxPinMux |0x0 |UINT32|0x00210035 # Pin muxing config for UART Rx pin
+gSiPkgTokenSpaceGuid.PcdSerialIo2ndUartTxPinMux |0x0 |UINT32|0x00210039 # Pin muxing config for UART Tx pin
+gSiPkgTokenSpaceGuid.PcdSerialIo2ndUartRtsPinMux |0x0 |UINT32|0x0021003D # Pin muxing config for UART Rts pin
+gSiPkgTokenSpaceGuid.PcdSerialIo2ndUartCtsPinMux |0x0 |UINT32|0x00210041 # Pin muxing config for UART Cts pin
+gSiPkgTokenSpaceGuid.PcdSerialIo2ndUartMmioBase |0xFE034000
+|UINT32|0x00210045 # PcdSerialIoUartMode = Enabled, need to assign MMIO
+Resource in SEC/PEI Phase
+
+##
+## PCI Express MMIO region length
+## Valid settings: 0x20000000/512MB, 0x10000000/256MB, 0x8000000/128MB,
+0x4000000/64MB ##
+gSiPkgTokenSpaceGuid.PcdPciExpressRegionLength|0x10000000|UINT32|0x0020
+0001
+##
+## Typically this should be the same with gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress.
+## This PCD is added for supporting different PCD type in different phases.
+##
+gSiPkgTokenSpaceGuid.PcdSiPciExpressBaseAddress
+|0xC0000000|UINT64|0x00200002 ## ## PCI Express MMIO temporary region
+length in SEC phase.
+## Valid settings: 0x20000000/512MB, 0x10000000/256MB, 0x8000000/128MB,
+0x4000000/64MB ##
+gSiPkgTokenSpaceGuid.PcdTemporaryPciExpressRegionLength|0x10000000|UINT
+32|0x00200005
--
2.36.1.windows.1
-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#108728): https://edk2.groups.io/g/devel/message/108728
Mute This Topic: https://groups.io/mt/101373955/7686176
Group Owner: devel+owner@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [rebecca@openfw.io]
-=-=-=-=-=-=-=-=-=-=-=-
^ permalink raw reply related [flat|nested] 41+ messages in thread
* Re: [edk2-devel] [PATCH v2 01/10] AlderlakeSiliconPkg/IpBlock: Add CpuPcieRp, Espi, Gpio components
2023-09-15 4:45 [edk2-devel] [PATCH v2 01/10] AlderlakeSiliconPkg/IpBlock: Add CpuPcieRp, Espi, Gpio components Saloni Kasbekar
` (9 preceding siblings ...)
2023-09-15 5:42 ` [edk2-devel] [PATCH v2 01/10] AlderlakeSiliconPkg/IpBlock: Add CpuPcieRp, Espi, Gpio components Chaganty, Rangasai V
@ 2023-09-15 23:56 ` Nate DeSimone
2023-09-16 0:26 ` Nate DeSimone
11 siblings, 0 replies; 41+ messages in thread
From: Nate DeSimone @ 2023-09-15 23:56 UTC (permalink / raw)
To: Kasbekar, Saloni, devel@edk2.groups.io
Cc: Chaganty, Rangasai V, Chuang, Rosen
Hi Saloni,
For a patch series this large, please send a cover letter for it in the future.
Acked-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
-----Original Message-----
From: Kasbekar, Saloni <saloni.kasbekar@intel.com>
Sent: Thursday, September 14, 2023 9:46 PM
To: devel@edk2.groups.io
Cc: Kasbekar, Saloni <saloni.kasbekar@intel.com>; Chaganty, Rangasai V <rangasai.v.chaganty@intel.com>; Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>; Chuang, Rosen <rosen.chuang@intel.com>
Subject: [PATCH v2 01/10] AlderlakeSiliconPkg/IpBlock: Add CpuPcieRp, Espi, Gpio components
Adds the following modules:
- IpBlock/CpuPcieRp/Include
- IpBlock/Espi/Library
- IpBlock/Gpio/IncludePrivate
- IpBlock/Gpio/Library
- IpBlock/Gpio/LibraryPrivate
Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Rosen Chuang <rosen.chuang@intel.com>
Signed-off-by: Saloni Kasbekar <saloni.kasbekar@intel.com>
---
.../IpBlock/CpuPcieRp/Include/CpuPcieInfo.h | 25 +
.../Espi/Library/PeiDxeSmmEspiLib/EspiLib.c | 58 ++
.../PeiDxeSmmEspiLib/PeiDxeSmmEspiLib.inf | 38 ++
.../IncludePrivate/Library/GpioHelpersLib.h | 50 ++
.../IncludePrivate/Library/GpioNativePads.h | 245 ++++++++
.../IncludePrivate/Library/GpioPrivateLib.h | 350 +++++++++++
.../Gpio/Library/PeiDxeSmmGpioLib/GpioInit.c | 546 ++++++++++++++++++
.../Gpio/Library/PeiDxeSmmGpioLib/GpioLib.c | 522 +++++++++++++++++
.../Library/PeiDxeSmmGpioLib/GpioLibrary.h | 29 +
.../Library/PeiDxeSmmGpioLib/GpioNativeLib.c | 177 ++++++
.../PeiDxeSmmGpioLib/PeiDxeSmmGpioLib.inf | 44 ++
.../BaseGpioHelpersLibNull.c | 51 ++
.../BaseGpioHelpersLibNull.inf | 25 +
.../GpioNativePrivateLibInternal.h | 48 ++
.../PeiDxeSmmGpioPrivateLib/GpioPrivateLib.c | 267 +++++++++
.../GpioPrivateLibPch.c | 172 ++++++
.../GpioPrivateLibVer2.c | 81 +++
.../PeiDxeSmmGpioPrivateLibVer2.inf | 40 ++
.../PeiGpioHelpersLib/PeiGpioHelpersLib.c | 218 +++++++
.../PeiGpioHelpersLib/PeiGpioHelpersLib.inf | 46 ++
20 files changed, 3032 insertions(+)
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/CpuPcieRp/Include/CpuPcieInfo.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Espi/Library/PeiDxeSmmEspiLib/EspiLib.c
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Espi/Library/PeiDxeSmmEspiLib/PeiDxeSmmEspiLib.inf
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/IncludePrivate/Library/GpioHelpersLib.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/IncludePrivate/Library/GpioNativePads.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/IncludePrivate/Library/GpioPrivateLib.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/Library/PeiDxeSmmGpioLib/GpioInit.c
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/Library/PeiDxeSmmGpioLib/GpioLib.c
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/Library/PeiDxeSmmGpioLib/GpioLibrary.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/Library/PeiDxeSmmGpioLib/GpioNativeLib.c
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/Library/PeiDxeSmmGpioLib/PeiDxeSmmGpioLib.inf
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/BaseGpioHelpersLibNull/BaseGpioHelpersLibNull.c
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/BaseGpioHelpersLibNull/BaseGpioHelpersLibNull.inf
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiDxeSmmGpioPrivateLib/GpioNativePrivateLibInternal.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiDxeSmmGpioPrivateLib/GpioPrivateLib.c
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiDxeSmmGpioPrivateLib/GpioPrivateLibPch.c
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiDxeSmmGpioPrivateLib/GpioPrivateLibVer2.c
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiDxeSmmGpioPrivateLib/PeiDxeSmmGpioPrivateLibVer2.inf
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiGpioHelpersLib/PeiGpioHelpersLib.c
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiGpioHelpersLib/PeiGpioHelpersLib.inf
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/CpuPcieRp/Include/CpuPcieInfo.h b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/CpuPcieRp/Include/CpuPcieInfo.h
new file mode 100644
index 0000000000..a6f8b16d10
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/CpuPcieRp/Include/CpuPcieInfo.h
@@ -0,0 +1,25 @@
+/** @file
+ This file contains definitions of PCIe controller information
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _CPU_PCIE_INFO_H_
+#define _CPU_PCIE_INFO_H_
+
+#define PCIE_HWEQ_COEFFS_MAX 5
+
+
+//
+// SA PCI Express* Port configuration
+//
+
+#define CPU_PCIE_MAX_ROOT_PORTS 4
+#define CPU_PCIE_MAX_CONTROLLERS 3
+
+#define SA_PEG_MAX_FUN 0x04
+#define SA_PEG_MAX_LANE 0x14
+
+
+
+#endif
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Espi/Library/PeiDxeSmmEspiLib/EspiLib.c b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Espi/Library/PeiDxeSmmEspiLib/EspiLib.c
new file mode 100644
index 0000000000..2e4d1375ca
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Espi/Library/PeiDxeSmmEspiLib/EspiLib.c
@@ -0,0 +1,58 @@
+/** @file
+ This file contains routines for eSPI
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#include <Base.h>
+#include <Uefi/UefiBaseType.h>
+#include <Library/IoLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/EspiLib.h>
+#include <Library/PchPcrLib.h>
+#include <Library/PchInfoLib.h>
+#include <Library/TimerLib.h>
+#include <PchLimits.h>
+#include <Register/PchPcrRegs.h>
+#include <Register/PchRegsLpc.h>
+
+
+/**
+ Checks if second device capability is enabled
+
+ @retval TRUE There's second device
+ @retval FALSE There's no second device
+**/
+BOOLEAN
+IsEspiSecondSlaveSupported (
+ VOID
+ )
+{
+ return ((PchPcrRead32 (PID_ESPISPI, R_ESPI_PCR_SOFTSTRAPS) & B_ESPI_PCR_SOFTSTRAPS_CS1_EN) != 0);
+}
+
+
+/**
+ Is eSPI enabled in strap.
+
+ @retval TRUE Espi is enabled in strap
+ @retval FALSE Espi is disabled in strap
+**/
+BOOLEAN
+IsEspiEnabled (
+ VOID
+ )
+{
+ return (PchPcrRead32 (PID_ESPISPI, R_ESPI_PCR_CFG_VAL) & B_ESPI_PCR_CFG_VAL_ESPI_EN) != 0;
+}
+
+typedef enum {
+ EspiSlaveOperationConfigRead,
+ EspiSlaveOperationConfigWrite,
+ EspiSlaveOperationStatusRead,
+ EspiSlaveOperationInBandReset
+} ESPI_SLAVE_OPERATION;
+
+
+
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Espi/Library/PeiDxeSmmEspiLib/PeiDxeSmmEspiLib.inf b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Espi/Library/PeiDxeSmmEspiLib/PeiDxeSmmEspiLib.inf
new file mode 100644
index 0000000000..e8db1e4e8d
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Espi/Library/PeiDxeSmmEspiLib/PeiDxeSmmEspiLib.inf
@@ -0,0 +1,38 @@
+## @file
+# Component description file for the PeiDxeSmmPchEspiLib
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+
+[Defines]
+INF_VERSION = 0x00010017
+BASE_NAME = PeiDxeSmmEspiLib
+FILE_GUID = 7F25F990-7989-4413-B414-1EDE557E9389
+VERSION_STRING = 1.0
+MODULE_TYPE = BASE
+LIBRARY_CLASS = EspiLib
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = IA32 X64 IPF EBC
+#
+
+
+
+[LibraryClasses]
+BaseLib
+IoLib
+DebugLib
+PchPcrLib
+TimerLib
+
+
+[Packages]
+MdePkg/MdePkg.dec
+AlderlakeSiliconPkg/SiPkg.dec
+
+
+[Sources]
+EspiLib.c
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/IncludePrivate/Library/GpioHelpersLib.h b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/IncludePrivate/Library/GpioHelpersLib.h
new file mode 100644
index 0000000000..cf67c81ed0
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/IncludePrivate/Library/GpioHelpersLib.h
@@ -0,0 +1,50 @@
+/** @file
+ Header file for GPIO Helpers Lib implementation.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _GPIO_HELPERS_LIB_H_
+#define _GPIO_HELPERS_LIB_H_
+
+#include <Library/GpioConfig.h>
+
+/**
+ This procedure stores GPIO group data about pads which PadConfig needs to be unlocked.
+
+ @param[in] GroupIndex GPIO group index
+ @param[in] DwNum DWORD index for a group.
+ For group which has less then 32 pads per group DwNum must be 0.
+ @param[in] PadsToLock DWORD bitmask for pads which are going to be left unlocked
+ Bit position - PadNumber
+ Bit value - 0: Skip, 1: Leave unlocked
+
+ @retval Status
+**/
+EFI_STATUS
+GpioStoreGroupDwUnlockPadConfigData (
+ IN UINT32 GroupIndex,
+ IN UINT32 DwNum,
+ IN UINT32 UnlockedPads
+ );
+
+/**
+ This procedure stores GPIO group data about pads which Output state needs to be unlocked.
+
+ @param[in] GroupIndex GPIO group index
+ @param[in] DwNum DWORD index for a group.
+ For group which has less then 32 pads per group DwNum must be 0.
+ @param[in] PadsToLock DWORD bitmask for pads which are going to be left unlocked
+ Bit position - PadNumber
+ Bit value - 0: Skip, 1: Leave unlocked
+
+ @retval Status
+**/
+EFI_STATUS
+GpioStoreGroupDwUnlockOutputData (
+ IN UINT32 GroupIndex,
+ IN UINT32 DwNum,
+ IN UINT32 UnlockedPads
+ );
+
+#endif // _GPIO_HELPERS_LIB_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/IncludePrivate/Library/GpioNativePads.h b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/IncludePrivate/Library/GpioNativePads.h
new file mode 100644
index 0000000000..dbd13963fa
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/IncludePrivate/Library/GpioNativePads.h
@@ -0,0 +1,245 @@
+/** @file
+ Header file for GPIO Native pads support
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _GPIO_NATIVE_PADS_H_
+#define _GPIO_NATIVE_PADS_H_
+
+//
+// GpioPad can contain additional information used to provide data on
+// native functions. Please refer to description of GPIO_NATIVE_PAD
+//
+// FFFF CCCC TTTG GGGG TTTT TTTP PPPP PPPP
+//
+// F - 2^4 = 16, native function number
+// C - 2^4 = 16, chipset ID
+// T - 2^10 = 1024 , abstract type representing native mode of a pad (e.g. SERIALIO_UART2_TX)
+// G - 2^5 = 32, group
+// P - 2^9 = 512, pad number
+//
+// F & T contain additional optional settings used for native pads
+//
+#define GPIO_NATIVE_PAD_DEF(GpioNativePad, NativeMode, NativeFunction) \
+ (GpioNativePad | (NativeMode << 28) | ((NativeFunction & 0x7F) << 9) | ((NativeFunction & 0x380) << 14))
+
+#define GPIO_NATIVE_GET_FUNCTION(GpioNativePad) ((((GpioNativePad) & 0xFE00) >> 9) | (((GpioNativePad) & 0xE00000) >> 14))
+#define GPIO_NATIVE_GET_PAD_FN(GpioNativePad) (((GpioNativePad) >> 28) & 0xF)
+#define GPIO_NATIVE_GET_PAD_MODE(GpioNativePad) ((GPIO_NATIVE_GET_PAD_FN(GpioNativePad) << 1) | 1)
+#define GPIO_NATIVE_TO_GPIO_PAD(GpioNativePad) (GpioNativePad & 0xF1F01FF)
+
+//
+// Below defines and macros are used to build abstract type
+// to help encode native pin information in GPIO_PAD
+//
+
+//
+// Macro used to define GPIO native function.
+// <Min,Max> defines range that can be used to encode given native signal.
+// Numbering must be unique and cannot overlap.
+// If there are many instances of similar signal (e.g. per controller) the lower
+// word will store value for a given instance in the form: Min + Instance
+// Upper word (Max) is left untouched and later used for verification
+//
+#define GPIO_NATIVE_FUNCTION_DEF(Min, Max) (((Max) << 16) + (Min))
+#define GPIO_NATIVE_FUNCTION_GET_MAX(NativeFunction) (((NativeFunction) >> 16) & 0xFFFF)
+#define GPIO_NATIVE_FUNCTION_GET_VALUE(NativeFunction) ((NativeFunction) & 0xFFFF)
+
+//
+// Macro GPIO_NATIVE_FUNCTION_GET_SIGNAL is created as synonym to macro GPIO_NATIVE_FUNCTION_GET_MAX
+// GPIO_NATIVE_FUNCTION_GET_SIGNAL used with below defines is more descriptive and easier to read
+// ex.
+// - GPIO_NATIVE_FUNCTION_GET_SIGNAL(GPIO_SERIAL_IO_UART_RX)
+// - GPIO_NATIVE_FUNCTION_GET_SIGNAL(GPIO_ISH_GP)
+// - ...
+//
+#define GPIO_NATIVE_FUNCTION_GET_SIGNAL(NativeFunction) (GPIO_NATIVE_FUNCTION_GET_MAX(NativeFunction))
+
+//
+// GPIO native modes
+// Those defines are internal to this header.
+// GPIO_FUNCTION_<IP>_<signal>(index) defines should be used by other modules instead.
+//
+#define GPIO_SERIAL_IO_UART_RX GPIO_NATIVE_FUNCTION_DEF(1,8)
+#define GPIO_SERIAL_IO_UART_TX GPIO_NATIVE_FUNCTION_DEF(9,16)
+#define GPIO_SERIAL_IO_UART_RTS GPIO_NATIVE_FUNCTION_DEF(17,24)
+#define GPIO_SERIAL_IO_UART_CTS GPIO_NATIVE_FUNCTION_DEF(25,31)
+#define GPIO_SERIAL_IO_SPI_MOSI GPIO_NATIVE_FUNCTION_DEF(32,39)
+#define GPIO_SERIAL_IO_SPI_MISO GPIO_NATIVE_FUNCTION_DEF(40,47)
+#define GPIO_SERIAL_IO_SPI_CLK GPIO_NATIVE_FUNCTION_DEF(48,55)
+#define GPIO_SERIAL_IO_SPI_CS GPIO_NATIVE_FUNCTION_DEF(56,71)
+#define GPIO_ISH_GP GPIO_NATIVE_FUNCTION_DEF(80,143)
+#define GPIO_ISH_UART_RX GPIO_NATIVE_FUNCTION_DEF(144,151)
+#define GPIO_ISH_UART_TX GPIO_NATIVE_FUNCTION_DEF(152,159)
+#define GPIO_ISH_UART_RTS GPIO_NATIVE_FUNCTION_DEF(160,167)
+#define GPIO_ISH_UART_CTS GPIO_NATIVE_FUNCTION_DEF(168,175)
+#define GPIO_ISH_SPI_MOSI GPIO_NATIVE_FUNCTION_DEF(184,191)
+#define GPIO_ISH_SPI_MISO GPIO_NATIVE_FUNCTION_DEF(192,199)
+#define GPIO_ISH_SPI_CLK GPIO_NATIVE_FUNCTION_DEF(200,207)
+#define GPIO_ISH_SPI_CS GPIO_NATIVE_FUNCTION_DEF(208,223)
+#define GPIO_ISH_I2C_SCL GPIO_NATIVE_FUNCTION_DEF(232,239)
+#define GPIO_ISH_I2C_SDA GPIO_NATIVE_FUNCTION_DEF(240,247)
+#define GPIO_THC_SPI_INT GPIO_NATIVE_FUNCTION_DEF(248,251)
+#define GPIO_DMIC_DATA GPIO_NATIVE_FUNCTION_DEF(258,261)
+#define GPIO_DMIC_CLKA GPIO_NATIVE_FUNCTION_DEF(262,265)
+#define GPIO_DMIC_CLKB GPIO_NATIVE_FUNCTION_DEF(266,269)
+#define GPIO_DDSP_HPD0 GPIO_NATIVE_FUNCTION_DEF(270,285)
+#define GPIO_PANEL_AVDD_EN GPIO_NATIVE_FUNCTION_DEF(286,289)
+#define GPIO_PANEL_BKLTEN GPIO_NATIVE_FUNCTION_DEF(290,293)
+#define GPIO_PANEL_BKLTCTL GPIO_NATIVE_FUNCTION_DEF(294,297)
+#define GPIO_PANEL_RESET GPIO_NATIVE_FUNCTION_DEF(298,301)
+#define GPIO_PANEL_AVEE_EN GPIO_NATIVE_FUNCTION_DEF(302,305)
+#define GPIO_PANEL_VIO_EN GPIO_NATIVE_FUNCTION_DEF(306,309)
+#define GPIO_PANEL_HPD GPIO_NATIVE_FUNCTION_DEF(310,313)
+#define GPIO_PANEL_TE_EN GPIO_NATIVE_FUNCTION_DEF(314,317)
+#define GPIO_HDMI_GMBUS_SCL GPIO_NATIVE_FUNCTION_DEF(318,325)
+#define GPIO_HDMI_GMBUS_SDA GPIO_NATIVE_FUNCTION_DEF(326,333)
+#define GPIO_SERIAL_IO_I2C_SCL GPIO_NATIVE_FUNCTION_DEF(338,353)
+#define GPIO_SERIAL_IO_I2C_SDA GPIO_NATIVE_FUNCTION_DEF(354,369)
+#define GPIO_SD_DATA GPIO_NATIVE_FUNCTION_DEF(374,377)
+#define GPIO_EMMC_DATA GPIO_NATIVE_FUNCTION_DEF(384,391)
+#define GPIO_THC_CLK_LOOPBACK GPIO_NATIVE_FUNCTION_DEF(395,396)
+#define GPIO_MIPI_PANEL_RESET GPIO_NATIVE_FUNCTION_DEF(401,404)
+#define GPIO_MIPI_SEC_POW_EN_AVEE GPIO_NATIVE_FUNCTION_DEF(405,408)
+#define GPIO_MIPI_SEC_POW_EN_AVDD GPIO_NATIVE_FUNCTION_DEF(409,412)
+#define GPIO_THC_WOT GPIO_NATIVE_FUNCTION_DEF(413,414)
+#define GPIO_SATA_DEVSLP GPIO_NATIVE_FUNCTION_DEF(415,446)
+#define GPIO_PCIE_CLKREQ GPIO_NATIVE_FUNCTION_DEF(447,478)
+
+//
+// Serial IO UART
+//
+
+#define GPIO_FUNCTION_SERIAL_IO_UART_RX(UartDev) (GPIO_SERIAL_IO_UART_RX + ((UINT32)UartDev))
+#define GPIO_FUNCTION_SERIAL_IO_UART_TX(UartDev) (GPIO_SERIAL_IO_UART_TX + ((UINT32)UartDev))
+#define GPIO_FUNCTION_SERIAL_IO_UART_RTS(UartDev) (GPIO_SERIAL_IO_UART_RTS + ((UINT32)UartDev))
+#define GPIO_FUNCTION_SERIAL_IO_UART_CTS(UartDev) (GPIO_SERIAL_IO_UART_CTS + ((UINT32)UartDev))
+
+//
+// Serial IO SPI
+//
+#define GPIO_SERIAL_IO_SPI_RANGE 8 // Number of SerialIo SPIx controllers supported in GPIO_NATIVE_PAD encoding
+
+#define GPIO_FUNCTION_SERIAL_IO_SPI_MOSI(SpiDev) (GPIO_SERIAL_IO_SPI_MOSI + ((UINT32)SpiDev))
+#define GPIO_FUNCTION_SERIAL_IO_SPI_MISO(SpiDev) (GPIO_SERIAL_IO_SPI_MISO + ((UINT32)SpiDev))
+#define GPIO_FUNCTION_SERIAL_IO_SPI_CLK(SpiDev) (GPIO_SERIAL_IO_SPI_CLK + ((UINT32)SpiDev))
+#define GPIO_FUNCTION_SERIAL_IO_SPI_CS(SpiDev, CsNum) (GPIO_SERIAL_IO_SPI_CS + ((UINT32)SpiDev) + ((UINT32)CsNum) * GPIO_SERIAL_IO_SPI_RANGE)
+
+//
+// Serial IO I2C
+//
+
+#define GPIO_FUNCTION_SERIAL_IO_I2C_SCL(I2cDev) (GPIO_SERIAL_IO_I2C_SCL + ((UINT32)I2cDev))
+#define GPIO_FUNCTION_SERIAL_IO_I2C_SDA(I2cDev) (GPIO_SERIAL_IO_I2C_SDA + ((UINT32)I2cDev))
+
+//
+// ISH GP
+//
+
+#define GPIO_FUNCTION_ISH_GP(GpNum) (GPIO_ISH_GP + ((UINT32)GpNum))
+
+//
+// ISH UART
+//
+
+#define GPIO_FUNCTION_ISH_UART_RX(UartDev) (GPIO_ISH_UART_RX + ((UINT32)UartDev))
+#define GPIO_FUNCTION_ISH_UART_TX(UartDev) (GPIO_ISH_UART_TX + ((UINT32)UartDev))
+#define GPIO_FUNCTION_ISH_UART_RTS(UartDev) (GPIO_ISH_UART_RTS + ((UINT32)UartDev))
+#define GPIO_FUNCTION_ISH_UART_CTS(UartDev) (GPIO_ISH_UART_CTS + ((UINT32)UartDev))
+
+//
+// ISH SPI
+//
+#define GPIO_ISH_SPI_RANGE 8 // Number of ISH SPI controllers supported in GPIO_NATIVE_PAD encoding
+
+#define GPIO_FUNCTION_ISH_SPI_MOSI(SpiDev) (GPIO_ISH_SPI_MOSI + ((UINT32)SpiDev))
+#define GPIO_FUNCTION_ISH_SPI_MISO(SpiDev) (GPIO_ISH_SPI_MISO + ((UINT32)SpiDev))
+#define GPIO_FUNCTION_ISH_SPI_CLK(SpiDev) (GPIO_ISH_SPI_CLK + ((UINT32)SpiDev))
+#define GPIO_FUNCTION_ISH_SPI_CS(SpiDev, CsNum) (GPIO_ISH_SPI_CS + ((UINT32)SpiDev) + ((UINT32)CsNum) * GPIO_ISH_SPI_RANGE)
+
+//
+// ISH I2C
+//
+
+#define GPIO_FUNCTION_ISH_I2C_SCL(I2cDev) (GPIO_ISH_I2C_SCL + ((UINT32)I2cDev))
+#define GPIO_FUNCTION_ISH_I2C_SDA(I2cDev) (GPIO_ISH_I2C_SDA + ((UINT32)I2cDev))
+
+//
+// SD Card
+//
+#define GPIO_FUNCTION_SD_DATA(Index) (GPIO_SD_DATA + ((UINT32)Index))
+
+//
+// EMMC
+//
+#define GPIO_FUNCTION_EMMC_DATA(Index) (GPIO_EMMC_DATA + ((UINT32)Index))
+
+//
+// THC SPI
+//
+
+#define GPIO_FUNCTION_THC_SPI_INT(SpiDev) (GPIO_THC_SPI_INT + ((UINT32)SpiDev))
+#define GPIO_FUNCTION_THC_CLK_LOOPBACK(SpiDev) (GPIO_THC_CLK_LOOPBACK + ((UINT32)SpiDev))
+#define GPIO_FUNCTION_THC_WOT(SpiDev) (GPIO_THC_WOT + ((UINT32)SpiDev))
+
+
+//
+// DMIC
+//
+
+#define GPIO_FUNCTION_DMIC_DATA(DmicDev) (GPIO_DMIC_DATA + ((UINT32)DmicDev))
+#define GPIO_FUNCTION_DMIC_CLKA(DmicDev) (GPIO_DMIC_CLKA + ((UINT32)DmicDev))
+#define GPIO_FUNCTION_DMIC_CLKB(DmicDev) (GPIO_DMIC_CLKB + ((UINT32)DmicDev))
+#define GPIO_FUNCTION_DMIC_CLK(DmicDev) (GPIO_DMIC_CLKA + ((UINT32)DmicDev)) // If there is no split between channel A/B use A range for such Clocks
+
+
+//
+// DDSP HPD
+//
+
+#define GPIO_FUNCTION_DDSP_HPD(HpdIndex) \
+ (HpdIndex > 7) ? GPIO_DDSP_HPD0 + 8 + (HpdIndex) - 'A' : GPIO_DDSP_HPD0 + HpdIndex
+
+//
+// HDMI_GMBUS
+//
+
+#define GPIO_FUNCTION_HDMI_SCL(DdiPort) (GPIO_HDMI_GMBUS_SCL + ((UINT32)DdiPort))
+#define GPIO_FUNCTION_HDMI_SDA(DdiPort) (GPIO_HDMI_GMBUS_SDA + ((UINT32)DdiPort))
+
+//
+// Panel
+//
+
+#define GPIO_FUNCTION_PANEL_AVDD_EN(PanelDev) (GPIO_PANEL_AVDD_EN + ((UINT32)PanelDev))
+#define GPIO_FUNCTION_PANEL_BKLTEN(PanelDev) (GPIO_PANEL_BKLTEN + ((UINT32)PanelDev))
+#define GPIO_FUNCTION_PANEL_BKLTCTL(PanelDev) (GPIO_PANEL_BKLTCTL + ((UINT32)PanelDev))
+#define GPIO_FUNCTION_PANEL_RESET(PanelDev) (GPIO_PANEL_RESET + ((UINT32)PanelDev))
+#define GPIO_FUNCTION_PANEL_AVEE_EN(PanelDev) (GPIO_PANEL_AVEE_EN + ((UINT32)PanelDev))
+#define GPIO_FUNCTION_PANEL_VIO_EN(PanelDev) (GPIO_PANEL_VIO_EN + ((UINT32)PanelDev))
+#define GPIO_FUNCTION_PANEL_HPD(PanelDev) (GPIO_PANEL_HPD + ((UINT32)PanelDev))
+#define GPIO_FUNCTION_PANEL_TE_EN(PanelDev) (GPIO_PANEL_TE_EN + ((UINT32)PanelDev))
+
+//
+// MIPI
+//
+#define GPIO_FUNCTION_MIPI_PANEL_RESET(PanelDev) (GPIO_MIPI_PANEL_RESET + ((UINT32)PanelDev))
+#define GPIO_FUNCTION_MIPI_SEC_POW_EN_AVEE(PanelDev) (GPIO_MIPI_SEC_POW_EN_AVEE + ((UINT32)PanelDev))
+#define GPIO_FUNCTION_MIPI_SEC_POW_EN_AVDD(PanelDev) (GPIO_MIPI_SEC_POW_EN_AVDD + ((UINT32)PanelDev))
+
+
+//
+// SATA DevSlp
+//
+#define GPIO_SATA_DEVSLP_RANGE 32 // Number of SATA DevSlp instances per controller supported in GPIO_NATIVE_PAD encoding
+
+#define GPIO_FUNCTION_SATA_DEVSLP(CsNum, SataDevSlpIndex) (GPIO_SATA_DEVSLP + ((UINT32)SataDevSlpIndex) + ((UINT32)CsNum) * GPIO_SATA_DEVSLP_RANGE)
+
+//
+// SRC CLKREQ
+//
+
+#define GPIO_FUNCTION_PCIE_CLKREQ(ClkReqIndex) (GPIO_PCIE_CLKREQ + ((UINT32)ClkReqIndex))
+
+#endif // _GPIO_NATIVE_PADS_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/IncludePrivate/Library/GpioPrivateLib.h b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/IncludePrivate/Library/GpioPrivateLib.h
new file mode 100644
index 0000000000..a757a4b057
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/IncludePrivate/Library/GpioPrivateLib.h
@@ -0,0 +1,350 @@
+/** @file
+ Header file for GpioPrivateLib.
+ All function in this library is available for PEI, DXE, and SMM,
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _GPIO_PRIVATE_LIB_H_
+#define _GPIO_PRIVATE_LIB_H_
+
+#include <Uefi/UefiBaseType.h>
+#include <Library/GpioConfig.h>
+#include <Library/PchPcrLib.h>
+
+/**
+ GPIO Standby State configuration
+ Standby State options for GPIO Pads
+**/
+typedef enum {
+ GpioIosStateDefault = 0x0,
+ GpioIosStateLatchLastValue = (0x0 << 1) | 0x01, ///< Latch last value driven on TX, TX Enable and RX Enable
+ GpioIosStateTx0Rx0RxDis = (0x1 << 1) | 0x01, ///< TX: 0, RX: 0 (internally), RX disabled
+ GpioIosStateTx0Rx1RxDis = (0x2 << 1) | 0x01, ///< TX: 0, RX: 1 (internally), RX disabled
+ GpioIosStateTx1Rx0RxDis = (0x3 << 1) | 0x01, ///< TX: 1, RX: 0 (internally), RX disabled
+ GpioIosStateTx1Rx1RxDis = (0x4 << 1) | 0x01, ///< TX: 1, RX: 1 (internally), RX disabled
+ GpioIosStateTx0RxEn = (0x5 << 1) | 0x01, ///< TX: 0, RX enabled
+ GpioIosStateTx1RxEn = (0x6 << 1) | 0x01, ///< TX: 1, RX enabled
+ GpioIosStateHizRx0 = (0x7 << 1) | 0x01, ///< Hi-Z, RX: 0 (internally)
+ GpioIosStateHizRx1 = (0x8 << 1) | 0x01, ///< Hi-Z, RX: 1 (internally)
+ GpioIosStateTxDisRxEn = (0x9 << 1) | 0x01, ///< TX Disabled and RX Enabled (i.e. wake or interrupt)
+ GpioIosStateMasked = (0xF << 1) | 0x01 ///< IO Standby signal is masked for this pad. In this mode, a pad operates as if IOStandby has not been asserted.
+} GPIO_IOSTANDBY_STATE;
+
+/**
+ GPIO Standby Term configuration
+ Standby Termination options for GPIO Pads
+**/
+typedef enum {
+ GpioIosTermDefault = 0x00,
+ GpioIosTermSame = (0x00 << 1) | 0x01, ///< Same as state specified in Term
+ GpioIosTermPuDisPdDis = (0x01 << 1) | 0x01, ///< Disable Pullup and Pulldown
+ GpioIosTermPuDisPdEn = (0x02 << 1) | 0x01, ///< Enable Pulldown
+ GpioIosTermPuEnPdDis = (0x03 << 1) | 0x01 ///< Enable Pullup
+} GPIO_IOSTANDBY_TERM;
+
+//
+// Structure for native pin data
+//
+typedef struct {
+ GPIO_PAD Pad;
+ GPIO_PAD_MODE Mode;
+ GPIO_IOSTANDBY_STATE IosState;
+ GPIO_IOSTANDBY_TERM IosTerm;
+} GPIO_PAD_NATIVE_FUNCTION;
+
+//
+// Structure for Serial GPIO pin definition
+//
+typedef struct {
+ GPIO_PAD_NATIVE_FUNCTION Sclock;
+ GPIO_PAD_NATIVE_FUNCTION Sload;
+ GPIO_PAD_NATIVE_FUNCTION Sdataout;
+} SGPIO_PINS;
+
+//
+// Structure for USB Virtual Wire OverCurrent Pad Mode group
+//
+typedef struct {
+ GPIO_PAD OcRxPad;
+ GPIO_PAD OcTxPad;
+} GPIO_VWOC_FUNCTION;
+
+//
+// Below defines are based on GPIO_CONFIG structure fields
+//
+#define B_GPIO_PAD_MODE_MASK 0xF
+#define N_GPIO_PAD_MODE_BIT_POS 0
+#define B_GPIO_DIRECTION_DIR_MASK 0x7
+#define N_GPIO_DIRECTION_DIR_BIT_POS 0
+#define B_GPIO_DIRECTION_INV_MASK 0x18
+#define N_GPIO_DIRECTION_INV_BIT_POS 3
+#define B_GPIO_OUTPUT_MASK 0x3
+#define N_GPIO_OUTPUT_BIT_POS 0
+#define N_GPIO_INT_CONFIG_INT_SOURCE_BIT_POS 0
+#define N_GPIO_INT_CONFIG_INT_TYPE_BIT_POS 5
+#define N_GPIO_ELECTRICAL_CONFIG_TERMINATION_BIT_POS 0
+#define N_GPIO_OTHER_CONFIG_RXRAW_BIT_POS 0
+
+//
+// Structure for storing information about registers offset, community,
+// maximal pad number for available groups
+//
+typedef struct {
+ PCH_SBI_PID Community;
+ UINT16 PadOwnOffset;
+ UINT16 HostOwnOffset;
+ UINT16 GpiIsOffset;
+ UINT16 GpiIeOffset;
+ UINT16 GpiGpeStsOffset;
+ UINT16 GpiGpeEnOffset;
+ UINT16 SmiStsOffset;
+ UINT16 SmiEnOffset;
+ UINT16 NmiStsOffset;
+ UINT16 NmiEnOffset;
+ UINT16 PadCfgLockOffset;
+ UINT16 PadCfgLockTxOffset;
+ UINT16 PadCfgOffset;
+ UINT16 PadPerGroup;
+} GPIO_GROUP_INFO;
+
+//
+// If in GPIO_GROUP_INFO structure certain register doesn't exist
+// it will have value equal to NO_REGISTER_FOR_PROPERTY
+//
+#define NO_REGISTER_FOR_PROPERTY 0xFFFF
+
+#define GPIO_PAD_DEF(Group,Pad) (UINT32)(((Group) << 16) + (Pad))
+#define GPIO_GROUP_DEF(GroupIndex,ChipsetId) ((GroupIndex) | ((ChipsetId) << 8))
+#define GPIO_GET_GROUP_INDEX(Group) ((Group) & 0x1F)
+#define GPIO_GET_GROUP_FROM_PAD(GpioPad) (((GpioPad) & 0x0F1F0000) >> 16)
+#define GPIO_GET_GROUP_INDEX_FROM_PAD(GpioPad) GPIO_GET_GROUP_INDEX (GPIO_GET_GROUP_FROM_PAD(GpioPad))
+#define GPIO_GET_PAD_NUMBER(GpioPad) ((GpioPad) & 0x1FF)
+#define GPIO_GET_CHIPSET_ID(GpioPad) (((GpioPad) >> 24) & 0xF)
+
+#define GPIO_GET_PAD_POSITION(PadNumber) ((PadNumber) % 32)
+#define GPIO_GET_DW_NUM(PadNumber) ((PadNumber) / 32u)
+
+/**
+ This procedure will retrieve address and length of GPIO info table
+
+ @param[out] GpioGroupInfoTableLength Length of GPIO group table
+
+ @retval Pointer to GPIO group table
+**/
+CONST GPIO_GROUP_INFO*
+GpioGetGroupInfoTable (
+ OUT UINT32 *GpioGroupInfoTableLength
+ );
+
+typedef struct {
+ CONST CHAR8* GpioGroupPrefix;
+ CONST GPIO_PAD FirstUniqueGpio;
+ CONST CHAR8** GroupUniqueNames;
+ CONST UINT32 UniqueNamesTableSize;
+} GPIO_GROUP_NAME_INFO;
+
+//
+// Helper macros for initializing GPIO_GROUP_NAME_INFO structures
+//
+#define GPIO_GROUP_NAME(GroupName,FirstUniqueGpio,GroupUniqueNamesTable) \
+ {GroupName, FirstUniqueGpio, GroupUniqueNamesTable, ARRAY_SIZE (GroupUniqueNamesTable)}
+
+#define GPIO_GROUP_NAME_BASIC(GroupName) \
+ {GroupName, 0, NULL, 0}
+
+/**
+ Get GPIO Chipset ID specific to PCH generation and series
+**/
+UINT32
+GpioGetThisChipsetId (
+ VOID
+ );
+
+/**
+ This procedure is used to check if GpioPad is valid for certain chipset
+
+ @param[in] GpioPad GPIO pad
+
+ @retval TRUE This pin is valid on this chipset
+ FALSE Incorrect pin
+**/
+BOOLEAN
+GpioIsCorrectPadForThisChipset (
+ IN GPIO_PAD GpioPad
+ );
+
+
+/**
+ This procedure is used by PchSmiDispatcher and will return information
+ needed to register GPI SMI.
+
+ @param[in] Index GPI SMI number
+ @param[out] GpioPin GPIO pin
+ @param[out] GpiSmiBitOffset GPI SMI bit position within GpiSmi Registers
+ @param[out] GpiHostSwOwnRegAddress Address of HOSTSW_OWN register
+ @param[out] GpiSmiStsRegAddress Address of GPI SMI status register
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid group or pad number
+**/
+EFI_STATUS
+GpioGetPadAndSmiRegs (
+ IN UINT32 Index,
+ OUT GPIO_PAD *GpioPin,
+ OUT UINT8 *GpiSmiBitOffset,
+ OUT UINT32 *GpiHostSwOwnRegAddress,
+ OUT UINT32 *GpiSmiStsRegAddress
+ );
+
+/**
+ This procedure calculates Pad Configuration Register DW offset
+
+ @param[in] GpioPad GPIO pad
+ @param[in] DwReg Index of the configuration register
+
+ @retval DW Register offset
+**/
+UINT32
+GpioGetGpioPadCfgAddressFromGpioPad (
+ IN GPIO_PAD GpioPad,
+ IN UINT32 DwReg
+ );
+
+
+/**
+ This procedure will check if GpioPad argument is valid.
+ Function will check below conditions:
+ - GpioPad represents a pad for current PCH
+ - GpioPad belongs to valid GpioGroup
+ - GPIO PadNumber is not greater than number of pads for this group
+
+ @param[in] GpioPad GPIO pad
+
+ @retval TRUE GPIO pad is valid and can be used with GPIO lib API
+ @retval FALSE GPIO pad is invalid and cannot be used with GPIO lib API
+**/
+BOOLEAN
+GpioIsPadValid (
+ IN GPIO_PAD GpioPad
+ );
+
+/**
+ This procedure will read GPIO Pad Configuration register
+
+ @param[in] GpioPad GPIO pad
+ @param[in] DwReg Choose PADCFG register: 0:DW0, 1:DW1
+
+ @retval PadCfgRegValue PADCFG_DWx value
+**/
+UINT32
+GpioReadPadCfgReg (
+ IN GPIO_PAD GpioPad,
+ IN UINT8 DwReg
+ );
+
+/**
+ Check if 0x13 opcode supported for writing to GPIO lock unlock register
+
+ @retval TRUE It's supported
+ @retval FALSE It's not supported
+**/
+BOOLEAN
+IsGpioLockOpcodeSupported (
+ VOID
+ );
+
+/**
+ Gpio Minimum Set
+
+ Set of Gpio Minimum function to use in Pre Mem phase.
+ To optimise execution and reduce memory footprint thse minimum version
+ of 'full' functions are stripped from:
+ - GpioPad PCH validation
+ - GpioPad Group belonging validation
+ - GpioPad Host ownership validation
+ - IoStandbyState configuration
+ The use of below functions has to be careful and with full
+ understanding of all pros and cons. Please refer to GpioPrivateLib.c
+ to familiarize with details of implementation.
+**/
+
+/**
+ This procedure reads GPIO register
+
+ @param[in] GpioGroupInfo Pointer to GPIO group table info
+ @param[in] Register Register offset
+
+ @retval Register value or "F"s in case of errors
+**/
+UINT32
+GpioRegisterAccessRead32 (
+ IN CONST GPIO_GROUP_INFO *GpioGroupInfo,
+ IN UINT32 Register
+ );
+
+/**
+ This procedure writes GPIO register
+
+ @param[in] GpioGroupInfo Pointer to GPIO group table info
+ @param[in] Register Register offset
+ @param[in] AndValue And value
+ @param[in] OrValue Or value
+
+ @retval EFI_DEVICE_ERROR vGPIO BAR not programmed
+ EFI_SUCCESS Operation completed successfully
+**/
+EFI_STATUS
+GpioRegisterAccessAndThenOr32 (
+ IN CONST GPIO_GROUP_INFO *GpioGroupInfo,
+ IN UINT32 Register,
+ IN UINT32 AndValue,
+ IN UINT32 OrValue
+ );
+
+/**
+ This procedure will calculate PADCFG register value based on GpioConfig data
+ The procedure can be various depending on chipset generation.
+ Available configuration options and corresponding registers fields
+ can distributed in different way in configuration registers.
+
+ @param[in] GpioPad GPIO Pad
+ @param[in] GpioConfig GPIO Configuration data
+ @param[out] PadCfgDwReg PADCFG DWx register value
+ @param[out] PadCfgDwRegMask Mask with PADCFG DWx register bits to be modified
+
+ @retval Status
+**/
+EFI_STATUS
+GpioPadCfgRegValueFromGpioConfig (
+ IN GPIO_PAD GpioPad,
+ IN CONST GPIO_CONFIG *GpioConfig,
+ OUT UINT32 *PadCfgDwReg,
+ OUT UINT32 *PadCfgDwRegMask
+ );
+
+/**
+ This procedure will write GPIO Lock/LockTx register
+ - For PCH SBI message is used.
+ - For IBL MMIO access is used.
+
+ @param[in] RegValue GPIO register (Lock or LockTx) value
+ @param[in] RegOffset GPIO register (Lock or LockTx) base offset
+ @param[in] DwNum Register number for current group.
+ For group which has less then 32 pads per group DwNum must be 0.
+ @param[in] GpioGroupInfo Pointer to GPIO group table info
+ @param[in] GroupIndex GPIO group index in the GpioGroupInfo table
+
+ @retval EFI_SUCCESS The function completed successfully
+ EFI_UNSUPPORTED Feature is not supported for this group or pad
+**/
+EFI_STATUS
+GpioInternalWriteLockRegister (
+ IN UINT32 RegValue,
+ IN UINT32 RegOffset,
+ IN UINT32 DwNum,
+ IN CONST GPIO_GROUP_INFO *GpioGroupInfo,
+ IN UINT32 GroupIndex
+ );
+
+#endif // _GPIO_PRIVATE_LIB_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/Library/PeiDxeSmmGpioLib/GpioInit.c b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/Library/PeiDxeSmmGpioLib/GpioInit.c
new file mode 100644
index 0000000000..cf6f92a50d
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/Library/PeiDxeSmmGpioLib/GpioInit.c
@@ -0,0 +1,546 @@
+/** @file
+ This file contains routines for GPIO initialization
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#include "GpioLibrary.h"
+
+//
+// GPIO_GROUP_DW_DATA structure is used by GpioConfigurePch function
+// to cache values which will be programmed into respective GPIO registers
+// after all GpioPads are processed. This way MMIO accesses are decreased
+// and instead of doing one programming for one GpioPad there is only
+// one access for whole register.
+//
+typedef struct {
+ UINT32 HostSoftOwnReg;
+ UINT32 HostSoftOwnRegMask;
+ UINT32 GpiGpeEnReg;
+ UINT32 GpiGpeEnRegMask;
+ UINT32 GpiNmiEnReg;
+ UINT32 GpiNmiEnRegMask;
+ UINT32 GpiSmiEnReg;
+ UINT32 GpiSmiEnRegMask;
+ UINT32 ConfigUnlockMask;
+ UINT32 OutputUnlockMask;
+} GPIO_GROUP_DW_DATA;
+
+//
+// GPIO_GROUP_DW_NUMBER contains number of DWords required to
+// store Pad data for all groups. Each pad uses one bit.
+//
+// For Cannonlake only vGPIO group has >32 pads but those pads
+// will not be accessed by this function so GPIO_GROUP_DW_NUMBER can be 1
+//
+#define GPIO_GROUP_DW_NUMBER 1
+
+/**
+ Get GPIO DW Register values (HOSTSW_OWN, GPE_EN, NMI_EN, Lock).
+
+ @param[in] PadNumber GPIO pad number
+ @param[in] GpioConfig GPIO Config data
+ @param[in out] DwRegsValues Values for GPIO DW Registers
+
+ @retval None
+**/
+STATIC
+VOID
+GpioDwRegValueFromGpioConfig (
+ IN UINT32 PadNumber,
+ IN CONST GPIO_CONFIG *GpioConfig,
+ IN OUT GPIO_GROUP_DW_DATA *GroupDwData
+ )
+{
+ UINT32 PadBitPosition;
+ UINT32 DwNum;
+
+ PadBitPosition = GPIO_GET_PAD_POSITION (PadNumber);
+ DwNum = GPIO_GET_DW_NUM (PadNumber);
+
+ if (DwNum >= GPIO_GROUP_DW_NUMBER) {
+ ASSERT (FALSE);
+ return;
+ }
+ //
+ // Update value to be programmed in HOSTSW_OWN register
+ //
+ GroupDwData[DwNum].HostSoftOwnRegMask |= (GpioConfig->HostSoftPadOwn & 0x1) << PadBitPosition;
+ GroupDwData[DwNum].HostSoftOwnReg |= (GpioConfig->HostSoftPadOwn >> 0x1) << PadBitPosition;
+
+ //
+ // Update value to be programmed in GPI_GPE_EN register
+ //
+ GroupDwData[DwNum].GpiGpeEnRegMask |= (GpioConfig->InterruptConfig & 0x1) << PadBitPosition;
+ GroupDwData[DwNum].GpiGpeEnReg |= ((GpioConfig->InterruptConfig & GpioIntSci) >> 3) << PadBitPosition;
+
+ //
+ // Update value to be programmed in GPI_NMI_EN register
+ //
+ GroupDwData[DwNum].GpiNmiEnRegMask |= (GpioConfig->InterruptConfig & 0x1) << PadBitPosition;
+ GroupDwData[DwNum].GpiNmiEnReg |= ((GpioConfig->InterruptConfig & GpioIntNmi) >> 1) << PadBitPosition;
+
+ //
+ // Update value to be programmed in GPI_SMI_EN register
+ GroupDwData[DwNum].GpiSmiEnRegMask |= (GpioConfig->InterruptConfig & 0x1) << PadBitPosition;
+ GroupDwData[DwNum].GpiSmiEnReg |= ((GpioConfig->InterruptConfig & GpioIntSmi) >> 2) << PadBitPosition;
+ if ((GpioConfig->InterruptConfig & GpioIntSmi) == GpioIntSmi) {
+ GroupDwData[DwNum].HostSoftOwnRegMask |= 1 << PadBitPosition;
+ GroupDwData[DwNum].HostSoftOwnReg |= 1 << PadBitPosition;
+ }
+
+ //
+ // Update information on Pad Configuration Lock
+ //
+ GroupDwData[DwNum].ConfigUnlockMask |= ((GpioConfig->LockConfig >> 1) & 0x1) << PadBitPosition;
+
+ //
+ // Update information on Pad Configuration Lock Tx
+ //
+ GroupDwData[DwNum].OutputUnlockMask |= ((GpioConfig->LockConfig >> 3) & 0x1) << PadBitPosition;
+
+ //
+ // if pad in GpioMode is an output default action should be to leave output unlocked
+ //
+ if ((GpioConfig->PadMode == GpioPadModeGpio) &&
+ (GpioConfig->Direction == GpioDirOut) &&
+ ((GpioConfig->LockConfig & B_GPIO_LOCK_CONFIG_OUTPUT_LOCK_MASK) == GpioLockDefault)) {
+ GroupDwData[DwNum].OutputUnlockMask |= 0x1 << PadBitPosition;
+ }
+}
+
+/**
+ This internal procedure will scan GPIO initialization table and unlock
+ all pads present in it
+
+ @param[in] NumberOfItem Number of GPIO pad records in table
+ @param[in] GpioInitTableAddress GPIO initialization table
+ @param[in] Index Index of GPIO Initialization table record
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid group or pad number
+**/
+STATIC
+EFI_STATUS
+GpioUnlockPadsForAGroup (
+ IN UINT32 NumberOfItems,
+ IN GPIO_INIT_CONFIG *GpioInitTableAddress,
+ IN UINT32 Index
+ )
+{
+ UINT32 PadsToUnlock[GPIO_GROUP_DW_NUMBER];
+ UINT32 DwNum;
+ UINT32 PadBitPosition;
+ CONST GPIO_GROUP_INFO *GpioGroupInfo;
+ UINT32 GpioGroupInfoLength;
+ CONST GPIO_INIT_CONFIG *GpioData;
+ GPIO_GROUP Group;
+ UINT32 GroupIndex;
+ UINT32 PadNumber;
+
+ GpioGroupInfo = GpioGetGroupInfoTable (&GpioGroupInfoLength);
+
+ GpioData = &GpioInitTableAddress[Index];
+ Group = GpioGetGroupFromGpioPad (GpioData->GpioPad);
+ GroupIndex = GpioGetGroupIndexFromGpioPad (GpioData->GpioPad);
+
+ ZeroMem (PadsToUnlock, sizeof (PadsToUnlock));
+ //
+ // Loop through pads for one group. If pad belongs to a different group then
+ // break and move to register programming.
+ //
+ while (Index < NumberOfItems) {
+
+ GpioData = &GpioInitTableAddress[Index];
+ if (GroupIndex != GpioGetGroupIndexFromGpioPad (GpioData->GpioPad)) {
+ //if next pad is from different group then break loop
+ break;
+ }
+
+ PadNumber = GpioGetPadNumberFromGpioPad (GpioData->GpioPad);
+ //
+ // Check if legal pin number
+ //
+ if (PadNumber >= GpioGroupInfo[GroupIndex].PadPerGroup) {
+ DEBUG ((DEBUG_ERROR, "GPIO ERROR: Pin number (%d) exceeds possible range for group %d\n", PadNumber, GroupIndex));
+ return EFI_INVALID_PARAMETER;
+ }
+
+ PadBitPosition = GPIO_GET_PAD_POSITION (PadNumber);
+ DwNum = GPIO_GET_DW_NUM (PadNumber);
+
+ if (DwNum >= GPIO_GROUP_DW_NUMBER) {
+ ASSERT (FALSE);
+ return EFI_UNSUPPORTED;
+ }
+ //
+ // Update pads which need to be unlocked
+ //
+ PadsToUnlock[DwNum] |= 0x1 << PadBitPosition;
+
+ //Move to next item
+ Index++;
+ }
+
+ for (DwNum = 0; DwNum <= GPIO_GET_DW_NUM (GpioGroupInfo[GroupIndex].PadPerGroup - 1); DwNum++) {
+ //
+ // Unlock pads
+ //
+ if (PadsToUnlock[DwNum] != 0) {
+ GpioUnlockPadCfgForGroupDw (Group, DwNum, PadsToUnlock[DwNum]);
+ GpioUnlockPadCfgTxForGroupDw (Group, DwNum, PadsToUnlock[DwNum]);
+ }
+ }
+
+ return EFI_SUCCESS;
+}
+
+/**
+ This procedure will initialize multiple PCH GPIO pins
+
+ @param[in] NumberofItem Number of GPIO pads to be updated
+ @param[in] GpioInitTableAddress GPIO initialization table
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid group or pad number
+**/
+STATIC
+EFI_STATUS
+GpioConfigurePch (
+ IN UINT32 NumberOfItems,
+ IN GPIO_INIT_CONFIG *GpioInitTableAddress
+ )
+{
+ UINT32 Index;
+ UINT32 PadCfgDwReg[GPIO_PADCFG_DW_REG_NUMBER];
+ UINT32 PadCfgDwRegMask[GPIO_PADCFG_DW_REG_NUMBER];
+ UINT32 PadCfgReg;
+ GPIO_GROUP_DW_DATA GroupDwData[GPIO_GROUP_DW_NUMBER];
+ UINT32 DwNum;
+ CONST GPIO_GROUP_INFO *GpioGroupInfo;
+ UINT32 GpioGroupInfoLength;
+ GPIO_PAD_OWN PadOwnVal;
+ CONST GPIO_INIT_CONFIG *GpioData;
+ UINT32 GroupIndex;
+ UINT32 PadNumber;
+ UINT32 DwRegIndex;
+
+ PadOwnVal = GpioPadOwnHost;
+
+ GpioGroupInfo = GpioGetGroupInfoTable (&GpioGroupInfoLength);
+
+ Index = 0;
+ while (Index < NumberOfItems) {
+
+ GpioData = &GpioInitTableAddress[Index];
+ GroupIndex = GpioGetGroupIndexFromGpioPad (GpioData->GpioPad);
+
+ DEBUG_CODE_BEGIN();
+ if (!GpioIsCorrectPadForThisChipset (GpioData->GpioPad)) {
+ DEBUG ((DEBUG_ERROR, "GPIO ERROR: Incorrect GpioPad (0x%08x) used on this chipset!\n", GpioData->GpioPad));
+ ASSERT (FALSE);
+ return EFI_UNSUPPORTED;
+ }
+ DEBUG_CODE_END ();
+
+ //
+ // Unlock pads for a given group which are going to be reconfigured
+ //
+ //
+ // Because PADCFGLOCK/LOCKTX register reset domain is Powergood, lock settings
+ // will get back to default only after G3 or DeepSx transition. On the other hand GpioPads
+ // configuration is controlled by a configurable type of reset - PadRstCfg. This means that if
+ // PadRstCfg != Powergood GpioPad will have its configuration locked despite it being not the
+ // one desired by BIOS. Before reconfiguring all pads they will get unlocked.
+ //
+ GpioUnlockPadsForAGroup (NumberOfItems, GpioInitTableAddress, Index);
+
+ ZeroMem (GroupDwData, sizeof (GroupDwData));
+ //
+ // Loop through pads for one group. If pad belongs to a different group then
+ // break and move to register programming.
+ //
+ while (Index < NumberOfItems) {
+
+ GpioData = &GpioInitTableAddress[Index];
+ if (GroupIndex != GpioGetGroupIndexFromGpioPad (GpioData->GpioPad)) {
+ //if next pad is from different group then break loop
+ break;
+ }
+
+ PadNumber = GpioGetPadNumberFromGpioPad (GpioData->GpioPad);
+
+ DEBUG_CODE_BEGIN ();
+ //
+ // Check if legal pin number
+ //
+ if (PadNumber >= GpioGroupInfo[GroupIndex].PadPerGroup) {
+ DEBUG ((DEBUG_ERROR, "GPIO ERROR: Pin number (%d) exceeds possible range for group %d\n", PadNumber, GroupIndex));
+ return EFI_INVALID_PARAMETER;
+ }
+
+ //
+ // Check if selected GPIO Pad is not owned by CSME/ISH
+ //
+ GpioGetPadOwnership (GpioData->GpioPad, &PadOwnVal);
+
+ if (PadOwnVal != GpioPadOwnHost) {
+ DEBUG ((DEBUG_ERROR, "GPIO ERROR: Accessing pad not owned by host (Group=%d, Pad=%d)!\n", GroupIndex, PadNumber));
+ DEBUG ((DEBUG_ERROR, "** Please make sure the GPIO usage in sync between CSME and BIOS configuration. \n"));
+ DEBUG ((DEBUG_ERROR, "** All the GPIO occupied by CSME should not do any configuration by BIOS.\n"));
+ //Move to next item
+ goto move_to_next_index;
+ }
+
+ //
+ // Check if Pad enabled for SCI is to be in unlocked state
+ //
+ if (((GpioData->GpioConfig.InterruptConfig & GpioIntSci) == GpioIntSci) &&
+ ((GpioData->GpioConfig.LockConfig & B_GPIO_LOCK_CONFIG_PAD_CONF_LOCK_MASK) != GpioPadConfigUnlock)){
+ DEBUG ((DEBUG_ERROR, "GPIO ERROR: GPIO used for SCI is not unlocked!\n"));
+ ASSERT (FALSE);
+ return EFI_INVALID_PARAMETER;
+ }
+ DEBUG_CODE_END ();
+
+ ZeroMem (PadCfgDwReg, sizeof (PadCfgDwReg));
+ ZeroMem (PadCfgDwRegMask, sizeof (PadCfgDwRegMask));
+ //
+ // Get GPIO PADCFG register value from GPIO config data
+ //
+ GpioPadCfgRegValueFromGpioConfig (
+ GpioData->GpioPad,
+ &GpioData->GpioConfig,
+ PadCfgDwReg,
+ PadCfgDwRegMask
+ );
+
+ //
+ // Write PADCFG DW0, DW1, DW2 registers
+ //
+ for (DwRegIndex = 0; DwRegIndex <= 2; DwRegIndex++) {
+ PadCfgReg = GpioGetGpioPadCfgAddressFromGpioPad (GpioData->GpioPad, DwRegIndex);
+ if (PadCfgReg != 0) {
+ GpioRegisterAccessAndThenOr32 (&GpioGroupInfo[GroupIndex], PadCfgReg, ~PadCfgDwRegMask[DwRegIndex], PadCfgDwReg[DwRegIndex]);
+ }
+ }
+
+ //
+ // Get GPIO DW register values from GPIO config data
+ //
+ GpioDwRegValueFromGpioConfig (
+ PadNumber,
+ &GpioData->GpioConfig,
+ GroupDwData
+ );
+
+ move_to_next_index:
+ //Move to next item
+ Index++;
+ }
+
+ for (DwNum = 0; DwNum <= GPIO_GET_DW_NUM (GpioGroupInfo[GroupIndex].PadPerGroup); DwNum++) {
+ //
+ // Write HOSTSW_OWN registers
+ //
+ if (GpioGroupInfo[GroupIndex].HostOwnOffset != NO_REGISTER_FOR_PROPERTY) {
+ GpioRegisterAccessAndThenOr32 (
+ &GpioGroupInfo[GroupIndex],
+ GpioGroupInfo[GroupIndex].HostOwnOffset + DwNum * 0x4,
+ ~GroupDwData[DwNum].HostSoftOwnRegMask,
+ GroupDwData[DwNum].HostSoftOwnReg
+ );
+ }
+
+ //
+ // Write GPI_GPE_EN registers
+ //
+ if (GpioGroupInfo[GroupIndex].GpiGpeEnOffset != NO_REGISTER_FOR_PROPERTY) {
+ GpioRegisterAccessAndThenOr32 (
+ &GpioGroupInfo[GroupIndex],
+ GpioGroupInfo[GroupIndex].GpiGpeEnOffset + DwNum * 0x4,
+ ~GroupDwData[DwNum].GpiGpeEnRegMask,
+ GroupDwData[DwNum].GpiGpeEnReg
+ );
+ }
+
+ //
+ // Write GPI_NMI_EN registers
+ //
+ if (GpioGroupInfo[GroupIndex].NmiEnOffset != NO_REGISTER_FOR_PROPERTY) {
+ GpioRegisterAccessAndThenOr32 (
+ &GpioGroupInfo[GroupIndex],
+ GpioGroupInfo[GroupIndex].NmiEnOffset + DwNum * 0x4,
+ ~GroupDwData[DwNum].GpiNmiEnRegMask,
+ GroupDwData[DwNum].GpiNmiEnReg
+ );
+ } else if (GroupDwData[DwNum].GpiNmiEnReg != 0x0) {
+ DEBUG ((DEBUG_ERROR, "GPIO ERROR: Group %d has no pads supporting NMI\n", GroupIndex));
+ ASSERT_EFI_ERROR (EFI_UNSUPPORTED);
+ }
+
+ //
+ // Write GPI_SMI_EN registers
+ //
+ if (GpioGroupInfo[GroupIndex].SmiEnOffset != NO_REGISTER_FOR_PROPERTY) {
+ GpioRegisterAccessAndThenOr32 (
+ &GpioGroupInfo[GroupIndex],
+ GpioGroupInfo[GroupIndex].SmiEnOffset + DwNum * 0x4,
+ ~GroupDwData[DwNum].GpiSmiEnRegMask,
+ GroupDwData[DwNum].GpiSmiEnReg
+ );
+ } else if (GroupDwData[DwNum].GpiSmiEnReg != 0x0) {
+ DEBUG ((DEBUG_ERROR, "GPIO ERROR: Group %d has no pads supporting SMI\n", GroupIndex));
+ ASSERT_EFI_ERROR (EFI_UNSUPPORTED);
+ }
+
+ //
+ // Update Pad Configuration unlock data
+ //
+ if (GroupDwData[DwNum].ConfigUnlockMask) {
+ GpioStoreGroupDwUnlockPadConfigData (GroupIndex, DwNum, GroupDwData[DwNum].ConfigUnlockMask);
+ }
+
+ //
+ // Update Pad Output unlock data
+ //
+ if (GroupDwData[DwNum].OutputUnlockMask) {
+ GpioStoreGroupDwUnlockOutputData (GroupIndex, DwNum, GroupDwData[DwNum].OutputUnlockMask);
+ }
+ }
+ }
+
+ return EFI_SUCCESS;
+}
+
+/**
+ This procedure will clear all status bits of any GPIO interrupts.
+
+ @param[in] none
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid group or pad number
+**/
+STATIC
+EFI_STATUS
+GpioClearAllGpioInterrupts (
+ VOID
+ )
+{
+ GPIO_GROUP Group;
+ CONST GPIO_GROUP_INFO *GpioGroupInfo;
+ GPIO_GROUP GpioGroupLowest;
+ GPIO_GROUP GpioGroupHighest;
+ UINT32 GroupIndex;
+ UINT32 GpioGroupInfoLength;
+ UINT32 DwNum;
+
+ GpioGroupInfo = GpioGetGroupInfoTable (&GpioGroupInfoLength);
+
+ GpioGroupLowest = GpioGetLowestGroup ();
+ GpioGroupHighest = GpioGetHighestGroup ();
+
+ for (Group = GpioGroupLowest; Group <= GpioGroupHighest; Group++) {
+ GroupIndex = GpioGetGroupIndexFromGroup (Group);
+ //
+ // Check if group has GPI IS register
+ //
+ if (GpioGroupInfo[GroupIndex].GpiIsOffset != NO_REGISTER_FOR_PROPERTY) {
+ //
+ // Clear all GPI_IS Status bits by writing '1'
+ //
+ for (DwNum = 0; DwNum <= GPIO_GET_DW_NUM (GpioGroupInfo[GroupIndex].PadPerGroup); DwNum++) {
+ GpioRegisterAccessAndThenOr32 (
+ &GpioGroupInfo[GroupIndex],
+ GpioGroupInfo[GroupIndex].GpiIsOffset + DwNum * 0x4,
+ ~(UINT32)0,
+ 0xFFFFFFFF
+ );
+ }
+ }
+
+ //
+ // Check if group has GPI_GPE_STS register
+ //
+ if (GpioGroupInfo[GroupIndex].GpiGpeStsOffset != NO_REGISTER_FOR_PROPERTY) {
+ //
+ // Clear all GPI_GPE_STS Status bits by writing '1'
+ //
+ for (DwNum = 0; DwNum <= GPIO_GET_DW_NUM (GpioGroupInfo[GroupIndex].PadPerGroup); DwNum++) {
+ GpioRegisterAccessAndThenOr32 (
+ &GpioGroupInfo[GroupIndex],
+ GpioGroupInfo[GroupIndex].GpiGpeStsOffset + DwNum * 0x4,
+ ~(UINT32)0,
+ 0xFFFFFFFF
+ );
+ }
+ }
+
+ //
+ // Check if group has SMI_STS register
+ //
+ if (GpioGroupInfo[GroupIndex].SmiStsOffset != NO_REGISTER_FOR_PROPERTY) {
+ //
+ // Clear all SMI_STS Status bits by writing '1'
+ //
+ for (DwNum = 0; DwNum <= GPIO_GET_DW_NUM (GpioGroupInfo[GroupIndex].PadPerGroup); DwNum++) {
+ GpioRegisterAccessAndThenOr32 (
+ &GpioGroupInfo[GroupIndex],
+ GpioGroupInfo[GroupIndex].SmiStsOffset + DwNum * 4,
+ ~(UINT32)0,
+ 0xFFFFFFFF
+ );
+ }
+ }
+
+ //
+ // Check if group has NMI_STS register
+ //
+ if (GpioGroupInfo[GroupIndex].NmiStsOffset != NO_REGISTER_FOR_PROPERTY) {
+ //
+ // Clear all NMI_STS Status bits by writing '1'
+ //
+ for (DwNum = 0; DwNum <= GPIO_GET_DW_NUM (GpioGroupInfo[GroupIndex].PadPerGroup); DwNum++) {
+ GpioRegisterAccessAndThenOr32 (
+ &GpioGroupInfo[GroupIndex],
+ GpioGroupInfo[GroupIndex].NmiStsOffset + DwNum * 4,
+ ~(UINT32)0,
+ 0xFFFFFFFF
+ );
+ }
+ }
+
+ }
+ return EFI_SUCCESS;
+}
+
+/**
+ This procedure will initialize multiple GPIO pins. Use GPIO_INIT_CONFIG structure.
+ Structure contains fields that can be used to configure each pad.
+ Pad not configured using GPIO_INIT_CONFIG will be left with hardware default values.
+ Separate fields could be set to hardware default if it does not matter, except
+ GpioPad and PadMode.
+ Function will work in most efficient way if pads which belong to the same group are
+ placed in adjacent records of the table.
+ Although function can enable pads for Native mode, such programming is done
+ by reference code when enabling related silicon feature.
+
+ @param[in] NumberofItem Number of GPIO pads to be updated
+ @param[in] GpioInitTableAddress GPIO initialization table
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid group or pad number
+**/
+EFI_STATUS
+GpioConfigurePads (
+ IN UINT32 NumberOfItems,
+ IN GPIO_INIT_CONFIG *GpioInitTableAddress
+ )
+{
+ EFI_STATUS Status;
+
+ Status = GpioConfigurePch (NumberOfItems, GpioInitTableAddress);
+
+ GpioClearAllGpioInterrupts ();
+ return Status;
+}
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/Library/PeiDxeSmmGpioLib/GpioLib.c b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/Library/PeiDxeSmmGpioLib/GpioLib.c
new file mode 100644
index 0000000000..19daed97c0
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/Library/PeiDxeSmmGpioLib/GpioLib.c
@@ -0,0 +1,522 @@
+/** @file
+ This file contains routines for GPIO
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#include "GpioLibrary.h"
+#include <Register/PchPcrRegs.h>
+
+/**
+ This procedure will check if GpioGroup argument is correct and
+ supplied DW reg number can be used for this group to access DW registers.
+ Function will check below conditions:
+ - Valid GpioGroup
+ - DwNum is has valid value for this group
+
+ @param[in] Group GPIO group
+ @param[in] DwNum Register number for current group (parameter applicable in accessing whole register).
+ For group which has less then 32 pads per group DwNum must be 0.
+
+ @retval TRUE DW Reg number and GpioGroup is valid
+ @retval FALSE DW Reg number and GpioGroup is invalid
+**/
+STATIC
+BOOLEAN
+GpioIsGroupAndDwNumValid (
+ IN GPIO_GROUP Group,
+ IN UINT32 DwNum
+ )
+{
+ UINT32 GroupIndex;
+ CONST GPIO_GROUP_INFO *GpioGroupInfo;
+ UINT32 GpioGroupInfoLength;
+
+ GpioGroupInfo = GpioGetGroupInfoTable (&GpioGroupInfoLength);
+
+ GroupIndex = GpioGetGroupIndexFromGroup (Group);
+
+ if ((Group < GpioGetLowestGroup ()) || (Group > GpioGetHighestGroup ()) || (GroupIndex >= GpioGroupInfoLength)) {
+ DEBUG ((DEBUG_ERROR, "GPIO ERROR: Group argument (%d) is not within range of possible groups for this PCH\n", GroupIndex));
+ goto Error;
+ }
+
+ //
+ // Check if DwNum argument does not exceed number of DWord registers
+ // resulting from available pads for certain group
+ //
+ if (DwNum > GPIO_GET_DW_NUM (GpioGroupInfo[GroupIndex].PadPerGroup - 1)){
+ goto Error;
+ }
+
+ return TRUE;
+Error:
+ ASSERT (FALSE);
+ return FALSE;
+}
+
+//
+// Possible registers to be accessed using GpioReadReg()/GpioWriteReg() functions
+//
+typedef enum {
+ GpioHostOwnershipRegister = 0,
+ GpioGpeEnableRegister,
+ GpioGpeStatusRegister,
+ GpioSmiEnableRegister,
+ GpioSmiStatusRegister,
+ GpioNmiEnableRegister,
+ GpioPadConfigLockRegister,
+ GpioPadLockOutputRegister
+} GPIO_REG;
+
+/**
+ This procedure will read GPIO register
+
+ @param[in] RegType GPIO register type
+ @param[in] Group GPIO group
+ @param[in] DwNum Register number for current group (parameter applicable in accessing whole register).
+ For group which has less then 32 pads per group DwNum must be 0.
+ @param[out] ReadVal Read data
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_UNSUPPORTED Feature is not supported for this group or pad
+**/
+STATIC
+EFI_STATUS
+GpioReadReg (
+ IN GPIO_REG RegType,
+ IN GPIO_GROUP Group,
+ IN UINT32 DwNum,
+ OUT UINT32 *ReadVal
+ )
+{
+ UINT32 RegOffset;
+ UINT32 GroupIndex;
+ CONST GPIO_GROUP_INFO *GpioGroupInfo;
+ UINT32 GpioGroupInfoLength;
+
+ RegOffset = NO_REGISTER_FOR_PROPERTY;
+ GroupIndex = GpioGetGroupIndexFromGroup (Group);
+
+ GpioGroupInfo = GpioGetGroupInfoTable (&GpioGroupInfoLength);
+
+ switch (RegType) {
+ case GpioHostOwnershipRegister:
+ RegOffset = GpioGroupInfo[GroupIndex].HostOwnOffset;
+ break;
+ case GpioGpeEnableRegister:
+ RegOffset = GpioGroupInfo[GroupIndex].GpiGpeEnOffset;
+ break;
+ case GpioGpeStatusRegister:
+ RegOffset = GpioGroupInfo[GroupIndex].GpiGpeStsOffset;
+ break;
+ case GpioSmiEnableRegister:
+ RegOffset = GpioGroupInfo[GroupIndex].SmiEnOffset;
+ break;
+ case GpioSmiStatusRegister:
+ RegOffset = GpioGroupInfo[GroupIndex].SmiStsOffset;
+ break;
+ case GpioNmiEnableRegister:
+ RegOffset = GpioGroupInfo[GroupIndex].NmiEnOffset;
+ break;
+ case GpioPadConfigLockRegister:
+ RegOffset = GpioGroupInfo[GroupIndex].PadCfgLockOffset;
+ break;
+ case GpioPadLockOutputRegister:
+ RegOffset = GpioGroupInfo[GroupIndex].PadCfgLockTxOffset;
+ break;
+ default:
+ break;
+ }
+
+ //
+ // Check if selected register exists
+ //
+ if (RegOffset == NO_REGISTER_FOR_PROPERTY) {
+ return EFI_UNSUPPORTED;
+ }
+
+ //
+ // If there are more then 32 pads per group then certain
+ // group information would be split into more then one DWord register.
+ //
+ if ((RegType == GpioPadConfigLockRegister) || (RegType == GpioPadLockOutputRegister)) {
+ //
+ // PadConfigLock and OutputLock registers when used for group containing more than 32 pads
+ // are not placed in a continuous way, e.g:
+ // 0x0 - PadConfigLock_DW0
+ // 0x4 - OutputLock_DW0
+ // 0x8 - PadConfigLock_DW1
+ // 0xC - OutputLock_DW1
+ //
+ RegOffset += DwNum * 0x8;
+ } else {
+ RegOffset += DwNum * 0x4;
+ }
+
+ *ReadVal = GpioRegisterAccessRead32 (&GpioGroupInfo[GroupIndex], RegOffset);
+
+ return EFI_SUCCESS;
+}
+
+/**
+ This procedure will write GPIO register
+
+ @param[in] RegType GPIO register type
+ @param[in] Group GPIO group
+ @param[in] DwNum Register number for current group (parameter applicable in accessing whole register).
+ For group which has less then 32 pads per group DwNum must be 0.
+ @param[in] RegAndMask Mask which will be AND'ed with register value
+ @param[in] RegOrMask Mask which will be OR'ed with register value
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_UNSUPPORTED Feature is not supported for this group or pad
+**/
+STATIC
+EFI_STATUS
+GpioWriteReg (
+ IN GPIO_REG RegType,
+ IN GPIO_GROUP Group,
+ IN UINT32 DwNum,
+ IN UINT32 RegAndMask,
+ IN UINT32 RegOrMask
+ )
+{
+ UINT32 RegOffset;
+ UINT32 GroupIndex;
+ CONST GPIO_GROUP_INFO *GpioGroupInfo;
+ UINT32 GpioGroupInfoLength;
+ UINT32 PadCfgLock;
+ BOOLEAN Lockable;
+
+ Lockable = FALSE;
+ PadCfgLock = 0;
+ RegOffset = NO_REGISTER_FOR_PROPERTY;
+ GroupIndex = GpioGetGroupIndexFromGroup (Group);
+
+ GpioGroupInfo = GpioGetGroupInfoTable (&GpioGroupInfoLength);
+
+ switch (RegType) {
+ case GpioHostOwnershipRegister:
+ RegOffset = GpioGroupInfo[GroupIndex].HostOwnOffset;
+ break;
+ case GpioGpeEnableRegister:
+ RegOffset = GpioGroupInfo[GroupIndex].GpiGpeEnOffset;
+ Lockable = TRUE;
+ break;
+ case GpioGpeStatusRegister:
+ RegOffset = GpioGroupInfo[GroupIndex].GpiGpeStsOffset;
+ break;
+ case GpioSmiEnableRegister:
+ RegOffset = GpioGroupInfo[GroupIndex].SmiEnOffset;
+ Lockable = TRUE;
+ break;
+ case GpioSmiStatusRegister:
+ RegOffset = GpioGroupInfo[GroupIndex].SmiStsOffset;
+ break;
+ case GpioNmiEnableRegister:
+ RegOffset = GpioGroupInfo[GroupIndex].NmiEnOffset;
+ Lockable = TRUE;
+ break;
+ case GpioPadConfigLockRegister:
+ case GpioPadLockOutputRegister:
+ default:
+ break;
+ }
+
+ //
+ // Check if selected register exists
+ //
+ if (RegOffset == NO_REGISTER_FOR_PROPERTY) {
+ return EFI_UNSUPPORTED;
+ }
+
+ if (Lockable) {
+ GpioGetPadCfgLockForGroupDw (Group, DwNum, &PadCfgLock);
+ if (PadCfgLock) {
+ //
+ // Check if for pads which are going to be reconfigured lock is set.
+ //
+ if ((~RegAndMask | RegOrMask) & PadCfgLock) {
+ //
+ // Unlock all pads for this Group DW reg for simplicity
+ // even if not all of those pads will have their settings reprogrammed
+ //
+ GpioUnlockPadCfgForGroupDw (Group, DwNum, PadCfgLock);
+ } else {
+ //
+ // No need to perform an unlock as pads which are going to be reconfigured
+ // are not in locked state
+ //
+ PadCfgLock = 0;
+ }
+ }
+ }
+
+ //
+ // If there are more then 32 pads per group then certain
+ // group information would be split into more then one DWord register.
+ //
+ RegOffset += DwNum * 0x4;
+
+ GpioRegisterAccessAndThenOr32 (&GpioGroupInfo[GroupIndex], RegOffset, RegAndMask,RegOrMask);
+
+ if (Lockable && PadCfgLock) {
+ //
+ // Lock previously unlocked pads
+ //
+ GpioLockPadCfgForGroupDw (Group, DwNum, PadCfgLock);
+ }
+
+ return EFI_SUCCESS;
+}
+
+/**
+ This procedure will write GPIO Lock/LockTx register using SBI.
+
+ @param[in] RegType GPIO register (Lock or LockTx)
+ @param[in] Group GPIO group number
+ @param[in] DwNum Register number for current group.
+ For group which has less then 32 pads per group DwNum must be 0.
+ @param[in] LockRegAndMask Mask which will be AND'ed with Lock register value
+ @param[in] LockRegOrMask Mask which will be Or'ed with Lock register value
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_UNSUPPORTED Feature is not supported for this group or pad
+**/
+STATIC
+EFI_STATUS
+GpioWriteLockReg (
+ IN GPIO_REG RegType,
+ IN GPIO_GROUP Group,
+ IN UINT32 DwNum,
+ IN UINT32 LockRegAndMask,
+ IN UINT32 LockRegOrMask
+ )
+{
+ CONST GPIO_GROUP_INFO *GpioGroupInfo;
+ UINT32 GpioGroupInfoLength;
+ UINT32 RegOffset;
+ UINT32 OldLockVal;
+ UINT32 NewLockVal;
+ UINT32 GroupIndex;
+
+ OldLockVal = 0;
+ NewLockVal = 0;
+
+ RegOffset = NO_REGISTER_FOR_PROPERTY;
+ GroupIndex = GpioGetGroupIndexFromGroup (Group);
+
+ GpioGroupInfo = GpioGetGroupInfoTable (&GpioGroupInfoLength);
+
+ switch (RegType) {
+ case GpioPadConfigLockRegister:
+ RegOffset = GpioGroupInfo[GroupIndex].PadCfgLockOffset;
+ GpioGetPadCfgLockForGroupDw (Group, DwNum, &OldLockVal);
+ break;
+ case GpioPadLockOutputRegister:
+ RegOffset = GpioGroupInfo[GroupIndex].PadCfgLockTxOffset;
+ GpioGetPadCfgLockTxForGroupDw (Group, DwNum, &OldLockVal);
+ break;
+ default:
+ break;
+ }
+
+ //
+ // Check if selected register exists
+ //
+ if (RegOffset == NO_REGISTER_FOR_PROPERTY) {
+ return EFI_UNSUPPORTED;
+ }
+
+ NewLockVal = (OldLockVal & LockRegAndMask) | LockRegOrMask;
+
+ return GpioInternalWriteLockRegister (NewLockVal, RegOffset, DwNum, GpioGroupInfo, GroupIndex);
+}
+
+/**
+ This procedure will get Gpio Pad Ownership
+
+ @param[in] GpioPad GPIO pad
+ @param[out] PadOwnVal Value of Pad Ownership
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid group or pad number
+**/
+EFI_STATUS
+GpioGetPadOwnership (
+ IN GPIO_PAD GpioPad,
+ OUT GPIO_PAD_OWN *PadOwnVal
+ )
+{
+ UINT32 Mask;
+ UINT32 RegOffset;
+ UINT32 GroupIndex;
+ UINT32 PadNumber;
+ CONST GPIO_GROUP_INFO *GpioGroupInfo;
+ UINT32 GpioGroupInfoLength;
+ UINT32 PadOwnRegValue;
+
+ if (!GpioIsPadValid (GpioPad)) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ GroupIndex = GpioGetGroupIndexFromGpioPad (GpioPad);
+ PadNumber = GpioGetPadNumberFromGpioPad (GpioPad);
+
+ GpioGroupInfo = GpioGetGroupInfoTable (&GpioGroupInfoLength);
+
+ //
+ // Check if selected register exists
+ //
+ if (GpioGroupInfo[GroupIndex].PadOwnOffset == NO_REGISTER_FOR_PROPERTY) {
+ *PadOwnVal = GpioPadOwnHost;
+ return EFI_UNSUPPORTED;
+ }
+ //
+ // Calculate RegOffset using Pad Ownership offset and GPIO Pad number.
+ // One DWord register contains information for 8 pads.
+ //
+ RegOffset = GpioGroupInfo[GroupIndex].PadOwnOffset + (PadNumber >> 3) * 0x4;
+
+ //
+ // Calculate pad bit position within DWord register
+ //
+ PadNumber %= 8;
+ Mask = (BIT1 | BIT0) << (PadNumber * 4);
+
+ PadOwnRegValue = GpioRegisterAccessRead32 (&GpioGroupInfo[GroupIndex], RegOffset);
+
+ *PadOwnVal = (GPIO_PAD_OWN) ((PadOwnRegValue & Mask) >> (PadNumber * 4));
+
+ return EFI_SUCCESS;
+}
+
+/**
+ This procedure will check state of Pad Config Lock for pads within one group
+
+ @param[in] Group GPIO group
+ @param[in] DwNum PadCfgLock register number for current group.
+ For group which has less then 32 pads per group DwNum must be 0.
+ @param[out] PadCfgLockRegVal Value of PadCfgLock register
+ Bit position - PadNumber
+ Bit value - 0: NotLocked, 1: Locked
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid group or DwNum parameter number
+**/
+EFI_STATUS
+GpioGetPadCfgLockForGroupDw (
+ IN GPIO_GROUP Group,
+ IN UINT32 DwNum,
+ OUT UINT32 *PadCfgLockRegVal
+ )
+{
+ if (!GpioIsGroupAndDwNumValid (Group, DwNum)) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ return GpioReadReg (
+ GpioPadConfigLockRegister,
+ Group,
+ DwNum,
+ PadCfgLockRegVal
+ );
+}
+/**
+ This procedure will check state of Pad Config Tx Lock for pads within one group
+
+ @param[in] Group GPIO group
+ @param[in] DwNum PadCfgLockTx register number for current group.
+ For group which has less then 32 pads per group DwNum must be 0.
+ @param[out] PadCfgLockTxRegVal Value of PadCfgLockTx register
+ Bit position - PadNumber
+ Bit value - 0: NotLockedTx, 1: LockedTx
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid group or DwNum parameter number
+**/
+EFI_STATUS
+GpioGetPadCfgLockTxForGroupDw (
+ IN GPIO_GROUP Group,
+ IN UINT32 DwNum,
+ OUT UINT32 *PadCfgLockTxRegVal
+ )
+{
+ if (!GpioIsGroupAndDwNumValid (Group, DwNum)) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ return GpioReadReg (
+ GpioPadLockOutputRegister,
+ Group,
+ DwNum,
+ PadCfgLockTxRegVal
+ );
+}
+/**
+ This procedure will clear PadCfgLock for selected pads within one group.
+ This function should be used only inside SMI.
+
+ @param[in] Group GPIO group
+ @param[in] DwNum PadCfgLock register number for current group.
+ For group which has less then 32 pads per group DwNum must be 0.
+ @param[in] PadsToUnlock Bitmask for pads which are going to be unlocked,
+ Bit position - PadNumber
+ Bit value - 0: DoNotUnlock, 1: Unlock
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid group or pad number
+**/
+EFI_STATUS
+GpioUnlockPadCfgForGroupDw (
+ IN GPIO_GROUP Group,
+ IN UINT32 DwNum,
+ IN UINT32 PadsToUnlock
+ )
+{
+ if (!GpioIsGroupAndDwNumValid (Group, DwNum)) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ return GpioWriteLockReg (
+ GpioPadConfigLockRegister,
+ Group,
+ DwNum,
+ ~PadsToUnlock,
+ 0
+ );
+}
+/**
+ This procedure will clear PadCfgLockTx for selected pads within one group.
+ This function should be used only inside SMI.
+
+ @param[in] Group GPIO group
+ @param[in] DwNum PadCfgLockTx register number for current group.
+ For group which has less then 32 pads per group DwNum must be 0.
+ @param[in] PadsToUnlockTx Bitmask for pads which are going to be unlocked,
+ Bit position - PadNumber
+ Bit value - 0: DoNotUnLockTx, 1: LockTx
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid group or pad number
+**/
+EFI_STATUS
+GpioUnlockPadCfgTxForGroupDw (
+ IN GPIO_GROUP Group,
+ IN UINT32 DwNum,
+ IN UINT32 PadsToUnlockTx
+ )
+{
+ if (!GpioIsGroupAndDwNumValid (Group, DwNum)) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ return GpioWriteLockReg (
+ GpioPadLockOutputRegister,
+ Group,
+ DwNum,
+ ~PadsToUnlockTx,
+ 0
+ );
+}
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/Library/PeiDxeSmmGpioLib/GpioLibrary.h b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/Library/PeiDxeSmmGpioLib/GpioLibrary.h
new file mode 100644
index 0000000000..2c2b4ee75c
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/Library/PeiDxeSmmGpioLib/GpioLibrary.h
@@ -0,0 +1,29 @@
+/** @file
+ Header file for GPIO Lib implementation.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _GPIO_LIBRARY_H_
+#define _GPIO_LIBRARY_H_
+
+#include <Base.h>
+#include <Uefi/UefiBaseType.h>
+#include <Library/IoLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/GpioLib.h>
+#include <Library/GpioNativeLib.h>
+#include <Library/GpioPrivateLib.h>
+#include <Library/PchInfoLib.h>
+#include <Library/PchCycleDecodingLib.h>
+#include <Library/PmcPrivateLib.h>
+#include <Library/GpioHelpersLib.h>
+#include <Register/GpioRegs.h>
+
+//
+// Number of PADCFG_DW registers
+//
+#define GPIO_PADCFG_DW_REG_NUMBER 4
+
+#endif // _GPIO_LIBRARY_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/Library/PeiDxeSmmGpioLib/GpioNativeLib.c b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/Library/PeiDxeSmmGpioLib/GpioNativeLib.c
new file mode 100644
index 0000000000..4e4c53e588
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/Library/PeiDxeSmmGpioLib/GpioNativeLib.c
@@ -0,0 +1,177 @@
+/** @file
+ This file contains routines for GPIO native and chipset specific usage
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#include "GpioLibrary.h"
+
+/**
+ This procedure will get number of pads for certain GPIO group
+
+ @param[in] Group GPIO group number
+
+ @retval Value Pad number for group
+ If illegal group number then return 0
+**/
+UINT32
+GpioGetPadPerGroup (
+ IN GPIO_GROUP Group
+ )
+{
+ CONST GPIO_GROUP_INFO *GpioGroupInfo;
+ UINT32 GpioGroupInfoLength;
+ UINT32 GroupIndex;
+ //
+ // Check if group argument exceeds GPIO GROUP INFO array
+ //
+ GpioGroupInfo = GpioGetGroupInfoTable (&GpioGroupInfoLength);
+ GroupIndex = GpioGetGroupIndexFromGroup (Group);
+
+ if ((UINTN) GroupIndex >= GpioGroupInfoLength) {
+ return 0;
+ } else {
+ return GpioGroupInfo[GroupIndex].PadPerGroup;
+ }
+}
+
+/**
+ This procedure will get number of groups
+
+ @param[in] none
+
+ @retval Value Group number
+**/
+UINT32
+GpioGetNumberOfGroups (
+ VOID
+ )
+{
+ UINT32 GpioGroupInfoLength;
+
+ GpioGetGroupInfoTable (&GpioGroupInfoLength);
+ return GpioGroupInfoLength;
+}
+/**
+ This procedure will get lowest group
+
+ @param[in] none
+
+ @retval Value Lowest Group
+**/
+GPIO_GROUP
+GpioGetLowestGroup (
+ VOID
+ )
+{
+ return GpioGetGroupFromGroupIndex (0);
+}
+/**
+ This procedure will get highest group
+
+ @param[in] none
+
+ @retval Value Highest Group
+**/
+GPIO_GROUP
+GpioGetHighestGroup (
+ VOID
+ )
+{
+ return GpioGetGroupFromGroupIndex (GpioGetNumberOfGroups () - 1);
+}
+
+/**
+ This procedure will get group number
+
+ @param[in] GpioPad Gpio Pad
+
+ @retval Value Group number
+**/
+GPIO_GROUP
+GpioGetGroupFromGpioPad (
+ IN GPIO_PAD GpioPad
+ )
+{
+ return GPIO_GET_GROUP_FROM_PAD (GpioPad);
+}
+
+/**
+ This procedure will get group index (0 based)
+
+ @param[in] GpioPad Gpio Pad
+
+ @retval Value Group Index
+**/
+UINT32
+GpioGetGroupIndexFromGpioPad (
+ IN GPIO_PAD GpioPad
+ )
+{
+ return (UINT32) GPIO_GET_GROUP_INDEX_FROM_PAD (GpioPad);
+}
+
+/**
+ This procedure will get group index (0 based) from group
+
+ @param[in] GpioGroup Gpio Group
+
+ @retval Value Group Index
+**/
+UINT32
+GpioGetGroupIndexFromGroup (
+ IN GPIO_GROUP GpioGroup
+ )
+{
+ return (UINT32) GPIO_GET_GROUP_INDEX (GpioGroup);
+}
+
+/**
+ This procedure will get group from group index (0 based)
+
+ @param[in] GroupIndex Group Index
+
+ @retval GpioGroup Gpio Group
+**/
+GPIO_GROUP
+GpioGetGroupFromGroupIndex (
+ IN UINT32 GroupIndex
+ )
+{
+ return GPIO_GROUP_DEF (GroupIndex, GpioGetThisChipsetId ());
+}
+
+/**
+ This procedure will get pad number (0 based) from Gpio Pad
+
+ @param[in] GpioPad Gpio Pad
+
+ @retval Value Pad Number
+**/
+UINT32
+GpioGetPadNumberFromGpioPad (
+ IN GPIO_PAD GpioPad
+ )
+{
+ return (UINT32) GPIO_GET_PAD_NUMBER (GpioPad);
+}
+/**
+ This procedure will return GpioPad from Group and PadNumber
+
+ @param[in] Group GPIO group
+ @param[in] PadNumber GPIO PadNumber
+
+ @retval GpioPad GpioPad
+**/
+GPIO_PAD
+GpioGetGpioPadFromGroupAndPadNumber (
+ IN GPIO_GROUP Group,
+ IN UINT32 PadNumber
+ )
+{
+ if (IsPchLp ()) {
+ return GPIO_PAD_DEF (Group,PadNumber);
+ } else {
+ return GPIO_PAD_DEF (Group,PadNumber);
+ }
+}
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/Library/PeiDxeSmmGpioLib/PeiDxeSmmGpioLib.inf b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/Library/PeiDxeSmmGpioLib/PeiDxeSmmGpioLib.inf
new file mode 100644
index 0000000000..21fb4417c1
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/Library/PeiDxeSmmGpioLib/PeiDxeSmmGpioLib.inf
@@ -0,0 +1,44 @@
+## @file
+# Component description file for the PeiDxeSmmGpioLib
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+
+[Defines]
+INF_VERSION = 0x00010017
+BASE_NAME = PeiDxeSmmGpioLib
+FILE_GUID = 16EC5CA8-8195-4847-B6CB-662BD7B763F2
+VERSION_STRING = 1.0
+MODULE_TYPE = BASE
+LIBRARY_CLASS = GpioLib
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = IA32 X64 IPF EBC
+#
+
+
+
+[LibraryClasses]
+BaseLib
+IoLib
+DebugLib
+PrintLib
+PchCycleDecodingLib
+PchSbiAccessLib
+PmcPrivateLib
+GpioPrivateLib
+GpioHelpersLib
+
+[Packages]
+MdePkg/MdePkg.dec
+AlderlakeSiliconPkg/SiPkg.dec
+
+
+[Sources]
+GpioLib.c
+GpioNativeLib.c
+GpioInit.c
+GpioLibrary.h
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/BaseGpioHelpersLibNull/BaseGpioHelpersLibNull.c b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/BaseGpioHelpersLibNull/BaseGpioHelpersLibNull.c
new file mode 100644
index 0000000000..b4b6c14329
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/BaseGpioHelpersLibNull/BaseGpioHelpersLibNull.c
@@ -0,0 +1,51 @@
+/** @file
+ This file contains NULL implementation for GPIO Helpers Lib
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#include <Uefi/UefiBaseType.h>
+#include <Library/GpioConfig.h>
+
+/**
+ This procedure stores GPIO group data about pads which PadConfig needs to be unlocked.
+
+ @param[in] GroupIndex GPIO group index
+ @param[in] DwNum DWORD index for a group.
+ For group which has less then 32 pads per group DwNum must be 0.
+ @param[in] UnlockedPads DWORD bitmask for pads which are going to be left unlocked
+ Bit position - PadNumber
+ Bit value - 0: Skip, 1: Leave unlocked
+
+ @retval Status
+**/
+EFI_STATUS
+GpioStoreGroupDwUnlockPadConfigData (
+ IN UINT32 GroupIndex,
+ IN UINT32 DwNum,
+ IN UINT32 UnlockedPads
+ )
+{
+ return EFI_SUCCESS;
+}
+
+/**
+ This procedure stores GPIO group data about pads which Output state needs to be unlocked.
+
+ @param[in] GroupIndex GPIO group index
+ @param[in] DwNum DWORD index for a group.
+ For group which has less then 32 pads per group DwNum must be 0.
+ @param[in] UnlockedPads DWORD bitmask for pads which are going to be left unlocked
+ Bit position - PadNumber
+ Bit value - 0: Skip, 1: Leave unlocked
+ @retval Status
+**/
+EFI_STATUS
+GpioStoreGroupDwUnlockOutputData (
+ IN UINT32 GroupIndex,
+ IN UINT32 DwNum,
+ IN UINT32 UnlockedPads
+ )
+{
+ return EFI_SUCCESS;
+}
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/BaseGpioHelpersLibNull/BaseGpioHelpersLibNull.inf b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/BaseGpioHelpersLibNull/BaseGpioHelpersLibNull.inf
new file mode 100644
index 0000000000..91d81af4b9
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/BaseGpioHelpersLibNull/BaseGpioHelpersLibNull.inf
@@ -0,0 +1,25 @@
+## @file
+# Component description file for the NULL GpioHelpersLib
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+
+[Defines]
+INF_VERSION = 0x00010017
+BASE_NAME = BaseGpioHelpersLib
+FILE_GUID = AB282608-2A50-4AE3-9242-64064ECF40D4
+VERSION_STRING = 1.0
+MODULE_TYPE = BASE
+LIBRARY_CLASS = GpioHelpersLib
+
+
+[Packages]
+MdePkg/MdePkg.dec
+AlderlakeSiliconPkg/SiPkg.dec
+
+
+[Sources]
+BaseGpioHelpersLibNull.c
+
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiDxeSmmGpioPrivateLib/GpioNativePrivateLibInternal.h b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiDxeSmmGpioPrivateLib/GpioNativePrivateLibInternal.h
new file mode 100644
index 0000000000..480990cb62
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiDxeSmmGpioPrivateLib/GpioNativePrivateLibInternal.h
@@ -0,0 +1,48 @@
+/** @file
+ Header file for GPIO Private Lib Internal functions.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _GPIO_NATIVE_PRIVATE_LIB_INTERNAL_H_
+#define _GPIO_NATIVE_PRIVATE_LIB_INTERNAL_H_
+
+#include <Library/GpioPrivateLib.h>
+
+
+/**
+ This function provides recommended GPIO IO Standby configuration for a given native function
+
+ @param[in] PadFunction PadFunction for a specific native signal. Please refer to GpioNativePads.h
+ @param[out] StandbyState IO Standby State for specified native function
+ @param[out] StandbyTerm IO Standby Termination for specified native function
+
+ @retval Status
+**/
+EFI_STATUS
+GpioGetFunctionIoStandbyConfig (
+ IN UINT32 PadFunction,
+ OUT GPIO_IOSTANDBY_STATE *StandbyState,
+ OUT GPIO_IOSTANDBY_TERM *StandbyTerm
+ );
+
+/**
+ This procedure will calculate PADCFG register value based on GpioConfig data
+ For physical/local/hard (not virtual) GPIO pads
+
+ @param[in] GpioPad GPIO Pad
+ @param[in] GpioConfig GPIO Configuration data
+ @param[out] PadCfgDwReg PADCFG DWx register value
+ @param[out] PadCfgDwRegMask Mask with PADCFG DWx register bits to be modified
+
+ @retval Status
+**/
+EFI_STATUS
+GpioPadCfgRegValueFromGpioConfigHardGpio (
+ IN GPIO_PAD GpioPad,
+ IN CONST GPIO_CONFIG *GpioConfig,
+ OUT UINT32 *PadCfgDwReg,
+ OUT UINT32 *PadCfgDwRegMask
+ );
+
+#endif // _GPIO_NATIVE_PRIVATE_LIB_INTERNAL_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiDxeSmmGpioPrivateLib/GpioPrivateLib.c b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiDxeSmmGpioPrivateLib/GpioPrivateLib.c
new file mode 100644
index 0000000000..7d5fa9fafd
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiDxeSmmGpioPrivateLib/GpioPrivateLib.c
@@ -0,0 +1,267 @@
+/** @file
+ This file contains GPIO routines for RC usage
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#include <Base.h>
+#include <Uefi/UefiBaseType.h>
+#include <Library/IoLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/GpioLib.h>
+#include <Library/GpioNativeLib.h>
+#include <Library/GpioPrivateLib.h>
+#include <Library/GpioNativePads.h>
+#include <Register/GpioRegs.h>
+#include "GpioNativePrivateLibInternal.h"
+
+/**
+ This procedure is used to check if GpioPad is valid for certain chipset
+
+ @param[in] GpioPad GPIO pad
+
+ @retval TRUE This pin is valid on this chipset
+ FALSE Incorrect pin
+**/
+BOOLEAN
+GpioIsCorrectPadForThisChipset (
+ IN GPIO_PAD GpioPad
+ )
+{
+ return ((GPIO_GET_CHIPSET_ID (GpioPad) == GpioGetThisChipsetId ()) &&
+ (GpioGetGroupIndexFromGpioPad (GpioPad) < GpioGetNumberOfGroups ()));
+}
+
+/**
+ This procedure is used by PchSmiDispatcher and will return information
+ needed to register GPI SMI.
+
+ @param[in] Index GPI SMI number
+ @param[out] GpioPin GPIO pin
+ @param[out] GpiSmiBitOffset GPI SMI bit position within GpiSmi Registers
+ @param[out] GpiHostSwOwnRegAddress Address of HOSTSW_OWN register
+ @param[out] GpiSmiStsRegAddress Address of GPI SMI status register
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid group or pad number
+**/
+EFI_STATUS
+GpioGetPadAndSmiRegs (
+ IN UINT32 Index,
+ OUT GPIO_PAD *GpioPin,
+ OUT UINT8 *GpiSmiBitOffset,
+ OUT UINT32 *GpiHostSwOwnRegAddress,
+ OUT UINT32 *GpiSmiStsRegAddress
+ )
+{
+ UINT32 GroupIndex;
+ UINT32 PadNumber;
+ CONST GPIO_GROUP_INFO *GpioGroupInfo;
+ GPIO_GROUP GpioGroup;
+ UINT32 GpioGroupInfoLength;
+ UINT32 SmiStsRegOffset;
+ UINT32 HostSwOwnRegOffset;
+ GPIO_PAD_OWN PadOwnVal;
+
+ GpioGroupInfo = GpioGetGroupInfoTable (&GpioGroupInfoLength);
+
+ PadNumber = 0;
+ GroupIndex = 0;
+ for (GroupIndex = 0; GroupIndex < GpioGroupInfoLength; GroupIndex++) {
+ PadNumber = Index;
+ if (PadNumber < GpioGroupInfo[GroupIndex].PadPerGroup) {
+ //
+ // Found group and pad number
+ //
+ break;
+ }
+ Index = Index - GpioGroupInfo[GroupIndex].PadPerGroup;
+ }
+
+ //
+ // Check if legal pad number
+ //
+ if (PadNumber >= GpioGroupInfo[GroupIndex].PadPerGroup){
+ return EFI_INVALID_PARAMETER;
+ }
+
+ //
+ // Check if selected group has GPI SMI Enable and Status registers
+ //
+ if (GpioGroupInfo[GroupIndex].SmiEnOffset == NO_REGISTER_FOR_PROPERTY) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ GpioGroup = GpioGetGroupFromGroupIndex (GroupIndex);
+ *GpioPin = GpioGetGpioPadFromGroupAndPadNumber (GpioGroup, PadNumber);
+
+ DEBUG_CODE_BEGIN ();
+ //
+ // Check if selected GPIO Pad is not owned by CSME/ISH/IE
+ //
+ GpioGetPadOwnership (*GpioPin, &PadOwnVal);
+ if (PadOwnVal != GpioPadOwnHost) {
+ DEBUG ((DEBUG_ERROR, "GPIO ERROR: GPIO not owned by host!\n"));
+ return EFI_INVALID_PARAMETER;
+ }
+ DEBUG_CODE_END ();
+
+ *GpiSmiBitOffset = (UINT8)(PadNumber % 32);
+
+ HostSwOwnRegOffset = GpioGroupInfo[GroupIndex].HostOwnOffset + (PadNumber / 32) * 0x4;
+ *GpiHostSwOwnRegAddress = PCH_PCR_ADDRESS (GpioGroupInfo[GroupIndex].Community, HostSwOwnRegOffset);
+
+ SmiStsRegOffset = GpioGroupInfo[GroupIndex].SmiStsOffset + (PadNumber / 32) * 0x4;
+ *GpiSmiStsRegAddress = PCH_PCR_ADDRESS (GpioGroupInfo[GroupIndex].Community, SmiStsRegOffset);
+
+ return EFI_SUCCESS;
+}
+
+/**
+ This procedure will check if GpioPad argument is valid.
+ Function will check below conditions:
+ - GpioPad represents a pad for current PCH
+ - GpioPad belongs to valid GpioGroup
+ - GPIO PadNumber is not greater than number of pads for this group
+
+ @param[in] GpioPad GPIO pad
+
+ @retval TRUE GPIO pad is valid and can be used with GPIO lib API
+ @retval FALSE GPIO pad is invalid and cannot be used with GPIO lib API
+**/
+BOOLEAN
+GpioIsPadValid (
+ IN GPIO_PAD GpioPad
+ )
+{
+ CONST GPIO_GROUP_INFO *GpioGroupInfo;
+ UINT32 GpioGroupInfoLength;
+ UINT32 PadNumber;
+ UINT32 GroupIndex;
+
+ if (!GpioIsCorrectPadForThisChipset (GpioPad)) {
+ DEBUG ((DEBUG_ERROR, "GPIO ERROR: Incorrect GpioPad (0x%08x) used on this chipset!\n", GpioPad));
+ goto Error;
+ }
+
+ GpioGroupInfo = GpioGetGroupInfoTable (&GpioGroupInfoLength);
+
+ //
+ // Check if legal pin number
+ //
+ GroupIndex = GpioGetGroupIndexFromGpioPad (GpioPad);
+ PadNumber = GpioGetPadNumberFromGpioPad (GpioPad);
+ if (PadNumber >= GpioGroupInfo[GroupIndex].PadPerGroup) {
+ DEBUG ((DEBUG_ERROR, "GPIO ERROR: Pin number (%d) exceeds range of group (max: %d)\n",
+ PadNumber,
+ GpioGroupInfo[GroupIndex].PadPerGroup));
+ goto Error;
+ }
+
+ return TRUE;
+Error:
+ ASSERT (FALSE);
+ return FALSE;
+}
+
+/**
+ This procedure will read GPIO Pad Configuration register
+
+ @param[in] GpioPad GPIO pad
+ @param[in] DwReg Choose PADCFG register: 0:DW0, 1:DW1
+
+ @retval PadCfgRegValue PADCFG_DWx value
+**/
+UINT32
+GpioReadPadCfgReg (
+ IN GPIO_PAD GpioPad,
+ IN UINT8 DwReg
+ )
+{
+ UINT32 PadCfgReg;
+ CONST GPIO_GROUP_INFO *GpioGroupInfo;
+ UINT32 GpioGroupInfoLength;
+ UINT32 GroupIndex;
+
+ GroupIndex = GpioGetGroupIndexFromGpioPad (GpioPad);
+ GpioGroupInfo = GpioGetGroupInfoTable (&GpioGroupInfoLength);
+
+ //
+ // Create Pad Configuration register offset
+ //
+ PadCfgReg = GpioGetGpioPadCfgAddressFromGpioPad (GpioPad, DwReg);
+ return GpioRegisterAccessRead32 (&GpioGroupInfo[GroupIndex], PadCfgReg);
+}
+
+
+/**
+ This procedure will calculate PADCFG register value based on GpioConfig data
+ For physical/local/hard (not virtual) GPIO pads
+
+ @param[in] GpioPad GPIO Pad
+ @param[in] GpioConfig GPIO Configuration data
+ @param[out] PadCfgDwReg PADCFG DWx register value
+ @param[out] PadCfgDwRegMask Mask with PADCFG DWx register bits to be modified
+
+ @retval Status
+**/
+EFI_STATUS
+GpioPadCfgRegValueFromGpioConfigHardGpio (
+ IN GPIO_PAD GpioPad,
+ IN CONST GPIO_CONFIG *GpioConfig,
+ OUT UINT32 *PadCfgDwReg,
+ OUT UINT32 *PadCfgDwRegMask
+ )
+{
+ //
+ // Configure how interrupt is triggered (RxEvCfg)
+ //
+ PadCfgDwRegMask[0] |= ((((GpioConfig->InterruptConfig & B_GPIO_INT_CONFIG_INT_TYPE_MASK) >> N_GPIO_INT_CONFIG_INT_TYPE_BIT_POS) == GpioHardwareDefault) ? 0x0 : B_GPIO_PCR_RX_LVL_EDG);
+ PadCfgDwReg[0] |= (((GpioConfig->InterruptConfig & B_GPIO_INT_CONFIG_INT_TYPE_MASK) >> (N_GPIO_INT_CONFIG_INT_TYPE_BIT_POS + 1)) << N_GPIO_PCR_RX_LVL_EDG);
+
+ //
+ // Configure interrupt generation (GPIRoutIOxAPIC/SCI/SMI/NMI)
+ //
+ PadCfgDwRegMask[0] |= ((((GpioConfig->InterruptConfig & B_GPIO_INT_CONFIG_INT_SOURCE_MASK) >> N_GPIO_INT_CONFIG_INT_SOURCE_BIT_POS) == GpioHardwareDefault) ? 0x0 : (B_GPIO_PCR_RX_NMI_ROUTE | B_GPIO_PCR_RX_SCI_ROUTE | B_GPIO_PCR_RX_SMI_ROUTE | B_GPIO_PCR_RX_APIC_ROUTE));
+ PadCfgDwReg[0] |= (((GpioConfig->InterruptConfig & B_GPIO_INT_CONFIG_INT_SOURCE_MASK) >> (N_GPIO_INT_CONFIG_INT_SOURCE_BIT_POS + 1)) << N_GPIO_PCR_RX_NMI_ROUTE);
+
+ //
+ // Configure GPIO direction (GPIORxDis and GPIOTxDis)
+ //
+ PadCfgDwRegMask[0] |= ((((GpioConfig->Direction & B_GPIO_DIRECTION_DIR_MASK) >> N_GPIO_DIRECTION_DIR_BIT_POS) == GpioHardwareDefault) ? 0x0 : (B_GPIO_PCR_RXDIS | B_GPIO_PCR_TXDIS));
+ PadCfgDwReg[0] |= (((GpioConfig->Direction & B_GPIO_DIRECTION_DIR_MASK) >> (N_GPIO_DIRECTION_DIR_BIT_POS + 1)) << N_GPIO_PCR_TXDIS);
+
+ //
+ // Configure GPIO input inversion (RXINV)
+ //
+ PadCfgDwRegMask[0] |= ((((GpioConfig->Direction & B_GPIO_DIRECTION_INV_MASK) >> N_GPIO_DIRECTION_INV_BIT_POS) == GpioHardwareDefault) ? 0x0 : B_GPIO_PCR_RXINV);
+ PadCfgDwReg[0] |= (((GpioConfig->Direction & B_GPIO_DIRECTION_INV_MASK) >> (N_GPIO_DIRECTION_INV_BIT_POS + 1)) << N_GPIO_PCR_RXINV);
+
+ //
+ // Configure GPIO output state (GPIOTxState)
+ //
+ PadCfgDwRegMask[0] |= ((((GpioConfig->OutputState & B_GPIO_OUTPUT_MASK) >> N_GPIO_OUTPUT_BIT_POS) == GpioHardwareDefault) ? 0x0 : B_GPIO_PCR_TX_STATE);
+ PadCfgDwReg[0] |= (((GpioConfig->OutputState & B_GPIO_OUTPUT_MASK) >> (N_GPIO_OUTPUT_BIT_POS + 1)) << N_GPIO_PCR_TX_STATE);
+
+ //
+ // Configure GPIO RX raw override to '1' (RXRAW1)
+ //
+ PadCfgDwRegMask[0] |= ((((GpioConfig->OtherSettings & B_GPIO_OTHER_CONFIG_RXRAW_MASK) >> N_GPIO_OTHER_CONFIG_RXRAW_BIT_POS) == GpioHardwareDefault) ? 0x0 : B_GPIO_PCR_RX_RAW1);
+ PadCfgDwReg[0] |= (((GpioConfig->OtherSettings & B_GPIO_OTHER_CONFIG_RXRAW_MASK) >> (N_GPIO_OTHER_CONFIG_RXRAW_BIT_POS + 1)) << N_GPIO_PCR_RX_RAW1);
+
+ //
+ // Configure GPIO Pad Mode (PMode)
+ //
+ PadCfgDwRegMask[0] |= ((((GpioConfig->PadMode & B_GPIO_PAD_MODE_MASK) >> N_GPIO_PAD_MODE_BIT_POS) == GpioHardwareDefault) ? 0x0 : B_GPIO_PCR_PAD_MODE);
+ PadCfgDwReg[0] |= (((GpioConfig->PadMode & B_GPIO_PAD_MODE_MASK) >> (N_GPIO_PAD_MODE_BIT_POS + 1)) << N_GPIO_PCR_PAD_MODE);
+
+ //
+ // Configure GPIO termination (Term)
+ //
+ PadCfgDwRegMask[1] |= ((((GpioConfig->ElectricalConfig & B_GPIO_ELECTRICAL_CONFIG_TERMINATION_MASK) >> N_GPIO_ELECTRICAL_CONFIG_TERMINATION_BIT_POS) == GpioHardwareDefault) ? 0x0 : B_GPIO_PCR_TERM);
+ PadCfgDwReg[1] |= (((GpioConfig->ElectricalConfig & B_GPIO_ELECTRICAL_CONFIG_TERMINATION_MASK) >> (N_GPIO_ELECTRICAL_CONFIG_TERMINATION_BIT_POS + 1)) << N_GPIO_PCR_TERM);
+
+ return EFI_SUCCESS;
+}
+
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiDxeSmmGpioPrivateLib/GpioPrivateLibPch.c b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiDxeSmmGpioPrivateLib/GpioPrivateLibPch.c
new file mode 100644
index 0000000000..3d16fd2acd
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiDxeSmmGpioPrivateLib/GpioPrivateLibPch.c
@@ -0,0 +1,172 @@
+/** @file
+ This file contains hard/physical/local (not virtual) GPIO information
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#include <Uefi/UefiBaseType.h>
+#include <Library/GpioLib.h>
+#include <Library/GpioPrivateLib.h>
+#include <Library/GpioNativeLib.h>
+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+#include <Library/PchSbiAccessLib.h>
+#include <Register/GpioRegs.h>
+#include "GpioNativePrivateLibInternal.h"
+
+/**
+ This procedure calculates Pad Configuration Register DW offset
+
+ @param[in] GpioPad GPIO pad
+ @param[in] DwReg Index of the configuration register
+
+ @retval DW Register offset
+**/
+UINT32
+GpioGetGpioPadCfgAddressFromGpioPad (
+ IN GPIO_PAD GpioPad,
+ IN UINT32 DwReg
+ )
+{
+ UINT32 PadCfgRegAddress;
+ CONST GPIO_GROUP_INFO *GpioGroupInfo;
+ UINT32 GpioGroupInfoLength;
+ UINT32 GroupIndex;
+ UINT32 PadNumber;
+
+ GroupIndex = GpioGetGroupIndexFromGpioPad (GpioPad);
+ PadNumber = GpioGetPadNumberFromGpioPad (GpioPad);
+
+ GpioGroupInfo = GpioGetGroupInfoTable (&GpioGroupInfoLength);
+
+ //
+ // Create Pad Configuration register offset
+ //
+ PadCfgRegAddress = GpioGroupInfo[GroupIndex].PadCfgOffset + DwReg * 4 + S_GPIO_PCR_PADCFG * PadNumber;
+
+ return PadCfgRegAddress;
+}
+
+/**
+ This procedure reads GPIO register
+
+ @param[in] GpioGroupInfo Pointer to GPIO group table info
+ @param[in] Register Register offset
+
+ @retval Register value or "F"s in case of errors
+**/
+UINT32
+GpioRegisterAccessRead32 (
+ IN CONST GPIO_GROUP_INFO *GpioGroupInfo,
+ IN UINT32 Register
+ )
+{
+ return MmioRead32 (PCH_PCR_ADDRESS (GpioGroupInfo->Community, Register));
+}
+
+/**
+ This procedure writes GPIO register
+
+ @param[in] GpioGroupInfo Pointer to GPIO group table info
+ @param[in] Register Register offset
+ @param[in] AndValue And value
+ @param[in] OrValue Or value
+
+ @retval EFI_SUCCESS Operation completed successfully
+**/
+EFI_STATUS
+GpioRegisterAccessAndThenOr32 (
+ IN CONST GPIO_GROUP_INFO *GpioGroupInfo,
+ IN UINT32 Register,
+ IN UINT32 AndValue,
+ IN UINT32 OrValue
+ )
+{
+ MmioAndThenOr32 (
+ PCH_PCR_ADDRESS (GpioGroupInfo->Community, Register),
+ AndValue,
+ OrValue
+ );
+ return EFI_SUCCESS;
+}
+
+/**
+ This procedure will calculate PADCFG register value based on GpioConfig data
+
+ @param[in] GpioPad GPIO Pad
+ @param[in] GpioConfig GPIO Configuration data
+ @param[out] PadCfgDwReg PADCFG DWx register value
+ @param[out] PadCfgDwRegMask Mask with PADCFG DWx register bits to be modified
+
+ @retval Status
+**/
+EFI_STATUS
+GpioPadCfgRegValueFromGpioConfig (
+ IN GPIO_PAD GpioPad,
+ IN CONST GPIO_CONFIG *GpioConfig,
+ OUT UINT32 *PadCfgDwReg,
+ OUT UINT32 *PadCfgDwRegMask
+ )
+{
+ return GpioPadCfgRegValueFromGpioConfigHardGpio (GpioPad, GpioConfig, PadCfgDwReg, PadCfgDwRegMask);
+}
+
+/**
+ This procedure will write GPIO Lock/LockTx register
+ - For PCH SBI message is used.
+
+ @param[in] RegValue GPIO register (Lock or LockTx) value
+ @param[in] RegOffset GPIO register (Lock or LockTx) base offset
+ @param[in] DwNum Register number for current group.
+ For group which has less then 32 pads per group DwNum must be 0.
+ @param[in] GpioGroupInfo Pointer to GPIO group table info
+ @param[in] GroupIndex GPIO group index in the GpioGroupInfo table
+
+ @retval EFI_SUCCESS The function completed successfully
+ EFI_UNSUPPORTED Feature is not supported for this group or pad
+**/
+EFI_STATUS
+GpioInternalWriteLockRegister (
+ IN UINT32 RegValue,
+ IN UINT32 RegOffset,
+ IN UINT32 DwNum,
+ IN CONST GPIO_GROUP_INFO *GpioGroupInfo,
+ IN UINT32 GroupIndex
+ )
+{
+ EFI_STATUS Status;
+ PCH_SBI_OPCODE Opcode;
+ UINT8 Response;
+
+ //
+ // If there are more then 32 pads per group then certain
+ // group information would be split into more then one DWord register.
+ // PadConfigLock and OutputLock registers when used for group containing more than 32 pads
+ // are not placed in a continuous way, e.g:
+ // 0x0 - PadConfigLock_DW0
+ // 0x4 - OutputLock_DW0
+ // 0x8 - PadConfigLock_DW1
+ // 0xC - OutputLock_DW1
+ //
+ RegOffset += DwNum * 0x8;
+
+ if (IsGpioLockOpcodeSupported ()) {
+ Opcode = GpioLockUnlock;
+ } else {
+ Opcode = PrivateControlWrite;
+ }
+
+ Status = PchSbiExecutionEx (
+ GpioGroupInfo[GroupIndex].Community,
+ RegOffset,
+ Opcode,
+ FALSE,
+ 0x000F,
+ 0x0000,
+ 0x0000,
+ &RegValue,
+ &Response
+ );
+ ASSERT_EFI_ERROR (Status);
+ return Status;
+}
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiDxeSmmGpioPrivateLib/GpioPrivateLibVer2.c b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiDxeSmmGpioPrivateLib/GpioPrivateLibVer2.c
new file mode 100644
index 0000000000..1348643553
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiDxeSmmGpioPrivateLib/GpioPrivateLibVer2.c
@@ -0,0 +1,81 @@
+/** @file
+ This file contains VER2 specific GPIO information
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#include <Uefi/UefiBaseType.h>
+#include <Library/DebugLib.h>
+#include <Library/PchInfoLib.h>
+#include <Library/GpioLib.h>
+#include <Library/GpioNativeLib.h>
+#include <Library/GpioNativePads.h>
+#include <Library/GpioPrivateLib.h>
+#include <Library/GpioHelpersLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/IoLib.h>
+#include <Register/GpioRegsVer2.h>
+#include <Register/PchPcrRegs.h>
+#include <Register/GpioRegs.h>
+#include <Pins/GpioPinsVer2Lp.h>
+#include <GpioNativePrivateLibInternal.h>
+#include <Library/PcdLib.h>
+GLOBAL_REMOVE_IF_UNREFERENCED GPIO_GROUP_INFO mPchLpGpioGroupInfo[] = {
+ {PID_GPIOCOM0, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_PAD_OWN, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_HOSTSW_OWN, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_GPI_IS, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_GPI_IE, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_GPI_GPE_STS, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_GPI_GPE_EN, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_SMI_STS, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_SMI_EN, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_NMI_STS, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_NMI_EN, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_PADCFGLOCK, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_PADCFGLOCKTX, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_PADCFG_OFFSET, GPIO_VER2_PCH_LP_GPIO_GPP_B_PAD_MAX}, //TGL PCH-LP GPP_B
+ {PID_GPIOCOM0, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, 0},
+ {PID_GPIOCOM0, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_A_PAD_OWN, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_A_HOSTSW_OWN, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_A_GPI_IS, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_A_GPI_IE, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_A_GPI_GPE_STS, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_A_GPI_GPE_EN, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_A_PADCFGLOCK, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_A_PADCFGLOCKTX, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_A_PADCFG_OFFSET, GPIO_VER2_PCH_LP_GPIO_GPP_A_PAD_MAX}, //TGL PCH-LP GPP_A
+ {PID_GPIOCOM5, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_R_PAD_OWN, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_R_HOSTSW_OWN, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_R_GPI_IS, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_R_GPI_IE, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_R_GPI_GPE_STS, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_R_GPI_GPE_EN, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_R_PADCFGLOCK, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_R_PADCFGLOCKTX, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_R_PADCFG_OFFSET, GPIO_VER2_PCH_LP_GPIO_GPP_R_PAD_MAX}, //TGL PCH-LP GPP_R
+ {PID_GPIOCOM5, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, 0},
+ {PID_GPIOCOM2, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPD_PAD_OWN, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPD_HOSTSW_OWN, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPD_GPI_IS, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPD_GPI_IE, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPD_GPI_GPE_STS, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPD_GPI_GPE_EN, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPD_PADCFGLOCK, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPD_PADCFGLOCKTX, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPD_PADCFG_OFFSET, GPIO_VER2_PCH_LP_GPIO_GPD_PAD_MAX}, //TGL PCH-LP GPD
+ {PID_GPIOCOM1, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_S_PAD_OWN, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_S_HOSTSW_OWN, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_S_GPI_IS, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_S_GPI_IE, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_S_GPI_GPE_STS, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_S_GPI_GPE_EN, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_S_PADCFGLOCK, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_S_PADCFGLOCKTX, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_S_PADCFG_OFFSET, GPIO_VER2_PCH_LP_GPIO_GPP_S_PAD_MAX}, //TGL PCH-LP GPP_S
+ {PID_GPIOCOM1, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_H_PAD_OWN, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_H_HOSTSW_OWN, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_H_GPI_IS, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_H_GPI_IE, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_H_GPI_GPE_STS, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_H_GPI_GPE_EN, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_H_PADCFGLOCK, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_H_PADCFGLOCKTX, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_H_PADCFG_OFFSET, GPIO_VER2_PCH_LP_GPIO_GPP_H_PAD_MAX}, //TGL PCH-LP GPP_H
+ {PID_GPIOCOM1, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_PAD_OWN, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_HOSTSW_OWN, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_GPI_IS, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_GPI_IE, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_GPI_GPE_STS, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_GPI_GPE_EN, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_SMI_STS, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_SMI_EN, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_NMI_STS, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_NMI_EN, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_PADCFGLOCK, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_PADCFGLOCKTX, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_PADCFG_OFFSET, GPIO_VER2_PCH_LP_GPIO_GPP_D_PAD_MAX}, //TGL PCH-LP GPP_D
+ {PID_GPIOCOM1, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, 0},
+ {PID_GPIOCOM1, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, 0},
+ {PID_GPIOCOM4, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_PAD_OWN, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_HOSTSW_OWN, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_GPI_IS, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_GPI_IE, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_GPI_GPE_STS, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_GPI_GPE_EN, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_SMI_STS, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_SMI_EN, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_NMI_STS, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_NMI_EN, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_PADCFGLOCK, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_PADCFGLOCKTX, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_PADCFG_OFFSET, GPIO_VER2_PCH_LP_GPIO_GPP_C_PAD_MAX}, //TGL PCH-LP GPP_C
+ {PID_GPIOCOM4, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_F_PAD_OWN, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_F_HOSTSW_OWN, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_F_GPI_IS, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_F_GPI_IE, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_F_GPI_GPE_STS, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_F_GPI_GPE_EN, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_F_PADCFGLOCK, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_F_PADCFGLOCKTX, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_F_PADCFG_OFFSET, GPIO_VER2_PCH_LP_GPIO_GPP_F_PAD_MAX}, //TGL PCH-LP GPP_F
+ {PID_GPIOCOM4, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, 0},
+ {PID_GPIOCOM4, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_PAD_OWN, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_HOSTSW_OWN, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_GPI_IS, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_GPI_IE, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_GPI_GPE_STS, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_GPI_GPE_EN, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_SMI_STS, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_SMI_EN, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_NMI_STS, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_NMI_EN, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_PADCFGLOCK, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_PADCFGLOCKTX, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_PADCFG_OFFSET, GPIO_VER2_PCH_LP_GPIO_GPP_E_PAD_MAX}, //TGL PCH-LP GPP_E
+};
+
+/**
+ This procedure will retrieve address and length of GPIO info table
+
+ @param[out] GpioGroupInfoTableLength Length of GPIO group table
+
+ @retval Pointer to GPIO group table
+
+**/
+CONST GPIO_GROUP_INFO*
+GpioGetGroupInfoTable (
+ OUT UINT32 *GpioGroupInfoTableLength
+ )
+{
+ *GpioGroupInfoTableLength = ARRAY_SIZE (mPchLpGpioGroupInfo);
+ return mPchLpGpioGroupInfo;
+}
+
+/**
+ Get GPIO Chipset ID specific to PCH generation and series
+**/
+UINT32
+GpioGetThisChipsetId (
+ VOID
+ )
+{
+ return GPIO_VER2_LP_CHIPSET_ID;
+}
+
+/**
+ Check if 0x13 opcode supported for writing to GPIO lock unlock register
+
+ @retval TRUE It's supported
+ @retval FALSE It's not supported
+**/
+BOOLEAN
+IsGpioLockOpcodeSupported (
+ VOID
+ )
+{
+ return TRUE;
+}
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiDxeSmmGpioPrivateLib/PeiDxeSmmGpioPrivateLibVer2.inf b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiDxeSmmGpioPrivateLib/PeiDxeSmmGpioPrivateLibVer2.inf
new file mode 100644
index 0000000000..2e9a6b7336
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiDxeSmmGpioPrivateLib/PeiDxeSmmGpioPrivateLibVer2.inf
@@ -0,0 +1,40 @@
+## @file
+# Component description file for the PeiDxeSmmGpioPrivateLib
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+[Defines]
+INF_VERSION = 0x00010017
+BASE_NAME = PeiDxeSmmGpioPrivateLibVer2
+FILE_GUID = 680A81B0-A087-4687-B5B4-146DA30042D6
+VERSION_STRING = 1.0
+MODULE_TYPE = BASE
+LIBRARY_CLASS = GpioPrivateLib
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = IA32 X64 IPF EBC
+#
+
+
+[LibraryClasses]
+ BaseLib
+ IoLib
+ DebugLib
+ PmcLib
+ PchInfoLib
+ GpioLib
+ GpioHelpersLib
+
+
+[Packages]
+ MdePkg/MdePkg.dec
+ AlderlakeSiliconPkg/SiPkg.dec
+
+
+[Sources]
+ GpioPrivateLib.c
+ GpioPrivateLibVer2.c
+ GpioPrivateLibPch.c
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiGpioHelpersLib/PeiGpioHelpersLib.c b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiGpioHelpersLib/PeiGpioHelpersLib.c
new file mode 100644
index 0000000000..9d47e6bfd5
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiGpioHelpersLib/PeiGpioHelpersLib.c
@@ -0,0 +1,218 @@
+/** @file
+ This file contains routines for PEI GPIO Helpers Lib
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#include <Library/HobLib.h>
+#include <Base.h>
+#include <Uefi/UefiBaseType.h>
+#include <Library/IoLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/GpioNativeLib.h>
+#include <Library/GpioPrivateLib.h>
+#include <Library/GpioHelpersLib.h>
+#include <Library/PeiServicesLib.h>
+#include <Library/ConfigBlockLib.h>
+#include <Ppi/SiPolicy.h>
+
+extern EFI_GUID gGpioLibUnlockHobGuid;
+
+//
+// GPIO Lock HOB
+// Stores information on GPIO pads that should be left unlocked
+//
+typedef struct {
+ //
+ // GPIO PadConfig unlock data
+ //
+ UINT32 PadConfig;
+ //
+ // GPIO Output unlock data
+ //
+ UINT32 OutputState;
+} GPIO_UNLOCK_HOB_DATA;
+
+/**
+ This procedure will get index of GPIO Unlock HOB structure for selected GroupIndex and DwNum.
+
+ @param[in] GroupIndex GPIO group index
+ @param[in] DwNum DWORD index for a group.
+ For group which has less then 32 pads per group DwNum must be 0.
+
+ @retval GpioUnlockHobIndex
+**/
+STATIC
+UINT32
+GpioUnlockDataIndex (
+ IN UINT32 GroupIndex,
+ IN UINT32 DwNum
+ )
+{
+ UINT32 GpioUnlockDataIndex;
+ UINT32 Index;
+
+ GpioUnlockDataIndex = 0;
+
+ for (Index = 0; Index < GroupIndex; Index++) {
+ GpioUnlockDataIndex += GPIO_GET_DW_NUM (GpioGetPadPerGroup (GpioGetGroupFromGroupIndex (Index))) + 1;
+ }
+
+ GpioUnlockDataIndex += DwNum;
+ return GpioUnlockDataIndex;
+}
+
+/**
+ This procedure will create GPIO HOB for storing unlock data
+
+ @retval Pointer to GPIO Unlock data structure
+**/
+STATIC
+GPIO_UNLOCK_HOB_DATA*
+GpioCreateUnlockData (
+ VOID
+ )
+{
+ VOID *HobData;
+ GPIO_GROUP Group;
+ GPIO_GROUP GroupMin;
+ GPIO_GROUP GroupMax;
+ UINT32 GpioUnlockDataRecords;
+
+ GroupMin = GpioGetLowestGroup ();
+ GroupMax = GpioGetHighestGroup ();
+ GpioUnlockDataRecords = 0;
+
+ for (Group = GroupMin; Group <= GroupMax; Group++) {
+ GpioUnlockDataRecords += GPIO_GET_DW_NUM (GpioGetPadPerGroup (Group)) + 1;
+ }
+
+ HobData = BuildGuidHob (&gGpioLibUnlockHobGuid, GpioUnlockDataRecords * sizeof (GPIO_UNLOCK_HOB_DATA));
+ if (HobData == NULL) {
+ return NULL;
+ }
+
+ ZeroMem (HobData, GpioUnlockDataRecords * sizeof (GPIO_UNLOCK_HOB_DATA));
+
+ return (GPIO_UNLOCK_HOB_DATA*)HobData;
+}
+
+/**
+ This procedure will Get GPIO Unlock data structure for storing unlock data.
+ If HOB doesn't exist it will be created.
+
+ @param[out] GpioUnlockData pointer to GPIO Unlock data structure
+
+ @retval Length number of GPIO unlock data records
+**/
+STATIC
+UINT32
+GpioGetUnlockData (
+ GPIO_UNLOCK_HOB_DATA **GpioUnlockData
+ )
+{
+ VOID *Hob;
+
+ Hob = GetFirstGuidHob (&gGpioLibUnlockHobGuid);
+ if (Hob == NULL) {
+ //
+ // It is the first time this function is used so create the HOB
+ //
+ *GpioUnlockData = GpioCreateUnlockData ();
+ if (*GpioUnlockData == NULL) {
+ return 0;
+ }
+ Hob = GetFirstGuidHob (&gGpioLibUnlockHobGuid);
+ } else {
+ *GpioUnlockData = (GPIO_UNLOCK_HOB_DATA*) GET_GUID_HOB_DATA (Hob);
+ }
+ return GET_GUID_HOB_DATA_SIZE (Hob) / sizeof (GPIO_UNLOCK_HOB_DATA);
+}
+
+/**
+ This procedure stores GPIO group data about pads which PadConfig needs to be unlocked.
+
+ @param[in] GroupIndex GPIO group index
+ @param[in] DwNum DWORD index for a group.
+ For group which has less then 32 pads per group DwNum must be 0.
+ @param[in] UnlockedPads DWORD bitmask for pads which are going to be left unlocked
+ Bit position - PadNumber
+ Bit value - 0: Skip, 1: Leave unlocked
+
+ @retval Status
+**/
+EFI_STATUS
+GpioStoreGroupDwUnlockPadConfigData (
+ IN UINT32 GroupIndex,
+ IN UINT32 DwNum,
+ IN UINT32 UnlockedPads
+ )
+{
+ GPIO_UNLOCK_HOB_DATA *GpioUnlockData;
+ UINT32 Length;
+ UINT32 Index;
+
+ if (UnlockedPads == 0) {
+ //
+ // No pads to be left unlocked
+ //
+ return EFI_SUCCESS;
+ }
+
+ Length = GpioGetUnlockData (&GpioUnlockData);
+ if (Length == 0) {
+ return EFI_NOT_FOUND;
+ }
+
+ Index = GpioUnlockDataIndex (GroupIndex, DwNum);
+ if (Index >= Length) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ GpioUnlockData[Index].PadConfig |= UnlockedPads;
+ return EFI_SUCCESS;
+}
+
+/**
+ This procedure stores GPIO group data about pads which Output state needs to be unlocked.
+
+ @param[in] GroupIndex GPIO group index
+ @param[in] DwNum DWORD index for a group.
+ For group which has less then 32 pads per group DwNum must be 0.
+ @param[in] UnlockedPads DWORD bitmask for pads which are going to be left unlocked
+ Bit position - PadNumber
+ Bit value - 0: Skip, 1: Leave unlocked
+ @retval Status
+**/
+EFI_STATUS
+GpioStoreGroupDwUnlockOutputData (
+ IN UINT32 GroupIndex,
+ IN UINT32 DwNum,
+ IN UINT32 UnlockedPads
+ )
+{
+ GPIO_UNLOCK_HOB_DATA *GpioUnlockData;
+ UINT32 Length;
+ UINT32 Index;
+
+ if (UnlockedPads == 0) {
+ //
+ // No pads to be left unlocked
+ //
+ return EFI_SUCCESS;
+ }
+
+ Length = GpioGetUnlockData (&GpioUnlockData);
+ if (Length == 0) {
+ return EFI_NOT_FOUND;
+ }
+
+ Index = GpioUnlockDataIndex (GroupIndex, DwNum);
+ if (Index >= Length) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ GpioUnlockData[Index].OutputState |= UnlockedPads;
+ return EFI_SUCCESS;
+}
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiGpioHelpersLib/PeiGpioHelpersLib.inf b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiGpioHelpersLib/PeiGpioHelpersLib.inf
new file mode 100644
index 0000000000..c1886b22f9
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiGpioHelpersLib/PeiGpioHelpersLib.inf
@@ -0,0 +1,46 @@
+## @file
+# Component description file for the PeiGpioHelpersLib
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+
+[Defines]
+INF_VERSION = 0x00010017
+BASE_NAME = PeiGpioHelpersLib
+FILE_GUID = 1838E1E7-3CC4-4A74-90D9-B421EF2A579F
+VERSION_STRING = 1.0
+MODULE_TYPE = PEIM
+LIBRARY_CLASS = GpioHelpersLib
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = IA32 X64 IPF EBC
+#
+
+
+[LibraryClasses]
+BaseLib
+IoLib
+DebugLib
+HobLib
+GpioLib
+ConfigBlockLib
+PeiServicesLib
+
+
+[Packages]
+MdePkg/MdePkg.dec
+AlderlakeSiliconPkg/SiPkg.dec
+
+
+[Sources]
+PeiGpioHelpersLib.c
+
+
+[Guids]
+gGpioLibUnlockHobGuid
+
+[Ppis]
+gSiPreMemPolicyPpiGuid
--
2.36.1.windows.1
-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#108737): https://edk2.groups.io/g/devel/message/108737
Mute This Topic: https://groups.io/mt/101373944/7686176
Group Owner: devel+owner@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [rebecca@openfw.io]
-=-=-=-=-=-=-=-=-=-=-=-
^ permalink raw reply related [flat|nested] 41+ messages in thread
* Re: [edk2-devel] [PATCH v2 02/10] AlderlakeSiliconPkg/IpBlock: Add Graphics, HostBridge, PcieRp components
2023-09-15 4:45 ` [edk2-devel] [PATCH v2 02/10] AlderlakeSiliconPkg/IpBlock: Add Graphics, HostBridge, PcieRp components Saloni Kasbekar
2023-09-15 5:42 ` Chaganty, Rangasai V
@ 2023-09-15 23:56 ` Nate DeSimone
1 sibling, 0 replies; 41+ messages in thread
From: Nate DeSimone @ 2023-09-15 23:56 UTC (permalink / raw)
To: Kasbekar, Saloni, devel@edk2.groups.io
Cc: Chaganty, Rangasai V, Chuang, Rosen
Acked-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
-----Original Message-----
From: Kasbekar, Saloni <saloni.kasbekar@intel.com>
Sent: Thursday, September 14, 2023 9:46 PM
To: devel@edk2.groups.io
Cc: Kasbekar, Saloni <saloni.kasbekar@intel.com>; Chaganty, Rangasai V <rangasai.v.chaganty@intel.com>; Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>; Chuang, Rosen <rosen.chuang@intel.com>
Subject: [PATCH v2 02/10] AlderlakeSiliconPkg/IpBlock: Add Graphics, HostBridge, PcieRp components
Adds the following modules:
- IpBlock/Graphics/Include
- IpBlock/Graphics/IncludePrivate
- IpBlock/Graphics/Library
- IpBlock/Graphics/LibraryPrivate
- IpBlock/HostBridge/IncludePrivate
- IpBlock/PcieRp/Library
Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Rosen Chuang <rosen.chuang@intel.com>
Signed-off-by: Saloni Kasbekar <saloni.kasbekar@intel.com>
---
.../Include/Ppi/GraphicsPlatformPolicyPpi.h | 76 +++++++++++
.../Library/DxeGraphicsPolicyLib.h | 71 +++++++++++
.../Library/DxeIgdOpRegionInitLib.h | 115 +++++++++++++++++
.../GraphicsInfoLibVer1.c | 52 ++++++++
.../GraphicsInfoLibVer1.inf | 33 +++++
.../DxeGraphicsPolicyLib.c | 116 +++++++++++++++++
.../DxeGraphicsPolicyLib.inf | 36 ++++++
.../DxeIgdOpRegionInit.c | 119 ++++++++++++++++++
.../DxeIgdOpRegionInitLib.inf | 47 +++++++
.../IncludePrivate/HostBridgeDataHob.h | 25 ++++
.../PchPcieRpLibInternal.h | 20 +++
.../PeiDxeSmmPchPcieRpLib/PchPcieRpLibVer2.c | 71 +++++++++++
.../PeiDxeSmmPchPcieRpLibVer2.inf | 37 ++++++
13 files changed, 818 insertions(+)
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/Include/Ppi/GraphicsPlatformPolicyPpi.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/IncludePrivate/Library/DxeGraphicsPolicyLib.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/IncludePrivate/Library/DxeIgdOpRegionInitLib.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/Library/PeiDxeSmmGraphicsInfoLib/GraphicsInfoLibVer1.c
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/Library/PeiDxeSmmGraphicsInfoLib/GraphicsInfoLibVer1.inf
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/LibraryPrivate/DxeGraphicsPolicyLib/DxeGraphicsPolicyLib.c
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/LibraryPrivate/DxeGraphicsPolicyLib/DxeGraphicsPolicyLib.inf
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/LibraryPrivate/DxeIgdOpRegionInitLib/DxeIgdOpRegionInit.c
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/LibraryPrivate/DxeIgdOpRegionInitLib/DxeIgdOpRegionInitLib.inf
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/HostBridge/IncludePrivate/HostBridgeDataHob.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PcieRp/Library/PeiDxeSmmPchPcieRpLib/PchPcieRpLibInternal.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PcieRp/Library/PeiDxeSmmPchPcieRpLib/PchPcieRpLibVer2.c
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PcieRp/Library/PeiDxeSmmPchPcieRpLib/PeiDxeSmmPchPcieRpLibVer2.inf
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/Include/Ppi/GraphicsPlatformPolicyPpi.h b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/Include/Ppi/GraphicsPlatformPolicyPpi.h
new file mode 100644
index 0000000000..a8f67061a5
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/Include/Ppi/Gra
+++ phicsPlatformPolicyPpi.h
@@ -0,0 +1,76 @@
+/** @file
+ The PEI_GRAPHICS_PLATFORM_POLICY_PPI provides platform information to PEI Graphics PEIM.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/
+
+#ifndef _PEI_GRAPHICS_PLATFORM_POLICY_PPI_H_
+#define _PEI_GRAPHICS_PLATFORM_POLICY_PPI_H_
+
+/**
+ Globally unique identifier for PEI platform policy PPI.
+**/
+#define PEI_GRAPHICS_PLATFORM_POLICY_PPI_GUID \ { \
+ 0x4eabcd09, 0x43d3, 0x4b4d, { 0xb7, 0x3d, 0x43, 0xc8, 0xd9, 0x89,
+0x99, 0x5 } \ }
+
+#define PEI_GRAPHICS_PLATFORM_POLICY_REVISION 1
+
+/**
+Pre-declaration of PEI graphics platform policy PPI.
+**/
+typedef struct _PEI_GRAPHICS_PLATFORM_POLICY_PPI
+PEI_GRAPHICS_PLATFORM_POLICY_PPI;
+
+/**
+ Enum defining the different lid status values **/ typedef enum {
+ LidClosed,
+ LidOpen,
+ LidStatusMax
+} LID_STATUS;
+
+/**
+ This function gets the platform lid status for LFP displays.
+
+ @param[out] CurrentLidStatus Output variable to store the lid status.
+
+ @retval EFI_SUCCESS Correct lid status is returned.
+ @retval EFI_UNSUPPORTED Platform does not support lid.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *GET_PLATFORM_LID_STATUS) (
+ OUT LID_STATUS *CurrentLidStatus
+ );
+
+/**
+ This function gets the base address of loaded VBT.
+
+ @param[out] VbtAddress Starting address of the VBT is returned in this parameter.
+ @param[out] VbtSize Size of the VBT is returned in this parameter.
+
+ @retval EFI_SUCCESS If the VBT is loaded and parameters contain valid values.
+ @return Other error codes meaning VBT is not loaded and parameters contain invalid values.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *GET_VBT_DATA) (
+ OUT EFI_PHYSICAL_ADDRESS *VbtAddress,
+ OUT UINT32 *VbtSize
+ );
+
+/**
+ This defines the PEI Graphics Platform Policy PPI structure.
+**/
+struct _PEI_GRAPHICS_PLATFORM_POLICY_PPI {
+ UINT32 Revision; ///< Revision of current implementation.
+ GET_PLATFORM_LID_STATUS GetPlatformLidStatus; ///< Function Pointer for get platform lid status.
+ GET_VBT_DATA GetVbtData; ///< Function pointer for get vbt data.
+};
+
+extern EFI_GUID gPeiGraphicsPlatformPpiGuid;
+
+#endif
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/IncludePrivate/Library/DxeGraphicsPolicyLib.h b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/IncludePrivate/Library/DxeGraphicsPolicyLib.h
new file mode 100644
index 0000000000..0347d4c94c
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/IncludePrivate/
+++ Library/DxeGraphicsPolicyLib.h
@@ -0,0 +1,71 @@
+/** @file
+ Header file for the DXE Graphics Policy Init library.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/ #ifndef
+_DXE_GRAPHICS_POLICY_LIB_H_ #define _DXE_GRAPHICS_POLICY_LIB_H_
+
+#include <Uefi.h>
+#include <Library/DebugLib.h>
+#include <Library/UefiLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/MemoryAllocationLib.h> #include <Protocol/SaPolicy.h>
+#include <ConfigBlock.h> #include <GraphicsConfig.h> #include
+<Library/SiConfigBlockLib.h>
+
+#define WORD_FIELD_VALID_BIT BIT15
+
+extern EFI_GUID gGraphicsDxeConfigGuid;
+
+/**
+ This function prints the Graphics DXE phase policy.
+
+ @param[in] SaPolicy - SA DXE Policy protocol **/ VOID
+GraphicsDxePolicyPrint (
+ IN SA_POLICY_PROTOCOL *SaPolicy
+ );
+
+/**
+ This function Load default Graphics DXE policy.
+
+ @param[in] ConfigBlockPointer The pointer to add Graphics config block
+**/
+VOID
+LoadIgdDxeDefault (
+ IN VOID *ConfigBlockPointer
+ );
+
+
+/**
+ Get DXE Graphics config block table total size.
+
+ @retval Size of DXE Graphics config block table
+**/
+UINT16
+EFIAPI
+GraphicsGetConfigBlockTotalSizeDxe (
+ VOID
+ );
+
+/**
+ GraphicsAddConfigBlocksDxe add all DXE Graphics config block.
+
+ @param[in] ConfigBlockTableAddress The pointer to add SA config blocks
+
+ @retval EFI_SUCCESS The policy default is initialized.
+ @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer
+**/
+EFI_STATUS
+EFIAPI
+GraphicsAddConfigBlocksDxe (
+ IN VOID *ConfigBlockTableAddress
+ );
+
+#endif // _DXE_GRAPHICs_POLICY_LIBRARY_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/IncludePrivate/Library/DxeIgdOpRegionInitLib.h b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/IncludePrivate/Library/DxeIgdOpRegionInitLib.h
new file mode 100644
index 0000000000..02e4988b2b
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/IncludePrivate/
+++ Library/DxeIgdOpRegionInitLib.h
@@ -0,0 +1,115 @@
+/** @file
+ This is part of the implementation of an Intel Graphics drivers
+OpRegion /
+ Software SCI interface between system BIOS, ASL code, and Graphics drivers.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/ #ifndef
+_DXE_IGD_OPREGION_INIT_LIB_H_ #define _DXE_IGD_OPREGION_INIT_LIB_H_
+
+///
+/// Statements that include other header files.
+///
+#include <Uefi.h>
+#include <Uefi/UefiBaseType.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <IndustryStandard/Pci.h>
+#include <Library/ConfigBlockLib.h>
+#include <Library/PciSegmentLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/MemoryAllocationLib.h> #include <Library/IoLib.h>
+#include <Library/DebugLib.h> #include <Library/HobLib.h> #include
+<Library/UefiLib.h> #include <Library/S3BootScriptLib.h> #include
+<Register/IgdRegs.h> #include <SiConfigHob.h> #include
+<Register/SaRegsHostBridge.h> /// /// Driver Consumed Protocol
+Prototypes /// #include <Protocol/PciIo.h> #include
+<Protocol/PciRootBridgeIo.h> #include <Protocol/SaPolicy.h> /// ///
+Driver Produced Protocol Prototypes /// #include
+<Protocol/IgdOpRegion.h>
+
+#pragma pack(push, 1)
+///
+///
+/// OpRegion (Miscellaneous) defines.
+///
+/// OpRegion Header defines.
+///
+typedef UINT16 STRING_REF;
+///
+/// Typedef stuctures
+///
+typedef struct {
+ UINT16 Signature; /// 0xAA55
+ UINT8 Size512;
+ UINT8 Reserved[21];
+ UINT16 PcirOffset;
+ UINT16 VbtOffset;
+} INTEL_VBIOS_OPTION_ROM_HEADER;
+
+typedef struct {
+ UINT32 Signature; /// "PCIR"
+ UINT16 VendorId; /// 0x8086
+ UINT16 DeviceId;
+ UINT16 Reserved0;
+ UINT16 Length;
+ UINT8 Revision;
+ UINT8 ClassCode[3];
+ UINT16 ImageLength;
+ UINT16 CodeRevision;
+ UINT8 CodeType;
+ UINT8 Indicator;
+ UINT16 Reserved1;
+} INTEL_VBIOS_PCIR_STRUCTURE;
+
+typedef struct {
+ UINT8 HeaderSignature[20];
+ UINT16 HeaderVersion;
+ UINT16 HeaderSize;
+ UINT16 HeaderVbtSize;
+ UINT8 HeaderVbtCheckSum;
+ UINT8 HeaderReserved;
+ UINT32 HeaderOffsetVbtDataBlock;
+ UINT32 HeaderOffsetAim1;
+ UINT32 HeaderOffsetAim2;
+ UINT32 HeaderOffsetAim3;
+ UINT32 HeaderOffsetAim4;
+ UINT8 DataHeaderSignature[16];
+ UINT16 DataHeaderVersion;
+ UINT16 DataHeaderSize;
+ UINT16 DataHeaderDataBlockSize;
+ UINT8 CoreBlockId;
+ UINT16 CoreBlockSize;
+ UINT16 CoreBlockBiosSize;
+ UINT8 CoreBlockBiosType;
+ UINT8 CoreBlockReleaseStatus;
+ UINT8 CoreBlockHWSupported;
+ UINT8 CoreBlockIntegratedHW;
+ UINT8 CoreBlockBiosBuild[4];
+ UINT8 CoreBlockBiosSignOn[155];
+} VBIOS_VBT_STRUCTURE;
+#pragma pack(pop)
+///
+/// Driver Private Function definitions ///
+
+/**
+ Update Graphics OpRegion after PCI enumeration.
+
+ @retval EFI_SUCCESS - The function completed successfully.
+**/
+EFI_STATUS
+UpdateIgdOpRegionEndOfDxe (
+ VOID
+ );
+#endif
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/Library/PeiDxeSmmGraphicsInfoLib/GraphicsInfoLibVer1.c b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/Library/PeiDxeSmmGraphicsInfoLib/GraphicsInfoLibVer1.c
new file mode 100644
index 0000000000..9dd9b33a49
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/Library/PeiDxeS
+++ mmGraphicsInfoLib/GraphicsInfoLibVer1.c
@@ -0,0 +1,52 @@
+/** @file
+ Source file for common Graphics Info Lib.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/ #include
+<Library/GraphicsInfoLib.h> #include <Register/IgdRegs.h> #include
+<Library/TimerLib.h> #include <Base.h>
+
+/**
+ GetIgdBusNumber: Get IGD Bus Number
+
+ @retval PCI bus number for IGD
+**/
+UINT8
+GetIgdBusNumber (
+ VOID
+ )
+{
+ return (UINT8) IGD_BUS_NUM;
+}
+
+/**
+ GetIgdDevNumber: Get IGD Dev Number
+
+ @retval PCI dev number for IGD
+**/
+UINT8
+GetIgdDevNumber (
+ VOID
+ )
+{
+ return (UINT8) IGD_DEV_NUM;
+}
+
+/**
+ GetIgdFunNumber: Get IGD Fun Number
+
+ @retval PCI fun number for IGD
+**/
+UINT8
+GetIgdFuncNumber (
+ VOID
+ )
+{
+ return (UINT8) IGD_FUN_NUM;
+}
+
+
+
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/Library/PeiDxeSmmGraphicsInfoLib/GraphicsInfoLibVer1.inf b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/Library/PeiDxeSmmGraphicsInfoLib/GraphicsInfoLibVer1.inf
new file mode 100644
index 0000000000..ca363ce105
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/Library/PeiDxeS
+++ mmGraphicsInfoLib/GraphicsInfoLibVer1.inf
@@ -0,0 +1,33 @@
+## @file
+# Graphics information library.
+#
+# All function in this library is available for PEI, DXE, and SMM, #
+But do not support UEFI RUNTIME environment call.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+
+[Defines]
+INF_VERSION = 0x00010017
+BASE_NAME = PeiDxeSmmGraphicsInfoLib
+FILE_GUID = AE4D5DE8-F092-4B2A-8003-F1A4CCBDC3E4
+VERSION_STRING = 1.0
+MODULE_TYPE = BASE
+LIBRARY_CLASS = GraphicsInfoLib
+
+[LibraryClasses]
+BaseLib
+IoLib
+DebugLib
+BaseMemoryLib
+PciSegmentLib
+TimerLib
+
+[Packages]
+MdePkg/MdePkg.dec
+AlderlakeSiliconPkg/SiPkg.dec
+
+[Sources]
+GraphicsInfoLibVer1.c
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/LibraryPrivate/DxeGraphicsPolicyLib/DxeGraphicsPolicyLib.c b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/LibraryPrivate/DxeGraphicsPolicyLib/DxeGraphicsPolicyLib.c
new file mode 100644
index 0000000000..a9344b424d
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/LibraryPrivate/
+++ DxeGraphicsPolicyLib/DxeGraphicsPolicyLib.c
@@ -0,0 +1,116 @@
+/** @file
+ This file provide services for DXE phase Graphics policy default initialization.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/
+
+#include <Library/DxeGraphicsPolicyLib.h>
+
+/**
+ This function prints the Graphics DXE phase policy.
+
+ @param[in] SaPolicy - SA DXE Policy protocol **/ VOID
+GraphicsDxePolicyPrint (
+ IN SA_POLICY_PROTOCOL *SaPolicy
+ )
+{
+ EFI_STATUS Status;
+ GRAPHICS_DXE_CONFIG *GraphicsDxeConfig;
+
+ //
+ // Get requisite IP Config Blocks which needs to be used here //
+ Status = GetConfigBlock ((VOID *) SaPolicy, &gGraphicsDxeConfigGuid,
+ (VOID *)&GraphicsDxeConfig); ASSERT_EFI_ERROR (Status);
+
+
+ DEBUG_CODE_BEGIN ();
+ DEBUG ((DEBUG_INFO, "\n------------------------ Graphics Policy (DXE)
+ print BEGIN -----------------\n")); DEBUG ((DEBUG_INFO, " Revision :
+ %d\n", GraphicsDxeConfig->Header.Revision));
+ ASSERT (GraphicsDxeConfig->Header.Revision ==
+ GRAPHICS_DXE_CONFIG_REVISION); DEBUG ((DEBUG_INFO,
+ "\n------------------------ Graphics Policy (DXE) print END
+ -----------------\n")); DEBUG_CODE_END ();
+
+ return;
+}
+
+
+/**
+ This function Load default Graphics DXE policy.
+
+ @param[in] ConfigBlockPointer The pointer to add Graphics config block
+**/
+VOID
+LoadIgdDxeDefault (
+ IN VOID *ConfigBlockPointer
+ )
+{
+ GRAPHICS_DXE_CONFIG *GraphicsDxeConfig;
+
+ GraphicsDxeConfig = ConfigBlockPointer;
+
+ ///
+ /// Initialize the Graphics configuration
+ ///
+ GraphicsDxeConfig->PlatformConfig = 1;
+ GraphicsDxeConfig->AlsEnable = 2;
+ GraphicsDxeConfig->BacklightControlSupport = 2;
+ GraphicsDxeConfig->IgdBlcConfig = 2;
+ GraphicsDxeConfig->GfxTurboIMON = 31;
+ ///
+ /// <EXAMPLE> Create a static Backlight Brightness Level Duty cycle
+Mapping Table
+ /// Possible 20 entries (example used 11), each 16 bits as follows:
+ /// [15] = Field Valid bit, [14:08] = Level in Percentage (0-64h), [07:00] = Desired duty cycle (0 - FFh).
+ ///
+ GraphicsDxeConfig->BCLM[0] = (0x0000 + WORD_FIELD_VALID_BIT); ///<
+0%
+ GraphicsDxeConfig->BCLM[1] = (0x0A19 + WORD_FIELD_VALID_BIT); ///<
+10%
+ GraphicsDxeConfig->BCLM[2] = (0x1433 + WORD_FIELD_VALID_BIT); ///<
+20%
+ GraphicsDxeConfig->BCLM[3] = (0x1E4C + WORD_FIELD_VALID_BIT); ///<
+30%
+ GraphicsDxeConfig->BCLM[4] = (0x2866 + WORD_FIELD_VALID_BIT); ///<
+40%
+ GraphicsDxeConfig->BCLM[5] = (0x327F + WORD_FIELD_VALID_BIT); ///<
+50%
+ GraphicsDxeConfig->BCLM[6] = (0x3C99 + WORD_FIELD_VALID_BIT); ///<
+60%
+ GraphicsDxeConfig->BCLM[7] = (0x46B2 + WORD_FIELD_VALID_BIT); ///<
+70%
+ GraphicsDxeConfig->BCLM[8] = (0x50CC + WORD_FIELD_VALID_BIT); ///<
+80%
+ GraphicsDxeConfig->BCLM[9] = (0x5AE5 + WORD_FIELD_VALID_BIT); ///<
+90%
+ GraphicsDxeConfig->BCLM[10] = (0x64FF + WORD_FIELD_VALID_BIT); ///<
+100% }
+
+static COMPONENT_BLOCK_ENTRY mGraphicsDxeIpBlocks = {
+ &gGraphicsDxeConfigGuid, sizeof (GRAPHICS_DXE_CONFIG),
+GRAPHICS_DXE_CONFIG_REVISION, LoadIgdDxeDefault};
+
+
+/**
+ Get DXE Graphics config block table total size.
+
+ @retval Size of DXE Graphics config block table
+**/
+UINT16
+EFIAPI
+GraphicsGetConfigBlockTotalSizeDxe (
+ VOID
+ )
+{
+ return mGraphicsDxeIpBlocks.Size;
+}
+
+/**
+ GraphicsAddConfigBlocksDxe add all DXE Graphics config block.
+
+ @param[in] ConfigBlockTableAddress The pointer to add SA config blocks
+
+ @retval EFI_SUCCESS The policy default is initialized.
+ @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer
+**/
+EFI_STATUS
+EFIAPI
+GraphicsAddConfigBlocksDxe (
+ IN VOID *ConfigBlockTableAddress
+ )
+{
+ EFI_STATUS Status;
+ Status = AddComponentConfigBlocks (ConfigBlockTableAddress,
+&mGraphicsDxeIpBlocks, 1);
+ return Status;
+}
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/LibraryPrivate/DxeGraphicsPolicyLib/DxeGraphicsPolicyLib.inf b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/LibraryPrivate/DxeGraphicsPolicyLib/DxeGraphicsPolicyLib.inf
new file mode 100644
index 0000000000..0fd6aba0bb
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/LibraryPrivate/
+++ DxeGraphicsPolicyLib/DxeGraphicsPolicyLib.inf
@@ -0,0 +1,36 @@
+## @file
+# Component description file for the DXE Graphics Policy Init library.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+[Defines]
+INF_VERSION = 0x00010017
+BASE_NAME = DxeGraphicsPolicyLib
+FILE_GUID = C6190599-287E-40F9-9B46-EE112A322EBF
+VERSION_STRING = 1.0
+MODULE_TYPE = BASE
+LIBRARY_CLASS = DxeGraphicsPolicyLib
+
+[LibraryClasses]
+BaseMemoryLib
+UefiRuntimeServicesTableLib
+UefiBootServicesTableLib
+DebugLib
+PostCodeLib
+ConfigBlockLib
+HobLib
+SiConfigBlockLib
+
+[Packages]
+MdePkg/MdePkg.dec
+AlderlakeSiliconPkg/SiPkg.dec
+
+[Sources]
+DxeGraphicsPolicyLib.c
+
+[Guids]
+gGraphicsDxeConfigGuid
+
+[Pcd]
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/LibraryPrivate/DxeIgdOpRegionInitLib/DxeIgdOpRegionInit.c b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/LibraryPrivate/DxeIgdOpRegionInitLib/DxeIgdOpRegionInit.c
new file mode 100644
index 0000000000..b3c9d28078
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/LibraryPrivate/
+++ DxeIgdOpRegionInitLib/DxeIgdOpRegionInit.c
@@ -0,0 +1,119 @@
+/** @file
+ This is part of the implementation of an Intel Graphics drivers
+OpRegion /
+ Software SCI interface between system BIOS, ASL code, and Graphics drivers.
+ The code in this file will load the driver and initialize the
+interface
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/
+
+#include <Library/DxeIgdOpRegionInitLib.h>
+
+
+
+GLOBAL_REMOVE_IF_UNREFERENCED IGD_OPREGION_PROTOCOL mIgdOpRegion;
+
+
+/**
+ Update Graphics OpRegion after PCI enumeration.
+
+ @param[in] void - None
+ @retval EFI_SUCCESS - The function completed successfully.
+**/
+EFI_STATUS
+UpdateIgdOpRegionEndOfDxe (
+ VOID
+)
+{
+ EFI_STATUS Status;
+ UINTN HandleCount;
+ EFI_HANDLE *HandleBuffer;
+ UINTN Index;
+ EFI_PCI_IO_PROTOCOL *PciIo;
+ PCI_TYPE00 Pci;
+ UINTN Segment;
+ UINTN Bus;
+ UINTN Device;
+ UINTN Function;
+
+ Bus = 0;
+ Device = 0;
+ Function = 0;
+
+ DEBUG ((DEBUG_INFO, "UpdateIgdOpRegionEndOfDxe\n"));
+
+ mIgdOpRegion.OpRegion->Header.PCON |= BIT8; //Set External Gfx
+ Adapter field is valid mIgdOpRegion.OpRegion->Header.PCON &= (UINT32)
+ (~BIT7); //Assume No External Gfx Adapter
+
+ ///
+ /// Get all PCI IO protocols handles
+ ///
+ Status = gBS->LocateHandleBuffer (
+ ByProtocol,
+ &gEfiPciIoProtocolGuid,
+ NULL,
+ &HandleCount,
+ &HandleBuffer
+ );
+
+ if (!EFI_ERROR (Status)) {
+ for (Index = 0; Index < HandleCount; Index++) {
+ ///
+ /// Get the PCI IO Protocol Interface corresponding to each handle
+ ///
+ Status = gBS->HandleProtocol (
+ HandleBuffer[Index],
+ &gEfiPciIoProtocolGuid,
+ (VOID **) &PciIo
+ );
+
+ if (!EFI_ERROR (Status)) {
+ ///
+ /// Read the PCI configuration space
+ ///
+ Status = PciIo->Pci.Read (
+ PciIo,
+ EfiPciIoWidthUint32,
+ 0,
+ sizeof (Pci) / sizeof (UINT32),
+ &Pci
+ );
+
+ ///
+ /// Find the display controllers devices
+ ///
+ if (!EFI_ERROR (Status) && IS_PCI_DISPLAY (&Pci)) {
+ Status = PciIo->GetLocation (
+ PciIo,
+ &Segment,
+ &Bus,
+ &Device,
+ &Function
+ );
+
+ //
+ // Assumption: Onboard devices will be sits on Bus no 0, while external devices will be sits on Bus no > 0
+ //
+ if (!EFI_ERROR (Status) && (Bus > 0)) {
+ //External Gfx Adapter Detected and Available
+ DEBUG ((DEBUG_INFO, "PCON - External Gfx Adapter Detected and Available\n"));
+ mIgdOpRegion.OpRegion->Header.PCON |= BIT7;
+ break;
+ }
+ }
+ }
+ }
+ }
+
+ ///
+ /// Free any allocated buffers
+ ///
+ if (HandleBuffer != NULL) {
+ FreePool (HandleBuffer);
+ }
+
+ ///
+ /// Return final status
+ ///
+ return Status;
+}
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/LibraryPrivate/DxeIgdOpRegionInitLib/DxeIgdOpRegionInitLib.inf b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/LibraryPrivate/DxeIgdOpRegionInitLib/DxeIgdOpRegionInitLib.inf
new file mode 100644
index 0000000000..e3a56d5563
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Graphics/LibraryPrivate/
+++ DxeIgdOpRegionInitLib/DxeIgdOpRegionInitLib.inf
@@ -0,0 +1,47 @@
+## @file
+# Component description file for the Dxe IGD OpRegion library.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+[Defines]
+INF_VERSION = 0x00010017
+BASE_NAME = DxeIgdOpRegionInitLib
+FILE_GUID = 18D47D72-555E-475B-A4E4-AD20C3BD8B15
+VERSION_STRING = 1.0
+MODULE_TYPE = DXE_DRIVER
+UEFI_SPECIFICATION_VERSION = 2.00
+LIBRARY_CLASS = DxeIgdOpRegionInitLib
+
+[LibraryClasses]
+UefiLib
+UefiRuntimeServicesTableLib
+UefiBootServicesTableLib
+DebugLib
+PostCodeLib
+ConfigBlockLib
+PciSegmentLib
+BaseMemoryLib
+MemoryAllocationLib
+IoLib
+S3BootScriptLib
+
+[Packages]
+MdePkg/MdePkg.dec
+AlderlakeSiliconPkg/SiPkg.dec
+IntelSiliconPkg/IntelSiliconPkg.dec
+
+[Pcd]
+gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress
+
+[Sources]
+DxeIgdOpRegionInit.c
+
+[Guids]
+gGraphicsDxeConfigGuid ## CONSUMES
+
+[Protocols]
+gIgdOpRegionProtocolGuid ## PRODUCES
+gSaPolicyProtocolGuid ## CONSUMES
+gEfiPciIoProtocolGuid ## CONSUMES
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/HostBridge/IncludePrivate/HostBridgeDataHob.h b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/HostBridge/IncludePrivate/HostBridgeDataHob.h
new file mode 100644
index 0000000000..671e821342
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/HostBridge/IncludePrivat
+++ e/HostBridgeDataHob.h
@@ -0,0 +1,25 @@
+/** @file
+ The GUID definition for Host Bridge Data Hob
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/ #ifndef
+_HOST_BRIDGE_DATA_HOB_H_ #define _HOST_BRIDGE_DATA_HOB_H_
+
+#include <Base.h>
+
+extern EFI_GUID gHostBridgeDataHobGuid; #pragma pack (push,1)
+
+///
+/// Host Bridge Data Hob
+///
+typedef struct {
+ EFI_HOB_GUID_TYPE EfiHobGuidType; ///< GUID Hob type structure for gSaDataHobGuid
+ UINT8 EnableAbove4GBMmio; ///< 0=Disable above 4GB MMIO resource support, 1=Enable above 4GB MMIO resource support
+ BOOLEAN SkipPamLock; ///< 0=All PAM registers will be locked in System Agent code, 1=Do not lock PAM registers in System Agent code.
+ UINT8 Rsvd1[2]; ///< Reserved for future use
+} HOST_BRIDGE_DATA_HOB;
+#pragma pack (pop)
+#endif
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PcieRp/Library/PeiDxeSmmPchPcieRpLib/PchPcieRpLibInternal.h b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PcieRp/Library/PeiDxeSmmPchPcieRpLib/PchPcieRpLibInternal.h
new file mode 100644
index 0000000000..e2be00fae7
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PcieRp/Library/PeiDxeSmm
+++ PchPcieRpLib/PchPcieRpLibInternal.h
@@ -0,0 +1,20 @@
+/** @file
+ PCIE root port library.
+ All function in this library is available for PEI, DXE, and SMM,
+ But do not support UEFI RUNTIME environment call.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/
+
+#ifndef _PCH_PCIE_RP_LIB_INTERNAL_H_
+#define _PCH_PCIE_RP_LIB_INTERNAL_H_
+
+typedef struct {
+ UINT8 DevNum;
+ UINT8 Pid;
+ UINT8 RpNumBase;
+} PCH_PCIE_CONTROLLER_INFO;
+
+#endif
+
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PcieRp/Library/PeiDxeSmmPchPcieRpLib/PchPcieRpLibVer2.c b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PcieRp/Library/PeiDxeSmmPchPcieRpLib/PchPcieRpLibVer2.c
new file mode 100644
index 0000000000..0702792597
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PcieRp/Library/PeiDxeSmm
+++ PchPcieRpLib/PchPcieRpLibVer2.c
@@ -0,0 +1,71 @@
+/** @file
+ PCIE root port library.
+ All function in this library is available for PEI, DXE, and SMM,
+ But do not support UEFI RUNTIME environment call.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/
+
+#include <Base.h>
+#include <Uefi/UefiBaseType.h>
+#include <Library/IoLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseLib.h>
+#include <Library/PciSegmentLib.h>
+#include <Library/PchInfoLib.h>
+#include <Library/PchPcrLib.h>
+#include <Library/PchPcieRpLib.h>
+#include <Register/PchRegs.h>
+#include <PchBdfAssignment.h>
+#include <PchPcieRpInfo.h>
+#include <Register/PchPcieRpRegs.h>
+#include <Register/PchPcrRegs.h>
+
+#include "PchPcieRpLibInternal.h"
+
+GLOBAL_REMOVE_IF_UNREFERENCED PCH_PCIE_CONTROLLER_INFO
+mPchPcieControllerInfo[] = {
+ { PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_1, PID_SPA, 0 },
+ { PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_5, PID_SPB, 4 },
+ { PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_9, PID_SPC, 8 },
+ { PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_13, PID_SPD, 12 },
+ { PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_17, PID_SPE, 16 }, // PCH-H
+only
+ { PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_21, PID_SPF, 20 } // PCH-H
+only };
+
+/**
+ Get Pch Pcie Root Port Device and Function Number by Root Port
+physical Number
+
+ @param[in] RpNumber Root port physical number. (0-based)
+ @param[out] RpDev Return corresponding root port device number.
+ @param[out] RpFun Return corresponding root port function number.
+
+ @retval EFI_SUCCESS Root port device and function is retrieved
+ @retval EFI_INVALID_PARAMETER RpNumber is invalid
+**/
+EFI_STATUS
+EFIAPI
+GetPchPcieRpDevFun (
+ IN UINTN RpNumber,
+ OUT UINTN *RpDev,
+ OUT UINTN *RpFun
+ )
+{
+ UINTN Index;
+ UINTN FuncIndex;
+ UINT32 PciePcd;
+
+ if (RpNumber >= GetPchMaxPciePortNum ()) {
+ DEBUG ((DEBUG_ERROR, "GetPchPcieRpDevFun invalid RpNumber %x", RpNumber));
+ ASSERT (FALSE);
+ return EFI_INVALID_PARAMETER;
+ }
+
+ Index = RpNumber / PCH_PCIE_CONTROLLER_PORTS; FuncIndex = RpNumber -
+ mPchPcieControllerInfo[Index].RpNumBase;
+ *RpDev = mPchPcieControllerInfo[Index].DevNum;
+ PciePcd = PchPcrRead32 (mPchPcieControllerInfo[Index].Pid,
+ R_SPX_PCR_PCD); *RpFun = (PciePcd >> (FuncIndex *
+ S_SPX_PCR_PCD_RP_FIELD)) & B_SPX_PCR_PCD_RP1FN;
+
+ return EFI_SUCCESS;
+}
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PcieRp/Library/PeiDxeSmmPchPcieRpLib/PeiDxeSmmPchPcieRpLibVer2.inf b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PcieRp/Library/PeiDxeSmmPchPcieRpLib/PeiDxeSmmPchPcieRpLibVer2.inf
new file mode 100644
index 0000000000..0acafbfc43
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PcieRp/Library/PeiDxeSmm
+++ PchPcieRpLib/PeiDxeSmmPchPcieRpLibVer2.inf
@@ -0,0 +1,37 @@
+## @file
+# PCIE root port Library.
+#
+# All function in this library is available for PEI, DXE, and SMM, #
+But do not support UEFI RUNTIME environment call.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+
+[Defines]
+INF_VERSION = 0x00010017
+BASE_NAME = PeiDxeSmmPchPcieRpLib
+FILE_GUID = B522981C-E0C5-4E04-A82A-C61D4F0B2C75
+VERSION_STRING = 1.0
+MODULE_TYPE = BASE
+LIBRARY_CLASS = PchPcieRpLib
+
+
+[LibraryClasses]
+BaseLib
+IoLib
+DebugLib
+PciSegmentLib
+PchInfoLib
+PchPcrLib
+
+
+[Packages]
+MdePkg/MdePkg.dec
+AlderlakeSiliconPkg/SiPkg.dec
+
+
+[Sources]
+PchPcieRpLibVer2.c
+
--
2.36.1.windows.1
-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#108738): https://edk2.groups.io/g/devel/message/108738
Mute This Topic: https://groups.io/mt/101373945/7686176
Group Owner: devel+owner@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [rebecca@openfw.io]
-=-=-=-=-=-=-=-=-=-=-=-
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [edk2-devel] [PATCH v2 03/10] AlderlakeSiliconPkg/IpBlock: Add P2sb, PchDmi components
2023-09-15 4:45 ` [edk2-devel] [PATCH v2 03/10] AlderlakeSiliconPkg/IpBlock: Add P2sb, PchDmi components Saloni Kasbekar
2023-09-15 5:42 ` Chaganty, Rangasai V
@ 2023-09-15 23:56 ` Nate DeSimone
1 sibling, 0 replies; 41+ messages in thread
From: Nate DeSimone @ 2023-09-15 23:56 UTC (permalink / raw)
To: Kasbekar, Saloni, devel@edk2.groups.io
Cc: Chaganty, Rangasai V, Chuang, Rosen
Acked-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
-----Original Message-----
From: Kasbekar, Saloni <saloni.kasbekar@intel.com>
Sent: Thursday, September 14, 2023 9:46 PM
To: devel@edk2.groups.io
Cc: Kasbekar, Saloni <saloni.kasbekar@intel.com>; Chaganty, Rangasai V <rangasai.v.chaganty@intel.com>; Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>; Chuang, Rosen <rosen.chuang@intel.com>
Subject: [PATCH v2 03/10] AlderlakeSiliconPkg/IpBlock: Add P2sb, PchDmi components
Adds the following modules:
- IpBlock/P2sb/IncludePrivate
- IpBlock/P2sb/Library
- IpBlock/P2sb/LibraryPrivate
- IpBlock/PchDmi/IncludePrivate
- IpBlock/PchDmi/LibraryPrivate
Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Rosen Chuang <rosen.chuang@intel.com>
Signed-off-by: Saloni Kasbekar <saloni.kasbekar@intel.com>
---
.../Library/P2SbSidebandAccessLib.h | 105 +++++++
.../IncludePrivate/Library/PchSbiAccessLib.h | 58 ++++
.../P2sb/IncludePrivate/P2SbController.h | 32 +++
.../P2sb/IncludePrivate/Register/P2sbRegs.h | 53 ++++
.../Library/PeiDxeSmmPchPcrLib/PchPcrLib.c | 266 ++++++++++++++++++
.../PeiDxeSmmPchPcrLib/PeiDxeSmmPchPcrLib.inf | 35 +++
.../PeiDxeSmmP2SbSidebandAccessLib.c | 208 ++++++++++++++
.../PeiDxeSmmP2SbSidebandAccessLib.inf | 30 ++
.../PchSbiAccessLib.c | 72 +++++
.../PeiDxeSmmPchSbiAccessLib.inf | 35 +++
.../PchDmi/IncludePrivate/Library/PchDmiLib.h | 60 ++++
.../PeiDxeSmmPchDmiLib/PchDmi14.c | 34 +++
.../PeiDxeSmmPchDmiLib/PchDmi14.h | 22 ++
.../PeiDxeSmmPchDmiLib/PchDmiLib.c | 110 ++++++++
.../PeiDxeSmmPchDmiLib/PeiDxeSmmPchDmiLib.inf | 43 +++
15 files changed, 1163 insertions(+)
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/IncludePrivate/Library/P2SbSidebandAccessLib.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/IncludePrivate/Library/PchSbiAccessLib.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/IncludePrivate/P2SbController.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/IncludePrivate/Register/P2sbRegs.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/Library/PeiDxeSmmPchPcrLib/PchPcrLib.c
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/Library/PeiDxeSmmPchPcrLib/PeiDxeSmmPchPcrLib.inf
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/LibraryPrivate/PeiDxeSmmP2SbSidebandAccessLib/PeiDxeSmmP2SbSidebandAccessLib.c
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/LibraryPrivate/PeiDxeSmmP2SbSidebandAccessLib/PeiDxeSmmP2SbSidebandAccessLib.inf
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/LibraryPrivate/PeiDxeSmmPchSbiAccessLib/PchSbiAccessLib.c
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/LibraryPrivate/PeiDxeSmmPchSbiAccessLib/PeiDxeSmmPchSbiAccessLib.inf
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PchDmi/IncludePrivate/Library/PchDmiLib.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivate/PeiDxeSmmPchDmiLib/PchDmi14.c
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivate/PeiDxeSmmPchDmiLib/PchDmi14.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivate/PeiDxeSmmPchDmiLib/PchDmiLib.c
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivate/PeiDxeSmmPchDmiLib/PeiDxeSmmPchDmiLib.inf
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/IncludePrivate/Library/P2SbSidebandAccessLib.h b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/IncludePrivate/Library/P2SbSidebandAccessLib.h
new file mode 100644
index 0000000000..e364508eb4
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/IncludePrivate/Libr
+++ ary/P2SbSidebandAccessLib.h
@@ -0,0 +1,105 @@
+/** @file
+ Header for P2SbSidebandAccessLib
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/
+
+#ifndef _P2SB_SIDEBAND_ACCESS_LIB_H_
+#define _P2SB_SIDEBAND_ACCESS_LIB_H_
+
+#include <RegisterAccess.h>
+#include <P2SbController.h>
+#include <Library/PchPcrLib.h> // For PCH_SBI_PID definition
+
+typedef PCH_SBI_PID P2SB_PID;
+
+typedef enum {
+ P2SbMemory = 0,
+ P2SbPciConfig,
+ P2SbPrivateConfig
+} P2SB_REGISTER_SPACE;
+
+typedef enum {
+ MemoryRead = 0x0,
+ MemoryWrite = 0x1,
+ PciConfigRead = 0x4,
+ PciConfigWrite = 0x5,
+ PrivateControlRead = 0x6,
+ PrivateControlWrite = 0x7,
+ GpioLockUnlock = 0x13
+} P2SB_SBI_OPCODE;
+
+typedef enum {
+ SBI_SUCCESSFUL = 0,
+ SBI_UNSUCCESSFUL = 1,
+ SBI_POWERDOWN = 2,
+ SBI_MIXED = 3,
+ SBI_INVALID_RESPONSE
+} P2SB_SBI_RESPONSE;
+
+typedef enum {
+ P2SbMmioAccess = 0,
+ P2SbMsgAccess
+} P2SB_SIDEBAND_ACCESS_METHOD;
+
+/**
+ REGISTER_ACCESS for P2SB device to support access to sideband registers.
+ Be sure to keep first member of this structure as REGISTER_ACCESS to
+allow
+ for correct casting between caller who sees this structure as
+REGISTER_ACCESS
+ and calle who will cast it to P2SB_SIDEBAND_REGISTER_ACCESS.
+**/
+typedef struct {
+ REGISTER_ACCESS Access;
+ P2SB_SIDEBAND_ACCESS_METHOD AccessMethod;
+ P2SB_PID P2SbPid;
+ UINT16 Fid;
+ P2SB_REGISTER_SPACE RegisterSpace;
+ BOOLEAN PostedWrites;
+ P2SB_CONTROLLER *P2SbCtrl;
+} P2SB_SIDEBAND_REGISTER_ACCESS;
+
+/**
+ Full function for executing P2SB SBI message
+ Take care of that there is no lock protection when using SBI programming in both POST time and SMI.
+ It will clash with POST time SBI programming when SMI happen.
+ Programmer MUST do the save and restore opration while using the
+PchSbiExecution inside SMI
+ to prevent from racing condition.
+ This function will reveal P2SB and hide P2SB if it's originally
+hidden. If more than one SBI access
+ needed, it's better to unhide the P2SB before calling and hide it back after done.
+
+ When the return value is "EFI_SUCCESS", the "Response" do not need to
+ be checked as it would have been SBI_SUCCESS. If the return value is
+ "EFI_DEVICE_ERROR", then this would provide additional information when needed.
+
+ @param[in] P2sbBase P2SB PCI config base
+ @param[in] Pid Port ID of the SBI message
+ @param[in] Offset Offset of the SBI message
+ @param[in] Opcode Opcode
+ @param[in] Posted Posted message
+ @param[in] Fbe First byte enable
+ @param[in] Bar Bar
+ @param[in] Fid Function ID
+ @param[in, out] Data32 Read/Write data
+ @param[out] Response Response
+
+ @retval EFI_SUCCESS Successfully completed.
+ @retval EFI_DEVICE_ERROR Transaction fail
+ @retval EFI_INVALID_PARAMETER Invalid parameter
+ @retval EFI_TIMEOUT Timeout while waiting for response
+**/
+EFI_STATUS
+P2SbSbiExecutionEx (
+ IN UINT64 P2sbBase,
+ IN P2SB_PID Pid,
+ IN UINT64 Offset,
+ IN P2SB_SBI_OPCODE Opcode,
+ IN BOOLEAN Posted,
+ IN UINT16 Fbe,
+ IN UINT16 Bar,
+ IN UINT16 Fid,
+ IN OUT UINT32 *Data32,
+ OUT UINT8 *Response
+ );
+
+#endif
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/IncludePrivate/Library/PchSbiAccessLib.h b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/IncludePrivate/Library/PchSbiAccessLib.h
new file mode 100644
index 0000000000..a46d8fb649
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/IncludePrivate/Libr
+++ ary/PchSbiAccessLib.h
@@ -0,0 +1,58 @@
+/** @file
+ Header file for PchSbiAccessLib.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/ #ifndef
+_PCH_SBI_ACCESS_LIB_H_ #define _PCH_SBI_ACCESS_LIB_H_
+
+#include <Library/PchPcrLib.h>
+#include <Library/P2SbSidebandAccessLib.h>
+
+typedef P2SB_SBI_OPCODE PCH_SBI_OPCODE ;
+
+typedef P2SB_SBI_RESPONSE PCH_SBI_RESPONSE;
+
+/**
+ Full function for executing PCH SBI message
+ Take care of that there is no lock protection when using SBI programming in both POST time and SMI.
+ It will clash with POST time SBI programming when SMI happen.
+ Programmer MUST do the save and restore opration while using the
+PchSbiExecution inside SMI
+ to prevent from racing condition.
+ This function will reveal P2SB and hide P2SB if it's originally
+hidden. If more than one SBI access
+ needed, it's better to unhide the P2SB before calling and hide it back after done.
+
+ When the return value is "EFI_SUCCESS", the "Response" do not need to
+ be checked as it would have been SBI_SUCCESS. If the return value is
+ "EFI_DEVICE_ERROR", then this would provide additional information when needed.
+
+ @param[in] Pid Port ID of the SBI message
+ @param[in] Offset Offset of the SBI message
+ @param[in] Opcode Opcode
+ @param[in] Posted Posted message
+ @param[in] Fbe First byte enable
+ @param[in] Bar Bar
+ @param[in] Fid Function ID
+ @param[in, out] Data32 Read/Write data
+ @param[out] Response Response
+
+ @retval EFI_SUCCESS Successfully completed.
+ @retval EFI_DEVICE_ERROR Transaction fail
+ @retval EFI_INVALID_PARAMETER Invalid parameter
+ @retval EFI_TIMEOUT Timeout while waiting for response
+**/
+EFI_STATUS
+PchSbiExecutionEx (
+ IN PCH_SBI_PID Pid,
+ IN UINT64 Offset,
+ IN PCH_SBI_OPCODE Opcode,
+ IN BOOLEAN Posted,
+ IN UINT16 Fbe,
+ IN UINT16 Bar,
+ IN UINT16 Fid,
+ IN OUT UINT32 *Data32,
+ OUT UINT8 *Response
+ );
+
+#endif // _PCH_SBI_ACCESS_LIB_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/IncludePrivate/P2SbController.h b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/IncludePrivate/P2SbController.h
new file mode 100644
index 0000000000..51c67d4624
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/IncludePrivate/P2Sb
+++ Controller.h
@@ -0,0 +1,32 @@
+/** @file
+ P2SB controller
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/ #ifndef
+_P2SB_CONTROLLER_H_ #define _P2SB_CONTROLLER_H_
+
+/**
+ P2SB structure
+ Stores information required to access to registers
+ like base address, S:B:D:F etc.
+ and definitions specific to P2SB.
+**/
+typedef struct {
+ /**
+ P2SB controller PCI config space address
+ in PCI Segment Library representation.
+ **/
+ UINT64 PciCfgBaseAddr;
+ /**
+ P2SB controller MMIO base address
+ **/
+ UINT64 Mmio;
+ /**
+ HPET MMIO base address
+ **/
+ UINT64 HpetMmio;
+} P2SB_CONTROLLER;
+
+#endif // _P2SB_CONTROLLER_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/IncludePrivate/Register/P2sbRegs.h b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/IncludePrivate/Register/P2sbRegs.h
new file mode 100644
index 0000000000..ffe35411f7
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/IncludePrivate/Regi
+++ ster/P2sbRegs.h
@@ -0,0 +1,53 @@
+/** @file
+ Register names for PCH P2SB device
+
+ Conventions:
+
+ - Register definition format:
+
+ Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_Re
+ gisterName
+ - Prefix:
+ Definitions beginning with "R_" are registers
+ Definitions beginning with "B_" are bits within registers
+ Definitions beginning with "V_" are meaningful values within the bits
+ Definitions beginning with "S_" are register size
+ Definitions beginning with "N_" are the bit position
+ - [GenerationName]:
+ Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc.).
+ Register name without GenerationName applies to all generations.
+ - [ComponentName]:
+ This field indicates the component name that the register belongs to (e.g. PCH, SA etc.)
+ Register name without ComponentName applies to all components.
+ Register that is specific to -H denoted by "_PCH_H_" in component name.
+ Register that is specific to -LP denoted by "_PCH_LP_" in component name.
+ - SubsystemName:
+ This field indicates the subsystem name of the component that the register belongs to
+ (e.g. PCIE, USB, SATA, GPIO, PMC etc.).
+ - RegisterSpace:
+ MEM - MMIO space register of subsystem.
+ IO - IO space register of subsystem.
+ PCR - Private configuration register of subsystem.
+ CFG - PCI configuration space register of subsystem.
+ - RegisterName:
+ Full register name.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/ #ifndef
+_P2SB_REGS_H_ #define _P2SB_REGS_H_
+
+//
+// Definition for SBI
+//
+#define R_P2SB_CFG_SBIADDR 0xD0
+#define R_P2SB_CFG_SBIDATA 0xD4
+#define R_P2SB_CFG_SBISTAT 0xD8
+#define B_P2SB_CFG_SBISTAT_OPCODE 0xFF00
+#define B_P2SB_CFG_SBISTAT_POSTED BIT7
+#define B_P2SB_CFG_SBISTAT_RESPONSE 0x0006
+#define N_P2SB_CFG_SBISTAT_RESPONSE 1
+#define B_P2SB_CFG_SBISTAT_INITRDY BIT0
+#define R_P2SB_CFG_SBIRID 0xDA
+#define R_P2SB_CFG_SBIEXTADDR 0xDC
+
+#endif
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/Library/PeiDxeSmmPchPcrLib/PchPcrLib.c b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/Library/PeiDxeSmmPchPcrLib/PchPcrLib.c
new file mode 100644
index 0000000000..a5b18613bc
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/Library/PeiDxeSmmPc
+++ hPcrLib/PchPcrLib.c
@@ -0,0 +1,266 @@
+/** @file
+ PCH PCR library.
+ All function in this library is available for PEI, DXE, and SMM,
+ But do not support UEFI RUNTIME environment call.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/
+
+#include <Base.h>
+#include <Uefi/UefiBaseType.h>
+#include <Library/IoLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseLib.h>
+#include <Library/PchInfoLib.h>
+#include <Library/PchPcrLib.h>
+#include <Library/PchSbiAccessLib.h>
+#include <Library/PciSegmentLib.h>
+#include <Register/PchPcrRegs.h>
+
+#ifndef MDEPKG_NDEBUG
+/**
+ Checks if the offset is valid for a given memory access width. Offset must align to width size.
+
+ @param[in] Offset Offset of a register
+ @param[in] Size Size of memory access in bytes
+
+ @retval FALSE Offset is not valid for a given memory access
+ @retval TRUE Offset is valid
+**/
+STATIC
+BOOLEAN
+PchIsPcrOffsetValid (
+ IN UINT32 Offset,
+ IN UINTN Size
+ )
+{
+ if (!IsP2sb20bPcrSupported ()) {
+ if (((Offset & (Size - 1)) != 0) || (Offset > 0xFFFF)) {
+ DEBUG ((DEBUG_ERROR, "PCR offset error. Invalid Offset: %x Size: %x", Offset, Size));
+ return FALSE;
+ } else {
+ return TRUE;
+ }
+ } else {
+ if (((Offset & (Size - 1)) != 0) || (Offset > 0xFFFFF)) {
+ DEBUG ((DEBUG_ERROR, "PCR offset error. Invalid Offset: %x Size: %x", Offset, Size));
+ return FALSE;
+ } else {
+ return TRUE;
+ }
+ }
+}
+#endif
+
+/**
+ Read PCR register.
+ It returns PCR register and size in 4bytes.
+ The Offset should not exceed 0xFFFF and must be aligned with size.
+
+ @param[in] Pid Port ID
+ @param[in] Offset Register offset of this Port ID
+
+ @retval UINT32 PCR register value.
+**/
+UINT32
+PchPcrRead32 (
+ IN PCH_SBI_PID Pid,
+ IN UINT32 Offset
+ )
+{
+#ifndef MDEPKG_NDEBUG
+ ASSERT (PchIsPcrOffsetValid (Offset, 4)); #endif
+ return MmioRead32 (PCH_PCR_ADDRESS (Pid, Offset)); }
+
+/**
+ Read PCR register.
+ It returns PCR register and size in 2bytes.
+ The Offset should not exceed 0xFFFF and must be aligned with size.
+
+ @param[in] Pid Port ID
+ @param[in] Offset Register offset of this Port ID
+
+ @retval UINT16 PCR register value.
+**/
+UINT16
+PchPcrRead16 (
+ IN PCH_SBI_PID Pid,
+ IN UINT32 Offset
+ )
+{
+#ifndef MDEPKG_NDEBUG
+ ASSERT (PchIsPcrOffsetValid (Offset, 2)); #endif
+ return MmioRead16 (PCH_PCR_ADDRESS (Pid, Offset)); }
+
+/**
+ Read PCR register.
+ It returns PCR register and size in 1bytes.
+ The Offset should not exceed 0xFFFF and must be aligned with size.
+
+ @param[in] Pid Port ID
+ @param[in] Offset Register offset of this Port ID
+
+ @retval UINT8 PCR register value
+**/
+UINT8
+PchPcrRead8 (
+ IN PCH_SBI_PID Pid,
+ IN UINT32 Offset
+ )
+{
+ return MmioRead8 (PCH_PCR_ADDRESS (Pid, Offset)); }
+
+/**
+ Write PCR register.
+ It programs PCR register and size in 4bytes.
+ The Offset should not exceed 0xFFFF and must be aligned with size.
+
+ @param[in] Pid Port ID
+ @param[in] Offset Register offset of Port ID.
+ @param[in] Data Input Data. Must be the same size as Size parameter.
+
+ @retval UINT32 Value written to register
+**/
+UINT32
+PchPcrWrite32 (
+ IN PCH_SBI_PID Pid,
+ IN UINT32 Offset,
+ IN UINT32 Data
+ )
+{
+#ifndef MDEPKG_NDEBUG
+ ASSERT (PchIsPcrOffsetValid (Offset, 4)); #endif
+ MmioWrite32 (PCH_PCR_ADDRESS (Pid, Offset), Data);
+
+ return Data;
+
+}
+
+/**
+ Write PCR register.
+ It programs PCR register and size in 2bytes.
+ The Offset should not exceed 0xFFFF and must be aligned with size.
+
+ @param[in] Pid Port ID
+ @param[in] Offset Register offset of Port ID.
+ @param[in] Data Input Data. Must be the same size as Size parameter.
+
+ @retval UINT16 Value written to register
+**/
+UINT16
+PchPcrWrite16 (
+ IN PCH_SBI_PID Pid,
+ IN UINT32 Offset,
+ IN UINT16 Data
+ )
+{
+#ifndef MDEPKG_NDEBUG
+ ASSERT (PchIsPcrOffsetValid (Offset, 2)); #endif
+ MmioWrite16 (PCH_PCR_ADDRESS (Pid, Offset), Data);
+
+ return Data;
+}
+
+/**
+ Write PCR register.
+ It programs PCR register and size in 1bytes.
+ The Offset should not exceed 0xFFFF and must be aligned with size.
+
+ @param[in] Pid Port ID
+ @param[in] Offset Register offset of Port ID.
+ @param[in] Data Input Data. Must be the same size as Size parameter.
+
+ @retval UINT8 Value written to register
+**/
+UINT8
+PchPcrWrite8 (
+ IN PCH_SBI_PID Pid,
+ IN UINT32 Offset,
+ IN UINT8 Data
+ )
+{
+
+ MmioWrite8 (PCH_PCR_ADDRESS (Pid, Offset), Data);
+
+ return Data;
+}
+
+/**
+ Write PCR register.
+ It programs PCR register and size in 4bytes.
+ The Offset should not exceed 0xFFFF and must be aligned with size.
+
+ @param[in] Pid Port ID
+ @param[in] Offset Register offset of Port ID.
+ @param[in] AndData AND Data. Must be the same size as Size parameter.
+ @param[in] OrData OR Data. Must be the same size as Size parameter.
+
+ @retval UINT32 Value written to register
+
+**/
+UINT32
+PchPcrAndThenOr32 (
+ IN PCH_SBI_PID Pid,
+ IN UINT32 Offset,
+ IN UINT32 AndData,
+ IN UINT32 OrData
+ )
+{
+ return PchPcrWrite32 (Pid, Offset, (PchPcrRead32 (Pid, Offset) &
+AndData) | OrData); }
+
+/**
+ Write PCR register.
+ It programs PCR register and size in 2bytes.
+ The Offset should not exceed 0xFFFF and must be aligned with size.
+
+ @param[in] Pid Port ID
+ @param[in] Offset Register offset of Port ID.
+ @param[in] AndData AND Data. Must be the same size as Size parameter.
+ @param[in] OrData OR Data. Must be the same size as Size parameter.
+
+ @retval UINT16 Value written to register
+
+**/
+UINT16
+PchPcrAndThenOr16 (
+ IN PCH_SBI_PID Pid,
+ IN UINT32 Offset,
+ IN UINT16 AndData,
+ IN UINT16 OrData
+ )
+{
+ return PchPcrWrite16 (Pid, Offset, (PchPcrRead16 (Pid, Offset) &
+AndData) | OrData); }
+
+/**
+ Write PCR register.
+ It programs PCR register and size in 1bytes.
+ The Offset should not exceed 0xFFFF and must be aligned with size.
+
+ @param[in] Pid Port ID
+ @param[in] Offset Register offset of Port ID.
+ @param[in] AndData AND Data. Must be the same size as Size parameter.
+ @param[in] OrData OR Data. Must be the same size as Size parameter.
+
+ @retval UINT8 Value written to register
+
+**/
+UINT8
+PchPcrAndThenOr8 (
+ IN PCH_SBI_PID Pid,
+ IN UINT32 Offset,
+ IN UINT8 AndData,
+ IN UINT8 OrData
+ )
+{
+ return PchPcrWrite8 (Pid, Offset, (PchPcrRead8 (Pid, Offset) &
+AndData) | OrData); }
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/Library/PeiDxeSmmPchPcrLib/PeiDxeSmmPchPcrLib.inf b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/Library/PeiDxeSmmPchPcrLib/PeiDxeSmmPchPcrLib.inf
new file mode 100644
index 0000000000..5e1b4914d8
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/Library/PeiDxeSmmPc
+++ hPcrLib/PeiDxeSmmPchPcrLib.inf
@@ -0,0 +1,35 @@
+## @file
+# PCH PCR Library.
+#
+# All function in this library is available for PEI, DXE, and SMM, #
+But do not support UEFI RUNTIME environment call.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+
+[Defines]
+INF_VERSION = 0x00010017
+BASE_NAME = PeiDxeSmmPchPcrLib
+FILE_GUID = 117C8D19-445B-46BF-B624-109F63709375
+VERSION_STRING = 1.0
+MODULE_TYPE = BASE
+LIBRARY_CLASS = PchPcrLib
+
+
+[LibraryClasses]
+BaseLib
+IoLib
+DebugLib
+PchInfoLib
+PchSbiAccessLib
+PciSegmentLib
+
+[Packages]
+MdePkg/MdePkg.dec
+AlderlakeSiliconPkg/SiPkg.dec
+
+
+[Sources]
+PchPcrLib.c
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/LibraryPrivate/PeiDxeSmmP2SbSidebandAccessLib/PeiDxeSmmP2SbSidebandAccessLib.c b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/LibraryPrivate/PeiDxeSmmP2SbSidebandAccessLib/PeiDxeSmmP2SbSidebandAccessLib.c
new file mode 100644
index 0000000000..52ec8fd9e1
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/LibraryPrivate/PeiD
+++ xeSmmP2SbSidebandAccessLib/PeiDxeSmmP2SbSidebandAccessLib.c
@@ -0,0 +1,208 @@
+/** @file
+ P2SB sideband access lib
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/
+
+#include <Base.h>
+#include <Uefi/UefiBaseType.h>
+#include <Library/IoLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseLib.h>
+#include <Library/PchInfoLib.h>
+#include <Library/P2SbSidebandAccessLib.h> #include
+<Library/PciSegmentLib.h> #include <Library/PchSbiAccessLib.h> #include
+<Register/P2sbRegs.h> #include <IndustryStandard/Pci30.h>
+
+#define P2SB_PCR_ADDRESS(MmioBase, Pid, Offset) ((UINTN) MmioBase |
+(UINT32) (((Offset) & 0x0F0000) << 8) | ((UINT8)(Pid) << 16) | (UINT16)
+((Offset) & 0xFFFF))
+
+/**
+ Full function for executing P2SB SBI message
+ Take care of that there is no lock protection when using SBI programming in both POST time and SMI.
+ It will clash with POST time SBI programming when SMI happen.
+ Programmer MUST do the save and restore opration while using the
+PchSbiExecution inside SMI
+ to prevent from racing condition.
+ This function will reveal P2SB and hide P2SB if it's originally
+hidden. If more than one SBI access
+ needed, it's better to unhide the P2SB before calling and hide it back after done.
+
+ When the return value is "EFI_SUCCESS", the "Response" do not need to
+ be checked as it would have been SBI_SUCCESS. If the return value is
+ "EFI_DEVICE_ERROR", then this would provide additional information when needed.
+
+ @param[in] P2sbBase P2SB PCI config base
+ @param[in] Pid Port ID of the SBI message
+ @param[in] Offset Offset of the SBI message
+ @param[in] Opcode Opcode
+ @param[in] Posted Posted message
+ @param[in] Fbe First byte enable
+ @param[in] Bar Bar
+ @param[in] Fid Function ID
+ @param[in, out] Data32 Read/Write data
+ @param[out] Response Response
+
+ @retval EFI_SUCCESS Successfully completed.
+ @retval EFI_DEVICE_ERROR Transaction fail
+ @retval EFI_INVALID_PARAMETER Invalid parameter
+ @retval EFI_TIMEOUT Timeout while waiting for response
+**/
+EFI_STATUS
+P2SbSbiExecutionEx (
+ IN UINT64 P2sbBase,
+ IN P2SB_PID Pid,
+ IN UINT64 Offset,
+ IN P2SB_SBI_OPCODE Opcode,
+ IN BOOLEAN Posted,
+ IN UINT16 Fbe,
+ IN UINT16 Bar,
+ IN UINT16 Fid,
+ IN OUT UINT32 *Data32,
+ OUT UINT8 *Response
+ )
+{
+ INT32 Timeout;
+ UINT16 SbiStat;
+
+ //
+ // Check opcode valid
+ //
+ switch (Opcode) {
+ case MemoryRead:
+ case MemoryWrite:
+ case PciConfigRead:
+ case PciConfigWrite:
+ case PrivateControlRead:
+ case PrivateControlWrite:
+ case GpioLockUnlock:
+ break;
+ default:
+ return EFI_INVALID_PARAMETER;
+ break;
+ }
+
+ if (PciSegmentRead16 (P2sbBase + PCI_VENDOR_ID_OFFSET) == 0xFFFF) {
+ ASSERT (FALSE);
+ return EFI_DEVICE_ERROR;
+ }
+ ///
+ /// BWG Section 2.2.1
+ /// 1. Poll P2SB PCI offset D8h[0] = 0b /// Make sure the previous
+ opeartion is completed.
+ ///
+ Timeout = 0xFFFFFFF;
+ while (Timeout > 0) {
+ SbiStat = PciSegmentRead16 (P2sbBase + R_P2SB_CFG_SBISTAT);
+ if ((SbiStat & B_P2SB_CFG_SBISTAT_INITRDY) == 0) {
+ break;
+ }
+ Timeout--;
+ }
+ if (Timeout == 0) {
+ return EFI_TIMEOUT;
+ }
+ //
+ // Initial Response status
+ //
+ *Response = SBI_INVALID_RESPONSE;
+ SbiStat = 0;
+ ///
+ /// 2. Write P2SB PCI offset D0h[31:0] with Address and Destination
+ Port ID ///
+ PciSegmentWrite32 (P2sbBase + R_P2SB_CFG_SBIADDR, (UINT32) ((Pid <<
+ 24) | (UINT16) Offset)); /// /// 3. Write P2SB PCI offset DCh[31:0]
+ with extended address, which is expected to be 0 in CNL PCH.
+ ///
+ PciSegmentWrite32 (P2sbBase + R_P2SB_CFG_SBIEXTADDR, (UINT32)
+ RShiftU64 (Offset, 16)); /// /// 5. Set P2SB PCI offset D8h[15:8] =
+ 00000110b for read
+ /// Set P2SB PCI offset D8h[15:8] = 00000111b for write
+ //
+ // Set SBISTAT[15:8] to the opcode passed in // Set SBISTAT[7] to
+ the posted passed in //
+ PciSegmentAndThenOr16 (
+ (P2sbBase + R_P2SB_CFG_SBISTAT),
+ (UINT16) ~(B_P2SB_CFG_SBISTAT_OPCODE | B_P2SB_CFG_SBISTAT_POSTED),
+ (UINT16) ((Opcode << 8) | (Posted << 7))
+ );
+ ///
+ /// 6. Write P2SB PCI offset DAh[15:0] = F000h /// // // Set
+ RID[15:0] = Fbe << 12 | Bar << 8 | Fid //
+ PciSegmentWrite16 (
+ (P2sbBase + R_P2SB_CFG_SBIRID),
+ (((Fbe & 0x000F) << 12) | ((Bar & 0x0007) << 8) | (Fid & 0x00FF))
+ );
+
+ switch (Opcode) {
+ case MemoryWrite:
+ case PciConfigWrite:
+ case PrivateControlWrite:
+ case GpioLockUnlock:
+ ///
+ /// 4. Write P2SB PCI offset D4h[31:0] with the intended data accordingly
+ ///
+ PciSegmentWrite32 ((P2sbBase + R_P2SB_CFG_SBIDATA), *Data32);
+ break;
+ default:
+ ///
+ /// 4. Write P2SB PCI offset D4h[31:0] with dummy data such as 0,
+ /// because all D0-DFh register range must be touched in CNL PCH
+ /// for a successful SBI transaction.
+ ///
+ PciSegmentWrite32 ((P2sbBase + R_P2SB_CFG_SBIDATA), 0);
+ break;
+ }
+ ///
+ /// 7. Set P2SB PCI offset D8h[0] = 1b, Poll P2SB PCI offset D8h[0] =
+0b
+ ///
+ //
+ // Set SBISTAT[0] = 1b, trigger the SBI operation
+ //
+ PciSegmentOr16 (P2sbBase + R_P2SB_CFG_SBISTAT, (UINT16)
+B_P2SB_CFG_SBISTAT_INITRDY);
+ //
+ // Poll SBISTAT[0] = 0b, Polling for Busy bit
+ //
+ Timeout = 0xFFFFFFF;
+ while (Timeout > 0) {
+ SbiStat = PciSegmentRead16 (P2sbBase + R_P2SB_CFG_SBISTAT);
+ if ((SbiStat & B_P2SB_CFG_SBISTAT_INITRDY) == 0) {
+ break;
+ }
+ Timeout--;
+ }
+ if (Timeout == 0) {
+ //
+ // If timeout, it's fatal error.
+ //
+ return EFI_TIMEOUT;
+ } else {
+ ///
+ /// 8. Check if P2SB PCI offset D8h[2:1] = 00b for successful transaction
+ ///
+ *Response = (UINT8) ((SbiStat & B_P2SB_CFG_SBISTAT_RESPONSE) >> N_P2SB_CFG_SBISTAT_RESPONSE);
+ if (*Response == SBI_SUCCESSFUL) {
+ switch (Opcode) {
+ case MemoryRead:
+ case PciConfigRead:
+ case PrivateControlRead:
+ ///
+ /// 9. Read P2SB PCI offset D4h[31:0] for SBI data
+ ///
+ *Data32 = PciSegmentRead32 (P2sbBase + R_P2SB_CFG_SBIDATA);
+ break;
+ default:
+ break;
+ }
+ return EFI_SUCCESS;
+ } else if (*Response == SBI_POWERDOWN) {
+ return EFI_NO_RESPONSE;
+ } else {
+ return EFI_DEVICE_ERROR;
+ }
+ }
+}
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/LibraryPrivate/PeiDxeSmmP2SbSidebandAccessLib/PeiDxeSmmP2SbSidebandAccessLib.inf b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/LibraryPrivate/PeiDxeSmmP2SbSidebandAccessLib/PeiDxeSmmP2SbSidebandAccessLib.inf
new file mode 100644
index 0000000000..9530e56940
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/LibraryPrivate/PeiD
+++ xeSmmP2SbSidebandAccessLib/PeiDxeSmmP2SbSidebandAccessLib.inf
@@ -0,0 +1,30 @@
+## @file
+# Library for accessing sideband register banks via the P2SB router.
+#
+# All function in this library is available for PEI, DXE, and SMM, #
+But do not support UEFI RUNTIME environment call.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+
+[Defines]
+INF_VERSION = 0x00010017
+BASE_NAME = PeiDxeSmmP2SbSidebandAccessLib FILE_GUID =
+425C479D-A489-4382-8C28-59A3521A24FF
+VERSION_STRING = 1.0
+MODULE_TYPE = BASE
+LIBRARY_CLASS = P2SbSidebandAccessLib
+
+[LibraryClasses]
+BaseLib
+IoLib
+DebugLib
+
+[Packages]
+MdePkg/MdePkg.dec
+AlderlakeSiliconPkg/SiPkg.dec
+
+[Sources]
+PeiDxeSmmP2SbSidebandAccessLib.c
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/LibraryPrivate/PeiDxeSmmPchSbiAccessLib/PchSbiAccessLib.c b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/LibraryPrivate/PeiDxeSmmPchSbiAccessLib/PchSbiAccessLib.c
new file mode 100644
index 0000000000..1f7bb82692
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/LibraryPrivate/PeiD
+++ xeSmmPchSbiAccessLib/PchSbiAccessLib.c
@@ -0,0 +1,72 @@
+/** @file
+ PCH SBI access library.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/
+
+#include <Base.h>
+#include <Uefi/UefiBaseType.h>
+#include <Library/IoLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseLib.h>
+#include <Library/PchSbiAccessLib.h>
+#include <Library/P2SbSidebandAccessLib.h> #include
+<Library/PchPciBdfLib.h> #include <Register/PchRegs.h> #include
+<Register/P2sbRegs.h>
+
+/**
+ Full function for executing PCH SBI message
+ Take care of that there is no lock protection when using SBI programming in both POST time and SMI.
+ It will clash with POST time SBI programming when SMI happen.
+ Programmer MUST do the save and restore opration while using the
+PchSbiExecution inside SMI
+ to prevent from racing condition.
+ This function will reveal P2SB and hide P2SB if it's originally
+hidden. If more than one SBI access
+ needed, it's better to unhide the P2SB before calling and hide it back after done.
+
+ When the return value is "EFI_SUCCESS", the "Response" do not need to
+ be checked as it would have been SBI_SUCCESS. If the return value is
+ "EFI_DEVICE_ERROR", then this would provide additional information when needed.
+
+ @param[in] Pid Port ID of the SBI message
+ @param[in] Offset Offset of the SBI message
+ @param[in] Opcode Opcode
+ @param[in] Posted Posted message
+ @param[in] Fbe First byte enable
+ @param[in] Bar Bar
+ @param[in] Fid Function ID
+ @param[in, out] Data32 Read/Write data
+ @param[out] Response Response
+
+ @retval EFI_SUCCESS Successfully completed.
+ @retval EFI_DEVICE_ERROR Transaction fail
+ @retval EFI_INVALID_PARAMETER Invalid parameter
+ @retval EFI_TIMEOUT Timeout while waiting for response
+**/
+EFI_STATUS
+PchSbiExecutionEx (
+ IN PCH_SBI_PID Pid,
+ IN UINT64 Offset,
+ IN PCH_SBI_OPCODE Opcode,
+ IN BOOLEAN Posted,
+ IN UINT16 Fbe,
+ IN UINT16 Bar,
+ IN UINT16 Fid,
+ IN OUT UINT32 *Data32,
+ OUT UINT8 *Response
+ )
+{
+ return P2SbSbiExecutionEx (
+ P2sbPciCfgBase (),
+ Pid,
+ Offset,
+ Opcode,
+ Posted,
+ Fbe,
+ Bar,
+ Fid,
+ Data32,
+ Response
+ );
+}
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/LibraryPrivate/PeiDxeSmmPchSbiAccessLib/PeiDxeSmmPchSbiAccessLib.inf b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/LibraryPrivate/PeiDxeSmmPchSbiAccessLib/PeiDxeSmmPchSbiAccessLib.inf
new file mode 100644
index 0000000000..a28a90c74b
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/P2sb/LibraryPrivate/PeiD
+++ xeSmmPchSbiAccessLib/PeiDxeSmmPchSbiAccessLib.inf
@@ -0,0 +1,35 @@
+## @file
+# PCH SBI access library.
+#
+# All function in this library is available for PEI, DXE, and SMM, #
+But do not support UEFI RUNTIME environment call.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+
+[Defines]
+INF_VERSION = 0x00010017
+BASE_NAME = PeiDxeSmmPchSbiAccessLib
+FILE_GUID = 96ECB0FB-A975-4DC8-B88A-D90C3378CE87
+VERSION_STRING = 1.0
+MODULE_TYPE = BASE
+LIBRARY_CLASS = PchSbiAccessLib
+
+
+[LibraryClasses]
+BaseLib
+IoLib
+DebugLib
+PchPciBdfLib
+P2SbSidebandAccessLib
+
+
+[Packages]
+MdePkg/MdePkg.dec
+AlderlakeSiliconPkg/SiPkg.dec
+
+
+[Sources]
+PchSbiAccessLib.c
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PchDmi/IncludePrivate/Library/PchDmiLib.h b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PchDmi/IncludePrivate/Library/PchDmiLib.h
new file mode 100644
index 0000000000..efbb76f6be
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PchDmi/IncludePrivate/Li
+++ brary/PchDmiLib.h
@@ -0,0 +1,60 @@
+/** @file
+ Header file for PchDmiLib.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/ #ifndef
+_PCH_DMI_LIB_H_ #define _PCH_DMI_LIB_H_
+
+/**
+ This function checks if DMI Secured Register Lock (SRL) is set
+
+ @retval SRL state
+**/
+BOOLEAN
+IsPchDmiLocked (
+ VOID
+ );
+
+/**
+ Get PCH TCO base address.
+
+ @retval Address Address of TCO base address.
+**/
+UINT16
+PchDmiGetTcoBase (
+ VOID
+ );
+
+/**
+ Set PCH LPC/eSPI IO decode ranges in DMI
+ Please check EDS for detail of LPC/eSPI IO decode ranges bit definition.
+ Bit 12: FDD range
+ Bit 9:8: LPT range
+ Bit 6:4: ComB range
+ Bit 2:0: ComA range
+
+ @param[in] LpcIoDecodeRanges LPC/eSPI IO decode ranges bit settings.
+
+ @retval EFI_SUCCESS Successfully completed.
+ @retval EFI_UNSUPPORTED DMIC.SRL is set.
+**/
+EFI_STATUS
+PchDmiSetLpcIoDecodeRanges (
+ IN UINT16 LpcIoDecodeRanges
+ );
+
+/**
+ Set PCH LPC/eSPI IO enable decoding in DMI
+
+ @param[in] LpcIoEnableDecoding LPC/eSPI IO enable decoding bit settings.
+
+ @retval EFI_SUCCESS Successfully completed.
+ @retval EFI_UNSUPPORTED DMIC.SRL is set.
+**/
+EFI_STATUS
+PchDmiSetLpcIoEnable (
+ IN UINT16 LpcIoEnableDecoding
+ );
+#endif // _PCH_DMI_LIB_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivate/PeiDxeSmmPchDmiLib/PchDmi14.c b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivate/PeiDxeSmmPchDmiLib/PchDmi14.c
new file mode 100644
index 0000000000..9f49790372
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivate/Pe
+++ iDxeSmmPchDmiLib/PchDmi14.c
@@ -0,0 +1,34 @@
+/** @file
+ This file contains functions for PCH DMI SIP14
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/
+
+#include <Base.h>
+#include <Uefi/UefiBaseType.h>
+#include <Library/IoLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseLib.h>
+#include <Library/PchInfoLib.h>
+#include <Library/PchPcrLib.h>
+#include <Library/PchDmiLib.h>
+#include <Library/PchCycleDecodingLib.h> #include <Library/PchPcrLib.h>
+#include <Library/PchInfoLib.h> #include <Register/PchDmiRegs.h>
+#include <Register/PchDmi14Regs.h> #include <Register/PchPcrRegs.h>
+
+/**
+ This function checks if DMI SIP14 Secured Register Lock (SRL) is set
+
+ @retval SRL state
+**/
+BOOLEAN
+IsPchDmi14Locked (
+ VOID
+ )
+{
+ return ((PchPcrRead32 (PID_DMI, R_PCH_DMI14_PCR_DMIC) &
+B_PCH_DMI14_PCR_DMIC_SRL) != 0); }
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivate/PeiDxeSmmPchDmiLib/PchDmi14.h b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivate/PeiDxeSmmPchDmiLib/PchDmi14.h
new file mode 100644
index 0000000000..494caebb4a
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivate/Pe
+++ iDxeSmmPchDmiLib/PchDmi14.h
@@ -0,0 +1,22 @@
+/** @file
+ Internal header file for PCH DMI library for SIP14
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/ #ifndef
+__PCH_DMI_14_H__ #define __PCH_DMI_14_H__
+
+#include <Library/PchDmiLib.h>
+
+/**
+ This function checks if DMI SIP14 Secured Register Lock (SRL) is set
+
+ @retval SRL state
+**/
+BOOLEAN
+IsPchDmi14Locked (
+ VOID
+ );
+
+#endif
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivate/PeiDxeSmmPchDmiLib/PchDmiLib.c b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivate/PeiDxeSmmPchDmiLib/PchDmiLib.c
new file mode 100644
index 0000000000..3d5436f1a3
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivate/Pe
+++ iDxeSmmPchDmiLib/PchDmiLib.c
@@ -0,0 +1,110 @@
+/** @file
+ PCH DMI library.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/ #include <Base.h>
+#include <Uefi/UefiBaseType.h> #include <Library/IoLib.h> #include
+<Library/DebugLib.h> #include <Library/BaseLib.h> #include
+<Library/PchInfoLib.h> #include <Library/PchPcrLib.h> #include
+<Library/PchDmiLib.h> #include <Library/PchCycleDecodingLib.h> #include
+<Register/PchPcrRegs.h> #include <Register/PchDmiRegs.h> #include
+<Register/PchRegsLpc.h>
+
+#include "PchDmi14.h"
+
+/**
+ This function checks if DMI Secured Register Lock (SRL) is set
+
+ @retval SRL state
+**/
+BOOLEAN
+IsPchDmiLocked (
+ VOID
+ )
+{
+ return IsPchDmi14Locked ();
+}
+
+/**
+ Get PCH TCO base address.
+
+ @retval Address Address of TCO base address.
+**/
+UINT16
+PchDmiGetTcoBase (
+ VOID
+ )
+{
+ //
+ // Read "TCO Base Address" PCR[DMI] + 2778h[15:5]
+ //
+ return (PchPcrRead16 (PID_DMI, R_PCH_DMI_PCR_TCOBASE) &
+B_PCH_DMI_PCR_TCOBASE_TCOBA); }
+
+/**
+ Set PCH LPC/eSPI IO decode ranges in DMI
+ Please check EDS for detail of LPC/eSPI IO decode ranges bit definition.
+ Bit 12: FDD range
+ Bit 9:8: LPT range
+ Bit 6:4: ComB range
+ Bit 2:0: ComA range
+
+ @param[in] LpcIoDecodeRanges LPC/eSPI IO decode ranges bit settings.
+
+ @retval EFI_SUCCESS Successfully completed.
+ @retval EFI_UNSUPPORTED DMIC.SRL is set.
+**/
+EFI_STATUS
+PchDmiSetLpcIoDecodeRanges (
+ IN UINT16 LpcIoDecodeRanges
+ )
+{
+ //
+ // This cycle decoding is only allowed to set when DMI is not locked.
+ //
+ if (IsPchDmiLocked ()) {
+ ASSERT (FALSE);
+ return EFI_UNSUPPORTED;
+ }
+
+ //
+ // program LPC I/O Decode Ranges, PCR[DMI] + 2770h[15:0] to the same value programmed in LPC/eSPI PCI offset 80h.
+ //
+ PchPcrWrite16 (PID_DMI, R_PCH_DMI_PCR_LPCIOD, LpcIoDecodeRanges);
+ return EFI_SUCCESS;
+}
+
+/**
+ Set PCH LPC/eSPI IO enable decoding in DMI
+
+ @param[in] LpcIoEnableDecoding LPC/eSPI IO enable decoding bit settings.
+
+ @retval EFI_SUCCESS Successfully completed.
+ @retval EFI_UNSUPPORTED DMIC.SRL is set.
+**/
+EFI_STATUS
+PchDmiSetLpcIoEnable (
+ IN UINT16 LpcIoEnableDecoding
+ )
+{
+ //
+ // This cycle decoding is only allowed to set when DMI is not locked.
+ //
+ if (IsPchDmiLocked ()) {
+ ASSERT (FALSE);
+ return EFI_UNSUPPORTED;
+ }
+
+ //
+ // program LPC I/O Decode Ranges, PCR[DMI] + 2774h[15:0] to the same value programmed in LPC/eSPI PCI offset 82h.
+ //
+ PchPcrWrite16 (PID_DMI, R_PCH_DMI_PCR_LPCIOE, LpcIoEnableDecoding);
+ return EFI_SUCCESS;
+}
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivate/PeiDxeSmmPchDmiLib/PeiDxeSmmPchDmiLib.inf b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivate/PeiDxeSmmPchDmiLib/PeiDxeSmmPchDmiLib.inf
new file mode 100644
index 0000000000..4e92117be3
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/PchDmi/LibraryPrivate/Pe
+++ iDxeSmmPchDmiLib/PeiDxeSmmPchDmiLib.inf
@@ -0,0 +1,43 @@
+## @file
+# Component description file for the PeiDxeSmmPchDmiLib #
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+[Defines]
+INF_VERSION = 0x00010017
+BASE_NAME = PeiDxeSmmPchDmiLib
+FILE_GUID = 067DC1C4-2668-4F06-9921-307514B66B34
+VERSION_STRING = 1.0
+MODULE_TYPE = BASE
+LIBRARY_CLASS = PchDmiLib
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = IA32 X64
+#
+
+[LibraryClasses]
+ BaseLib
+ IoLib
+ DebugLib
+ PchInfoLib
+ PchPcrLib
+
+
+[Packages]
+ MdePkg/MdePkg.dec
+ AlderlakeSiliconPkg/SiPkg.dec
+
+
+[Sources]
+ PchDmiLib.c
+ PchDmi14.c
+ PchDmi14.h
+
+[Guids]
+ gPchDmiConfigGuid ## CONSUMES
+ gPchDmiPreMemConfigGuid ## CONSUMES
+
+[Pcd]
--
2.36.1.windows.1
-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#108739): https://edk2.groups.io/g/devel/message/108739
Mute This Topic: https://groups.io/mt/101373946/7686176
Group Owner: devel+owner@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [rebecca@openfw.io]
-=-=-=-=-=-=-=-=-=-=-=-
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [edk2-devel] [PATCH v2 04/10] AlderlakeSiliconPkg/IpBlock: Add Pmc, Spi components
2023-09-15 4:45 ` [edk2-devel] [PATCH v2 04/10] AlderlakeSiliconPkg/IpBlock: Add Pmc, Spi components Saloni Kasbekar
2023-09-15 5:42 ` Chaganty, Rangasai V
@ 2023-09-15 23:56 ` Nate DeSimone
1 sibling, 0 replies; 41+ messages in thread
From: Nate DeSimone @ 2023-09-15 23:56 UTC (permalink / raw)
To: Kasbekar, Saloni, devel@edk2.groups.io
Cc: Chaganty, Rangasai V, Chuang, Rosen
Acked-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
-----Original Message-----
From: Kasbekar, Saloni <saloni.kasbekar@intel.com>
Sent: Thursday, September 14, 2023 9:46 PM
To: devel@edk2.groups.io
Cc: Kasbekar, Saloni <saloni.kasbekar@intel.com>; Chaganty, Rangasai V <rangasai.v.chaganty@intel.com>; Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>; Chuang, Rosen <rosen.chuang@intel.com>
Subject: [PATCH v2 04/10] AlderlakeSiliconPkg/IpBlock: Add Pmc, Spi components
Adds the following modules:
- IpBlock/Pmc/IncludePrivate
- IpBlock/Pmc/Library
- IpBlock/Pmc/LibraryPrivate
- IpBlock/Spi/IncludePrivate
- IpBlock/Spi/Library
- IpBlock/Spi/LibraryPrivate
- IpBlock/Spi/Smm
Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Rosen Chuang <rosen.chuang@intel.com>
Signed-off-by: Saloni Kasbekar <saloni.kasbekar@intel.com>
---
.../IncludePrivate/Library/PmcPrivateLib.h | 47 +
.../IpBlock/Pmc/IncludePrivate/PmcSocConfig.h | 67 +
.../PeiDxeSmmPmcLib/PeiDxeSmmPmcLib.inf | 38 +
.../Pmc/Library/PeiDxeSmmPmcLib/PmcLib.c | 50 +
.../PeiDxeSmmPmcPrivateLib.inf | 43 +
.../PeiDxeSmmPmcPrivateLib/PmcPrivateLib.c | 86 ++
.../Spi/IncludePrivate/Library/SpiCommonLib.h | 376 ++++++
.../Spi/IncludePrivate/Register/SpiRegs.h | 116 ++
.../IpBlock/Spi/Library/PeiSpiLib/PchSpi.c | 209 +++
.../Spi/Library/PeiSpiLib/PeiSpiLib.inf | 41 +
.../BaseSpiCommonLib/BaseSpiCommonLib.inf | 29 +
.../BaseSpiCommonLib/SpiCommon.c | 1127 +++++++++++++++++
.../AlderlakeSiliconPkg/IpBlock/Spi/Smm/Spi.c | 387 ++++++
.../IpBlock/Spi/Smm/SpiSmm.inf | 46 +
14 files changed, 2662 insertions(+)
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Pmc/IncludePrivate/Library/PmcPrivateLib.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Pmc/IncludePrivate/PmcSocConfig.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Pmc/Library/PeiDxeSmmPmcLib/PeiDxeSmmPmcLib.inf
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Pmc/Library/PeiDxeSmmPmcLib/PmcLib.c
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Pmc/LibraryPrivate/PeiDxeSmmPmcPrivateLib/PeiDxeSmmPmcPrivateLib.inf
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Pmc/LibraryPrivate/PeiDxeSmmPmcPrivateLib/PmcPrivateLib.c
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/IncludePrivate/Library/SpiCommonLib.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/IncludePrivate/Register/SpiRegs.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/Library/PeiSpiLib/PchSpi.c
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/Library/PeiSpiLib/PeiSpiLib.inf
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/LibraryPrivate/BaseSpiCommonLib/BaseSpiCommonLib.inf
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/LibraryPrivate/BaseSpiCommonLib/SpiCommon.c
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/Smm/Spi.c
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/Smm/SpiSmm.inf
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Pmc/IncludePrivate/Library/PmcPrivateLib.h b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Pmc/IncludePrivate/Library/PmcPrivateLib.h
new file mode 100644
index 0000000000..6ec244b127
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Pmc/IncludePrivate/Library/PmcPrivateLib.h
@@ -0,0 +1,47 @@
+/** @file
+ Header file for private PmcLib.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _PMC_PRIVATE_LIB_H_
+#define _PMC_PRIVATE_LIB_H_
+
+#include <Library/PmcLib.h>
+#include "Register/PmcRegs.h"
+
+typedef enum {
+ PmcSwSmiRate1p5ms = 0,
+ PmcSwSmiRate16ms,
+ PmcSwSmiRate32ms,
+ PmcSwSmiRate64ms
+} PMC_SWSMI_RATE;
+
+/**
+ This function sets SW SMI Rate.
+
+ @param[in] SwSmiRate Refer to PMC_SWSMI_RATE for possible values
+**/
+VOID
+PmcSetSwSmiRate (
+ IN PMC_SWSMI_RATE SwSmiRate
+ );
+
+typedef enum {
+ PmcPeriodicSmiRate8s = 0,
+ PmcPeriodicSmiRate16s,
+ PmcPeriodicSmiRate32s,
+ PmcPeriodicSmiRate64s
+} PMC_PERIODIC_SMI_RATE;
+
+/**
+ This function sets Periodic SMI Rate.
+
+ @param[in] PeriodicSmiRate Refer to PMC_PERIODIC_SMI_RATE for possible values
+**/
+VOID
+PmcSetPeriodicSmiRate (
+ IN PMC_PERIODIC_SMI_RATE PeriodicSmiRate
+ );
+
+#endif // _PMC_PRIVATE_LIB_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Pmc/IncludePrivate/PmcSocConfig.h b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Pmc/IncludePrivate/PmcSocConfig.h
new file mode 100644
index 0000000000..523a84a180
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Pmc/IncludePrivate/PmcSocConfig.h
@@ -0,0 +1,67 @@
+/** @file
+ PMC SoC configuration
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PMC_SOC_CONFIGURATION_H_
+#define _PMC_SOC_CONFIGURATION_H_
+
+typedef enum {
+ AdrSinglePhase = 0,
+ AdrDualPhase
+} ADR_PHASE_TYPE;
+
+typedef enum {
+ AdrGpioB = 0,
+ AdrGpioC
+} ADR_GPIO;
+
+typedef enum {
+ AdrOverPmSync = 0,
+ AdrOverDmi
+} ADR_MSG_INTERFACE;
+
+typedef struct {
+ BOOLEAN Supported;
+ ADR_PHASE_TYPE AdrPhaseType;
+ ADR_GPIO AdrGpio;
+ ADR_MSG_INTERFACE AdrMsgInterface;
+ //
+ // On some designs ADR_GEN_CFG has been moved in the HW.
+ // Set this to if ADR_GEN_CFG is located at 0x1908
+ //
+ BOOLEAN AdrGenCfgMoved;
+} PMC_ADR_SOC_CONFIG;
+
+typedef struct {
+ BOOLEAN CppmCgInterfaceVersion;
+ BOOLEAN LpmSupported;
+ UINT8 LpmInterfaceVersion;
+ BOOLEAN OsIdleSupported;
+ BOOLEAN TimedGpioSupported;
+ UINT32 CpuIovrRampTime;
+ BOOLEAN PsOnSupported;
+ BOOLEAN ModPhySusPgSupported;
+ UINT8 SciIrq;
+ BOOLEAN FabricPowerGatingCppmQualificationEnable;
+ BOOLEAN EspiBoot;
+ BOOLEAN UsbDbcConnected;
+ UINT32 Usb3LanesConnectedBitmask;
+ BOOLEAN DisableIosfSbClockGating;
+ BOOLEAN SkipModPhyGatingPolicy;
+ PMC_ADR_SOC_CONFIG AdrSocConfig;
+ BOOLEAN AllSbrIdleQualifierEnable;
+ UINT32 LpmPriVal; ///< Low Power Mode Priority
+
+} PMC_SOC_CONFIG;
+
+typedef struct {
+ BOOLEAN OverrideFetRampTime;
+ UINT8 FetRampTime;
+ UINT8 IsFetRampTime;
+ UINT16 FuseDownloadDelayUs;
+} PMC_FIVR_SOC_CONFIG;
+
+#endif
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Pmc/Library/PeiDxeSmmPmcLib/PeiDxeSmmPmcLib.inf b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Pmc/Library/PeiDxeSmmPmcLib/PeiDxeSmmPmcLib.inf
new file mode 100644
index 0000000000..e9784ceb9c
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Pmc/Library/PeiDxeSmmPmcLib/PeiDxeSmmPmcLib.inf
@@ -0,0 +1,38 @@
+## @file
+# PEI/DXE/SMM PCH PMC Lib.
+#
+# All function in this library is available for PEI, DXE, and SMM,
+# But do not support UEFI RUNTIME environment call.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+[Defines]
+ INF_VERSION = 0x00010017
+ BASE_NAME = PeiDxeSmmPmcLib
+ FILE_GUID = 9D60C364-5086-41E3-BC9D-C62AB7233DBF
+ VERSION_STRING = 1.0
+ MODULE_TYPE = BASE
+ LIBRARY_CLASS = PmcLib
+
+[LibraryClasses]
+ BaseLib
+ IoLib
+ DebugLib
+ PciSegmentLib
+ PchCycleDecodingLib
+ PchPcrLib
+ PchInfoLib
+ PmcPrivateLib
+ BaseMemoryLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ AlderlakeSiliconPkg/SiPkg.dec
+
+[Pcd]
+ gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress
+
+[Sources]
+ PmcLib.c
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Pmc/Library/PeiDxeSmmPmcLib/PmcLib.c b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Pmc/Library/PeiDxeSmmPmcLib/PmcLib.c
new file mode 100644
index 0000000000..91e741a294
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Pmc/Library/PeiDxeSmmPmcLib/PmcLib.c
@@ -0,0 +1,50 @@
+/** @file
+ PCH PMC Library.
+ All function in this library is available for PEI, DXE, and SMM,
+ But do not support UEFI RUNTIME environment call.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <Base.h>
+#include <Uefi/UefiBaseType.h>
+#include <Library/IoLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/PciSegmentLib.h>
+#include <Library/PchCycleDecodingLib.h>
+#include <Library/PmcLib.h>
+#include <Library/PchPcrLib.h>
+#include <Library/PchInfoLib.h>
+#include <Library/PmcPrivateLib.h>
+#include <PchReservedResources.h>
+#include <Register/PmcRegs.h>
+#include <Register/PchRegs.h>
+
+/**
+ Get PCH ACPI base address.
+
+ @retval Address Address of PWRM base address.
+**/
+UINT16
+PmcGetAcpiBase (
+ VOID
+ )
+{
+ return PcdGet16 (PcdAcpiBaseAddress);
+}
+
+/**
+ Get PCH PWRM base address.
+
+ @retval Address Address of PWRM base address.
+**/
+UINT32
+PmcGetPwrmBase (
+ VOID
+ )
+{
+ return PCH_PWRM_BASE_ADDRESS;
+}
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Pmc/LibraryPrivate/PeiDxeSmmPmcPrivateLib/PeiDxeSmmPmcPrivateLib.inf b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Pmc/LibraryPrivate/PeiDxeSmmPmcPrivateLib/PeiDxeSmmPmcPrivateLib.inf
new file mode 100644
index 0000000000..e6693f767d
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Pmc/LibraryPrivate/PeiDxeSmmPmcPrivateLib/PeiDxeSmmPmcPrivateLib.inf
@@ -0,0 +1,43 @@
+## @file
+# PEI/DXE/SMM PCH PMC Private Lib.
+#
+# All function in this library is available for PEI, DXE, and SMM,
+# But do not support UEFI RUNTIME environment call.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+
+[Defines]
+INF_VERSION = 0x00010017
+BASE_NAME = PeiDxeSmmPmcPrivateLib
+FILE_GUID = EB69B12B-6D4C-4B12-BB31-66CBCC4C1DC7
+VERSION_STRING = 1.0
+MODULE_TYPE = BASE
+LIBRARY_CLASS = PmcPrivateLib
+
+
+[LibraryClasses]
+BaseLib
+IoLib
+DebugLib
+TimerLib
+PciSegmentLib
+PmcLib
+BaseMemoryLib
+PchPciBdfLib
+
+[Packages]
+MdePkg/MdePkg.dec
+AlderlakeSiliconPkg/SiPkg.dec
+
+
+[Pcd]
+gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress
+
+[FixedPcd]
+
+[Sources]
+PmcPrivateLib.c
+
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Pmc/LibraryPrivate/PeiDxeSmmPmcPrivateLib/PmcPrivateLib.c b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Pmc/LibraryPrivate/PeiDxeSmmPmcPrivateLib/PmcPrivateLib.c
new file mode 100644
index 0000000000..b720305d15
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Pmc/LibraryPrivate/PeiDxeSmmPmcPrivateLib/PmcPrivateLib.c
@@ -0,0 +1,86 @@
+/** @file
+ PCH private PMC Library for all PCH generations.
+ All function in this library is available for PEI, DXE, and SMM,
+ But do not support UEFI RUNTIME environment call.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <Base.h>
+#include <Uefi/UefiBaseType.h>
+#include <Library/IoLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/PmcLib.h>
+#include <Library/PciSegmentLib.h>
+#include <Library/TimerLib.h>
+#include <Library/PmcPrivateLib.h>
+#include <PchReservedResources.h>
+#include <Register/PchRegs.h>
+#include <Register/PmcRegs.h>
+#include <IndustryStandard/Pci30.h>
+#include <Library/PchPciBdfLib.h>
+
+
+/**
+ This function sets SW SMI Rate.
+
+ @param[in] SwSmiRate Refer to PMC_SWSMI_RATE for possible values
+**/
+VOID
+PmcSetSwSmiRate (
+ IN PMC_SWSMI_RATE SwSmiRate
+ )
+{
+ UINT32 PchPwrmBase;
+ STATIC UINT8 SwSmiRateRegVal[4] = {
+ V_PMC_PWRM_GEN_PMCON_A_SWSMI_RTSL_1_5MS,
+ V_PMC_PWRM_GEN_PMCON_A_SWSMI_RTSL_16MS,
+ V_PMC_PWRM_GEN_PMCON_A_SWSMI_RTSL_32MS,
+ V_PMC_PWRM_GEN_PMCON_A_SWSMI_RTSL_64MS
+ };
+
+ ASSERT (SwSmiRate <= PmcSwSmiRate64ms);
+
+ PchPwrmBase = PmcGetPwrmBase ();
+
+ //
+ // SWSMI_RATE_SEL BIT (PWRMBASE offset 1020h[7:6]) bits are in RTC well
+ //
+ MmioAndThenOr8 (
+ PchPwrmBase + R_PMC_PWRM_GEN_PMCON_A,
+ (UINT8)~B_PMC_PWRM_GEN_PMCON_A_SWSMI_RTSL,
+ SwSmiRateRegVal[SwSmiRate]
+ );
+}
+
+/**
+ This function sets Periodic SMI Rate.
+
+ @param[in] PeriodicSmiRate Refer to PMC_PERIODIC_SMI_RATE for possible values
+**/
+VOID
+PmcSetPeriodicSmiRate (
+ IN PMC_PERIODIC_SMI_RATE PeriodicSmiRate
+ )
+{
+ UINT32 PchPwrmBase;
+ STATIC UINT8 PeriodicSmiRateRegVal[4] = {
+ V_PMC_PWRM_GEN_PMCON_A_PER_SMI_8S,
+ V_PMC_PWRM_GEN_PMCON_A_PER_SMI_16S,
+ V_PMC_PWRM_GEN_PMCON_A_PER_SMI_32S,
+ V_PMC_PWRM_GEN_PMCON_A_PER_SMI_64S
+ };
+
+ ASSERT (PeriodicSmiRate <= PmcPeriodicSmiRate64s);
+
+ PchPwrmBase = PmcGetPwrmBase ();
+
+ MmioAndThenOr8 (
+ PchPwrmBase + R_PMC_PWRM_GEN_PMCON_A,
+ (UINT8)~B_PMC_PWRM_GEN_PMCON_A_PER_SMI_SEL,
+ PeriodicSmiRateRegVal[PeriodicSmiRate]
+ );
+}
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/IncludePrivate/Library/SpiCommonLib.h b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/IncludePrivate/Library/SpiCommonLib.h
new file mode 100644
index 0000000000..e13718c9e9
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/IncludePrivate/Library/SpiCommonLib.h
@@ -0,0 +1,376 @@
+/** @file
+ Header file for the PCH SPI Common Driver.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _SPI_COMMON_LIB_H_
+#define _SPI_COMMON_LIB_H_
+
+#include <Protocol/Spi.h>
+
+//
+// Maximum time allowed while waiting the SPI cycle to complete
+// Wait Time = 6 seconds = 6000000 microseconds
+// Wait Period = 10 microseconds
+//
+#define SPI_WAIT_TIME 6000000 ///< Wait Time = 6 seconds = 6000000 microseconds
+
+#define SPI_WAIT_PERIOD 10 ///< Wait Period = 10 microseconds
+
+///
+/// Flash cycle Type
+///
+typedef enum {
+ FlashCycleRead,
+ FlashCycleWrite,
+ FlashCycleErase,
+ FlashCycleReadSfdp,
+ FlashCycleReadJedecId,
+ FlashCycleWriteStatus,
+ FlashCycleReadStatus,
+ FlashCycleMax
+} FLASH_CYCLE_TYPE;
+
+///
+/// Flash Component Number
+///
+typedef enum {
+ FlashComponent0,
+ FlashComponent1,
+ FlashComponentMax
+} FLASH_COMPONENT_NUM;
+
+///
+/// Private data structure definitions for the driver
+///
+#define PCH_SPI_PRIVATE_DATA_SIGNATURE SIGNATURE_32 ('P', 'S', 'P', 'I')
+
+typedef struct {
+ UINT32 Signature;
+ EFI_HANDLE Handle;
+ PCH_SPI_PROTOCOL SpiProtocol;
+ UINT16 PchAcpiBase;
+ UINT64 PchSpiBase;
+ UINT8 ReadPermission;
+ UINT8 WritePermission;
+ UINT32 SfdpVscc0Value;
+ UINT32 SfdpVscc1Value;
+ UINT16 PchStrapBaseAddr;
+ UINT16 PchStrapSize;
+ UINT16 CpuStrapBaseAddr;
+ UINT16 CpuStrapSize;
+ UINT8 NumberOfComponents;
+ UINT32 Component1StartAddr;
+ UINT32 TotalFlashSize;
+} SPI_INSTANCE;
+
+#define SPI_INSTANCE_FROM_SPIPROTOCOL(a) CR (a, SPI_INSTANCE, SpiProtocol, PCH_SPI_PRIVATE_DATA_SIGNATURE)
+
+//
+// Function prototypes used by the SPI protocol.
+//
+
+/**
+ Initialize an SPI protocol instance.
+
+ @param[in] SpiInstance Pointer to SpiInstance to initialize
+
+ @retval EFI_SUCCESS The protocol instance was properly initialized
+ @exception EFI_UNSUPPORTED The PCH is not supported by this module
+**/
+EFI_STATUS
+SpiProtocolConstructor (
+ IN SPI_INSTANCE *SpiInstance
+ );
+
+/**
+ This function is a hook for Spi to disable BIOS Write Protect
+
+ @retval EFI_SUCCESS The protocol instance was properly initialized
+ @retval EFI_ACCESS_DENIED The BIOS Region can only be updated in SMM phase
+
+**/
+EFI_STATUS
+EFIAPI
+DisableBiosWriteProtect (
+ VOID
+ );
+
+/**
+ This function is a hook for Spi to enable BIOS Write Protect
+
+
+**/
+VOID
+EFIAPI
+EnableBiosWriteProtect (
+ VOID
+ );
+
+/**
+ Acquire pch spi mmio address.
+
+ @param[in] SpiInstance Pointer to SpiInstance to initialize
+
+ @retval PchSpiBar0 return SPI MMIO address
+**/
+UINTN
+AcquireSpiBar0 (
+ IN SPI_INSTANCE *SpiInstance
+ );
+
+/**
+ Release pch spi mmio address.
+
+ @param[in] SpiInstance Pointer to SpiInstance to initialize
+
+ @retval None
+**/
+VOID
+ReleaseSpiBar0 (
+ IN SPI_INSTANCE *SpiInstance
+ );
+
+/**
+ Check if it's granted to do flash write.
+
+ @retval TRUE It's secure to do flash write.
+ @retval FALSE It's not secure to do flash write.
+**/
+BOOLEAN
+IsSpiFlashWriteGranted (
+ VOID
+ );
+
+/**
+ Check if a save and restore of the SPI controller state is necessary
+
+ @retval TRUE It's necessary to save and restore SPI controller state
+ @retval FALSE It's not necessary to save and restore SPI controller state
+**/
+BOOLEAN
+IsSpiControllerSaveRestoreEnabled (
+ VOID
+ );
+
+/**
+ Read data from the flash part.
+
+ @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
+ @param[in] FlashRegionType The Flash Region type for flash cycle which is listed in the Descriptor.
+ @param[in] Address The Flash Linear Address must fall within a region for which BIOS has access permissions.
+ @param[in] ByteCount Number of bytes in the data portion of the SPI cycle.
+ @param[out] Buffer The Pointer to caller-allocated buffer containing the dada received.
+ It is the caller's responsibility to make sure Buffer is large enough for the total number of bytes read.
+
+ @retval EFI_SUCCESS Command succeed.
+ @retval EFI_INVALID_PARAMETER The parameters specified are not valid.
+ @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
+**/
+EFI_STATUS
+EFIAPI
+SpiProtocolFlashRead (
+ IN PCH_SPI_PROTOCOL *This,
+ IN FLASH_REGION_TYPE FlashRegionType,
+ IN UINT32 Address,
+ IN UINT32 ByteCount,
+ OUT UINT8 *Buffer
+ );
+
+/**
+ Write data to the flash part.
+
+ @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
+ @param[in] FlashRegionType The Flash Region type for flash cycle which is listed in the Descriptor.
+ @param[in] Address The Flash Linear Address must fall within a region for which BIOS has access permissions.
+ @param[in] ByteCount Number of bytes in the data portion of the SPI cycle.
+ @param[in] Buffer Pointer to caller-allocated buffer containing the data sent during the SPI cycle.
+
+ @retval EFI_SUCCESS Command succeed.
+ @retval EFI_INVALID_PARAMETER The parameters specified are not valid.
+ @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
+**/
+EFI_STATUS
+EFIAPI
+SpiProtocolFlashWrite (
+ IN PCH_SPI_PROTOCOL *This,
+ IN FLASH_REGION_TYPE FlashRegionType,
+ IN UINT32 Address,
+ IN UINT32 ByteCount,
+ IN UINT8 *Buffer
+ );
+
+/**
+ Erase some area on the flash part.
+
+ @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
+ @param[in] FlashRegionType The Flash Region type for flash cycle which is listed in the Descriptor.
+ @param[in] Address The Flash Linear Address must fall within a region for which BIOS has access permissions.
+ @param[in] ByteCount Number of bytes in the data portion of the SPI cycle.
+
+ @retval EFI_SUCCESS Command succeed.
+ @retval EFI_INVALID_PARAMETER The parameters specified are not valid.
+ @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
+**/
+EFI_STATUS
+EFIAPI
+SpiProtocolFlashErase (
+ IN PCH_SPI_PROTOCOL *This,
+ IN FLASH_REGION_TYPE FlashRegionType,
+ IN UINT32 Address,
+ IN UINT32 ByteCount
+ );
+
+/**
+ Read SFDP data from the flash part.
+
+ @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
+ @param[in] ComponentNumber The Componen Number for chip select
+ @param[in] Address The starting byte address for SFDP data read.
+ @param[in] ByteCount Number of bytes in SFDP data portion of the SPI cycle
+ @param[out] SfdpData The Pointer to caller-allocated buffer containing the SFDP data received
+ It is the caller's responsibility to make sure Buffer is large enough for the total number of bytes read
+
+ @retval EFI_SUCCESS Command succeed.
+ @retval EFI_INVALID_PARAMETER The parameters specified are not valid.
+ @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
+**/
+EFI_STATUS
+EFIAPI
+SpiProtocolFlashReadSfdp (
+ IN PCH_SPI_PROTOCOL *This,
+ IN UINT8 ComponentNumber,
+ IN UINT32 Address,
+ IN UINT32 ByteCount,
+ OUT UINT8 *SfdpData
+ );
+
+/**
+ Read Jedec Id from the flash part.
+
+ @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
+ @param[in] ComponentNumber The Componen Number for chip select
+ @param[in] ByteCount Number of bytes in JedecId data portion of the SPI cycle, the data size is 3 typically
+ @param[out] JedecId The Pointer to caller-allocated buffer containing JEDEC ID received
+ It is the caller's responsibility to make sure Buffer is large enough for the total number of bytes read.
+
+ @retval EFI_SUCCESS Command succeed.
+ @retval EFI_INVALID_PARAMETER The parameters specified are not valid.
+ @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
+**/
+EFI_STATUS
+EFIAPI
+SpiProtocolFlashReadJedecId (
+ IN PCH_SPI_PROTOCOL *This,
+ IN UINT8 ComponentNumber,
+ IN UINT32 ByteCount,
+ OUT UINT8 *JedecId
+ );
+
+/**
+ Write the status register in the flash part.
+
+ @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
+ @param[in] ByteCount Number of bytes in Status data portion of the SPI cycle, the data size is 1 typically
+ @param[in] StatusValue The Pointer to caller-allocated buffer containing the value of Status register writing
+
+ @retval EFI_SUCCESS Command succeed.
+ @retval EFI_INVALID_PARAMETER The parameters specified are not valid.
+ @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
+**/
+EFI_STATUS
+EFIAPI
+SpiProtocolFlashWriteStatus (
+ IN PCH_SPI_PROTOCOL *This,
+ IN UINT32 ByteCount,
+ IN UINT8 *StatusValue
+ );
+
+/**
+ Read status register in the flash part.
+
+ @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
+ @param[in] ByteCount Number of bytes in Status data portion of the SPI cycle, the data size is 1 typically
+ @param[out] StatusValue The Pointer to caller-allocated buffer containing the value of Status register received.
+
+ @retval EFI_SUCCESS Command succeed.
+ @retval EFI_INVALID_PARAMETER The parameters specified are not valid.
+ @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
+**/
+EFI_STATUS
+EFIAPI
+SpiProtocolFlashReadStatus (
+ IN PCH_SPI_PROTOCOL *This,
+ IN UINT32 ByteCount,
+ OUT UINT8 *StatusValue
+ );
+
+/**
+ Get the SPI region base and size, based on the enum type
+
+ @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
+ @param[in] FlashRegionType The Flash Region type for for the base address which is listed in the Descriptor.
+ @param[out] BaseAddress The Flash Linear Address for the Region 'n' Base
+ @param[out] RegionSize The size for the Region 'n'
+
+ @retval EFI_SUCCESS Read success
+ @retval EFI_INVALID_PARAMETER Invalid region type given
+ @retval EFI_DEVICE_ERROR The region is not used
+**/
+EFI_STATUS
+EFIAPI
+SpiProtocolGetRegionAddress (
+ IN PCH_SPI_PROTOCOL *This,
+ IN FLASH_REGION_TYPE FlashRegionType,
+ OUT UINT32 *BaseAddress,
+ OUT UINT32 *RegionSize
+ );
+
+/**
+ Read PCH Soft Strap Values
+
+ @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
+ @param[in] SoftStrapAddr PCH Soft Strap address offset from FPSBA.
+ @param[in] ByteCount Number of bytes in SoftStrap data portion of the SPI cycle
+ @param[out] SoftStrapValue The Pointer to caller-allocated buffer containing PCH Soft Strap Value.
+ If the value of ByteCount is 0, the data type of SoftStrapValue should be UINT16 and SoftStrapValue will be PCH Soft Strap Length
+ It is the caller's responsibility to make sure Buffer is large enough for the total number of bytes read.
+
+ @retval EFI_SUCCESS Command succeed.
+ @retval EFI_INVALID_PARAMETER The parameters specified are not valid.
+ @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
+**/
+EFI_STATUS
+EFIAPI
+SpiProtocolReadPchSoftStrap (
+ IN PCH_SPI_PROTOCOL *This,
+ IN UINT32 SoftStrapAddr,
+ IN UINT32 ByteCount,
+ OUT VOID *SoftStrapValue
+ );
+
+/**
+ Read CPU Soft Strap Values
+
+ @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
+ @param[in] SoftStrapAddr CPU Soft Strap address offset from FCPUSBA.
+ @param[in] ByteCount Number of bytes in SoftStrap data portion of the SPI cycle.
+ @param[out] SoftStrapValue The Pointer to caller-allocated buffer containing CPU Soft Strap Value.
+ If the value of ByteCount is 0, the data type of SoftStrapValue should be UINT16 and SoftStrapValue will be PCH Soft Strap Length
+ It is the caller's responsibility to make sure Buffer is large enough for the total number of bytes read.
+
+ @retval EFI_SUCCESS Command succeed.
+ @retval EFI_INVALID_PARAMETER The parameters specified are not valid.
+ @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
+**/
+EFI_STATUS
+EFIAPI
+SpiProtocolReadCpuSoftStrap (
+ IN PCH_SPI_PROTOCOL *This,
+ IN UINT32 SoftStrapAddr,
+ IN UINT32 ByteCount,
+ OUT VOID *SoftStrapValue
+ );
+
+#endif
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/IncludePrivate/Register/SpiRegs.h b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/IncludePrivate/Register/SpiRegs.h
new file mode 100644
index 0000000000..5cb4791142
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/IncludePrivate/Register/SpiRegs.h
@@ -0,0 +1,116 @@
+/** @file
+ Register names for PCH SPI device.
+
+ Conventions:
+
+ - Register definition format:
+ Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_RegisterName
+ - Prefix:
+ Definitions beginning with "R_" are registers
+ Definitions beginning with "B_" are bits within registers
+ Definitions beginning with "V_" are meaningful values within the bits
+ Definitions beginning with "S_" are register size
+ Definitions beginning with "N_" are the bit position
+ - [GenerationName]:
+ Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc.).
+ Register name without GenerationName applies to all generations.
+ - [ComponentName]:
+ This field indicates the component name that the register belongs to (e.g. PCH, SA etc.)
+ Register name without ComponentName applies to all components.
+ Register that is specific to -H denoted by "_PCH_H_" in component name.
+ Register that is specific to -LP denoted by "_PCH_LP_" in component name.
+ - SubsystemName:
+ This field indicates the subsystem name of the component that the register belongs to
+ (e.g. PCIE, USB, SATA, GPIO, PMC etc.).
+ - RegisterSpace:
+ MEM - MMIO space register of subsystem.
+ IO - IO space register of subsystem.
+ PCR - Private configuration register of subsystem.
+ CFG - PCI configuration space register of subsystem.
+ - RegisterName:
+ Full register name.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _SPI_REGS_H_
+#define _SPI_REGS_H_
+
+//
+// SPI Registers
+//
+#define R_SPI_CFG_BAR0 0x10
+#define B_SPI_CFG_BAR0_MASK 0x0FFF
+
+
+#define R_SPI_CFG_BC 0xDC
+#define S_SPI_CFG_BC 4
+#define N_SPI_CFG_BC_ASE_BWP 11
+#define B_SPI_CFG_BC_ASE_BWP BIT11
+#define N_SPI_CFG_BC_ASYNC_SS 10
+#define B_SPI_CFG_BC_ASYNC_SS BIT10
+#define N_SPI_CFG_BC_SYNC_SS 8
+#define B_SPI_CFG_BC_SYNC_SS BIT8
+#define B_SPI_CFG_BC_BILD BIT7
+#define B_SPI_CFG_BC_EISS BIT5 ///< Enable InSMM.STS
+#define B_SPI_CFG_BC_SRC (BIT3 | BIT2)
+#define N_SPI_CFG_BC_SRC 2
+#define V_SPI_CFG_BC_SRC_PREF_DIS_CACHE_DIS 0x01 ///< No prefetching and no caching
+#define N_SPI_CFG_BC_BLE 1
+#define B_SPI_CFG_BC_WPD BIT0 ///< Write Protect Disable
+
+//
+// BIOS Flash Program Registers (based on SPI_BAR0)
+//
+#define R_SPI_MEM_HSFSC 0x04 ///< Hardware Sequencing Flash Status and Control Register(32bits)
+#define B_SPI_MEM_HSFSC_FDBC_MASK 0x3F000000 ///< Flash Data Byte Count ( <= 64), Count = (Value in this field) + 1.
+#define N_SPI_MEM_HSFSC_FDBC 24
+#define B_SPI_MEM_HSFSC_CYCLE_MASK 0x001E0000 ///< Flash Cycle.
+#define N_SPI_MEM_HSFSC_CYCLE 17
+#define V_SPI_MEM_HSFSC_CYCLE_READ 0 ///< Flash Cycle Read
+#define V_SPI_MEM_HSFSC_CYCLE_WRITE 2 ///< Flash Cycle Write
+#define V_SPI_MEM_HSFSC_CYCLE_4K_ERASE 3 ///< Flash Cycle 4K Block Erase
+#define V_SPI_MEM_HSFSC_CYCLE_64K_ERASE 4 ///< Flash Cycle 64K Sector Erase
+#define V_SPI_MEM_HSFSC_CYCLE_READ_SFDP 5 ///< Flash Cycle Read SFDP
+#define V_SPI_MEM_HSFSC_CYCLE_READ_JEDEC_ID 6 ///< Flash Cycle Read JEDEC ID
+#define V_SPI_MEM_HSFSC_CYCLE_WRITE_STATUS 7 ///< Flash Cycle Write Status
+#define V_SPI_MEM_HSFSC_CYCLE_READ_STATUS 8 ///< Flash Cycle Read Status
+#define B_SPI_MEM_HSFSC_CYCLE_FGO BIT16 ///< Flash Cycle Go.
+#define B_SPI_MEM_HSFSC_FDV BIT14 ///< Flash Descriptor Valid, once valid software can use hareware sequencing regs
+#define B_SPI_MEM_HSFSC_WRSDIS BIT11 ///< Write Status Disable
+#define B_SPI_MEM_HSFSC_SAF_CE BIT8 ///< SAF ctype error
+#define B_SPI_MEM_HSFSC_SAF_LE BIT6 ///< SAF link error
+#define B_SPI_MEM_HSFSC_SCIP BIT5 ///< SPI cycle in progress
+#define B_SPI_MEM_HSFSC_SAF_DLE BIT4 ///< SAF Data length error
+#define B_SPI_MEM_HSFSC_SAF_ERROR BIT3 ///< SAF Error
+#define B_SPI_MEM_HSFSC_AEL BIT2 ///< Access Error Log
+#define B_SPI_MEM_HSFSC_FCERR BIT1 ///< Flash Cycle Error
+#define B_SPI_MEM_HSFSC_FDONE BIT0 ///< Flash Cycle Done
+#define R_SPI_MEM_FADDR 0x08 ///< SPI Flash Address
+#define B_SPI_MEM_FADDR_MASK 0x07FFFFFF ///< SPI Flash Address Mask (0~26bit)
+#define R_SPI_MEM_FDATA00 0x10 ///< SPI Data 00 (32 bits)
+#define R_SPI_MEM_FRAP 0x50 ///< Flash Region Access Permissions Register
+#define B_SPI_MEM_FRAP_BRWA_MASK 0x0000FF00 ///< BIOS Region Write Access MASK, Region0~7 - 0: Flash Descriptor; 1: BIOS; 2: ME; 3: GbE; 4: PlatformData
+#define N_SPI_MEM_FRAP_BRWA 8 ///< BIOS Region Write Access bit position
+#define B_SPI_MEM_FRAP_BRRA_MASK 0x000000FF ///< BIOS Region Read Access MASK, Region0~7 - 0: Flash Descriptor; 1: BIOS; 2: ME; 3: GbE; 4: PlatformData
+#define R_SPI_MEM_FREG0_FLASHD 0x54 ///< Flash Region 0(Flash Descriptor)(32bits)
+#define S_SPI_MEM_FREGX 4 ///< Size of Flash Region register
+#define B_SPI_MEM_FREGX_LIMIT_MASK 0x7FFF0000 ///< Flash Region Limit [30:16] represents [26:12], [11:0] are assumed to be FFFh
+#define N_SPI_MEM_FREGX_LIMIT 16 ///< Region limit bit position
+#define N_SPI_MEM_FREGX_LIMIT_REPR 12 ///< Region limit bit represents position
+#define B_SPI_MEM_FREGX_BASE_MASK 0x00007FFF ///< Flash Region Base, [14:0] represents [26:12]
+#define N_SPI_MEM_FREGX_BASE 0 ///< Region base bit position
+#define N_SPI_MEM_FREGX_BASE_REPR 12 ///< Region base bit represents position
+#define R_SPI_MEM_FDOC 0xB4 ///< Flash Descriptor Observability Control Register(32 bits)
+#define B_SPI_MEM_FDOC_FDSS_MASK (BIT14 | BIT13 | BIT12) ///< Flash Descritor Section Select
+#define V_SPI_MEM_FDOC_FDSS_FSDM 0x0000 ///< Flash Signature and Descriptor Map
+#define V_SPI_MEM_FDOC_FDSS_COMP 0x1000 ///< Component
+
+#define B_SPI_MEM_FDOC_FDSI_MASK 0x0FFC ///< Flash Descriptor Section Index
+#define R_SPI_MEM_FDOD 0xB8 ///< Flash Descriptor Observability Data Register(32 bits)
+#define R_SPI_MEM_SFDP0_VSCC0 0xC4 ///< Vendor Specific Component Capabilities Register(32 bits)
+
+#define B_SPI_MEM_SFDPX_VSCCX_EO_64K BIT29 ///< 64k Erase valid (EO_64k_valid)
+#define R_SPI_MEM_SFDP1_VSCC1 0xC8 ///< Vendor Specific Component Capabilities Register(32 bits)
+
+#endif
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/Library/PeiSpiLib/PchSpi.c b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/Library/PeiSpiLib/PchSpi.c
new file mode 100644
index 0000000000..aaf4e1790f
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/Library/PeiSpiLib/PchSpi.c
@@ -0,0 +1,209 @@
+/** @file
+ PCH SPI PEI Library implements the SPI Host Controller Compatibility Interface.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#include <Library/IoLib.h>
+#include <Library/DebugLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/PeiServicesLib.h>
+#include <Library/PciSegmentLib.h>
+#include <Ppi/Spi.h>
+#include <Library/SpiCommonLib.h>
+#include <PchReservedResources.h>
+#include <IndustryStandard/Pci30.h>
+#include <Register/PchRegs.h>
+#include <Register/PchRegsLpc.h>
+#include <Register/SpiRegs.h>
+#include <Library/PchPciBdfLib.h>
+
+typedef struct {
+ EFI_PEI_PPI_DESCRIPTOR PpiDescriptor;
+ SPI_INSTANCE SpiInstance;
+} PEI_SPI_INSTANCE;
+
+/**
+ PCI Enumeratuion is not done till later in DXE
+ Initlialize SPI BAR0 to a default value till enumeration is done
+ also enable memory space decoding for SPI
+
+**/
+VOID
+InitSpiBar0 (
+ VOID
+ )
+{
+ UINT64 PchSpiBase;
+ PchSpiBase = SpiPciCfgBase ();
+ PciSegmentWrite32 (PchSpiBase + R_SPI_CFG_BAR0, PCH_SPI_BASE_ADDRESS);
+ PciSegmentOr32 (PchSpiBase + PCI_COMMAND_OFFSET, EFI_PCI_COMMAND_MEMORY_SPACE);
+}
+
+/**
+ This function Initial SPI services
+
+ @retval EFI_STATUS Results of the installation of the SPI services
+**/
+EFI_STATUS
+EFIAPI
+SpiServiceInit (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+ PEI_SPI_INSTANCE *PeiSpiInstance;
+ SPI_INSTANCE *SpiInstance;
+ PCH_SPI_PPI *SpiPpi;
+
+ Status = PeiServicesLocatePpi (
+ &gPchSpiPpiGuid,
+ 0,
+ NULL,
+ (VOID **)&SpiPpi
+ );
+
+ if (Status != EFI_SUCCESS) {
+ DEBUG ((DEBUG_INFO, "SpiServiceInit() Start\n"));
+
+ //
+ // PCI Enumeratuion is not done till later in DXE
+ // Initlialize SPI BAR0 to a default value till enumeration is done
+ // also enable memory space decoding for SPI
+ //
+ InitSpiBar0 ();
+
+ PeiSpiInstance = (PEI_SPI_INSTANCE *) AllocateZeroPool (sizeof (PEI_SPI_INSTANCE));
+ if (NULL == PeiSpiInstance) {
+ return EFI_OUT_OF_RESOURCES;
+ }
+
+ SpiInstance = &(PeiSpiInstance->SpiInstance);
+ SpiProtocolConstructor (SpiInstance);
+
+ PeiSpiInstance->PpiDescriptor.Flags = EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST;
+ PeiSpiInstance->PpiDescriptor.Guid = &gPchSpiPpiGuid;
+ PeiSpiInstance->PpiDescriptor.Ppi = &(SpiInstance->SpiProtocol);
+
+ ///
+ /// Install the SPI PPI
+ ///
+ DEBUG ((DEBUG_INFO, "SPI PPI Installed\n"));
+ Status = PeiServicesInstallPpi (&PeiSpiInstance->PpiDescriptor);
+ ASSERT_EFI_ERROR (Status);
+
+ DEBUG ((DEBUG_INFO, "SpiServiceInit() End\n"));
+ }
+ else {
+ DEBUG ((DEBUG_INFO, "SPI PPI already installed\n"));
+ }
+ return Status;
+}
+
+/**
+ Acquire pch spi mmio address.
+
+ @param[in] SpiInstance Pointer to SpiInstance to initialize
+
+ @retval PchSpiBar0 return SPI MMIO address
+**/
+UINTN
+AcquireSpiBar0 (
+ IN SPI_INSTANCE *SpiInstance
+ )
+{
+ return PciSegmentRead32 (SpiInstance->PchSpiBase + R_SPI_CFG_BAR0) & ~(B_SPI_CFG_BAR0_MASK);
+}
+
+/**
+ Release pch spi mmio address. Do nothing.
+
+ @param[in] SpiInstance Pointer to SpiInstance to initialize
+
+ @retval None
+**/
+VOID
+ReleaseSpiBar0 (
+ IN SPI_INSTANCE *SpiInstance
+ )
+{
+}
+
+/**
+ This function is a hook for Spi to disable BIOS Write Protect
+
+ @retval EFI_SUCCESS The protocol instance was properly initialized
+ @retval EFI_ACCESS_DENIED The BIOS Region can only be updated in SMM phase
+
+**/
+EFI_STATUS
+EFIAPI
+DisableBiosWriteProtect (
+ VOID
+ )
+{
+ UINT64 SpiBaseAddress;
+
+ SpiBaseAddress = SpiPciCfgBase ();
+ if ((PciSegmentRead8 (SpiBaseAddress + R_SPI_CFG_BC) & B_SPI_CFG_BC_EISS) != 0) {
+ return EFI_ACCESS_DENIED;
+ }
+ ///
+ /// Enable the access to the BIOS space for both read and write cycles
+ ///
+ PciSegmentOr8 (
+ SpiBaseAddress + R_SPI_CFG_BC,
+ B_SPI_CFG_BC_WPD
+ );
+
+ return EFI_SUCCESS;
+}
+
+/**
+ This function is a hook for Spi to enable BIOS Write Protect
+**/
+VOID
+EFIAPI
+EnableBiosWriteProtect (
+ VOID
+ )
+{
+ UINT64 SpiBaseAddress;
+
+ SpiBaseAddress = SpiPciCfgBase ();
+ ///
+ /// Disable the access to the BIOS space for write cycles
+ ///
+ PciSegmentAnd8 (
+ SpiBaseAddress + R_SPI_CFG_BC,
+ (UINT8) (~B_SPI_CFG_BC_WPD)
+ );
+}
+
+/**
+ Check if it's granted to do flash write.
+
+ @retval TRUE It's secure to do flash write.
+ @retval FALSE It's not secure to do flash write.
+**/
+BOOLEAN
+IsSpiFlashWriteGranted (
+ VOID
+ )
+{
+ return TRUE;
+}
+
+/**
+ Check if a save and restore of the SPI controller state is necessary
+
+ @retval TRUE It's necessary to save and restore SPI controller state
+ @retval FALSE It's not necessary to save and restore SPI controller state
+**/
+BOOLEAN
+IsSpiControllerSaveRestoreEnabled (
+ VOID
+ )
+{
+ return FALSE;
+}
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/Library/PeiSpiLib/PeiSpiLib.inf b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/Library/PeiSpiLib/PeiSpiLib.inf
new file mode 100644
index 0000000000..c3bf6d02a1
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/Library/PeiSpiLib/PeiSpiLib.inf
@@ -0,0 +1,41 @@
+## @file
+# Component description file for PCH Reset Lib Pei Phase
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+[Defines]
+INF_VERSION = 0x00010017
+BASE_NAME = PeiSpiLib
+FILE_GUID = 4998447D-7948-448F-AB75-96E24E18FF23
+VERSION_STRING = 1.0
+MODULE_TYPE = PEIM
+LIBRARY_CLASS = SpiLib
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = IA32 X64 IPF
+#
+
+[LibraryClasses]
+DebugLib
+PeiServicesLib
+PeiServicesTablePointerLib
+MemoryAllocationLib
+PciSegmentLib
+SpiCommonLib
+PchPciBdfLib
+
+[Packages]
+MdePkg/MdePkg.dec
+AlderlakeSiliconPkg/SiPkg.dec
+
+
+[Sources]
+PchSpi.c
+
+
+[Ppis]
+gPchSpiPpiGuid ## PRODUCES
+
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/LibraryPrivate/BaseSpiCommonLib/BaseSpiCommonLib.inf b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/LibraryPrivate/BaseSpiCommonLib/BaseSpiCommonLib.inf
new file mode 100644
index 0000000000..25ab91940c
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/LibraryPrivate/BaseSpiCommonLib/BaseSpiCommonLib.inf
@@ -0,0 +1,29 @@
+## @file
+# Component description file for the PchSpiCommonLib
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = BaseSpiCommonLib
+ FILE_GUID = A37CB67E-7D85-45B3-B07E-BF65BDB603E8
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = SpiCommonLib
+
+[Sources]
+ SpiCommon.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ AlderlakeSiliconPkg/SiPkg.dec
+
+[LibraryClasses]
+ IoLib
+ DebugLib
+ PmcLib
+ PchPciBdfLib
+
+[Pcd]
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/LibraryPrivate/BaseSpiCommonLib/SpiCommon.c b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/LibraryPrivate/BaseSpiCommonLib/SpiCommon.c
new file mode 100644
index 0000000000..ab51521f14
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/LibraryPrivate/BaseSpiCommonLib/SpiCommon.c
@@ -0,0 +1,1127 @@
+/** @file
+ PCH SPI Common Driver implements the SPI Host Controller Compatibility Interface.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#include <Uefi/UefiBaseType.h>
+#include <Library/BaseLib.h>
+#include <Library/IoLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <IndustryStandard/Pci30.h>
+#include <Library/PmcLib.h>
+#include <Library/PciSegmentLib.h>
+#include <Protocol/Spi.h>
+#include <Library/SpiCommonLib.h>
+#include <Register/PchRegs.h>
+#include <Register/SpiRegs.h>
+#include <Register/FlashRegs.h>
+#include <Register/PmcRegs.h>
+#include <Library/PchPciBdfLib.h>
+
+#define DEFAULT_CPU_STRAP_BASE_OFFSET 0x300 // Default CPU Straps base offset
+#define B_SPI_MEM_HSFSC_SAVE_MASK (B_SPI_MEM_HSFSC_FDBC_MASK | B_SPI_MEM_HSFSC_CYCLE_MASK)
+
+/**
+ Initialize an SPI protocol instance.
+
+ @param[in] SpiInstance Pointer to SpiInstance to initialize
+
+ @retval EFI_SUCCESS The protocol instance was properly initialized
+ @exception EFI_UNSUPPORTED The PCH is not supported by this module
+**/
+EFI_STATUS
+SpiProtocolConstructor (
+ IN SPI_INSTANCE *SpiInstance
+ )
+{
+ UINTN PchSpiBar0;
+ UINT32 Data32;
+ UINT16 Mdtba;
+ EFI_STATUS Status;
+
+ //
+ // Initialize the SPI protocol instance
+ //
+ SpiInstance->Signature = PCH_SPI_PRIVATE_DATA_SIGNATURE;
+ SpiInstance->Handle = NULL;
+ SpiInstance->SpiProtocol.Revision = PCH_SPI_SERVICES_REVISION;
+ SpiInstance->SpiProtocol.FlashRead = SpiProtocolFlashRead;
+ SpiInstance->SpiProtocol.FlashWrite = SpiProtocolFlashWrite;
+ SpiInstance->SpiProtocol.FlashErase = SpiProtocolFlashErase;
+ SpiInstance->SpiProtocol.FlashReadSfdp = SpiProtocolFlashReadSfdp;
+ SpiInstance->SpiProtocol.FlashReadJedecId = SpiProtocolFlashReadJedecId;
+ SpiInstance->SpiProtocol.FlashWriteStatus = SpiProtocolFlashWriteStatus;
+ SpiInstance->SpiProtocol.FlashReadStatus = SpiProtocolFlashReadStatus;
+ SpiInstance->SpiProtocol.GetRegionAddress = SpiProtocolGetRegionAddress;
+ SpiInstance->SpiProtocol.ReadPchSoftStrap = SpiProtocolReadPchSoftStrap;
+ SpiInstance->SpiProtocol.ReadCpuSoftStrap = SpiProtocolReadCpuSoftStrap;
+
+ SpiInstance->PchSpiBase = SpiPciCfgBase ();
+
+ SpiInstance->PchAcpiBase = PmcGetAcpiBase ();
+ ASSERT (SpiInstance->PchAcpiBase != 0);
+
+ PchSpiBar0 = PciSegmentRead32 (SpiInstance->PchSpiBase + R_SPI_CFG_BAR0) & ~(B_SPI_CFG_BAR0_MASK);
+ if (PchSpiBar0 == 0) {
+ DEBUG ((DEBUG_ERROR, "ERROR : PchSpiBar0 is invalid!\n"));
+ ASSERT (FALSE);
+ }
+
+ if ((MmioRead32 (PchSpiBar0 + R_SPI_MEM_HSFSC) & B_SPI_MEM_HSFSC_FDV) == 0) {
+ DEBUG ((DEBUG_ERROR, "ERROR : SPI Flash Signature invalid, cannot use the Hardware Sequencing registers!\n"));
+ ASSERT (FALSE);
+ }
+
+ //
+ // Get Region 0 - 7 read Permission bits, region 8 and above are not permitted.
+ //
+ SpiInstance->ReadPermission = MmioRead8 (PchSpiBar0 + R_SPI_MEM_FRAP) & B_SPI_MEM_FRAP_BRRA_MASK;
+ DEBUG ((DEBUG_INFO, "Flash Region read Permission : %0x\n", SpiInstance->ReadPermission));
+ //
+ // Get Region 0 - 7 write Permission bits, region 8 and above are not permitted.
+ //
+ SpiInstance->WritePermission = (UINT8) ((MmioRead16 (PchSpiBar0 + R_SPI_MEM_FRAP) &
+ B_SPI_MEM_FRAP_BRWA_MASK) >> N_SPI_MEM_FRAP_BRWA);
+ DEBUG ((DEBUG_INFO, "Flash Region write Permission : %0x\n", SpiInstance->WritePermission));
+
+ SpiInstance->SfdpVscc0Value = MmioRead32 (PchSpiBar0 + R_SPI_MEM_SFDP0_VSCC0);
+ DEBUG ((DEBUG_INFO, "Component 0 SFDP VSCC value : %0x\n", SpiInstance->SfdpVscc0Value));
+ SpiInstance->SfdpVscc1Value = MmioRead32 (PchSpiBar0 + R_SPI_MEM_SFDP1_VSCC1);
+ DEBUG ((DEBUG_INFO, "Component 1 SFDP VSCC value : %0x\n", SpiInstance->SfdpVscc1Value));
+
+ //
+ // Select to Flash Map 0 Register to get the number of flash Component
+ //
+ MmioAndThenOr32 (
+ PchSpiBar0 + R_SPI_MEM_FDOC,
+ (UINT32) (~(B_SPI_MEM_FDOC_FDSS_MASK | B_SPI_MEM_FDOC_FDSI_MASK)),
+ (UINT32) (V_SPI_MEM_FDOC_FDSS_FSDM | R_FLASH_FDBAR_FLASH_MAP0)
+ );
+
+ //
+ // Copy Zero based Number Of Components
+ //
+ SpiInstance->NumberOfComponents = (UINT8) ((MmioRead16 (PchSpiBar0 + R_SPI_MEM_FDOD) & B_FLASH_FDBAR_NC) >> N_FLASH_FDBAR_NC);
+ DEBUG ((DEBUG_INFO, "Component Number : %0x\n", SpiInstance->NumberOfComponents + 1));
+
+ MmioAndThenOr32 (
+ PchSpiBar0 + R_SPI_MEM_FDOC,
+ (UINT32) (~(B_SPI_MEM_FDOC_FDSS_MASK | B_SPI_MEM_FDOC_FDSI_MASK)),
+ (UINT32) (V_SPI_MEM_FDOC_FDSS_COMP | R_FLASH_FCBA_FLCOMP)
+ );
+
+ //
+ // Copy Component 0 Density
+ //
+ Data32 = MmioRead32 (PchSpiBar0 + R_SPI_MEM_FDOD);
+ if (SpiInstance->NumberOfComponents > 0) {
+ SpiInstance->Component1StartAddr = V_FLASH_FLCOMP_COMP_512KB <<
+ (Data32 & B_FLASH_FLCOMP_COMP0_MASK);
+ DEBUG ((DEBUG_INFO, "Component 1 StartAddr : %0x\n", SpiInstance->Component1StartAddr));
+ SpiInstance->TotalFlashSize = SpiInstance->Component1StartAddr +
+ (V_FLASH_FLCOMP_COMP_512KB <<
+ ((Data32 & B_FLASH_FLCOMP_COMP1_MASK) >>
+ N_FLASH_FLCOMP_COMP1));
+ } else {
+ SpiInstance->TotalFlashSize = V_FLASH_FLCOMP_COMP_512KB <<
+ (Data32 & B_FLASH_FLCOMP_COMP0_MASK);
+ }
+ DEBUG ((DEBUG_INFO, "Total Flash Size : %0x\n", SpiInstance->TotalFlashSize));
+
+ //
+ // Select FLASH_MAP1 to get Flash PCH Strap Base Address
+ //
+ MmioAndThenOr32 (
+ (PchSpiBar0 + R_SPI_MEM_FDOC),
+ (UINT32) (~(B_SPI_MEM_FDOC_FDSS_MASK | B_SPI_MEM_FDOC_FDSI_MASK)),
+ (UINT32) (V_SPI_MEM_FDOC_FDSS_FSDM | R_FLASH_FDBAR_FLASH_MAP1)
+ );
+ //
+ // Align FPSBA with address bits for the PCH Strap portion of flash descriptor
+ //
+ Data32 = MmioRead32 (PchSpiBar0 + R_SPI_MEM_FDOD);
+ SpiInstance->PchStrapBaseAddr = (UINT16) (((Data32 & B_FLASH_FDBAR_FPSBA)
+ >> N_FLASH_FDBAR_FPSBA)
+ << N_FLASH_FDBAR_FPSBA_REPR);
+ DEBUG ((DEBUG_INFO, "PchStrapBaseAddr : %0x\n", SpiInstance->PchStrapBaseAddr));
+ ASSERT (SpiInstance->PchStrapBaseAddr != 0);
+ //
+ // PCH Strap Length, [31:24] represents number of Dwords
+ //
+ SpiInstance->PchStrapSize = (UINT16) (((Data32 & B_FLASH_FDBAR_PCHSL)
+ >> N_FLASH_FDBAR_PCHSL)
+ * sizeof (UINT32));
+ DEBUG ((DEBUG_INFO, "PchStrapSize : %0x\n", SpiInstance->PchStrapSize));
+
+ //
+ // Select FLASH_MAP2 to get Flash CPU Strap Base Address
+ //
+ MmioAndThenOr32 (
+ (PchSpiBar0 + R_SPI_MEM_FDOC),
+ (UINT32) (~(B_SPI_MEM_FDOC_FDSS_MASK | B_SPI_MEM_FDOC_FDSI_MASK)),
+ (UINT32) (V_SPI_MEM_FDOC_FDSS_FSDM | R_FLASH_FDBAR_FLASH_MAP2)
+ );
+ //
+ // Align FPSBA with address bits for the CPU Strap portion of flash descriptor
+ //
+ Data32 = MmioRead32 (PchSpiBar0 + R_SPI_MEM_FDOD);
+ //
+ // CPU Strap Length, [23:16] represents number of Dwords
+ //
+ SpiInstance->CpuStrapSize = (UINT16) (((Data32 & B_FLASH_FDBAR_CPUSL)
+ >> N_FLASH_FDBAR_CPUSL)
+ * sizeof (UINT32));
+
+ //
+ // CPU Strap Address [11:2] represent offset from MDTBA
+ //
+ SpiInstance->CpuStrapBaseAddr = (UINT16) ((Data32 & B_FLASH_FDBAR_FCPUSBA) >> N_FLASH_FDBAR_FCPUSBA);
+ ASSERT (SpiInstance->CpuStrapBaseAddr != 0);
+
+ //
+ // If CPU Strap base address is different than 0x300 need to add MDTBA value for final location
+ //
+ if (SpiInstance->CpuStrapBaseAddr != DEFAULT_CPU_STRAP_BASE_OFFSET) {
+ Status = SpiProtocolFlashRead (&(SpiInstance->SpiProtocol), FlashRegionAll, R_FLASH_UMAP1, sizeof (Data32), (UINT8 *) (&Data32));
+ ASSERT_EFI_ERROR (Status);
+ Mdtba = (UINT16)(((Data32 & B_FLASH_UMAP1_MDTBA) >> N_FLASH_UMAP1_MDTBA) << N_FLASH_UMAP1_MDTBA_REPR);
+ DEBUG ((DEBUG_INFO, "Mdtba : %0x\n", Mdtba));
+ // Add MDTBA offset for final address of CPU Straps
+ SpiInstance->CpuStrapBaseAddr += Mdtba;
+ }
+
+ DEBUG ((DEBUG_INFO, "CpuStrapBaseAddr : %0x\n", SpiInstance->CpuStrapBaseAddr));
+ DEBUG ((DEBUG_INFO, "CpuStrapSize : %0x\n", SpiInstance->CpuStrapSize));
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Delay for at least the request number of microseconds for Runtime usage.
+
+ @param[in] ABase Acpi base address
+ @param[in] Microseconds Number of microseconds to delay.
+
+**/
+VOID
+EFIAPI
+PchPmTimerStallRuntimeSafe (
+ IN UINT16 ABase,
+ IN UINTN Microseconds
+ )
+{
+ UINTN Ticks;
+ UINTN Counts;
+ UINTN CurrentTick;
+ UINTN OriginalTick;
+ UINTN RemainingTick;
+
+ if (Microseconds == 0) {
+ return;
+ }
+
+ OriginalTick = IoRead32 ((UINTN) (ABase + R_ACPI_IO_PM1_TMR)) & B_ACPI_IO_PM1_TMR_TMR_VAL;
+ CurrentTick = OriginalTick;
+
+ //
+ // The timer frequency is 3.579545 MHz, so 1 ms corresponds 3.58 clocks
+ //
+ Ticks = Microseconds * 358 / 100 + OriginalTick + 1;
+
+ //
+ // The loops needed by timer overflow
+ //
+ Counts = Ticks / V_ACPI_IO_PM1_TMR_MAX_VAL;
+
+ //
+ // Remaining clocks within one loop
+ //
+ RemainingTick = Ticks % V_ACPI_IO_PM1_TMR_MAX_VAL;
+
+ //
+ // not intend to use TMROF_STS bit of register PM1_STS, because this adds extra
+ // one I/O operation, and maybe generate SMI
+ //
+ while ((Counts != 0) || (RemainingTick > CurrentTick)) {
+ CurrentTick = IoRead32 ((UINTN) (ABase + R_ACPI_IO_PM1_TMR)) & B_ACPI_IO_PM1_TMR_TMR_VAL;
+ //
+ // Check if timer overflow
+ //
+ if ((CurrentTick < OriginalTick)) {
+ if (Counts != 0) {
+ Counts--;
+ } else {
+ //
+ // If timer overflow and Counts equ to 0, that means we already stalled more than
+ // RemainingTick, break the loop here
+ //
+ break;
+ }
+ }
+
+ OriginalTick = CurrentTick;
+ }
+}
+
+/**
+ Wait execution cycle to complete on the SPI interface.
+
+ @param[in] This The SPI protocol instance
+ @param[in] PchSpiBar0 Spi MMIO base address
+ @param[in] ErrorCheck TRUE if the SpiCycle needs to do the error check
+
+ @retval TRUE SPI cycle completed on the interface.
+ @retval FALSE Time out while waiting the SPI cycle to complete.
+ It's not safe to program the next command on the SPI interface.
+**/
+STATIC
+BOOLEAN
+WaitForSpiCycleComplete (
+ IN PCH_SPI_PROTOCOL *This,
+ IN UINTN PchSpiBar0,
+ IN BOOLEAN ErrorCheck
+ )
+{
+ UINT64 WaitTicks;
+ UINT64 WaitCount;
+ UINT32 Data32;
+ SPI_INSTANCE *SpiInstance;
+
+ SpiInstance = SPI_INSTANCE_FROM_SPIPROTOCOL (This);
+
+ //
+ // Convert the wait period allowed into to tick count
+ //
+ WaitCount = SPI_WAIT_TIME / SPI_WAIT_PERIOD;
+ //
+ // Wait for the SPI cycle to complete.
+ //
+ for (WaitTicks = 0; WaitTicks < WaitCount; WaitTicks++) {
+ Data32 = MmioRead32 (PchSpiBar0 + R_SPI_MEM_HSFSC);
+ if ((Data32 & B_SPI_MEM_HSFSC_SCIP) == 0) {
+ MmioWrite8 (PchSpiBar0 + R_SPI_MEM_HSFSC, B_SPI_MEM_HSFSC_FCERR | B_SPI_MEM_HSFSC_FDONE);
+ if (((Data32 & B_SPI_MEM_HSFSC_FCERR) != 0) && (ErrorCheck == TRUE)) {
+ return FALSE;
+ } else {
+ return TRUE;
+ }
+ }
+ PchPmTimerStallRuntimeSafe (SpiInstance->PchAcpiBase, SPI_WAIT_PERIOD);
+ }
+ return FALSE;
+}
+
+/**
+ This function waits for a pending SPI transaction to complete without clearing
+ status fields
+
+ @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
+ @param[in] PchSpiBar0 SPI MMIO address
+
+ @retval TRUE SPI cycle completed on the interface.
+ @retval FALSE Time out while waiting the SPI cycle to complete.
+ It's not safe to program the next command on the SPI interface.
+**/
+BOOLEAN
+STATIC
+WaitForScipNoClear (
+ IN PCH_SPI_PROTOCOL *This,
+ IN UINTN PchSpiBar0
+ )
+{
+ UINT64 WaitTicks;
+ UINT64 WaitCount;
+ SPI_INSTANCE *SpiInstance;
+ UINT32 Data32;
+
+ SpiInstance = SPI_INSTANCE_FROM_SPIPROTOCOL (This);
+
+ //
+ // Wait for the SPI cycle to complete.
+ //
+ WaitCount = SPI_WAIT_TIME / SPI_WAIT_PERIOD;
+ for (WaitTicks = 0; WaitTicks < WaitCount; WaitTicks++) {
+ Data32 = MmioRead32 (PchSpiBar0 + R_SPI_MEM_HSFSC);
+ if ((Data32 & B_SPI_MEM_HSFSC_SCIP) == 0) {
+ return TRUE;
+ }
+ PchPmTimerStallRuntimeSafe (SpiInstance->PchAcpiBase, SPI_WAIT_PERIOD);
+ }
+ return FALSE;
+}
+
+/**
+ This function sets the FDONE and optionally FCERR bits in the HSFS_CTL register
+
+ @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
+ @param[in] PchSpiBar0 SPI MMIO address
+ @param[in] SetErrorBit Set to TRUE to set the FCERR bit
+
+**/
+VOID
+STATIC
+SetHsfscFdone (
+ IN PCH_SPI_PROTOCOL *This,
+ IN UINTN PchSpiBar0,
+ IN BOOLEAN SetFcErrorBit
+ )
+{
+ EFI_STATUS Status;
+ UINT32 HardwareSpiAddr;
+ UINT32 FlashRegionSize;
+ UINT32 Index;
+ UINT8 DataCount;
+
+ Status = SpiProtocolGetRegionAddress (This, FlashRegionBios, &HardwareSpiAddr, &FlashRegionSize);
+ if (EFI_ERROR (Status)) {
+ return;
+ }
+
+ //
+ // Clear FDONE and FCERR
+ //
+ MmioWrite8 (PchSpiBar0 + R_SPI_MEM_HSFSC, B_SPI_MEM_HSFSC_FCERR | B_SPI_MEM_HSFSC_FDONE);
+
+ //
+ // Fill data buffer
+ //
+ if (SetFcErrorBit) {
+ for (Index = 0; Index < 64; Index += sizeof (UINT32)) {
+ MmioWrite32 (PchSpiBar0 + R_SPI_MEM_FDATA00 + Index, 0xFFFFFFFF);
+ }
+ }
+
+ //
+ // Set the Flash Address
+ //
+ MmioWrite32 (
+ (PchSpiBar0 + R_SPI_MEM_FADDR),
+ (UINT32) (HardwareSpiAddr & B_SPI_MEM_FADDR_MASK)
+ );
+ //
+ // Set Data count, Flash cycle, and Set Go bit to start a cycle
+ //
+ if (SetFcErrorBit) {
+ DataCount = 0x3F;
+ } else {
+ DataCount = 0;
+ }
+ MmioAndThenOr32 (
+ PchSpiBar0 + R_SPI_MEM_HSFSC,
+ (UINT32) (~(B_SPI_MEM_HSFSC_FDBC_MASK | B_SPI_MEM_HSFSC_CYCLE_MASK)),
+ (UINT32) (((DataCount << N_SPI_MEM_HSFSC_FDBC) & B_SPI_MEM_HSFSC_FDBC_MASK) |
+ (V_SPI_MEM_HSFSC_CYCLE_READ << N_SPI_MEM_HSFSC_CYCLE) |
+ B_SPI_MEM_HSFSC_CYCLE_FGO)
+ );
+
+ if (SetFcErrorBit) {
+ //
+ // Intentionally write to FDATA while a cycle is in progress to generate an error
+ //
+ for (Index = 0; Index < 64; Index += sizeof (UINT32)) {
+ MmioWrite32 (PchSpiBar0 + R_SPI_MEM_FDATA00 + Index, 0x0);
+ }
+ }
+
+ WaitForScipNoClear (This, PchSpiBar0);
+}
+
+/**
+ This function sends the programmed SPI command to the device.
+
+ @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
+ @param[in] SpiRegionType The SPI Region type for flash cycle which is listed in the Descriptor
+ @param[in] FlashCycleType The Flash SPI cycle type list in HSFC (Hardware Sequencing Flash Control Register) register
+ @param[in] Address The Flash Linear Address must fall within a region for which BIOS has access permissions.
+ @param[in] ByteCount Number of bytes in the data portion of the SPI cycle.
+ @param[in,out] Buffer Pointer to caller-allocated buffer containing the dada received or sent during the SPI cycle.
+
+ @retval EFI_SUCCESS SPI command completes successfully.
+ @retval EFI_DEVICE_ERROR Device error, the command aborts abnormally.
+ @retval EFI_ACCESS_DENIED Some unrecognized or blocked command encountered in hardware sequencing mode
+ @retval EFI_INVALID_PARAMETER The parameters specified are not valid.
+**/
+STATIC
+EFI_STATUS
+SendSpiCmd (
+ IN PCH_SPI_PROTOCOL *This,
+ IN FLASH_REGION_TYPE FlashRegionType,
+ IN FLASH_CYCLE_TYPE FlashCycleType,
+ IN UINT32 Address,
+ IN UINT32 ByteCount,
+ IN OUT UINT8 *Buffer
+ )
+{
+ UINT32 FdataSave[16];
+ EFI_STATUS Status;
+ UINT32 Index;
+ SPI_INSTANCE *SpiInstance;
+ UINT64 SpiBaseAddress;
+ UINTN PchSpiBar0;
+ UINT32 HardwareSpiAddr;
+ UINT32 FlashRegionSize;
+ UINT32 SpiDataCount;
+ UINT32 FlashCycle;
+ UINT8 BiosCtlSave;
+ UINT32 SmiEnSave;
+ UINT16 ABase;
+ UINT32 HsfstsCtl;
+ UINT32 FaddrSave;
+ UINT32 HsfscSave;
+ BOOLEAN HsfscFdoneSave;
+ BOOLEAN HsfscFcerrSave;
+ BOOLEAN RestoreState;
+
+ //
+ // For flash write, there is a requirement that all CPU threads are in SMM
+ // before the flash protection is disabled.
+ //
+ if ((FlashCycleType == FlashCycleWrite) || (FlashCycleType == FlashCycleErase)) {
+ if (!IsSpiFlashWriteGranted ()) {
+ return EFI_ACCESS_DENIED;
+ }
+ }
+
+ Status = EFI_SUCCESS;
+ SpiInstance = SPI_INSTANCE_FROM_SPIPROTOCOL (This);
+ SpiBaseAddress = SpiInstance->PchSpiBase;
+ ABase = SpiInstance->PchAcpiBase;
+ RestoreState = FALSE;
+
+ //
+ // Disable SMIs to make sure normal mode flash access is not interrupted by an SMI
+ // whose SMI handler accesses flash (e.g. for error logging)
+ //
+ // *** NOTE: if the SMI_LOCK bit is set (i.e., PMC PCI Offset A0h [4]='1'),
+ // clearing B_GBL_SMI_EN will not have effect. In this situation, some other
+ // synchronization methods must be applied here or in the consumer of the
+ // SendSpiCmd. An example method is disabling the specific SMI sources
+ // whose SMI handlers access flash before flash cycle and re-enabling the SMI
+ // sources after the flash cycle .
+ //
+ SmiEnSave = IoRead32 ((UINTN) (ABase + R_ACPI_IO_SMI_EN));
+ IoWrite32 ((UINTN) (ABase + R_ACPI_IO_SMI_EN), SmiEnSave & (UINT32) (~B_ACPI_IO_SMI_EN_GBL_SMI));
+ BiosCtlSave = PciSegmentRead8 (SpiBaseAddress + R_SPI_CFG_BC) & B_SPI_CFG_BC_SRC;
+
+ //
+ // Acquire SPI BAR0
+ //
+ PchSpiBar0 = AcquireSpiBar0 (SpiInstance);
+
+ //
+ // If it's write cycle, disable Prefetching, Caching and disable BIOS Write Protect
+ //
+ if ((FlashCycleType == FlashCycleWrite) ||
+ (FlashCycleType == FlashCycleErase)) {
+ Status = DisableBiosWriteProtect ();
+ if (EFI_ERROR (Status)) {
+ goto SendSpiCmdEnd;
+ }
+ PciSegmentAndThenOr8 (
+ SpiBaseAddress + R_SPI_CFG_BC,
+ (UINT8) (~B_SPI_CFG_BC_SRC),
+ (UINT8) (V_SPI_CFG_BC_SRC_PREF_DIS_CACHE_DIS << N_SPI_CFG_BC_SRC)
+ );
+ }
+
+ //
+ // Save current SPI controller state
+ //
+ if (IsSpiControllerSaveRestoreEnabled ()) {
+ if (!WaitForScipNoClear (This, PchSpiBar0)) {
+ Status = EFI_DEVICE_ERROR;
+ goto SendSpiCmdEnd;
+ }
+ HsfscSave = MmioRead32 (PchSpiBar0 + R_SPI_MEM_HSFSC);
+ HsfscFdoneSave = ((HsfscSave & B_SPI_MEM_HSFSC_FDONE) != 0) ? TRUE : FALSE;
+ HsfscFcerrSave = ((HsfscSave & B_SPI_MEM_HSFSC_FCERR) != 0) ? TRUE : FALSE;
+ HsfscSave &= B_SPI_MEM_HSFSC_SAVE_MASK;
+ FaddrSave = MmioRead32 (PchSpiBar0 + R_SPI_MEM_FADDR);
+ for (Index = 0; Index < 64; Index += sizeof (UINT32)) {
+ FdataSave[Index >> 2] = MmioRead32 (PchSpiBar0 + R_SPI_MEM_FDATA00 + Index);
+ }
+ RestoreState = TRUE;
+ }
+
+ //
+ // Make sure it's safe to program the command.
+ //
+ if (!WaitForSpiCycleComplete (This, PchSpiBar0, FALSE)) {
+ Status = EFI_DEVICE_ERROR;
+ goto SendSpiCmdEnd;
+ }
+
+ //
+ // Check if Write Status isn't disabled in HW Sequencing
+ //
+ if (FlashCycleType == FlashCycleWriteStatus) {
+ HsfstsCtl = MmioRead32 (PchSpiBar0 + R_SPI_MEM_HSFSC);
+ if ((HsfstsCtl & B_SPI_MEM_HSFSC_WRSDIS) != 0) {
+ Status = EFI_ACCESS_DENIED;
+ goto SendSpiCmdEnd;
+ }
+ }
+
+ Status = SpiProtocolGetRegionAddress (This, FlashRegionType, &HardwareSpiAddr, &FlashRegionSize);
+ if (EFI_ERROR (Status)) {
+ goto SendSpiCmdEnd;
+ }
+ HardwareSpiAddr += Address;
+ if ((Address + ByteCount) > FlashRegionSize) {
+ Status = EFI_INVALID_PARAMETER;
+ goto SendSpiCmdEnd;
+ }
+
+ //
+ // Check for PCH SPI hardware sequencing required commands
+ //
+ FlashCycle = 0;
+ switch (FlashCycleType) {
+ case FlashCycleRead:
+ FlashCycle = (UINT32) (V_SPI_MEM_HSFSC_CYCLE_READ << N_SPI_MEM_HSFSC_CYCLE);
+ break;
+ case FlashCycleWrite:
+ FlashCycle = (UINT32) (V_SPI_MEM_HSFSC_CYCLE_WRITE << N_SPI_MEM_HSFSC_CYCLE);
+ break;
+ case FlashCycleErase:
+ if (((ByteCount % SIZE_4KB) != 0) ||
+ ((HardwareSpiAddr % SIZE_4KB) != 0)) {
+ ASSERT (FALSE);
+ Status = EFI_INVALID_PARAMETER;
+ goto SendSpiCmdEnd;
+ }
+ break;
+ case FlashCycleReadSfdp:
+ FlashCycle = (UINT32) (V_SPI_MEM_HSFSC_CYCLE_READ_SFDP << N_SPI_MEM_HSFSC_CYCLE);
+ break;
+ case FlashCycleReadJedecId:
+ FlashCycle = (UINT32) (V_SPI_MEM_HSFSC_CYCLE_READ_JEDEC_ID << N_SPI_MEM_HSFSC_CYCLE);
+ break;
+ case FlashCycleWriteStatus:
+ FlashCycle = (UINT32) (V_SPI_MEM_HSFSC_CYCLE_WRITE_STATUS << N_SPI_MEM_HSFSC_CYCLE);
+ break;
+ case FlashCycleReadStatus:
+ FlashCycle = (UINT32) (V_SPI_MEM_HSFSC_CYCLE_READ_STATUS << N_SPI_MEM_HSFSC_CYCLE);
+ break;
+ default:
+ //
+ // Unrecognized Operation
+ //
+ ASSERT (FALSE);
+ Status = EFI_INVALID_PARAMETER;
+ goto SendSpiCmdEnd;
+ break;
+ }
+
+ do {
+ SpiDataCount = ByteCount;
+ if ((FlashCycleType == FlashCycleRead) ||
+ (FlashCycleType == FlashCycleWrite) ||
+ (FlashCycleType == FlashCycleReadSfdp)) {
+ //
+ // Trim at 256 byte boundary per operation,
+ // - PCH SPI controller requires trimming at 4KB boundary
+ // - Some SPI chips require trimming at 256 byte boundary for write operation
+ // - Trimming has limited performance impact as we can read / write at most 64 bytes
+ // per operation
+ //
+ if (HardwareSpiAddr + ByteCount > ((HardwareSpiAddr + BIT8) &~(BIT8 - 1))) {
+ SpiDataCount = (((UINT32) (HardwareSpiAddr) + BIT8) &~(BIT8 - 1)) - (UINT32) (HardwareSpiAddr);
+ }
+ //
+ // Calculate the number of bytes to shift in/out during the SPI data cycle.
+ // Valid settings for the number of bytes during each data portion of the
+ // PCH SPI cycles are: 0, 1, 2, 3, 4, 5, 6, 7, 8, 16, 24, 32, 40, 48, 56, 64
+ //
+ if (SpiDataCount >= 64) {
+ SpiDataCount = 64;
+ } else if ((SpiDataCount &~0x07) != 0) {
+ SpiDataCount = SpiDataCount &~0x07;
+ }
+ }
+ if (FlashCycleType == FlashCycleErase) {
+ if (((ByteCount / SIZE_64KB) != 0) &&
+ ((ByteCount % SIZE_64KB) == 0) &&
+ ((HardwareSpiAddr % SIZE_64KB) == 0)) {
+ if ((SpiInstance->NumberOfComponents == 0) ||
+ (HardwareSpiAddr < SpiInstance->Component1StartAddr)) {
+ //
+ // Check whether Component0 support 64k Erase
+ //
+ if ((SpiInstance->SfdpVscc0Value & B_SPI_MEM_SFDPX_VSCCX_EO_64K) != 0) {
+ SpiDataCount = SIZE_64KB;
+ } else {
+ SpiDataCount = SIZE_4KB;
+ }
+ } else {
+ //
+ // Check whether Component1 support 64k Erase
+ //
+ if ((SpiInstance->SfdpVscc1Value & B_SPI_MEM_SFDPX_VSCCX_EO_64K) != 0) {
+ SpiDataCount = SIZE_64KB;
+ } else {
+ SpiDataCount = SIZE_4KB;
+ }
+ }
+ } else {
+ SpiDataCount = SIZE_4KB;
+ }
+ if (SpiDataCount == SIZE_4KB) {
+ FlashCycle = (UINT32) (V_SPI_MEM_HSFSC_CYCLE_4K_ERASE << N_SPI_MEM_HSFSC_CYCLE);
+ } else {
+ FlashCycle = (UINT32) (V_SPI_MEM_HSFSC_CYCLE_64K_ERASE << N_SPI_MEM_HSFSC_CYCLE);
+ }
+ }
+ //
+ // If it's write cycle, load data into the SPI data buffer.
+ //
+ if ((FlashCycleType == FlashCycleWrite) || (FlashCycleType == FlashCycleWriteStatus)) {
+ if ((SpiDataCount & 0x07) != 0) {
+ //
+ // Use Byte write if Data Count is 0, 1, 2, 3, 4, 5, 6, 7
+ //
+ for (Index = 0; Index < SpiDataCount; Index++) {
+ MmioWrite8 (PchSpiBar0 + R_SPI_MEM_FDATA00 + Index, Buffer[Index]);
+ }
+ } else {
+ //
+ // Use Dword write if Data Count is 8, 16, 24, 32, 40, 48, 56, 64
+ //
+ for (Index = 0; Index < SpiDataCount; Index += sizeof (UINT32)) {
+ MmioWrite32 (PchSpiBar0 + R_SPI_MEM_FDATA00 + Index, *(UINT32 *) (Buffer + Index));
+ }
+ }
+ }
+
+ //
+ // Set the Flash Address
+ //
+ MmioWrite32 (
+ (PchSpiBar0 + R_SPI_MEM_FADDR),
+ (UINT32) (HardwareSpiAddr & B_SPI_MEM_FADDR_MASK)
+ );
+
+ //
+ // Set Data count, Flash cycle, and Set Go bit to start a cycle
+ //
+ MmioAndThenOr32 (
+ PchSpiBar0 + R_SPI_MEM_HSFSC,
+ (UINT32) (~(B_SPI_MEM_HSFSC_FDBC_MASK | B_SPI_MEM_HSFSC_CYCLE_MASK)),
+ (UINT32) ((((SpiDataCount - 1) << N_SPI_MEM_HSFSC_FDBC) & B_SPI_MEM_HSFSC_FDBC_MASK) | FlashCycle | B_SPI_MEM_HSFSC_CYCLE_FGO)
+ );
+ //
+ // end of command execution
+ //
+ // Wait the SPI cycle to complete.
+ //
+ if (!WaitForSpiCycleComplete (This, PchSpiBar0, TRUE)) {
+ ASSERT (FALSE);
+ Status = EFI_DEVICE_ERROR;
+ goto SendSpiCmdEnd;
+ }
+ //
+ // If it's read cycle, load data into the call's buffer.
+ //
+ if ((FlashCycleType == FlashCycleRead) ||
+ (FlashCycleType == FlashCycleReadSfdp) ||
+ (FlashCycleType == FlashCycleReadJedecId) ||
+ (FlashCycleType == FlashCycleReadStatus)) {
+ if ((SpiDataCount & 0x07) != 0) {
+ //
+ // Use Byte read if Data Count is 0, 1, 2, 3, 4, 5, 6, 7
+ //
+ for (Index = 0; Index < SpiDataCount; Index++) {
+ Buffer[Index] = MmioRead8 (PchSpiBar0 + R_SPI_MEM_FDATA00 + Index);
+ }
+ } else {
+ //
+ // Use Dword read if Data Count is 8, 16, 24, 32, 40, 48, 56, 64
+ //
+ for (Index = 0; Index < SpiDataCount; Index += sizeof (UINT32)) {
+ *(UINT32 *) (Buffer + Index) = MmioRead32 (PchSpiBar0 + R_SPI_MEM_FDATA00 + Index);
+ }
+ }
+ }
+
+ HardwareSpiAddr += SpiDataCount;
+ Buffer += SpiDataCount;
+ ByteCount -= SpiDataCount;
+ } while (ByteCount > 0);
+
+SendSpiCmdEnd:
+ //
+ // Restore SPI controller state
+ //
+ if (RestoreState) {
+ if (HsfscFdoneSave) {
+ SetHsfscFdone (This, PchSpiBar0, HsfscFcerrSave);
+ }
+ MmioAndThenOr32 (
+ PchSpiBar0 + R_SPI_MEM_HSFSC,
+ (UINT32) ~(B_SPI_MEM_HSFSC_SAVE_MASK |
+ B_SPI_MEM_HSFSC_SAF_CE | // This bit clears when set to 1, ensure 0 is written
+ B_SPI_MEM_HSFSC_SAF_LE | // This bit clears when set to 1, ensure 0 is written
+ B_SPI_MEM_HSFSC_SAF_DLE | // This bit clears when set to 1, ensure 0 is written
+ B_SPI_MEM_HSFSC_SAF_ERROR | // This bit clears when set to 1, ensure 0 is written
+ B_SPI_MEM_HSFSC_AEL | // This bit clears when set to 1, ensure 0 is written
+ B_SPI_MEM_HSFSC_FCERR | // This bit clears when set to 1, ensure 0 is written
+ B_SPI_MEM_HSFSC_FDONE), // This bit clears when set to 1, ensure 0 is written
+ HsfscSave
+ );
+ MmioWrite32 (PchSpiBar0 + R_SPI_MEM_FADDR, FaddrSave);
+ for (Index = 0; Index < 64; Index += sizeof (UINT32)) {
+ MmioWrite32 (PchSpiBar0 + R_SPI_MEM_FDATA00 + Index, FdataSave[Index >> 2]);
+ }
+ }
+
+ //
+ // Restore the settings for SPI Prefetching and Caching and enable BIOS Write Protect
+ //
+ if ((FlashCycleType == FlashCycleWrite) ||
+ (FlashCycleType == FlashCycleErase)) {
+ EnableBiosWriteProtect ();
+ PciSegmentAndThenOr8 (
+ SpiBaseAddress + R_SPI_CFG_BC,
+ (UINT8) ~B_SPI_CFG_BC_SRC,
+ BiosCtlSave
+ );
+ }
+ ReleaseSpiBar0 (SpiInstance);
+
+ //
+ // Restore SMIs.
+ //
+ IoWrite32 ((UINTN) (ABase + R_ACPI_IO_SMI_EN), SmiEnSave);
+
+ return Status;
+}
+
+/**
+ Read data from the flash part.
+
+ @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
+ @param[in] FlashRegionType The Flash Region type for flash cycle which is listed in the Descriptor.
+ @param[in] Address The Flash Linear Address must fall within a region for which BIOS has access permissions.
+ @param[in] ByteCount Number of bytes in the data portion of the SPI cycle.
+ @param[out] Buffer The Pointer to caller-allocated buffer containing the dada received.
+ It is the caller's responsibility to make sure Buffer is large enough for the total number of bytes read.
+
+ @retval EFI_SUCCESS Command succeed.
+ @retval EFI_INVALID_PARAMETER The parameters specified are not valid.
+ @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
+**/
+EFI_STATUS
+EFIAPI
+SpiProtocolFlashRead (
+ IN PCH_SPI_PROTOCOL *This,
+ IN FLASH_REGION_TYPE FlashRegionType,
+ IN UINT32 Address,
+ IN UINT32 ByteCount,
+ OUT UINT8 *Buffer
+ )
+{
+ EFI_STATUS Status;
+
+ //
+ // Sends the command to the SPI interface to execute.
+ //
+ Status = SendSpiCmd (
+ This,
+ FlashRegionType,
+ FlashCycleRead,
+ Address,
+ ByteCount,
+ Buffer
+ );
+ return Status;
+}
+
+/**
+ Write data to the flash part.
+
+ @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
+ @param[in] FlashRegionType The Flash Region type for flash cycle which is listed in the Descriptor.
+ @param[in] Address The Flash Linear Address must fall within a region for which BIOS has access permissions.
+ @param[in] ByteCount Number of bytes in the data portion of the SPI cycle.
+ @param[in] Buffer Pointer to caller-allocated buffer containing the data sent during the SPI cycle.
+
+ @retval EFI_SUCCESS Command succeed.
+ @retval EFI_INVALID_PARAMETER The parameters specified are not valid.
+ @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
+**/
+EFI_STATUS
+EFIAPI
+SpiProtocolFlashWrite (
+ IN PCH_SPI_PROTOCOL *This,
+ IN FLASH_REGION_TYPE FlashRegionType,
+ IN UINT32 Address,
+ IN UINT32 ByteCount,
+ IN UINT8 *Buffer
+ )
+{
+ EFI_STATUS Status;
+
+ //
+ // Sends the command to the SPI interface to execute.
+ //
+ Status = SendSpiCmd (
+ This,
+ FlashRegionType,
+ FlashCycleWrite,
+ Address,
+ ByteCount,
+ Buffer
+ );
+ return Status;
+}
+
+/**
+ Erase some area on the flash part.
+
+ @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
+ @param[in] FlashRegionType The Flash Region type for flash cycle which is listed in the Descriptor.
+ @param[in] Address The Flash Linear Address must fall within a region for which BIOS has access permissions.
+ @param[in] ByteCount Number of bytes in the data portion of the SPI cycle.
+
+ @retval EFI_SUCCESS Command succeed.
+ @retval EFI_INVALID_PARAMETER The parameters specified are not valid.
+ @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
+**/
+EFI_STATUS
+EFIAPI
+SpiProtocolFlashErase (
+ IN PCH_SPI_PROTOCOL *This,
+ IN FLASH_REGION_TYPE FlashRegionType,
+ IN UINT32 Address,
+ IN UINT32 ByteCount
+ )
+{
+ EFI_STATUS Status;
+
+ //
+ // Sends the command to the SPI interface to execute.
+ //
+ Status = SendSpiCmd (
+ This,
+ FlashRegionType,
+ FlashCycleErase,
+ Address,
+ ByteCount,
+ NULL
+ );
+ return Status;
+}
+
+/**
+ Read SFDP data from the flash part.
+
+ @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
+ @param[in] ComponentNumber The Componen Number for chip select
+ @param[in] Address The starting byte address for SFDP data read.
+ @param[in] ByteCount Number of bytes in SFDP data portion of the SPI cycle
+ @param[out] SfdpData The Pointer to caller-allocated buffer containing the SFDP data received
+ It is the caller's responsibility to make sure Buffer is large enough for the total number of bytes read
+
+ @retval EFI_SUCCESS Command succeed.
+ @retval EFI_INVALID_PARAMETER The parameters specified are not valid.
+ @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
+ @retval EFI_UNSUPPORTED Unsupported operation with SAF Mode enabled
+**/
+EFI_STATUS
+EFIAPI
+SpiProtocolFlashReadSfdp (
+ IN PCH_SPI_PROTOCOL *This,
+ IN UINT8 ComponentNumber,
+ IN UINT32 Address,
+ IN UINT32 ByteCount,
+ OUT UINT8 *SfdpData
+ )
+{
+ return EFI_SUCCESS;
+}
+
+/**
+ Read Jedec Id from the flash part.
+
+ @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
+ @param[in] ComponentNumber The Componen Number for chip select
+ @param[in] ByteCount Number of bytes in JedecId data portion of the SPI cycle, the data size is 3 typically
+ @param[out] JedecId The Pointer to caller-allocated buffer containing JEDEC ID received
+ It is the caller's responsibility to make sure Buffer is large enough for the total number of bytes read.
+
+ @retval EFI_SUCCESS Command succeed.
+ @retval EFI_INVALID_PARAMETER The parameters specified are not valid.
+ @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
+ @retval EFI_UNSUPPORTED Unsupported operation with SAF Mode enabled
+**/
+EFI_STATUS
+EFIAPI
+SpiProtocolFlashReadJedecId (
+ IN PCH_SPI_PROTOCOL *This,
+ IN UINT8 ComponentNumber,
+ IN UINT32 ByteCount,
+ OUT UINT8 *JedecId
+ )
+{
+ return EFI_SUCCESS;
+}
+
+/**
+ Write the status register in the flash part.
+
+ @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
+ @param[in] ByteCount Number of bytes in Status data portion of the SPI cycle, the data size is 1 typically
+ @param[in] StatusValue The Pointer to caller-allocated buffer containing the value of Status register writing
+
+ @retval EFI_SUCCESS Command succeed.
+ @retval EFI_INVALID_PARAMETER The parameters specified are not valid.
+ @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
+ @retval EFI_UNSUPPORTED Unsupported operation with SAF Mode enabled
+**/
+EFI_STATUS
+EFIAPI
+SpiProtocolFlashWriteStatus (
+ IN PCH_SPI_PROTOCOL *This,
+ IN UINT32 ByteCount,
+ IN UINT8 *StatusValue
+ )
+{
+ return EFI_SUCCESS;
+}
+
+/**
+ Read status register in the flash part.
+
+ @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
+ @param[in] ByteCount Number of bytes in Status data portion of the SPI cycle, the data size is 1 typically
+ @param[out] StatusValue The Pointer to caller-allocated buffer containing the value of Status register received.
+
+ @retval EFI_SUCCESS Command succeed.
+ @retval EFI_INVALID_PARAMETER The parameters specified are not valid.
+ @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
+ @retval EFI_UNSUPPORTED Unsupported operation with SAF Mode enabled
+**/
+EFI_STATUS
+EFIAPI
+SpiProtocolFlashReadStatus (
+ IN PCH_SPI_PROTOCOL *This,
+ IN UINT32 ByteCount,
+ OUT UINT8 *StatusValue
+ )
+{
+ return EFI_SUCCESS;
+}
+
+/**
+ Get the SPI region base and size, based on the enum type
+
+ @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
+ @param[in] FlashRegionType The Flash Region type for for the base address which is listed in the Descriptor.
+ @param[out] BaseAddress The Flash Linear Address for the Region 'n' Base
+ @param[out] RegionSize The size for the Region 'n'
+
+ @retval EFI_SUCCESS Read success
+ @retval EFI_INVALID_PARAMETER Invalid region type given
+ @retval EFI_DEVICE_ERROR The region is not used
+**/
+EFI_STATUS
+EFIAPI
+SpiProtocolGetRegionAddress (
+ IN PCH_SPI_PROTOCOL *This,
+ IN FLASH_REGION_TYPE FlashRegionType,
+ OUT UINT32 *BaseAddress,
+ OUT UINT32 *RegionSize
+ )
+{
+ SPI_INSTANCE *SpiInstance;
+ UINTN PchSpiBar0;
+ UINT32 ReadValue;
+
+ SpiInstance = SPI_INSTANCE_FROM_SPIPROTOCOL (This);
+
+ if (FlashRegionType >= FlashRegionMax) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ if (FlashRegionType == FlashRegionAll) {
+ *BaseAddress = 0;
+ *RegionSize = SpiInstance->TotalFlashSize;
+ return EFI_SUCCESS;
+ }
+
+ PchSpiBar0 = AcquireSpiBar0 (SpiInstance);
+
+ ReadValue = MmioRead32 (PchSpiBar0 + (R_SPI_MEM_FREG0_FLASHD + (S_SPI_MEM_FREGX * ((UINT32) FlashRegionType))));
+
+ ReleaseSpiBar0 (SpiInstance);
+
+ //
+ // If the region is not used, the Region Base is 7FFFh and Region Limit is 0000h
+ //
+ if (ReadValue == B_SPI_MEM_FREGX_BASE_MASK) {
+ return EFI_DEVICE_ERROR;
+ }
+ *BaseAddress = ((ReadValue & B_SPI_MEM_FREGX_BASE_MASK) >> N_SPI_MEM_FREGX_BASE) <<
+ N_SPI_MEM_FREGX_BASE_REPR;
+ //
+ // Region limit address Bits[11:0] are assumed to be FFFh
+ //
+ *RegionSize = ((((ReadValue & B_SPI_MEM_FREGX_LIMIT_MASK) >> N_SPI_MEM_FREGX_LIMIT) + 1) <<
+ N_SPI_MEM_FREGX_LIMIT_REPR) - *BaseAddress;
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Read PCH Soft Strap Values
+
+ @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
+ @param[in] SoftStrapAddr PCH Soft Strap address offset from FPSBA.
+ @param[in] ByteCount Number of bytes in SoftStrap data portion of the SPI cycle
+ @param[out] SoftStrapValue The Pointer to caller-allocated buffer containing PCH Soft Strap Value.
+ If the value of ByteCount is 0, the data type of SoftStrapValue should be UINT16 and SoftStrapValue will be PCH Soft Strap Length
+ It is the caller's responsibility to make sure Buffer is large enough for the total number of bytes read.
+
+ @retval EFI_SUCCESS Command succeed.
+ @retval EFI_INVALID_PARAMETER The parameters specified are not valid.
+ @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
+**/
+EFI_STATUS
+EFIAPI
+SpiProtocolReadPchSoftStrap (
+ IN PCH_SPI_PROTOCOL *This,
+ IN UINT32 SoftStrapAddr,
+ IN UINT32 ByteCount,
+ OUT VOID *SoftStrapValue
+ )
+{
+ return EFI_SUCCESS;
+}
+
+/**
+ Read CPU Soft Strap Values
+
+ @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
+ @param[in] SoftStrapAddr CPU Soft Strap address offset from FCPUSBA.
+ @param[in] ByteCount Number of bytes in SoftStrap data portion of the SPI cycle.
+ @param[out] SoftStrapValue The Pointer to caller-allocated buffer containing CPU Soft Strap Value.
+ If the value of ByteCount is 0, the data type of SoftStrapValue should be UINT16 and SoftStrapValue will be PCH Soft Strap Length
+ It is the caller's responsibility to make sure Buffer is large enough for the total number of bytes read.
+
+ @retval EFI_SUCCESS Command succeed.
+ @retval EFI_INVALID_PARAMETER The parameters specified are not valid.
+ @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
+**/
+EFI_STATUS
+EFIAPI
+SpiProtocolReadCpuSoftStrap (
+ IN PCH_SPI_PROTOCOL *This,
+ IN UINT32 SoftStrapAddr,
+ IN UINT32 ByteCount,
+ OUT VOID *SoftStrapValue
+ )
+{
+ return EFI_SUCCESS;
+}
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/Smm/Spi.c b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/Smm/Spi.c
new file mode 100644
index 0000000000..2dd80eba7c
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/Smm/Spi.c
@@ -0,0 +1,387 @@
+/** @file
+ PCH SPI SMM Driver implements the SPI Host Controller Compatibility Interface.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <Library/IoLib.h>
+#include <Library/DebugLib.h>
+#include <Library/UefiDriverEntryPoint.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/BaseLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/SmmServicesTableLib.h>
+#include <Library/PciSegmentLib.h>
+#include <Protocol/Spi.h>
+#include <Protocol/SmmCpu.h>
+#include <Library/SpiCommonLib.h>
+#include <PchReservedResources.h>
+#include <Library/PchPciBdfLib.h>
+#include <IndustryStandard/Pci30.h>
+#include <Register/PchRegs.h>
+#include <Register/SpiRegs.h>
+
+//
+// Global variables
+//
+GLOBAL_REMOVE_IF_UNREFERENCED SPI_INSTANCE *mSpiInstance;
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_SMM_CPU_PROTOCOL *mSmmCpuProtocol;
+//
+// mPchSpiResvMmioAddr keeps the reserved MMIO range assigned to SPI.
+// In SMM it always set back the reserved MMIO address to SPI BAR0 to ensure the MMIO range
+// won't overlap with SMRAM range, and trusted.
+//
+GLOBAL_REMOVE_IF_UNREFERENCED UINT32 mSpiResvMmioAddr;
+//
+// mPchSpiSavedMmioAddr keeps the MMIO range assigned to SPI by PCI enumeration.
+// In SMM this is used to restore the original value for SPI BAR0 after finishing
+// commands to the SPI controller.
+//
+GLOBAL_REMOVE_IF_UNREFERENCED UINT32 mSpiSavedMmioAddr;
+//
+// mPchSpiBar0RefCount stores the reference count for SPI BAR0.
+//
+GLOBAL_REMOVE_IF_UNREFERENCED UINT32 mPchSpiBar0RefCount;
+//
+// mPchSpiSavedPciCmdReg stores the PCI command register state at the start of the
+// SPI transaction. This is used to restore the original PCI command register
+// state after finishing commands to the SPI controller.
+//
+GLOBAL_REMOVE_IF_UNREFERENCED UINT8 mPchSpiSavedPciCmdReg;
+GLOBAL_REMOVE_IF_UNREFERENCED BOOLEAN mBootServiceExited;
+
+/**
+ This function is invoked at ExitBootServices()
+
+ @param[in] Protocol Protocol unique ID.
+ @param[in] Interface Interface instance.
+ @param[in] Handle The handle on which the interface is installed..
+
+ @retval Status.
+**/
+EFI_STATUS
+EFIAPI
+SpiExitBootServicesCallback (
+ IN CONST EFI_GUID *Protocol,
+ IN VOID *Interface,
+ IN EFI_HANDLE Handle
+ )
+{
+ mBootServiceExited = TRUE;
+ return EFI_SUCCESS;
+}
+
+/**
+ <b>SPI Runtime SMM Module Entry Point</b>\n
+ - <b>Introduction</b>\n
+ The SPI SMM module provide a standard way for other modules to use the PCH SPI Interface in SMM.
+
+ - @pre
+ - EFI_SMM_BASE2_PROTOCOL
+ - Documented in System Management Mode Core Interface Specification .
+
+ - @result
+ The SPI SMM driver produces @link _PCH_SPI_PROTOCOL PCH_SPI_PROTOCOL @endlink with GUID
+ gPchSmmSpiProtocolGuid which is different from SPI RUNTIME driver.
+
+ - <b>Integration Check List</b>\n
+ - This driver supports Descriptor Mode only.
+ - This driver supports Hardware Sequence only.
+ - When using SMM SPI Protocol to perform flash access in an SMI handler,
+ and the SMI occurrence is asynchronous to normal mode code execution,
+ proper synchronization mechanism must be applied, e.g. disable SMI before
+ the normal mode SendSpiCmd() starts and re-enable SMI after
+ the normal mode SendSpiCmd() completes.
+ @note The implementation of SendSpiCmd() uses GBL_SMI_EN in
+ SMI_EN register (ABase + 30h) to disable and enable SMIs. But this may
+ not be effective as platform may well set the SMI_LOCK bit (i.e., PMC PCI Offset A0h [4]).
+ So the synchronization at caller level is likely needed.
+
+ @param[in] ImageHandle Image handle of this driver.
+ @param[in] SystemTable Global system service table.
+
+ @retval EFI_SUCCESS Initialization complete.
+ @exception EFI_UNSUPPORTED The chipset is unsupported by this driver.
+ @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize the driver.
+ @retval EFI_DEVICE_ERROR Device error, driver exits abnormally.
+**/
+EFI_STATUS
+EFIAPI
+InstallPchSpi (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUS Status;
+ VOID *Registration;
+
+ //
+ // Init PCH spi reserved MMIO address.
+ //
+ mSpiResvMmioAddr = PCH_SPI_BASE_ADDRESS;
+ mSpiSavedMmioAddr = 0;
+ mPchSpiBar0RefCount = 0;
+ mPchSpiSavedPciCmdReg = 0;
+ mBootServiceExited = FALSE;
+
+ ///
+ /// Allocate pool for SPI protocol instance
+ ///
+ Status = gSmst->SmmAllocatePool (
+ EfiRuntimeServicesData, /// MemoryType don't care
+ sizeof (SPI_INSTANCE),
+ (VOID **) &mSpiInstance
+ );
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ if (mSpiInstance == NULL) {
+ return EFI_OUT_OF_RESOURCES;
+ }
+
+ ZeroMem ((VOID *) mSpiInstance, sizeof (SPI_INSTANCE));
+ ///
+ /// Initialize the SPI protocol instance
+ ///
+ Status = SpiProtocolConstructor (mSpiInstance);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ //
+ // Register ExitBootServices callback
+ //
+ Status = gSmst->SmmRegisterProtocolNotify (
+ &gEdkiiSmmExitBootServicesProtocolGuid,
+ SpiExitBootServicesCallback,
+ &Registration
+ );
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ //
+ // Install the SMM PCH_SPI_PROTOCOL interface
+ //
+ Status = gSmst->SmmInstallProtocolInterface (
+ &(mSpiInstance->Handle),
+ &gPchSmmSpiProtocolGuid,
+ EFI_NATIVE_INTERFACE,
+ &(mSpiInstance->SpiProtocol)
+ );
+ if (EFI_ERROR (Status)) {
+ gSmst->SmmFreePool (mSpiInstance);
+ return EFI_DEVICE_ERROR;
+ }
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Acquire PCH SPI MMIO address.
+ It is not expected for this BAR0 to change because the SPI device is usually
+ hidden from the OS. But if it is ever different from the preallocated address,
+ reassign it back. In SMM, BAR0 will always be overwritten and the reserved
+ MMIO range for SPI will be returned.
+
+ @param[in] SpiInstance Pointer to SpiInstance to initialize
+
+ @retval PchSpiBar0 return SPI MMIO address
+**/
+UINTN
+AcquireSpiBar0 (
+ IN SPI_INSTANCE *SpiInstance
+ )
+{
+ UINT32 SpiBar0;
+ UINT8 PciCmdReg;
+
+ //
+ // Save original SPI physical MMIO address
+ //
+ SpiBar0 = PciSegmentRead32 (SpiInstance->PchSpiBase + R_SPI_CFG_BAR0) & ~(B_SPI_CFG_BAR0_MASK);
+ PciCmdReg = PciSegmentRead8 (SpiInstance->PchSpiBase + PCI_COMMAND_OFFSET);
+
+ if ((SpiBar0 != mSpiResvMmioAddr) || ((PciCmdReg & EFI_PCI_COMMAND_MEMORY_SPACE) == 0)) {
+ //
+ // Save PCI command register state and BAR value assigned by PCI enumeration
+ //
+ mPchSpiSavedPciCmdReg = PciCmdReg;
+ mSpiSavedMmioAddr = SpiBar0;
+
+ //
+ // Temporary disable MSE, and override with SPI reserved MMIO address, then enable MSE.
+ //
+ PciSegmentAnd8 (SpiInstance->PchSpiBase + PCI_COMMAND_OFFSET, (UINT8) ~EFI_PCI_COMMAND_MEMORY_SPACE);
+ PciSegmentWrite32 (SpiInstance->PchSpiBase + R_SPI_CFG_BAR0, mSpiResvMmioAddr);
+ PciSegmentOr8 (SpiInstance->PchSpiBase + PCI_COMMAND_OFFSET, EFI_PCI_COMMAND_MEMORY_SPACE);
+ } else if (mPchSpiBar0RefCount == 0) {
+ mSpiSavedMmioAddr = 0;
+ mPchSpiSavedPciCmdReg = 0;
+ }
+ mPchSpiBar0RefCount++;
+
+ //
+ // SPIBAR0 will be different before and after PCI enum so need to get it from SPI BAR0 reg.
+ //
+ return mSpiResvMmioAddr;
+}
+
+/**
+ Release PCH SPI MMIO address. If AcquireSpiBar0() previously overwrote the
+ value of BAR0, this function will restore the original value assigned by PCI
+ enumeration
+
+ @param[in] SpiInstance Pointer to SpiInstance to initialize
+
+ @retval None
+**/
+VOID
+ReleaseSpiBar0 (
+ IN SPI_INSTANCE *SpiInstance
+ )
+{
+ //
+ // Reference counting is used here because multiple nested calls to
+ // AcquireSpiBar0()/ReleaseSpiBar0() will cause SpiBar0 to be reprogrammed
+ // back to the original value before access to the SPI controller is done.
+ // Reference counting ensures that the BAR is not restored until after access
+ // is complete.
+ //
+ if (mPchSpiBar0RefCount <= 1) {
+ mPchSpiBar0RefCount = 0;
+ if (mSpiSavedMmioAddr != 0) {
+ //
+ // Temporary disable MSE, restore the original SPI MMIO address, then
+ // restore PCI command register state
+ //
+ PciSegmentAnd8 (SpiInstance->PchSpiBase + PCI_COMMAND_OFFSET, (UINT8)~EFI_PCI_COMMAND_MEMORY_SPACE);
+ PciSegmentWrite32 (SpiInstance->PchSpiBase + R_SPI_CFG_BAR0, mSpiSavedMmioAddr);
+ PciSegmentWrite8 (SpiInstance->PchSpiBase + PCI_COMMAND_OFFSET, mPchSpiSavedPciCmdReg);
+
+ //
+ // Clear saved state
+ //
+ mSpiSavedMmioAddr = 0;
+ mPchSpiSavedPciCmdReg = 0;
+ }
+ } else {
+ mPchSpiBar0RefCount--;
+ }
+}
+
+/**
+ This function is a hook for Spi to disable BIOS Write Protect
+
+ @retval EFI_SUCCESS The protocol instance was properly initialized
+ @retval EFI_ACCESS_DENIED The BIOS Region can only be updated in SMM phase
+
+**/
+EFI_STATUS
+EFIAPI
+DisableBiosWriteProtect (
+ VOID
+ )
+{
+ UINT64 SpiBaseAddress;
+
+ SpiBaseAddress = SpiPciCfgBase ();
+ // Write clear BC_SYNC_SS prior to change WPD from 0 to 1.
+ //
+ PciSegmentOr8 (
+ SpiBaseAddress + R_SPI_CFG_BC + 1,
+ (B_SPI_CFG_BC_SYNC_SS >> 8)
+ );
+ ///
+ /// Set BIOSWE bit (SPI PCI Offset DCh [0]) = 1b
+ /// Enable the access to the BIOS space for both read and write cycles
+ ///
+ PciSegmentOr8 (
+ SpiBaseAddress + R_SPI_CFG_BC,
+ B_SPI_CFG_BC_WPD
+ );
+
+ return EFI_SUCCESS;
+}
+
+/**
+ This function is a hook for Spi to enable BIOS Write Protect
+**/
+VOID
+EFIAPI
+EnableBiosWriteProtect (
+ VOID
+ )
+{
+ UINT64 SpiBaseAddress;
+
+ SpiBaseAddress = SpiPciCfgBase ();
+ ///
+ /// Clear BIOSWE bit (SPI PCI Offset DCh [0]) = 0b
+ /// Disable the access to the BIOS space for write cycles
+ ///
+ PciSegmentAnd8 (
+ SpiBaseAddress + R_SPI_CFG_BC,
+ (UINT8) (~B_SPI_CFG_BC_WPD)
+ );
+
+}
+
+/**
+ Check if it's granted to do flash write.
+
+ @retval TRUE It's secure to do flash write.
+ @retval FALSE It's not secure to do flash write.
+**/
+BOOLEAN
+IsSpiFlashWriteGranted (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+ UINT32 CpuIndex;
+ UINT64 ProcessorId;
+
+ if (mSmmCpuProtocol == NULL) {
+ Status = gSmst->SmmLocateProtocol (&gEfiSmmCpuProtocolGuid, NULL, (VOID **)&mSmmCpuProtocol);
+ ASSERT_EFI_ERROR (Status);
+ if (mSmmCpuProtocol == NULL) {
+ return TRUE;
+ }
+ }
+
+ for (CpuIndex = 0; CpuIndex < gSmst->NumberOfCpus; CpuIndex++) {
+ Status = mSmmCpuProtocol->ReadSaveState (
+ mSmmCpuProtocol,
+ sizeof (ProcessorId),
+ EFI_SMM_SAVE_STATE_REGISTER_PROCESSOR_ID,
+ CpuIndex,
+ &ProcessorId
+ );
+ //
+ // If the processor is in SMM at the time the SMI occurred,
+ // it will return success. Otherwise, EFI_NOT_FOUND is returned.
+ //
+ if (EFI_ERROR (Status)) {
+ return FALSE;
+ }
+ }
+
+ return TRUE;
+}
+
+/**
+ Check if a save and restore of the SPI controller state is necessary
+
+ @retval TRUE It's necessary to save and restore SPI controller state
+ @retval FALSE It's not necessary to save and restore SPI controller state
+**/
+BOOLEAN
+IsSpiControllerSaveRestoreEnabled (
+ VOID
+ )
+{
+ return mBootServiceExited;
+}
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/Smm/SpiSmm.inf b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/Smm/SpiSmm.inf
new file mode 100644
index 0000000000..78913423fb
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Spi/Smm/SpiSmm.inf
@@ -0,0 +1,46 @@
+## @file
+# Component description file for the SPI SMM driver.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+
+[Defines]
+INF_VERSION = 0x00010017
+BASE_NAME = SpiSmm
+FILE_GUID = 27F4917B-A707-4aad-9676-26DF168CBF0D
+VERSION_STRING = 1.0
+MODULE_TYPE = DXE_SMM_DRIVER
+PI_SPECIFICATION_VERSION = 1.10
+ENTRY_POINT = InstallPchSpi
+
+
+[LibraryClasses]
+DebugLib
+IoLib
+UefiDriverEntryPoint
+UefiBootServicesTableLib
+BaseLib
+SmmServicesTableLib
+SpiCommonLib
+PchPciBdfLib
+
+[Packages]
+MdePkg/MdePkg.dec
+AlderlakeSiliconPkg/SiPkg.dec
+
+
+[Sources]
+Spi.c
+
+
+[Protocols]
+gPchSmmSpiProtocolGuid ## PRODUCES
+gEfiSmmCpuProtocolGuid ## CONSUMES
+gEdkiiSmmExitBootServicesProtocolGuid ## CONSUMES
+
+
+[Depex]
+gEfiSmmBase2ProtocolGuid AND # This is for SmmServicesTableLib
+gEfiSmmCpuProtocolGuid
--
2.36.1.windows.1
-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#108740): https://edk2.groups.io/g/devel/message/108740
Mute This Topic: https://groups.io/mt/101373948/7686176
Group Owner: devel+owner@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [rebecca@openfw.io]
-=-=-=-=-=-=-=-=-=-=-=-
^ permalink raw reply related [flat|nested] 41+ messages in thread
* Re: [edk2-devel] [PATCH v2 05/10] AlderlakeSiliconPkg/Include: Add ConfigBlock headers
2023-09-15 4:45 ` [edk2-devel] [PATCH v2 05/10] AlderlakeSiliconPkg/Include: Add ConfigBlock headers Saloni Kasbekar
2023-09-15 5:42 ` Chaganty, Rangasai V
@ 2023-09-15 23:56 ` Nate DeSimone
1 sibling, 0 replies; 41+ messages in thread
From: Nate DeSimone @ 2023-09-15 23:56 UTC (permalink / raw)
To: Kasbekar, Saloni, devel@edk2.groups.io
Cc: Chaganty, Rangasai V, Chuang, Rosen
Acked-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
-----Original Message-----
From: Kasbekar, Saloni <saloni.kasbekar@intel.com>
Sent: Thursday, September 14, 2023 9:46 PM
To: devel@edk2.groups.io
Cc: Kasbekar, Saloni <saloni.kasbekar@intel.com>; Chaganty, Rangasai V <rangasai.v.chaganty@intel.com>; Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>; Chuang, Rosen <rosen.chuang@intel.com>
Subject: [PATCH v2 05/10] AlderlakeSiliconPkg/Include: Add ConfigBlock headers
Adds the header includes for the ConfigBlocks
Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Rosen Chuang <rosen.chuang@intel.com>
Signed-off-by: Saloni Kasbekar <saloni.kasbekar@intel.com>
---
.../CpuPcieRp/Gen3/CpuPcieConfigGen3.h | 48 ++
.../CpuPcieRp/Gen4/CpuPcieConfig.h | 240 ++++++++
.../Include/ConfigBlock/Espi/LpcConfig.h | 38 ++
.../Include/ConfigBlock/Fivr/FivrConfig.h | 183 ++++++
.../Include/ConfigBlock/Gpio/GpioDevConfig.h | 37 ++
.../Graphics/Gen12/GraphicsConfig.h | 212 +++++++
.../HostBridge/Ver1/HostBridgeConfig.h | 58 ++
.../ConfigBlock/Itss/InterruptConfig.h | 38 ++
.../ConfigBlock/Memory/Ver2/MemoryConfig.h | 551 ++++++++++++++++++
.../Include/ConfigBlock/PchDmi/PchDmiConfig.h | 65 +++
.../PcieRp/PchPcieRp/PchPcieRpConfig.h | 180 ++++++
.../Include/ConfigBlock/PcieRp/PcieConfig.h | 408 +++++++++++++
.../ConfigBlock/PcieRp/PciePreMemConfig.h | 36 ++
.../Include/ConfigBlock/Pmc/AdrConfig.h | 76 +++
.../Include/ConfigBlock/Pmc/PmConfig.h | 86 +++
.../Include/ConfigBlock/Rtc/RtcConfig.h | 37 ++
.../ConfigBlock/SerialIo/SerialIoConfig.h | 33 ++
.../Include/ConfigBlock/SiConfig.h | 105 ++++
.../Include/ConfigBlock/SiPreMemConfig.h | 63 ++
.../Include/ConfigBlock/Smbus/SmbusConfig.h | 49 ++
.../ConfigBlock/Spi/FlashProtectionConfig.h | 54 ++
.../Include/ConfigBlock/Tcss/TcssPeiConfig.h | 71 +++
.../Include/ConfigBlock/Vmd/VmdPeiConfig.h | 60 ++
.../Include/ConfigBlock/Wdt/WatchDogConfig.h | 30 +
24 files changed, 2758 insertions(+)
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/CpuPcieRp/Gen3/CpuPcieConfigGen3.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/CpuPcieRp/Gen4/CpuPcieConfig.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Espi/LpcConfig.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Fivr/FivrConfig.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Gpio/GpioDevConfig.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Graphics/Gen12/GraphicsConfig.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/HostBridge/Ver1/HostBridgeConfig.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Itss/InterruptConfig.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Memory/Ver2/MemoryConfig.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/PchDmi/PchDmiConfig.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/PcieRp/PchPcieRp/PchPcieRpConfig.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/PcieRp/PcieConfig.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/PcieRp/PciePreMemConfig.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Pmc/AdrConfig.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Pmc/PmConfig.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Rtc/RtcConfig.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/SerialIo/SerialIoConfig.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/SiConfig.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/SiPreMemConfig.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Smbus/SmbusConfig.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Spi/FlashProtectionConfig.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Tcss/TcssPeiConfig.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Vmd/VmdPeiConfig.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Wdt/WatchDogConfig.h
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/CpuPcieRp/Gen3/CpuPcieConfigGen3.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/CpuPcieRp/Gen3/CpuPcieConfigGen3.h
new file mode 100644
index 0000000000..5b437c8311
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/CpuPcieRp/Gen3/CpuPcieConfigGen3.h
@@ -0,0 +1,48 @@
+/** @file
+Pcie root port policy
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _CPU_PCIE_CONFIG_GEN3_H_
+#define _CPU_PCIE_CONFIG_GEN3_H_
+
+#include <Library/GpioLib.h>
+#include <Library/CpuPcieInfoFruLib.h>
+#include <PcieConfig.h>
+#include <ConfigBlock.h>
+#include <Register/SaRegsHostBridge.h>
+
+#pragma pack(push, 1)
+
+
+#define L0_SET BIT0
+#define L1_SET BIT1
+
+
+///
+/// SA GPIO Data Structure
+///
+typedef struct {
+ GPIO_PAD GpioPad; ///< Offset 0: GPIO Pad
+ UINT8 Value; ///< Offset 4: GPIO Value
+ UINT8 Rsvd0[3]; ///< Offset 5: Reserved for 4 bytes alignment
+ UINT32 Active : 1; ///< Offset 8: 0=Active Low; 1=Active High
+ UINT32 RsvdBits0 : 31;
+} SA_GPIO_INFO_PCIE;
+
+///
+/// SA Board PEG GPIO Info
+///
+typedef struct {
+ SA_GPIO_INFO_PCIE SaPeg0ResetGpio; ///< Offset 0: PEG0 PERST# GPIO assigned, must be a PCH GPIO pin
+ SA_GPIO_INFO_PCIE SaPeg3ResetGpio; ///< Offset 12: PEG3 PERST# GPIO assigned, must be a PCH GPIO pin
+ BOOLEAN GpioSupport; ///< Offset 24: 1=Supported; 0=Not Supported
+ UINT8 Rsvd0[3]; ///< Offset 25: Reserved for 4 bytes alignment
+} PEG_GPIO_DATA;
+
+
+#pragma pack (pop)
+
+#endif // _CPU_PCIE_CONFIG_GEN3_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/CpuPcieRp/Gen4/CpuPcieConfig.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/CpuPcieRp/Gen4/CpuPcieConfig.h
new file mode 100644
index 0000000000..999748d711
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/CpuPcieRp/Gen4/CpuPcieConfig.h
@@ -0,0 +1,240 @@
+/** @file
+ Pcie root port policy
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _CPU_PCIE_CONFIG_H_
+#define _CPU_PCIE_CONFIG_H_
+
+#include <Library/GpioLib.h>
+#include <Library/CpuPcieInfoFruLib.h>
+#include <PcieConfig.h>
+#include <ConfigBlock.h>
+#include <Register/SaRegsHostBridge.h>
+
+#pragma pack(push, 1)
+
+#define CPU_PCIE_RP_PREMEM_CONFIG_REVISION 1
+
+/**
+ Making any setup structure change after code frozen
+ will need to maintain backward compatibility, bump up
+ structure revision and update below history table\n
+ <b>Revision 1</b>: - Initial version.
+**/
+
+#define CPU_PCIE_CONFIG_REVISION 10
+
+#define L0_SET BIT0
+#define L1_SET BIT1
+
+/**
+ CPU PCIe Root Port Pre-Memory Configuration
+ Contains Root Port settings and capabilities
+ <b>Revision 1</b>: - Initial version.
+ <b>Revision 2</b>: - Adding Dekel Suqelch Workaround Setup Variable
+ <b>Revision 3</b>: - Deprecate Dekel Suqelch Workaround Setup Variable
+ <b>Revision 4</b>: - Adding New FOM Setup Variable
+ <b>Revision 5</b>: - Add CdrRelock Policy to CPU_PCIE_RP_PREMEM_CONFIG.
+**/
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Config Block Header
+ /**
+ Root Port enabling mask.
+ Bit0 presents RP1, Bit1 presents RP2, and so on.
+ 0: Disable; <b>1: Enable</b>.
+ **/
+ UINT32 RpEnabledMask;
+ /**
+ Assertion on Link Down GPIOs
+ - <b>Disabled</b> (0x0) : Disable assertion on Link Down GPIOs(Default)
+ - Enabled (0x1) : Enable assertion on Link Down GPIOs
+ **/
+ UINT8 LinkDownGpios;
+ /**
+ Enable ClockReq Messaging
+ - <b>Disabled</> (0x0) : Disable ClockReq Messaging(Default)
+ - Enabled (0x1) : Enable ClockReq Messaging
+ **/
+ UINT8 ClkReqMsgEnable;
+ /**
+ Dekel Recipe Workaround
+ <b>2</b>
+ 1=Minimal, 9=Maximum,
+ **/
+ UINT8 DekelSquelchWa; // Deprecated variable
+ UINT8 Rsvd0[1];
+ /**
+ Determines each PCIE Port speed capability.
+ <b>0: Auto</b>; 1: Gen1; 2: Gen2; 3: Gen3; 4: Gen4 (see: CPU_PCIE_SPEED)
+ **/
+ UINT8 PcieSpeed[CPU_PCIE_MAX_ROOT_PORTS];
+
+ /**
+ Enable ClockReq Messaging Policy is for all Rootports
+ - <b>Disabled</> (0x0) : Disable ClockReq Messaging(Default)
+ - Enabled (0x1) : Enable ClockReq Messaging
+ **/
+ UINT8 ClkReqMsgEnableRp[CPU_PCIE_MAX_ROOT_PORTS];
+ /**
+ To Enable/Disable New FOM
+ <b>0: Disable</b>; 1: Enable
+ **/
+ UINT8 NewFom[CPU_PCIE_MAX_ROOT_PORTS];
+ /**
+ To Enable/Disable CDR Relock
+ <b>0: Disable</b>; 1: Enable
+ **/
+ UINT8 CdrRelock[CPU_PCIE_MAX_ROOT_PORTS];
+} CPU_PCIE_RP_PREMEM_CONFIG;
+
+/**
+ Represent lane specific PCIe Gen3 equalization parameters.
+**/
+typedef struct {
+ UINT8 Cm; ///< Coefficient C-1
+ UINT8 Cp; ///< Coefficient C+1
+ UINT8 PegGen3RootPortPreset; ///< <b>(Test)</b> Used for programming PEG Gen3 preset values per lane. Range: 0-9, 8 is default for each lane
+ UINT8 PegGen3EndPointPreset; ///< <b>(Test)</b> Used for programming PEG Gen3 preset values per lane. Range: 0-9, 7 is default for each lane
+ UINT8 PegGen3EndPointHint; ///< <b>(Test)</b> Hint value per lane for the PEG Gen3 End Point. Range: 0-6, 2 is default for each lane
+ UINT8 PegGen4RootPortPreset; ///< <b>(Test)</b> Used for programming PEG Gen4 preset values per lane. Range: 0-9, 8 is default for each lane
+ UINT8 PegGen4EndPointPreset; ///< <b>(Test)</b> Used for programming PEG Gen4 preset values per lane. Range: 0-9, 7 is default for each lane
+ UINT8 PegGen4EndPointHint; ///< <b>(Test)</b> Hint value per lane for the PEG Gen4 End Point. Range: 0-6, 2 is default for each lane
+} CPU_PCIE_EQ_LANE_PARAM;
+
+/**
+ The CPU_PCI_ROOT_PORT_CONFIG describe the feature and capability of each CPU PCIe root port.
+**/
+typedef struct {
+
+ UINT32 ExtSync : 1; ///< Indicate whether the extended synch is enabled. <b>0: Disable</b>; 1: Enable.
+ UINT32 MultiVcEnabled : 1; ///< Multiple Virtual Channel. 0: Disable; <b>1: Enable</b>
+ UINT32 RsvdBits0 : 30; ///< Reserved bits
+ /**
+ PCIe Gen4 Equalization Method
+ - HwEq (0x1) : Hardware Equalization (Default)
+ - StaticEq (0x2) : Static Equalization
+ **/
+ UINT8 Gen4EqPh3Method;
+ UINT8 FomsCp; ///< FOM Score Board Control Policy
+ UINT8 RsvdBytes0[2]; ///< Reserved bytes
+
+ //
+ // Gen3 Equalization settings
+ //
+ UINT32 Gen3Uptp : 4; ///< <b>(Test)</b> Upstream Port Transmitter Preset used during Gen3 Link Equalization. Used for all lanes. Default is <b>7</b>.
+ UINT32 Gen3Dptp : 4; ///< <b>(Test)</b> Downstream Port Transmiter Preset used during Gen3 Link Equalization. Used for all lanes. Default is <b>7</b>.
+ //
+ // Gen4 Equalization settings
+ //
+ UINT32 Gen4Uptp : 4; ///< <b>(Test)</b> Upstream Port Transmitter Preset used during Gen4 Link Equalization. Used for all lanes. Default is <b>7</b>.
+ UINT32 Gen4Dptp : 4; ///< <b>(Test)</b> Downstream Port Transmiter Preset used during Gen4 Link Equalization. Used for all lanes. Default is <b>7</b>.
+ //
+ // Gen5 Equalization settings
+ //
+ UINT32 Gen5Uptp : 4; ///< <b>(Test)</b> Upstream Port Transmitter Preset used during Gen5 Link Equalization. Used for all lanes. Default is <b>5</b>.
+ UINT32 Gen5Dptp : 4; ///< <b>(Test)</b> Downstream Port Transmiter Preset used during Gen5 Link Equalization. Used for all lanes. Default is <b>7</b>.
+ UINT32 RsvdBits1 : 8; ///< Reserved Bits
+
+ PCIE_ROOT_PORT_COMMON_CONFIG PcieRpCommonConfig; ///< <b>(Test)</b> Includes policies which are common to both SA and PCH RootPort
+
+} CPU_PCIE_ROOT_PORT_CONFIG;
+
+typedef struct {
+ UINT8 PcieGen3PresetCoeffSelection; ///<Gen3 Preset or Coefficient Selection
+ UINT8 PcieGen4PresetCoeffSelection; ///<Gen4 Preset or Coefficient Selection
+ UINT8 PcieGen5PresetCoeffSelection; ///<Gen5 Preset or Coefficient Selection
+ UINT8 Func0LinkDisable; ///< Disable Func0 Port
+} CPU_PCIE_ROOT_PORT_CONFIG2;
+
+/**
+ The CPU_PCIE_CONFIG block describes the expected configuration of the CPU PCI Express controllers
+ <b>Revision 1< / b>:
+ -Initial version.
+ <b>Revision 2</b>:
+ - SlotSelection policy added
+ <b>Revision 3</b>
+ - Deprecate PegGen3ProgramStaticEq and PegGen4ProgramStaticEq
+ <b>Revision 4</b>:
+ - Deprecating SetSecuredRegisterLock
+ <b>Revision 5</b>:
+ - Moved ClockGating policy to PCIE_ROOT_PORT_COMMON_CONFIG
+ - Moved PowerGating policy to PCIE_ROOT_PORT_COMMON_CONFIG
+ - Deprecate VcEnabled policy
+ <b>Revision 7</b>:
+ - Deprecating Gen3PresetCoeffSelection and Gen4PresetCoeffSelection
+ <b>Revision 8</b>:
+ - Added Serl policy
+ <b>Revision 9</b>:
+ - Align revision with CPU_PCIE_CONFIG_REVISION value
+ <b>Revision 10</b>:
+ - Deprecate EqPh3LaneParam.Cm and EqPh3LaneParam.Cp
+**/
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Config Block Header
+ ///
+ /// These members describe the configuration of each SA PCIe root port.
+ ///
+ CPU_PCIE_ROOT_PORT_CONFIG RootPort[CPU_PCIE_MAX_ROOT_PORTS];
+ ///
+ /// Gen3 Equalization settings for physical PCIe lane, index 0 represents PCIe lane 1, etc.
+ /// Corresponding entries are used when root port EqPh3Method is PchPcieEqStaticCoeff (default).
+ ///
+ CPU_PCIE_EQ_LANE_PARAM EqPh3LaneParam[SA_PEG_MAX_LANE]; //@ Deprecated Policy
+ ///
+ /// List of coefficients used during equalization (applicable to both software and hardware EQ)
+ ///
+ PCIE_EQ_PARAM HwEqGen4CoeffList[PCIE_HWEQ_COEFFS_MAX]; //@ Deprecated Policy
+
+ PCIE_COMMON_CONFIG PcieCommonConfig; /// < <b>(Test)</b> Includes policies which are common to both SA and PCH PCIe
+
+ UINT32 FiaProgramming : 1; /// < Skip Fia Configuration and lock if enable
+ // Deprecated Policy
+ /**
+ <b>(Test)</b> Program PEG Gen3 EQ Phase1 Static Presets
+ - Disabled (0x0) : Disable EQ Phase1 Static Presets Programming
+ - <b>Enabled</b> (0x1) : Enable EQ Phase1 Static Presets Programming (Default)
+ **/
+ UINT32 PegGen3ProgramStaticEq : 1;
+
+ // Deprecated Policy
+ /**
+ <b>(Test)</b> Program PEG Gen4 EQ Phase1 Static Presets
+ - Disabled (0x0) : Disable EQ Phase1 Static Presets Programming
+ - <b>Enabled</b> (0x1) : Enable EQ Phase1 Static Presets Programming (Default)
+ **/
+ UINT32 PegGen4ProgramStaticEq : 1;
+ /**
+ <b>(Test)</b> Cpu Pcie Secure Register Lock
+ - Disabled (0x0)
+ - <b>Enabled</b> (0x1)
+ **/
+ UINT32 SetSecuredRegisterLock : 1; // Deprecated Policy
+ ///
+ /// This member allows to select between the PCI Express M2 or CEMx4 slot <b>1: PCIe M2</b>; 0: CEMx4 slot.
+ ///
+ UINT32 SlotSelection : 1;
+
+ UINT32 Serl : 1;
+
+ UINT32 RsvdBits0 : 26;
+
+ /**
+ PCIe device override table
+ The PCIe device table is being used to override PCIe device ASPM settings.
+ This is a pointer points to a 32bit address. And it's only used in PostMem phase.
+ Please refer to PCIE_DEVICE_OVERRIDE structure for the table.
+ Last entry VendorId must be 0.
+ The prototype of this policy is:
+ PCIE_DEVICE_OVERRIDE *PcieDeviceOverrideTablePtr;
+ **/
+ UINT32 PcieDeviceOverrideTablePtr;
+ CPU_PCIE_ROOT_PORT_CONFIG2 RootPort2[CPU_PCIE_MAX_ROOT_PORTS];
+ PCIE_COMMON_CONFIG2 PcieCommonConfig2;
+ } CPU_PCIE_CONFIG;
+
+#pragma pack (pop)
+
+#endif // _CPU_PCIE_CONFIG_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Espi/LpcConfig.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Espi/LpcConfig.h
new file mode 100644
index 0000000000..324facde78
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Espi/LpcConfig.h
@@ -0,0 +1,38 @@
+/** @file
+ Lpc policy
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _LPC_CONFIG_H_
+#define _LPC_CONFIG_H_
+
+#define PCH_LPC_PREMEM_CONFIG_REVISION 1
+extern EFI_GUID gLpcPreMemConfigGuid;
+
+#pragma pack (push,1)
+
+/**
+ This structure contains the policies which are related to LPC.
+**/
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Config Block Header
+ /**
+ Enhance the port 8xh decoding.
+ Original LPC only decodes one byte of port 80h, with this enhancement LPC can decode word or dword of port 80h-83h.
+ @note: this will occupy one LPC generic IO range register. While this is enabled, read from port 80h always return 0x00.
+ 0: Disable, <b>1: Enable</b>
+ **/
+ UINT32 EnhancePort8xhDecoding : 1;
+ /**
+ Hardware Autonomous Enable.
+ When enabled, LPC will automatically engage power gating when it has reached its idle condition.
+ 0: Disable, <b>1: Enable</b>
+ **/
+ UINT32 LpcPmHAE : 1;
+ UINT32 RsvdBits : 30; ///< Reserved bits
+} PCH_LPC_PREMEM_CONFIG;
+
+#pragma pack (pop)
+
+#endif // _LPC_CONFIG_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Fivr/FivrConfig.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Fivr/FivrConfig.h
new file mode 100644
index 0000000000..501e00c0e1
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Fivr/FivrConfig.h
@@ -0,0 +1,183 @@
+/** @file
+ PCH FIVR policy
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _FIVR_CONFIG_H_
+#define _FIVR_CONFIG_H_
+
+/**
+ <b>Revision 1</b>: - Initial version.
+**/
+#define PCH_FIVR_CONFIG_REVISION 1
+extern EFI_GUID gFivrConfigGuid;
+
+#pragma pack (push,1)
+
+/**
+ Rail support in S0ix and Sx
+ Settings other than FivrRailDisabled can be OR'ed
+**/
+typedef enum {
+ FivrRailDisabled = 0,
+ FivrRailInS0i1S0i2 = BIT0,
+ FivrRailInS0i3 = BIT1,
+ FivrRailInS3 = BIT2,
+ FivrRailInS4 = BIT3,
+ FivrRailInS5 = BIT4,
+ FivrRailInS0ix = FivrRailInS0i1S0i2 | FivrRailInS0i3,
+ FivrRailInSx = FivrRailInS3 | FivrRailInS4 | FivrRailInS5,
+ FivrRailAlwaysOn = FivrRailInS0ix | FivrRailInSx
+} FIVR_RAIL_SX_STATE;
+
+typedef enum {
+ FivrRetentionActive = BIT0,
+ FivrNormActive = BIT1,
+ FivrMinActive = BIT2,
+ FivrMinRetention = BIT3
+} FIVR_RAIL_SUPPORTED_VOLTAGE;
+
+/**
+ Structure for V1p05/Vnn VR rail configuration
+**/
+typedef struct {
+ /**
+ Mask to enable the usage of external VR rail in specific S0ix or Sx states
+ Use values from FIVR_RAIL_SX_STATE
+ The default is <b>FivrRailDisabled</b>.
+ **/
+ UINT32 EnabledStates : 6;
+
+ /**
+ VR rail voltage value that will be used in S0i2/S0i3 states.
+ This value is given in 2.5mV increments (0=0mV, 1=2.5mV, 2=5mV...)
+ The default for Vnn is set to <b>420 - 1050 mV</b>.
+ **/
+ UINT32 Voltage : 11;
+ /**
+ @deprecated
+ THIS POLICY IS DEPRECATED, PLEASE USE IccMaximum INSTEAD
+ VR rail Icc Max Value
+ Granularity of this setting is 1mA and maximal possible value is 500mA
+ The default is <b> 0mA </b>.
+ **/
+ UINT32 IccMax : 8;
+ /**
+ UINT32 Alignement
+ **/
+ UINT32 RsvdBits1 : 7;
+ /**
+ This register holds the control hold off values to be used when
+ changing the rail control for external bypass value in us
+ **/
+ UINT32 CtrlRampTmr : 8;
+
+ /**
+ Mask to set the supported configuration in VR rail.
+ Use values from FIVR_RAIL_SUPPORTED_VOLTAGE
+ **/
+ UINT32 SupportedVoltageStates : 4;
+
+ /**
+ VR rail Icc Maximum Value
+ Granularity of this setting is 1mA and maximal possible value is 500mA
+ The default is <b> 0mA </b>.
+ **/
+ UINT32 IccMaximum : 16;
+ /**
+ UINT32 Alignment
+ **/
+ UINT32 RsvdBits2 : 4;
+
+} FIVR_EXT_RAIL_CONFIG;
+
+
+/**
+ Structure for VCCIN_AUX voltage rail configuration
+**/
+typedef struct {
+ /**
+ Transition time in microseconds from Low Current Mode Voltage to High Current Mode Voltage.
+ Voltage transition time required by motherboard voltage regulator when PCH changes
+ the VCCIN_AUX regulator set point from the low current mode voltage and high current mode voltage.
+ This field has 1us resolution.
+ When value is 0 PCH will not transition VCCIN_AUX to low current mode voltage.
+ The default is <b> 0xC </b>.
+ **/
+ UINT8 LowToHighCurModeVolTranTime;
+
+ /**
+ Transition time in microseconds from Retention Mode Voltage to High Current Mode Voltage.
+ Voltage transition time required by motherboard voltage regulator when PCH changes
+ the VCCIN_AUX regulator set point from the retention mode voltage to high current mode voltage.
+ This field has 1us resolution.
+ When value is 0 PCH will not transition VCCIN_AUX to retention voltage.
+ The default is <b> 0x36 </b>.
+ **/
+ UINT8 RetToHighCurModeVolTranTime;
+
+ /**
+ Transition time in microseconds from Retention Mode Voltage to Low Current Mode Voltage.
+ Voltage transition time required by motherboard voltage regulator when PCH changes
+ the VCCIN_AUX regulator set point from the retention mode voltage to low current mode voltage.
+ This field has 1us resolution.
+ When value is 0 PCH will not transition VCCIN_AUX to retention voltage.
+ The default is <b> 0x2B </b>.
+ **/
+ UINT8 RetToLowCurModeVolTranTime;
+ UINT8 RsvdByte1;
+ /**
+ Transition time in microseconds from Off (0V) to High Current Mode Voltage.
+ Voltage transition time required by motherboard voltage regulator when PCH changes
+ the VCCIN_AUX regulator set point from 0V to the high current mode voltage.
+ This field has 1us resolution.
+ 0 = Transition to 0V is disabled
+ Setting this field to 0 sets VCCIN_AUX as a fixed rail that stays on
+ in all S0 & Sx power states after initial start up on G3 exit
+ The default is <b> 0x96 </b>.
+ **/
+ UINT32 OffToHighCurModeVolTranTime : 11;
+ UINT32 RsvdBits1 : 21;
+} FIVR_VCCIN_AUX_CONFIG;
+
+/**
+ The PCH_FIVR_CONFIG block describes FIVR settings.
+**/
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Config Block Header
+ /**
+ External V1P05 VR rail configuration.
+ **/
+ FIVR_EXT_RAIL_CONFIG ExtV1p05Rail;
+ /**
+ External Vnn VR rail configuration.
+ **/
+ FIVR_EXT_RAIL_CONFIG ExtVnnRail;
+ /**
+ Additional External Vnn VR rail configuration that will get applied
+ in Sx entry SMI callback. Required only if External Vnn VR
+ needs different settings for Sx than those specified in ExtVnnRail.
+ **/
+ FIVR_EXT_RAIL_CONFIG ExtVnnRailSx;
+ /**
+ VCCIN_AUX voltage rail configuration.
+ **/
+ FIVR_VCCIN_AUX_CONFIG VccinAux;
+
+ /**
+ Enable/Disable FIVR Dynamic Power Management
+ Default is <b> 1 </b>.
+ **/
+ UINT32 FivrDynPm : 1;
+ /**
+ Enable/Disable Bypass of FIVR configuration
+ Default is <b> 0 </b>.
+ **/
+ UINT32 BypassFivrConfig : 1;
+ UINT32 RsvdBits2 : 30;
+} PCH_FIVR_CONFIG;
+
+#pragma pack (pop)
+
+#endif // _FIVR_CONFIG_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Gpio/GpioDevConfig.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Gpio/GpioDevConfig.h
new file mode 100644
index 0000000000..5652df0259
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Gpio/GpioDevConfig.h
@@ -0,0 +1,37 @@
+/** @file
+ GPIO device policy
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _GPIO_DEV_CONFIG_H_
+#define _GPIO_DEV_CONFIG_H_
+
+extern EFI_GUID gGpioDxeConfigGuid;
+
+#define GPIO_DXE_CONFIG_REVISION 1
+
+#pragma pack (push,1)
+
+/**
+ This structure contains the DXE policies which are related to GPIO device.
+
+ <b>Revision 1:</b>
+ - Inital version.
+**/
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Config Block Header
+ /**
+ If GPIO ACPI device is not used by OS it can be hidden. In such case
+ no other device exposed to the system can reference GPIO device in one
+ of its resources through GpioIo(..) or GpioInt(..) ACPI descriptors.
+ <b>0: Disable</b>; 1: Enable
+ **/
+ UINT32 HideGpioAcpiDevice : 1;
+ UINT32 RsvdBits : 31; ///< Reserved bits
+
+} GPIO_DXE_CONFIG;
+
+#pragma pack (pop)
+
+#endif // _GPIO_DEV_CONFIG_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Graphics/Gen12/GraphicsConfig.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Graphics/Gen12/GraphicsConfig.h
new file mode 100644
index 0000000000..c6a2f36612
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Graphics/Gen12/GraphicsConfig.h
@@ -0,0 +1,212 @@
+/** @file
+ Policy definition for Internal Graphics Config Block.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _GRAPHICS_CONFIG_H_
+#define _GRAPHICS_CONFIG_H_
+#pragma pack(push, 1)
+
+#define GRAPHICS_DXE_CONFIG_REVISION 2
+
+#define MAX_BCLM_ENTRIES 20
+
+
+//
+// DDI defines
+//
+typedef enum {
+ DdiDisable = 0x00,
+ DdiDdcEnable = 0x01,
+} DDI_DDC_TBT_VAL;
+
+typedef enum {
+ DdiHpdDisable = 0x00,
+ DdiHpdEnable = 0x01,
+} DDI_HPD_VAL;
+
+typedef enum {
+ DdiPortDisabled = 0x00,
+ DdiPortEdp = 0x01,
+ DdiPortMipiDsi = 0x02,
+} DDI_PORT_SETTINGS;
+
+/**
+ This structure configures the Native GPIOs for DDI port per VBT settings.
+**/
+typedef struct {
+ UINT8 DdiPortAConfig; /// The Configuration of DDI port A, this settings must match VBT's settings. DdiPortDisabled - No LFP is connected on DdiPortA, <b>DdiPortEdp - Set DdiPortA to eDP</b>, DdiPortMipiDsi - Set DdiPortA to MIPI DSI
+ UINT8 DdiPortBConfig; /// The Configuration of DDI port B, this settings must match VBT's settings. DdiPortDisabled - No LFP is connected on DdiPortB, <b>DdiPortEdp - Set DdiPortB to eDP</b>, DdiPortMipiDsi - Set DdiPortB to MIPI DSI
+ UINT8 DdiPortAHpd; /// The HPD setting of DDI Port A, this settings must match VBT's settings. <b>DdiHpdDisable - Disable HPD</b>, DdiHpdEnable - Enable HPD
+ UINT8 DdiPortBHpd; /// The HPD setting of DDI Port B, this settings must match VBT's settings. DdiHpdDisable - Disable HPD, <b>DdiHpdEnable - Enable HPD</b>
+ UINT8 DdiPortCHpd; /// The HPD setting of DDI Port C, this settings must match VBT's settings. <b>DdiHpdDisable - Disable HPD</b>, DdiHpdEnable - Enable HPD
+ UINT8 DdiPort1Hpd; /// The HPD setting of DDI Port 1, this settings must match VBT's settings. <b>DdiHpdDisable - Disable HPD</b>, DdiHpdEnable - Enable HPD
+ UINT8 DdiPort2Hpd; /// The HPD setting of DDI Port 2, this settings must match VBT's settings. <b>DdiHpdDisable - Disable HPD</b>, DdiHpdEnable - Enable HPD
+ UINT8 DdiPort3Hpd; /// The HPD setting of DDI Port 3, this settings must match VBT's settings. <b>DdiHpdDisable - Disable HPD</b>, DdiHpdEnable - Enable HPD
+ UINT8 DdiPort4Hpd; /// The HPD setting of DDI Port 4, this settings must match VBT's settings. <b>DdiHpdDisable - Disable HPD</b>, DdiHpdEnable - Enable HPD
+ UINT8 DdiPortADdc; /// The DDC setting of DDI Port A, this settings must match VBT's settings. <b>DdiDisable - Disable DDC</b>, DdiDdcEnable - Enable DDC
+ UINT8 DdiPortBDdc; /// The DDC setting of DDI Port B, this settings must match VBT's settings. DdiDisable - Disable DDC, <b>DdiDdcEnable - Enable DDC </b>
+ UINT8 DdiPortCDdc; /// The DDC setting of DDI Port C, this settings must match VBT's settings. <b>DdiDisable - Disable DDC</b>, DdiDdcEnable - Enable DDC
+ UINT8 DdiPort1Ddc; /// The DDC setting of DDI Port 1, this settings must match VBT's settings. <b>DdiDisable - Disable DDC</b>, DdiDdcEnable - Enable DDC
+ UINT8 DdiPort2Ddc; /// The DDC setting of DDI Port 2, this settings must match VBT's settings. <b>DdiDisable - Disable DDC</b>, DdiDdcEnable - Enable DDC
+ UINT8 DdiPort3Ddc; /// The DDC setting of DDI Port 3, this settings must match VBT's settings. <b>DdiDisable - Disable DDC</b>, DdiDdcEnable - Enable DDC
+ UINT8 DdiPort4Ddc; /// The DDC setting of DDI Port 4, this settings must match VBT's settings. <b>DdiDisable - Disable DDC</b>, DdiDdcEnable - Enable DDC
+} DDI_CONFIGURATION;
+
+/**
+ This Configuration block is to configure GT related PreMem data/variables.\n
+ <b>Revision 1</b>:
+ - Initial version.
+**/
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Block Header
+ /**
+ Offset 28
+ Selection of the primary display device: 0=iGFX, 1=PEG, 2=PCIe Graphics on PCH, <b>3=AUTO</b>, 4=Switchable Graphics\n
+ When AUTO mode selected, the priority of display devices is: PCIe Graphics on PCH > PEG > iGFX
+ **/
+ UINT8 PrimaryDisplay;
+ /**
+ Offset 29
+ Intel Gfx Support. It controls enabling/disabling iGfx device.
+ When AUTO mode selected, iGFX will be turned off when external graphics detected.
+ If FALSE, all other polices can be ignored.
+ <b>2 = AUTO</b>;
+ 0 = FALSE;
+ 1 = TRUE.
+ **/
+ UINT8 InternalGraphics;
+ /**
+ Offset 30
+ Pre-allocated memory for iGFX\n
+ 0 = 0MB,1 or 247 = 32MB,\n
+ 2 = 64MB,\n
+ 240 = 4MB, 241 = 8MB,\n
+ 242 = 12MB, 243 = 16MB,\n
+ 244 = 20MB, 245 = 24MB,\n
+ 246 = 28MB, 248 = 36MB,\n
+ 249 = 40MB, 250 = 44MB,\n
+ 251 = 48MB, 252 = 52MB,\n
+ 253 = 56MB,<b> 254 = 60MB</b>,\n
+ <b>Note: enlarging pre-allocated memory for iGFX may need to reduce MmioSize because of 4GB boundary limitation</b>
+ **/
+ UINT16 IgdDvmt50PreAlloc;
+ UINT8 PanelPowerEnable; ///< Offset 32 :<b>(Test)</b> Control for enabling/disabling VDD force bit (Required only for early enabling of eDP panel): 0=FALSE, <b>1=TRUE</b>
+ UINT8 ApertureSize; ///< Offset 33 :Graphics aperture size (256MB is the recommended size as per BWG) : 0=128MB, <b>1=256MB</b>, 3=512MB, 7=1024MB, 15=2048MB.
+ UINT8 GtPsmiSupport; ///< Offset 34 :PSMI support On/Off: <b>0=FALSE</b>, 1=TRUE
+ UINT8 PsmiRegionSize; ///< Offset 35 :Psmi region size: <b>0=32MB</b>, 1=288MB, 2=544MB, 3=800MB, 4=1056MB
+ UINT8 DismSize; ///< Offset 36 :DiSM Size for 2LM Sku: <b>0=0GB</b>, 1=1GB, 2=2GB, 3=3GB, 4=4GB, 5=5GB, 6=6GB, 7=7GB
+ UINT8 DfdRestoreEnable; ///< Offset 37 :(Deprecated) Display memory map programming for DFD Restore <b>0- Disable</b>, 1- Enable
+ UINT16 GttSize; ///< Offset 38 :Selection of iGFX GTT Memory size: 1=2MB, 2=4MB, <b>3=8MB</b>
+ /**
+ Offset 40
+ Temp Address of System Agent GTTMMADR: Default is <b>0xAF000000</b>
+ **/
+ UINT32 GttMmAdr;
+ UINT32 GmAdr; ///< Offset 44 Obsolete not to be used, use GmAdr64
+ DDI_CONFIGURATION DdiConfiguration; ///< Offset 48 DDI configuration, need to match with VBT settings.
+
+ UINT8 GtClosEnable; ///< Offset 50 Gt ClOS
+ UINT8 Rsvd0[7]; ///< Offset 51 Reserved for 4 bytes of alignment
+ /**
+ Offset 58
+ Temp Address of System Agent GMADR: Default is <b>0xB0000000</b>
+ **/
+ UINT64 GmAdr64;
+ UINT16 DeltaT12PowerCycleDelay; ///< Offset 66 Power Cycle Delay required for eDP as per VESA standard.0 - 0 ms, <b>0xFFFF - Auto calculate to max 500 ms<\b>
+ UINT8 DisplayAudioLink; ///< Offset 68 Enable/Disable Display Audio Links in Pre-OS.<b>0- Disable</b>, 1- Enable
+ UINT8 OemT12DelayOverride; ///< Offset 69 :Oem T12 Delay Override <b> Disable<\b>,Enable-Enable T12 Time.
+ UINT8 Rsvd2[4]; ///< Offset 70 Reserved for 4 bytes of alignment
+} GRAPHICS_PEI_PREMEM_CONFIG;
+
+/**
+ This configuration block is to configure IGD related variables used in PostMem PEI.
+ If Intel Gfx Device is not supported, all policies can be ignored.
+ <b>Revision 1</b>:
+ - Initial version.
+ <b>Revision 2</b>:
+ - Removed DfdRestoreEnable.
+ <b>Revision 3</b>:
+ - Removed DdiConfiguration.
+ <b>Revision 4</b>:
+ - Added new CdClock frequency
+ <b>Revision 5</b>:
+ - Added GT Chicket bits
+ <b>Revision 6</b>:
+ - Added LogoPixelHeight and LogoPixelWidth
+ <b>Revision 7</b>:
+ - Added SkipFspGop
+ <b>Revision 8</b>:
+ - Added VerticalResolution and HorizontalResolution
+
+**/
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Block Header
+ UINT8 RenderStandby; ///< Offset 28 :<b>(Test)</b> This field is used to enable or disable RC6 (Render Standby): 0=FALSE, <b>1=TRUE</b>
+ UINT8 PmSupport; ///< Offset 29 :<b>(Test)</b> Configure GT to use along with PM Support TRUE/FALSE: 0=FALSE, <b>1=TRUE</b>
+ /**
+ Offset 30
+ CdClock Frequency select\n
+ <b>0xFF = Auto. Max CdClock freq based on Reference Clk</b> \n
+ 0: 192 Mhz, 1: 307.2 Mhz, 2: 312 Mhz, 3: 324 Mhz, 4: 326.4 Mhz, 5: 552 Mhz, 6: 556.8 Mhz, 7: 648 Mhz, 8: 652.8 Mhz
+
+ **/
+ UINT16 CdClock;
+ UINT8 PeiGraphicsPeimInit; ///< Offset 32 : This policy is used to enable/disable Intel Gfx PEIM.<b>0- Disable</b>, 1- Enable
+ UINT8 CdynmaxClampEnable; ///< Offset 33 : This policy is used to enable/disable CDynmax Clamping Feature (CCF) <b>1- Enable</b>, 0- Disable
+ UINT16 GtFreqMax; ///< Offset 34 : <b>(Test)</b> Max GT frequency limited by user in multiples of 50MHz: Default value which indicates normal frequency is <b>0xFF</b>
+ UINT8 DisableTurboGt; ///< Offset 36 : This policy is used to enable/disable DisableTurboGt <b>0- Disable</b>, 1- Enable
+ UINT8 SkipCdClockInit; ///< Offset 37 : SKip full CD clock initialization. <b>0- Disable</b>, 1- Enable
+ UINT8 RC1pFreqEnable; ///< Offset 38 : This policy is used to enable/disable RC1p Frequency. <b>0- Disable</b>, 1- Enable
+ UINT8 PavpEnable; ///< Offset 39 :IGD PAVP TRUE/FALSE: 0=FALSE, <b>1=TRUE</b>
+ VOID* LogoPtr; ///< Offset 40 Address of Intel Gfx PEIM Logo to be displayed
+ UINT32 LogoSize; ///< Offset 44 Intel Gfx PEIM Logo Size
+ VOID* GraphicsConfigPtr; ///< Offset 48 Address of the Graphics Configuration Table
+ VOID* BltBufferAddress; ///< Offset 52 Address of Blt buffer for PEIM Logo use
+ UINT32 BltBufferSize; ///< Offset 56 The size for Blt Buffer, calculating by PixelWidth * PixelHeight * 4 bytes (the size of EFI_GRAPHICS_OUTPUT_BLT_PIXEL)
+ UINT8 ProgramGtChickenBits; ///< Offset 60 Program GT Chicket bits in GTTMMADR + 0xD00 BITS [3:1].
+ UINT8 SkipFspGop; ///< Offset 61 This policy is used to skip PEIM GOP in FSP.<b>0- Use FSP provided GOP driver</b>, 1- Skip FSP provided GOP driver
+ UINT8 Rsvd1[2]; ///< Offset 62 Reserved for 4 bytes alignment
+ UINT32 LogoPixelHeight; ///< Offset 64 Address of LogoPixelHeight for PEIM Logo use
+ UINT32 LogoPixelWidth; ///< Offset 68 Address of LogoPixelWidth for PEIM Logo use
+ UINT32 VerticalResolution; ///< Offset 72 Address of VerticalResolution for PEIM Logo use
+ UINT32 HorizontalResolution; ///< Offset 76 Address of HorizontalResolution for PEIM Logo use
+} GRAPHICS_PEI_CONFIG;
+
+/**
+ This configuration block is to configure IGD related variables used in DXE.
+ If Intel Gfx Device is not supported or disabled, all policies will be ignored.
+ The data elements should be initialized by a Platform Module.\n
+ <b>Revision 1</b>:
+ - Initial version.
+ <b>Revision 2</b>:
+ - Removed IgdDvmtMemSize.
+**/
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Offset 0-27: Config Block Header
+ UINT32 Size; ///< Offset 28 - 31: This field gives the size of the GOP VBT Data buffer
+ EFI_PHYSICAL_ADDRESS VbtAddress; ///< Offset 32 - 39: This field points to the GOP VBT data buffer
+ UINT8 PlatformConfig; ///< Offset 40: This field gives the Platform Configuration Information (0=Platform is S0ix Capable for ULT SKUs only, <b>1=Platform is not S0ix Capable</b>, 2=Force Platform is S0ix Capable for All SKUs)
+ UINT8 AlsEnable; ///< Offset 41: Ambient Light Sensor Enable: <b>0=Disable</b>, 2=Enable
+ UINT8 BacklightControlSupport; ///< Offset 42: Backlight Control Support: 0=PWM Inverted, <b>2=PWM Normal</b>
+ UINT8 IgdBootType; ///< Offset 43: IGD Boot Type CMOS option: <b>0=Default</b>, 0x01=CRT, 0x04=EFP, 0x08=LFP, 0x20=EFP3, 0x40=EFP2, 0x80=LFP2
+ UINT32 IuerStatusVal; ///< Offset 44 - 47: Offset 16 This field holds the current status of all the supported Ultrabook events (Intel(R) Ultrabook Event Status bits)
+ CHAR16 GopVersion[0x10]; ///< Offset 48 - 79:This field holds the GOP Driver Version. It is an Output Protocol and updated by the Silicon code
+ /**
+ Offset 80: IGD Panel Type CMOS option\n
+ <b>0=Default</b>, 1=640X480LVDS, 2=800X600LVDS, 3=1024X768LVDS, 4=1280X1024LVDS, 5=1400X1050LVDS1\n
+ 6=1400X1050LVDS2, 7=1600X1200LVDS, 8=1280X768LVDS, 9=1680X1050LVDS, 10=1920X1200LVDS, 13=1600X900LVDS\n
+ 14=1280X800LVDS, 15=1280X600LVDS, 16=2048X1536LVDS, 17=1366X768LVDS
+ **/
+ UINT8 IgdPanelType;
+ UINT8 IgdPanelScaling; ///< Offset 81: IGD Panel Scaling: <b>0=AUTO</b>, 1=OFF, 6=Force scaling
+ UINT8 IgdBlcConfig; ///< Offset 82: Backlight Control Support: 0=PWM Inverted, <b>2=PWM Normal</b>
+ UINT8 IgdDvmtMemSize; ///< Offset 83: @deprecated IGD DVMT Memory Size: 1=128MB, <b>2=256MB</b>, 3=MAX
+ UINT8 GfxTurboIMON; ///< Offset 84: IMON Current Value: 14=Minimal, <b>31=Maximum</b>
+ UINT8 Reserved[3]; ///< Offset 85: Reserved for DWORD alignment.
+ UINT16 BCLM[MAX_BCLM_ENTRIES]; ///< Offset 88: IGD Backlight Brightness Level Duty cycle Mapping Table.
+} GRAPHICS_DXE_CONFIG;
+#pragma pack(pop)
+
+#endif // _GRAPHICS_CONFIG_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/HostBridge/Ver1/HostBridgeConfig.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/HostBridge/Ver1/HostBridgeConfig.h
new file mode 100644
index 0000000000..11ef7b119c
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/HostBridge/Ver1/HostBridgeConfig.h
@@ -0,0 +1,58 @@
+/** @file
+ Configurations for HostBridge
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _HOST_BRIDGE_CONFIG_H_
+#define _HOST_BRIDGE_CONFIG_H_
+
+#include <ConfigBlock.h>
+
+
+extern EFI_GUID gHostBridgePeiPreMemConfigGuid;
+extern EFI_GUID gHostBridgePeiConfigGuid;
+
+#pragma pack (push,1)
+
+/**
+ This configuration block describes HostBridge settings in PreMem.\n
+ <b>Revision 1</b>:
+ - Initial version.
+**/
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Block Header
+ UINT32 MchBar; ///< Offset 28 Address of System Agent MCHBAR: <b>0xFEDC0000(TGL)/0xFEA80000(JSL)<b>
+ UINT32 DmiBar; ///< Offset 32 Address of System Agent DMIBAR: <b>0xFEDA0000</b>
+ UINT32 EpBar; ///< Offset 36 Address of System Agent EPBAR: <b>0xFEDA1000</b>
+ UINT32 GdxcBar; ///< Offset 40 Address of System Agent GDXCBAR: <b>0xFED84000</b>
+ UINT32 RegBar; ///< Offset 44 Address of System Agent REGBAR: <b>0xFB000000</b>
+ UINT32 EdramBar; ///< Offset 48 Address of System Agent EDRAMBAR: <b>0xFED80000</b>
+ /**
+ Offset 52 :
+ Size of reserved MMIO space for PCI devices\n
+ <b>0=AUTO</b>, 512=512MB, 768=768MB, 1024=1024MB, 1280=1280MB, 1536=1536MB, 1792=1792MB,
+ 2048=2048MB, 2304=2304MB, 2560=2560MB, 2816=2816MB, 3072=3072MB\n
+ When AUTO mode selected, the MMIO size will be calculated by required MMIO size from PCIe devices detected.
+ **/
+ UINT32 MmioSize;
+ UINT32 MmioSizeAdjustment; ///< Offset 56 Increase (given positive value) or Decrease (given negative value) the Reserved MMIO size when Dynamic Tolud/AUTO mode enabled (in MBs): <b>0=no adjustment</b>
+ UINT8 EnableAbove4GBMmio; ///< Offset 60 Enable/disable above 4GB MMIO resource support: 0=Disable, <b>1=Enable</b>
+ UINT8 Reserved[3]; ///< Offset 61 Reserved for future use.
+} HOST_BRIDGE_PREMEM_CONFIG;
+
+
+/**
+ This configuration block describes HostBridge settings in Post-Mem.\n
+ <b>Revision 1</b>:
+ - Initial version.
+**/
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Block Header
+ UINT8 SkipPamLock; ///< Offset 28 :To skip PAM register locking. @note It is still recommended to set PCI Config space B0: D0: F0: Offset 80h[0]=1 in platform code even Silicon code skipped this.\n <b>0=All PAM registers will be locked in Silicon code</b>, 1=Skip lock PAM registers in Silicon code.
+ UINT8 Reserved[3]; ///< Offset 29 Reserved for future use.
+} HOST_BRIDGE_PEI_CONFIG;
+
+#pragma pack (pop)
+
+#endif
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Itss/InterruptConfig.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Itss/InterruptConfig.h
new file mode 100644
index 0000000000..926c7ab6ab
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Itss/InterruptConfig.h
@@ -0,0 +1,38 @@
+/** @file
+ Interrupt policy
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _INTERRUPT_CONFIG_H_
+#define _INTERRUPT_CONFIG_H_
+
+extern EFI_GUID gInterruptConfigGuid;
+
+#pragma pack (push,1)
+
+//
+// --------------------- Interrupts Config ------------------------------
+//
+typedef enum {
+ PchNoInt, ///< No Interrupt Pin
+ PchIntA,
+ PchIntB,
+ PchIntC,
+ PchIntD
+} PCH_INT_PIN;
+
+///
+/// The PCH_DEVICE_INTERRUPT_CONFIG block describes interrupt pin, IRQ and interrupt mode for PCH device.
+///
+typedef struct {
+ UINT8 Device; ///< Device number
+ UINT8 Function; ///< Device function
+ UINT8 IntX; ///< Interrupt pin: INTA-INTD (see PCH_INT_PIN)
+ UINT8 Irq; ///< IRQ to be set for device.
+} PCH_DEVICE_INTERRUPT_CONFIG;
+
+
+#pragma pack (pop)
+
+#endif // _INTERRUPT_CONFIG_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Memory/Ver2/MemoryConfig.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Memory/Ver2/MemoryConfig.h
new file mode 100644
index 0000000000..2be85da5a8
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Memory/Ver2/MemoryConfig.h
@@ -0,0 +1,551 @@
+/** @file
+ Policy definition of Memory Config Block
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _MEMORY_CONFIG_H_
+#define _MEMORY_CONFIG_H_
+
+
+#pragma pack(push, 1)
+
+// MEMORY_CONFIGURATION_REVISION:
+// 3 - Adds DDR5 PDA Enumeration training
+// 4 - Adds LPDDR4 Command Mirroring
+// 5 - Adds PprEnableType
+// 6 - Removed IbeccParity
+// 7 - Adds MarginLimitCheck training within MEMORY_CONFIGURATION
+// 8 - Adds LpddrRttCa, LpddrRttWr
+// 9 - Adds VddqVoltage, VppVoltage
+// 10 - Changes PprEnableType to PprEnable
+// 11 - Changes DisableDimmChannel to DisableChannel
+// 12 - Added DIMMDFE
+// 13 - Added ExtendedBankHashing
+// 14 - Added IBECC Error Injection knobs: IbeccErrInjControl, IbeccErrInjAddress, IbeccErrInjMask, IbeccErrInjCount
+// 15 - Added DynamicMemoryBoost
+// 16 - Added ReuseAdlDdr5Board
+// 17 - Added RefreshWm; Deprecated RefreshPanicWm and RefreshHpWm
+// 18 - Added DebugValue
+// 19 - Added McRefreshRate; Deprecated McRefresh2X
+// 20 - Added RealtimeMemoryFrequency
+// 21 - Added PeriodicDcc and LpMode
+// 22 - Added Tx Dqs Dcc Training
+// 23 - Added tRFCpb, tRFC2, tRFC4, tRRD_L, tRRD_S, tWTR_L, tCCD_L, tWTR_S
+// 24 - Added EccErrInjAddress, EccErrInjMask, EccErrInjCount
+// 25 - Added FreqLimitMixedConfig, FirstDimmBitMask, UserBd
+// 26 - Added SagvSwitchFactorIA/GT/IO/Stall, SagvHeuristicsDownControl, SagvHeuristicsUpControl
+// 27 - Added DRAMDCA
+// 28 - Added FreqLimitMixedConfig_1R1R_8GB, FreqLimitMixedConfig_1R1R_16GB, FreqLimitMixedConfig_1R1R_8GB_16GB, FreqLimitMixedConfig_2R2R
+// 29 - Added LctCmdEyeWidth
+// 30 - Added FirstDimmBitMaskEcc
+// 31 - Added Lp5BankMode
+// 32 - Added WRDS
+// 33 - Added EARLYDIMMDFE for Early DIMM DFE Training
+// 34 - Added OverloadSAM
+#define MEMORY_CONFIGURATION_REVISION 34
+
+// MEMORY_CONFIG_NO_CRC_REVISION:
+// 3 - adds DDR5 SetMemoryPmicVoltage in SA_FUNCTION_CALLS
+#define MEMORY_CONFIG_NO_CRC_REVISION 3
+
+///
+/// MEMORY_CONFIGURATION interface definitions
+///
+#define MRC_MAX_RCOMP_TARGETS 5
+///
+/// Memory SubSystem Definitions
+///
+#define MEM_CFG_MAX_CONTROLLERS 2
+#define MEM_CFG_MAX_CHANNELS 4
+#define MEM_CFG_MAX_DIMMS 2
+#define MEM_CFG_NUM_BYTES_MAPPED 2
+#define MEM_CFG_MAX_SPD_SIZE 1024
+#define MEM_CFG_MAX_SOCKETS (MEM_CFG_MAX_CONTROLLERS * MEM_CFG_MAX_CHANNELS * MEM_CFG_MAX_DIMMS)
+#ifndef MEM_MAX_SAGV_POINTS
+#define MEM_MAX_SAGV_POINTS 4
+#endif
+#define MEM_MAX_IBECC_REGIONS 8
+
+///
+/// SA SPD profile selections.
+///
+typedef enum {
+ DEFAULT_SPD, ///< Standard DIMM profile select.
+ CUSTOM_PROFILE, ///< XMP enthusiast settings: User specifies various override values
+ XMP_PROFILE_1, ///< XMP enthusiast settings: XMP profile #1
+ XMP_PROFILE_2, ///< XMP enthusiast settings: XMP profile #2
+ XMP_PROFILE_3, ///< XMP enthusiast settings: XMP profile #3
+ XMP_USER_PROFILE_4, ///< XMP enthusiast settings: XMP user profile #4
+ XMP_USER_PROFILE_5, ///< XMP enthusiast settings: XMP user profile #5
+ SPDProfileMax = 0xFF ///< Ensures SA_SPD is UINT8
+} SA_SPD;
+
+///
+/// Define the boot modes used by the SPD read function.
+///
+typedef enum {
+ SpdCold, ///< Cold boot
+ SpdWarm, ///< Warm boot
+ SpdS3, ///< S3 resume
+ SpdFast, ///< Fast boot
+ SpdBootModeMax ///< Delimiter
+} SPD_BOOT_MODE;
+
+/**
+ SPD Data Buffer
+**/
+typedef struct {
+ UINT8 SpdData[MEM_CFG_MAX_CONTROLLERS][MEM_CFG_MAX_CHANNELS][MEM_CFG_MAX_DIMMS][MEM_CFG_MAX_SPD_SIZE]; ///< SpdData
+//Next Field Offset 2048
+} SPD_DATA_BUFFER;
+
+/**
+ DqDqs Mapping
+**/
+typedef struct {
+ UINT8 DqsMapCpu2Dram[MEM_CFG_MAX_CONTROLLERS][MEM_CFG_MAX_CHANNELS][MEM_CFG_NUM_BYTES_MAPPED]; ///< DqsMapCpu2Dram
+ UINT8 DqMapCpu2Dram[MEM_CFG_MAX_CONTROLLERS][MEM_CFG_MAX_CHANNELS][MEM_CFG_NUM_BYTES_MAPPED][8]; ///< DqMapCpu2Dram
+//Next Field Offset 16
+} SA_MEMORY_DQDQS_MAPPING;
+
+/**
+ Rcomp Policies
+**/
+typedef struct {
+ UINT16 RcompResistor; ///< Offset 0: Reference RCOMP resistors on motherboard ~ 100 ohms
+ UINT16 RcompTarget[MRC_MAX_RCOMP_TARGETS]; ///< Offset 1: RCOMP target values for DqOdt, DqDrv, CmdDrv, CtlDrv, ClkDrv
+//Next Field Offset 16
+} SA_MEMORY_RCOMP;
+
+/**
+ SPD Offset Table
+**/
+typedef struct {
+ UINT16 Start; ///< Offset 0
+ UINT16 End; ///< Offset 2
+ UINT8 BootMode; ///< Offset 4
+ UINT8 Reserved3[3]; ///< Offset 5 Reserved for future use
+} SPD_OFFSET_TABLE;
+
+///
+/// SA memory address decode.
+///
+typedef struct
+{
+ UINT8 Controller; ///< Offset 0 Zero based Controller number
+ UINT8 Channel; ///< Offset 1 Zero based Channel number
+ UINT8 Dimm; ///< Offset 2 Zero based DIMM number
+ UINT8 Rank; ///< Offset 3 Zero based Rank number
+ UINT8 BankGroup; ///< Offset 4 Zero based Bank Group number
+ UINT8 Bank; ///< Offset 5 Zero based Bank number
+ UINT16 Cas; ///< Offset 6 Zero based CAS number
+ UINT32 Ras; ///< Offset 8 Zero based RAS number
+} SA_ADDRESS_DECODE;
+
+typedef UINT8 (EFIAPI * SA_IO_READ_8) (UINTN IoAddress); ///< CPU I/O port 8-bit read.
+typedef UINT16 (EFIAPI * SA_IO_READ_16) (UINTN IoAddress); ///< CPU I/O port 16-bit read.
+typedef UINT32 (EFIAPI * SA_IO_READ_32) (UINTN IoAddress); ///< CPU I/O port 32-bit read.
+typedef UINT8 (EFIAPI * SA_IO_WRITE_8) (UINTN IoAddress, UINT8 Value); ///< CPU I/O port 8-bit write.
+typedef UINT16 (EFIAPI * SA_IO_WRITE_16) (UINTN IoAddress, UINT16 Value); ///< CPU I/O port 16-bit write.
+typedef UINT32 (EFIAPI * SA_IO_WRITE_32) (UINTN IoAddress, UINT32 Value); ///< CPU I/O port 32-bit write.
+typedef UINT8 (EFIAPI * SA_MMIO_READ_8) (UINTN Address); ///< Memory Mapped I/O port 8-bit read.
+typedef UINT16 (EFIAPI * SA_MMIO_READ_16) (UINTN Address); ///< Memory Mapped I/O port 16-bit read.
+typedef UINT32 (EFIAPI * SA_MMIO_READ_32) (UINTN Address); ///< Memory Mapped I/O port 32-bit read.
+typedef UINT64 (EFIAPI * SA_MMIO_READ_64) (UINTN Address); ///< Memory Mapped I/O port 64-bit read.
+typedef UINT8 (EFIAPI * SA_MMIO_WRITE_8) (UINTN Address, UINT8 Value); ///< Memory Mapped I/O port 8-bit write.
+typedef UINT16 (EFIAPI * SA_MMIO_WRITE_16) (UINTN Address, UINT16 Value); ///< Memory Mapped I/O port 16-bit write.
+typedef UINT32 (EFIAPI * SA_MMIO_WRITE_32) (UINTN Address, UINT32 Value); ///< Memory Mapped I/O port 32-bit write.
+typedef UINT64 (EFIAPI * SA_MMIO_WRITE_64) (UINTN Address, UINT64 Value); ///< Memory Mapped I/O port 64-bit write.
+typedef UINT8 (EFIAPI * SA_SMBUS_READ_8) (UINTN Address, RETURN_STATUS *Status); ///< Smbus 8-bit read.
+typedef UINT16 (EFIAPI * SA_SMBUS_READ_16) (UINTN Address, RETURN_STATUS *Status); ///< Smbus 16-bit read.
+typedef UINT8 (EFIAPI * SA_SMBUS_WRITE_8) (UINTN Address, UINT8 Value, RETURN_STATUS *Status); ///< Smbus 8-bit write.
+typedef UINT16 (EFIAPI * SA_SMBUS_WRITE_16) (UINTN Address, UINT16 Value, RETURN_STATUS *Status); ///< Smbus 16-bit write.
+typedef UINT32 (EFIAPI * SA_GET_PCI_DEVICE_ADDRESS) (UINT8 Bus, UINT8 Device, UINT8 Function, UINT8 Offset); ///< Get PCI device address.
+typedef UINT32 (EFIAPI * SA_GET_PCIE_DEVICE_ADDRESS) (UINT8 Bus, UINT8 Device, UINT8 Function, UINT8 Offset); ///< Get PCI express device address.
+typedef VOID (EFIAPI * SA_GET_RTC_TIME) (UINT8 *Second, UINT8 *Minute, UINT8 *Hour, UINT8 *Day, UINT8 *Month, UINT16 *Year); ///< Get the current time value.
+typedef UINT64 (EFIAPI * SA_GET_CPU_TIME) (VOID); ///< The current CPU time in milliseconds.
+typedef VOID * (EFIAPI * SA_MEMORY_COPY) (VOID *Destination, CONST VOID *Source, UINTN NumBytes); ///< Perform byte copy operation.
+typedef VOID * (EFIAPI * SA_MEMORY_SET_BYTE) (VOID *Buffer, UINTN NumBytes, UINT8 Value); ///< Perform byte initialization operation.
+typedef VOID * (EFIAPI * SA_MEMORY_SET_WORD) (VOID *Buffer, UINTN NumWords, UINT16 Value); ///< Perform word initialization operation.
+typedef VOID * (EFIAPI * SA_MEMORY_SET_DWORD) (VOID *Buffer, UINTN NumDwords, UINT32 Value); ///< Perform dword initialization operation.
+typedef UINT64 (EFIAPI * SA_LEFT_SHIFT_64) (UINT64 Data, UINTN NumBits); ///< Left shift the 64-bit data value by specified number of bits.
+typedef UINT64 (EFIAPI * SA_RIGHT_SHIFT_64) (UINT64 Data, UINTN NumBits); ///< Right shift the 64-bit data value by specified number of bits.
+typedef UINT64 (EFIAPI * SA_MULT_U64_U32) (UINT64 Multiplicand, UINT32 Multiplier); ///< Multiply a 64-bit data value by a 32-bit data value.
+typedef UINT64 (EFIAPI * SA_DIV_U64_U64) (UINT64 Dividend, UINT64 Divisor, UINT64 *Remainder); ///< Divide a 64-bit data value by a 64-bit data value.
+typedef BOOLEAN (EFIAPI * SA_GET_SPD_DATA) (SPD_BOOT_MODE BootMode, UINT8 SpdAddress, UINT8 *Buffer, UINT8 *Ddr3Table, UINT32 Ddr3TableSize, UINT8 *Ddr4Table, UINT32 Ddr4TableSize, UINT8 *LpddrTable, UINT32 LpddrTableSize); ///< Read the SPD data over the SMBus, at the given SmBus SPD address and copy the data to the data structure.
+typedef UINT8 (EFIAPI * SA_GET_MC_ADDRESS_DECODE) (UINT64 Address, SA_ADDRESS_DECODE *DramAddress);
+typedef UINT8 (EFIAPI * SA_GET_MC_ADDRESS_ENCODE) (SA_ADDRESS_DECODE *DramAddress, UINT64 Address);
+typedef BOOLEAN (EFIAPI * SA_GET_RANDOM_NUMBER) (UINT32 *Rand); ///< Get the next random 32-bit number.
+typedef EFI_STATUS (EFIAPI * SA_CPU_MAILBOX_READ) (UINT32 Type, UINT32 Command, UINT32 *Value, UINT32 *Status); ///< Perform a CPU mailbox read.
+typedef EFI_STATUS (EFIAPI * SA_CPU_MAILBOX_WRITE) (UINT32 Type, UINT32 Command, UINT32 Value, UINT32 *Status); ///< Perform a CPU mailbox write.
+typedef UINT32 (EFIAPI * SA_GET_MEMORY_VDD) (VOID *GlobalData, UINT32 DefaultVdd); ///< Get the current memory voltage (VDD).
+typedef UINT32 (EFIAPI * SA_SET_MEMORY_VDD) (VOID *GlobalData, UINT32 DefaultVdd, UINT32 Value); ///< Set the memory voltage (VDD) to the given value.
+typedef UINT32 (EFIAPI * SA_SET_MEMORY_PMIC_VOLTAGE) (VOID *GlobalData, UINT8 SpdAddress, UINT32 Vdd, UINT32 Vddq, UINT32 Vpp); ///< Set DDR5 memory voltages (VDD, VDDQ, VPP) to the given values.
+typedef UINT32 (EFIAPI * SA_CHECKPOINT) (VOID *GlobalData, UINT32 CheckPoint, VOID *Scratch); ///< Check point that is called at various points in the MRC.
+typedef VOID (EFIAPI * SA_DEBUG_HOOK) (VOID *GlobalData, UINT16 DisplayDebugNumber); ///< Typically used to display to the I/O port 80h.
+typedef UINT8 (EFIAPI * SA_CHANNEL_EXIST) (VOID *Outputs, UINT8 Channel); ///< Returns whether Channel is or is not present.
+typedef INT32 (EFIAPI * SA_PRINTF) (VOID *Debug, UINT32 Level, char *Format, ...); ///< Print to output stream/device.
+typedef VOID (EFIAPI * SA_DEBUG_PRINT) (VOID *String); ///< Output a string to the debug stream/device.
+typedef UINT32 (EFIAPI * SA_CHANGE_MARGIN) (VOID *GlobalData, UINT8 Param, INT32 Value0, INT32 Value1, UINT8 EnMultiCast, UINT8 Channel, UINT8 RankIn, UINT8 Byte, UINT8 BitIn, UINT8 UpdateMrcData, UINT8 SkipWait, UINT32 RegFileParam); ///< Change the margin.
+typedef UINT8 (EFIAPI * SA_SIGN_EXTEND) (UINT8 Value, UINT8 OldMsb, UINT8 NewMsb); ///< Sign extends OldMSB to NewMSB Bits (Eg: Bit 6 to Bit 7).
+typedef VOID (EFIAPI * SA_SHIFT_PI_COMMAND_TRAIN) (VOID *GlobalData, UINT8 Channel, UINT8 Iteration, UINT8 RankMask, UINT8 GroupMask, INT32 NewValue, UINT8 UpdateHost); ///< Move CMD/CTL/CLK/CKE PIs during training.
+typedef VOID (EFIAPI * SA_UPDATE_VREF) (VOID *GlobalData, UINT8 Channel, UINT8 RankMask, UINT16 DeviceMask, UINT8 VrefType, INT32 Offset, BOOLEAN UpdateMrcData, BOOLEAN PDAmode, BOOLEAN SkipWait); ///< Update the Vref value and wait until it is stable.
+typedef UINT8 (EFIAPI * SA_GET_RTC_CMOS) (UINT8 Location); ///< Get the current value of the specified RTC CMOS location.
+typedef UINT64 (EFIAPI * SA_MSR_READ_64) (UINT32 Location); ///< Get the current value of the specified MSR location.
+typedef UINT64 (EFIAPI * SA_MSR_WRITE_64) (UINT32 Location, UINT64 Data); ///< Set the current value of the specified MSR location.
+typedef VOID (EFIAPI * SA_MRC_RETURN_FROM_SMC) (VOID *GlobalData, UINT32 MrcStatus); ///< Hook function after returning from MrcStartMemoryConfiguration()
+typedef VOID (EFIAPI * SA_MRC_DRAM_RESET) (UINT32 PciEBaseAddress, UINT32 ResetValue); ///< Assert or deassert DRAM_RESET# pin; this is used in JEDEC Reset.
+typedef VOID (EFIAPI * SA_DELAY_NS) (VOID *GlobalData, UINT32 DelayNs); ///< Delay (stall) for the given amount of nanoseconds.
+typedef VOID (EFIAPI * SA_SET_LOCK_PRMRR) (UINT64 PrmrrBaseAddress, UINT32 PrmrrSize);
+
+
+///
+/// Function calls into the SA.
+///
+typedef struct {
+ SA_IO_READ_8 IoRead8; ///< Offset 0: - CPU I/O port 8-bit read.
+ SA_IO_READ_16 IoRead16; ///< Offset 4: - CPU I/O port 16-bit read.
+ SA_IO_READ_32 IoRead32; ///< Offset 8: - CPU I/O port 32-bit read.
+ SA_IO_WRITE_8 IoWrite8; ///< Offset 12: - CPU I/O port 8-bit write.
+ SA_IO_WRITE_16 IoWrite16; ///< Offset 16: - CPU I/O port 16-bit write.
+ SA_IO_WRITE_32 IoWrite32; ///< Offset 20: - CPU I/O port 32-bit write.
+ SA_MMIO_READ_8 MmioRead8; ///< Offset 24: - Memory Mapped I/O port 8-bit read.
+ SA_MMIO_READ_16 MmioRead16; ///< Offset 28: - Memory Mapped I/O port 16-bit read.
+ SA_MMIO_READ_32 MmioRead32; ///< Offset 32: - Memory Mapped I/O port 32-bit read.
+ SA_MMIO_READ_64 MmioRead64; ///< Offset 36: - Memory Mapped I/O port 64-bit read.
+ SA_MMIO_WRITE_8 MmioWrite8; ///< Offset 40: - Memory Mapped I/O port 8-bit write.
+ SA_MMIO_WRITE_16 MmioWrite16; ///< Offset 44: - Memory Mapped I/O port 16-bit write.
+ SA_MMIO_WRITE_32 MmioWrite32; ///< Offset 48: - Memory Mapped I/O port 32-bit write.
+ SA_MMIO_WRITE_64 MmioWrite64; ///< Offset 52: - Memory Mapped I/O port 64-bit write.
+ SA_SMBUS_READ_8 SmbusRead8; ///< Offset 56: - Smbus 8-bit read.
+ SA_SMBUS_READ_16 SmbusRead16; ///< Offset 60: - Smbus 16-bit read.
+ SA_SMBUS_WRITE_8 SmbusWrite8; ///< Offset 64: - Smbus 8-bit write.
+ SA_SMBUS_WRITE_16 SmbusWrite16; ///< Offset 68: - Smbus 16-bit write.
+ SA_GET_PCI_DEVICE_ADDRESS GetPciDeviceAddress; ///< Offset 72: - Get PCI device address.
+ SA_GET_PCIE_DEVICE_ADDRESS GetPcieDeviceAddress; ///< Offset 76: - Get PCI express device address.
+ SA_GET_RTC_TIME GetRtcTime; ///< Offset 80: - Get the current time value.
+ SA_GET_CPU_TIME GetCpuTime; ///< Offset 84: - The current CPU time in milliseconds.
+ SA_MEMORY_COPY CopyMem; ///< Offset 88: - Perform byte copy operation.
+ SA_MEMORY_SET_BYTE SetMem; ///< Offset 92: - Perform byte initialization operation.
+ SA_MEMORY_SET_WORD SetMemWord; ///< Offset 96: - Perform word initialization operation.
+ SA_MEMORY_SET_DWORD SetMemDword; ///< Offset 100: - Perform dword initialization operation.
+ SA_LEFT_SHIFT_64 LeftShift64; ///< Offset 104: - Left shift the 64-bit data value by specified number of bits.
+ SA_RIGHT_SHIFT_64 RightShift64; ///< Offset 108: - Right shift the 64-bit data value by specified number of bits.
+ SA_MULT_U64_U32 MultU64x32; ///< Offset 112: - Multiply a 64-bit data value by a 32-bit data value.
+ SA_DIV_U64_U64 DivU64x64; ///< Offset 116: - Divide a 64-bit data value by a 64-bit data value.
+ SA_GET_SPD_DATA GetSpdData; ///< Offset 120: - Read the SPD data over the SMBus, at the given SmBus SPD address and copy the data to the data structure.
+ SA_GET_RANDOM_NUMBER GetRandomNumber; ///< Offset 124: - Get the next random 32-bit number.
+ SA_CPU_MAILBOX_READ CpuMailboxRead; ///< Offset 128: - Perform a CPU mailbox read.
+ SA_CPU_MAILBOX_WRITE CpuMailboxWrite; ///< Offset 132: - Perform a CPU mailbox write.
+ SA_GET_MEMORY_VDD GetMemoryVdd; ///< Offset 136: - Get the current memory voltage (VDD).
+ SA_SET_MEMORY_VDD SetMemoryVdd; ///< Offset 140: - Set the memory voltage (VDD) to the given value.
+ SA_CHECKPOINT CheckPoint; ///< Offset 144: - Check point that is called at various points in the MRC.
+ SA_DEBUG_HOOK DebugHook; ///< Offset 148: - Typically used to display to the I/O port 80h.
+ SA_DEBUG_PRINT DebugPrint; ///< Offset 152: - Output a string to the debug stream/device.
+ SA_GET_RTC_CMOS GetRtcCmos; ///< Offset 156: - Get the current value of the specified RTC CMOS location.
+ SA_MSR_READ_64 ReadMsr64; ///< Offset 160: - Get the current value of the specified MSR location.
+ SA_MSR_WRITE_64 WriteMsr64; ///< Offset 164 - Set the current value of the specified MSR location.
+ SA_MRC_RETURN_FROM_SMC MrcReturnFromSmc; ///< Offset 168 - Hook function after returning from MrcStartMemoryConfiguration()
+ SA_MRC_DRAM_RESET MrcDramReset; ///< Offset 172 - Assert or deassert DRAM_RESET# pin; this is used in JEDEC Reset.
+ SA_DELAY_NS MrcDelayNs; ///< Offset 176 - Delay (stall) for the given amount of nanoseconds.
+ SA_SET_MEMORY_PMIC_VOLTAGE SetMemoryPmicVoltage; ///< Offset 180: - Set the memory voltage (VDD/VDDQ/VPP) by PMIC for DDR5.
+} SA_FUNCTION_CALLS;
+
+///
+/// Function calls into the MRC.
+///
+typedef struct {
+ SA_CHANNEL_EXIST MrcChannelExist; ///< Offset 0: - Returns whether Channel is or is not present.
+ SA_PRINTF MrcPrintf; ///< Offset 4: - Print to output stream/device.
+ SA_CHANGE_MARGIN MrcChangeMargin; ///< Offset 8: - Change the margin.
+ SA_SIGN_EXTEND MrcSignExtend; ///< Offset 12: - Sign extends OldMSB to NewMSB Bits (Eg: Bit 6 to Bit 7).
+ SA_SHIFT_PI_COMMAND_TRAIN ShiftPiCommandTrain; ///< Offset 16: - Move CMD/CTL/CLK/CKE PIs during training.
+ SA_UPDATE_VREF MrcUpdateVref; ///< Offset 20: - Update the Vref value and wait until it is stable.
+} SA_MEMORY_FUNCTIONS;
+
+/**
+ Memory Configuration
+ The contents of this structure are CRC'd by the MRC for option change detection.
+ This structure is copied en mass to the MrcInput structure. If you add fields here, you must update the MrcInput structure.
+ Revision history is at the top of this file
+**/
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Block Header
+ UINT16 Size; ///< Offset 28 The size of this structure, in bytes. Must be the first entry in this structure.
+ UINT8 HobBufferSize; ///< Offset 30 Size of HOB buffer for MRC
+
+ UINT8 SpdProfileSelected; ///< Offset 31 SPD XMP profile selection - for XMP supported DIMM: <b>0=Default DIMM profile</b>, 1=Custom Profile, 2=XMP Profile 1, 3=XMP Profile 2, 4=XMP Profile 3, 5=XMP User Profile 4, 6=XMP User Profile 5
+
+ // The following parameters are used only when SpdProfileSelected is User Defined (CUSTOM_PROFILE)
+ UINT16 tCL; ///< Offset 32 User defined Memory Timing tCL value, valid when SpdProfileSelected is CUSTOM_PROFILE: <b>0=AUTO</b>, 31=Maximum.
+ UINT16 tRCDtRP; ///< Offset 34 User defined Memory Timing tRCD value (same as tRP), valid when SpdProfileSelected is CUSTOM_PROFILE: <b>0=AUTO</b>, 63=Maximum
+ UINT16 tRAS; ///< Offset 36 User defined Memory Timing tRAS value, valid when SpdProfileSelected is CUSTOM_PROFILE: <b>0=AUTO</b>, 64=Maximum.
+ UINT16 tWR; ///< Offset 38 User defined Memory Timing tWR value, valid when SpdProfileSelected is CUSTOM_PROFILE: <b>0=AUTO</b>, legal values: 5, 6, 7, 8, 10, 12, 14, 16, 18, 20, 24.
+ UINT16 tRFC; ///< Offset 40 User defined Memory Timing tRFC value, valid when SpdProfileSelected is CUSTOM_PROFILE: <b>0=AUTO</b>, 1023=Maximum.
+ UINT16 tRRD; ///< Offset 42 User defined Memory Timing tRRD value, valid when SpdProfileSelected is CUSTOM_PROFILE: <b>0=AUTO</b>, 15=Maximum.
+ UINT16 tWTR; ///< Offset 44 User defined Memory Timing tWTR value, valid when SpdProfileSelected is CUSTOM_PROFILE: <b>0=AUTO</b>, 28=Maximum.
+ UINT16 tRTP; ///< Offset 46 User defined Memory Timing tRTP value, valid when SpdProfileSelected is CUSTOM_PROFILE: <b>0=AUTO</b>, 15=Maximum. DDR4 legal values: 5, 6, 7, 8, 9, 10, 12
+ UINT16 tFAW; ///< Offset 48 User defined Memory Timing tFAW value, valid when SpdProfileSelected is CUSTOM_PROFILE: <b>0=AUTO</b>, 63=Maximum.
+ UINT16 tCWL; ///< Offset 50 User defined Memory Timing tCWL value, valid when SpdProfileSelected is CUSTOM_PROFILE: <b>0=AUTO</b>, 20=Maximum.
+ UINT16 tREFI; ///< Offset 52 User defined Memory Timing tREFI value, valid when SpdProfileSelected is CUSTOM_PROFILE: <b>0=AUTO</b>, 65535=Maximum.
+ UINT16 PciIndex; ///< Offset 54 Pci index register address: <b>0xCF8=Default</b>
+ UINT16 PciData; ///< Offset 56 Pci data register address: <b>0xCFC=Default</b>
+ UINT16 VddVoltage; ///< Offset 58 DRAM voltage (Vdd) in millivolts: <b>0=Platform Default (no override)</b>, 1200=1.2V, 1350=1.35V etc.
+ UINT16 Idd3n; ///< Offset 60 EPG Active standby current (Idd3N) in milliamps from DIMM datasheet.
+ UINT16 Idd3p; ///< Offset 62 EPG Active power-down current (Idd3P) in milliamps from DIMM datasheet.
+
+ UINT32 EccSupport:1; ///< Offset 64 Bit 0 - DIMM Ecc Support option - for Desktop only: 0=Disable, <b>1=Enable</b>
+ UINT32 MrcSafeConfig:1; ///< Bit 1 - MRC Safe Mode: <b>0=Disable</b>, 1=Enable
+ UINT32 RemapEnable:1; ///< Bit 2 - This option is used to control whether to enable/disable memory remap above 4GB: 0=Disable, <b>1=Enable</b>.
+ UINT32 ScramblerSupport:1; ///< Bit 3 - Memory scrambler support: 0=Disable, <b>1=Enable</b>
+ UINT32 Vc1ReadMeter:1; ///< Bit 4 - VC1 Read Metering Enable: 0=Disable, <b>1=Enable</b>
+ UINT32 ForceSingleSubchannel:1; ///< Bit 5 - TRUE means use SubChannel0 only (for LPDDR4): <b>0=Disable</b>, 1=Enable
+ UINT32 SimicsFlag:1; ///< Bit 6 - Option to Enable SIMICS: 0=Disable, <b>1=Enable</b>
+ UINT32 Ddr4DdpSharedClock:1; ///< Bit 7 - Select if CLK0 is shared between Rank0 and Rank1 in DDR4 DDP package. <b>0=Not shared</b>, 1=Shared
+ UINT32 SharedZqPin:1; ///< Bit 8 - Select if the ZQ resistor is shared between Ranks in DDR4/LPDDR4 DRAM Packages <b>0=Not Shared</b>, 1=Shared
+ UINT32 LpDqsOscEn:1; ///< Bit 9 - LPDDR Write DQ/DQS Retraining: 0=Disable, <b>1=Enable</b>
+ UINT32 RmtPerTask:1; ///< Bit 10 - Rank Margin Tool Per Task. <b>0 = Disabled</b>, 1 = Enabled
+ UINT32 TrainTrace:1; ///< Bit 11 - Trained state tracing debug. <b>0 = Disabled</b>, 1 = Enabled
+ UINT32 SafeMode:1; ///< Bit 12 - Define if safe mode is enabled for MC/IO
+ UINT32 MsHashEnable:1; ///< Bit 13 - Controller Hash Enable: 0=Disable, <b>1=Enable</b>
+ UINT32 DisPgCloseIdleTimeout:1; ///< Bit 14 - Disable Page Close Idle Timeout: 0=Enable, <b>1=Disable</b>
+ UINT32 Ibecc:1; ///< Bit 15 - In-band ECC: <b>0=Disable</b>, 1=Enable
+ UINT32 IbeccOperationMode:2; ///< Bits 16:17 - In-band ECC Operation Mode: 0=Functional Mode protects requests based on the address range, 1=Makes all requests non protected and ignore range checks, <b>2=Makes all requests protected and ignore range checks</b>
+ UINT32 ChHashOverride:1; ///< Bit 18 - Select if Channel Hash setting values will be taken from input parameters or automatically taken from POR values depending on DRAM type detected.
+ UINT32 EccDftEn:1; ///< Bit 19 - ECC DFT support option
+ UINT32 Write0:1; ///< Bit 20 - Write0 feature (LP5/DDR5): 0=Disable, <b>1=Enable</b>
+ UINT32 ReuseAdlSDdr5Board:1; ///< Bit 21 - Indicate whether adl ddr5 board is reused.
+ UINT32 PeriodicDcc:1; ///< Bit 22 - Periodic DCC: <b>0=Disable</b>, 1=Enable
+ UINT32 LpMode:2; ///< Bit 23:24 - LPMode: <b>0=Auto</b>, 1=Enabled, 2=Disabled, 3=Reserved
+ UINT32 RsvdO64B25to31:7; ///< Bits 25:31 reserved
+ UINT8 DisableChannel[MEM_CFG_MAX_CONTROLLERS][MEM_CFG_MAX_CHANNELS]; ///< Offset 68-75
+ UINT8 Ratio; ///< Offset 76 DDR Frequency ratio, to multiply by 133 or 100 MHz depending on RefClk. <b>0 = Auto</b>
+ UINT8 ProbelessTrace; ///< Offset 77 Probeless Trace: <b>0=Disabled</b>, <b>1=Enabled</b>
+ /**
+ Channel Hash Enable.\n
+ NOTE: BIT7 will interleave the channels at a 2 cache-line granularity, BIT8 at 4 and BIT9 at 8\n
+ 0=BIT6, <B>1=BIT7</B>, 2=BIT8, 3=BIT9
+ **/
+ UINT8 ChHashInterleaveBit; ///< Offset 78 Option to select interleave Address bit. Valid values are 0 - 3 for BITS 6 - 9 (Valid values for BDW are 0-7 for BITS 6 - 13)
+ UINT8 SmramMask; ///< Offset 79 Reserved memory ranges for SMRAM
+ UINT32 BClkFrequency; ///< Offset 80 Base reference clock value, in Hertz: <b>100000000 = 100Hz</b>, 125000000=125Hz, 167000000=167Hz, 250000000=250Hz
+
+ /// Training Algorithms 1 Offset 84
+ UINT32 ECT:1; ///< Bit 0 - Enable/Disable Early Command Training. Note it is not recommended to change this setting from the default value: <b>0=Disable</b>, 1=Enable.
+ UINT32 SOT:1; ///< Bit 1 - Enable/Disable Sense Amp Offset Training. Note it is not recommended to change this setting from the default value: 0=Disable, <b>1=Enable</b>.
+ UINT32 ERDMPRTC2D:1; ///< Bit 2 - Enable/Disable Early ReadMPR Timing Centering 2D. Note it is not recommended to change this setting from the default value: 0=Disable, <b>1=Enable</b>.
+ UINT32 RDMPRT:1; ///< Bit 3 - Enable/Disable Read MPR Training. Note it is not recommended to change this setting from the default value: 0=Disable, <b>1=Enable</b>.
+ UINT32 RCVET:1; ///< Bit 4 - Enable/Disable Receive Enable Training. Note it is not recommended to change this setting from the default value: 0=Disable, <b>1=Enable</b>.
+ UINT32 JWRL:1; ///< Bit 5 - Enable/Disable JEDEC Write Leveling Training. Note it is not recommended to change this setting from the default value: 0=Disable, <b>1=Enable</b>.
+ UINT32 EWRTC2D:1; ///< Bit 6 - Enable/Disable Early Write Time Centering 2D Training. Note it is not recommended to change this setting from the default value: 0=Disable, <b>1=Enable</b>.
+ UINT32 ERDTC2D:1; ///< Bit 7 - Enable/Disable Early Read Time Centering 2D Training. Note it is not recommended to change this setting from the default value: 0=Disable, <b>1=Enable</b>.
+ UINT32 WRTC1D:1; ///< Bit 8 - Enable/Disable 1D Write Timing Centering Training. Note it is not recommended to change this setting from the default value: 0=Disable, <b>1=Enable</b>.
+ UINT32 WRVC1D:1; ///< Bit 9 - Enable/Disable 1D Write Voltage Centering Training. Note it is not recommended to change this setting from the default value: 0=Disable, <b>1=Enable</b>.
+ UINT32 RDTC1D:1; ///< Bit 10 - Enable/Disable 1D Read Timing Centering Training. Note it is not recommended to change this setting from the default value: 0=Disable, <b>1=Enable</b>.
+ UINT32 DIMMODTT:1; ///< Bit 11 - Enable/Disable DIMM ODT Training. Note it is not recommended to change this setting from the default value: <b>0=Disable</b>, 1=Enable.
+ UINT32 DIMMRONT:1; ///< Bit 12 - Enable/Disable DIMM RON training. Note it is not recommended to change this setting from the default value: 0=Disable, <b>1=Enable</b>.
+ UINT32 WRDSEQT:1; ///< Bit 13 - Enable/Disable Write Drive Strength / Equalization Training 2D. Note it is not recommended to change this setting from the default value: <b>0=Disable</b>, 1=Enable.
+ UINT32 WRSRT:1; ///< Bit 14 - Enable/Disable Write Slew Rate traning. Note it is not recommended to change this setting from the default value: 0=Disable, <b>1=Enable.</b>
+ UINT32 RDODTT:1; ///< Bit 15 - Enable/Disable Read ODT Training. Note it is not recommended to change this setting from the default value: <b>0=Disable</b>, 1=Enable.
+ UINT32 RDEQT:1; ///< Bit 16 - Enable/Disable Read Equalization Training. Note it is not recommended to change this setting from the default value: <b>0=Disable</b>, 1=Enable.
+ UINT32 RDAPT:1; ///< Bit 17 - Enable/Disable Read Amplifier Power Training. Note it is not recommended to change this setting from the default value: <b>0=Disable</b>, 1=Enable.
+ UINT32 WRTC2D:1; ///< Bit 18 - Enable/Disable 2D Write Timing Centering Training. Note it is not recommended to change this setting from the default value: 0=Disable, <b>1=Enable</b>.
+ UINT32 RDTC2D:1; ///< Bit 19 - Enable/Disable 2D Read Timing Centering Training. Note it is not recommended to change this setting from the default value: 0=Disable, <b>1=Enable</b>.
+ UINT32 WRVC2D:1; ///< Bit 20 - Enable/Disable 2D Write Voltage Centering Training. Note it is not recommended to change this setting from the default value: 0=Disable, <b>1=Enable</b>.
+ UINT32 RDVC2D:1; ///< Bit 21 - Enable/Disable 2D Read Voltage Centering Training. Note it is not recommended to change this setting from the default value: 0=Disable, <b>1=Enable</b>.
+ UINT32 CMDVC:1; ///< Bit 22 - Enable/Disable Command Vref Centering Training. Note it is not recommended to change this setting from the default value 0=Disable, <b>1=Enable</b>.
+ UINT32 LCT:1; ///< Bit 23 - Enable/Disable Late Command Training. Note it is not recommended to change this setting from the default value: 0=Disable, <b>1=Enable</b>.
+ UINT32 RTL:1; ///< Bit 24 - Enable/Disable Round Trip Latency function. Note it is not recommended to change this setting from the default value: 0=Disable, <b>1=Enable</b>.
+ UINT32 TAT:1; ///< Bit 25 - Enable/Disable Turn Around Time function. Note it is not recommended to change this setting from the default value: <b>0=Disable</b>, 1=Enable.
+ UINT32 RMT:1; ///< Bit 26 - Enable/Disable Rank Margin Tool function: <b>0=Disable</b>, 1=Enable.
+ UINT32 MEMTST:1; ///< Bit 27 - Enable/Disable Memory Test function: <b>0=Disable</b>, 1=Enable.
+ UINT32 ALIASCHK:1; ///< Bit 28 - Enable/Disable DIMM SPD Alias Check: 0=Disable, <b>1=Enable</b>
+ UINT32 RCVENC1D:1; ///< Bit 29 - Enable/Disable Receive Enable Centering Training (LPDDR Only). Note it is not recommended to change this setting from the default value: <b>0=Disable</b>, 1=Enable
+ UINT32 RMC:1; ///< Bit 30 - Enable/Disable Retrain Margin Check. Note it is not recommended to change this setting from the default value: <b>0=Disable</b>, 1=Enable
+ UINT32 WRDSUDT:1; ///< Bit 31 - Enable/Disable Write Drive Strength Up/Dn independently. Note it is not recommended to change this setting from the default value: <b>0=Disable</b>, 1=Enable
+ /// Training Algorithms 2 Offset 88
+ UINT32 DCC : 1; ///< Bit 0 - Enable/Disable Duty Cycle Correction: 0=Disable, 1=Enable.
+ UINT32 RDVC1D : 1; ///< Bit 1 - Enable/Disable Read Voltage Centering 1D: 0=Disable, 1=Enable.
+ UINT32 TXTCO : 1; ///< Bit 2 - Enable/Disable Write TCO Comp Training: 0=Disable, 1=Enable.
+ UINT32 CLKTCO : 1; ///< Bit 3 - Enable/Disable Clock TCO Comp Training: 0=Disable, 1=Enable.
+ UINT32 CMDSR : 1; ///< Bit 4 - Enable/Disable CMD Slew Rate Training: 0=Disable, 1=Enable.
+ UINT32 CMDDSEQ : 1; ///< Bit 5 - Enable/Disable CMD Drive Strength and Tx Equalization: 0=Disable, 1=Enable.
+ UINT32 DIMMODTCA : 1; ///< Bit 6 - Enable/Disable Dimm ODT CA Training: 0=Disable, 1=Enable.
+ UINT32 TXTCODQS : 1; ///< Bit 7 - Enable/Disable Write TCO Dqs Training: 0=Disable, 1=Enable.
+ UINT32 CMDDRUD : 1; ///< Bit 8 - Enable/Disable CMD/CTL Drive Strength Up/Dn 2D: 0=Disable, 1=Enable.
+ UINT32 VCCDLLBP : 1; ///< Bit 9 - Enable/Disable VccDLL bypass to VccIOG training: 0=Disable, 1=Enable.
+ UINT32 PVTTDNLP : 1; ///< Bit 10 - Enable/Disable PanicVttDnLp Training: 0=Disable, 1=Enable.
+ UINT32 RDVREFDC : 1; ///< Bit 11 - Enable/Disable Read Vref Decap Training: 0=Disable, 1=Enable.
+ UINT32 VDDQT : 1; ///< Bit 12 - Enable/Disable Vddq Training: 0=Disable, 1=Enable.
+ UINT32 RMTBIT : 1; ///< Bit 13 - Enable/Disable Rank Margin Tool Per Bit: 0=Disable, 1=Enable.
+ UINT32 PDA : 1; ///< BIT 14 - Enable/Disable PDA Enumeration Training. Note it is not recommended to change this setting from the default value: 0=Disable, <b>1=Enable</b>.
+ UINT32 DIMMDFE : 1; ///< BIT 15 - Enable/Disable DIMM DFE Training: 0=Disable, <b>1=Enable</b>.
+ UINT32 TXDQSDCC : 1; ///< BIT 16 - Enable/Disable TX DQS DCC Training: 0=Disable, <b>1=Enable</b>.
+ UINT32 DRAMDCA : 1; ///< BIT 17 - Enable/Disable DRAM DCA Training: 0=Disable, <b>1=Enable</b>.
+ UINT32 WRDS : 1; ///< BIT 18 - Enable/Disable Write Driver Strength Training: 0=Disable, <b>1=Enable</b>.
+ UINT32 EARLYDIMMDFE : 1; ///< BIT 19 - Enable/Disable EARLY DIMM DFE Training: 0=Disable, <b>1=Enable</b>.
+ UINT32 ReservedBits2 :12; ///< Bits 20:31 - Reserved
+
+ UINT32 MrcTimeMeasure:1; ///< Offset 92 Bit 0 - Enables serial debug level to display the MRC execution times only: <b>0=Disable</b>, 1=Enable
+ UINT32 MrcFastBoot:1; ///< Bit 1 - Enables the MRC fast boot path for faster cold boot execution: 0=Disable, <b>1=Enable</b>
+ UINT32 DqPinsInterleaved:1; ///< Bit 2 - Interleaving mode of DQ/DQS pins which depends on board routing: <b>0=Disable</b>, 1=Enable
+ UINT32 RankInterleave:1; ///< Bit 3 - Rank Interleave Mode: 0=Disable, <b>1=Enable</b>
+ UINT32 EnhancedInterleave:1; ///< Bit 4 - Enhanced Interleave Mode: 0=Disable, <b>1=Enable</b>
+ UINT32 WeaklockEn:1; ///< Bit 5 - Weak Lock Enable: 0=Disable, <b>1=Enable</b>
+ UINT32 ChHashEnable:1; ///< Bit 6 - Channel Hash Enable: 0=Disable, <b>1=Enable</b>
+ UINT32 EnablePwrDn:1; ///< Bit 7 - Enable Power Down control for DDR: 0=PCODE control, <b>1=BIOS control</b>
+ UINT32 EnablePwrDnLpddr:1; ///< Bit 8 - Enable Power Down for LPDDR: 0=PCODE control, <b>1=BIOS control</b>
+ UINT32 SrefCfgEna:1; ///< Bit 9 - Enable Self Refresh: 0=Disable, <b>1=Enable</b>
+ UINT32 ThrtCkeMinDefeatLpddr:1; ///< Bit 10 - Throttler CKE min defeature for LPDDR: 0=Disable, <b>1=Enable</b>
+ UINT32 ThrtCkeMinDefeat:1; ///< Bit 11 - Throttler CKE min defeature: <b>0=Disable</b>, 1=Enable
+ UINT32 AutoSelfRefreshSupport:1; ///< Bit 12 - FALSE = No auto self refresh support, <b>TRUE = auto self refresh support</b>
+ UINT32 ExtTemperatureSupport:1; ///< Bit 13 - FALSE = No extended temperature support, <b>TRUE = extended temperature support</b>
+ UINT32 MobilePlatform:1; ///< Bit 14 - Memory controller device id indicates: <b>TRUE if mobile</b>, FALSE if not. Note: This will be auto-detected and updated.
+ UINT32 Force1Dpc:1; ///< Bit 15 - TRUE means force one DIMM per channel, <b>FALSE means no limit</b>
+ UINT32 ForceSingleRank:1; ///< Bit 16 - TRUE means use Rank0 only (in each DIMM): <b>0=Disable</b>, 1=Enable
+ UINT32 VttTermination:1; ///< Bit 17 - Vtt Termination for Data ODT: <b>0=Disable</b>, 1=Enable
+ UINT32 VttCompForVsshi:1; ///< Bit 18 - Enable/Disable Vtt Comparator For Vsshi: <b>0=Disable</b>, 1=Enable
+ UINT32 ExitOnFailure:1; ///< Bit 19 - MRC option for exit on failure or continue on failure: 0=Disable, <b>1=Enable</b>
+ UINT32 NewFeatureEnable1:1; ///< Bit 20 - Generic enable knob for new feature set 1 <b>0: Disable </b>; 1: Enable
+ UINT32 NewFeatureEnable2:1; ///< Bit 21 - Generic enable knob for new feature set 2 <b>0: Disable </b>; 1: Enable
+ UINT32 RhSelect:2; ///< Bit 22-23 - RH Select: <b>0=Disable</b>, 1=RFM, 2=pTRR
+ UINT32 RefreshPanicWm:4; ///< Bit 24-27 - Deprecated from revision 17. Use RefreshWm instead.
+ UINT32 RefreshHpWm:4; ///< Bit 28-31 - Deprecated from revision 17. Use RefreshWm instead.
+ UINT32 VddSettleWaitTime; ///< Offset 96 Amount of time in microseconds to wait for Vdd to settle on top of 200us required by JEDEC spec: <b>Default=0</b>
+ UINT16 SrefCfgIdleTmr; ///< Offset 100 Self Refresh idle timer: <b>512=Minimal</b>, 65535=Maximum
+ UINT16 ChHashMask; ///< Offset 102 Channel Hash Mask: 0x0001=BIT6 set(Minimal), 0x3FFF=BIT[19:6] set(Maximum), <b>0x30CE= BIT[19:18, 13:12 ,9:7] set</b>
+ UINT16 DdrFreqLimit; ///< Offset 104 Memory Frequency limit: <b>0 = Auto</b>, or memory speed value in MT/s: 1067, 1333, 1600 etc. See the possible values in MrcInterface.h
+ UINT8 MaxRttWr; ///< Offset 106 Maximum DIMM RTT_WR to use in power training: <b>0=ODT Off</b>, 1 = 120 ohms
+ UINT8 ThrtCkeMinTmr; ///< Offset 107 Throttler CKE min timer: 0=Minimal, 0xFF=Maximum, <b>0x00=Default</b>
+ UINT8 ThrtCkeMinTmrLpddr; ///< Offset 108 Throttler CKE min timer for LPDDR: 0=Minimal, 0xFF=Maximum, <b>0x00=Default</b>
+ BOOLEAN PerBankRefresh; ///< Offset 109 Enables and Disables the per bank refresh. This only impacts memory technologies that support PBR: LPDDR4, LPDDR5 and DDR5. FALSE=Disabled, <b>TRUE=Enabled</b>
+ UINT8 SaGv; ///< Offset 110 SA GV: <b>0=Disabled</b>, 1=Point1, 2=Point2, 3=Point3, 4=Point4, 5=Enabled
+ UINT8 NModeSupport; ///< Offset 111 Memory N Mode Support - Enable user to select Auto, 1N or 2N: <b>0=AUTO</b>, 1=1N, 2=2N.
+ UINT8 RefClk; ///< Offset 112 Selects the DDR base reference clock. 0x01 = 100MHz, <b>0x00 = 133MHz</b>
+ UINT8 EnCmdRate; ///< Offset 113 CMD Rate Enable: 0=Disable, 5=2 CMDs, <b>7=3 CMDs</b>, 9=4 CMDs, 11=5 CMDs, 13=6 CMDs, 15=7 CMDs
+ UINT8 Refresh2X; ///< Offset 114 Refresh 2x: <b>0=Disable</b>, 1=Enable for WARM or HOT, 2=Enable for HOT only
+ UINT8 EpgEnable; ///< Offset 115 Enable Energy Performance Gain.
+ UINT8 UserThresholdEnable; ///< Offset 116 Flag to manually select the DIMM CLTM Thermal Threshold, 0=Disable, 1=Enable, <b>0=Default</b>
+ UINT8 UserBudgetEnable; ///< Offset 117 Flag to manually select the Budget Registers for CLTM Memory Dimms , 0=Disable, 1=Enable, <b>0=Default</b>
+ UINT8 RetrainOnFastFail; ///< Offset 118 Restart MRC in Cold mode if SW MemTest fails during Fast flow. 0 = Disabled, <b>1 = Enabled</b>
+ UINT8 PowerDownMode; ///< Offset 119 CKE Power Down Mode: <b>0xFF=AUTO</b>, 0=No Power Down, 1= APD mode, 6=PPD-DLL Off mode
+ UINT8 PwdwnIdleCounter; ///< Offset 120 CKE Power Down Mode Idle Counter: 0=Minimal, 255=Maximum, <b>0x80=0x80 DCLK</b>
+ UINT8 CmdRanksTerminated; ///< Offset 121 LPDDR: Bitmask of ranks that have CA bus terminated. <b>0x01=Default, Rank0 is terminating and Rank1 is non-terminating</b>
+ UINT16 MsHashMask; ///< Offset 122 Controller Hash Mask: 0x0001=BIT6 set(Minimal), 0x3FFF=BIT[19:6] set(Maximum), <b>0x30CE= BIT[19:18, 13:12 ,9:7] set</b>
+ UINT32 Lp5CccConfig; ///< Offset 124 BitMask where bits [3:0] are controller 0 Channel [3:0] and [7:4] are Controller 1 Channel [3:0]. 0 selects Ascending mapping and 1 selects Descending mapping.
+ UINT8 RMTLoopCount; ///< Offset 128 Indicates the Loop Count to be used for Rank Margin Tool Testing: 1=Minimal, 32=Maximum, 0=AUTO, <b>0=Default</b>
+ UINT8 MsHashInterleaveBit; ///< Offset 129 Option to select interleave Address bit. Valid values are 0 - 3 for BITS 6 - 9
+ UINT8 GearRatio; ///< Offset 130 Gear mode when SAGV is disabled: <b>0=Auto</b>, 1 - Gear1, 2 - Gear2, 4 - Gear4.
+ UINT8 Ddr4OneDpc; ///< Offset 131 DDR4 1DPC performance feature: 0 - Disabled; 1 - Enabled on DIMM0 only, 2 - Enabled on DIMM1 only; 3 - Enabled on both DIMMs. (bit [0] - DIMM0, bit [1] - DIMM1)
+ UINT32 BclkRfiFreq[MEM_MAX_SAGV_POINTS]; ///< Offset 132 Bclk RFI Frequency for each SAGV point in Hz units. 98000000Hz = 98MHz <b>0 - No RFI Tuning</b>. Range is 98Mhz-100Mhz.
+ UINT16 SaGvFreq[MEM_MAX_SAGV_POINTS]; ///< Offset 148 Frequency per SAGV point. 0 is Auto, otherwise holds the frequency value expressed as an integer: <b>0=Default</b>, 1067, 1333, 1600, 1800, 1867, etc.
+ UINT8 SaGvGear[MEM_MAX_SAGV_POINTS]; ///< Offset 156 Gear ratio per SAGV point. 0 is Auto, otherwise holds the Gear ratio expressed as an integer: <b>0=Auto</b>, 1, 2, 4
+ UINT8 IbeccProtectedRangeEnable[MEM_MAX_IBECC_REGIONS]; ///< Offset 160 Enable use of address range for ECC Protection: <b>0=Disabled</b>, 1=Enabled
+ UINT32 IbeccProtectedRangeBase[MEM_MAX_IBECC_REGIONS]; ///< Offset 168 Base address for address range of ECC Protection: [0..0x3FFFFFF]
+ UINT32 IbeccProtectedRangeMask[MEM_MAX_IBECC_REGIONS]; ///< Offset 200 Mask address for address range of ECC Protection: [1..0x3FFFFFF]
+
+ UINT8 McRefresh2X; ///< Offset 232 Deprecated from revision 19, use McRefreshRate instead
+ UINT8 Lfsr0Mask; ///< Offset 233 RH pTRR LFSR0 Mask
+ UINT8 Lfsr1Mask; ///< Offset 234 RH pTRR LFSR1 Mask
+ UINT8 CmdMirror; ///< Offset 235 BitMask where bits [3:0] are controller 0 Channel [3:0] and [7:4] are Controller 1 Channel [3:0]. 0 = No Command Mirror and 1 = Command Mirror.
+ UINT8 AllowOppRefBelowWriteThrehold; ///< Offset 236 Option to allow opportunistic refreshes while we don't exit power down.
+ UINT8 WriteThreshold; ///< Offset 237 Option to set number of writes that can be accumulated while CKE is low before CKE is asserted.
+ UINT8 PprEnable; ///< Offset 238 Post-Package Repair: 0: Disabled, 2: Hard PPR
+ UINT8 MarginLimitCheck; ///< Offset 239 Margin limit check enable: <b>0=Disable</b>, 1=L1 only, 2=L2 only, 3=Both L1 and L2
+ UINT16 MarginLimitL2; ///< Offset 240 Margin limit check L2 threshold: <b>100=Default</b>
+ UINT8 LpddrRttWr; ///< Offset 242 Initial RttWr for LP4/5 in Ohms, 0 means Auto
+ UINT8 LpddrRttCa; ///< Offset 243 Initial RttCa for LP4/5 in Ohms, 0 means Auto
+ UINT16 VddqVoltage; ///< Offset 244 DRAM voltage (Vddq) in millivolts: <b>0=Platform Default (no override)</b>, 1200=1.2V, 1350=1.35V etc.
+ UINT16 VppVoltage; ///< Offset 246 DRAM voltage (Vpp) in millivolts: <b>0=Platform Default (no override)</b>, 1800=1.8V, 2050=2.05V etc.
+ UINT8 ExtendedBankHashing; ///< Offset 248 Enable EBH (Extended Bank Hashing): 0=Disabled; <b>1 = Enabled</b>
+ UINT8 DynamicMemoryBoost; ///< Offset 249 Enable/Disable Dynamic Memory Boost Feature. Only valid if SpdProfileSelected is an XMP Profile; otherwise ignored. <b>0=Disabled</b>, 1=Enabled.
+ UINT8 IbeccErrInjControl; ///< Offset 250 In-band ECC: Error Injection Control 0: No Error Injection, 1:Inject Correctable Error Address match, 3:Inject Correctable Error on insertion counter, 5: Inject Uncorrectable Error Address match, 7:Inject Uncorrectable Error on insertion counter
+ UINT8 RealtimeMemoryFrequency; ///< Offset 251 Enable/Disable Realtime Memory Frequency feature. Only valid if SpdProfileSelected is an XMP Profile; otherwise ignored. <b>0=Disabled</b>, 1=Enabled.
+ UINT32 IbeccErrInjCount; ///< Offset 252 Number of transactions between ECC error injection
+ UINT64 IbeccErrInjAddress; ///< Offset 256 Address to match against for ECC error injection
+ UINT64 IbeccErrInjMask; ///< Offset 264 Mask to match against for ECC error injection
+ UINT8 RefreshWm; ///< Offset 272 Refresh Watermarks, 0 = Low, <b>1 = High</b>
+ UINT8 McRefreshRate; ///< Offset 273 Type of solution to be used for RHP - 0/1/2/3 = RefreshNORMAL/Refresh1x/Refresh2x/Refresh4x
+ UINT8 Reserved274[2]; ///< Offset 274-275 Reserved for natural alignment
+ UINT32 DebugValue; ///< Offset 276 Debug Value for general use
+ UINT16 tRFCpb; ///< Offset 280 User defined Memory Timing tRFCpb value, valid when SpdProfileSelected is CUSTOM_PROFILE: <b>0=AUTO</b>, 28=Maximum.
+ UINT16 tRFC2; ///< Offset 282 User defined Memory Timing tRFC2 value, valid when SpdProfileSelected is CUSTOM_PROFILE: <b>0=AUTO</b>, 28=Maximum.
+ UINT16 tRFC4; ///< Offset 284 User defined Memory Timing tRFC4 value, valid when SpdProfileSelected is CUSTOM_PROFILE: <b>0=AUTO</b>, 28=Maximum.
+ UINT16 tRRD_L; ///< Offset 286 User defined Memory Timing tRRD_L value, valid when SpdProfileSelected is CUSTOM_PROFILE: <b>0=AUTO</b>, 28=Maximum.
+ UINT16 tRRD_S; ///< Offset 288 User defined Memory Timing tRRD_S value, valid when SpdProfileSelected is CUSTOM_PROFILE: <b>0=AUTO</b>, 28=Maximum.
+ UINT16 tWTR_L; ///< Offset 290 User defined Memory Timing tWTR_L value, valid when SpdProfileSelected is CUSTOM_PROFILE: <b>0=AUTO</b>, 28=Maximum.
+ UINT16 tCCD_L; ///< Offset 292 User defined Memory Timing tCCD_L value, valid when SpdProfileSelected is CUSTOM_PROFILE: <b>0=AUTO</b>, 28=Maximum.
+ UINT16 tWTR_S; ///< Offset 294 User defined Memory Timing tWTR_S value, valid when SpdProfileSelected is CUSTOM_PROFILE: <b>0=AUTO</b>, 28=Maximum.
+ UINT64 EccErrInjAddress; ///< Offset 296 Address to match against for ECC error injection
+ UINT64 EccErrInjMask; ///< Offset 304 Mask to match against for ECC error injection
+ UINT32 EccErrInjCount; ///< Offset 312 Number of transactions between ECC error injection
+
+
+ UINT16 FreqLimitMixedConfig; ///< Offset 316 Override the reduced speed in mixed 2DPC config or non-POR 2DPC config. <b>0=Auto</b>, otherwise speed in MT/s: 1067, 1333 etc. See the possible values in MrcInterface.h
+ UINT8 FirstDimmBitMask; ///< Offset 318 Defines which DIMM should be populated first on a 2DPC board.
+ ///< 4 bit mask: Bit[0]: MC0 DIMM0, Bit[1]: MC0 DIMM1, Bit[2]: MC1 DIMM0, Bit[3]: MC1 DIMM1.
+ ///< For each MC, the first DIMM to be populated should be set to '1'.
+ ///< Note: this mask is only for non-ECC DIMM.
+ UINT8 UserBd; ///< Offset 319 MrcBoardType
+ ///< 1 - Desktop 1DPC
+ ///< 2 - Desktop 2DPC, Daisy Chain, far DIMM should be populated first
+ ///< 3 - Desktop 2DPC, T-topology with asymmetrical DIMM0/1 routing, has particular DIMM population order
+ ///< 4 - Desktop 2DPC, T-topology with symmetrical DIMM0/1 routing, no particular DIMM population order
+ ///< 5 - ULT Mobile
+ UINT8 SagvSwitchFactorIA; ///< Offset 320 Sagv Switch Factor: <b>1 </b>, 50=Maximum, default 30.
+ UINT8 SagvSwitchFactorGT; ///< Offset 321 Sagv Switch Factor: <b>1 </b>, 50=Maximum, default 30.
+ UINT8 SagvSwitchFactorIO; ///< Offset 322 Sagv Switch Factor: <b>1 </b>, 50=Maximum, default 30.
+ UINT8 SagvSwitchFactorStall; ///< Offset 323 Sagv Switch Factor: <b>1 </b>, 50=Maximum, default 30.
+ UINT8 SagvHeuristicsUpControl;///< Offset 324 Sagv duration in ms before heuristics up: <b>1 </b>, 50=Maximum, default 1ms.
+ UINT8 SagvHeuristicsDownControl; ///< Offset 325 Sagv duration in ms before heuristics down: <b>1 </b>, 50=Maximum, default 1ms.
+ UINT16 FreqLimitMixedConfig_1R1R_8GB; ///< Offset 326 The frequency limit for mixed DIMM configuration 1R1R_8GB (1R 8GB and 1R 8GB in one channel).
+ ///< It's to be set by customer. Customer can connect it to a setup option, or an UPD, etc. By default, the value will be 2000.
+ UINT16 FreqLimitMixedConfig_1R1R_16GB; ///< Offset 328 The frequency limit for mixed DIMM configuration 1R1R_16GB (1R 16GB and 1R 16GB in one channel).
+ ///< It's to be set by customer. Customer can connect it to a setup option, or an UPD, etc. By default, the value will be 2000.
+ UINT16 FreqLimitMixedConfig_1R1R_8GB_16GB; ///< Offset 330 The frequency limit for mixed DIMM configuration 1R1R_8GB_16GB (1R 8GB and 1R 16GB in one channel).
+ ///< It's to be set by customer. Customer can connect it to a setup option, or an UPD, etc. By default, the value will be 2000.
+ UINT16 FreqLimitMixedConfig_2R2R; ///< Offset 332 The frequency limit for mixed DIMM configuration 2R_2R (2R 32GB and 2R 32GB in one channel).
+ ///< It's to be set by customer. Customer can connect it to a setup option, or an UPD, etc. By default, the value will be 2000.
+ UINT16 LctCmdEyeWidth; ///< Offset 334 LCT Command eyewidth
+ UINT8 FirstDimmBitMaskEcc; ///< Offset 336 Defines which ECC DIMM should be populated first on a 2DPC board.
+ ///< 4 bit mask: Bit[0]: MC0 DIMM0, Bit[1]: MC0 DIMM1, Bit[2]: MC1 DIMM0, Bit[3]: MC1 DIMM1.
+ ///< For each MC, the first DIMM to be populated should be set to '1'.
+ ///< For example, if one MC is T-topology, there is no special population rule, can put it as 11 for this MC and it means either D0 or D1 can be
+ ///< be populated firstly.
+ ///< Note: this mask is only for ECC DIMM, not for non-ECC DIMM.
+ UINT8 Lp5BankMode; ///< Offset 337 LP5 Bank Mode
+ UINT8 OverloadSAM; ///< Offset 338 Overload SAM to copy the sagv frquency point.
+ UINT8 Reserved339[5]; ///< Offset 339-343 Reserved for natural alignment
+} MEMORY_CONFIGURATION;
+
+/// Memory Configuration
+/// The contents of this structure are not CRC'd by the MRC for option change detection.
+/// <b>Revision 1</b>: - Initial version.
+/// <b>Revision 2</b>: - Added MemTestOnWarmBoot
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Block Header
+ SA_FUNCTION_CALLS SaCall; ///< Offset 28 Function calls into the SA.
+ SA_MEMORY_FUNCTIONS MrcCall; ///< Offset 212 Function calls into the MRC.
+ SPD_DATA_BUFFER *SpdData; ///< Offset 236 Memory SPD data, will be used by the MRC when SPD SmBus address is zero.
+ SA_MEMORY_DQDQS_MAPPING *DqDqsMap; ///< Offset 240 LPDDR DQ bit and DQS byte swizzling between CPU and DRAM.
+ SA_MEMORY_RCOMP *RcompData; ///< Offset 244 DDR RCOMP resistors and target values.
+ UINT64 PlatformMemorySize; ///< Offset 248 The minimum platform memory size required to pass control into DXE
+ UINT32 CleanMemory:1; ///< Offset 256 Ask MRC to clear memory content: <b>FALSE=Do not Clear Memory</b>; TRUE=Clear Memory
+ UINT32 ReservedBits5:31;
+ /**
+ Sets the serial debug message level\n
+ 0x00 = Disabled\n
+ 0x01 = Errors only\n
+ 0x02 = Errors and Warnings\n
+ <b>0x03 = Errors, Warnings, and Info</b>\n
+ 0x04 = Errors, Warnings, Info, and Events\n
+ 0x05 = Displays Memory Init Execution Time Summary only\n
+ **/
+ UINT8 SerialDebugLevel; ///< Offset 260
+ UINT8 MemTestOnWarmBoot; ///< Offset 261 Run Base Memory Test On WarmBoot: 0=Disabled, <b>1=Enabled</b>
+ UINT8 Reserved11[2]; ///< Offset 262 - 263 Reserved
+} MEMORY_CONFIG_NO_CRC;
+#pragma pack(pop)
+
+#endif // _MEMORY_CONFIG_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/PchDmi/PchDmiConfig.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/PchDmi/PchDmiConfig.h
new file mode 100644
index 0000000000..84cc21091f
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/PchDmi/PchDmiConfig.h
@@ -0,0 +1,65 @@
+/** @file
+ DMI policy
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _PCH_DMI_CONFIG_H_
+#define _PCH_DMI_CONFIG_H_
+
+extern EFI_GUID gPchDmiConfigGuid;
+
+/*
+<b>Revision 1</b>: - Initial version.
+*/
+#define PCH_DMI_PREMEM_CONFIG_REVISION 1
+extern EFI_GUID gPchDmiPreMemConfigGuid;
+
+#pragma pack (push,1)
+
+#define PCH_DMI_HWEQ_COEFFS_MAX 8
+/**
+ Lane specific Dmi Gen3, Gen4 equalization parameters.
+**/
+typedef struct {
+ UINT8 Cm; ///< Coefficient C-1
+ UINT8 Cp; ///< Coefficient C+1
+ UINT8 Rsvd0[2]; ///< Reserved bytes
+} PCH_DMI_EQ_PARAM;
+
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Config Block
+ PCH_DMI_EQ_PARAM DmiHwEqGen3CoeffList[PCH_DMI_HWEQ_COEFFS_MAX];
+ UINT8 DmiHweq;
+ UINT8 Reserved[3];
+} PCH_DMI_PREMEM_CONFIG;
+
+
+/**
+ The PCH_DMI_CONFIG block describes the expected configuration of the PCH for DMI.
+ <b>Revision 1</b>:
+ - Initial version.
+**/
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Config Block Header
+
+ UINT32 PwrOptEnable : 1; ///< <b>0: Disable</b>; 1: Enable DMI Power Optimizer on PCH side.
+ UINT32 DmiAspmCtrl : 8; ///< ASPM configuration on the PCH side of the DMI/OPI Link. Default is <b>PchPcieAspmAutoConfig</b>
+ UINT32 CwbEnable : 1; ///< 0: Disable; <b>1: Enable</b> Central Write Buffer feature configurable and enabled by default
+ UINT32 L1RpCtl : 1; ///< 0: Disable; <b>1: Enable</b> Allow DMI enter L1 when all root ports are in L1, L0s or link down. Disabled by default.
+ /**
+ When set to TRUE turns on:
+ - L1 State Controller Power Gating
+ - L1 State PHY Data Lane Power Gating
+ - PHY Common Lane Power Gating
+ - Hardware Autonomous Enable
+ - PMC Request Enable and Sleep Enable
+ **/
+ UINT32 DmiPowerReduction : 1;
+ UINT32 ClockGating : 1; ///< 0: Disable; 1: Enable clock gating.
+ UINT32 Rsvdbits : 19; ///< Reserved bits
+} PCH_DMI_CONFIG;
+
+#pragma pack (pop)
+
+#endif // _PCH_DMI_CONFIG_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/PcieRp/PchPcieRp/PchPcieRpConfig.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/PcieRp/PchPcieRp/PchPcieRpConfig.h
new file mode 100644
index 0000000000..d97f3b878a
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/PcieRp/PchPcieRp/PchPcieRpConfig.h
@@ -0,0 +1,180 @@
+/** @file
+ PCH Pcie root port policy
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _PCH_PCIERP_CONFIG_H_
+#define _PCH_PCIERP_CONFIG_H_
+
+#include <PchLimits.h>
+#include <PcieConfig.h>
+#include <ConfigBlock.h>
+
+
+
+
+
+/*
+ Making any setup structure change after code frozen
+ will need to maintain backward compatibility, bump up
+ structure revision and update below history table\n
+
+<b>Revision 1</b>: - Initial version.
+*/
+#define PCIE_RP_DXE_CONFIG_REVISION 1
+
+extern EFI_GUID gPchPcieConfigGuid;
+extern EFI_GUID gPcieRpPreMemConfigGuid;
+
+#pragma pack (push,1)
+
+typedef enum {
+ PchPcieOverrideDisabled = 0,
+ PchPcieL1L2Override = 0x01,
+ PchPcieL1SubstatesOverride = 0x02,
+ PchPcieL1L2AndL1SubstatesOverride = 0x03,
+ PchPcieLtrOverride = 0x04
+} PCH_PCIE_OVERRIDE_CONFIG;
+
+///
+/// The values before AutoConfig match the setting of PCI Express Base Specification 1.1, please be careful for adding new feature
+///
+typedef enum {
+ PchPcieAspmDisabled,
+ PchPcieAspmL0s,
+ PchPcieAspmL1,
+ PchPcieAspmL0sL1,
+ PchPcieAspmAutoConfig,
+ PchPcieAspmMax
+} PCH_PCIE_ASPM_CONTROL;
+
+/**
+ Refer to PCH EDS for the PCH implementation values corresponding
+ to below PCI-E spec defined ranges
+**/
+typedef enum {
+ PchPcieL1SubstatesDisabled,
+ PchPcieL1SubstatesL1_1,
+ PchPcieL1SubstatesL1_1_2,
+ PchPcieL1SubstatesMax
+} PCH_PCIE_L1SUBSTATES_CONTROL;
+
+enum PCH_PCIE_MAX_PAYLOAD {
+ PchPcieMaxPayload128 = 0,
+ PchPcieMaxPayload256,
+ PchPcieMaxPayloadMax
+};
+
+
+/**
+ PCH_PCIE_CLOCK describes PCIe source clock generated by PCH.
+**/
+typedef struct {
+ UINT8 Usage; ///< Purpose of given clock (see PCH_PCIE_CLOCK_USAGE). Default: Unused, 0xFF
+ UINT8 ClkReq; ///< ClkSrc - ClkReq mapping. Default: 1:1 mapping with Clock numbers
+ UINT8 RsvdBytes[2]; ///< Reserved byte
+ UINT32 ClkReqGpioPinMux; /// Muxed GPIO details. Refer GPIO_*_MUXING_SRC_CLKREQ_x*
+} PCH_PCIE_CLOCK;
+
+
+/**
+ The PCH_PCI_EXPRESS_ROOT_PORT_CONFIG describe the feature and capability of each PCH PCIe root port.
+**/
+typedef struct {
+ PCIE_ROOT_PORT_COMMON_CONFIG PcieRpCommonConfig; ///an instance of Pcie Common Config
+ UINT8 ExtSync; ///< Indicate whether the extended synch is enabled. <b>0: Disable</b>; 1: Enable.
+ //
+ // Error handlings
+ //
+ UINT8 SystemErrorEnable; ///< Indicate whether the System Error is enabled. <b>0: Disable</b>; 1: Enable.
+ /**
+ The Multiple VC (MVC) supports hardware to avoid HoQ block for latency sensitive TC.
+ Currently it is only applicable to Root Ports with 2pX4 port configuration with 2 VCs,or
+ DMI port configuration with 3 VCs. For Root Ports 2pX4 configuration, two RPs (RP0,
+ RP2) shall support two PCIe VCs (VC0 & VC1) and the other RPs (RP1, RP3) shall be
+ disabled.
+ <b>0: Disable</b>; 1: Enable
+ **/
+ UINT8 MvcEnabled;
+ /**
+ Virtual Pin Port is industry standard introduced to PCIe Hot Plug support in systems
+ when GPIO pins expansion is needed. It is server specific feature.
+ <b>0x00: Default</b>; 0xFF: Disabled
+ **/
+ UINT8 VppPort;
+ UINT8 VppAddress; ///< PCIe Hot Plug VPP SMBus Address. Default is zero.
+ UINT8 RsvdBytes0[3]; ///< Reserved bytes
+} PCH_PCIE_ROOT_PORT_CONFIG;
+
+/**
+ The PCH_PCIE_CONFIG block describes the expected configuration of the PCH PCI Express controllers
+ <b>Revision 1</b>:
+ - Initial version.
+ <b>Revision 2</b>:
+ - Moved EnablePort8xhDecode policy to PCIE_COMMON_CONFIG
+**/
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Config Block Header
+ ///
+ /// These members describe the configuration of each PCH PCIe root port.
+ ///
+ PCIE_COMMON_CONFIG PcieCommonConfig;
+ PCH_PCIE_ROOT_PORT_CONFIG RootPort[PCH_MAX_PCIE_ROOT_PORTS];
+ PCH_PCIE_ROOT_PORT_CONFIG DmiPort;
+
+ ///
+ /// <b>(Test)</b> The Index of PCIe Port that is selected for Port8xh Decode (0 Based)
+ ///
+ UINT8 PchPciePort8xhDecodePortIndex;
+ UINT8 DmiPowerReduction;
+ UINT8 RsvdBytes0[2];
+} PCH_PCIE_CONFIG;
+
+/**
+ The PCH_PCIE_RP_PREMEM_CONFIG block describes early configuration of the PCH PCI Express controllers
+ <b>Revision 1</b>:
+ - Initial version.
+**/
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Config Block Header
+ /**
+ Root Port enabling mask.
+ Bit0 presents RP1, Bit1 presents RP2, and so on.
+ 0: Disable; <b>1: Enable</b>.
+ **/
+ UINT32 RpEnabledMask;
+ /// Configuration of PCIe source clocks
+ ///
+ PCH_PCIE_CLOCK PcieClock[PCH_MAX_PCIE_CLOCKS];
+
+ /**
+ Per Controller Bifurcation Configuration
+ <b>0: Disabled</b>; 1: 4x1; 2: 1x2_2x1; 3: 2x2; 4: 1x4; 5: 4x2; 6: 1x4_2x2; 7: 2x2_1x4; 8: 2x4; 9: 1x8 (see: PCIE_BIFURCATION_CONFIG)
+ **/
+ UINT8 Bifurcation[PCH_MAX_PCIE_CONTROLLERS];
+ UINT8 Rsvd4[(4 - PCH_MAX_PCIE_CONTROLLERS % 4) % 4];
+} PCH_PCIE_RP_PREMEM_CONFIG;
+
+/**
+ The PCIE_RP_DXE_CONFIG block describes the expected configuration of the PCH PCI Express controllers in DXE phase
+
+ <b>Revision 1</b>:
+ - Init version
+**/
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Config Block Header
+
+ /**
+ PCIe device override table
+ The PCIe device table is being used to override PCIe device ASPM settings.
+ And it's only used in DXE phase.
+ Please refer to PCIE_DEVICE_OVERRIDE structure for the table.
+ Last entry VendorId must be 0.
+ **/
+ PCIE_DEVICE_OVERRIDE *PcieDeviceOverrideTablePtr;
+} PCIE_RP_DXE_CONFIG;
+
+#pragma pack (pop)
+
+#endif // _PCH_PCIERP_CONFIG_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/PcieRp/PcieConfig.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/PcieRp/PcieConfig.h
new file mode 100644
index 0000000000..07a5644f43
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/PcieRp/PcieConfig.h
@@ -0,0 +1,408 @@
+/** @file
+ PCIe Config Block
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _PCIE_CONFIG_H_
+#define _PCIE_CONFIG_H_
+#include <CpuPcieInfo.h>
+
+#define PCIE_LINK_EQ_COEFFICIENTS_MAX 10
+#define PCIE_LINK_EQ_PRESETS_MAX 11
+extern EFI_GUID gPcieConfigGuid;
+
+#pragma pack (push,1)
+
+enum PCIE_COMPLETION_TIMEOUT {
+ PcieCompletionTO_Default,
+ PcieCompletionTO_50_100us,
+ PcieCompletionTO_1_10ms,
+ PcieCompletionTO_16_55ms,
+ PcieCompletionTO_65_210ms,
+ PcieCompletionTO_260_900ms,
+ PcieCompletionTO_1_3P5s,
+ PcieCompletionTO_4_13s,
+ PcieCompletionTO_17_64s,
+ PcieCompletionTO_Disabled
+};
+
+typedef enum {
+ PcieAuto,
+ PcieGen1,
+ PcieGen2,
+ PcieGen3,
+ PcieGen4,
+ PcieGen5
+} PCIE_SPEED;
+
+typedef enum {
+ PcieDisabled,
+ PcieL1SUB_1,
+ PcieL1SUB_1_2
+}L1_SUBSTATES;
+
+/**
+ Represent lane specific PCIe Gen3 equalization parameters.
+**/
+typedef struct {
+ UINT8 Cm; ///< Coefficient C-1
+ UINT8 Cp; ///< Coefficient C+1
+ UINT8 Rsvd0[2]; ///< Reserved bytes
+} PCIE_EQ_PARAM;
+
+typedef struct {
+ UINT16 LtrMaxSnoopLatency; ///< <b>(Test)</b> Latency Tolerance Reporting, Max Snoop Latency.
+ UINT16 LtrMaxNoSnoopLatency; ///< <b>(Test)</b> Latency Tolerance Reporting, Max Non-Snoop Latency.
+ UINT8 SnoopLatencyOverrideMode; ///< <b>(Test)</b> Latency Tolerance Reporting, Snoop Latency Override Mode.
+ UINT8 SnoopLatencyOverrideMultiplier; ///< <b>(Test)</b> Latency Tolerance Reporting, Snoop Latency Override Multiplier.
+ UINT16 SnoopLatencyOverrideValue; ///< <b>(Test)</b> Latency Tolerance Reporting, Snoop Latency Override Value.
+ UINT8 NonSnoopLatencyOverrideMode; ///< <b>(Test)</b> Latency Tolerance Reporting, Non-Snoop Latency Override Mode.
+ UINT8 NonSnoopLatencyOverrideMultiplier; ///< <b>(Test)</b> Latency Tolerance Reporting, Non-Snoop Latency Override Multiplier.
+ UINT16 NonSnoopLatencyOverrideValue; ///< <b>(Test)</b> Latency Tolerance Reporting, Non-Snoop Latency Override Value.
+ UINT8 LtrConfigLock; ///< <b>0: Disable</b>; 1: Enable.
+ UINT8 ForceLtrOverride;
+ UINT16 RsvdByte1;
+} PCIE_LTR_CONFIG;
+
+
+/**
+ Specifies the form factor that the slot
+ implements. For custom form factors that
+ do not require any special handling please
+ set PcieFormFactorOther.
+**/
+typedef enum {
+ PcieFormFactorOther = 0,
+ PcieFormFactorCem,
+ PcieFormFactorMiniPci,
+ PcieFormFactorM2,
+ PcieFormFactorOcuLink,
+ PcieFormFactorExpressModule, // Also known as Server IO module(SIOM)
+ PcieFormFactorExpressCard,
+ PcieFormFactorU2 // Also known as SF-8639
+} PCIE_FORM_FACTOR;
+
+typedef enum {
+ PcieLinkHardwareEq = 0, ///< Hardware is responsible for performing coefficient/preset search.
+ PcieLinkFixedEq ///< No coefficient/preset search is performed. Fixed values are used.
+} PCIE_LINK_EQ_METHOD;
+
+typedef enum {
+ PcieLinkEqPresetMode = 0, ///< Use presets during PCIe link equalization
+ PcieLinkEqCoefficientMode ///< Use coefficients during PCIe link equalization
+} PCIE_LINK_EQ_MODE;
+
+typedef struct {
+ UINT32 PreCursor; ///< Pre-cursor coefficient
+ UINT32 PostCursor; ///< Post-cursor coefficient
+} PCIE_LINK_EQ_COEFFICIENTS;
+
+/**
+ PCIe Link EQ Platform Settings
+**/
+typedef struct {
+ UINT8 PcieLinkEqMethod; ///< Tells BIOS which link EQ method should be used for this port. Please refer to PCIE_LINK_EQ_METHOD for details of supported methods. Default: PcieLinkHardwareEq
+ UINT8 PcieLinkEqMode; ///< Tells BIOS which mode should be used for PCIe link EQ. Please refer to PCIE_LINK_EQ_MODE for details of supported modes. Default: depends on SoC
+ /**
+ Specifies if BIOS should perform local transmitter override during phase 2 of EQ process.
+ If enabled value in Ph2LocalTransmitterOverridePreset must be valid.
+ <b>0: Disabled</b>; 1: Enabled
+ **/
+ UINT8 LocalTransmitterOverrideEnable;
+ /**
+ Tells BIOS how many presets/coefficients should be used during link EQ.
+ Entries in the Ph3CoefficientsList or Ph3PresetList(depending on chosen mode) need to be valid up to the number specified in this field.
+ **/
+ UINT8 Ph3NumberOfPresetsOrCoefficients;
+
+ PCIE_LINK_EQ_COEFFICIENTS Ph3CoefficientsList[PCIE_LINK_EQ_COEFFICIENTS_MAX]; ///< List of the PCIe coefficients to be used during equalization process. Only valid if PcieLinkEqMode is PcieLinkEqCoefficientMode
+ UINT32 Ph3PresetList[PCIE_LINK_EQ_PRESETS_MAX]; ///< List of the PCIe preset values to be used during equalization process. Only valid if PcieLinkEqMode is PcieLinkEqPresetMode
+ UINT32 Ph1DownstreamPortTransmitterPreset; ///< Specifies the value of the downstream port transmitter preset to be used during phase 1 of the equalization process. Will be applied to all lanes
+ UINT32 Ph1UpstreamPortTransmitterPreset; ///< Specifies the value of the upstream port transmitter preset to be used during phase 1 of the equalization process. Will be applied to all lanes
+ /**
+ Specifies the preset that should be used during local transmitter override during phase 2 of EQ process.
+ Used only if LocalTransmitterOverrideEnable is TRUE. Will be applied to all PCIe lanes of the root port.
+ Valid up to the PCIE_LINK_EQ_PRESET_MAX value. <b>Default: 0<\b>
+ **/
+ UINT32 Ph2LocalTransmitterOverridePreset;
+ UINT32 PCETTimer; ///< PCET Timer value for single PCIe speed.
+ UINT8 RemotePresetCoeffoverride; ///< Remote Transmitter Preset Coefficient Override for single PCIe speed.
+ /**
+ PCIe Equalization Phase 3 Enable Control
+ - <b>Disabled</b> (0x0) : Disable phase 3 (Default)
+ - Enabled (0x1) : Enable phase 3
+ **/
+ UINT8 EqPh3Bypass;
+ /**
+ PCIe Equalization Phase 2-3 Enable Control
+ - <b>Disabled</b> (0x0) : Disable Phase 2 - Phase 3 (Default)
+ - Enabled (0x1) : Enable Phase 2 - Phase 3
+ **/
+ UINT8 EqPh23Bypass;
+ UINT8 TsLockTimer; ///< 8.0GT/s Training Sequence Wait Latency For Presets / Coefficients Evaluation - Gen3 TS Lock Timer
+} PCIE_LINK_EQ_PLATFORM_SETTINGS;
+
+//Note: This structure will be expanded to hold all common PCIe policies between SA and PCH RootPort
+typedef struct {
+ UINT32 HotPlug : 1; ///< Indicate whether the root port is hot plug available. <b>0: Disable</b>; 1: Enable.
+ UINT32 PmSci : 1; ///< Indicate whether the root port power manager SCI is enabled. 0: Disable; <b>1: Enable</b>.
+ UINT32 TransmitterHalfSwing : 1; ///< Indicate whether the Transmitter Half Swing is enabled. <b>0: Disable</b>; 1: Enable.
+ UINT32 AcsEnabled : 1; ///< Indicate whether the ACS is enabled. 0: Disable; <b>1: Enable</b>.
+ //
+ // Error handlings
+ //
+ UINT32 AdvancedErrorReporting : 1; ///< Indicate whether the Advanced Error Reporting is enabled. <b>0: Disable</b>; 1: Enable.
+ UINT32 UnsupportedRequestReport : 1; ///< Indicate whether the Unsupported Request Report is enabled. <b>0: Disable</b>; 1: Enable.
+ UINT32 FatalErrorReport : 1; ///< Indicate whether the Fatal Error Report is enabled. <b>0: Disable</b>; 1: Enable.
+ UINT32 NoFatalErrorReport : 1; ///< Indicate whether the No Fatal Error Report is enabled. <b>0: Disable</b>; 1: Enable.
+ UINT32 CorrectableErrorReport : 1; ///< Indicate whether the Correctable Error Report is enabled. <b>0: Disable</b>; 1: Enable.
+ UINT32 SystemErrorOnFatalError : 1; ///< Indicate whether the System Error on Fatal Error is enabled. <b>0: Disable</b>; 1: Enable.
+ UINT32 SystemErrorOnNonFatalError : 1; ///< Indicate whether the System Error on Non Fatal Error is enabled. <b>0: Disable</b>; 1: Enable.
+ UINT32 SystemErrorOnCorrectableError : 1; ///< Indicate whether the System Error on Correctable Error is enabled. <b>0: Disable</b>; 1: Enable.
+ /**
+ Max Payload Size supported, Default <b>128B</b>, see enum CPU_PCIE_MAX_PAYLOAD
+ Changes Max Payload Size Supported field in Device Capabilities of the root port.
+ **/
+ UINT32 MaxPayload : 2;
+ UINT32 DpcEnabled : 1; ///< Downstream Port Containment. 0: Disable; <b>1: Enable</b>
+ UINT32 RpDpcExtensionsEnabled : 1; ///< RP Extensions for Downstream Port Containment. 0: Disable; <b>1: Enable</b>
+ /**
+ Indicates how this root port is connected to endpoint. 0: built-in device; <b>1: slot</b>
+ Built-in is incompatible with hotplug-capable ports.
+ **/
+ UINT32 SlotImplemented : 1;
+ UINT32 PtmEnabled : 1; ///< Enables PTM capability
+ UINT32 SlotPowerLimitScale : 2; ///< <b>(Test)</b> Specifies scale used for slot power limit value. Leave as 0 to set to default. Default is <b>zero</b>.
+ UINT32 SlotPowerLimitValue : 12; //< <b>(Test)</b> Specifies upper limit on power supplies by slot. Leave as 0 to set to default. Default is <b>zero</b>.
+ /**
+ Probe CLKREQ# signal before enabling CLKREQ# based power management.
+ Conforming device shall hold CLKREQ# low until CPM is enabled. This feature attempts
+ to verify CLKREQ# signal is connected by testing pad state before enabling CPM.
+ In particular this helps to avoid issues with open-ended PCIe slots.
+ This is only applicable to non hot-plug ports.
+ <b>0: Disable</b>; 1: Enable.
+ **/
+ UINT32 ClkReqDetect : 1;
+ /**
+ Set if the slot supports manually operated retention latch.
+ **/
+ UINT32 MrlSensorPresent : 1;
+ UINT32 RelaxedOrder : 1;
+ UINT32 NoSnoop : 1;
+ ///
+ /// This member describes whether Peer Memory Writes are enabled on the platform. <b>0: Disable</b>; 1: Enable.
+ ///
+ UINT32 EnablePeerMemoryWrite : 1;
+ ///
+ /// This member describes whether the PCI Express Clock Gating for each root port
+ /// is enabled by platform modules. <b>0: Disable</b>; 1: Enable.
+ ///
+ UINT32 ClockGating : 1;
+ ///
+ /// This member describes whether the PCI Express Power Gating for each root port
+ /// is enabled by platform modules. <b>0: Disable</b>; 1: Enable.
+ ///
+ UINT32 PowerGating : 1;
+ UINT32 RsvdBits0 : 25; ///< Reserved bits.
+ /**
+ PCIe Gen3 Equalization Phase 3 Method (see CPU_PCIE_EQ_METHOD).
+ 0: DEPRECATED, hardware equalization; <b>1: hardware equalization</b>; 4: Fixed Coefficients
+ **/
+ UINT8 Gen3EqPh3Method;
+ UINT8 PhysicalSlotNumber; ///< Indicates the slot number for the root port. Default is the value as root port index.
+ UINT8 CompletionTimeout; ///< The completion timeout configuration of the root port (see: CPU_PCIE_COMPLETION_TIMEOUT). Default is <b>PchPcieCompletionTO_Default</b>.
+ //
+ // Power Management
+ //
+ UINT8 Aspm; ///< The ASPM configuration of the root port (see: CPU_PCIE_ASPM_CONTROL). Default is <b>PchPcieAspmAutoConfig</b>.
+ UINT8 L1Substates; ///< The L1 Substates configuration of the root port (see: CPU_PCIE_L1SUBSTATES_CONTROL). Default is <b>PchPcieL1SubstatesL1_1_2</b>.
+ UINT8 LtrEnable; ///< Latency Tolerance Reporting Mechanism. <b>0: Disable</b>; 1: Enable.
+ UINT8 EnableCpm; ///< Enables Clock Power Management; even if disabled, CLKREQ# signal can still be controlled by L1 PM substates mechanism
+ UINT8 PcieSpeed; ///< Contains speed of PCIe bus (see: PCIE_SPEED)
+ /**
+ <b>(Test)</b>
+ Forces LTR override to be permanent
+ The default way LTR override works is:
+ rootport uses LTR override values provided by BIOS until connected device sends an LTR message, then it will use values from the message
+ This settings allows force override of LTR mechanism. If it's enabled, then:
+ rootport will use LTR override values provided by BIOS forever; LTR messages sent from connected device will be ignored
+ **/
+ PCIE_LTR_CONFIG PcieRpLtrConfig; ///< <b>(Test)</b> Latency Tolerance Reporting Policies including LTR limit and Override
+ /**
+ The number of milliseconds reference code will wait for link to exit Detect state for enabled ports
+ before assuming there is no device and potentially disabling the port.
+ It's assumed that the link will exit detect state before root port initialization (sufficient time
+ elapsed since PLTRST de-assertion) therefore default timeout is zero. However this might be useful
+ if device power-up seqence is controlled by BIOS or a specific device requires more time to detect.
+ In case of non-common clock enabled the default timout is 15ms.
+ <b>Default: 0</b>
+ **/
+ UINT16 DetectTimeoutMs;
+ UINT8 FormFactor; // Please check PCIE_FORM_FACTOR for supported values
+ UINT8 L1Low; ///< L1.LOW enable/disable. <b>0: Disable</b>; 1: Enable.
+ UINT8 LinkDownGpios;
+ ///
+ /// <b>0: Use project default equalization settings</b>; 1: Use equalization settings from PcieLinkEqPlatformSettings
+ ///
+ UINT8 OverrideEqualizationDefaults;
+ UINT8 Reserved[2];
+ PCIE_LINK_EQ_PLATFORM_SETTINGS PcieGen3LinkEqPlatformSettings; ///< Global PCIe Gen3 link EQ settings that BIOS will use during PCIe link EQ for every port.
+ PCIE_LINK_EQ_PLATFORM_SETTINGS PcieGen4LinkEqPlatformSettings; ///< Global PCIe Gen4 link EQ settings that BIOS will use during PCIe link EQ for every port.
+ PCIE_LINK_EQ_PLATFORM_SETTINGS PcieGen5LinkEqPlatformSettings; ///< Global PCIe Gen5 link EQ settings that BIOS will use during PCIe link EQ for every port.
+} PCIE_ROOT_PORT_COMMON_CONFIG;
+
+/**
+ PCIe Common Config
+ @note This structure will be expanded to hold all common PCIe policies between SA and PCH
+**/
+typedef struct {
+ /**
+ RpFunctionSwap allows BIOS to use root port function number swapping when root port of function 0 is disabled.
+ A PCIE device can have higher functions only when Function0 exists. To satisfy this requirement,
+ BIOS will always enable Function0 of a device that contains more than 0 enabled root ports.
+ - <b>Enabled: One of enabled root ports get assigned to Function0.</b>
+ This offers no guarantee that any particular root port will be available at a specific DevNr:FuncNr location
+ - Disabled: Root port that corresponds to Function0 will be kept visible even though it might be not used.
+ That way rootport - to - DevNr:FuncNr assignment is constant. This option will impact ports 1, 9, 17.
+ NOTE: This option will not work if ports 1, 9, 17 are fused or configured for RST PCIe storage or disabled through policy
+ In other words, it only affects ports that would become hidden because they have no device connected.
+ NOTE: Disabling function swap may have adverse impact on power management. This option should ONLY
+ be used when each one of root ports 1, 9, 17:
+ - is configured as PCIe and has correctly configured ClkReq signal, or
+ - does not own any mPhy lanes (they are configured as SATA or USB)
+ **/
+ UINT32 RpFunctionSwap : 1;
+ /**
+ Compliance Test Mode shall be enabled when using Compliance Load Board.
+ <b>0: Disable</b>, 1: Enable
+ **/
+ UINT32 ComplianceTestMode : 1;
+ UINT32 RsvdBits0 : 30; ///< Reserved bits
+ ///
+ /// <b>(Test)</b> This member describes whether PCIE root port Port 8xh Decode is enabled. <b>0: Disable</b>; 1: Enable.
+ ///
+ UINT8 EnablePort8xhDecode;
+ UINT8 RsvdBytes0[3];
+ ///
+ /// List of coefficients used during equalization (applicable to both software and hardware EQ)
+ /// Deprecated Policy
+ ///
+ PCIE_EQ_PARAM HwEqGen3CoeffList[PCIE_HWEQ_COEFFS_MAX];
+} PCIE_COMMON_CONFIG;
+
+typedef struct {
+ PCIE_EQ_PARAM HwEqGen3CoeffList[CPU_PCIE_MAX_ROOT_PORTS][PCIE_HWEQ_COEFFS_MAX];
+ PCIE_EQ_PARAM HwEqGen4CoeffList[CPU_PCIE_MAX_ROOT_PORTS][PCIE_HWEQ_COEFFS_MAX];
+ PCIE_EQ_PARAM HwEqGen5CoeffList[CPU_PCIE_MAX_ROOT_PORTS][PCIE_HWEQ_COEFFS_MAX];
+} PCIE_COMMON_CONFIG2;
+
+
+/**
+ PCIe device table entry entry
+
+ The PCIe device table is being used to override PCIe device ASPM settings.
+ To take effect table consisting of such entries must be instelled as PPI
+ on gPchPcieDeviceTablePpiGuid.
+ Last entry VendorId must be 0.
+**/
+typedef struct {
+ UINT16 VendorId; ///< The vendor Id of Pci Express card ASPM setting override, 0xFFFF means any Vendor ID
+ UINT16 DeviceId; ///< The Device Id of Pci Express card ASPM setting override, 0xFFFF means any Device ID
+ UINT8 RevId; ///< The Rev Id of Pci Express card ASPM setting override, 0xFF means all steppings
+ UINT8 BaseClassCode; ///< The Base Class Code of Pci Express card ASPM setting override, 0xFF means all base class
+ UINT8 SubClassCode; ///< The Sub Class Code of Pci Express card ASPM setting override, 0xFF means all sub class
+ UINT8 EndPointAspm; ///< Override device ASPM (see: PCH_PCIE_ASPM_CONTROL)
+ ///< Bit 1 must be set in OverrideConfig for this field to take effect
+ UINT16 OverrideConfig; ///< The override config bitmap (see: PCH_PCIE_OVERRIDE_CONFIG).
+ /**
+ The L1Substates Capability Offset Override. (applicable if bit 2 is set in OverrideConfig)
+ This field can be zero if only the L1 Substate value is going to be override.
+ **/
+ UINT16 L1SubstatesCapOffset;
+ /**
+ L1 Substate Capability Mask. (applicable if bit 2 is set in OverrideConfig)
+ Set to zero then the L1 Substate Capability [3:0] is ignored, and only L1s values are override.
+ Only bit [3:0] are applicable. Other bits are ignored.
+ **/
+ UINT8 L1SubstatesCapMask;
+ /**
+ L1 Substate Port Common Mode Restore Time Override. (applicable if bit 2 is set in OverrideConfig)
+ L1sCommonModeRestoreTime and L1sTpowerOnScale can have a valid value of 0, but not the L1sTpowerOnValue.
+ If L1sTpowerOnValue is zero, all L1sCommonModeRestoreTime, L1sTpowerOnScale, and L1sTpowerOnValue are ignored,
+ and only L1SubstatesCapOffset is override.
+ **/
+ UINT8 L1sCommonModeRestoreTime;
+ /**
+ L1 Substate Port Tpower_on Scale Override. (applicable if bit 2 is set in OverrideConfig)
+ L1sCommonModeRestoreTime and L1sTpowerOnScale can have a valid value of 0, but not the L1sTpowerOnValue.
+ If L1sTpowerOnValue is zero, all L1sCommonModeRestoreTime, L1sTpowerOnScale, and L1sTpowerOnValue are ignored,
+ and only L1SubstatesCapOffset is override.
+ **/
+ UINT8 L1sTpowerOnScale;
+ /**
+ L1 Substate Port Tpower_on Value Override. (applicable if bit 2 is set in OverrideConfig)
+ L1sCommonModeRestoreTime and L1sTpowerOnScale can have a valid value of 0, but not the L1sTpowerOnValue.
+ If L1sTpowerOnValue is zero, all L1sCommonModeRestoreTime, L1sTpowerOnScale, and L1sTpowerOnValue are ignored,
+ and only L1SubstatesCapOffset is override.
+ **/
+ UINT8 L1sTpowerOnValue;
+
+ /**
+ SnoopLatency bit definition
+ Note: All Reserved bits must be set to 0
+
+ BIT[15] - When set to 1b, indicates that the values in bits 9:0 are valid
+ When clear values in bits 9:0 will be ignored
+ BITS[14:13] - Reserved
+ BITS[12:10] - Value in bits 9:0 will be multiplied with the scale in these bits
+ 000b - 1 ns
+ 001b - 32 ns
+ 010b - 1024 ns
+ 011b - 32,768 ns
+ 100b - 1,048,576 ns
+ 101b - 33,554,432 ns
+ 110b - Reserved
+ 111b - Reserved
+ BITS[9:0] - Snoop Latency Value. The value in these bits will be multiplied with
+ the scale in bits 12:10
+
+ This field takes effect only if bit 3 is set in OverrideConfig.
+ **/
+ UINT16 SnoopLatency;
+ /**
+ NonSnoopLatency bit definition
+ Note: All Reserved bits must be set to 0
+
+ BIT[15] - When set to 1b, indicates that the values in bits 9:0 are valid
+ When clear values in bits 9:0 will be ignored
+ BITS[14:13] - Reserved
+ BITS[12:10] - Value in bits 9:0 will be multiplied with the scale in these bits
+ 000b - 1 ns
+ 001b - 32 ns
+ 010b - 1024 ns
+ 011b - 32,768 ns
+ 100b - 1,048,576 ns
+ 101b - 33,554,432 ns
+ 110b - Reserved
+ 111b - Reserved
+ BITS[9:0] - Non Snoop Latency Value. The value in these bits will be multiplied with
+ the scale in bits 12:10
+
+ This field takes effect only if bit 3 is set in OverrideConfig.
+ **/
+ UINT16 NonSnoopLatency;
+
+ /**
+ Forces LTR override to be permanent
+ The default way LTR override works is:
+ rootport uses LTR override values provided by BIOS until connected device sends an LTR message, then it will use values from the message
+ This settings allows force override of LTR mechanism. If it's enabled, then:
+ rootport will use LTR override values provided by BIOS forever; LTR messages sent from connected device will be ignored
+ **/
+ UINT8 ForceLtrOverride;
+ UINT8 Reserved[3];
+} PCIE_DEVICE_OVERRIDE;
+
+#pragma pack (pop)
+#endif // _PCIE_CONFIG_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/PcieRp/PciePreMemConfig.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/PcieRp/PciePreMemConfig.h
new file mode 100644
index 0000000000..fe0be3ec12
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/PcieRp/PciePreMemConfig.h
@@ -0,0 +1,36 @@
+/** @file
+ PCIe Config Block PreMem
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _PCIE_PREMEM_CONFIG_H_
+#define _PCIE_PREMEM_CONFIG_H_
+
+
+extern EFI_GUID gPciePreMemConfigGuid;
+
+#pragma pack (push,1)
+
+/**
+ PCIe IMR Config
+**/
+typedef struct {
+ UINT8 ImrEnabled; ///< PCIe IMR. <b>0: Disable</b>; 1: Enable.
+ UINT8 ImrRpLocation; ///< 0: PCH_PCIe; 1: CPU_PCIe. If PCIeImrEnabled is TRUE then this will use to select the Root port location from PCH PCIe or CPU PCIe.Refer PCIE_IMR_ROOT_PORT_LOCATION above
+ UINT16 ImrSize; ///< PCIe IMR size in megabytes
+ UINT8 ImrRpSelection; ///< Index of root port that is selected for PCIe IMR (0 based)
+ UINT8 Rsvd0[3];
+} PCIE_IMR_CONFIG;
+
+/**
+ PCIe Pre-Memory Configuration
+ <b>Revision 1</b>: - Initial version.
+**/
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Offset 0 - 27 Config Block Header
+ PCIE_IMR_CONFIG PcieImr; ///< IMR Configuration
+} PCIE_PREMEM_CONFIG;
+
+#pragma pack (pop)
+#endif // _PCIE_PREMEM_CONFIG_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Pmc/AdrConfig.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Pmc/AdrConfig.h
new file mode 100644
index 0000000000..35ecb53ed2
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Pmc/AdrConfig.h
@@ -0,0 +1,76 @@
+/** @file
+ ADR policy
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _ADR_CONFIG_H_
+#define _ADR_CONFIG_H_
+
+#include <ConfigBlock.h>
+
+extern EFI_GUID gAdrConfigGuid;
+
+#pragma pack (push,1)
+
+
+/**
+ ADR Source Enable
+**/
+typedef union {
+ struct {
+ UINT32 Reserved1 : 1;
+ UINT32 AdrSrcPbo : 1;
+ UINT32 AdrSrcPmcUncErr : 1;
+ UINT32 AdrSrcPchThrm : 1;
+ UINT32 AdrSrcMePbo : 1;
+ UINT32 AdrSrcCpuThrm : 1;
+ UINT32 AdrSrcMegbl : 1;
+ UINT32 AdrSrcLtReset : 1;
+ UINT32 AdrSrcPmcWdt : 1;
+ UINT32 AdrSrcMeWdt : 1;
+ UINT32 AdrSrcPmcFw : 1;
+ UINT32 AdrSrcPchpwrFlr : 1;
+ UINT32 AdrSrcSyspwrFlr : 1;
+ UINT32 Reserved2 : 1;
+ UINT32 AdrSrcMiaUxsErr : 1;
+ UINT32 AdrSrcMiaUxErr : 1;
+ UINT32 AdrSrcCpuThrmWdt : 1;
+ UINT32 AdrSrcMeUncErr : 1;
+ UINT32 AdrSrcAdrGpio : 1;
+ UINT32 AdrSrcOcwdtNoicc : 1;
+ UINT32 AdrSrcOcwdtIcc : 1;
+ UINT32 AdrSrcCseHecUncErr : 1;
+ UINT32 AdrSrcPmcSramUncErr : 1;
+ UINT32 AdrSrcPmcIromParity : 1;
+ UINT32 AdrSrcPmcRfFusaErr : 1;
+ UINT32 Reserved3 : 4;
+ UINT32 AdrSrcPpbrParityErr : 1;
+ UINT32 Reserved4 : 2;
+ } Field;
+ UINT32 Value;
+} ADR_SOURCE_ENABLE;
+
+/**
+ ADR Configuration
+ <b>Revision 1</b>: - Initial version.
+**/
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Config Block Header
+ UINT32 AdrEn : 2; ///< Determine if Adr is enabled - 0: PLATFORM_POR, 1: FORCE_ENABLE, 2: FORCE_DISABLE
+ UINT32 AdrTimerEn : 2; ///< Determine if Adr timer options are enabled - 0: PLATFORM_POR, 1: FORCE_ENABLE, 2: FORCE_DISABLE
+ UINT32 AdrTimer1Val : 8; ///< Determines the Timeout value used for the ADR timer 1. A value of zero bypasses the timer
+ UINT32 AdrMultiplier1Val : 3; ///< Specifies the tick frequency upon which the timer 1 will increment. ADR_TIMER_SCALE should be used to encode values
+ UINT32 AdrTimer2Val : 8; ///< Determines the Timeout value used for the ADR timer 2. A value of zero bypasses the timer
+ UINT32 AdrMultiplier2Val : 3; ///< Specifies the tick frequency upon which the timer 2 will increment. ADR_TIMER_SCALE should be used to encode values
+ UINT32 AdrHostPartitionReset : 2; ///< Determine if Host Partition Reset is enabled - 0: PLATFORM_POR, 1: FORCE_ENABLE, 2: FORCE_DISABLE
+ UINT32 AdrSrcOverride : 1; ///< Check if default ADR sources will be overriten with custom 0: Not overwritten, 1: Overwritten
+ UINT32 AdrPlatAckEn : 2; ///< Determine if Platform Acknowledge is enabled - 0: PLATFORM_POR, 1: FORCE_ENABLE, 2: FORCE_DISABLE
+ UINT32 ReservedBits : 1;
+ ADR_SOURCE_ENABLE AdrSrcSel; ///< Determine which ADR sources are enabled - 0: Enabled, 1: Disabled
+} ADR_CONFIG;
+
+#pragma pack (pop)
+
+#endif // _ADR_CONFIG_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Pmc/PmConfig.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Pmc/PmConfig.h
new file mode 100644
index 0000000000..0a2ae50e6a
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Pmc/PmConfig.h
@@ -0,0 +1,86 @@
+/** @file
+ Power Management policy
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _PM_CONFIG_H_
+#define _PM_CONFIG_H_
+
+#include <ConfigBlock.h>
+
+extern EFI_GUID gPmConfigGuid;
+
+#pragma pack (push,1)
+
+/**
+ Description of Global Reset Trigger/Event Mask register
+**/
+typedef union {
+ struct {
+ UINT32 Reserved1 : 1;
+ UINT32 Pbo : 1;
+ UINT32 PmcUncErr : 1;
+ UINT32 PchThrm : 1;
+ UINT32 MePbo : 1;
+ UINT32 CpuThrm : 1;
+ UINT32 Megbl : 1;
+ UINT32 LtReset : 1;
+ UINT32 PmcWdt : 1;
+ UINT32 MeWdt : 1;
+ UINT32 PmcFw : 1;
+ UINT32 PchpwrFlr : 1;
+ UINT32 SyspwrFlr : 1;
+ UINT32 Reserved2 : 1;
+ UINT32 MiaUxsErr : 1;
+ UINT32 MiaUxErr : 1;
+ UINT32 CpuThrmWdt : 1;
+ UINT32 MeUncErr : 1;
+ UINT32 AdrGpio : 1;
+ UINT32 OcwdtNoicc : 1;
+ UINT32 OcwdtIcc : 1;
+ UINT32 CseHecUncErr : 1;
+ UINT32 PmcSramUncErr : 1;
+ UINT32 PmcIromParity : 1;
+ UINT32 PmcRfFusaErr : 1;
+ UINT32 Reserved3 : 4;
+ UINT32 PpbrParityErr : 1;
+ UINT32 Reserved4 : 2;
+ } Field;
+ UINT32 Value;
+} PMC_GLOBAL_RESET_MASK;
+
+typedef union {
+ struct {
+ UINT32 HostResetTimeout : 1;
+ UINT32 SxEntryTimeout : 1;
+ UINT32 HostRstProm : 1;
+ UINT32 HsmbMsg : 1;
+ UINT32 Pmc3Strike : 1;
+ UINT32 FwGblrstScratch5 : 1;
+ UINT32 PmcDmaTimeout : 1;
+ UINT32 EspiType7 : 1;
+ UINT32 EspiType8 : 1;
+ UINT32 FwGblRstScratch10 : 1;
+ UINT32 FwGblRstScratch11 : 1;
+ UINT32 LpmFwErr : 1;
+ UINT32 BscanMode : 1;
+ UINT32 SlpLvlRspErr : 1;
+ UINT32 FwGblrstScratch15 : 1;
+ UINT32 FwGblrstScratch16 : 1;
+ UINT32 FwGblrstScratch17 : 1;
+ UINT32 FwGblrstScratch18 : 1;
+ UINT32 FwGblrstScratch19 : 1;
+ UINT32 FwGblrstScratch20 : 1;
+ UINT32 FwGblrstScratch21 : 1;
+ UINT32 FwGblrstScratch22 : 1;
+ UINT32 FwGblrstScratch23 : 1;
+ UINT32 Rsvd : 9;
+ } Field;
+ UINT32 Value;
+} PMC_GLOBAL_RESET_MASK1;
+
+
+#pragma pack (pop)
+
+#endif // _PM_CONFIG_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Rtc/RtcConfig.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Rtc/RtcConfig.h
new file mode 100644
index 0000000000..62f8303558
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Rtc/RtcConfig.h
@@ -0,0 +1,37 @@
+/** @file
+ RTC policy
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _RTC_CONFIG_H_
+#define _RTC_CONFIG_H_
+
+extern EFI_GUID gRtcConfigGuid;
+
+#pragma pack (push,1)
+
+/**
+ The RTC_CONFIG block describes the expected configuration of RTC configuration.
+**/
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Config Block Header
+ /**
+ When set, prevents RTC TS (BUC.TS) from being changed.
+ This BILD bit has different function compared to LPC/eSPI, SPI.
+ 0: Disabled; <b>1: Enabled</b>
+ **/
+ UINT32 BiosInterfaceLock : 1;
+ /**
+ When set, bytes 38h-3Fh in the upper 128bytes bank of RTC RAM are locked
+ and cannot be accessed.
+ Writes will be droipped and reads will not return any guaranteed data.
+ 0: Disabled; <b>1: Enabled</b>
+ **/
+ UINT32 MemoryLock : 1;
+ UINT32 RsvdBits0 : 30;
+} RTC_CONFIG;
+
+#pragma pack (pop)
+
+#endif // _RTC_CONFIG_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/SerialIo/SerialIoConfig.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/SerialIo/SerialIoConfig.h
new file mode 100644
index 0000000000..b5c3b21606
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/SerialIo/SerialIoConfig.h
@@ -0,0 +1,33 @@
+/** @file
+ Serial IO policy
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _SERIAL_IO_CONFIG_H_
+#define _SERIAL_IO_CONFIG_H_
+
+extern EFI_GUID gSerialIoConfigGuid;
+
+#include <SerialIoDevices.h>
+
+#pragma pack (push,1)
+
+/**
+ The SERIAL_IO_CONFIG block provides the configurations to set the Serial IO controllers
+
+ <b>Revision 1:</b>
+ - Inital version.
+ <b>Revision 2:</b>
+ - Modified SPI Config to support pinmux functionality.
+**/
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Config Block Header
+ SERIAL_IO_SPI_CONFIG SpiDeviceConfig[PCH_MAX_SERIALIO_SPI_CONTROLLERS]; ///< SPI Configuration
+ SERIAL_IO_I2C_CONFIG I2cDeviceConfig[PCH_MAX_SERIALIO_I2C_CONTROLLERS]; ///< I2C Configuration
+ SERIAL_IO_UART_CONFIG UartDeviceConfig[PCH_MAX_SERIALIO_UART_CONTROLLERS]; ///< UART Configuration
+} SERIAL_IO_CONFIG;
+
+#pragma pack (pop)
+
+#endif // _SERIAL_IO_CONFIG_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/SiConfig.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/SiConfig.h
new file mode 100644
index 0000000000..5b59f08df2
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/SiConfig.h
@@ -0,0 +1,105 @@
+/** @file
+ Si Config Block
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _SI_CONFIG_H_
+#define _SI_CONFIG_H_
+
+#define SI_CONFIG_REVISION 1
+
+extern EFI_GUID gSiConfigGuid;
+
+
+#pragma pack (push,1)
+
+/**
+ The Silicon Policy allows the platform code to publish a set of configuration
+ information that the RC drivers will use to configure the silicon hardware.
+
+ <b>Revision 1</b>: - Initial version.
+**/
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Offset 0 - 27 Config Block Header
+ //
+ // Platform specific common policies that used by several silicon components.
+ //
+ UINT8 CsmFlag; ///< offset 28 CSM status flag.@deprecated.
+ /**
+ This is used to skip the SSID programming in silicon code.
+ When set to TRUE, silicon code will not do any SSID programming and platform code
+ needs to handle that by itself properly.
+ <b>0: FALSE</b>, 1: TRUE
+ **/
+ UINT8 SkipSsidProgramming; ///< offset 29
+ UINT8 RsvdBytes0[2]; ///< offset 30 - 31
+ /**
+ When SkipSsidProgramming is FALSE, silicon code will use this as default value
+ to program the SVID for all internal devices.
+ <b>0: use silicon default SVID 0x8086 </b>, Non-zero: use customized SVID.
+ **/
+ UINT16 CustomizedSvid; ///< offset 32 - 33
+ /**
+ When SkipSsidProgramming is FALSE, silicon code will use this as default value
+ to program the Sid for all internal devices.
+ <b>0: use silicon default SSID 0x7270 </b>, Non-zero: use customized SSID.
+ **/
+ UINT16 CustomizedSsid; ///< offset 34 - 35
+ UINT32 *SsidTablePtr; ///< offset 36 - 39
+ /**
+ Number of valid enties in SsidTablePtr.
+ This is valid when SkipSsidProgramming is FALSE;
+ <b>Default is 0.</b>
+ **/
+ UINT16 NumberOfSsidTableEntry; ///< offset 40 - 41
+ UINT8 RsvdBytes1[2]; ///< offset 42 - 43
+ /**
+ This is used to skip setting BIOS_DONE MSR during firmware update boot mode.
+ When set to TRUE and boot mode is BOOT_ON_FLASH_UPDATE,
+ skip setting BIOS_DONE MSR at EndofPei.
+ <b>0: FALSE</b>, 1: TRUE
+ **/
+ UINT8 SkipBiosDoneWhenFwUpdate; ///< Offset 44
+ UINT8 RsvdBytes2[3]; ///< Offset 45 - 47
+} SI_CONFIG;
+
+#pragma pack (pop)
+
+
+///
+/// Subsystem Vendor ID / Subsystem ID
+///
+typedef struct {
+ UINT16 SubSystemVendorId;
+ UINT16 SubSystemId;
+} SVID_SID_VALUE;
+
+//
+// Below is to match PCI_SEGMENT_LIB_ADDRESS () which can directly send to PciSegmentRead/Write functions.
+//
+typedef struct {
+ union {
+ struct {
+ UINT32 Register:12;
+ UINT32 Function:3;
+ UINT32 Device:5;
+ UINT32 Bus:8;
+ UINT32 Reserved1:4;
+ UINT32 Segment:16;
+ UINT32 Reserved2:16;
+ } Bits;
+ UINT64 SegBusDevFuncRegister;
+ } Address;
+ SVID_SID_VALUE SvidSidValue;
+ UINT32 Reserved;
+} SVID_SID_INIT_ENTRY;
+
+
+typedef struct {
+ UINT32 SkipBus;
+ UINT32 SkipDevice;
+ UINT32 SkipFunction;
+} SVID_SID_SKIP_TABLE;
+
+#endif // _SI_CONFIG_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/SiPreMemConfig.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/SiPreMemConfig.h
new file mode 100644
index 0000000000..584a0d4169
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/SiPreMemConfig.h
@@ -0,0 +1,63 @@
+/** @file
+ Si Config Block PreMem
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _SI_PREMEM_CONFIG_H_
+#define _SI_PREMEM_CONFIG_H_
+
+#define SI_PREMEM_CONFIG_REVISION 1
+
+extern EFI_GUID gSiPreMemConfigGuid;
+
+typedef enum {
+ ProbeTypeDisabled = 0x00,
+ ProbeTypeDciOob = 0x02,
+ ProbeType2WireDciOob = 0x06,
+ ProbeTypeManual = 0x07,
+ ProbeTypeMax
+} PLATFORM_DEBUG_CONSENT_PROBE_TYPE;
+
+#pragma pack (push,1)
+/**
+ The Silicon PreMem Policy allows the platform code to publish a set of configuration
+ information that the RC drivers will use to configure the silicon hardware.
+
+ <b>Revision 1</b>:
+ - Initial version.
+**/
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Offset 0 - 27 Config Block Header
+ /**
+ Platform Debug Consent
+ As a main switch to enable platform debug capability and relevant settings with specified probe type.
+ Manual: Do not use Platform Debug Consent to override other debug-relevant policies, but the user must set each debug option manually, aimed at advanced users.
+
+ PDC-dependent policies are listed:
+ DciPreMemConfig->DciEn
+ CpuTraceHubConfig->EnableMode
+ CpuTraceHubConfig->CpuTraceHubMemReg0Size
+ CpuTraceHubConfig->CpuTraceHubMemReg1Size
+ PchTraceHubPreMemConfig->EnableMode
+ PchTraceHubPreMemConfig->MemReg0Size
+ PchTraceHubPreMemConfig->MemReg1Size
+
+ Note: DCI OOB (aka BSSB) uses CCA probe.
+ Refer to definition of PLATFORM_DEBUG_CONSENT_PROBE_TYPE
+ <b>0:Disabled</b>; 2:DCI OOB (All + TraceHubs); 6:2-wire DCI OOB (Low power); 7:Manual
+ **/
+ UINT32 PlatformDebugConsent : 4; /// offset 28 - 31
+ UINT32 RsvdBits : 28;
+ /**
+ This is used to skip override boot mode during firmware update boot mode.
+ When set to TRUE and boot mode is BOOT_ON_FLASH_UPDATE,
+ skip setting boot mode to BOOT_WITH_FULL_CONFIGURATION in PEI memory init.
+ <b>0: FALSE</b>, 1: TRUE
+ **/
+ UINT8 SkipOverrideBootModeWhenFwUpdate; /// offset 32
+ UINT8 RsvdBytes[3]; /// offset 33 - 35
+} SI_PREMEM_CONFIG;
+
+#pragma pack (pop)
+#endif // _SI_PREMEM_CONFIG_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Smbus/SmbusConfig.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Smbus/SmbusConfig.h
new file mode 100644
index 0000000000..2fc724552b
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Smbus/SmbusConfig.h
@@ -0,0 +1,49 @@
+/** @file
+ Smbus policy
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _SMBUS_CONFIG_H_
+#define _SMBUS_CONFIG_H_
+
+extern EFI_GUID gSmbusPreMemConfigGuid;
+
+#pragma pack (push,1)
+
+#define PCH_MAX_SMBUS_RESERVED_ADDRESS 128
+
+///
+/// The SMBUS_CONFIG block lists the reserved addresses for non-ARP capable devices in the platform.
+///
+typedef struct {
+ /**
+ Revision 1: Init version
+ **/
+ CONFIG_BLOCK_HEADER Header; ///< Config Block Header
+ /**
+ This member describes whether or not the SMBus controller of PCH should be enabled.
+ 0: Disable; <b>1: Enable</b>.
+ **/
+ UINT32 Enable : 1;
+ UINT32 ArpEnable : 1; ///< Enable SMBus ARP support, <b>0: Disable</b>; 1: Enable.
+ UINT32 DynamicPowerGating : 1; ///< <b>(Test)</b> <b>Disable</b> or Enable Smbus dynamic power gating.
+ ///
+ /// <b>(Test)</b> SPD Write Disable, 0: leave SPD Write Disable bit; <b>1: set SPD Write Disable bit.</b>
+ /// For security recommendations, SPD write disable bit must be set.
+ ///
+ UINT32 SpdWriteDisable : 1;
+ UINT32 SmbAlertEnable : 1; ///< Enable SMBus Alert pin (SMBALERT#). 0: <b>Disabled<b>, 1: Enabled.
+ UINT32 RsvdBits0 : 27; ///< Reserved bits
+ UINT16 SmbusIoBase; ///< SMBUS Base Address (IO space). Default is <b>0xEFA0</b>.
+ UINT8 Rsvd0; ///< Reserved bytes
+ UINT8 NumRsvdSmbusAddresses; ///< The number of elements in the RsvdSmbusAddressTable.
+ /**
+ Array of addresses reserved for non-ARP-capable SMBus devices.
+ **/
+ UINT8 RsvdSmbusAddressTable[PCH_MAX_SMBUS_RESERVED_ADDRESS];
+} PCH_SMBUS_PREMEM_CONFIG;
+
+#pragma pack (pop)
+
+#endif // _SMBUS_CONFIG_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Spi/FlashProtectionConfig.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Spi/FlashProtectionConfig.h
new file mode 100644
index 0000000000..45dc538064
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Spi/FlashProtectionConfig.h
@@ -0,0 +1,54 @@
+/** @file
+ FlashProtection policy
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _FLASH_PROTECTION_CONFIG_H_
+#define _FLASH_PROTECTION_CONFIG_H_
+
+extern EFI_GUID gFlashProtectionConfigGuid;
+
+#pragma pack (push,1)
+
+//
+// Flash Protection Range Register
+//
+#define PCH_FLASH_PROTECTED_RANGES 5
+
+/**
+ Protected Flash Range
+**/
+typedef struct {
+ UINT32 WriteProtectionEnable : 1; ///< Write or erase is blocked by hardware. <b>0: Disable</b>; 1: Enable.
+ UINT32 ReadProtectionEnable : 1; ///< Read is blocked by hardware. <b>0: Disable</b>; 1: Enable.
+ UINT32 RsvdBits : 30; ///< Reserved
+ /**
+ The address of the upper limit of protection
+ This is a left shifted address by 12 bits with address bits 11:0 are assumed to be FFFh for limit comparison
+ **/
+ UINT16 ProtectedRangeLimit;
+ /**
+ The address of the upper limit of protection
+ This is a left shifted address by 12 bits with address bits 11:0 are assumed to be 0
+ **/
+ UINT16 ProtectedRangeBase;
+} PROTECTED_RANGE;
+
+/**
+ The PCH provides a method for blocking writes and reads to specific ranges
+ in the SPI flash when the Protected Ranges are enabled.
+ PROTECTED_RANGE is used to specify if flash protection are enabled,
+ the write protection enable bit and the read protection enable bit,
+ and to specify the upper limit and lower base for each register
+ Platform code is responsible to get the range base by PchGetSpiRegionAddresses routine,
+ and set the limit and base accordingly.
+**/
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Config Block Header
+ PROTECTED_RANGE ProtectRange[PCH_FLASH_PROTECTED_RANGES]; ///< Protected Flash Ranges
+} PCH_FLASH_PROTECTION_CONFIG;
+
+#pragma pack (pop)
+
+#endif // _FLASH_PROTECTION_CONFIG_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Tcss/TcssPeiConfig.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Tcss/TcssPeiConfig.h
new file mode 100644
index 0000000000..95bcaaa951
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Tcss/TcssPeiConfig.h
@@ -0,0 +1,71 @@
+/** @file
+ TCSS PEI policy
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _TCSS_PEI_CONFIG_H_
+#define _TCSS_PEI_CONFIG_H_
+
+#include <ConfigBlock.h>
+
+extern EFI_GUID gTcssPeiConfigGuid;
+
+#pragma pack (push,1)
+
+
+#define MAX_IOM_AUX_BIAS_COUNT 4
+
+///
+/// The IOM_AUX_ORI_PAD_CONFIG describes IOM TypeC port map GPIO pin.
+/// Those GPIO setting for DP Aux Orientation Bias Control when the TypeC port didn't have re-timer.
+/// IOM needs know Pull-Up and Pull-Down pin for Bias control
+///
+typedef struct {
+ UINT32 GpioPullN; ///< GPIO Pull Up Ping number that is for IOM indecate the pull up pin from TypeC port.
+ UINT32 GpioPullP; ///< GPIO Pull Down Ping number that is for IOM indecate the pull down pin from TypeC port.
+} IOM_AUX_ORI_PAD_CONFIG;
+
+///
+/// The IOM_EC_INTERFACE_CONFIG block describes interaction between BIOS and IOM-EC.
+///
+
+typedef struct {
+ UINT32 VccSt; ///< IOM VCCST request. (Not equal to actual VCCST value)
+ UINT32 UsbOverride; ///< IOM to override USB connection.
+ UINT32 D3ColdEnable; ///< Enable/disable D3 Cold support in TCSS
+ UINT32 D3HotEnable; ///< Enable/disable D3 Hot support in TCSS
+} IOM_INTERFACE_CONFIG;
+
+///
+/// The PMC_INTERFACE_CONFIG block describes interaction between BIOS and PMC
+///
+typedef struct {
+ UINT8 PmcPdEnable; ///< PMC PD Solution Enable
+ UINT8 Rsvd[3];
+} PMC_INTERFACE_CONFIG;
+
+///
+/// The TCSS_IOM_PEI_CONFIG block describes IOM Aux/HSL override settings for TCSS.
+///
+typedef struct {
+ UINT16 AuxOri; ///< Bits defining value for IOM Aux Orientation Register
+ UINT16 HslOri; ///< Bits defining value for IOM HSL Orientation Register
+} TCSS_IOM_ORI_OVERRIDE;
+
+///
+/// The TCSS_IOM_PEI_CONFIG block describes IOM settings for TCSS.
+///
+typedef struct {
+ IOM_AUX_ORI_PAD_CONFIG IomAuxPortPad[MAX_IOM_AUX_BIAS_COUNT]; ///< The IOM_AUX_ORI_BIAS_CTRL port config setting.
+ TCSS_IOM_ORI_OVERRIDE IomOverrides;
+ IOM_INTERFACE_CONFIG IomInterface; ///< Config settings are BIOS <-> IOM interface.
+ PMC_INTERFACE_CONFIG PmcInterface; ///< Config settings for BIOS <-> PMC interface
+ UINT8 TcStateLimit; ///< Tcss C-State deep stage
+ UINT8 Reserved[3]; ///< Reserved bytes for future use
+} TCSS_IOM_PEI_CONFIG;
+
+
+#pragma pack (pop)
+
+#endif /* _TCSS_PEI_CONFIG_H_ */
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Vmd/VmdPeiConfig.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Vmd/VmdPeiConfig.h
new file mode 100644
index 0000000000..37e6439abb
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Vmd/VmdPeiConfig.h
@@ -0,0 +1,60 @@
+/** @file
+ VMD PEI policy
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _VMD_PEI_CONFIG_H_
+#define _VMD_PEI_CONFIG_H_
+
+#include <ConfigBlock.h>
+
+#pragma pack (push,1)
+
+#define VMD_MAX_DEVICES 31
+
+typedef struct {
+ UINT8 RpBus;
+ UINT8 RpDevice;
+ UINT8 RpFunction;
+ UINT8 RpEnable;
+} RP_BDF_DATA;
+
+/**
+ This configuration block is to configure VMD related variables used in PostMem PEI.
+ If VMD Device is not supported, all policies can be ignored.
+ <b>Revision 1</b>:
+ - Initial version.
+ <b>Revision 2</b>:
+ - Deprecated VmdPortAEnable, VmdPortBEnable, VmdPortCEnable, VmdPortDEnable.
+ - Added VmdPortEnable[VMD_MAX_DEVICES] and structure to hold Vmd EFI Variable details.
+ (Added B/D/F fields along with Port Enable for up to max 31 devices).
+ <b>Revision 3</b>:
+ Added policy to get the Bar values from platform PCD.
+ <b>Revision 4</b>: Added VmdGlobalMapping to map all the storage devices under VMD
+**/
+
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Block Header
+ UINT8 VmdEnable; ///< Offset 28 This field used to enable VMD controller 1=Enable <b>0=Disable(default)</b>
+ UINT8 VmdPortAEnable; /// Deprecated < Offset 29 This field used to enable VMD portA Support 1=Enable and 0=Disable (default)
+ UINT8 VmdPortBEnable; /// Deprecated < Offset 30 This field used to enable VMD portB Support 1=Enable and 0=Disable (default)
+ UINT8 VmdPortCEnable; /// Deprecated < Offset 31 This field used to enable VMD portC Support 1=Enable and 0=Disable (default)
+ UINT8 VmdPortDEnable; /// Deprecated < Offset 32 This field used to enable VMD portD Support 1=Enable and 0=Disable (default)
+ UINT8 VmdCfgBarSize; ///< Offset 33 This is used to set the VMD Config Bar Size. <b>25(32MB)</b>
+ UINT8 VmdCfgBarAttr; ///< Offset 34 This is used to set VMD Config Bar Attributes 0: VMD_32BIT_NONPREFETCH, 1: VMD_64BIT_PREFETCH, <b>2: VMD_64BIT_NONPREFETCH(Default)</b>
+ UINT8 VmdMemBarSize1; ///< Offset 35 This is used to set the VMD Mem Bar1 size. <b>25 (32MB)</b>.
+ UINT8 VmdMemBar1Attr; ///< Offset 36 This is used to set VMD Mem Bar1 Attributes <b>0: VMD_32BIT_NONPREFETCH(Default) </b> 1: VMD_64BIT_NONPREFETCH, 2: VMD_64BIT_PREFETCH
+ UINT8 VmdMemBarSize2; ///< Offset 37 This is used to set the VMD Mem Bar2 size. <b>20(1MB)</b>.
+ UINT8 VmdMemBar2Attr; ///< Offset 38 This is used to set VMD Mem Bar2 Attributes 0: VMD_32BIT_NONPREFETCH <b>1: VMD_64BIT_NONPREFETCH(Default)</b>, 2: VMD_64BIT_PREFETCH
+ UINT8 VmdGlobalMapping; ///< Offset 39 This field used to enable Global Mapping 1=Enable <b>0=Disable(default)</b>
+ RP_BDF_DATA VmdPortEnable[VMD_MAX_DEVICES]; ///< Offset 40 to 163 This field used to to store b/d/f for each root port along with enable Support 1=Enable <b>0=Disable (default)</b>
+ VOID *VmdVariablePtr; /// This config block will be updated as per the EFI variable.
+ UINT32 VmdCfgBarBase; /// Temp Address VMD CFG BAR Default is <b>0xA0000000</b>
+ UINT32 VmdMemBar1Base; /// Temp Address VMD CFG BAR Default is <b>0xA2000000</b>
+ UINT32 VmdMemBar2Base; /// Temp Address VMD CFG BAR Default is <b>0xA4000000</b>
+} VMD_PEI_CONFIG;
+
+#pragma pack (pop)
+
+#endif /* _VMD_PEI_PREMEM_CONFIG_H_ */
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Wdt/WatchDogConfig.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Wdt/WatchDogConfig.h
new file mode 100644
index 0000000000..ad17488ecc
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock/Wdt/WatchDogConfig.h
@@ -0,0 +1,30 @@
+/** @file
+ WatchDog policy
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _WATCH_DOG_CONFIG_H_
+#define _WATCH_DOG_CONFIG_H_
+
+extern EFI_GUID gWatchDogPreMemConfigGuid;
+
+#pragma pack (push,1)
+
+/**
+ This policy clears status bits and disable watchdog, then lock the
+ WDT registers.
+ while WDT is designed to be disabled and locked by Policy,
+ bios should not enable WDT by WDT PPI. In such case, bios shows the
+ warning message but not disable and lock WDT register to make sure
+ WDT event trigger correctly.
+**/
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Config Block Header
+ UINT32 DisableAndLock : 1; ///< <b>(Test)</b> Set 1 to clear WDT status, then disable and lock WDT registers. <b>0: Disable</b>; 1: Enable.
+ UINT32 RsvdBits : 31;
+} PCH_WDT_PREMEM_CONFIG;
+
+#pragma pack (pop)
+
+#endif // _WATCH_DOG_CONFIG_H_
--
2.36.1.windows.1
-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#108742): https://edk2.groups.io/g/devel/message/108742
Mute This Topic: https://groups.io/mt/101373949/7686176
Group Owner: devel+owner@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [rebecca@openfw.io]
-=-=-=-=-=-=-=-=-=-=-=-
^ permalink raw reply related [flat|nested] 41+ messages in thread
* Re: [edk2-devel] [PATCH v2 06/10] AlderlakeSiliconPkg/Include: Add Library, Pins, Ppi Includes
2023-09-15 4:45 ` [edk2-devel] [PATCH v2 06/10] AlderlakeSiliconPkg/Include: Add Library, Pins, Ppi Includes Saloni Kasbekar
2023-09-15 5:43 ` Chaganty, Rangasai V
@ 2023-09-15 23:56 ` Nate DeSimone
1 sibling, 0 replies; 41+ messages in thread
From: Nate DeSimone @ 2023-09-15 23:56 UTC (permalink / raw)
To: Kasbekar, Saloni, devel@edk2.groups.io
Cc: Chaganty, Rangasai V, Chuang, Rosen
Acked-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
-----Original Message-----
From: Kasbekar, Saloni <saloni.kasbekar@intel.com>
Sent: Thursday, September 14, 2023 9:46 PM
To: devel@edk2.groups.io
Cc: Kasbekar, Saloni <saloni.kasbekar@intel.com>; Chaganty, Rangasai V <rangasai.v.chaganty@intel.com>; Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>; Chuang, Rosen <rosen.chuang@intel.com>
Subject: [PATCH v2 06/10] AlderlakeSiliconPkg/Include: Add Library, Pins, Ppi Includes
Adds the following Includes:
- Include/Library
- Include/Pins
- Include/Ppi
Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Rosen Chuang <rosen.chuang@intel.com>
Signed-off-by: Saloni Kasbekar <saloni.kasbekar@intel.com>
---
.../Include/Library/ConfigBlockLib.h | 64 +++
.../Include/Library/EspiLib.h | 34 ++
.../Include/Library/GpioConfig.h | 372 ++++++++++++++++++
.../Include/Library/GpioLib.h | 174 ++++++++
.../Include/Library/GpioNativeLib.h | 135 +++++++
.../Include/Library/GraphicsInfoLib.h | 46 +++
.../Include/Library/MmPciLib.h | 27 ++
.../Include/Library/PchPcieRpLib.h | 41 ++
.../Include/Library/PchPcrLib.h | 221 +++++++++++
.../Library/PeiDxeSmmReserveMmio64SizeLib.h | 21 +
.../Include/Library/PeiSiPolicyUpdateLib.h | 154 ++++++++
.../Include/Library/PmcLib.h | 40 ++
.../Include/Library/ResetSystemLib.h | 68 ++++
.../Include/Library/SecPlatformLib.h | 81 ++++
.../Include/Library/SiConfigBlockLib.h | 56 +++
.../Include/Library/SiPolicyLib.h | 39 ++
.../Include/Library/SpiLib.h | 21 +
.../Include/Pins/GpioPinsVer2Lp.h | 36 ++
.../Include/Ppi/FspmArchConfigPpi.h | 32 ++
.../Include/Ppi/PeiPreMemSiDefaultPolicy.h | 33 ++
.../Include/Ppi/PeiSiDefaultPolicy.h | 33 ++
.../AlderlakeSiliconPkg/Include/Ppi/Spi.h | 29 ++
.../AlderlakeSiliconPkg/Include/Ppi/Wdt.h | 22 ++
23 files changed, 1779 insertions(+)
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Library/ConfigBlockLib.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Library/EspiLib.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Library/GpioConfig.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Library/GpioLib.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Library/GpioNativeLib.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Library/GraphicsInfoLib.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Library/MmPciLib.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Library/PchPcieRpLib.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Library/PchPcrLib.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Library/PeiDxeSmmReserveMmio64SizeLib.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Library/PeiSiPolicyUpdateLib.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Library/PmcLib.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Library/ResetSystemLib.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Library/SecPlatformLib.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Library/SiConfigBlockLib.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Library/SiPolicyLib.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Library/SpiLib.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Pins/GpioPinsVer2Lp.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Ppi/FspmArchConfigPpi.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Ppi/PeiPreMemSiDefaultPolicy.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Ppi/PeiSiDefaultPolicy.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Ppi/Spi.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Ppi/Wdt.h
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/ConfigBlockLib.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/ConfigBlockLib.h
new file mode 100644
index 0000000000..d9966c76e9
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/ConfigBlockLib.h
@@ -0,0 +1,64 @@
+/** @file
+ Header file for Config Block Lib implementation
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _CONFIG_BLOCK_LIB_H_
+#define _CONFIG_BLOCK_LIB_H_
+
+/**
+ Create config block table
+
+ @param[in] TotalSize - Max size to be allocated for the Config Block Table
+ @param[out] ConfigBlockTableAddress - On return, points to a pointer to the beginning of Config Block Table Address
+
+ @retval EFI_INVALID_PARAMETER - Invalid Parameter
+ @retval EFI_OUT_OF_RESOURCES - Out of resources
+ @retval EFI_SUCCESS - Successfully created Config Block Table at ConfigBlockTableAddress
+**/
+EFI_STATUS
+EFIAPI
+CreateConfigBlockTable (
+ IN UINT16 TotalSize,
+ OUT VOID **ConfigBlockTableAddress
+ );
+
+/**
+ Add config block into config block table structure
+
+ @param[in] ConfigBlockTableAddress - A pointer to the beginning of Config Block Table Address
+ @param[out] ConfigBlockAddress - On return, points to a pointer to the beginning of Config Block Address
+
+ @retval EFI_OUT_OF_RESOURCES - Config Block Table is full and cannot add new Config Block or
+ Config Block Offset Table is full and cannot add new Config Block.
+ @retval EFI_SUCCESS - Successfully added Config Block
+**/
+EFI_STATUS
+EFIAPI
+AddConfigBlock (
+ IN VOID *ConfigBlockTableAddress,
+ OUT VOID **ConfigBlockAddress
+ );
+
+/**
+ Retrieve a specific Config Block data by GUID
+
+ @param[in] ConfigBlockTableAddress - A pointer to the beginning of Config Block Table Address
+ @param[in] ConfigBlockGuid - A pointer to the GUID uses to search specific Config Block
+ @param[out] ConfigBlockAddress - On return, points to a pointer to the beginning of Config Block Address
+
+ @retval EFI_NOT_FOUND - Could not find the Config Block
+ @retval EFI_SUCCESS - Config Block found and return
+**/
+EFI_STATUS
+EFIAPI
+GetConfigBlock (
+ IN VOID *ConfigBlockTableAddress,
+ IN EFI_GUID *ConfigBlockGuid,
+ OUT VOID **ConfigBlockAddress
+ );
+
+#endif // _CONFIG_BLOCK_LIB_H_
+
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/EspiLib.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/EspiLib.h
new file mode 100644
index 0000000000..3c37def986
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/EspiLib.h
@@ -0,0 +1,34 @@
+/** @file
+ Header file for PchEspiLib.
+ All function in this library is available for PEI, DXE, and SMM,
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _ESPI_LIB_H_
+#define _ESPI_LIB_H_
+
+/**
+ Checks if there's second device connected under CS#1
+
+ @retval TRUE There's second device
+ @retval FALSE There's no second device
+**/
+BOOLEAN
+IsEspiSecondSlaveSupported (
+ VOID
+ );
+
+/**
+ Is eSPI enabled in strap.
+
+ @retval TRUE Espi is enabled in strap
+ @retval FALSE Espi is disabled in strap
+**/
+BOOLEAN
+IsEspiEnabled (
+ VOID
+ );
+
+#endif // _ESPI_LIB_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/GpioConfig.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/GpioConfig.h
new file mode 100644
index 0000000000..43c0da46d7
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/GpioConfig.h
@@ -0,0 +1,372 @@
+/** @file
+ Header file for GpioConfig structure used by GPIO library.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _GPIO_CONFIG_H_
+#define _GPIO_CONFIG_H_
+
+#pragma pack(push, 1)
+
+///
+/// For any GpioPad usage in code use GPIO_PAD type
+///
+typedef UINT32 GPIO_PAD;
+
+///
+/// GpioPad with additional native function information.
+/// This type is used to represent signal muxing alternatives. Platform will provide such value to
+/// identify muxing selection for given signal on a specific SOC.
+/// Please refer to the board layout
+///
+typedef UINT32 GPIO_NATIVE_PAD;
+
+
+///
+/// For any GpioGroup usage in code use GPIO_GROUP type
+///
+typedef UINT32 GPIO_GROUP;
+
+/**
+ GPIO configuration structure used for pin programming.
+ Structure contains fields that can be used to configure pad.
+**/
+typedef struct {
+ /**
+ Pad Mode
+ Pad can be set as GPIO or one of its native functions.
+ When in native mode setting Direction (except Inversion), OutputState,
+ InterruptConfig, Host Software Pad Ownership and OutputStateLock are unnecessary.
+ Refer to definition of GPIO_PAD_MODE.
+ Refer to EDS for each native mode according to the pad.
+ **/
+ UINT32 PadMode : 5;
+ /**
+ Host Software Pad Ownership
+ Set pad to ACPI mode or GPIO Driver Mode.
+ Refer to definition of GPIO_HOSTSW_OWN.
+ **/
+ UINT32 HostSoftPadOwn : 2;
+ /**
+ GPIO Direction
+ Can choose between In, In with inversion, Out, both In and Out, both In with inversion and out or disabling both.
+ Refer to definition of GPIO_DIRECTION for supported settings.
+ **/
+ UINT32 Direction : 6;
+ /**
+ Output State
+ Set Pad output value.
+ Refer to definition of GPIO_OUTPUT_STATE for supported settings.
+ This setting takes place when output is enabled.
+ **/
+ UINT32 OutputState : 2;
+ /**
+ GPIO Interrupt Configuration
+ Set Pad to cause one of interrupts (IOxAPIC/SCI/SMI/NMI).
+ This setting is applicable only if GPIO is in GpioMode with input enabled.
+ Refer to definition of GPIO_INT_CONFIG for supported settings.
+ **/
+ UINT32 InterruptConfig : 9;
+ /**
+ GPIO Power Configuration.
+ This setting controls Pad Reset Configuration.
+ Refer to definition of GPIO_RESET_CONFIG for supported settings.
+ **/
+ UINT32 PowerConfig : 8;
+ /**
+ GPIO Electrical Configuration
+ This setting controls pads termination.
+ Refer to definition of GPIO_ELECTRICAL_CONFIG for supported settings.
+ **/
+ UINT32 ElectricalConfig : 9;
+ /**
+ GPIO Lock Configuration
+ This setting controls pads lock.
+ Refer to definition of GPIO_LOCK_CONFIG for supported settings.
+ **/
+ UINT32 LockConfig : 4;
+ /**
+ Additional GPIO configuration
+ Refer to definition of GPIO_OTHER_CONFIG for supported settings.
+ **/
+ UINT32 OtherSettings : 9;
+
+ /**
+ Virtual GPIO eSPI Chip Select configuration
+ This setting selects between CS0 and CS1.
+ Refer to definition of VGPIO_CS_CONFIG for supported settings.
+ **/
+ UINT32 VgpioCs : 2;
+
+ UINT32 RsvdBits : 8; ///< Reserved bits for future extension
+} GPIO_CONFIG;
+
+
+typedef enum {
+ GpioHardwareDefault = 0x0 ///< Leave setting unmodified
+} GPIO_HARDWARE_DEFAULT;
+
+/**
+ GPIO Pad Mode
+ Refer to GPIO documentation on native functions available for certain pad.
+ If GPIO is set to one of NativeX modes then following settings are not applicable
+ and can be skipped:
+ - Interrupt related settings
+ - Host Software Ownership
+ - Output/Input enabling/disabling
+ - Output lock
+**/
+typedef enum {
+ GpioPadModeHwDefault = 0x0,
+ GpioPadModeGpio = 0x1,
+ GpioPadModeNative1 = 0x3,
+ GpioPadModeNative2 = 0x5,
+ GpioPadModeNative3 = 0x7,
+ GpioPadModeNative4 = 0x9,
+ GpioPadModeNative5 = 0xB,
+ GpioPadModeNative6 = 0xD,
+ GpioPadModeNative7 = 0xF
+} GPIO_PAD_MODE;
+
+/**
+ Host Software Pad Ownership modes
+ This setting affects GPIO interrupt status registers. Depending on chosen ownership
+ some GPIO Interrupt status register get updated and other masked.
+ Please refer to EDS for HOSTSW_OWN register description.
+**/
+typedef enum {
+ GpioHostOwnDefault = 0x0, ///< Leave ownership value unmodified
+ /**
+ Set HOST ownership to ACPI.
+ Use this setting if pad is not going to be used by GPIO OS driver.
+ If GPIO is configured to generate SCI/SMI/NMI then this setting must be
+ used for interrupts to work
+ **/
+ GpioHostOwnAcpi = 0x1,
+ /**
+ Set HOST ownership to GPIO Driver mode.
+ Use this setting only if GPIO pad should be controlled by GPIO OS Driver.
+ GPIO OS Driver will be able to control the pad if appropriate entry in
+ ACPI exists (refer to ACPI specification for GpioIo and GpioInt descriptors)
+ **/
+ GpioHostOwnGpio = 0x3
+} GPIO_HOSTSW_OWN;
+
+///
+/// GPIO Direction
+///
+typedef enum {
+ GpioDirDefault = 0x0, ///< Leave pad direction setting unmodified
+ GpioDirInOut = (0x1 | (0x1 << 3)), ///< Set pad for both output and input
+ GpioDirInInvOut = (0x1 | (0x3 << 3)), ///< Set pad for both output and input with inversion
+ GpioDirIn = (0x3 | (0x1 << 3)), ///< Set pad for input only
+ GpioDirInInv = (0x3 | (0x3 << 3)), ///< Set pad for input with inversion
+ GpioDirOut = 0x5, ///< Set pad for output only
+ GpioDirNone = 0x7 ///< Disable both output and input
+} GPIO_DIRECTION;
+
+/**
+ GPIO Output State
+ This field is relevant only if output is enabled
+**/
+typedef enum {
+ GpioOutDefault = 0x0, ///< Leave output value unmodified
+ GpioOutLow = 0x1, ///< Set output to low
+ GpioOutHigh = 0x3 ///< Set output to high
+} GPIO_OUTPUT_STATE;
+
+/**
+ GPIO interrupt configuration
+ This setting is applicable only if pad is in GPIO mode and has input enabled.
+ GPIO_INT_CONFIG allows to choose which interrupt is generated (IOxAPIC/SCI/SMI/NMI)
+ and how it is triggered (edge or level). Refer to PADCFG_DW0 register description in
+ EDS for details on this settings.
+ Field from GpioIntNmi to GpioIntApic can be OR'ed with GpioIntLevel to GpioIntBothEdge
+ to describe an interrupt e.g. GpioIntApic | GpioIntLevel
+ If GPIO is set to cause an SCI then also GPI_GPE_EN is enabled for this pad.
+ If GPIO is set to cause an NMI then also GPI_NMI_EN is enabled for this pad.
+ Not all GPIO are capable of generating an SMI or NMI interrupt.
+ When routing GPIO to cause an IOxAPIC interrupt care must be taken, as this
+ interrupt cannot be shared and its IRQn number is not configurable.
+ Refer to EDS for GPIO pads IRQ numbers (PADCFG_DW1.IntSel)
+ If GPIO is under GPIO OS driver control and appropriate ACPI GpioInt descriptor
+ exist then use only trigger type setting (from GpioIntLevel to GpioIntBothEdge).
+ This type of GPIO Driver interrupt doesn't have any additional routing setting
+ required to be set by BIOS. Interrupt is handled by GPIO OS Driver.
+**/
+
+typedef enum {
+ GpioIntDefault = 0x0, ///< Leave value of interrupt routing unmodified
+ GpioIntDis = 0x1, ///< Disable IOxAPIC/SCI/SMI/NMI interrupt generation
+ GpioIntNmi = 0x3, ///< Enable NMI interrupt only
+ GpioIntSmi = 0x5, ///< Enable SMI interrupt only
+ GpioIntSci = 0x9, ///< Enable SCI interrupt only
+ GpioIntApic = 0x11, ///< Enable IOxAPIC interrupt only
+ GpioIntLevel = (0x1 << 5), ///< Set interrupt as level triggered
+ GpioIntEdge = (0x3 << 5), ///< Set interrupt as edge triggered (type of edge depends on input inversion)
+ GpioIntLvlEdgDis = (0x5 << 5), ///< Disable interrupt trigger
+ GpioIntBothEdge = (0x7 << 5) ///< Set interrupt as both edge triggered
+} GPIO_INT_CONFIG;
+
+#define B_GPIO_INT_CONFIG_INT_SOURCE_MASK 0x1F ///< Mask for GPIO_INT_CONFIG for interrupt source
+#define B_GPIO_INT_CONFIG_INT_TYPE_MASK 0xE0 ///< Mask for GPIO_INT_CONFIG for interrupt type
+
+/**
+ GPIO Power Configuration
+ GPIO_RESET_CONFIG allows to set GPIO Reset type (PADCFG_DW0.PadRstCfg) which will
+ be used to reset certain GPIO settings.
+ Refer to EDS for settings that are controllable by PadRstCfg.
+**/
+typedef enum {
+ GpioResetDefault = 0x00, ///< Leave value of pad reset unmodified
+ /**
+ Resume Reset (RSMRST)
+ GPP: PadRstCfg = 00b = "Powergood"
+ GPD: PadRstCfg = 11b = "Resume Reset"
+ Pad setting will reset on:
+ - DeepSx transition
+ - G3
+ Pad settings will not reset on:
+ - S3/S4/S5 transition
+ - Warm/Cold/Global reset
+ **/
+ GpioResumeReset = 0x01,
+ /**
+ Host Deep Reset
+ PadRstCfg = 01b = "Deep GPIO Reset"
+ Pad settings will reset on:
+ - Warm/Cold/Global reset
+ - DeepSx transition
+ - G3
+ Pad settings will not reset on:
+ - S3/S4/S5 transition
+ **/
+ GpioHostDeepReset = 0x03,
+ /**
+ Platform Reset (PLTRST)
+ PadRstCfg = 10b = "GPIO Reset"
+ Pad settings will reset on:
+ - S3/S4/S5 transition
+ - Warm/Cold/Global reset
+ - DeepSx transition
+ - G3
+ **/
+ GpioPlatformReset = 0x05,
+ /**
+ Deep Sleep Well Reset (DSW_PWROK)
+ GPP: not applicable
+ GPD: PadRstCfg = 00b = "Powergood"
+ Pad settings will reset on:
+ - G3
+ Pad settings will not reset on:
+ - S3/S4/S5 transition
+ - Warm/Cold/Global reset
+ - DeepSx transition
+ **/
+ GpioDswReset = 0x07,
+ /**
+ Global reset. Server chipsets only.
+ PadRstCfg = 11b = "Global reset"
+ Pad settings will reset on:
+ - Global reset
+ - G3
+ Pad settings will not reset on:
+ - S3/S4/S5 transition
+ - Warm/Cold reset
+ - DeepSx transition
+ **/
+ GpioGlobalReset = 0x09
+} GPIO_RESET_CONFIG;
+
+/**
+ GPIO Electrical Configuration
+ Configuration options for GPIO termination setting
+**/
+typedef enum {
+ GpioTermDefault = 0x0, ///< Leave termination setting unmodified
+ GpioTermNone = 0x1, ///< none
+ GpioTermWpd5K = 0x5, ///< 5kOhm weak pull-down
+ GpioTermWpd20K = 0x9, ///< 20kOhm weak pull-down
+ GpioTermWpu1K = 0x13, ///< 1kOhm weak pull-up
+ GpioTermWpu2K = 0x17, ///< 2kOhm weak pull-up
+ GpioTermWpu5K = 0x15, ///< 5kOhm weak pull-up
+ GpioTermWpu20K = 0x19, ///< 20kOhm weak pull-up
+ GpioTermWpu1K2K = 0x1B, ///< 1kOhm & 2kOhm weak pull-up
+ /**
+ Native function controls pads termination
+ This setting is applicable only to some native modes.
+ Please check EDS to determine which native functionality
+ can control pads termination
+ **/
+ GpioTermNative = 0x1F
+} GPIO_ELECTRICAL_CONFIG;
+
+#define B_GPIO_ELECTRICAL_CONFIG_TERMINATION_MASK 0x1F ///< Mask for GPIO_ELECTRICAL_CONFIG for termination value
+
+/**
+ GPIO LockConfiguration
+ Set GPIO configuration lock and output state lock.
+ GpioPadConfigUnlock/Lock and GpioOutputStateUnlock can be OR'ed.
+ By default GPIO pads will be locked unless GPIO lib is explicitly
+ informed that certain pad is to be left unlocked.
+ Lock settings reset is in Powergood domain. Care must be taken when using this setting
+ as fields it locks may be reset by a different signal and can be controlled
+ by what is in GPIO_RESET_CONFIG (PADCFG_DW0.PadRstCfg). GPIO library provides
+ functions which allow to unlock a GPIO pad. If possible each GPIO lib function will try to unlock
+ an already locked pad upon request for reconfiguration
+**/
+typedef enum {
+ /**
+ Perform default action
+ - if pad is an GPO, lock configuration but leave output unlocked
+ - if pad is an GPI, lock everything
+ - if pad is in native, lock everything
+**/
+ GpioLockDefault = 0x0,
+ GpioPadConfigUnlock = 0x3, ///< Leave Pad configuration unlocked
+ GpioPadConfigLock = 0x1, ///< Lock Pad configuration
+ GpioOutputStateUnlock = 0xC, ///< Leave Pad output control unlocked
+ GpioPadUnlock = 0xF, ///< Leave both Pad configuration and output control unlocked
+ GpioPadLock = 0x5, ///< Lock both Pad configuration and output control
+ /**
+ Below statuses are used for
+ return from GpioGetPadConfig function
+ **/
+ GpioLockTxLockCfgUnLock = 0x7, ///< Tx State locked, Pad Configuration unlocked
+ GpioLockTxUnLockCfgLock = 0xD ///< Tx State unlocked, Pad Configuration locked
+} GPIO_LOCK_CONFIG;
+
+#define B_GPIO_LOCK_CONFIG_PAD_CONF_LOCK_MASK 0x3 ///< Mask for GPIO_LOCK_CONFIG for Pad Configuration Lock
+#define B_GPIO_LOCK_CONFIG_OUTPUT_LOCK_MASK 0xC ///< Mask for GPIO_LOCK_CONFIG for Pad Output Lock
+
+/**
+ Other GPIO Configuration
+ GPIO_OTHER_CONFIG is used for less often settings and for future extensions
+ Supported settings:
+ - RX raw override to '1' - allows to override input value to '1'
+ This setting is applicable only if in input mode (both in GPIO and native usage).
+ The override takes place at the internal pad state directly from buffer and before the RXINV.
+**/
+typedef enum {
+ GpioRxRaw1Default = 0x0, ///< Use default input override value
+ GpioRxRaw1Dis = 0x1, ///< Don't override input
+ GpioRxRaw1En = 0x3 ///< Override input to '1'
+} GPIO_OTHER_CONFIG;
+
+/**
+ Virtual GPIO eSPI Chip Select configuration
+ This setting selects between CS0 and CS1.
+ Supported settings:
+ - Chipselect CS0 and CS1
+**/
+typedef enum {
+ VgpioCs0 = 0x0, ///< Chipselect CS0
+ VgpioCs1 = 0x1, ///< Chipselect CS1
+} VGPIO_CS_CONFIG;
+
+#define B_GPIO_OTHER_CONFIG_RXRAW_MASK 0x3 ///< Mask for GPIO_OTHER_CONFIG for RxRaw1 setting
+
+#pragma pack(pop)
+
+#endif //_GPIO_CONFIG_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/GpioLib.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/GpioLib.h
new file mode 100644
index 0000000000..d787e13be4
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/GpioLib.h
@@ -0,0 +1,174 @@
+/** @file
+ Header file for GpioLib.
+ All function in this library is available for PEI, DXE, and SMM
+
+ @note: When GPIO pads are owned by ME Firmware, BIOS/host should not
+ attempt to access these GPIO Pads registers, registers value
+ returned in this case will be 0xFF.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _GPIO_LIB_H_
+#define _GPIO_LIB_H_
+
+#include <Library/GpioConfig.h>
+
+typedef struct {
+ GPIO_PAD GpioPad;
+ GPIO_CONFIG GpioConfig;
+} GPIO_INIT_CONFIG;
+
+/**
+ This procedure will initialize multiple GPIO pins. Use GPIO_INIT_CONFIG structure.
+ Structure contains fields that can be used to configure each pad.
+ Pad not configured using GPIO_INIT_CONFIG will be left with hardware default values.
+ Separate fields could be set to hardware default if it does not matter, except
+ GpioPad and PadMode.
+ Function will work in most efficient way if pads which belong to the same group are
+ placed in adjacent records of the table.
+ Although function can enable pads for Native mode, such programming is done
+ by reference code when enabling related silicon feature.
+
+ @param[in] NumberofItem Number of GPIO pads to be updated
+ @param[in] GpioInitTableAddress GPIO initialization table
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid group or pad number
+**/
+EFI_STATUS
+GpioConfigurePads (
+ IN UINT32 NumberOfItems,
+ IN GPIO_INIT_CONFIG *GpioInitTableAddress
+ );
+
+///
+/// Possible values of Pad Ownership
+/// If Pad is not under Host ownership then GPIO registers
+/// are not accessible by host (e.g. BIOS) and reading them
+/// will return 0xFFs.
+///
+typedef enum {
+ GpioPadOwnHost = 0x0,
+ GpioPadOwnCsme = 0x1,
+ GpioPadOwnIsh = 0x2,
+} GPIO_PAD_OWN;
+
+/**
+ This procedure will get Gpio Pad Ownership
+
+ @param[in] GpioPad GPIO pad
+ @param[out] PadOwnVal Value of Pad Ownership
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid GpioPad
+**/
+EFI_STATUS
+GpioGetPadOwnership (
+ IN GPIO_PAD GpioPad,
+ OUT GPIO_PAD_OWN *PadOwnVal
+ );
+
+/**
+ This procedure will check state of Pad Config Lock for pads within one group
+
+ @param[in] Group GPIO group
+ @param[in] DwNum PadCfgLock register number for current group.
+ For group which has less then 32 pads per group DwNum must be 0.
+ @param[out] PadCfgLockRegVal Value of PadCfgLock register
+ Bit position - PadNumber
+ Bit value - 0: NotLocked, 1: Locked
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid group or DwNum parameter number
+**/
+EFI_STATUS
+GpioGetPadCfgLockForGroupDw (
+ IN GPIO_GROUP Group,
+ IN UINT32 DwNum,
+ OUT UINT32 *PadCfgLockRegVal
+ );
+
+/**
+ This procedure will check state of Pad Config Tx Lock for pads within one group
+
+ @param[in] Group GPIO group
+ @param[in] DwNum PadCfgLockTx register number for current group.
+ For group which has less then 32 pads per group DwNum must be 0.
+ @param[out] PadCfgLockTxRegVal Value of PadCfgLockTx register
+ Bit position - PadNumber
+ Bit value - 0: NotLockedTx, 1: LockedTx
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid group or DwNum parameter number
+**/
+EFI_STATUS
+GpioGetPadCfgLockTxForGroupDw (
+ IN GPIO_GROUP Group,
+ IN UINT32 DwNum,
+ OUT UINT32 *PadCfgLockTxRegVal
+ );
+
+/**
+ This procedure will clear PadCfgLock for selected pads within one group.
+ Unlocking a pad will cause an SMI (if enabled)
+
+ @param[in] Group GPIO group
+ @param[in] DwNum PadCfgLock register number for current group.
+ For group which has less then 32 pads per group DwNum must be 0.
+ @param[in] PadsToUnlock Bitmask for pads which are going to be unlocked,
+ Bit position - PadNumber
+ Bit value - 0: DoNotUnlock, 1: Unlock
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid group or pad number
+**/
+EFI_STATUS
+GpioUnlockPadCfgForGroupDw (
+ IN GPIO_GROUP Group,
+ IN UINT32 DwNum,
+ IN UINT32 PadsToUnlock
+ );
+
+/**
+ This procedure will set PadCfgLock for selected pads within one group
+
+ @param[in] Group GPIO group
+ @param[in] DwNum PadCfgLock register number for current group.
+ For group which has less then 32 pads per group DwNum must be 0.
+ @param[in] PadsToLock Bitmask for pads which are going to be locked,
+ Bit position - PadNumber
+ Bit value - 0: DoNotLock, 1: Lock
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid group or DwNum parameter number
+**/
+EFI_STATUS
+GpioLockPadCfgForGroupDw (
+ IN GPIO_GROUP Group,
+ IN UINT32 DwNum,
+ IN UINT32 PadsToLock
+ );
+
+/**
+ This procedure will clear PadCfgLockTx for selected pads within one group.
+ Unlocking a pad will cause an SMI (if enabled)
+
+ @param[in] Group GPIO group
+ @param[in] DwNum PadCfgLockTx register number for current group.
+ For group which has less then 32 pads per group DwNum must be 0.
+ @param[in] PadsToUnlockTx Bitmask for pads which are going to be unlocked,
+ Bit position - PadNumber
+ Bit value - 0: DoNotUnLockTx, 1: LockTx
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid group or pad number
+**/
+EFI_STATUS
+GpioUnlockPadCfgTxForGroupDw (
+ IN GPIO_GROUP Group,
+ IN UINT32 DwNum,
+ IN UINT32 PadsToUnlockTx
+ );
+
+#endif // _GPIO_LIB_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/GpioNativeLib.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/GpioNativeLib.h
new file mode 100644
index 0000000000..971f931442
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/GpioNativeLib.h
@@ -0,0 +1,135 @@
+/** @file
+ Header file for GpioLib for native and Si specific usage.
+ All function in this library is available for PEI, DXE, and SMM,
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _GPIO_NATIVE_LIB_H_
+#define _GPIO_NATIVE_LIB_H_
+
+#include <Library/GpioConfig.h>
+
+/**
+ This procedure will get number of pads for certain GPIO group
+
+ @param[in] Group GPIO group number
+
+ @retval Value Pad number for group
+ If illegal group number then return 0
+**/
+UINT32
+GpioGetPadPerGroup (
+ IN GPIO_GROUP Group
+ );
+
+/**
+ This procedure will get number of groups
+
+ @param[in] none
+
+ @retval Value Group number
+**/
+UINT32
+GpioGetNumberOfGroups (
+ VOID
+ );
+/**
+ This procedure will get lowest group
+
+ @param[in] none
+
+ @retval Value Lowest Group
+**/
+GPIO_GROUP
+GpioGetLowestGroup (
+ VOID
+ );
+
+/**
+ This procedure will get highest group
+
+ @param[in] none
+
+ @retval Value Highest Group
+**/
+GPIO_GROUP
+GpioGetHighestGroup (
+ VOID
+ );
+
+/**
+ This procedure will get group
+
+ @param[in] GpioPad Gpio Pad
+
+ @retval Value Group
+**/
+GPIO_GROUP
+GpioGetGroupFromGpioPad (
+ IN GPIO_PAD GpioPad
+ );
+
+/**
+ This procedure will get group index (0 based) from GpioPad
+
+ @param[in] GpioPad Gpio Pad
+
+ @retval Value Group Index
+**/
+UINT32
+GpioGetGroupIndexFromGpioPad (
+ IN GPIO_PAD GpioPad
+ );
+
+/**
+ This procedure will get group index (0 based) from group
+
+ @param[in] GpioGroup Gpio Group
+
+ @retval Value Group Index
+**/
+UINT32
+GpioGetGroupIndexFromGroup (
+ IN GPIO_GROUP GpioGroup
+ );
+
+/**
+ This procedure will get group from group index (0 based)
+
+ @param[in] GroupIndex Group Index
+
+ @retval GpioGroup Gpio Group
+**/
+GPIO_GROUP
+GpioGetGroupFromGroupIndex (
+ IN UINT32 GroupIndex
+ );
+
+/**
+ This procedure will get pad number (0 based) from Gpio Pad
+
+ @param[in] GpioPad Gpio Pad
+
+ @retval Value Pad Number
+**/
+UINT32
+GpioGetPadNumberFromGpioPad (
+ IN GPIO_PAD GpioPad
+ );
+
+/**
+ This procedure will return GpioPad from Group and PadNumber
+
+ @param[in] Group GPIO group
+ @param[in] PadNumber GPIO PadNumber
+
+ @retval GpioPad GpioPad
+**/
+GPIO_PAD
+GpioGetGpioPadFromGroupAndPadNumber (
+ IN GPIO_GROUP Group,
+ IN UINT32 PadNumber
+ );
+
+#endif // _GPIO_NATIVE_LIB_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/GraphicsInfoLib.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/GraphicsInfoLib.h
new file mode 100644
index 0000000000..bd9a7734b1
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/GraphicsInfoLib.h
@@ -0,0 +1,46 @@
+/** @file
+ Header file for Graphics Private Info Lib implementation.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _GRAPHICS_INFO_LIB_H_
+#define _GRAPHICS_INFO_LIB_H_
+
+#include <Library/BaseLib.h>
+#include <Library/PciSegmentLib.h>
+#include <IndustryStandard/Pci22.h>
+#include <Register/SaRegsHostBridge.h>
+
+/**
+ GetIgdBusNumber: Get IGD Bus Number
+
+ @retval PCI bus number for IGD
+**/
+UINT8
+GetIgdBusNumber (
+ VOID
+ );
+
+/**
+ GetIgdDevNumber: Get IGD Dev Number
+
+ @retval PCI dev number for IGD
+**/
+UINT8
+GetIgdDevNumber (
+ VOID
+ );
+
+/**
+ GetIgdFunNumber: Get IGD Fun Number
+
+ @retval PCI fun number for IGD
+**/
+UINT8
+GetIgdFuncNumber (
+ VOID
+ );
+
+#endif
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/MmPciLib.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/MmPciLib.h
new file mode 100644
index 0000000000..04249eefdf
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/MmPciLib.h
@@ -0,0 +1,27 @@
+/** @file
+ Get Pci Express address library implementation.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _MM_PCI_LIB_H_
+#define _MM_PCI_LIB_H_
+
+/**
+ This procedure will get PCIE address
+
+ @param[in] Bus Pci Bus Number
+ @param[in] Device Pci Device Number
+ @param[in] Function Pci Function Number
+
+ @retval PCIE address
+**/
+UINTN
+EFIAPI
+MmPciBase (
+ IN UINT32 Bus,
+ IN UINT32 Device,
+ IN UINT32 Function
+);
+
+#endif // _PEI_DXE_SMM_MM_PCI_LIB_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/PchPcieRpLib.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/PchPcieRpLib.h
new file mode 100644
index 0000000000..d9ca215d85
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/PchPcieRpLib.h
@@ -0,0 +1,41 @@
+/** @file
+ Header file for PchPcieRpLib.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _PCH_PCIERP_LIB_H_
+#define _PCH_PCIERP_LIB_H_
+
+#include <Uefi.h>
+#include <Library/PchPcrLib.h>
+
+/**
+ Get Pch Pcie Root Port Device and Function Number by Root Port physical Number
+
+ @param[in] RpNumber Root port physical number. (0-based)
+ @param[out] RpDev Return corresponding root port device number.
+ @param[out] RpFun Return corresponding root port function number.
+
+ @retval EFI_SUCCESS
+**/
+EFI_STATUS
+EFIAPI
+GetPchPcieRpDevFun (
+ IN UINTN RpNumber,
+ OUT UINTN *RpDev,
+ OUT UINTN *RpFun
+ );
+
+/**
+ Gets pci segment base address of PCIe root port.
+
+ @param RpIndex Root Port Index (0 based)
+ @return PCIe port base address.
+**/
+UINT64
+PchPcieBase (
+ IN UINT32 RpIndex
+ );
+
+#endif // _PCH_PCIERP_LIB_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/PchPcrLib.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/PchPcrLib.h
new file mode 100644
index 0000000000..19a1a98639
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/PchPcrLib.h
@@ -0,0 +1,221 @@
+/** @file
+ Header file for PchPcrLib.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _PCH_PCR_LIB_H_
+#define _PCH_PCR_LIB_H_
+
+#include <PchReservedResources.h>
+
+/**
+ Definition for PCR address
+ The PCR address is used to the PCR MMIO programming
+
+ SBREG_BAR_20BITADDRESS is configured by SoC
+
+ SBREG_BAR_20BITADDRESS=1, the format has included 16b addressing.
+ +---------------------------------------------------------------------------------------------+
+ | Addr[63:28] | Addr[27:24] | Addr[23:16] | Addr[15:2] | Addr[1:0] |
+ +----------------+-----------------------+-----------------+----------------------------------+
+ | REG_BAR[63:28] | TargetRegister[19:16] | TargetPort[7:0] | TargetRegister[15:2] |
+ +---------------------------------------------------------------------------------------------+
+
+ SBREG_BAR_20BITADDRESS=0
+ +---------------------------------------------------------------------------------------------+
+ | Addr[63:24] | Addr[27:24] | Addr[23:16] | Addr[15:2] | Addr[1:0] |
+ +----------------+-----------------------+-----------------+----------------------------------+
+ | REG_BAR[63:24] | REG_BAR[27:24] | TargetPort[7:0] | TargetRegister[15:2] |
+ +---------------------------------------------------------------------------------------------+
+**/
+#define PCH_PCR_ADDRESS(Pid, Offset) (PCH_PCR_BASE_ADDRESS | (UINT32) (((Offset) & 0x0F0000) << 8) | ((UINT8)(Pid) << 16) | (UINT16) ((Offset) & 0xFFFF))
+
+/**
+ PCH PCR boot script accessing macro
+ Those macros are only available for DXE phase.
+**/
+#define PCH_PCR_BOOT_SCRIPT_WRITE(Width, Pid, Offset, Count, Buffer) \
+ S3BootScriptSaveMemWrite (Width, PCH_PCR_ADDRESS (Pid, Offset), Count, Buffer); \
+
+#define PCH_PCR_BOOT_SCRIPT_READ_WRITE(Width, Pid, Offset, DataOr, DataAnd) \
+ S3BootScriptSaveMemReadWrite (Width, PCH_PCR_ADDRESS (Pid, Offset), DataOr, DataAnd); \
+
+#define PCH_PCR_BOOT_SCRIPT_READ(Width, Pid, Offset, BitMask, BitValue) \
+ S3BootScriptSaveMemPoll (Width, PCH_PCR_ADDRESS (Pid, Offset), BitMask, BitValue, 1, 1);
+
+typedef UINT8 PCH_SBI_PID;
+
+/**
+ Read PCR register.
+ It returns PCR register and size in 4bytes.
+ The Offset should not exceed 0xFFFF and must be aligned with size.
+
+ @param[in] Pid Port ID
+ @param[in] Offset Register offset of this Port ID
+
+ @retval UINT32 PCR register value.
+**/
+UINT32
+PchPcrRead32 (
+ IN PCH_SBI_PID Pid,
+ IN UINT32 Offset
+ );
+
+/**
+ Read PCR register.
+ It returns PCR register and size in 2bytes.
+ The Offset should not exceed 0xFFFF and must be aligned with size.
+
+ @param[in] Pid Port ID
+ @param[in] Offset Register offset of this Port ID
+
+ @retval UINT16 PCR register value.
+**/
+UINT16
+PchPcrRead16 (
+ IN PCH_SBI_PID Pid,
+ IN UINT32 Offset
+ );
+
+/**
+ Read PCR register.
+ It returns PCR register and size in 1bytes.
+ The Offset should not exceed 0xFFFF and must be aligned with size.
+
+ @param[in] Pid Port ID
+ @param[in] Offset Register offset of this Port ID
+
+ @retval UINT8 PCR register value
+**/
+UINT8
+PchPcrRead8 (
+ IN PCH_SBI_PID Pid,
+ IN UINT32 Offset
+ );
+
+/**
+ Write PCR register.
+ It programs PCR register and size in 4bytes.
+ The Offset should not exceed 0xFFFF and must be aligned with size.
+
+ @param[in] Pid Port ID
+ @param[in] Offset Register offset of Port ID.
+ @param[in] Data Input Data. Must be the same size as Size parameter.
+
+ @retval UINT32 Value written to register
+**/
+UINT32
+PchPcrWrite32 (
+ IN PCH_SBI_PID Pid,
+ IN UINT32 Offset,
+ IN UINT32 InData
+ );
+
+/**
+ Write PCR register.
+ It programs PCR register and size in 2bytes.
+ The Offset should not exceed 0xFFFF and must be aligned with size.
+
+ @param[in] Pid Port ID
+ @param[in] Offset Register offset of Port ID.
+ @param[in] Data Input Data. Must be the same size as Size parameter.
+
+ @retval UINT16 Value written to register
+**/
+UINT16
+PchPcrWrite16 (
+ IN PCH_SBI_PID Pid,
+ IN UINT32 Offset,
+ IN UINT16 InData
+ );
+
+/**
+ Write PCR register.
+ It programs PCR register and size in 1bytes.
+ The Offset should not exceed 0xFFFF and must be aligned with size.
+
+ @param[in] Pid Port ID
+ @param[in] Offset Register offset of Port ID.
+ @param[in] Data Input Data. Must be the same size as Size parameter.
+
+ @retval UINT8 Value written to register
+**/
+UINT8
+PchPcrWrite8 (
+ IN PCH_SBI_PID Pid,
+ IN UINT32 Offset,
+ IN UINT8 InData
+ );
+
+/**
+ Write PCR register.
+ It programs PCR register and size in 4bytes.
+ The Offset should not exceed 0xFFFF and must be aligned with size.
+
+ @param[in] Pid Port ID
+ @param[in] Offset Register offset of Port ID.
+ @param[in] AndData AND Data. Must be the same size as Size parameter.
+ @param[in] OrData OR Data. Must be the same size as Size parameter.
+
+ @retval UINT32 Value written to register
+
+**/
+UINT32
+PchPcrAndThenOr32 (
+ IN PCH_SBI_PID Pid,
+ IN UINT32 Offset,
+ IN UINT32 AndData,
+ IN UINT32 OrData
+ );
+
+/**
+ Write PCR register.
+ It programs PCR register and size in 2bytes.
+ The Offset should not exceed 0xFFFF and must be aligned with size.
+
+ @param[in] Pid Port ID
+ @param[in] Offset Register offset of Port ID.
+ @param[in] AndData AND Data. Must be the same size as Size parameter.
+ @param[in] OrData OR Data. Must be the same size as Size parameter.
+
+ @retval UINT16 Value written to register
+
+**/
+UINT16
+PchPcrAndThenOr16 (
+ IN PCH_SBI_PID Pid,
+ IN UINT32 Offset,
+ IN UINT16 AndData,
+ IN UINT16 OrData
+ );
+
+/**
+ Write PCR register.
+ It programs PCR register and size in 1bytes.
+ The Offset should not exceed 0xFFFF and must be aligned with size.
+
+ @param[in] Pid Port ID
+ @param[in] Offset Register offset of Port ID.
+ @param[in] AndData AND Data. Must be the same size as Size parameter.
+ @param[in] OrData OR Data. Must be the same size as Size parameter.
+
+ @retval UINT8 Value written to register
+
+**/
+UINT8
+PchPcrAndThenOr8 (
+ IN PCH_SBI_PID Pid,
+ IN UINT32 Offset,
+ IN UINT8 AndData,
+ IN UINT8 OrData
+ );
+
+
+typedef enum {
+ PchIpDmi = 1,
+ PchIpIclk,
+} PCH_IP_PID_ENUM;
+
+
+#endif // _PCH_PCR_LIB_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/PeiDxeSmmReserveMmio64SizeLib.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/PeiDxeSmmReserveMmio64SizeLib.h
new file mode 100644
index 0000000000..d27f858892
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/PeiDxeSmmReserveMmio64SizeLib.h
@@ -0,0 +1,21 @@
+/** @file
+ PEI/DXE/SMM library for reserved 64-bit MMIO space.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PEI_DXE_SMM_RESERVE_MMIO_64_SIZE_LIB_H_
+#define _PEI_DXE_SMM_RESERVE_MMIO_64_SIZE_LIB_H_
+
+/**
+ The function return the 64 bit MMIO size to reserve.
+
+ @retval The 64-bit MMIO size
+**/
+UINT64
+ReserveMmio64Size (
+ VOID
+ );
+
+#endif // _PEI_DXE_SMM_RESERVE_MMIO_64_SIZE_LIB_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/PeiSiPolicyUpdateLib.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/PeiSiPolicyUpdateLib.h
new file mode 100644
index 0000000000..79e7752e4a
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/PeiSiPolicyUpdateLib.h
@@ -0,0 +1,154 @@
+/** @file
+ Header file for PEI SiPolicyUpdate Library.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PEI_SI_POLICY_UPDATE_LIB_H_
+#define _PEI_SI_POLICY_UPDATE_LIB_H_
+
+#include <Ppi/SiPolicy.h>
+
+/**
+ This function performs CPU PEI Policy initialization in Post-memory.
+
+ @retval EFI_SUCCESS The PPI is installed and initialized.
+ @retval EFI ERRORS The PPI is not successfully installed.
+ @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize the driver
+**/
+EFI_STATUS
+EFIAPI
+UpdatePeiCpuPolicy (
+ VOID
+ );
+
+/**
+ This function performs CPU PEI Policy initialization in PreMem.
+
+ @retval EFI_SUCCESS The PPI is installed and initialized.
+ @retval EFI ERRORS The PPI is not successfully installed.
+ @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize the driver
+**/
+EFI_STATUS
+EFIAPI
+UpdatePeiCpuPolicyPreMem (
+ VOID
+ );
+
+
+/**
+ This function performs SA PEI Policy initialization.
+
+ @retval EFI_SUCCESS The PPI is installed and initialized.
+**/
+EFI_STATUS
+EFIAPI
+UpdatePeiSaPolicy (
+ VOID
+ );
+
+/**
+ This function performs SA PEI Policy initialization for PreMem.
+
+ @retval EFI_SUCCESS Update complete.
+**/
+EFI_STATUS
+EFIAPI
+UpdatePeiSaPolicyPreMem (
+ VOID
+ );
+
+/**
+ This function performs PCH PEI Policy initialization.
+
+ @retval EFI_SUCCESS The PPI is installed and initialized.
+ @retval EFI ERRORS The PPI is not successfully installed.
+ @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize the driver
+**/
+EFI_STATUS
+EFIAPI
+UpdatePeiPchPolicy (
+ VOID
+ );
+
+/**
+ This function performs PCH PEI Policy initialization.
+
+ @retval EFI_SUCCESS The PPI is installed and initialized.
+ @retval EFI ERRORS The PPI is not successfully installed.
+ @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize the driver
+**/
+EFI_STATUS
+EFIAPI
+UpdatePeiPchPolicyPreMem (
+ VOID
+ );
+
+/**
+ Update the ME Policy Library
+
+ @retval EFI_SUCCESS Update complete.
+ @retval Others Update unsuccessful.
+**/
+EFI_STATUS
+EFIAPI
+UpdatePeiMePolicy (
+ VOID
+ );
+
+/**
+ Update the ME Policy Library
+
+ @retval EFI_SUCCESS Update complete.
+**/
+EFI_STATUS
+EFIAPI
+UpdatePeiMePolicyPreMem (
+ VOID
+ );
+
+
+
+/**
+ Update the TBT Policy Library
+
+ @retval EFI_SUCCESS Update complete.
+**/
+EFI_STATUS
+EFIAPI
+UpdatePeiTbtPolicy (
+ VOID
+ );
+
+/**
+ Update the ME Server Policy Ppi (pre mem)
+
+ @param[in, out] SiPreMemPolicyPpi PEI Pre Mem Si Policy
+
+ @retval EFI_SUCCESS Initialization complete.
+ @retval EFI_UNSUPPORTED The chipset is unsupported by this driver.
+ @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize the driver.
+ @retval EFI_DEVICE_ERROR Device error, driver exits abnormally.
+ @retval EFI_INVALID_PARAMETER Wrong pointer passed to the function
+**/
+EFI_STATUS
+UpdatePeiMeServerPreMemPolicy (
+ IN OUT SI_PREMEM_POLICY_PPI *SiPreMemPolicy
+ );
+
+/**
+ Update the ME Server Policy Ppi (post mem)
+
+ @param[in, out] SiPolicyPpi PEI Si Policy
+
+ @retval EFI_SUCCESS Initialization complete.
+ @retval EFI_UNSUPPORTED The chipset is unsupported by this driver.
+ @retval EFI_DEVICE_ERROR Device error, driver exits abnormally.
+ @retval EFI_INVALID_PARAMETER Wrong pointer passed to the function
+**/
+ EFI_STATUS
+UpdatePeiMeServerPolicy (
+ IN OUT SI_POLICY_PPI *SiPolicyPpi
+ );
+#endif
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/PmcLib.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/PmcLib.h
new file mode 100644
index 0000000000..7d49a14164
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/PmcLib.h
@@ -0,0 +1,40 @@
+/** @file
+ Header file for PmcLib.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _PMC_LIB_H_
+#define _PMC_LIB_H_
+
+#include <PmConfig.h>
+
+
+typedef struct {
+ UINT32 Buf0;
+ UINT32 Buf1;
+ UINT32 Buf2;
+ UINT32 Buf3;
+} PMC_IPC_COMMAND_BUFFER;
+
+/**
+ Get PCH ACPI base address.
+
+ @retval Address Address of PWRM base address.
+**/
+UINT16
+PmcGetAcpiBase (
+ VOID
+ );
+
+/**
+ Get PCH PWRM base address.
+
+ @retval Address Address of PWRM base address.
+**/
+UINT32
+PmcGetPwrmBase (
+ VOID
+ );
+
+#endif // _PMC_LIB_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/ResetSystemLib.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/ResetSystemLib.h
new file mode 100644
index 0000000000..6146e8610d
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/ResetSystemLib.h
@@ -0,0 +1,68 @@
+/** @file
+ System reset Library Services. This library class defines a set of
+ methods that reset the whole system.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef __RESET_SYSTEM_LIB_H__
+#define __RESET_SYSTEM_LIB_H__
+
+/**
+ This function causes a system-wide reset (cold reset), in which
+ all circuitry within the system returns to its initial state. This type of reset
+ is asynchronous to system operation and operates without regard to
+ cycle boundaries.
+
+ If this function returns, it means that the system does not support cold reset.
+**/
+VOID
+EFIAPI
+ResetCold (
+ VOID
+ );
+
+/**
+ This function causes a system-wide initialization (warm reset), in which all processors
+ are set to their initial state. Pending cycles are not corrupted.
+
+ If this function returns, it means that the system does not support warm reset.
+**/
+VOID
+EFIAPI
+ResetWarm (
+ VOID
+ );
+
+/**
+ This function causes the system to enter a power state equivalent
+ to the ACPI G2/S5 or G3 states.
+
+ If this function returns, it means that the system does not support shutdown reset.
+**/
+VOID
+EFIAPI
+ResetShutdown (
+ VOID
+ );
+
+/**
+ This function causes a systemwide reset. The exact type of the reset is
+ defined by the EFI_GUID that follows the Null-terminated Unicode string passed
+ into ResetData. If the platform does not recognize the EFI_GUID in ResetData
+ the platform must pick a supported reset type to perform.The platform may
+ optionally log the parameters from any non-normal reset that occurs.
+
+ @param[in] DataSize The size, in bytes, of ResetData.
+ @param[in] ResetData The data buffer starts with a Null-terminated string,
+ followed by the EFI_GUID.
+**/
+VOID
+EFIAPI
+ResetPlatformSpecific (
+ IN UINTN DataSize,
+ IN VOID *ResetData
+ );
+
+#endif
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/SecPlatformLib.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/SecPlatformLib.h
new file mode 100644
index 0000000000..7fa23b1a51
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/SecPlatformLib.h
@@ -0,0 +1,81 @@
+/** @file
+ Prototype of SEC Platform hook library.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _SEC_PLATFORM_LIB_H_
+#define _SEC_PLATFORM_LIB_H_
+
+#include <Ppi/SecPlatformInformation.h>
+#include <Ppi/SecPerformance.h>
+
+/**
+ A developer supplied function to perform platform specific operations.
+
+ It's a developer supplied function to perform any operations appropriate to a
+ given platform. It's invoked just before passing control to PEI core by SEC
+ core. Platform developer may modify the SecCoreData passed to PEI Core.
+ It returns a platform specific PPI list that platform wishes to pass to PEI core.
+ The Generic SEC core module will merge this list to join the final list passed to
+ PEI core.
+
+ @param SecCoreData The same parameter as passing to PEI core. It
+ could be overridden by this function.
+
+ @return The platform specific PPI list to be passed to PEI core or
+ NULL if there is no need of such platform specific PPI list.
+
+**/
+EFI_PEI_PPI_DESCRIPTOR *
+EFIAPI
+SecPlatformMain (
+ IN OUT EFI_SEC_PEI_HAND_OFF *SecCoreData
+ );
+
+
+/**
+ This interface conveys state information out of the Security (SEC) phase into PEI.
+
+ @param PeiServices Pointer to the PEI Services Table.
+ @param StructureSize Pointer to the variable describing size of the input buffer.
+ @param PlatformInformationRecord Pointer to the EFI_SEC_PLATFORM_INFORMATION_RECORD.
+
+ @retval EFI_SUCCESS The data was successfully returned.
+ @retval EFI_BUFFER_TOO_SMALL The buffer was too small.
+
+**/
+EFI_STATUS
+EFIAPI
+SecPlatformInformation (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN OUT UINT64 *StructureSize,
+ OUT EFI_SEC_PLATFORM_INFORMATION_RECORD *PlatformInformationRecord
+ );
+
+/**
+ This interface conveys performance information out of the Security (SEC) phase into PEI.
+
+ This service is published by the SEC phase. The SEC phase handoff has an optional
+ EFI_PEI_PPI_DESCRIPTOR list as its final argument when control is passed from SEC into the
+ PEI Foundation. As such, if the platform supports collecting performance data in SEC,
+ this information is encapsulated into the data structure abstracted by this service.
+ This information is collected for the boot-strap processor (BSP) on IA-32.
+
+ @param[in] PeiServices The pointer to the PEI Services Table.
+ @param[in] This The pointer to this instance of the PEI_SEC_PERFORMANCE_PPI.
+ @param[out] Performance The pointer to performance data collected in SEC phase.
+
+ @retval EFI_SUCCESS The data was successfully returned.
+**/
+EFI_STATUS
+EFIAPI
+SecGetPerformance (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN PEI_SEC_PERFORMANCE_PPI *This,
+ OUT FIRMWARE_SEC_PERFORMANCE *Performance
+ );
+
+#endif
+
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/SiConfigBlockLib.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/SiConfigBlockLib.h
new file mode 100644
index 0000000000..7bb111a932
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/SiConfigBlockLib.h
@@ -0,0 +1,56 @@
+/** @file
+ Prototype of the SiConfigBlockLib library.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _SI_CONFIG_BLOCK_LIB_H_
+#define _SI_CONFIG_BLOCK_LIB_H_
+
+
+typedef
+VOID
+(*LOAD_DEFAULT_FUNCTION) (
+ IN VOID *ConfigBlockPointer
+ );
+
+typedef struct {
+ EFI_GUID *Guid;
+ UINT16 Size;
+ UINT8 Revision;
+ LOAD_DEFAULT_FUNCTION LoadDefault;
+} COMPONENT_BLOCK_ENTRY;
+
+/**
+ GetComponentConfigBlockTotalSize get config block table total size.
+
+ @param[in] ComponentBlocks Component blocks array
+ @param[in] TotalBlockCount Number of blocks
+
+ @retval Size of config block table
+**/
+UINT16
+EFIAPI
+GetComponentConfigBlockTotalSize (
+ IN COMPONENT_BLOCK_ENTRY *ComponentBlocks,
+ IN UINT16 TotalBlockCount
+ );
+
+/**
+ AddComponentConfigBlocks add all config blocks.
+
+ @param[in] ConfigBlockTableAddress The pointer to add config blocks
+ @param[in] ComponentBlocks Config blocks array
+ @param[in] TotalBlockCount Number of blocks
+
+ @retval EFI_SUCCESS The policy default is initialized.
+ @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer
+**/
+EFI_STATUS
+EFIAPI
+AddComponentConfigBlocks (
+ IN VOID *ConfigBlockTableAddress,
+ IN COMPONENT_BLOCK_ENTRY *ComponentBlocks,
+ IN UINT16 TotalBlockCount
+ );
+#endif // _SI_CONFIG_BLOCK_LIB_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/SiPolicyLib.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/SiPolicyLib.h
new file mode 100644
index 0000000000..f821ea2fdf
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/SiPolicyLib.h
@@ -0,0 +1,39 @@
+/** @file
+ Prototype of the SiPolicyLib library.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _SI_POLICY_LIB_H_
+#define _SI_POLICY_LIB_H_
+
+#include <Ppi/SiPolicy.h>
+
+/**
+ SiPreMemInstallPolicyReadyPpi installs SiPreMemPolicyReadyPpi.
+ While installed, RC assumes the Policy is ready and finalized. So please update and override
+ any setting before calling this function.
+
+ @retval EFI_SUCCESS The policy is installed.
+ @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer
+**/
+EFI_STATUS
+EFIAPI
+SiPreMemInstallPolicyReadyPpi (
+ VOID
+ );
+
+/**
+ SiInstallPolicyReadyPpi installs SiPolicyReadyPpi.
+ While installed, RC assumes the Policy is ready and finalized. So please update and override
+ any setting before calling this function.
+
+ @retval EFI_SUCCESS The policy is installed.
+ @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer
+**/
+EFI_STATUS
+EFIAPI
+SiInstallPolicyReadyPpi (
+ VOID
+ );
+#endif // _SI_POLICY_LIB_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/SpiLib.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/SpiLib.h
new file mode 100644
index 0000000000..ca56e74e0f
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Library/SpiLib.h
@@ -0,0 +1,21 @@
+/** @file
+ Header file for Spi Library.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _SPI_LIB_H_
+#define _SPI_LIB_H_
+
+/**
+ This function Initial SPI services
+
+ @retval EFI_STATUS Results of the installation of the SPI services
+**/
+EFI_STATUS
+EFIAPI
+SpiServiceInit (
+ VOID
+ );
+
+#endif
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Pins/GpioPinsVer2Lp.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Pins/GpioPinsVer2Lp.h
new file mode 100644
index 0000000000..2f58de78f6
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Pins/GpioPinsVer2Lp.h
@@ -0,0 +1,36 @@
+/** @file
+ GPIO pins for TGL-PCH-LP,
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _GPIO_PINS_VER2_LP_H_
+#define _GPIO_PINS_VER2_LP_H_
+///
+/// This header file should be used together with
+/// PCH GPIO lib in C and ASL. All defines used
+/// must match both ASL/C syntax
+///
+
+///
+/// Unique ID used in GpioPad defines
+///
+#define GPIO_VER2_LP_CHIPSET_ID 0x9
+
+///
+/// TGL LP GPIO pins
+/// Use below for functions from PCH GPIO Lib which
+/// require GpioPad as argument. Encoding used here
+/// has all information required by library functions
+///
+#define GPIO_VER2_LP_GPP_H0 0x09070000
+#define GPIO_VER2_LP_GPP_H1 0x09070001
+#define GPIO_VER2_LP_GPP_D16 0x09080010
+#define GPIO_VER2_LP_GPP_C2 0x090B0002
+
+#define GPIO_VER2_LP_GPP_F9 0x090C0009
+#define GPIO_VER2_LP_GPP_F10 0x090C000A
+#define GPIO_VER2_LP_GPP_F20 0x090C0014
+
+#define GPIO_VER2_LP_GPP_E7 0x090E0007
+#endif // _GPIO_PINS_VER2_LP_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Ppi/FspmArchConfigPpi.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Ppi/FspmArchConfigPpi.h
new file mode 100644
index 0000000000..7ed834b9f5
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Ppi/FspmArchConfigPpi.h
@@ -0,0 +1,32 @@
+/** @file
+ Header file for FSP-M Arch Config PPI
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _FSPM_ARCH_CONFIG_PPI_H_
+#define _FSPM_ARCH_CONFIG_PPI_H_
+
+///
+/// Global ID for the FSPM_ARCH_CONFIG_PPI.
+///
+#define FSPM_ARCH_CONFIG_GUID \
+ { \
+ 0x824d5a3a, 0xaf92, 0x4c0c, { 0x9f, 0x19, 0x19, 0x52, 0x6d, 0xca, 0x4a, 0xbb } \
+ }
+
+///
+/// This PPI provides FSP-M Arch Config PPI.
+///
+typedef struct {
+ UINT8 Revision;
+ UINT8 Reserved[3];
+ VOID *NvsBufferPtr;
+ UINT32 BootLoaderTolumSize;
+ UINT8 Reserved1[4];
+} FSPM_ARCH_CONFIG_PPI;
+
+extern EFI_GUID gFspmArchConfigPpiGuid;
+
+#endif // _FSPM_ARCH_CONFIG_PPI_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Ppi/PeiPreMemSiDefaultPolicy.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Ppi/PeiPreMemSiDefaultPolicy.h
new file mode 100644
index 0000000000..0713dbd55b
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Ppi/PeiPreMemSiDefaultPolicy.h
@@ -0,0 +1,33 @@
+/** @file
+ This file defines the function to initialize default silicon policy PPI.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI_H_
+#define _PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI_H_
+
+//
+// Forward declaration for the PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI.
+//
+typedef struct _PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI;
+
+/**
+ Initialize and install default silicon policy PPI
+**/
+typedef
+EFI_STATUS
+(EFIAPI *PEI_PREMEM_POLICY_INIT) (
+ VOID
+ );
+
+///
+/// This PPI provides function to install default silicon policy
+///
+struct _PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI {
+ PEI_PREMEM_POLICY_INIT PeiPreMemPolicyInit; ///< PeiPreMemPolicyInit()
+};
+
+extern EFI_GUID gSiPreMemDefaultPolicyInitPpiGuid;
+
+#endif // _PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Ppi/PeiSiDefaultPolicy.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Ppi/PeiSiDefaultPolicy.h
new file mode 100644
index 0000000000..83bdbe0f6e
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Ppi/PeiSiDefaultPolicy.h
@@ -0,0 +1,33 @@
+/** @file
+ This file defines the function to initialize default silicon policy PPI.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _PEI_SI_DEFAULT_POLICY_INIT_PPI_H_
+#define _PEI_SI_DEFAULT_POLICY_INIT_PPI_H_
+
+//
+// Forward declaration for the PEI_SI_DEFAULT_POLICY_INIT_PPI.
+//
+typedef struct _PEI_SI_DEFAULT_POLICY_INIT_PPI PEI_SI_DEFAULT_POLICY_INIT_PPI;
+
+/**
+ Initialize and install default silicon policy PPI
+**/
+typedef
+EFI_STATUS
+(EFIAPI *PEI_POLICY_INIT) (
+ VOID
+ );
+
+///
+/// This PPI provides function to install default silicon policy
+///
+struct _PEI_SI_DEFAULT_POLICY_INIT_PPI {
+ PEI_POLICY_INIT PeiPolicyInit; ///< PeiPolicyInit()
+};
+
+extern EFI_GUID gSiDefaultPolicyInitPpiGuid;
+
+#endif // _PEI_SI_DEFAULT_POLICY_INIT_PPI_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Ppi/Spi.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Ppi/Spi.h
new file mode 100644
index 0000000000..0faf1e3443
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Ppi/Spi.h
@@ -0,0 +1,29 @@
+/** @file
+ This file defines the PCH SPI PPI which implements the
+ Intel(R) PCH SPI Host Controller Compatibility Interface.
+
+ @note The APIs in this file are designed to be backward compatible with
+ previous versions. Any change in behavior of these APIs will result in
+ newer version of the API.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _PCH_SPI_PPI_H_
+#define _PCH_SPI_PPI_H_
+
+#include <Protocol/Spi.h>
+
+//
+// Extern the GUID for PPI users.
+//
+extern EFI_GUID gPchSpiPpiGuid;
+
+/**
+ Reuse the PCH_SPI_PROTOCOL definitions
+ This is possible becaues the PPI implementation does not rely on a PeiService pointer,
+ as it uses EDKII Glue Lib to do IO accesses
+**/
+typedef PCH_SPI_PROTOCOL PCH_SPI_PPI;
+
+#endif
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Ppi/Wdt.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Ppi/Wdt.h
new file mode 100644
index 0000000000..bd8163fea0
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Ppi/Wdt.h
@@ -0,0 +1,22 @@
+/** @file
+ Watchdog Timer PPI
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _PEI_WDT_H_
+#define _PEI_WDT_H_
+
+#include <Protocol/Wdt.h>
+
+//
+// Extern the GUID for PPI users.
+//
+extern EFI_GUID gWdtPpiGuid;
+
+///
+/// Reuse WDT_PROTOCOL definition
+///
+typedef WDT_PROTOCOL WDT_PPI;
+
+#endif
--
2.36.1.windows.1
-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#108741): https://edk2.groups.io/g/devel/message/108741
Mute This Topic: https://groups.io/mt/101373950/7686176
Group Owner: devel+owner@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [rebecca@openfw.io]
-=-=-=-=-=-=-=-=-=-=-=-
^ permalink raw reply related [flat|nested] 41+ messages in thread
* Re: [edk2-devel] [PATCH v2 07/10] AlderlakeSiliconPkg/Include: Add Protocol, Register, Other Includes
2023-09-15 4:45 ` [edk2-devel] [PATCH v2 07/10] AlderlakeSiliconPkg/Include: Add Protocol, Register, Other Includes Saloni Kasbekar
2023-09-15 5:43 ` Chaganty, Rangasai V
@ 2023-09-15 23:56 ` Nate DeSimone
1 sibling, 0 replies; 41+ messages in thread
From: Nate DeSimone @ 2023-09-15 23:56 UTC (permalink / raw)
To: Kasbekar, Saloni, devel@edk2.groups.io
Cc: Chaganty, Rangasai V, Chuang, Rosen
Acked-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
-----Original Message-----
From: Kasbekar, Saloni <saloni.kasbekar@intel.com>
Sent: Thursday, September 14, 2023 9:46 PM
To: devel@edk2.groups.io
Cc: Kasbekar, Saloni <saloni.kasbekar@intel.com>; Chaganty, Rangasai V <rangasai.v.chaganty@intel.com>; Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>; Chuang, Rosen <rosen.chuang@intel.com>
Subject: [PATCH v2 07/10] AlderlakeSiliconPkg/Include: Add Protocol, Register, Other Includes
Adds the following Includes:
- Include/
- Include/Protocol
- Include/Register
Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Rosen Chuang <rosen.chuang@intel.com>
Signed-off-by: Saloni Kasbekar <saloni.kasbekar@intel.com>
---
.../AlderlakeSiliconPkg/Include/ConfigBlock.h | 53 +++
.../AlderlakeSiliconPkg/Include/CpuPcieHob.h | 48 +++
.../Include/Protocol/IgdOpRegion.h | 22 ++
.../Include/Protocol/Spi.h | 346 ++++++++++++++++++
.../Include/Protocol/Wdt.h | 111 ++++++
.../Include/Register/FlashRegs.h | 73 ++++
.../Include/Register/GpioRegs.h | 103 ++++++
.../Include/Register/GpioRegsVer2.h | 211 +++++++++++
.../Include/Register/PchDmi14Regs.h | 49 +++
.../Include/Register/PchDmiRegs.h | 51 +++
.../Include/Register/PchPcieRpRegs.h | 45 +++
.../Include/Register/PchRegsLpc.h | 77 ++++
.../Include/Register/PmcRegs.h | 134 +++++++
.../Include/Register/RtcRegs.h | 44 +++
.../Include/Register/TcoRegs.h | 71 ++++
.../Include/SerialIoDevices.h | 226 ++++++++++++
.../AlderlakeSiliconPkg/Include/SiConfigHob.h | 17 +
.../Include/SiPolicyStruct.h | 64 ++++
18 files changed, 1745 insertions(+)
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/CpuPcieHob.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Protocol/IgdOpRegion.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Protocol/Spi.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Protocol/Wdt.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Register/FlashRegs.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Register/GpioRegs.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Register/GpioRegsVer2.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Register/PchDmi14Regs.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Register/PchDmiRegs.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Register/PchPcieRpRegs.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Register/PchRegsLpc.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Register/PmcRegs.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Register/RtcRegs.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/Register/TcoRegs.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/SerialIoDevices.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/SiConfigHob.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Include/SiPolicyStruct.h
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock.h
new file mode 100644
index 0000000000..2e609bc8d9
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/ConfigBlock.h
@@ -0,0 +1,53 @@
+/** @file
+ Header file for Config Block Lib implementation
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _CONFIG_BLOCK_H_
+#define _CONFIG_BLOCK_H_
+
+#include <Uefi/UefiBaseType.h>
+#include <Uefi/UefiMultiPhase.h>
+#include <Pi/PiBootMode.h>
+#include <Pi/PiHob.h>
+
+#pragma pack (push,1)
+
+///
+/// Config Block Header
+///
+typedef struct _CONFIG_BLOCK_HEADER {
+ EFI_HOB_GUID_TYPE GuidHob; ///< Offset 0-23 GUID extension HOB header
+ UINT8 Revision; ///< Offset 24 Revision of this config block
+ UINT8 Attributes; ///< Offset 25 The main revision for config block
+ UINT8 Reserved[2]; ///< Offset 26-27 Reserved for future use
+} CONFIG_BLOCK_HEADER;
+
+///
+/// Config Block
+///
+typedef struct _CONFIG_BLOCK {
+ CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Header of config block
+ //
+ // Config Block Data
+ //
+} CONFIG_BLOCK;
+
+///
+/// Config Block Table Header
+///
+typedef struct _CONFIG_BLOCK_TABLE_STRUCT {
+ CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 GUID number for main entry of config block
+ UINT8 Rsvd0[2]; ///< Offset 28-29 Reserved for future use
+ UINT16 NumberOfBlocks; ///< Offset 30-31 Number of config blocks (N)
+ UINT32 AvailableSize; ///< Offset 32-35 Current config block table size
+///
+/// Individual Config Block Structures are added here in memory as part of AddConfigBlock()
+///
+} CONFIG_BLOCK_TABLE_HEADER;
+#pragma pack (pop)
+
+#endif // _CONFIG_BLOCK_H_
+
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/CpuPcieHob.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/CpuPcieHob.h
new file mode 100644
index 0000000000..dccd6e7d7a
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/CpuPcieHob.h
@@ -0,0 +1,48 @@
+/** @file
+ The GUID definition for CpuPcieHob
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _CPU_PCIE_HOB_H_
+#define _CPU_PCIE_HOB_H_
+
+#include <Base.h>
+#include <CpuPcieInfo.h>
+#include <CpuPcieConfig.h>
+
+extern EFI_GUID gCpuPcieHobGuid;
+#pragma pack (push,1)
+
+
+/**
+ The CPU_PCIE_HOB block describes the expected configuration of the CpuPcie controllers
+**/
+typedef struct {
+ ///
+ /// These members describe the configuration of each CPU PCIe root port.
+ ///
+ EFI_HOB_GUID_TYPE EfiHobGuidType; ///< Offset 0 - 23: GUID Hob type structure for gCpuPcieHobGuid
+ CPU_PCIE_ROOT_PORT_CONFIG RootPort[CPU_PCIE_MAX_ROOT_PORTS];
+ UINT8 L1SubStates[CPU_PCIE_MAX_ROOT_PORTS]; ///< The L1 Substates configuration of the root port
+
+ UINT32 DekelFwVersionMinor; ///< Dekel Firmware Minor Version
+ UINT32 DekelFwVersionMajor; ///< Dekel Firmware Major Version
+ BOOLEAN InitPcieAspmAfterOprom; ///< 1=initialize PCIe ASPM after Oprom; 0=before (This will be set basing on policy)
+ UINT32 RpEnabledMask; ///< Rootport enabled mask based on DEVEN register
+ UINT32 RpEnMaskFromDevEn; ///< Rootport enabled mask based on Device Id
+ UINT8 DisableClkReqMsg[CPU_PCIE_MAX_ROOT_PORTS]; ///< 1=ClkReqMsg disabled, 0=ClkReqMsg enabled
+ UINT8 SlotSelection; ///< 1=M2 slot, 0=CEMx4 slot
+ BOOLEAN ComplianceTest; ///< Compliance Test based on policy
+ UINT32 HsPhyRecipeVersionMajor; ///< HS-Phy Recipe Major Version
+ UINT32 HsPhyRecipeVersionMinor; ///< HS-Phy Recipe Minor Version
+ UINT32 HsPhyFwProdMajor; ///< HS-Phy Firmware Product Major Verison
+ UINT32 HsPhyFwProdMinor; ///< HS-Phy Firmware Product Minor Verison
+ UINT32 HsPhyFwHotFix; ///< HS-Phy Firmware Hot Fix Version
+ UINT32 HsPhyFwBuild; ///< HS-Phy Firmware Build version
+ UINT32 HsPhyFwEvBitProgMajor; ///< HS-Phy Firmware EV Bit Prog Major
+ UINT32 HsPhyFwEvBitProgMinor; ///< HS-Phy Firmware EV Bit Prog Minor
+ UINT32 HsPhyMap; ///< HS-Phy Mapping Based on HS-Py supported ports
+} CPU_PCIE_HOB;
+#pragma pack (pop)
+#endif
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Protocol/IgdOpRegion.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Protocol/IgdOpRegion.h
new file mode 100644
index 0000000000..9f69671f35
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Protocol/IgdOpRegion.h
@@ -0,0 +1,22 @@
+/** @file
+ This file is part of the IGD OpRegion Implementation. The IGD OpRegion is
+ an interface between system BIOS, ASL code, and Graphics drivers.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _IGD_OPREGION_PROTOCOL_H_
+#define _IGD_OPREGION_PROTOCOL_H_
+
+#include <IndustryStandard/IgdOpRegion.h>
+
+extern EFI_GUID gIgdOpRegionProtocolGuid;
+
+///
+/// IGD OpRegion Protocol
+///
+typedef struct {
+ IGD_OPREGION_STRUCTURE *OpRegion; ///< IGD Operation Region Structure
+} IGD_OPREGION_PROTOCOL;
+
+#endif
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Protocol/Spi.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Protocol/Spi.h
new file mode 100644
index 0000000000..cbf2883fa4
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Protocol/Spi.h
@@ -0,0 +1,346 @@
+/** @file
+ This file defines the PCH SPI Protocol which implements the
+ Intel(R) PCH SPI Host Controller Compatibility Interface.
+
+ @note The APIs in this file are designed to be backward compatible with
+ previous versions. Any change in behavior of these APIs will result in
+ newer version of the API.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _PCH_SPI_PROTOCOL_H_
+#define _PCH_SPI_PROTOCOL_H_
+
+//
+// Extern the GUID for protocol users.
+//
+extern EFI_GUID gPchSpiProtocolGuid;
+extern EFI_GUID gPchSmmSpiProtocolGuid;
+
+//
+// Forward reference for ANSI C compatibility
+//
+typedef struct _PCH_SPI_PROTOCOL PCH_SPI_PROTOCOL;
+
+//
+// SPI protocol data structures and definitions
+//
+
+/**
+ Flash Region Type
+**/
+typedef enum {
+ FlashRegionDescriptor,
+ FlashRegionBios,
+ FlashRegionMe,
+ FlashRegionGbE,
+ FlashRegionPlatformData,
+ FlashRegionDer,
+ FlashRegionSecondaryBios,
+ FlashRegionuCodePatch,
+ FlashRegionEC,
+ FlashRegionDeviceExpansion2,
+ FlashRegionIE,
+ FlashRegion10Gbe_A,
+ FlashRegion10Gbe_B,
+ FlashRegion13,
+ FlashRegion14,
+ FlashRegion15,
+ FlashRegionAll,
+ FlashRegionMax
+} FLASH_REGION_TYPE;
+
+//
+// Protocol member functions
+//
+
+/**
+ Read data from the flash part.
+
+ @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
+ @param[in] FlashRegionType The Flash Region type for flash cycle which
+ is listed in the Descriptor.
+ @param[in] Address The Flash Linear Address must fall within a
+ region for which BIOS has access permissions.
+ @param[in] ByteCount Number of bytes in the data portion of the
+ SPI cycle.
+ @param[out] Buffer The Pointer to caller-allocated buffer
+ containing the dada received.
+ It is the caller's responsibility to make
+ sure Buffer is large enough for the total
+ number of bytes read.
+
+ @retval EFI_SUCCESS Command succeed.
+ @retval EFI_INVALID_PARAMETER The parameters specified are not valid.
+ @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *PCH_SPI_FLASH_READ) (
+ IN PCH_SPI_PROTOCOL *This,
+ IN FLASH_REGION_TYPE FlashRegionType,
+ IN UINT32 Address,
+ IN UINT32 ByteCount,
+ OUT UINT8 *Buffer
+ );
+
+/**
+ Write data to the flash part. Remark: Erase may be needed before write to the
+ flash part.
+
+ @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
+ @param[in] FlashRegionType The Flash Region type for flash cycle which
+ is listed in the Descriptor.
+ @param[in] Address The Flash Linear Address must fall within a
+ region for which BIOS has access permissions.
+ @param[in] ByteCount Number of bytes in the data portion of the
+ SPI cycle.
+ @param[in] Buffer Pointer to caller-allocated buffer containing
+ the data sent during the SPI cycle.
+
+ @retval EFI_SUCCESS Command succeed.
+ @retval EFI_INVALID_PARAMETER The parameters specified are not valid.
+ @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *PCH_SPI_FLASH_WRITE) (
+ IN PCH_SPI_PROTOCOL *This,
+ IN FLASH_REGION_TYPE FlashRegionType,
+ IN UINT32 Address,
+ IN UINT32 ByteCount,
+ IN UINT8 *Buffer
+ );
+
+/**
+ Erase area on the flash part.
+
+ @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
+ @param[in] FlashRegionType The Flash Region type for flash cycle which
+ is listed in the Descriptor.
+ @param[in] Address The Flash Linear Address must fall within a
+ region for which BIOS has access permissions.
+ @param[in] ByteCount Number of bytes in the data portion of the
+ SPI cycle.
+
+ @retval EFI_SUCCESS Command succeed.
+ @retval EFI_INVALID_PARAMETER The parameters specified are not valid.
+ @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *PCH_SPI_FLASH_ERASE) (
+ IN PCH_SPI_PROTOCOL *This,
+ IN FLASH_REGION_TYPE FlashRegionType,
+ IN UINT32 Address,
+ IN UINT32 ByteCount
+ );
+
+/**
+ Read SFDP data from the flash part.
+
+ @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
+ @param[in] ComponentNumber The Componen Number for chip select
+ @param[in] Address The starting byte address for SFDP data read.
+ @param[in] ByteCount Number of bytes in SFDP data portion of the
+ SPI cycle
+ @param[out] SfdpData The Pointer to caller-allocated buffer
+ containing the SFDP data received
+ It is the caller's responsibility to make
+ sure Buffer is large enough for the total
+ number of bytes read
+
+ @retval EFI_SUCCESS Command succeed.
+ @retval EFI_INVALID_PARAMETER The parameters specified are not valid.
+ @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *PCH_SPI_FLASH_READ_SFDP) (
+ IN PCH_SPI_PROTOCOL *This,
+ IN UINT8 ComponentNumber,
+ IN UINT32 Address,
+ IN UINT32 ByteCount,
+ OUT UINT8 *SfdpData
+ );
+
+/**
+ Read Jedec Id from the flash part.
+
+ @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
+ @param[in] ComponentNumber The Componen Number for chip select
+ @param[in] ByteCount Number of bytes in JedecId data portion of
+ the SPI cycle, the data size is 3 typically
+ @param[out] JedecId The Pointer to caller-allocated buffer
+ containing JEDEC ID received.
+ It is the caller's responsibility to make
+ sure Buffer is large enough for the total
+ number of bytes read.
+
+ @retval EFI_SUCCESS Command succeed.
+ @retval EFI_INVALID_PARAMETER The parameters specified are not valid.
+ @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *PCH_SPI_FLASH_READ_JEDEC_ID) (
+ IN PCH_SPI_PROTOCOL *This,
+ IN UINT8 ComponentNumber,
+ IN UINT32 ByteCount,
+ OUT UINT8 *JedecId
+ );
+
+/**
+ Write the status register in the flash part.
+
+ @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
+ @param[in] ByteCount Number of bytes in Status data portion of the
+ SPI cycle, the data size is 1 typically
+ @param[in] StatusValue The Pointer to caller-allocated buffer
+ containing the value of Status register writing
+
+ @retval EFI_SUCCESS Command succeed.
+ @retval EFI_INVALID_PARAMETER The parameters specified are not valid.
+ @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *PCH_SPI_FLASH_WRITE_STATUS) (
+ IN PCH_SPI_PROTOCOL *This,
+ IN UINT32 ByteCount,
+ IN UINT8 *StatusValue
+ );
+
+/**
+ Read status register in the flash part.
+
+ @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
+ @param[in] ByteCount Number of bytes in Status data portion of the
+ SPI cycle, the data size is 1 typically
+ @param[out] StatusValue The Pointer to caller-allocated buffer
+ containing the value of Status register received.
+
+ @retval EFI_SUCCESS Command succeed.
+ @retval EFI_INVALID_PARAMETER The parameters specified are not valid.
+ @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *PCH_SPI_FLASH_READ_STATUS) (
+ IN PCH_SPI_PROTOCOL *This,
+ IN UINT32 ByteCount,
+ OUT UINT8 *StatusValue
+ );
+
+/**
+ Get the SPI region base and size, based on the enum type
+
+ @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
+ @param[in] FlashRegionType The Flash Region type for for the base address
+ which is listed in the Descriptor.
+ @param[out] BaseAddress The Flash Linear Address for the Region 'n'
+ Base
+ @param[out] RegionSize The size for the Region 'n'
+
+ @retval EFI_SUCCESS Read success
+ @retval EFI_INVALID_PARAMETER Invalid region type given
+ @retval EFI_DEVICE_ERROR The region is not used
+**/
+typedef
+EFI_STATUS
+(EFIAPI *PCH_SPI_GET_REGION_ADDRESS) (
+ IN PCH_SPI_PROTOCOL *This,
+ IN FLASH_REGION_TYPE FlashRegionType,
+ OUT UINT32 *BaseAddress,
+ OUT UINT32 *RegionSize
+ );
+
+/**
+ Read PCH Soft Strap Values
+
+ @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
+ @param[in] SoftStrapAddr PCH Soft Strap address offset from FPSBA.
+ @param[in] ByteCount Number of bytes in SoftStrap data portion of
+ the SPI cycle
+ @param[out] SoftStrapValue The Pointer to caller-allocated buffer
+ containing PCH Soft Strap Value.
+ If the value of ByteCount is 0, the data type
+ of SoftStrapValue should be UINT16 and
+ SoftStrapValue will be PCH Soft Strap Length.
+ It is the caller's responsibility to make sure
+ Buffer is large enough for the total number of
+ bytes read.
+
+ @retval EFI_SUCCESS Command succeed.
+ @retval EFI_INVALID_PARAMETER The parameters specified are not valid.
+ @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *PCH_SPI_READ_PCH_SOFTSTRAP) (
+ IN PCH_SPI_PROTOCOL *This,
+ IN UINT32 SoftStrapAddr,
+ IN UINT32 ByteCount,
+ OUT VOID *SoftStrapValue
+ );
+
+/**
+ Read CPU Soft Strap Values
+
+ @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
+ @param[in] SoftStrapAddr CPU Soft Strap address offset from FCPUSBA.
+ @param[in] ByteCount Number of bytes in SoftStrap data portion of
+ the SPI cycle.
+ @param[out] SoftStrapValue The Pointer to caller-allocated buffer
+ containing CPU Soft Strap Value.
+ If the value of ByteCount is 0, the data type
+ of SoftStrapValue should be UINT16 and
+ SoftStrapValue will be PCH Soft Strap Length
+ It is the caller's responsibility to make sure
+ Buffer is large enough for the total number
+ of bytes read.
+
+ @retval EFI_SUCCESS Command succeed.
+ @retval EFI_INVALID_PARAMETER The parameters specified are not valid.
+ @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *PCH_SPI_READ_CPU_SOFTSTRAP) (
+ IN PCH_SPI_PROTOCOL *This,
+ IN UINT32 SoftStrapAddr,
+ IN UINT32 ByteCount,
+ OUT VOID *SoftStrapValue
+ );
+
+/**
+ These protocols/PPI allows a platform module to perform SPI operations
+ through the Intel PCH SPI Host Controller Interface.
+**/
+struct _PCH_SPI_PROTOCOL {
+ /**
+ This member specifies the revision of this structure. This field is
+ used to indicate backwards compatible changes to the protocol.
+ **/
+ UINT8 Revision;
+ PCH_SPI_FLASH_READ FlashRead; ///< Read data from the flash part.
+ PCH_SPI_FLASH_WRITE FlashWrite; ///< Write data to the flash part. Remark: Erase may be needed before write to the flash part.
+ PCH_SPI_FLASH_ERASE FlashErase; ///< Erase some area on the flash part.
+ PCH_SPI_FLASH_READ_SFDP FlashReadSfdp; ///< Read SFDP data from the flash part.
+ PCH_SPI_FLASH_READ_JEDEC_ID FlashReadJedecId; ///< Read Jedec Id from the flash part.
+ PCH_SPI_FLASH_WRITE_STATUS FlashWriteStatus; ///< Write the status register in the flash part.
+ PCH_SPI_FLASH_READ_STATUS FlashReadStatus; ///< Read status register in the flash part.
+ PCH_SPI_GET_REGION_ADDRESS GetRegionAddress; ///< Get the SPI region base and size
+ PCH_SPI_READ_PCH_SOFTSTRAP ReadPchSoftStrap; ///< Read PCH Soft Strap Values
+ PCH_SPI_READ_CPU_SOFTSTRAP ReadCpuSoftStrap; ///< Read CPU Soft Strap Values
+};
+
+/**
+ PCH SPI PPI/PROTOCOL revision number
+
+ Revision 1: Initial version
+**/
+#define PCH_SPI_SERVICES_REVISION 1
+
+#endif
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Protocol/Wdt.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Protocol/Wdt.h
new file mode 100644
index 0000000000..a68085fa54
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Protocol/Wdt.h
@@ -0,0 +1,111 @@
+/** @file
+ Watchdog Timer protocol
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _DXE_WDT_H_
+#define _DXE_WDT_H_
+
+//
+// Extern the GUID for protocol users.
+//
+extern EFI_GUID gWdtProtocolGuid;
+//
+// Forward reference for ANSI C compatibility
+//
+typedef struct _WDT_PROTOCOL WDT_PROTOCOL;
+
+/**
+ Reloads WDT with new timeout value and starts it. Also sets Unexpected Reset bit, which
+ causes the next reset to be treated as watchdog expiration - unless AllowKnownReset()
+ function was called too.
+
+ @param[in] TimeoutValue Time in seconds before WDT times out. Supported range = 1 - 1024.
+
+ @retval EFI_SUCCESS if everything's OK
+ @retval EFI_INVALID_PARAMETER if TimeoutValue parameter is wrong
+**/
+typedef
+EFI_STATUS
+(EFIAPI *WDT_RELOAD_AND_START) (
+ UINT32 TimeoutValue
+ );
+
+/**
+ Returns WDT failure status.
+
+ @retval V_PCH_OC_WDT_CTL_STATUS_FAILURE If there was WDT expiration or unexpected reset
+ @retval V_PCH_OC_WDT_CTL_STATUS_OK Otherwise
+**/
+typedef
+UINT8
+(EFIAPI *WDT_CHECK_STATUS) (
+ VOID
+ );
+
+/**
+ Returns information if WDT coverage for the duration of BIOS execution
+ was requested by an OS application.
+
+ @retval TRUE if WDT was requested
+ @retval FALSE if WDT was not requested
+**/
+typedef
+UINT8
+(EFIAPI *IS_WDT_REQUIRED) (
+ VOID
+ );
+
+/**
+ Returns WDT enabled/disabled status.
+
+ @retval TRUE if WDT is enabled
+ @retval FALSE if WDT is disabled
+**/
+typedef
+UINT8
+(EFIAPI *IS_WDT_ENABLED) (
+ VOID
+ );
+
+/**
+ Disables WDT timer.
+**/
+typedef
+VOID
+(EFIAPI *WDT_DISABLE) (
+ VOID
+ );
+
+/**
+ Normally, each reboot performed while watchdog runs is considered a failure.
+ This function allows platform to perform expected reboots with WDT running,
+ without being interpreted as failures.
+ In DXE phase, it is enough to call this function any time before reset.
+ In PEI phase, between calling this function and performing reset, ReloadAndStart()
+ must not be called.
+**/
+typedef
+VOID
+(EFIAPI *WDT_ALLOW_KNOWN_RESET) (
+ VOID
+ );
+
+/**
+ These protocols and PPI allow a platform module to perform watch dog timer operations
+ through the Intel PCH LPC Host Controller Interface. The WDT protocol and WDT PPI
+ implement the Intel (R) Watch Dog timer for DXE, and PEI environments, respectively.
+ WDT_PROTOCOL referenced hereafter represents both WDT_PROTOCOL and WDT_PPI, as they
+ share the identical data structure.
+**/
+struct _WDT_PROTOCOL {
+ WDT_RELOAD_AND_START ReloadAndStart; ///< Reloads WDT with new timeout value and starts it.
+ WDT_CHECK_STATUS CheckStatus; ///< Returns WDT failure status.
+ WDT_DISABLE Disable; ///< Disables WDT timer.
+ WDT_ALLOW_KNOWN_RESET AllowKnownReset; ///< Perform expected reboots with WDT running, without being interpreted as failures.
+ IS_WDT_REQUIRED IsWdtRequired; ///< Returns information if WDT coverage for the duration of BIOS execution was requested by an OS application.
+ IS_WDT_ENABLED IsWdtEnabled; ///< Returns WDT enabled/disabled status.
+};
+
+#endif
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/FlashRegs.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/FlashRegs.h
new file mode 100644
index 0000000000..860f823655
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/FlashRegs.h
@@ -0,0 +1,73 @@
+/** @file
+ Register names for Flash registers
+
+ Conventions:
+
+ - Register definition format:
+ Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_RegisterName
+ - Prefix:
+ Definitions beginning with "R_" are registers
+ Definitions beginning with "B_" are bits within registers
+ Definitions beginning with "V_" are meaningful values within the bits
+ Definitions beginning with "S_" are register size
+ Definitions beginning with "N_" are the bit position
+ - [GenerationName]:
+ Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc.).
+ Register name without GenerationName applies to all generations.
+ - [ComponentName]:
+ This field indicates the component name that the register belongs to (e.g. PCH, SA etc.)
+ Register name without ComponentName applies to all components.
+ Register that is specific to -H denoted by "_PCH_H_" in component name.
+ Register that is specific to -LP denoted by "_PCH_LP_" in component name.
+ - SubsystemName:
+ This field indicates the subsystem name of the component that the register belongs to
+ (e.g. PCIE, USB, SATA, GPIO, PMC etc.).
+ - RegisterSpace:
+ MEM - MMIO space register of subsystem.
+ IO - IO space register of subsystem.
+ PCR - Private configuration register of subsystem.
+ CFG - PCI configuration space register of subsystem.
+ - RegisterName:
+ Full register name.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _FLASH_REGS_H_
+#define _FLASH_REGS_H_
+
+
+//
+// Flash Descriptor Base Address Region (FDBAR) from Flash Region 0
+//
+#define R_FLASH_FDBAR_FLASH_MAP0 0x04
+#define B_FLASH_FDBAR_NC 0x00000300 ///< Number Of Components
+#define N_FLASH_FDBAR_NC 8 ///< Number Of Components
+#define R_FLASH_FDBAR_FLASH_MAP1 0x08
+#define B_FLASH_FDBAR_FPSBA 0x00FF0000 ///< PCH Strap Base Address, [23:16] represents [11:4]
+#define N_FLASH_FDBAR_FPSBA 16 ///< PCH Strap base Address bit position
+#define N_FLASH_FDBAR_FPSBA_REPR 4 ///< PCH Strap base Address bit represents position
+#define B_FLASH_FDBAR_PCHSL 0xFF000000 ///< PCH Strap Length, [31:24] represents number of Dwords
+#define N_FLASH_FDBAR_PCHSL 24 ///< PCH Strap Length bit position
+#define R_FLASH_FDBAR_FLASH_MAP2 0x0C
+#define B_FLASH_FDBAR_FCPUSBA 0x00000FFC ///< CPU Strap Base Address [11:2]
+#define N_FLASH_FDBAR_FCPUSBA 2 ///< CPU Strap Base Address bit position
+#define B_FLASH_FDBAR_CPUSL 0x00FF0000 ///< CPU Strap Length, [23:16] represents number of Dwords
+#define N_FLASH_FDBAR_CPUSL 16 ///< CPU Strap Length bit position
+
+//
+// Flash Component Base Address (FCBA) from Flash Region 0
+//
+#define R_FLASH_FCBA_FLCOMP 0x00 ///< Flash Components Register
+#define B_FLASH_FLCOMP_COMP1_MASK 0xF0 ///< Flash Component 1 Size MASK
+#define N_FLASH_FLCOMP_COMP1 4 ///< Flash Component 1 Size bit position
+#define B_FLASH_FLCOMP_COMP0_MASK 0x0F ///< Flash Component 0 Size MASK
+#define V_FLASH_FLCOMP_COMP_512KB 0x80000
+//
+// Descriptor Upper Map Section from Flash Region 0
+//
+#define R_FLASH_UMAP1 0xEFC ///< Flash Upper Map 1
+#define B_FLASH_UMAP1_MDTBA 0xFF000000 ///< MIP Descriptor Table Base Address
+#define N_FLASH_UMAP1_MDTBA 24 ///< MDTBA bits position
+#define N_FLASH_UMAP1_MDTBA_REPR 4 ///< MDTBA address representation position
+#endif
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/GpioRegs.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/GpioRegs.h
new file mode 100644
index 0000000000..c89dccb7bd
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/GpioRegs.h
@@ -0,0 +1,103 @@
+/** @file
+ Register names for PCH GPIO
+
+Conventions:
+
+ - Register definition format:
+ Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_RegisterName
+ - Prefix:
+ Definitions beginning with "R_" are registers
+ Definitions beginning with "B_" are bits within registers
+ Definitions beginning with "V_" are meaningful values within the bits
+ Definitions beginning with "S_" are register size
+ Definitions beginning with "N_" are the bit position
+ - [GenerationName]:
+ Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc.).
+ Register name without GenerationName applies to all generations.
+ - [ComponentName]:
+ This field indicates the component name that the register belongs to (e.g. PCH, SA etc.)
+ Register name without ComponentName applies to all components.
+ Register that is specific to -H denoted by "_PCH_H_" in component name.
+ Register that is specific to -LP denoted by "_PCH_LP_" in component name.
+ - SubsystemName:
+ This field indicates the subsystem name of the component that the register belongs to
+ (e.g. PCIE, USB, SATA, GPIO, PMC etc.).
+ - RegisterSpace:
+ MEM - MMIO space register of subsystem.
+ IO - IO space register of subsystem.
+ PCR - Private configuration register of subsystem.
+ CFG - PCI configuration space register of subsystem.
+ - RegisterName:
+ Full register name.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _GPIO_REGS_H_
+#define _GPIO_REGS_H_
+
+//
+// PADCFG register is split into multiple DW registers
+// S_GPIO_PCR_PADCFG refers to number of bytes used by all those registers for one pad
+//
+#define S_GPIO_PCR_PADCFG 0x10
+
+//
+// Pad Configuration Register DW0
+//
+
+
+//RX Raw Override to 1
+#define B_GPIO_PCR_RX_RAW1 BIT28
+#define N_GPIO_PCR_RX_RAW1 28
+
+//RX Level/Edge Configuration
+#define B_GPIO_PCR_RX_LVL_EDG (BIT26 | BIT25)
+#define N_GPIO_PCR_RX_LVL_EDG 25
+
+//RX Invert
+#define B_GPIO_PCR_RXINV BIT23
+#define N_GPIO_PCR_RXINV 23
+
+//GPIO Input Route IOxAPIC
+#define B_GPIO_PCR_RX_APIC_ROUTE BIT20
+
+//GPIO Input Route SCI
+#define B_GPIO_PCR_RX_SCI_ROUTE BIT19
+
+//GPIO Input Route SMI
+#define B_GPIO_PCR_RX_SMI_ROUTE BIT18
+
+//GPIO Input Route NMI
+#define B_GPIO_PCR_RX_NMI_ROUTE BIT17
+#define N_GPIO_PCR_RX_NMI_ROUTE 17
+
+//GPIO Pad Mode
+#define B_GPIO_PCR_PAD_MODE (BIT12 | BIT11 | BIT10)
+#define N_GPIO_PCR_PAD_MODE 10
+
+//GPIO RX Disable
+#define B_GPIO_PCR_RXDIS BIT9
+
+//GPIO TX Disable
+#define B_GPIO_PCR_TXDIS BIT8
+#define N_GPIO_PCR_TXDIS 8
+
+//GPIO TX State
+#define B_GPIO_PCR_TX_STATE BIT0
+#define N_GPIO_PCR_TX_STATE 0
+
+//Termination
+#define B_GPIO_PCR_TERM (BIT13 | BIT12 | BIT11 | BIT10)
+#define N_GPIO_PCR_TERM 10
+
+
+///
+/// GPIO SMI data used for EFI_SMM_GPI_DISPATCH2_PROTOCOL
+/// Below defines are to be used internally by PCH SMI dispatcher only
+///
+#define PCH_GPIO_NUM_SUPPORTED_GPIS 512
+#define S_GPIO_PCR_GP_SMI_STS 4
+
+#endif // _GPIO_REGS_H_
+
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/GpioRegsVer2.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/GpioRegsVer2.h
new file mode 100644
index 0000000000..7789236b5e
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/GpioRegsVer2.h
@@ -0,0 +1,211 @@
+/** @file
+ Register names for VER2 GPIO
+
+Conventions:
+
+ - Register definition format:
+ Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_RegisterName
+ - Prefix:
+ Definitions beginning with "R_" are registers
+ Definitions beginning with "B_" are bits within registers
+ Definitions beginning with "V_" are meaningful values within the bits
+ Definitions beginning with "S_" are register size
+ Definitions beginning with "N_" are the bit position
+ - [GenerationName]:
+ Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc.).
+ Register name without GenerationName applies to all generations.
+ - [ComponentName]:
+ This field indicates the component name that the register belongs to (e.g. PCH, SA etc.)
+ Register name without ComponentName applies to all components.
+ Register that is specific to -H denoted by "_PCH_H_" in component name.
+ Register that is specific to -LP denoted by "_PCH_LP_" in component name.
+ - SubsystemName:
+ This field indicates the subsystem name of the component that the register belongs to
+ (e.g. PCIE, USB, SATA, GPIO, PMC etc.).
+ - RegisterSpace:
+ MEM - MMIO space register of subsystem.
+ IO - IO space register of subsystem.
+ PCR - Private configuration register of subsystem.
+ CFG - PCI configuration space register of subsystem.
+ - RegisterName:
+ Full register name.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _GPIO_REGS_VER2_H_
+#define _GPIO_REGS_VER2_H_
+
+#define GPIO_VER2_PCH_LP_GPIO_GPP_B_PAD_MAX 26
+#define GPIO_VER2_PCH_LP_GPIO_GPP_A_PAD_MAX 25
+#define GPIO_VER2_PCH_LP_GPIO_GPP_R_PAD_MAX 8
+#define GPIO_VER2_PCH_LP_GPIO_GPD_PAD_MAX 17
+#define GPIO_VER2_PCH_LP_GPIO_GPP_S_PAD_MAX 8
+#define GPIO_VER2_PCH_LP_GPIO_GPP_H_PAD_MAX 24
+#define GPIO_VER2_PCH_LP_GPIO_GPP_D_PAD_MAX 21
+#define GPIO_VER2_PCH_LP_GPIO_GPP_F_PAD_MAX 25
+#define GPIO_VER2_PCH_LP_GPIO_GPP_C_PAD_MAX 24
+#define GPIO_VER2_PCH_LP_GPIO_GPP_E_PAD_MAX 25
+
+//
+// GPIO Community 0 Private Configuration Registers
+//
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_PAD_OWN 0x20
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_A_PAD_OWN 0x38
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_PADCFGLOCK 0x80
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_PADCFGLOCKTX 0x84
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_A_PADCFGLOCK 0x90
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_A_PADCFGLOCKTX 0x94
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_HOSTSW_OWN 0xB0
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_A_HOSTSW_OWN 0xB8
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_GPI_IS 0x0100
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_A_GPI_IS 0x0108
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_GPI_IE 0x0120
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_A_GPI_IE 0x0128
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_GPI_GPE_STS 0x0140
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_A_GPI_GPE_STS 0x0148
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_GPI_GPE_EN 0x0160
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_A_GPI_GPE_EN 0x0168
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_SMI_STS 0x0180
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_SMI_EN 0x01A0
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_NMI_STS 0x01C0
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_NMI_EN 0x01E0
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_PADCFG_OFFSET 0x700
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_A_PADCFG_OFFSET 0x9A0
+
+//
+// GPIO Community 1 Private Configuration Registers
+//
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_S_PAD_OWN 0x20
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_H_PAD_OWN 0x24
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_PAD_OWN 0x30
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_S_PADCFGLOCK 0x80
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_S_PADCFGLOCKTX 0x84
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_H_PADCFGLOCK 0x88
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_H_PADCFGLOCKTX 0x8C
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_PADCFGLOCK 0x90
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_PADCFGLOCKTX 0x94
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_S_HOSTSW_OWN 0xB0
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_H_HOSTSW_OWN 0xB4
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_HOSTSW_OWN 0xB8
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_S_GPI_IS 0x0100
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_H_GPI_IS 0x0104
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_GPI_IS 0x0108
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_S_GPI_IE 0x0120
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_H_GPI_IE 0x0124
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_GPI_IE 0x0128
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_S_GPI_GPE_STS 0x0140
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_H_GPI_GPE_STS 0x0144
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_GPI_GPE_STS 0x0148
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_S_GPI_GPE_EN 0x0160
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_H_GPI_GPE_EN 0x0164
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_GPI_GPE_EN 0x0168
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_SMI_STS 0x0188
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_SMI_EN 0x01A8
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_NMI_STS 0x01C8
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_NMI_EN 0x01E8
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_S_PADCFG_OFFSET 0x700
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_H_PADCFG_OFFSET 0x780
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_PADCFG_OFFSET 0x900
+//
+// GPIO Community 2 Private Configuration Registers
+//
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPD_PAD_OWN 0x20
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPD_PADCFGLOCK 0x80
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPD_PADCFGLOCKTX 0x84
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPD_HOSTSW_OWN 0xB0
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPD_GPI_IS 0x0100
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPD_GPI_IE 0x0120
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPD_GPI_GPE_STS 0x0140
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPD_GPI_GPE_EN 0x0160
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPD_PADCFG_OFFSET 0x700
+
+//
+// GPIO Community 4 Private Configuration Registers
+//
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_PAD_OWN 0x20
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_F_PAD_OWN 0x2C
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_PAD_OWN 0x40
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_PADCFGLOCK 0x80
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_PADCFGLOCKTX 0x84
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_F_PADCFGLOCK 0x88
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_F_PADCFGLOCKTX 0x8C
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_PADCFGLOCK 0x98
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_PADCFGLOCKTX 0x9C
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_HOSTSW_OWN 0xB0
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_F_HOSTSW_OWN 0xB4
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_HOSTSW_OWN 0xBC
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_GPI_IS 0x0100
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_F_GPI_IS 0x0104
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_GPI_IS 0x010C
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_GPI_IE 0x0120
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_F_GPI_IE 0x0124
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_GPI_IE 0x012C
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_GPI_GPE_STS 0x0140
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_F_GPI_GPE_STS 0x0144
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_GPI_GPE_STS 0x014C
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_GPI_GPE_EN 0x0160
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_F_GPI_GPE_EN 0x0164
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_GPI_GPE_EN 0x016C
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_SMI_STS 0x0180
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_SMI_STS 0x018C
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_SMI_EN 0x01A0
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_SMI_EN 0x01AC
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_NMI_STS 0x01C0
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_NMI_STS 0x01CC
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_NMI_EN 0x01E0
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_NMI_EN 0x01EC
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_PADCFG_OFFSET 0x700
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_F_PADCFG_OFFSET 0x880
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_PADCFG_OFFSET 0xA70
+
+//
+// GPIO Community 5 Private Configuration Registers
+//
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_R_PAD_OWN 0x20
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_R_PADCFGLOCK 0x80
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_R_PADCFGLOCKTX 0x84
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_R_HOSTSW_OWN 0xB0
+
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_R_GPI_IS 0x0100
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_R_GPI_IE 0x0120
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_R_GPI_GPE_STS 0x0140
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_R_GPI_GPE_EN 0x0160
+#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_R_PADCFG_OFFSET 0x700
+
+#endif // _GPIO_REGS_VER2_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/PchDmi14Regs.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/PchDmi14Regs.h
new file mode 100644
index 0000000000..f30bf62614
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/PchDmi14Regs.h
@@ -0,0 +1,49 @@
+/** @file
+ Register names for PCH DMI SIP14
+
+Conventions:
+
+ - Register definition format:
+ Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_RegisterName
+ - Prefix:
+ Definitions beginning with "R_" are registers
+ Definitions beginning with "B_" are bits within registers
+ Definitions beginning with "V_" are meaningful values within the bits
+ Definitions beginning with "S_" are register size
+ Definitions beginning with "N_" are the bit position
+ - [GenerationName]:
+ Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc.).
+ Register name without GenerationName applies to all generations.
+ - [ComponentName]:
+ This field indicates the component name that the register belongs to (e.g. PCH, SA etc.)
+ Register name without ComponentName applies to all components.
+ Register that is specific to -H denoted by "_PCH_H_" in component name.
+ Register that is specific to -LP denoted by "_PCH_LP_" in component name.
+ - SubsystemName:
+ This field indicates the subsystem name of the component that the register belongs to
+ (e.g. PCIE, USB, SATA, GPIO, PMC etc.).
+ - RegisterSpace:
+ MEM - MMIO space register of subsystem.
+ IO - IO space register of subsystem.
+ PCR - Private configuration register of subsystem.
+ CFG - PCI configuration space register of subsystem.
+ - RegisterName:
+ Full register name.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _PCH_DMI14_REGS_H_
+#define _PCH_DMI14_REGS_H_
+
+//
+// DMI Chipset Configuration Registers (PID:DMI)
+//
+
+//
+// DMI Control
+//
+#define R_PCH_DMI14_PCR_DMIC 0x2234 ///< DMI Control
+#define B_PCH_DMI14_PCR_DMIC_SRL BIT31 ///< Secured register lock
+
+#endif
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/PchDmiRegs.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/PchDmiRegs.h
new file mode 100644
index 0000000000..649e8dd17b
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/PchDmiRegs.h
@@ -0,0 +1,51 @@
+/** @file
+ Register names for PCH DMI and OP-DMI
+
+Conventions:
+
+ - Register definition format:
+ Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_RegisterName
+ - Prefix:
+ Definitions beginning with "R_" are registers
+ Definitions beginning with "B_" are bits within registers
+ Definitions beginning with "V_" are meaningful values within the bits
+ Definitions beginning with "S_" are register size
+ Definitions beginning with "N_" are the bit position
+ - [GenerationName]:
+ Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc.).
+ Register name without GenerationName applies to all generations.
+ - [ComponentName]:
+ This field indicates the component name that the register belongs to (e.g. PCH, SA etc.)
+ Register name without ComponentName applies to all components.
+ Register that is specific to -H denoted by "_PCH_H_" in component name.
+ Register that is specific to -LP denoted by "_PCH_LP_" in component name.
+ - SubsystemName:
+ This field indicates the subsystem name of the component that the register belongs to
+ (e.g. PCIE, USB, SATA, GPIO, PMC etc.).
+ - RegisterSpace:
+ MEM - MMIO space register of subsystem.
+ IO - IO space register of subsystem.
+ PCR - Private configuration register of subsystem.
+ CFG - PCI configuration space register of subsystem.
+ - RegisterName:
+ Full register name.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _PCH_DMI_REGS_H_
+#define _PCH_DMI_REGS_H_
+
+//
+// PCH DMI Chipset Configuration Registers (PID:DMI)
+//
+
+//
+// PCH DMI Source Decode PCRs (Common)
+//
+#define R_PCH_DMI_PCR_LPCIOD 0x2770 ///< LPC I/O Decode Ranges
+#define R_PCH_DMI_PCR_LPCIOE 0x2774 ///< LPC I/O Enables
+#define R_PCH_DMI_PCR_TCOBASE 0x2778 ///< TCO Base Address
+#define B_PCH_DMI_PCR_TCOBASE_TCOBA 0xFFE0 ///< TCO Base Address Mask
+
+#endif
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/PchPcieRpRegs.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/PchPcieRpRegs.h
new file mode 100644
index 0000000000..17c68cbaaa
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/PchPcieRpRegs.h
@@ -0,0 +1,45 @@
+/** @file
+ Register names for PCH PCI-E root port devices
+
+ Conventions:
+
+ - Register definition format:
+ Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_RegisterName
+ - Prefix:
+ Definitions beginning with "R_" are registers
+ Definitions beginning with "B_" are bits within registers
+ Definitions beginning with "V_" are meaningful values within the bits
+ Definitions beginning with "S_" are register size
+ Definitions beginning with "N_" are the bit position
+ - [GenerationName]:
+ Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc.).
+ Register name without GenerationName applies to all generations.
+ - [ComponentName]:
+ This field indicates the component name that the register belongs to (e.g. PCH, SA etc.)
+ Register name without ComponentName applies to all components.
+ Register that is specific to -H denoted by "_PCH_H_" in component name.
+ Register that is specific to -LP denoted by "_PCH_LP_" in component name.
+ - SubsystemName:
+ This field indicates the subsystem name of the component that the register belongs to
+ (e.g. PCIE, USB, SATA, GPIO, PMC etc.).
+ - RegisterSpace:
+ MEM - MMIO space register of subsystem.
+ IO - IO space register of subsystem.
+ PCR - Private configuration register of subsystem.
+ CFG - PCI configuration space register of subsystem.
+ - RegisterName:
+ Full register name.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _PCH_REGS_PCIE_H_
+#define _PCH_REGS_PCIE_H_
+
+//
+// PCIE PCRs (PID:SPA SPB SPC SPD SPE SPF)
+//
+#define R_SPX_PCR_PCD 0 ///< Port configuration and disable
+#define B_SPX_PCR_PCD_RP1FN (BIT2 | BIT1 | BIT0) ///< Port 1 Function Number
+#define S_SPX_PCR_PCD_RP_FIELD 4 ///< 4 bits for each RP FN
+#endif
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/PchRegsLpc.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/PchRegsLpc.h
new file mode 100644
index 0000000000..326b266352
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/PchRegsLpc.h
@@ -0,0 +1,77 @@
+/** @file
+ Register names for PCH LPC/eSPI device
+
+Conventions:
+
+ - Register definition format:
+ Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_RegisterName
+ - Prefix:
+ Definitions beginning with "R_" are registers
+ Definitions beginning with "B_" are bits within registers
+ Definitions beginning with "V_" are meaningful values within the bits
+ Definitions beginning with "S_" are register size
+ Definitions beginning with "N_" are the bit position
+ - [GenerationName]:
+ Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc.).
+ Register name without GenerationName applies to all generations.
+ - [ComponentName]:
+ This field indicates the component name that the register belongs to (e.g. PCH, SA etc.)
+ Register name without ComponentName applies to all components.
+ Register that is specific to -H denoted by "_PCH_H_" in component name.
+ Register that is specific to -LP denoted by "_PCH_LP_" in component name.
+ - SubsystemName:
+ This field indicates the subsystem name of the component that the register belongs to
+ (e.g. PCIE, USB, SATA, GPIO, PMC etc.).
+ - RegisterSpace:
+ MEM - MMIO space register of subsystem.
+ IO - IO space register of subsystem.
+ PCR - Private configuration register of subsystem.
+ CFG - PCI configuration space register of subsystem.
+ - RegisterName:
+ Full register name.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _PCH_REGS_LPC_H_
+#define _PCH_REGS_LPC_H_
+
+//
+// PCI to LPC Bridge Registers
+//
+
+#define R_LPC_CFG_IOD 0x80
+#define R_LPC_CFG_IOE 0x82
+#define R_ESPI_CFG_CS1IORE 0xA0
+
+#define R_LPC_CFG_ULKMC 0x94
+#define B_LPC_CFG_ULKMC_A20PASSEN BIT5
+#define B_LPC_CFG_ULKMC_64WEN BIT3
+#define B_LPC_CFG_ULKMC_64REN BIT2
+#define B_LPC_CFG_ULKMC_60WEN BIT1
+#define B_LPC_CFG_ULKMC_60REN BIT0
+
+//
+// APM Registers
+//
+#define R_PCH_IO_APM_CNT 0xB2
+#define R_PCH_IO_APM_STS 0xB3
+#define R_LPC_CFG_BC 0xDC ///< Bios Control
+#define S_LPC_CFG_BC 1
+#define N_LPC_CFG_BC_LE 1
+
+//
+// Reset Generator I/O Port
+//
+#define R_PCH_IO_RST_CNT 0xCF9
+#define V_PCH_IO_RST_CNT_FULLRESET 0x0E
+#define V_PCH_IO_RST_CNT_HARDRESET 0x06
+//
+// eSPI PCR Registers
+//
+#define R_ESPI_PCR_CFG_VAL 0xC00C ///< ESPI Enabled Strap
+#define B_ESPI_PCR_CFG_VAL_ESPI_EN BIT0 ///< ESPI Enabled Strap bit position
+#define R_ESPI_PCR_SOFTSTRAPS 0xC210 ///< eSPI Sofstraps Register 0
+#define B_ESPI_PCR_SOFTSTRAPS_CS1_EN BIT12 ///< CS1# Enable
+
+#endif
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/PmcRegs.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/PmcRegs.h
new file mode 100644
index 0000000000..f7153b931c
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/PmcRegs.h
@@ -0,0 +1,134 @@
+/** @file
+ Register names for PCH PMC device
+
+ Conventions:
+
+ - Register definition format:
+ Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_RegisterName
+ - Prefix:
+ Definitions beginning with "R_" are registers
+ Definitions beginning with "B_" are bits within registers
+ Definitions beginning with "V_" are meaningful values within the bits
+ Definitions beginning with "S_" are register size
+ Definitions beginning with "N_" are the bit position
+ - [GenerationName]:
+ Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc.).
+ Register name without GenerationName applies to all generations.
+ - [ComponentName]:
+ This field indicates the component name that the register belongs to (e.g. PCH, SA etc.)
+ Register name without ComponentName applies to all components.
+ Register that is specific to -H denoted by "_PCH_H_" in component name.
+ Register that is specific to -LP denoted by "_PCH_LP_" in component name.
+ - SubsystemName:
+ This field indicates the subsystem name of the component that the register belongs to
+ (e.g. PCIE, USB, SATA, GPIO, PMC etc.).
+ - RegisterSpace:
+ MEM - MMIO space register of subsystem.
+ IO - IO space register of subsystem.
+ PCR - Private configuration register of subsystem.
+ CFG - PCI configuration space register of subsystem.
+ - RegisterName:
+ Full register name.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _PCH_REGS_PMC_H_
+#define _PCH_REGS_PMC_H_
+
+//
+// ACPI and legacy I/O register offsets from ACPIBASE
+//
+#define R_ACPI_IO_PM1_STS 0x00
+#define S_ACPI_IO_PM1_STS 2
+#define B_ACPI_IO_PM1_STS_PRBTNOR BIT11
+#define B_ACPI_IO_PM1_STS_PWRBTN BIT8
+#define N_ACPI_IO_PM1_STS_RTC 10
+#define N_ACPI_IO_PM1_STS_PWRBTN 8
+#define N_ACPI_IO_PM1_STS_TMROF 0
+
+#define R_ACPI_IO_PM1_EN 0x02
+#define S_ACPI_IO_PM1_EN 2
+#define B_ACPI_IO_PM1_EN_PWRBTN BIT8
+#define N_ACPI_IO_PM1_EN_RTC 10
+#define N_ACPI_IO_PM1_EN_PWRBTN 8
+#define N_ACPI_IO_PM1_EN_TMROF 0
+
+#define R_ACPI_IO_PM1_CNT 0x04 ///< Power Management 1 Control
+#define B_ACPI_IO_PM1_CNT_SLP_EN BIT13 ///< Sleep Enable
+#define B_ACPI_IO_PM1_CNT_SLP_TYP (BIT12 | BIT11 | BIT10) ///< Sleep Type
+#define V_ACPI_IO_PM1_CNT_S0 0
+#define V_ACPI_IO_PM1_CNT_S1 BIT10
+#define V_ACPI_IO_PM1_CNT_S3 (BIT12 | BIT10)
+#define V_ACPI_IO_PM1_CNT_S4 (BIT12 | BIT11)
+#define V_ACPI_IO_PM1_CNT_S5 (BIT12 | BIT11 | BIT10)
+#define B_ACPI_IO_PM1_CNT_SCI_EN BIT0 ///< SCI Enable
+
+#define R_ACPI_IO_PM1_TMR 0x08 ///< Power Management 1 Timer
+#define B_ACPI_IO_PM1_TMR_TMR_VAL 0xFFFFFF ///< Timer Value
+#define V_ACPI_IO_PM1_TMR_MAX_VAL 0x1000000 ///< The timer is 24 bit overflow
+
+#define R_ACPI_IO_SMI_EN 0x30 ///< SMI Control and Enable
+#define S_ACPI_IO_SMI_EN 4
+#define B_ACPI_IO_SMI_EN_LEGACY_USB2 BIT17
+#define B_ACPI_IO_SMI_EN_TCO BIT13
+#define B_ACPI_IO_SMI_EN_SWSMI_TMR BIT6
+#define B_ACPI_IO_SMI_EN_APMC BIT5
+#define B_ACPI_IO_SMI_EN_LEGACY_USB BIT3
+#define B_ACPI_IO_SMI_EN_EOS BIT1 ///< End of SMI
+#define B_ACPI_IO_SMI_EN_GBL_SMI BIT0
+#define N_ACPI_IO_SMI_EN_LEGACY_USB3 31
+#define N_ACPI_IO_SMI_EN_PERIODIC 14
+#define N_ACPI_IO_SMI_EN_TCO 13
+#define N_ACPI_IO_SMI_EN_MCSMI 11
+#define N_ACPI_IO_SMI_EN_SWSMI_TMR 6
+#define N_ACPI_IO_SMI_EN_APMC 5
+#define N_ACPI_IO_SMI_EN_ON_SLP_EN 4
+#define N_ACPI_IO_SMI_EN_LEGACY_USB 3
+
+#define R_ACPI_IO_SMI_STS 0x34 ///< SMI Status Register
+#define S_ACPI_IO_SMI_STS 4
+#define B_ACPI_IO_SMI_STS_GPIO_UNLOCK BIT27
+#define B_ACPI_IO_SMI_STS_TCO BIT13
+#define B_ACPI_IO_SMI_STS_APM BIT5
+#define N_ACPI_IO_SMI_STS_LEGACY_USB3 31
+#define N_ACPI_IO_SMI_STS_SPI 26
+#define N_ACPI_IO_SMI_STS_SMBUS 16
+#define N_ACPI_IO_SMI_STS_SERIRQ 15
+#define N_ACPI_IO_SMI_STS_PERIODIC 14
+#define N_ACPI_IO_SMI_STS_TCO 13
+#define N_ACPI_IO_SMI_STS_MCSMI 11
+#define N_ACPI_IO_SMI_STS_GPIO_SMI 10
+#define N_ACPI_IO_SMI_STS_GPE0 9
+#define N_ACPI_IO_SMI_STS_PM1_STS_REG 8
+#define N_ACPI_IO_SMI_STS_SWSMI_TMR 6
+#define N_ACPI_IO_SMI_STS_APM 5
+#define N_ACPI_IO_SMI_STS_ON_SLP_EN 4
+#define N_ACPI_IO_SMI_STS_LEGACY_USB 3
+
+#define R_ACPI_IO_GPE0_STS_127_96 0x6C ///< General Purpose Event 0 Status [127:96]
+#define S_ACPI_IO_GPE0_STS_127_96 4
+#define B_ACPI_IO_GPE0_STS_127_96_WADT BIT18
+#define N_ACPI_IO_GPE0_STS_127_96_PME_B0 13
+#define N_ACPI_IO_GPE0_STS_127_96_PME 11
+#define R_ACPI_IO_GPE0_EN_127_96 0x7C ///< General Purpose Event 0 Enable [127:96]
+#define S_ACPI_IO_GPE0_EN_127_96 4
+#define B_ACPI_IO_GPE0_EN_127_96_WADT BIT18
+#define N_ACPI_IO_GPE0_EN_127_96_PME_B0 13
+#define N_ACPI_IO_GPE0_EN_127_96_PME 11
+
+//
+// PWRM Registers
+//
+#define R_PMC_PWRM_GEN_PMCON_A 0x1020 ///< General PM Configuration A
+#define B_PMC_PWRM_GEN_PMCON_A_SWSMI_RTSL 0xC0
+#define V_PMC_PWRM_GEN_PMCON_A_SWSMI_RTSL_64MS 0xC0
+#define V_PMC_PWRM_GEN_PMCON_A_SWSMI_RTSL_32MS 0x80
+#define V_PMC_PWRM_GEN_PMCON_A_SWSMI_RTSL_16MS 0x40
+#define V_PMC_PWRM_GEN_PMCON_A_SWSMI_RTSL_1_5MS 0x00
+#define B_PMC_PWRM_GEN_PMCON_A_PER_SMI_SEL (BIT2|BIT1) ///< Period SMI Select
+#define V_PMC_PWRM_GEN_PMCON_A_PER_SMI_64S 0x0000
+#define V_PMC_PWRM_GEN_PMCON_A_PER_SMI_32S 0x0002
+#define V_PMC_PWRM_GEN_PMCON_A_PER_SMI_16S 0x0004
+#define V_PMC_PWRM_GEN_PMCON_A_PER_SMI_8S 0x0006
+#endif
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/RtcRegs.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/RtcRegs.h
new file mode 100644
index 0000000000..8424ef5897
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/RtcRegs.h
@@ -0,0 +1,44 @@
+/** @file
+ Register names for RTC device
+
+Conventions:
+
+ - Register definition format:
+ Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_RegisterName
+ - Prefix:
+ Definitions beginning with "R_" are registers
+ Definitions beginning with "B_" are bits within registers
+ Definitions beginning with "V_" are meaningful values within the bits
+ Definitions beginning with "S_" are register size
+ Definitions beginning with "N_" are the bit position
+ - [GenerationName]:
+ Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc.).
+ Register name without GenerationName applies to all generations.
+ - [ComponentName]:
+ This field indicates the component name that the register belongs to (e.g. PCH, SA etc.)
+ Register name without ComponentName applies to all components.
+ Register that is specific to -H denoted by "_PCH_H_" in component name.
+ Register that is specific to -LP denoted by "_PCH_LP_" in component name.
+ - SubsystemName:
+ This field indicates the subsystem name of the component that the register belongs to
+ (e.g. PCIE, USB, SATA, GPIO, PMC etc.).
+ - RegisterSpace:
+ MEM - MMIO space register of subsystem.
+ IO - IO space register of subsystem.
+ PCR - Private configuration register of subsystem.
+ CFG - PCI configuration space register of subsystem.
+ - RegisterName:
+ Full register name.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _REGS_RTC_H_
+#define _REGS_RTC_H_
+
+#define R_RTC_IO_INDEX_ALT 0x74
+#define R_RTC_IO_TARGET_ALT 0x75
+#define R_RTC_IO_EXT_INDEX_ALT 0x76
+#define R_RTC_IO_REGD 0x0D
+
+#endif
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/TcoRegs.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/TcoRegs.h
new file mode 100644
index 0000000000..c3afcd5079
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/Register/TcoRegs.h
@@ -0,0 +1,71 @@
+/** @file
+ Register names for PCH TCO device
+
+ Conventions:
+
+ - Register definition format:
+ Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_RegisterName
+ - Prefix:
+ Definitions beginning with "R_" are registers
+ Definitions beginning with "B_" are bits within registers
+ Definitions beginning with "V_" are meaningful values within the bits
+ Definitions beginning with "S_" are register size
+ Definitions beginning with "N_" are the bit position
+ - [GenerationName]:
+ Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc.).
+ Register name without GenerationName applies to all generations.
+ - [ComponentName]:
+ This field indicates the component name that the register belongs to (e.g. PCH, SA etc.)
+ Register name without ComponentName applies to all components.
+ Register that is specific to -H denoted by "_PCH_H_" in component name.
+ Register that is specific to -LP denoted by "_PCH_LP_" in component name.
+ - SubsystemName:
+ This field indicates the subsystem name of the component that the register belongs to
+ (e.g. PCIE, USB, SATA, GPIO, PMC etc.).
+ - RegisterSpace:
+ MEM - MMIO space register of subsystem.
+ IO - IO space register of subsystem.
+ PCR - Private configuration register of subsystem.
+ CFG - PCI configuration space register of subsystem.
+ - RegisterName:
+ Full register name.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _TCO_REGS_H_
+#define _TCO_REGS_H_
+
+//
+// TCO register I/O map
+//
+#define R_TCO_IO_TCO1_STS 0x04
+#define S_TCO_IO_TCO1_STS 2
+#define B_TCO_IO_TCO1_STS_DMISERR BIT12
+#define B_TCO_IO_TCO1_STS_DMISMI BIT10
+#define B_TCO_IO_TCO1_STS_DMISCI BIT9
+#define B_TCO_IO_TCO1_STS_BIOSWR BIT8
+#define B_TCO_IO_TCO1_STS_NEWCENTURY BIT7
+#define B_TCO_IO_TCO1_STS_TIMEOUT BIT3
+#define B_TCO_IO_TCO1_STS_TCO_INT BIT2
+#define B_TCO_IO_TCO1_STS_SW_TCO_SMI BIT1
+#define N_TCO_IO_TCO1_STS_DMISMI 10
+#define N_TCO_IO_TCO1_STS_BIOSWR 8
+#define N_TCO_IO_TCO1_STS_NEWCENTURY 7
+#define N_TCO_IO_TCO1_STS_TIMEOUT 3
+#define N_TCO_IO_TCO1_STS_SW_TCO_SMI 1
+#define N_TCO_IO_TCO1_STS_NMI2SMI 0
+
+#define R_TCO_IO_TCO2_STS 0x06
+#define S_TCO_IO_TCO2_STS 2
+#define N_TCO_IO_TCO2_STS_INTRD_DET 0
+
+#define R_TCO_IO_TCO1_CNT 0x08
+#define S_TCO_IO_TCO1_CNT 2
+#define N_TCO_IO_TCO1_CNT_NMI2SMI_EN 9
+
+#define R_TCO_IO_TCO2_CNT 0x0A
+#define S_TCO_IO_TCO2_CNT 2
+#define N_TCO_IO_TCO2_CNT_INTRD_SEL 2
+
+#endif
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/SerialIoDevices.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/SerialIoDevices.h
new file mode 100644
index 0000000000..1829fb90ff
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/SerialIoDevices.h
@@ -0,0 +1,226 @@
+/** @file
+ Serial IO policy
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _SERIAL_IO_DEVICES_H_
+#define _SERIAL_IO_DEVICES_H_
+
+#include <Protocol/SerialIo.h>
+#include <PchLimits.h>
+
+#pragma pack (push,1)
+
+/**
+ Available working modes for SerialIo SPI Host Controller
+
+ 0: SerialIoSpiDisabled;
+ - Device is placed in D3
+ - Gpio configuration is skipped
+ - PSF:
+ !important! If given device is Function 0 and other higher functions on given device
+ are enabled, PSF disabling is skipped. PSF default will remain and device PCI CFG Space will still be visible.
+ This is needed to allow PCI enumerator access functions above 0 in a multifunction device.
+ <b>1: SerialIoSpiPci;</b>
+ - Gpio pin configuration in native mode for each assigned pin
+ - Device will be enabled in PSF
+ - Only BAR0 will be enabled
+ 2: SerialIoSpiHidden;
+ - Gpio pin configuration in native mode for each assigned pin
+ - Device disabled in the PSF
+ - Both BARs are enabled, BAR1 becomes devices Pci Config Space
+ - BAR0 assigned from the global PCH reserved memory range, reported as motherboard resource by SIRC
+ @note
+ If this controller is located at function 0 and it's mode is set to hidden it will not be visible in the PCI space.
+**/
+typedef enum {
+ SerialIoSpiDisabled,
+ SerialIoSpiPci,
+ SerialIoSpiHidden
+} SERIAL_IO_SPI_MODE;
+
+/**
+ Used to set Inactive/Idle polarity of Spi Chip Select
+**/
+typedef enum {
+ SerialIoSpiCsActiveLow = 0,
+ SerialIoSpiCsActiveHigh = 1
+} SERIAL_IO_CS_POLARITY;
+
+/**
+ SPI signals pin muxing settings. If signal can be enable only on a single pin
+ then this parameter is ignored by RC. Refer to GPIO_*_MUXING_SERIALIO_SPIx_* in GpioPins*.h
+ for supported settings on a given platform
+**/
+typedef struct {
+ UINT32 Cs[PCH_MAX_SERIALIO_SPI_CHIP_SELECTS]; ///< CS Pin mux configuration. Refer to GPIO_*_MUXING_SERIALIO_SPIx_CS_*
+ UINT32 Clk; ///< CLK Pin mux configuration. Refer to GPIO_*_MUXING_SERIALIO_SPIx_CLK_*
+ UINT32 Miso; ///< MISO Pin mux configuration. Refer to GPIO_*_MUXING_SERIALIO_SPIx_MISO_*
+ UINT32 Mosi; ///< MOSI Pin mux configuration. Refer to GPIO_*_MUXING_SERIALIO_SPIx_MOSI_*
+} SPI_PIN_MUX;
+
+/**
+ The SERIAL_IO_SPI_CONFIG provides the configurations to set the Serial IO SPI controller
+**/
+typedef struct {
+ UINT8 Mode; ///< <b>SerialIoSpiPci </b> see SERIAL_IO_SPI_MODE
+ UINT8 DefaultCsOutput; ///< <b>0 = CS0</b> CS1, CS2, CS3. Default CS used by the SPI HC
+ UINT8 CsPolarity[PCH_MAX_SERIALIO_SPI_CHIP_SELECTS]; ///< Selects SPI ChipSelect signal polarity, 0 = low <b>1 = High</b>
+ UINT8 CsEnable[PCH_MAX_SERIALIO_SPI_CHIP_SELECTS]; ///< <b>0 = Enable</b> 1 = Disable. Based on this setting GPIO for given SPIx CSx will be configured in Native mode
+ UINT8 CsMode; ///< <b>0 = HW Control</b> 1 = SW Control. Sets Chip Select Control mode Hardware or Software.
+ UINT8 CsState; ///< <b>0 = CS is set to low</b> 1 = CS is set to high
+ SPI_PIN_MUX PinMux; ///< SPI Pinmux configuration
+} SERIAL_IO_SPI_CONFIG;
+
+/**
+ Available working modes for SerialIo UART Host Controller
+
+ 0: SerialIoUartDisabled;
+ - Device is placed in D3
+ - Gpio configuration is skipped
+ - PSF:
+ !important! If given device is Function 0 and other higher functions on given device
+ are enabled, PSF disabling is skipped. PSF default will remain and device PCI CFG Space will still be visible.
+ This is needed to allow PCI enumerator access functions above 0 in a multifunction device.
+ <b>1: SerialIoUartPci;</b>
+ - Designated for Serial IO UART OS driver usage
+ - Gpio pin configuration in native mode for each assigned pin
+ - Device will be enabled in PSF
+ - Only BAR0 will be enabled
+ 2: SerialIoUartHidden;
+ - Designated for BIOS and/or DBG2 OS kernel debug
+ - Gpio pin configuration in native mode for each assigned pin
+ - Device disabled in the PSF
+ - Both BARs are enabled, BAR1 becomes devices Pci Config Space
+ - BAR0 assigned from the global PCH reserved memory range, reported as motherboard resource by SIRC
+ @note
+ If this controller is located at function 0 and it's mode is set to hidden it will not be visible in the PCI space.
+ 3: SerialIoUartCom;
+ - Designated for 16550/PNP0501 compatible COM device
+ - Gpio pin configuration in native mode for each assigned pin
+ - Device disabled in the PSF
+ - Both BARs are enabled, BAR1 becomes devices Pci Config Space
+ - BAR0 assigned from the global PCH reserved memory range, reported as motherboard resource by SIRC
+ 4: SerialIoUartSkipInit;
+ - Gpio configuration is skipped
+ - PSF configuration is skipped
+ - BAR assignemnt is skipped
+ - D-satate setting is skipped
+
+**/
+typedef enum {
+ SerialIoUartDisabled,
+ SerialIoUartPci,
+ SerialIoUartHidden,
+ SerialIoUartCom,
+ SerialIoUartSkipInit
+} SERIAL_IO_UART_MODE;
+
+/**
+ UART Settings
+**/
+typedef struct {
+ UINT32 BaudRate; ///< <b> 115200 </b> Max 6000000 MdePkg.dec PcdUartDefaultBaudRate
+ UINT8 Parity; ///< <b> 1 - No Parity</b> see EFI_PARITY_TYPE MdePkg.dec PcdUartDefaultParity
+ UINT8 DataBits; ///< <b>8</b> MdePkg.dec PcdUartDefaultDataBits
+ UINT8 StopBits; ///< <b>1 - One Stop Bit</b> see EFI_STOP_BITS_TYPE MdePkg.dec PcdUartDefaultStopBits
+ UINT8 AutoFlow; ///< <b>FALSE</b> IntelFrameworkModulePkg.dsc PcdIsaBusSerialUseHalfHandshake
+} SERIAL_IO_UART_ATTRIBUTES;
+
+/**
+ UART signals pin muxing settings. If signal can be enable only on a single pin
+ then this parameter is ignored by RC. Refer to GPIO_*_MUXING_SERIALIO_UARTx_* in GpioPins*.h
+ for supported settings on a given platform
+**/
+typedef struct {
+ UINT32 Rx; ///< RXD Pin mux configuration. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RXD_*
+ UINT32 Tx; ///< TXD Pin mux configuration. Refer to GPIO_*_MUXING_SERIALIO_UARTx_TXD_*
+ UINT32 Rts; ///< RTS Pin mux configuration. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RTS_*
+ UINT32 Cts; ///< CTS Pin mux configuration. Refer to GPIO_*_MUXING_SERIALIO_UARTx_CTS_*
+} UART_PIN_MUX;
+
+/**
+ Serial IO UART Controller Configuration
+**/
+typedef struct {
+ SERIAL_IO_UART_ATTRIBUTES Attributes; ///< see SERIAL_IO_UART_ATTRIBUTES
+ UART_PIN_MUX PinMux; ///< UART pin mux configuration
+ UINT8 Mode; ///< <b> SerialIoUartPci </b> see SERIAL_IO_UART_MODE
+ UINT8 DBG2; ///< <b> FALSE </b> If TRUE adds UART to DBG2 table and overrides UartPg to SerialIoUartPgDisabled
+ UINT8 PowerGating; ///< <b> SerialIoUartPgAuto </b> Applies to Hidden/COM/SkipInit see SERIAL_IO_UART_PG
+ UINT8 DmaEnable; ///< <b> TRUE </b> Applies to SerialIoUartPci only. Informs OS driver to use DMA, if false it will run in PIO mode
+} SERIAL_IO_UART_CONFIG;
+
+typedef enum {
+ SerialIoUartPgDisabled, ///< No _PS0/_PS3 support, device left in D0, after initialization
+/**
+ In mode: SerialIoUartCom;
+ _PS0/_PS3 that supports getting device out of reset
+ In mode: SerialIoUartPci
+ Keeps UART in D0 and assigns Fixed MMIO for SEC/PEI usage only
+**/
+ SerialIoUartPgEnabled,
+ SerialIoUartPgAuto ///< _PS0 and _PS3, detection through ACPI if device was initialized prior to first PG. If it was used (DBG2) PG is disabled,
+} SERIAL_IO_UART_PG;
+
+/**
+ Available working modes for SerialIo I2C Host Controller
+
+ 0: SerialIoI2cDisabled;
+ - Device is placed in D3
+ - Gpio configuration is skipped
+ - PSF:
+ !important! If given device is Function 0 and other higher functions on given device
+ are enabled, PSF disabling is skipped. PSF default will remain and device PCI CFG Space will still be visible.
+ This is needed to allow PCI enumerator access functions above 0 in a multifunction device.
+ <b>1: SerialIoI2cPci;</b>
+ - Gpio pin configuration in native mode for each assigned pin
+ - Device will be enabled in PSF
+ - Only BAR0 will be enabled
+ 2: SerialIoI2cHidden;
+ - Gpio pin configuration in native mode for each assigned pin
+ - Device disabled in the PSF
+ - Both BARs are enabled, BAR1 becomes devices Pci Config Space
+ - BAR0 assigned from the global PCH reserved memory range, reported as motherboard resource by SIRC
+ @note
+ If this controller is located at function 0 and it's mode is set to hidden it will not be visible in the PCI space.
+**/
+typedef enum {
+ SerialIoI2cDisabled,
+ SerialIoI2cPci,
+ SerialIoI2cHidden
+} SERIAL_IO_I2C_MODE;
+
+/**
+ I2C signals pin muxing settings. If signal can be enable only on a single pin
+ then this parameter is ignored by RC. Refer to GPIO_*_MUXING_SERIALIO_I2Cx_* in GpioPins*.h
+ for supported settings on a given platform
+**/
+typedef struct {
+ UINT32 Sda; ///< SDA Pin mux configuration. Refer to GPIO_*_MUXING_SERIALIO_I2Cx_SDA_*
+ UINT32 Scl; ///< SCL Pin mux configuration. Refer to GPIO_*_MUXING_SERIALIO_I2Cx_SCL_*
+} I2C_PIN_MUX;
+
+/**
+ Serial IO I2C Controller Configuration
+**/
+typedef struct {
+ UINT8 Mode; /// <b>SerialIoI2cPci <b> see SERIAL_IO_I2C_MODE
+ /**
+ I2C Pads Internal Termination.
+ For more information please see Platform Design Guide.
+ Supported values (check GPIO_ELECTRICAL_CONFIG for reference):
+ <b>GpioTermNone: No termination</b>,
+ GpioTermWpu1K: 1kOhm weak pull-up,
+ GpioTermWpu5K: 5kOhm weak pull-up,
+ GpioTermWpu20K: 20kOhm weak pull-up
+ **/
+ UINT8 PadTermination;
+ UINT8 Reserved[2];
+ I2C_PIN_MUX PinMux; ///< I2C pin mux configuration
+} SERIAL_IO_I2C_CONFIG;
+
+#pragma pack (pop)
+
+#endif // _SERIAL_IO_DEVICES_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/SiConfigHob.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/SiConfigHob.h
new file mode 100644
index 0000000000..089141d143
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/SiConfigHob.h
@@ -0,0 +1,17 @@
+/** @file
+ Silicon Config HOB is used for gathering platform
+ related Intel silicon information and config setting.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _SI_CONFIG_HOB_H_
+#define _SI_CONFIG_HOB_H_
+
+#include <SiPolicyStruct.h>
+
+extern EFI_GUID gSiConfigHobGuid;
+
+// Rename SI_CONFIG_HOB into SI_CONFIG_HOB_DATA for it does not follow HOB structure.
+typedef CONST SI_CONFIG SI_CONFIG_HOB_DATA;
+#endif
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Include/SiPolicyStruct.h b/Silicon/Intel/AlderlakeSiliconPkg/Include/SiPolicyStruct.h
new file mode 100644
index 0000000000..4dacba242e
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Include/SiPolicyStruct.h
@@ -0,0 +1,64 @@
+/** @file
+ Intel reference code configuration policies.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _SI_POLICY_STRUCT_H_
+#define _SI_POLICY_STRUCT_H_
+
+#include <ConfigBlock.h>
+#include <ConfigBlock/SiPreMemConfig.h>
+#include <ConfigBlock/SiConfig.h>
+
+/**
+ Silicon Policy revision number
+ Any change to this structure will result in an update in the revision number
+
+ This member specifies the revision of the Silicon Policy. This field is used to indicate change
+ to the policy structure.
+
+ <b>Revision 1</b>:
+ - Initial version.
+**/
+#define SI_POLICY_REVISION 1
+
+/**
+ Silicon pre-memory Policy revision number
+ Any change to this structure will result in an update in the revision number
+
+ <b>Revision 1</b>:
+ - Initial version.
+**/
+#define SI_PREMEM_POLICY_REVISION 1
+
+
+/**
+ SI Policy PPI in Pre-Mem\n
+ All SI config block change history will be listed here\n\n
+
+ - <b>Revision 1</b>:
+ - Initial version.\n
+**/
+struct _SI_PREMEM_POLICY_STRUCT {
+ CONFIG_BLOCK_TABLE_HEADER TableHeader; ///< Config Block Table Header
+/*
+ Individual Config Block Structures are added here in memory as part of AddConfigBlock()
+*/
+};
+
+/**
+ SI Policy PPI\n
+ All SI config block change history will be listed here\n\n
+
+ - <b>Revision 1</b>:
+ - Initial version.\n
+**/
+struct _SI_POLICY_STRUCT {
+ CONFIG_BLOCK_TABLE_HEADER TableHeader; ///< Config Block Table Header
+/*
+ Individual Config Block Structures are added here in memory as part of AddConfigBlock()
+*/
+};
+
+#endif
--
2.36.1.windows.1
-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#108743): https://edk2.groups.io/g/devel/message/108743
Mute This Topic: https://groups.io/mt/101373951/7686176
Group Owner: devel+owner@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [rebecca@openfw.io]
-=-=-=-=-=-=-=-=-=-=-=-
^ permalink raw reply related [flat|nested] 41+ messages in thread
* Re: [edk2-devel] [PATCH v2 08/10] AlderlakeSiliconPkg/Fru: Add AdlCpu Fru
2023-09-15 4:45 ` [edk2-devel] [PATCH v2 08/10] AlderlakeSiliconPkg/Fru: Add AdlCpu Fru Saloni Kasbekar
2023-09-15 5:43 ` Chaganty, Rangasai V
@ 2023-09-15 23:56 ` Nate DeSimone
1 sibling, 0 replies; 41+ messages in thread
From: Nate DeSimone @ 2023-09-15 23:56 UTC (permalink / raw)
To: Kasbekar, Saloni, devel@edk2.groups.io
Cc: Chaganty, Rangasai V, Chuang, Rosen
Acked-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
-----Original Message-----
From: Kasbekar, Saloni <saloni.kasbekar@intel.com>
Sent: Thursday, September 14, 2023 9:46 PM
To: devel@edk2.groups.io
Cc: Kasbekar, Saloni <saloni.kasbekar@intel.com>; Chaganty, Rangasai V <rangasai.v.chaganty@intel.com>; Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>; Chuang, Rosen <rosen.chuang@intel.com>
Subject: [PATCH v2 08/10] AlderlakeSiliconPkg/Fru: Add AdlCpu Fru
Adds the following modules:
- AdlCpu/CpuPcieRp
- AdlCpu/Include
- AdlCpu/IncludePrivate
- AdlCpu/LibraryPrivate
- AdlCpu/PeiReportCpuHob
- AdlCpu DSCs
Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Rosen Chuang <rosen.chuang@intel.com>
Signed-off-by: Saloni Kasbekar <saloni.kasbekar@intel.com>
---
.../Fru/AdlCpu/CommonLib.dsc | 9 +
.../CpuPcieInfoFruLib.c | 87 ++++++++++
.../PeiDxeSmmCpuPcieInfoFruLib.inf | 39 +++++
.../AlderlakeSiliconPkg/Fru/AdlCpu/DxeLib.dsc | 8 +
.../Fru/AdlCpu/Include/CpuGenInfo.h | 42 +++++
.../Include/Library/CpuPcieInfoFruLib.h | 45 +++++
.../Include/Register/SaRegsHostBridge.h | 64 +++++++
.../AdlCpu/IncludePrivate/CpuGenInfoFruLib.h | 44 +++++ .../AdlCpu/IncludePrivate/Register/IgdRegs.h | 34 ++++
.../BaseCpuInfoFruLib/BaseCpuInfoFruLib.c | 164 ++++++++++++++++++
.../BaseCpuInfoFruLib/BaseCpuInfoFruLib.inf | 29 ++++
.../PeiReportCpuHobLib/PeiReportCpuHobLib.c | 22 +++
.../PeiReportCpuHobLib/PeiReportCpuHobLib.inf | 26 +++
13 files changed, 613 insertions(+)
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/CommonLib.dsc
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/CpuPcieRp/Library/PeiDxeSmmCpuPcieInfoFruLib/CpuPcieInfoFruLib.c
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/CpuPcieRp/Library/PeiDxeSmmCpuPcieInfoFruLib/PeiDxeSmmCpuPcieInfoFruLib.inf
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/DxeLib.dsc
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/Include/CpuGenInfo.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/Include/Library/CpuPcieInfoFruLib.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/Include/Register/SaRegsHostBridge.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/IncludePrivate/CpuGenInfoFruLib.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/IncludePrivate/Register/IgdRegs.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/LibraryPrivate/BaseCpuInfoFruLib/BaseCpuInfoFruLib.c
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/LibraryPrivate/BaseCpuInfoFruLib/BaseCpuInfoFruLib.inf
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/PeiReportCpuHob/Library/PeiReportCpuHobLib/PeiReportCpuHobLib.c
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/PeiReportCpuHob/Library/PeiReportCpuHobLib/PeiReportCpuHobLib.inf
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/CommonLib.dsc b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/CommonLib.dsc
new file mode 100644
index 0000000000..35a3cce916
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/CommonLib.dsc
@@ -0,0 +1,9 @@
+## @file
+# Component description file for the AlderLake CPU Common FRU libraries.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+CpuPcieInfoFruLib|$(PLATFORM_SI_PACKAGE)/Fru/AdlCpu/CpuPcieRp/Library/P
+CpuPcieInfoFruLib|eiDxeSmmCpuPcieInfoFruLib/PeiDxeSmmCpuPcieInfoFruLib.
+CpuPcieInfoFruLib|inf
+CpuInfoFruLib|$(PLATFORM_SI_PACKAGE)/Fru/AdlCpu/LibraryPrivate/BaseCpuI
+CpuInfoFruLib|nfoFruLib/BaseCpuInfoFruLib.inf
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/CpuPcieRp/Library/PeiDxeSmmCpuPcieInfoFruLib/CpuPcieInfoFruLib.c b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/CpuPcieRp/Library/PeiDxeSmmCpuPcieInfoFruLib/CpuPcieInfoFruLib.c
new file mode 100644
index 0000000000..277b73fe67
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/CpuPcieRp/Library/Pei
+++ DxeSmmCpuPcieInfoFruLib/CpuPcieInfoFruLib.c
@@ -0,0 +1,87 @@
+/** @file
+ CPU PCIe information library.
+
+ All function in this library is available for PEI, DXE, and SMM, But
+ do not support UEFI RUNTIME environment call.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/ #include
+<Uefi/UefiBaseType.h> #include <Library/CpuPlatformLib.h> #include
+<Library/DebugLib.h> #include <Library/BaseLib.h> #include
+<Library/PciSegmentLib.h> #include <Register/SaRegsHostBridge.h>
+#include <Library/CpuPcieInfoFruLib.h> #include <CpuPcieInfo.h>
+
+/**
+ Get Maximum CPU Pcie Root Port Number
+
+ @retval Maximum CPU Pcie Root Port Number **/
+UINT8
+GetMaxCpuPciePortNum (
+ VOID
+ )
+{
+ switch (GetCpuSku ()) {
+ case EnumCpuUlt:
+ return CPU_PCIE_ULT_MAX_ROOT_PORT;
+ case EnumCpuUlx:
+ return CPU_PCIE_ULX_MAX_ROOT_PORT;
+ default:
+ return CPU_PCIE_ULT_MAX_ROOT_PORT;
+ }
+}
+
+/**
+ Get CPU Pcie Root Port Device and Function Number by Root Port
+physical Number
+
+ @param[in] RpNumber Root port physical number. (0-based)
+ @param[out] RpDev Return corresponding root port device number.
+ @param[out] RpFun Return corresponding root port function number.
+
+ @retval EFI_SUCCESS Root port device and function is retrieved
+ @retval EFI_INVALID_PARAMETER RpNumber is invalid
+**/
+EFI_STATUS
+EFIAPI
+GetCpuPcieRpDevFun (
+ IN UINTN RpNumber,
+ OUT UINTN *RpDev,
+ OUT UINTN *RpFun
+ )
+{
+ if (RpNumber > GetMaxCpuPciePortNum ()) {
+ DEBUG ((DEBUG_ERROR, "GetCpuPcieRpDevFun invalid RpNumber %x", RpNumber));
+ ASSERT (FALSE);
+ return EFI_INVALID_PARAMETER;
+ }
+
+ switch (RpNumber) {
+ case 0:
+ *RpDev = 6;
+ *RpFun = 0;
+ break;
+ case 1:
+ *RpDev = 1;
+ *RpFun = 0;
+ break;
+ case 2:
+ if (GetCpuSku () == EnumCpuTrad) {
+ *RpDev = 1;
+ *RpFun = 1;
+ } else {
+ *RpDev = 6;
+ *RpFun = 2;
+ }
+ break;
+ default:
+ *RpDev = 6;
+ *RpFun = 0;
+ break;
+ }
+ return EFI_SUCCESS;
+}
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/CpuPcieRp/Library/PeiDxeSmmCpuPcieInfoFruLib/PeiDxeSmmCpuPcieInfoFruLib.inf b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/CpuPcieRp/Library/PeiDxeSmmCpuPcieInfoFruLib/PeiDxeSmmCpuPcieInfoFruLib.inf
new file mode 100644
index 0000000000..f850f1a5f1
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/CpuPcieRp/Library/Pei
+++ DxeSmmCpuPcieInfoFruLib/PeiDxeSmmCpuPcieInfoFruLib.inf
@@ -0,0 +1,39 @@
+## @file
+# CPU PCIe information library for TigerLake PCH.
+#
+# All function in this library is available for PEI, DXE, and SMM, #
+But do not support UEFI RUNTIME environment call.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+
+[Defines]
+INF_VERSION = 0x00010017
+BASE_NAME = PeiDxeSmmCpuPcieInfoFruLib
+FILE_GUID = 59CA5352-ED46-4449-BF1C-0D0074C4D5B1
+VERSION_STRING = 1.0
+MODULE_TYPE = BASE
+LIBRARY_CLASS = CpuPcieInfoFruLib
+
+
+[LibraryClasses]
+IoLib
+BaseLib
+DebugLib
+PrintLib
+PciSegmentLib
+PchPcrLib
+PmcPrivateLib
+PcdLib
+ConfigBlockLib
+CpuPlatformLib
+
+[Packages]
+MdePkg/MdePkg.dec
+AlderlakeSiliconPkg/SiPkg.dec
+
+[Sources]
+CpuPcieInfoFruLib.c
+
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/DxeLib.dsc b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/DxeLib.dsc
new file mode 100644
index 0000000000..644230484e
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/DxeLib.dsc
@@ -0,0 +1,8 @@
+# @file
+# Component description file for the AlderLake CPU DXE FRU libraries.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+DxeGraphicsPolicyLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Graphics/LibraryPri
+DxeGraphicsPolicyLib|vate/DxeGraphicsPolicyLib/DxeGraphicsPolicyLib.inf
+DxeIgdOpRegionInitLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Graphics/LibraryPr
+DxeIgdOpRegionInitLib|ivate/DxeIgdOpRegionInitLib/DxeIgdOpRegionInitLib
+DxeIgdOpRegionInitLib|.inf
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/Include/CpuGenInfo.h b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/Include/CpuGenInfo.h
new file mode 100644
index 0000000000..482316829d
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/Include/CpuGenInfo.h
@@ -0,0 +1,42 @@
+/** @file
+ Header file for Cpu Information
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/ #ifndef
+_CPU_GEN_INFO_H_ #define _CPU_GEN_INFO_H_
+
+#include <CpuRegs.h>
+
+//
+// Processor Definitions
+//
+#define CPUID_FULL_FAMILY_MODEL_ALDERLAKE_MOBILE 0x000906A0
+
+///
+/// Enums for CPU Stepping IDs
+///
+typedef enum {
+
+ ///
+ /// AlderLake Mobile Steppings(ULT)
+ ///
+ EnumAdlJ0 = 0,
+ EnumAdlK0 = 2,
+ EnumAdlL0 = 3,
+
+ ///
+ /// AlderLake Mobile Steppings(ULX)
+ ///
+ EnumAdlQ0 = 1,
+ EnumAdlR0 = 4,
+ EnumAdlS0 = 5,
+
+
+ ///
+ /// Max Stepping
+ ///
+ EnumCpuSteppingMax = CPUID_FULL_STEPPING } CPU_STEPPING; #endif
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/Include/Library/CpuPcieInfoFruLib.h b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/Include/Library/CpuPcieInfoFruLib.h
new file mode 100644
index 0000000000..9dafa98631
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/Include/Library/CpuPc
+++ ieInfoFruLib.h
@@ -0,0 +1,45 @@
+/** @file
+ Header file for CpuPcieInfoFruLib.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/ #ifndef
+_CPU_PCIE_INFO_FRU_LIB_H_ #define _CPU_PCIE_INFO_FRU_LIB_H_
+
+#include <CpuPcieInfo.h>
+
+#define CPU_PCIE_MAX_ROOT_PORTS 4
+#define CPU_PCIE_MAX_CONTROLLERS 3
+
+#define CPU_PCIE_ULT_MAX_ROOT_PORT 3
+#define CPU_PCIE_ULX_MAX_ROOT_PORT 1
+
+/**
+ Get CPU Maximum Pcie Root Port Number
+
+ @retval PcieMaxRootPort Pch Maximum Pcie Root Port Number
+**/
+UINT8
+GetMaxCpuPciePortNum (
+ VOID
+ );
+
+/**
+ Get CPU Pcie Root Port Device and Function Number by Root Port
+physical Number
+
+ @param[in] RpNumber Root port physical number. (0-based)
+ @param[out] RpDev Return corresponding root port device number.
+ @param[out] RpFun Return corresponding root port function number.
+
+ @retval EFI_SUCCESS Root port device and function is retrieved
+ @retval EFI_INVALID_PARAMETER RpNumber is invalid
+**/
+EFI_STATUS
+EFIAPI
+GetCpuPcieRpDevFun (
+ IN UINTN RpNumber,
+ OUT UINTN *RpDev,
+ OUT UINTN *RpFun
+ );
+#endif // _CPU_PCIE_INFO_FRU_LIB_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/Include/Register/SaRegsHostBridge.h b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/Include/Register/SaRegsHostBridge.h
new file mode 100644
index 0000000000..be4bba3283
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/Include/Register/SaRe
+++ gsHostBridge.h
@@ -0,0 +1,64 @@
+/** @file
+ Register names for Host Bridge block
+ <b>Conventions</b>:
+ - Prefixes:
+ - Definitions beginning with "R_" are registers
+ - Definitions beginning with "B_" are bits within registers
+ - Definitions beginning with "V_" are meaningful values of bits within the registers
+ - Definitions beginning with "S_" are register sizes
+ - Definitions beginning with "N_" are the bit position
+ - In general, SA registers are denoted by "_SA_" in register names
+ - Registers / bits that are different between SA generations are denoted by
+ "_SA_[generation_name]_" in register/bit names. e.g., "_SA_HSW_"
+ - Registers / bits that are different between SKUs are denoted by "_[SKU_name]"
+ at the end of the register/bit names
+ - Registers / bits of new devices introduced in a SA generation will be just named
+ as "_SA_" without [generation_name] inserted.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/ #ifndef
+_SA_REGS_HOST_BRIDGE_H_ #define _SA_REGS_HOST_BRIDGE_H_
+
+#define SA_SEG_NUM 0x00
+//
+// DEVICE 0 (Memory Controller Hub)
+//
+#define SA_MC_BUS 0x00
+#define SA_MC_DEV 0x00
+#define SA_MC_FUN 0x00
+#define R_SA_MC_DEVICE_ID 0x02
+
+//
+// AlderLake CPU Mobile SA Device IDs B0:D0:F0 //
+#define V_SA_DEVICE_ID_MB_ULT_1 0x4641 ///< AlderLake P (6+8+GT) SA DID
+#define V_SA_DEVICE_ID_MB_ULT_2 0x4649 ///< AlderLake P (6+4(f)+GT) SA DID
+#define V_SA_DEVICE_ID_MB_ULT_3 0x4621 ///< AlderLake P (4(f)+8+GT) SA DID
+#define V_SA_DEVICE_ID_MB_ULT_4 0x4609 ///< AlderLake P (2(f)+4(f)+GT) SA DID
+#define V_SA_DEVICE_ID_MB_ULT_5 0x4601 ///< AlderLake P (2+8+GT) SA DID
+#define V_SA_DEVICE_ID_MB_ULT_6 0x4661 ///< AlderLake P (6+8+2) SA DID
+#define V_SA_DEVICE_ID_MB_ULT_7 0x4629 ///< AlderLake P (4+4+1) SA DID
+#define V_SA_DEVICE_ID_MB_ULT_8 0x4619 ///< AlderLake P (1+4+GT) SA DID
+#define V_SA_DEVICE_ID_MB_ULT_9 0x4659 ///< AlderLake P (1+8+GT) SA DID
+#define V_SA_DEVICE_ID_MB_ULT_10 0x4645 ///< AlderLake P (6+6+GT) SA DID
+///
+/// Description:
+/// The SMRAMC register controls how accesses to Compatible SMRAM spaces are treated. The Open, Close and Lock bits function only when G_SMRAME bit is set to 1. Also, the Open bit must be reset before the Lock bit is set.
+///
+#define R_SA_SMRAMC (0x88)
+
+///
+/// Description:
+/// This register contains the Top of low memory address.
+///
+#define R_SA_TOLUD (0xbc)
+///
+/// Description of TOLUD (20:31)
+/// This register contains bits 31 to 20 of an address one byte above the maximum DRAM memory below 4G that is usable by the operating system. Address bits 31 down to 20 programmed to 01h implies a minimum memory size of 1MB. Configuration software must set this value to the smaller of the following 2 choices: maximum amount memory in the system minus ME stolen memory plus one byte or the minimum address allocated for PCI memory. Address bits 19:0 are assumed to be 0_0000h for the purposes of address comparison. The Host interface positively decodes an address towards DRAM if the incoming address is less than the value programmed in this register.
+/// The Top of Low Usable DRAM is the lowest address above both Graphics Stolen memory and Tseg. BIOS determines the base of Graphics Stolen Memory by subtracting the Graphics Stolen Memory Size from TOLUD and further decrements by Tseg size to determine base of Tseg. All the Bits in this register are locked in LT mode.
+/// This register must be 1MB aligned when reclaim is enabled.
+///
+#define B_SA_TOLUD_TOLUD_MASK (0xfff00000)
+#endif
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/IncludePrivate/CpuGenInfoFruLib.h b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/IncludePrivate/CpuGenInfoFruLib.h
new file mode 100644
index 0000000000..5ad7bf4982
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/IncludePrivate/CpuGen
+++ InfoFruLib.h
@@ -0,0 +1,44 @@
+ /** @file
+ This file contains Cpu Information for specific generation.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/ #ifndef
+_CPU_GEN_INFO_FRU_LIB_H_ #define _CPU_GEN_INFO_FRU_LIB_H_ #include
+<CpuRegs.h> #include <CpuGenInfo.h> #include <Register/CommonMsr.h>
+
+///
+/// Used to identify the CPU used for programming with the VR override
+table /// typedef enum {
+ EnumUnknownCpuId = 0,
+ EnumMinCpuId = 1,
+
+ ///
+ /// ADL P
+ ///
+ EnumAdlP15Watt282fCpuId = 0x30,
+ EnumAdlP28Watt482fCpuId = 0x31,
+ EnumAdlP28Watt682fCpuId = 0x32,
+ EnumAdlP45Watt682fCpuId = 0x35,
+ EnumAdlP15Watt142fCpuId = 0x36,
+ EnumAdlP15Watt242fCpuId = 0x37,
+ EnumAdlP45Watt482fCpuId = 0x38,
+ EnumAdlP45Watt442fCpuId = 0x39,
+ EnumAdlP28Watt442fCpuId = 0x3A,
+ EnumAdlP28Watt282fCpuId = 0x3B,
+ EnumAdlP28Watt242fCpuId = 0x3C,
+ EnumAdlP28Watt142fCpuId = 0x3D,
+ EnumAdlP45Watt242fCpuId = 0x3E,
+ EnumAdlP28Watt182fCpuId = 0x3F,
+ EnumAdlP28Watt662fCpuId = 0x40,
+ EnumAdlP28Watt642fCpuId = 0x41,
+ EnumAdlP45Watt642fCpuId = 0x42,
+ EnumAdlPMaxCpuId = EnumAdlP45Watt642fCpuId,
+
+} CPU_IDENTIFIER;
+
+#endif // _CPU_GEN_INFO_FRU_LIB_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/IncludePrivate/Register/IgdRegs.h b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/IncludePrivate/Register/IgdRegs.h
new file mode 100644
index 0000000000..289b293b32
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/IncludePrivate/Regist
+++ er/IgdRegs.h
@@ -0,0 +1,34 @@
+/** @file
+ Register names for IGD block
+ <b>Conventions</b>:
+ - Prefixes:
+ - Definitions beginning with "R_" are registers
+ - Definitions beginning with "B_" are bits within registers
+ - Definitions beginning with "V_" are meaningful values of bits within the registers
+ - Definitions beginning with "S_" are register sizes
+ - Definitions beginning with "N_" are the bit position
+ - In general, SA registers are denoted by "_SA_" in register names
+ - Registers / bits that are different between SA generations are denoted by
+ "_SA_[generation_name]_" in register/bit names. e.g., "_SA_HSW_"
+ - Registers / bits that are different between SKUs are denoted by "_[SKU_name]"
+ at the end of the register/bit names
+ - Registers / bits of new devices introduced in a SA generation will be just named
+ as "_SA_" without [generation_name] inserted.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/ #ifndef
+_IGD_REGS_H_ #define _IGD_REGS_H_
+
+///
+/// Device 2 Register Equates
+///
+//
+// The following equates must be reviewed and revised when the specification is ready.
+//
+#define IGD_BUS_NUM 0x00
+#define IGD_DEV_NUM 0x02
+#define IGD_FUN_NUM 0x00
+
+#endif
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/LibraryPrivate/BaseCpuInfoFruLib/BaseCpuInfoFruLib.c b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/LibraryPrivate/BaseCpuInfoFruLib/BaseCpuInfoFruLib.c
new file mode 100644
index 0000000000..d93048eb6e
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/LibraryPrivate/BaseCp
+++ uInfoFruLib/BaseCpuInfoFruLib.c
@@ -0,0 +1,164 @@
+/** @file
+ This file contains the Cpu Information for specific generation.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/ #include
+<CpuGenInfoFruLib.h> #include <Library/BaseLib.h> #include
+<Library/DebugLib.h> #include <Register/Cpuid.h> #include
+<Library/CpuPlatformLib.h> #include <Library/CpuInfoFruLib.h> #include
+<Register/ArchitecturalMsr.h> #include <Library/MemoryAllocationLib.h>
+#include <Register/CommonMsr.h> #include <IndustryStandard/SmBios.h>
+#include <Library/PcdLib.h> #include <Library/PchInfoLib.h> #include
+<IndustryStandard/Pci22.h> #include <Register/IgdRegs.h>
+
+
+STATIC CONST CHAR8 mAdlCpuFamilyString[] = "AlderLake"; typedef struct
+{
+ UINT32 CPUID;
+ UINT8 CpuSku;
+ CHAR8 *String;
+} CPU_REV;
+
+typedef struct {
+ CPU_IDENTIFIER CpuIdentifier;
+ UINT8 SupportedCores;
+ UINT8 SupportedAtomCores;
+} CPU_CORE_COUNT;
+
+GLOBAL_REMOVE_IF_UNREFERENCED CONST CPU_REV mProcessorRevisionTable[] = {
+ {CPUID_FULL_FAMILY_MODEL_ALDERLAKE_MOBILE + EnumAdlJ0, EnumCpuUlt, "J0"},
+ {CPUID_FULL_FAMILY_MODEL_ALDERLAKE_MOBILE + EnumAdlK0, EnumCpuUlt, "K0"},
+ {CPUID_FULL_FAMILY_MODEL_ALDERLAKE_MOBILE + EnumAdlL0, EnumCpuUlt, "L0"},
+ {CPUID_FULL_FAMILY_MODEL_ALDERLAKE_MOBILE + EnumAdlQ0, EnumCpuUlt, "Q0"},
+ {CPUID_FULL_FAMILY_MODEL_ALDERLAKE_MOBILE + EnumAdlR0, EnumCpuUlt, "R0"},
+ {CPUID_FULL_FAMILY_MODEL_ALDERLAKE_MOBILE + EnumAdlQ0, EnumCpuUlx, "Q0"},
+ {CPUID_FULL_FAMILY_MODEL_ALDERLAKE_MOBILE + EnumAdlR0, EnumCpuUlx, "R0"},
+ {CPUID_FULL_FAMILY_MODEL_ALDERLAKE_MOBILE + EnumAdlS0, EnumCpuUlx, "S0"}
+};
+
+///
+/// PowerLimits Override table for all SKUs. Non-cTDP parts would have '0' data for TDP level information.
+///
+GLOBAL_REMOVE_IF_UNREFERENCED PPM_OVERRIDE_TABLE
+mPowerLimitsOverrideTable[] = { ///
+/// CpuIdentifier TDP MSR PL1 MSR PL2 TdpUp TdpUp TdpNominal TdpNominal TdpDown TdpDown MSR MSR Disablefvm
+/// PL1 PL2 PL1 PL2 PL1 PL2 PL1 PL2 PL4 PL4
+ {EnumAdlP15Watt282fCpuId, 1500, 1500, 5500, 0, 5500, 0, 5500, 0, 5500, 12300, 0}, /// 15W 282 ADL-P
+ {EnumAdlP15Watt142fCpuId, 1500, 1500, 5500, 0, 5500, 0, 5500, 0, 5500, 12300, 0}, /// 15W 142 ADL-P
+ {EnumAdlP15Watt242fCpuId, 1500, 1500, 5500, 0, 5500, 0, 5500, 0, 5500, 12300, 0}, /// 15W 242 ADL-P
+ {EnumAdlP28Watt282fCpuId, 2800, 2800, 6400, 0, 6400, 0, 6400, 0, 6400, 9000, 0}, /// 28W 282 ADL-P
+ {EnumAdlP28Watt482fCpuId, 2800, 2800, 6400, 0, 6400, 0, 6400, 0, 6400, 9000, 0}, /// 28W 482 ADL-P
+ {EnumAdlP28Watt682fCpuId, 2800, 2800, 6400, 0, 6400, 0, 6400, 0, 6400, 14000, 0}, /// 26W 682 ADL-P
+ {EnumAdlP28Watt142fCpuId, 2800, 2800, 6400, 0, 6400, 0, 6400, 0, 6400, 9000, 0}, /// 28W 142 ADL-P
+ {EnumAdlP28Watt242fCpuId, 2800, 2800, 6400, 0, 6400, 0, 6400, 0, 6400, 9000, 0}, /// 28W 242 ADL-P
+ {EnumAdlP28Watt442fCpuId, 2800, 2800, 6400, 0, 6400, 0, 6400, 0, 6400, 9000, 0}, /// 28W 442 ADL-P
+ {EnumAdlP28Watt182fCpuId, 2800, 2800, 6400, 0, 6400, 0, 6400, 0, 6400, 9000, 0}, /// 28W 182 ADL-P
+ {EnumAdlP28Watt642fCpuId, 2800, 2800, 6400, 0, 6400, 0, 6400, 0, 6400, 14000, 0}, /// 26W 682 ADL-P
+ {EnumAdlP28Watt662fCpuId, 2800, 2800, 6400, 0, 6400, 0, 6400, 0, 6400, 14000, 0}, /// 26W 682 ADL-P
+ {EnumAdlP45Watt682fCpuId, 4500, 4500, 11500, 0, 11500, 0, 11500, 0, 11500, 21500, 0}, /// 45W 682 ADL-P
+ {EnumAdlP45Watt242fCpuId, 4500, 4500, 9500, 0, 9500, 0, 9500, 0, 9500, 12500, 0}, /// 45W 242 ADL-P
+ {EnumAdlP45Watt482fCpuId, 4500, 4500, 9500, 0, 9500, 0, 9500, 0, 9500, 12500, 0}, /// 45W 482 ADL-P
+ {EnumAdlP45Watt442fCpuId, 4500, 4500, 9500, 0, 9500, 0, 9500, 0, 9500, 12500, 0}, /// 45W 442 ADL-P
+ {EnumAdlP45Watt642fCpuId, 4500, 4500, 11500, 0, 11500, 0, 11500, 0, 11500, 21500, 0}, /// 45W 642 ADL-P
+};
+
+GLOBAL_REMOVE_IF_UNREFERENCED CONST CPU_CORE_COUNT mCpuCoreCountMappingTable[] = {
+ { EnumAdlP15Watt282fCpuId, 2, 8},
+ { EnumAdlP28Watt282fCpuId, 2, 8},
+ { EnumAdlP28Watt482fCpuId, 4, 8},
+ { EnumAdlP28Watt682fCpuId, 6, 8},
+ { EnumAdlP45Watt682fCpuId, 6, 8},
+ { EnumAdlP45Watt482fCpuId, 4, 8},
+ { EnumAdlP45Watt442fCpuId, 4, 4},
+ { EnumAdlP28Watt442fCpuId, 4, 4},
+ { EnumAdlP15Watt142fCpuId, 1, 4},
+ { EnumAdlP28Watt142fCpuId, 1, 4},
+ { EnumAdlP15Watt242fCpuId, 2, 4},
+ { EnumAdlP28Watt242fCpuId, 2, 4},
+ { EnumAdlP45Watt242fCpuId, 2, 4},
+ { EnumAdlP45Watt642fCpuId, 6, 4},
+ { EnumAdlP28Watt182fCpuId, 1, 8},
+ { EnumAdlP28Watt642fCpuId, 6, 4},
+ { EnumAdlP28Watt662fCpuId, 6, 6},
+};
+
+/**
+ Return CPU Sku
+
+ @param[in] UINT32 CpuFamilyModel
+ @param[in] UINT16 CpuDid
+
+ @retval UINT8 CPU Sku
+**/
+UINT8
+GetCpuSkuInfo (
+ IN UINT32 CpuFamilyModel,
+ IN UINT16 CpuDid
+ )
+{
+ UINT8 CpuType;
+ BOOLEAN SkuFound;
+
+ SkuFound = TRUE;
+ CpuType = EnumCpuUnknown;
+
+ switch (CpuFamilyModel) {
+ case CPUID_FULL_FAMILY_MODEL_ALDERLAKE_MOBILE:
+ switch (CpuDid) {
+ case V_SA_DEVICE_ID_MB_ULT_1: // AlderLake P (6+8+GT)
+ case V_SA_DEVICE_ID_MB_ULT_2: // AlderLake P (6+4(f)+GT)
+ case V_SA_DEVICE_ID_MB_ULT_3: // AlderLake P (4(f)+8+GT)
+ case V_SA_DEVICE_ID_MB_ULT_4: // AlderLake P (2(f)+4(f)+GT)
+ case V_SA_DEVICE_ID_MB_ULT_5: // AlderLake P (2+8+GT)
+ case V_SA_DEVICE_ID_MB_ULT_6: // AlderLake P (2+4(f)+GT)
+ case V_SA_DEVICE_ID_MB_ULT_7: // AlderLake P (4+4(f)+GT)
+ case V_SA_DEVICE_ID_MB_ULT_8: // AlderLake P (1+4+GT) SA DID
+ case V_SA_DEVICE_ID_MB_ULT_9: // AlderLake P (1+8+GT) SA DID
+ case V_SA_DEVICE_ID_MB_ULT_10: // AlderLake P (6+6+GT) SA DID
+ CpuType = EnumCpuUlt;
+ break;
+ default:
+ SkuFound = FALSE;
+ break;
+ }
+ break;
+ default:
+ SkuFound = FALSE;
+ break;
+ }
+
+ if (!SkuFound) {
+ DEBUG ((DEBUG_ERROR, "Unsupported CPU SKU, Device ID: 0x%02X, CPUID: 0x%08X!\n", CpuDid, CpuFamilyModel));
+ ASSERT (FALSE);
+ }
+
+ return CpuType;
+}
+
+
+/**
+ This function returns the supported Physical Address Size
+
+ @retval returns the supported Physical Address Size.
+**/
+UINT8
+GetMaxPhysicalAddressSizeFru (
+ VOID
+ )
+{
+ //
+ // Even though CPUID Leaf CPUID_VIR_PHY_ADDRESS_SIZE (0x80000008) MAX_PA will report 46.
+ // For ADL BIOS will return Memory expansion 39 bit (0 - 38) + MKTME (Bits 39-41 must be zero - 3 bit hole in the middle) 42-45 bit is MKTME Keys.
+ //
+ return 39;
+}
+
+
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/LibraryPrivate/BaseCpuInfoFruLib/BaseCpuInfoFruLib.inf b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/LibraryPrivate/BaseCpuInfoFruLib/BaseCpuInfoFruLib.inf
new file mode 100644
index 0000000000..22bcbdf43c
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/LibraryPrivate/BaseCp
+++ uInfoFruLib/BaseCpuInfoFruLib.inf
@@ -0,0 +1,29 @@
+## @file
+# This file contains the Cpu Information for specific generation.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+
+[Defines]
+INF_VERSION = 0x00010017
+BASE_NAME = BaseCpuInfoFruLib
+FILE_GUID = 72E44627-C719-4B2D-8C5D-963E167E5AAC
+VERSION_STRING = 1.0
+MODULE_TYPE = BASE
+LIBRARY_CLASS = CpuInfoFruLib
+
+[LibraryClasses]
+BaseLib
+DebugLib
+PchInfoLib
+
+[Packages]
+MdePkg/MdePkg.dec
+UefiCpuPkg/UefiCpuPkg.dec
+AlderlakeSiliconPkg/SiPkg.dec
+
+[Sources]
+BaseCpuInfoFruLib.c
+
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/PeiReportCpuHob/Library/PeiReportCpuHobLib/PeiReportCpuHobLib.c b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/PeiReportCpuHob/Library/PeiReportCpuHobLib/PeiReportCpuHobLib.c
new file mode 100644
index 0000000000..7ea605a05b
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/PeiReportCpuHob/Libra
+++ ry/PeiReportCpuHobLib/PeiReportCpuHobLib.c
@@ -0,0 +1,22 @@
+/** @file
+
+ Source code file for Report CPU HOB library.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/
+
+#include <Base.h>
+#include <Library/HobLib.h>
+#include <Library/CpuPlatformLib.h>
+
+VOID
+ReportCpuHob (
+ VOID
+ )
+{
+ ///
+ /// Create a CPU hand-off information
+ ///
+ BuildCpuHob (GetMaxPhysicalAddressSize (), 16); }
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/PeiReportCpuHob/Library/PeiReportCpuHobLib/PeiReportCpuHobLib.inf b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/PeiReportCpuHob/Library/PeiReportCpuHobLib/PeiReportCpuHobLib.inf
new file mode 100644
index 0000000000..0ba4744eea
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlCpu/PeiReportCpuHob/Libra
+++ ry/PeiReportCpuHobLib/PeiReportCpuHobLib.inf
@@ -0,0 +1,26 @@
+### @file
+# Component information file for the Report CPU HOB library.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+[Defines]
+ INF_VERSION = 0x00010017
+ BASE_NAME = PeiReportCpuHobLib
+ FILE_GUID = F19AA754-CE24-448D-B755-1F939B00C23D
+ VERSION_STRING = 1.0
+ MODULE_TYPE = PEIM
+ LIBRARY_CLASS = ReportCpuHobLib
+
+[LibraryClasses]
+ BaseLib
+ HobLib
+ CpuPlatformLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ AlderlakeSiliconPkg/SiPkg.dec
+
+[Sources]
+ PeiReportCpuHobLib.c
--
2.36.1.windows.1
-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#108744): https://edk2.groups.io/g/devel/message/108744
Mute This Topic: https://groups.io/mt/101373952/7686176
Group Owner: devel+owner@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [rebecca@openfw.io]
-=-=-=-=-=-=-=-=-=-=-=-
^ permalink raw reply related [flat|nested] 41+ messages in thread
* Re: [edk2-devel] [PATCH v2 09/10] AlderlakeSiliconPkg: Add AdlPch Fru and IncludePrivate modules
2023-09-15 4:45 ` [edk2-devel] [PATCH v2 09/10] AlderlakeSiliconPkg: Add AdlPch Fru and IncludePrivate modules Saloni Kasbekar
2023-09-15 5:43 ` Chaganty, Rangasai V
@ 2023-09-15 23:57 ` Nate DeSimone
1 sibling, 0 replies; 41+ messages in thread
From: Nate DeSimone @ 2023-09-15 23:57 UTC (permalink / raw)
To: Kasbekar, Saloni, devel@edk2.groups.io
Cc: Chaganty, Rangasai V, Chuang, Rosen
Acked-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
-----Original Message-----
From: Kasbekar, Saloni <saloni.kasbekar@intel.com>
Sent: Thursday, September 14, 2023 9:46 PM
To: devel@edk2.groups.io
Cc: Kasbekar, Saloni <saloni.kasbekar@intel.com>; Chaganty, Rangasai V <rangasai.v.chaganty@intel.com>; Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>; Chuang, Rosen <rosen.chuang@intel.com>
Subject: [PATCH v2 09/10] AlderlakeSiliconPkg: Add AdlPch Fru and IncludePrivate modules
Adds the following modules:
- AdlPch/Include
- AdlPch/IncludePrivate
- AdlPch/Library
- AdlPch DSCs
- IncludePrivate
Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Rosen Chuang <rosen.chuang@intel.com>
Signed-off-by: Saloni Kasbekar <saloni.kasbekar@intel.com>
---
.../Fru/AdlPch/CommonLib.dsc | 29 ++
.../AlderlakeSiliconPkg/Fru/AdlPch/Dxe.dsc | 10 +
.../AlderlakeSiliconPkg/Fru/AdlPch/DxeLib.dsc | 7 +
.../Fru/AdlPch/Include/PchBdfAssignment.h | 81 +++++
.../Fru/AdlPch/Include/PchLimits.h | 47 +++
.../Fru/AdlPch/Include/PchPcieRpInfo.h | 17 ++
.../Fru/AdlPch/Include/PchReservedResources.h | 13 + .../AdlPch/Include/PchReservedResourcesAdpP.h | 36 +++
.../IncludePrivate/Register/PchPcrRegs.h | 59 ++++
.../IncludePrivate/Register/PchRegsLpcAdl.h | 30 ++
.../PeiDxeSmmPchInfoLib/PchInfoLibAdl.c | 223 ++++++++++++++
.../PeiDxeSmmPchInfoLib/PchInfoLibPrivate.h | 44 +++
.../PeiDxeSmmPchInfoLibAdl.inf | 37 +++
.../AlderlakeSiliconPkg/Fru/AdlPch/Pei.dsc | 7 +
.../AlderlakeSiliconPkg/Fru/AdlPch/PeiLib.dsc | 12 +
.../IncludePrivate/RegisterAccess.h | 288 ++++++++++++++++++
16 files changed, 940 insertions(+)
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/CommonLib.dsc
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Dxe.dsc
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/DxeLib.dsc
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Include/PchBdfAssignment.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Include/PchLimits.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Include/PchPcieRpInfo.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Include/PchReservedResources.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Include/PchReservedResourcesAdpP.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/IncludePrivate/Register/PchPcrRegs.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/IncludePrivate/Register/PchRegsLpcAdl.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Library/PeiDxeSmmPchInfoLib/PchInfoLibAdl.c
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Library/PeiDxeSmmPchInfoLib/PchInfoLibPrivate.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Library/PeiDxeSmmPchInfoLib/PeiDxeSmmPchInfoLibAdl.inf
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Pei.dsc
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/PeiLib.dsc
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IncludePrivate/RegisterAccess.h
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/CommonLib.dsc b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/CommonLib.dsc
new file mode 100644
index 0000000000..3f508f83a1
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/CommonLib.dsc
@@ -0,0 +1,29 @@
+## @file
+# Component description file for the AlderLake PCH Common FRU libraries.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+
+ PchPcrLib|$(PLATFORM_SI_PACKAGE)/IpBlock/P2sb/Library/PeiDxeSmmPchPcrL
+ ib/PeiDxeSmmPchPcrLib.inf
+ PchSbiAccessLib|$(PLATFORM_SI_PACKAGE)/IpBlock/P2sb/LibraryPrivate/Pei
+ DxeSmmPchSbiAccessLib/PeiDxeSmmPchSbiAccessLib.inf
+
+ P2SbSidebandAccessLib|$(PLATFORM_SI_PACKAGE)/IpBlock/P2sb/LibraryPriva
+ te/PeiDxeSmmP2SbSidebandAccessLib/PeiDxeSmmP2SbSidebandAccessLib.inf
+
+
+ EspiLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Espi/Library/PeiDxeSmmEspiLib/P
+ eiDxeSmmEspiLib.inf
+
+
+
+ PmcLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Pmc/Library/PeiDxeSmmPmcLib/PeiD
+ xeSmmPmcLib.inf
+ PmcPrivateLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Pmc/LibraryPrivate/PeiDxe
+ SmmPmcPrivateLib/PeiDxeSmmPmcPrivateLib.inf
+
+ SpiCommonLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Spi/LibraryPrivate/BaseSpi
+ CommonLib/BaseSpiCommonLib.inf
+ GpioLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Gpio/Library/PeiDxeSmmGpioLib/P
+ eiDxeSmmGpioLib.inf
+ PchDmiLib|$(PLATFORM_SI_PACKAGE)/IpBlock/PchDmi/LibraryPrivate/PeiDxeS
+ mmPchDmiLib/PeiDxeSmmPchDmiLib.inf
+
+
+ GpioPrivateLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Gpio/LibraryPrivate/PeiD
+ xeSmmGpioPrivateLib/PeiDxeSmmGpioPrivateLibVer2.inf
+
+ PchPcieRpLib|$(PLATFORM_SI_PACKAGE)/IpBlock/PcieRp/Library/PeiDxeSmmPc
+ hPcieRpLib/PeiDxeSmmPchPcieRpLibVer2.inf
+
+
+ #
+ # Common FRU Libraries
+ #
+
+ PchInfoLib|$(PLATFORM_SI_PACKAGE)/Fru/AdlPch/Library/PeiDxeSmmPchInfoL
+ ib/PeiDxeSmmPchInfoLibAdl.inf
+
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Dxe.dsc b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Dxe.dsc
new file mode 100644
index 0000000000..b443611d9a
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Dxe.dsc
@@ -0,0 +1,10 @@
+## @file
+# Component description file for the AlderLake PCH DXE FRU drivers.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+ $(PLATFORM_SI_PACKAGE)/IpBlock/Spi/Smm/SpiSmm.inf
+
+
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/DxeLib.dsc b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/DxeLib.dsc
new file mode 100644
index 0000000000..e350b8e643
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/DxeLib.dsc
@@ -0,0 +1,7 @@
+# @file
+# Component description file for the AlderLake PCH DXE FRU libraries.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+GpioHelpersLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Gpio/LibraryPrivate/BaseG
+pioHelpersLibNull/BaseGpioHelpersLibNull.inf
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Include/PchBdfAssignment.h b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Include/PchBdfAssignment.h
new file mode 100644
index 0000000000..b8af6d7624
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Include/PchBdfAssignm
+++ ent.h
@@ -0,0 +1,81 @@
+/** @file
+ Header file for AlderLake PCH devices PCI Bus Device Function map.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/ #ifndef
+_PCH_BDF_ASSIGNMENT_H_ #define _PCH_BDF_ASSIGNMENT_H_
+
+#define NOT_PRESENT 0xFF
+
+//
+// PCH PCIe Controllers
+//
+#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_1 28
+#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_2 28
+#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_3 28
+#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_4 28
+#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_5 28
+#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_6 28
+#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_7 28
+#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_8 28
+#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_9 29
+#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_10 29
+#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_11 29
+#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_12 29
+#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_13 29
+#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_14 29
+#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_15 29
+#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_16 29
+#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_17 27
+#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_18 27
+#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_19 27
+#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_20 27
+#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_21 27
+#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_22 27
+#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_23 27
+#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_24 27
+#ifdef PCH_ADPP
+#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_25 NOT_PRESENT
+#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_26 NOT_PRESENT
+#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_27 NOT_PRESENT
+#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_28 NOT_PRESENT
+#else
+#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_25 26
+#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_26 26
+#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_27 26
+#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_28 26
+#endif
+
+//
+// USB3 (XHCI) Controller PCI config
+//
+#define PCI_DEVICE_NUMBER_PCH_XHCI 20
+#define PCI_FUNCTION_NUMBER_PCH_XHCI 0
+
+
+
+
+//
+// LPC Controller (D31:F0)
+//
+#define PCI_DEVICE_NUMBER_PCH_LPC 31
+#define PCI_FUNCTION_NUMBER_PCH_LPC 0
+
+//
+// Primary to Sideband (P2SB) Bridge (D31:F1) //
+#define PCI_DEVICE_NUMBER_PCH_P2SB 31
+#define PCI_FUNCTION_NUMBER_PCH_P2SB 1
+
+
+
+//
+// SPI Controller (D31:F5)
+//
+#define PCI_DEVICE_NUMBER_PCH_SPI 31
+#define PCI_FUNCTION_NUMBER_PCH_SPI 5
+
+
+#endif // _PCH_BDF_ASSIGNMENT_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Include/PchLimits.h b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Include/PchLimits.h
new file mode 100644
index 0000000000..dad3a9a073
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Include/PchLimits.h
@@ -0,0 +1,47 @@
+/** @file
+ Build time limits of PCH resources.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/ #ifndef
+_PCH_LIMITS_H_ #define _PCH_LIMITS_H_
+/*
+ * Defines povided in this file are indended to be used only where
+static value
+ * is needed. They are set to values which allow to accomodate multiple
+projects
+ * needs. Where runtime usage is possible please used dedicated
+functions from
+ * PchInfoLib to retrieve accurate values */
+
+
+
+//
+// PCIe limits
+//
+#define PCH_MAX_PCIE_ROOT_PORTS 28
+#define PCH_MAX_PCIE_CONTROLLERS 7
+
+//
+// PCIe clocks limits
+//
+#define PCH_MAX_PCIE_CLOCKS 18
+
+//
+// DMI lanes
+//
+#define PCH_MAX_DMI_LANES 8
+
+//
+// SerialIo limits
+//
+#define PCH_MAX_SERIALIO_I2C_CONTROLLERS 8
+#define PCH_MAX_SERIALIO_SPI_CONTROLLERS 7
+#define PCH_MAX_SERIALIO_SPI_CHIP_SELECTS 2
+#define PCH_MAX_SERIALIO_UART_CONTROLLERS 7
+
+//
+// Number of eSPI slaves
+//
+#define PCH_MAX_ESPI_SLAVES 2
+
+#endif // _PCH_LIMITS_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Include/PchPcieRpInfo.h b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Include/PchPcieRpInfo.h
new file mode 100644
index 0000000000..9276b61e1f
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Include/PchPcieRpInfo
+++ .h
@@ -0,0 +1,17 @@
+/** @file
+ Pcie Root Port info header
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/
+
+#ifndef _PCH_PCIERP_INFO_H_
+#define _PCH_PCIERP_INFO_H_
+
+//
+// Number of PCIe ports per PCIe controller //
+#define PCH_PCIE_CONTROLLER_PORTS 4u
+
+
+#endif
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Include/PchReservedResources.h b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Include/PchReservedResources.h
new file mode 100644
index 0000000000..f4adfab74f
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Include/PchReservedRe
+++ sources.h
@@ -0,0 +1,13 @@
+/** @file
+ PCH preserved MMIO resource definitions.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/
+
+#ifndef _PCH_PRESERVED_RESOURCES_H_
+#define _PCH_PRESERVED_RESOURCES_H_
+#include "PchReservedResourcesAdpP.h"
+
+#endif // _PCH_PRESERVED_RESOURCES_H_
+
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Include/PchReservedResourcesAdpP.h b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Include/PchReservedResourcesAdpP.h
new file mode 100644
index 0000000000..69aac29cea
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Include/PchReservedRe
+++ sourcesAdpP.h
@@ -0,0 +1,36 @@
+/** @file
+ PCH preserved MMIO resource definitions.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/ #ifndef
+_PCH_PRESERVED_RESOURCES_ADP_P_H_
+#define _PCH_PRESERVED_RESOURCES_ADP_P_H_
+
+/**
+ Detailed recommended static allocation
+ +-------------------------------------------------------------------------+
+ | PCH preserved MMIO range, 32 MB, from 0xFC800000 to 0xFE7FFFFF |
+ +-------------------------------------------------------------------------+
+ | Size | Start | End | Usage |
+ | 8 MB | 0xFC800000 | 0xFCFFFFFF | TraceHub SW BAR |
+ | 16 MB | 0xFD000000 | 0xFDFFFFFF | SBREG |
+ | 64 KB | 0xFE000000 | 0xFE00FFFF | PMC MBAR |
+ | 4 KB | 0xFE010000 | 0xFE010FFF | SPI BAR0 |
+ | 176 KB | 0xFE020000 | 0xFE04BFFF | SerialIo BAR in ACPI mode |
+ | 400 KB | 0xFE04C000 | 0xFE0AFFFF | Unused |
+ | 64 KB | 0xFE0B0000 | 0xFE0BFFFF | eSPI LGMR BAR |
+ | 64 KB | 0xFE0C0000 | 0xFE0CFFFF | eSPI2 SEGMR BAR |
+ | 192 KB | 0xFE0D0000 | 0xFE0FFFFF | Unused |
+ | 1 MB | 0xFE100000 | 0xFE1FFFFF | TraceHub MTB BAR |
+ | 2 MB | 0xFE200000 | 0xFE3FFFFF | TraceHub FW BAR |
+ | 2 MB | 0xFE400000 | 0xFE5FFFFF | Unused |
+ | 2 MB | 0xFE600000 | 0xFE7FFFFF | Temp address |
+
++----------------------------------------------------------------------
+---+
+**/
+#define PCH_PCR_BASE_ADDRESS 0xFD000000 ///< SBREG MMIO base address
+#define PCH_PWRM_BASE_ADDRESS 0xFE000000 ///< PMC MBAR MMIO base address
+#define PCH_SPI_BASE_ADDRESS 0xFE010000 ///< SPI BAR0 MMIO base address
+
+#endif // _PCH_PRESERVED_RESOURCES_ADP_P_H_
+
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/IncludePrivate/Register/PchPcrRegs.h b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/IncludePrivate/Register/PchPcrRegs.h
new file mode 100644
index 0000000000..fe548dae4b
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/IncludePrivate/Regist
+++ er/PchPcrRegs.h
@@ -0,0 +1,59 @@
+/** @file
+ Register names for PCH private chipset register
+
+Conventions:
+
+ - Register definition format:
+
+ Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_Re
+ gisterName
+ - Prefix:
+ Definitions beginning with "R_" are registers
+ Definitions beginning with "B_" are bits within registers
+ Definitions beginning with "V_" are meaningful values within the bits
+ Definitions beginning with "S_" are register size
+ Definitions beginning with "N_" are the bit position
+ - [GenerationName]:
+ Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc.).
+ Register name without GenerationName applies to all generations.
+ - [ComponentName]:
+ This field indicates the component name that the register belongs to (e.g. PCH, SA etc.)
+ Register name without ComponentName applies to all components.
+ Register that is specific to -H denoted by "_PCH_H_" in component name.
+ Register that is specific to -LP denoted by "_PCH_LP_" in component name.
+ - SubsystemName:
+ This field indicates the subsystem name of the component that the register belongs to
+ (e.g. PCIE, USB, SATA, GPIO, PMC etc.).
+ - RegisterSpace:
+ MEM - MMIO space register of subsystem.
+ IO - IO space register of subsystem.
+ PCR - Private configuration register of subsystem.
+ CFG - PCI configuration space register of subsystem.
+ - RegisterName:
+ Full register name.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/
+
+#ifndef _PCH_REGS_PCR_H_
+#define _PCH_REGS_PCR_H_
+
+
+/**
+ Definition for SBI PID
+ The PCH_SBI_PID defines the PID for PCR MMIO programming and PCH SBI programming as well.
+**/
+#define PID_DMI 0x88
+#define PID_ESPISPI 0x72
+#define PID_SPF 0x85
+#define PID_SPE 0x84
+#define PID_SPD 0x83
+#define PID_SPC 0x82
+#define PID_SPB 0x81
+#define PID_SPA 0x80
+#define PID_GPIOCOM0 0x6E
+#define PID_GPIOCOM1 0x6D
+#define PID_GPIOCOM2 0x6C
+#define PID_GPIOCOM4 0x6A
+#define PID_GPIOCOM5 0x69
+
+#endif
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/IncludePrivate/Register/PchRegsLpcAdl.h b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/IncludePrivate/Register/PchRegsLpcAdl.h
new file mode 100644
index 0000000000..8b1a01036e
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/IncludePrivate/Regist
+++ er/PchRegsLpcAdl.h
@@ -0,0 +1,30 @@
+/** @file
+ Register names for ADL PCH LPC/eSPI device
+
+ Conventions:
+
+ - Prefixes:
+ Definitions beginning with "R_" are registers
+ Definitions beginning with "B_" are bits within registers
+ Definitions beginning with "V_" are meaningful values within the bits
+ Definitions beginning with "S_" are register sizes
+ Definitions beginning with "N_" are the bit position
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/ #ifndef
+_PCH_REGS_LPC_ADL_H_ #define _PCH_REGS_LPC_ADL_H_
+
+//
+// ADL PCH-P/M LPC Device IDs
+//
+#define V_ADL_PCH_P_LPC_CFG_DEVICE_ID_MB_0 0x5180 ///< LPC/eSPI Controller
+#define V_ADL_PCH_P_LPC_CFG_DEVICE_ID_MB_1 0x5181 ///< LPC/eSPI Controller P SuperSKU
+#define V_ADL_PCH_P_LPC_CFG_DEVICE_ID_MB_2 0x5182 ///< LPC/eSPI Controller P Premium
+#define V_ADL_PCH_P_LPC_CFG_DEVICE_ID_MB_3 0x5183 ///< LPC/eSPI Controller Placeholder
+#define V_ADL_PCH_P_LPC_CFG_DEVICE_ID_MB_4 0x5184 ///< LPC/eSPI Controller
+#define V_ADL_PCH_P_LPC_CFG_DEVICE_ID_MB_5 0x5185 ///< LPC/eSPI Controller
+
+
+#endif
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Library/PeiDxeSmmPchInfoLib/PchInfoLibAdl.c b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Library/PeiDxeSmmPchInfoLib/PchInfoLibAdl.c
new file mode 100644
index 0000000000..c74d665533
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Library/PeiDxeSmmPchI
+++ nfoLib/PchInfoLibAdl.c
@@ -0,0 +1,223 @@
+/** @file
+ Pch information library for ADL.
+
+ All function in this library is available for PEI, DXE, and SMM, But
+ do not support UEFI RUNTIME environment call.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/ #include <Base.h>
+#include <PchPcieRpInfo.h> #include <Uefi/UefiBaseType.h> #include
+<Library/PchInfoLib.h> #include <Library/PmcPrivateLib.h> #include
+<Library/PrintLib.h> #include <Library/IoLib.h> #include
+<Library/DebugLib.h> #include <Library/BaseLib.h> #include
+<Library/PciSegmentLib.h> #include <Library/PcdLib.h> #include
+<Library/PchPciBdfLib.h> #include <Register/PchRegsLpcAdl.h> #include
+<Register/PchRegs.h> #include <Register/PchRegsLpc.h> #include
+<IndustryStandard/Pci30.h> #include "PchInfoLibPrivate.h"
+
+
+/**
+ Return LPC Device Id
+
+ @retval PCH_LPC_DEVICE_ID PCH Lpc Device ID
+**/
+UINT16
+PchGetLpcDid (
+ VOID
+ )
+{
+ UINT64 LpcBaseAddress;
+
+ LpcBaseAddress = LpcPciCfgBase ();
+
+ return PciSegmentRead16 (LpcBaseAddress + PCI_DEVICE_ID_OFFSET);
+}
+
+/**
+ Return Pch Series
+
+ @retval PCH_SERIES Pch Series
+**/
+PCH_SERIES
+PchSeries (
+ VOID
+ )
+{
+ PCH_SERIES PchSer;
+ static PCH_SERIES PchSeries = PCH_UNKNOWN_SERIES;
+
+ if (PchSeries != PCH_UNKNOWN_SERIES) {
+ return PchSeries;
+ }
+
+ PchSer = PchSeriesFromLpcDid (PchGetLpcDid ());
+
+ PchSeries = PchSer;
+
+ return PchSer;
+}
+
+/**
+ Return Pch stepping type
+
+ @retval PCH_STEPPING Pch stepping type
+**/
+PCH_STEPPING
+PchStepping (
+ VOID
+ )
+{
+ UINT8 RevId;
+ UINT64 LpcBaseAddress;
+ static PCH_STEPPING PchStepping = PCH_STEPPING_MAX;
+
+ if (PchStepping != PCH_STEPPING_MAX) {
+ return PchStepping;
+ }
+
+ LpcBaseAddress = LpcPciCfgBase ();
+ RevId = PciSegmentRead8 (LpcBaseAddress + PCI_REVISION_ID_OFFSET);
+
+ RevId = PchSteppingFromRevId (RevId);
+
+ PchStepping = RevId;
+
+ return RevId;
+}
+
+/**
+ Check if this is PCH P series
+
+ @retval TRUE It's PCH P series
+ @retval FALSE It's not PCH P series
+**/
+BOOLEAN
+IsPchP (
+ VOID
+ )
+{
+ return (PchSeries () == PCH_P);
+}
+
+/**
+ return support status for P2SB PCR 20-bit addressing
+
+ @retval TRUE
+ @retval FALSE
+**/
+BOOLEAN
+IsP2sb20bPcrSupported (
+ VOID
+ )
+{
+ return FALSE;
+}
+
+/**
+ Determine Pch Series based on Device Id
+
+ @param[in] LpcDeviceId Lpc Device Id
+
+ @retval PCH_SERIES Pch Series
+**/
+PCH_SERIES
+PchSeriesFromLpcDid (
+ IN UINT16 LpcDeviceId
+ )
+{
+ return PCH_P;
+}
+
+/**
+ Determine Pch Stepping based on Revision ID
+
+ @param[in] RevId Pch Revision Id
+
+ @retval PCH_STEPPING Pch Stepping
+**/
+PCH_STEPPING
+PchSteppingFromRevId (
+ IN UINT8 RevId
+ )
+{
+ return RevId;
+}
+
+
+/**
+ Check if this is PCH LP series
+
+ @retval TRUE It's PCH LP series
+ @retval FALSE It's not PCH LP series
+**/
+BOOLEAN
+IsPchLp (
+ VOID
+ )
+{
+ return (PchSeries () == PCH_LP || PchSeries () == PCH_P || PchSeries () == PCH_M || PchSeries () == PCH_N );
+}
+/**
+ Get RST mode supported by the silicon
+
+ @retval RST_MODE RST mode supported by silicon
+**/
+
+GLOBAL_REMOVE_IF_UNREFERENCED
+struct PCH_SKU_STRING mSkuStrs[] = {
+ //
+ // ADL PCH LPC Device IDs
+ //
+ {V_ADL_PCH_P_LPC_CFG_DEVICE_ID_MB_0, "ADL SKU 0"},
+ {V_ADL_PCH_P_LPC_CFG_DEVICE_ID_MB_1, "P Super SKU (SSKU)"},
+ {V_ADL_PCH_P_LPC_CFG_DEVICE_ID_MB_2, "P Premium"},
+ {V_ADL_PCH_P_LPC_CFG_DEVICE_ID_MB_3, "ADL No UFS"},
+ {V_ADL_PCH_P_LPC_CFG_DEVICE_ID_MB_4, "ADL SKU 4"},
+ {V_ADL_PCH_P_LPC_CFG_DEVICE_ID_MB_5, "ADL SKU 5"},
+
+ {0xFFFF, NULL}
+};
+
+/**
+ Get Pch Maximum Pcie Root Port Number
+
+ @retval Pch Maximum Pcie Root Port Number
+**/
+UINT8
+GetPchMaxPciePortNum (
+ VOID
+ )
+{
+ switch (PchSeries ()) {
+ case PCH_P:
+ case PCH_N:
+ return 12;
+ case PCH_S:
+ return 28;
+ default:
+ return 0;
+ }
+}
+
+/**
+ Get Pch Maximum Serial IO I2C controllers number
+
+ @retval Pch Maximum Serial IO I2C controllers number
+**/
+UINT8
+GetPchMaxSerialIoI2cControllersNum (
+ VOID
+ )
+{
+ return 8;
+}
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Library/PeiDxeSmmPchInfoLib/PchInfoLibPrivate.h b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Library/PeiDxeSmmPchInfoLib/PchInfoLibPrivate.h
new file mode 100644
index 0000000000..a4bd4d5aa7
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Library/PeiDxeSmmPchInfoLib/PchInfoLibPrivate.h
@@ -0,0 +1,44 @@
+/** @file
+ Private header for PCH Info Lib.
+
+ All function in this library is available for PEI, DXE, and SMM,
+ But do not support UEFI RUNTIME environment call.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+/**
+ Structure for PCH SKU string mapping
+**/
+struct PCH_SKU_STRING {
+ UINT16 Id;
+ CHAR8 *String;
+};
+
+extern struct PCH_SKU_STRING mSkuStrs[];
+
+/**
+ Determine Pch Series based on Device Id
+
+ @param[in] LpcDeviceId Lpc Device Id
+
+ @retval PCH_SERIES Pch Series
+**/
+PCH_SERIES
+PchSeriesFromLpcDid (
+ IN UINT16 LpcDeviceId
+ );
+
+/**
+ Determine Pch Stepping based on Revision ID
+
+ @param[in] RevId Pch Revision Id
+
+ @retval PCH_STEPPING Pch Stepping
+**/
+PCH_STEPPING
+PchSteppingFromRevId (
+ IN UINT8 RevId
+ );
+
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Library/PeiDxeSmmPchInfoLib/PeiDxeSmmPchInfoLibAdl.inf b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Library/PeiDxeSmmPchInfoLib/PeiDxeSmmPchInfoLibAdl.inf
new file mode 100644
index 0000000000..28a6863aed
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Library/PeiDxeSmmPchInfoLib/PeiDxeSmmPchInfoLibAdl.inf
@@ -0,0 +1,37 @@
+## @file
+# PCH information library for Alderlake PCH.
+#
+# All function in this library is available for PEI, DXE, and SMM,
+# But do not support UEFI RUNTIME environment call.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+
+[Defines]
+INF_VERSION = 0x00010017
+BASE_NAME = PeiDxeSmmPchInfoLibAdl
+FILE_GUID = F5B0CBB7-4AFC-4535-A5EC-D9ECEDA24DC5
+VERSION_STRING = 1.0
+MODULE_TYPE = BASE
+LIBRARY_CLASS = PchInfoLib
+
+
+[LibraryClasses]
+BaseLib
+IoLib
+DebugLib
+PrintLib
+PciSegmentLib
+PmcPrivateLib
+PcdLib
+
+
+[Packages]
+MdePkg/MdePkg.dec
+AlderlakeSiliconPkg/SiPkg.dec
+
+
+[Sources]
+PchInfoLibAdl.c
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Pei.dsc b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Pei.dsc
new file mode 100644
index 0000000000..8a923554dd
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/Pei.dsc
@@ -0,0 +1,7 @@
+## @file
+# Component description file for the AlderLake PCH PEI FRU drivers.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/PeiLib.dsc b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/PeiLib.dsc
new file mode 100644
index 0000000000..ebe2bbfda0
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Fru/AdlPch/PeiLib.dsc
@@ -0,0 +1,12 @@
+## @file
+# Component description file for the AlderLake PCH PEI FRU libraries.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+ SpiLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Spi/Library/PeiSpiLib/PeiSpiLib.inf
+
+ GpioHelpersLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Gpio/LibraryPrivate/PeiGpioHelpersLib/PeiGpioHelpersLib.inf
+
+
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IncludePrivate/RegisterAccess.h b/Silicon/Intel/AlderlakeSiliconPkg/IncludePrivate/RegisterAccess.h
new file mode 100644
index 0000000000..25a0ba49d2
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IncludePrivate/RegisterAccess.h
@@ -0,0 +1,288 @@
+/** @file
+ Header file for register access.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _REGISTER_ACCESS_H_
+#define _REGISTER_ACCESS_H_
+
+typedef struct _REGISTER_ACCESS REGISTER_ACCESS;
+
+/**
+ Reads an 8-bit register
+
+ @param[in] This Pointer to REGISTER_ACCESS
+ @param[in] Offset Offset of the register in the register bank
+
+ @return The 8-bit register value specified by Offset
+**/
+typedef
+UINT8
+(*REG_READ8) (
+ IN REGISTER_ACCESS *This,
+ IN UINT32 Offset
+ );
+
+/**
+ Writes an 8-bit register
+
+ @param[in] This Pointer to REGISTER_ACCESS
+ @param[in] Offset Offset of the register in the register bank
+ @param[in] Value Value to write to register
+
+ @return The 8-bit register value written to register
+**/
+typedef
+UINT8
+(*REG_WRITE8) (
+ IN REGISTER_ACCESS *This,
+ IN UINT32 Offset,
+ IN UINT8 Value
+ );
+
+/**
+ Performs an 8-bit or on the register
+
+ @param[in] This Pointer to REGISTER_ACCESS
+ @param[in] Offset Offset of the register in the register bank
+ @param[in] OrData Data with which register should be OR-ed
+
+ @return The 8-bit register value written to register
+**/
+typedef
+UINT8
+(*REG_OR8) (
+ IN REGISTER_ACCESS *This,
+ IN UINT32 Offset,
+ IN UINT8 OrData
+ );
+
+/**
+ Performs an 8-bit and on the register
+
+ @param[in] This Pointer to REGISTER_ACCESS
+ @param[in] Offset Offset of the register in the register bank
+ @param[in] AndData Data with which register should be AND-ed
+
+ @return The 8-bit register value written to register
+**/
+typedef
+UINT8
+(*REG_AND8) (
+ IN REGISTER_ACCESS *This,
+ IN UINT32 Offset,
+ IN UINT8 AndData
+ );
+
+/**
+ Performs an 8-bit and then or on the register
+
+ @param[in] This Pointer to REGISTER_ACCESS
+ @param[in] Offset Offset of the register in the register bank
+ @param[in] AndData Data with which register should be AND-ed
+ @param[in] OrData Data with which register should be OR-ed
+
+ @return The 8-bit register value written to register
+**/
+typedef
+UINT8
+(*REG_AND_THEN_OR8) (
+ IN REGISTER_ACCESS *This,
+ IN UINT32 Offset,
+ IN UINT8 AndData,
+ IN UINT8 OrData
+ );
+
+/**
+ Reads a 16-bit register
+
+ @param[in] This Pointer to REGISTER_ACCESS
+ @param[in] Offset Offset of the register in the register bank
+
+ @return The 16-bit register value specified by Offset
+**/
+typedef
+UINT16
+(*REG_READ16) (
+ IN REGISTER_ACCESS *This,
+ IN UINT32 Offset
+ );
+
+/**
+ Writes a 16-bit register
+
+ @param[in] This Pointer to REGISTER_ACCESS
+ @param[in] Offset Offset of the register in the register bank
+ @param[in] Value Value to write to register
+
+ @return The 16-bit register value written to register
+**/
+typedef
+UINT16
+(*REG_WRITE16) (
+ IN REGISTER_ACCESS *This,
+ IN UINT32 Offset,
+ IN UINT16 Value
+ );
+
+/**
+ Performs a 16-bit or on the register
+
+ @param[in] This Pointer to REGISTER_ACCESS
+ @param[in] Offset Offset of the register in the register bank
+ @param[in] OrData Data with which register should be OR-ed
+
+ @return The 16-bit register value written to register
+**/
+typedef
+UINT16
+(*REG_OR16) (
+ IN REGISTER_ACCESS *This,
+ IN UINT32 Offset,
+ IN UINT16 OrData
+ );
+
+/**
+ Performs a 16-bit and on the register
+
+ @param[in] This Pointer to REGISTER_ACCESS
+ @param[in] Offset Offset of the register in the register bank
+ @param[in] AndData Data with which register should be AND-ed
+
+ @return The 16-bit register value written to register
+**/
+typedef
+UINT16
+(*REG_AND16) (
+ IN REGISTER_ACCESS *This,
+ IN UINT32 Offset,
+ IN UINT16 AndData
+ );
+
+/**
+ Performs a 16-bit and then or on the register
+
+ @param[in] This Pointer to REGISTER_ACCESS
+ @param[in] Offset Offset of the register in the register bank
+ @param[in] AndData Data with which register should be AND-ed
+ @param[in] OrData Data with which register should be OR-ed
+
+ @return The 16-bit register value written to register
+**/
+typedef
+UINT16
+(*REG_AND_THEN_OR16) (
+ IN REGISTER_ACCESS *This,
+ IN UINT32 Offset,
+ IN UINT16 AndData,
+ IN UINT16 OrData
+ );
+
+/**
+ Reads a 32-bit register
+
+ @param[in] This Pointer to REGISTER_ACCESS
+ @param[in] Offset Offset of the register in the register bank
+
+ @return The 32-bit register value specified by Offset
+**/
+typedef
+UINT32
+(*REG_READ32) (
+ IN REGISTER_ACCESS *This,
+ IN UINT32 Offset
+ );
+
+/**
+ Writes a 32-bit register
+
+ @param[in] This Pointer to REGISTER_ACCESS
+ @param[in] Offset Offset of the register in the register bank
+ @param[in] Value Value to write to register
+
+ @return The 32-bit register value written to register
+**/
+typedef
+UINT32
+(*REG_WRITE32) (
+ IN REGISTER_ACCESS *This,
+ IN UINT32 Offset,
+ IN UINT32 Value
+ );
+
+/**
+ Performs a 32-bit or on the register
+
+ @param[in] This Pointer to REGISTER_ACCESS
+ @param[in] Offset Offset of the register in the register bank
+ @param[in] OrData Data with which register should be OR-ed
+
+ @return The 32-bit register value written to register
+**/
+typedef
+UINT32
+(*REG_OR32) (
+ IN REGISTER_ACCESS *This,
+ IN UINT32 Offset,
+ IN UINT32 OrData
+ );
+
+/**
+ Performs a 32-bit and on the register
+
+ @param[in] This Pointer to REGISTER_ACCESS
+ @param[in] Offset Offset of the register in the register bank
+ @param[in] AndData Data with which register should be AND-ed
+
+ @return The 32-bit register value written to register
+**/
+typedef
+UINT32
+(*REG_AND32) (
+ IN REGISTER_ACCESS *This,
+ IN UINT32 Offset,
+ IN UINT32 AndData
+ );
+
+/**
+ Performs a 32-bit and then or on the register
+
+ @param[in] This Pointer to REGISTER_ACCESS
+ @param[in] Offset Offset of the register in the register bank
+ @param[in] AndData Data with which register should be AND-ed
+ @param[in] OrData Data with which register should be OR-ed
+
+ @return The 32-bit register value written to register
+**/
+typedef
+UINT32
+(*REG_AND_THEN_OR32) (
+ IN REGISTER_ACCESS *This,
+ IN UINT32 Offset,
+ IN UINT32 AndData,
+ IN UINT32 OrData
+ );
+
+struct _REGISTER_ACCESS {
+ REG_READ8 Read8;
+ REG_WRITE8 Write8;
+ REG_OR8 Or8;
+ REG_AND8 And8;
+ REG_AND_THEN_OR8 AndThenOr8;
+
+ REG_READ16 Read16;
+ REG_WRITE16 Write16;
+ REG_OR16 Or16;
+ REG_AND16 And16;
+ REG_AND_THEN_OR16 AndThenOr16;
+
+ REG_READ32 Read32;
+ REG_WRITE32 Write32;
+ REG_OR32 Or32;
+ REG_AND32 And32;
+ REG_AND_THEN_OR32 AndThenOr32;
+};
+
+#endif
--
2.36.1.windows.1
-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#108745): https://edk2.groups.io/g/devel/message/108745
Mute This Topic: https://groups.io/mt/101373953/7686176
Group Owner: devel+owner@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [rebecca@openfw.io]
-=-=-=-=-=-=-=-=-=-=-=-
^ permalink raw reply related [flat|nested] 41+ messages in thread
* Re: [edk2-devel] [PATCH v2 10/10] AlderlakeSiliconPkg: Add Alderlake Product and SiPkg.dec
2023-09-15 4:45 ` [edk2-devel] [PATCH v2 10/10] AlderlakeSiliconPkg: Add Alderlake Product and SiPkg.dec Saloni Kasbekar
2023-09-15 5:43 ` Chaganty, Rangasai V
@ 2023-09-15 23:57 ` Nate DeSimone
1 sibling, 0 replies; 41+ messages in thread
From: Nate DeSimone @ 2023-09-15 23:57 UTC (permalink / raw)
To: Kasbekar, Saloni, devel@edk2.groups.io
Cc: Chaganty, Rangasai V, Chuang, Rosen
Acked-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
-----Original Message-----
From: Kasbekar, Saloni <saloni.kasbekar@intel.com>
Sent: Thursday, September 14, 2023 9:46 PM
To: devel@edk2.groups.io
Cc: Kasbekar, Saloni <saloni.kasbekar@intel.com>; Chaganty, Rangasai V <rangasai.v.chaganty@intel.com>; Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>; Chuang, Rosen <rosen.chuang@intel.com>
Subject: [PATCH v2 10/10] AlderlakeSiliconPkg: Add Alderlake Product and SiPkg.dec
Adds the following modules:
- Product/Alderlake/Include
- Product/Alderlake/Library
- Product/Alderlake DSCs
- SiPkg.dec
Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Rosen Chuang <rosen.chuang@intel.com>
Signed-off-by: Saloni Kasbekar <saloni.kasbekar@intel.com>
---
.../Product/Alderlake/Include/Ppi/SiPolicy.h | 55 ++
.../Library/PeiSiPolicyLib/PeiSiPolicyLib.c | 47 ++
.../Library/PeiSiPolicyLib/PeiSiPolicyLib.inf | 47 ++
.../PeiSiPolicyLib/PeiSiPolicyLibPreMem.c | 47 ++
.../PeiSiPolicyLib/PeiSiPolicyLibrary.h | 21 +
.../Product/Alderlake/SiPkgBuildOption.dsc | 122 ++++
.../Product/Alderlake/SiPkgCommonLib.dsc | 36 +
.../Product/Alderlake/SiPkgDxe.dsc | 32 +
.../Product/Alderlake/SiPkgDxeLib.dsc | 23 +
.../Product/Alderlake/SiPkgPeiLib.dsc | 19 +
Silicon/Intel/AlderlakeSiliconPkg/SiPkg.dec | 625 ++++++++++++++++++
11 files changed, 1074 insertions(+)
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/Include/Ppi/SiPolicy.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/Library/PeiSiPolicyLib/PeiSiPolicyLib.c
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/Library/PeiSiPolicyLib/PeiSiPolicyLib.inf
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/Library/PeiSiPolicyLib/PeiSiPolicyLibPreMem.c
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/Library/PeiSiPolicyLib/PeiSiPolicyLibrary.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/SiPkgBuildOption.dsc
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/SiPkgCommonLib.dsc
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/SiPkgDxe.dsc
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/SiPkgDxeLib.dsc
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/SiPkgPeiLib.dsc
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/SiPkg.dec
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/Include/Ppi/SiPolicy.h b/Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/Include/Ppi/SiPolicy.h
new file mode 100644
index 0000000000..703f0221bd
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/Include/Ppi/Si
+++ Policy.h
@@ -0,0 +1,55 @@
+/** @file
+ Silicon Policy PPI is used for specifying platform
+ related Intel silicon information and policy setting.
+ This PPI is consumed by the silicon PEI modules and carried
+ over to silicon DXE modules.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/
+
+#ifndef _SI_POLICY_PPI_H_
+#define _SI_POLICY_PPI_H_
+
+#include <SiPolicyStruct.h>
+#include <PchPolicyCommon.h>
+#include <PchPreMemPolicyCommon.h>
+#include <Uefi.h>
+#include <ConfigBlock/CpuConfig.h>
+#include <ConfigBlock/CpuConfigLibPreMemConfig.h>
+#include <ConfigBlock/CpuSecurityPreMemConfig.h>
+
+#ifndef DISABLED
+#define DISABLED 0
+#endif
+#ifndef ENABLED
+#define ENABLED 1
+#endif
+
+extern EFI_GUID gSiPreMemPolicyPpiGuid; extern EFI_GUID
+gSiPolicyPpiGuid;
+
+
+#include <GraphicsConfig.h>
+
+
+#include <CpuPcieConfigGen3.h>
+#include <CpuPcieConfig.h>
+extern EFI_GUID gCpuPciePeiPreMemConfigGuid; extern EFI_GUID
+gCpuPcieRpConfigGuid;
+
+#include <MemoryConfig.h>
+extern EFI_GUID gMemoryConfigGuid;
+extern EFI_GUID gMemoryConfigNoCrcGuid;
+
+#include <ConfigBlock/SaMiscPeiPreMemConfig.h>
+extern EFI_GUID gSaMiscPeiPreMemConfigGuid;
+
+#include <HostBridgeConfig.h>
+extern EFI_GUID gHostBridgePeiPreMemConfigGuid; extern EFI_GUID
+gHostBridgePeiConfigGuid;
+
+typedef struct _SI_PREMEM_POLICY_STRUCT SI_PREMEM_POLICY_PPI; typedef
+struct _SI_POLICY_STRUCT SI_POLICY_PPI;
+
+#endif // _SI_POLICY_PPI_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/Library/PeiSiPolicyLib/PeiSiPolicyLib.c b/Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/Library/PeiSiPolicyLib/PeiSiPolicyLib.c
new file mode 100644
index 0000000000..886415bdaa
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/Library/PeiSiP
+++ olicyLib/PeiSiPolicyLib.c
@@ -0,0 +1,47 @@
+/** @file
+ This file is PeiSiPolicyLib library creates default settings of RC
+ Policy and installs RC Policy PPI.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/ #include
+"PeiSiPolicyLibrary.h"
+#include <Library/PcdLib.h>
+#include <Library/PchInfoLib.h>
+
+
+/**
+ SiInstallPolicyReadyPpi installs SiPolicyReadyPpi.
+ While installed, RC assumes the Policy is ready and finalized. So
+please update and override
+ any setting before calling this function.
+
+ @retval EFI_SUCCESS The policy is installed.
+ @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer
+**/
+EFI_STATUS
+EFIAPI
+SiInstallPolicyReadyPpi (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+ EFI_PEI_PPI_DESCRIPTOR *SiPolicyReadyPpiDesc;
+
+ SiPolicyReadyPpiDesc = (EFI_PEI_PPI_DESCRIPTOR *) AllocateZeroPool
+ (sizeof (EFI_PEI_PPI_DESCRIPTOR)); if (SiPolicyReadyPpiDesc == NULL) {
+ ASSERT (FALSE);
+ return EFI_OUT_OF_RESOURCES;
+ }
+
+ SiPolicyReadyPpiDesc->Flags = EFI_PEI_PPI_DESCRIPTOR_PPI |
+ EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST;
+ SiPolicyReadyPpiDesc->Guid = &gSiPolicyReadyPpiGuid;
+ SiPolicyReadyPpiDesc->Ppi = NULL;
+
+ //
+ // Install Silicon Policy Ready PPI
+ //
+ Status = PeiServicesInstallPpi (SiPolicyReadyPpiDesc);
+ ASSERT_EFI_ERROR (Status);
+ return Status;
+}
+
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/Library/PeiSiPolicyLib/PeiSiPolicyLib.inf b/Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/Library/PeiSiPolicyLib/PeiSiPolicyLib.inf
new file mode 100644
index 0000000000..7dab1ff510
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/Library/PeiSiP
+++ olicyLib/PeiSiPolicyLib.inf
@@ -0,0 +1,47 @@
+## @file
+# Component description file for the PeiSiPolicyLib library.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+
+[Defines]
+INF_VERSION = 0x00010017
+BASE_NAME = PeiSiPolicyLib
+FILE_GUID = 97584FAE-9299-4202-9889-2D339E4BFA5B
+VERSION_STRING = 1.0
+MODULE_TYPE = PEIM
+LIBRARY_CLASS = SiPolicyLib
+
+
+[LibraryClasses]
+DebugLib
+IoLib
+PeiServicesLib
+BaseMemoryLib
+MemoryAllocationLib
+ConfigBlockLib
+PcdLib
+CpuPlatformLib
+
+[Packages]
+MdePkg/MdePkg.dec
+AlderlakeSiliconPkg/SiPkg.dec
+
+[Sources]
+PeiSiPolicyLib.c
+PeiSiPolicyLibrary.h
+PeiSiPolicyLibPreMem.c
+
+
+[Guids]
+gSiConfigGuid ## CONSUMES
+gSiPreMemConfigGuid ## CONSUMES
+gPciePreMemConfigGuid ## CONSUMES
+
+[Ppis]
+gSiPolicyPpiGuid ## PRODUCES
+gSiPreMemPolicyPpiGuid ## PRODUCES
+gSiPolicyReadyPpiGuid ## CONSUMES
+gSiPreMemPolicyReadyPpiGuid ## CONSUMES
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/Library/PeiSiPolicyLib/PeiSiPolicyLibPreMem.c b/Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/Library/PeiSiPolicyLib/PeiSiPolicyLibPreMem.c
new file mode 100644
index 0000000000..93bffac2b0
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/Library/PeiSiP
+++ olicyLib/PeiSiPolicyLibPreMem.c
@@ -0,0 +1,47 @@
+/** @file
+ This file is PeiSiPolicyLib library creates default settings of RC
+ Policy and installs RC Policy PPI.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/ #include
+"PeiSiPolicyLibrary.h"
+#include <Base.h>
+#include <PciePreMemConfig.h>
+#include <Library/PchInfoLib.h>
+#include <Library/CpuPlatformLib.h>
+
+/**
+ SiPreMemInstallPolicyReadyPpi installs SiPreMemPolicyReadyPpi.
+ While installed, RC assumes the Policy is ready and finalized. So
+please update and override
+ any setting before calling this function.
+
+ @retval EFI_SUCCESS The policy is installed.
+ @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer
+**/
+EFI_STATUS
+EFIAPI
+SiPreMemInstallPolicyReadyPpi (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+ EFI_PEI_PPI_DESCRIPTOR *SiPolicyReadyPreMemPpiDesc;
+
+ SiPolicyReadyPreMemPpiDesc = (EFI_PEI_PPI_DESCRIPTOR *)
+ AllocateZeroPool (sizeof (EFI_PEI_PPI_DESCRIPTOR)); if (SiPolicyReadyPreMemPpiDesc == NULL) {
+ ASSERT (FALSE);
+ return EFI_OUT_OF_RESOURCES;
+ }
+
+ SiPolicyReadyPreMemPpiDesc->Flags = EFI_PEI_PPI_DESCRIPTOR_PPI |
+ EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST;
+ SiPolicyReadyPreMemPpiDesc->Guid = &gSiPreMemPolicyReadyPpiGuid;
+ SiPolicyReadyPreMemPpiDesc->Ppi = NULL;
+
+ //
+ // Install PreMem Silicon Policy Ready PPI
+ //
+ Status = PeiServicesInstallPpi (SiPolicyReadyPreMemPpiDesc);
+ ASSERT_EFI_ERROR (Status);
+ return Status;
+}
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/Library/PeiSiPolicyLib/PeiSiPolicyLibrary.h b/Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/Library/PeiSiPolicyLib/PeiSiPolicyLibrary.h
new file mode 100644
index 0000000000..aac24cf187
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/Library/PeiSiP
+++ olicyLib/PeiSiPolicyLibrary.h
@@ -0,0 +1,21 @@
+/** @file
+ Header file for the PeiSiPolicyLib library.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent **/ #ifndef
+_PEI_SI_POLICY_LIBRARY_H_ #define _PEI_SI_POLICY_LIBRARY_H_
+
+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/PeiServicesLib.h>
+#include <Library/MemoryAllocationLib.h> #include
+<Library/ConfigBlockLib.h> #include <Ppi/SiPolicy.h> #include
+<Library/SiPolicyLib.h>
+
+
+
+#endif // _PEI_SI_POLICY_LIBRARY_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/SiPkgBuildOption.dsc b/Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/SiPkgBuildOption.dsc
new file mode 100644
index 0000000000..290d6eb885
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/SiPkgBuildOpti
+++ on.dsc
@@ -0,0 +1,122 @@
+## @file
+# Silicon build option configuration file.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+[BuildOptions]
+# Define Build Options both for EDK and EDKII drivers.
+
+# SA
+!if gSiPkgTokenSpaceGuid.PcdAdlLpSupport == TRUE DEFINE
+PCH_BUILD_OPTIONS = -DPCH_ADPP !else DEFINE PCH_BUILD_OPTIONS =
+-DPCH_ADL !endif # # SA # !if gSiPkgTokenSpaceGuid.PcdBdatEnable ==
+TRUE
+ DEFINE BDAT_BUILD_OPTION = -DBDAT_SUPPORT=1 !else
+ DEFINE BDAT_BUILD_OPTION =
+!endif
+
+ DEFINE SLE_BUILD_OPTIONS =
+!if $(TARGET) == RELEASE
+!if gSiPkgTokenSpaceGuid.PcdSiCatalogDebugEnable == TRUE
+ DEFINE DEBUG_BUILD_OPTIONS =
+!else
+ # MDEPKG_NDEBUG is introduced for the intention
+ # of size reduction when compiler optimization is disabled. If
+MDEPKG_NDEBUG is
+ # defined, then debug and assert related macros wrapped by it are the NULL implementations.
+ DEFINE DEBUG_BUILD_OPTIONS = -DMDEPKG_NDEBUG !endif !else
+ DEFINE DEBUG_BUILD_OPTIONS =
+!endif
+
+!if ($(TARGET) == RELEASE) AND
+(gSiPkgTokenSpaceGuid.PcdSiCatalogDebugEnable == TRUE)
+ DEFINE RELEASE_CATALOG_BUILD_OPTIONS = -DRELEASE_CATALOG !else
+ DEFINE RELEASE_CATALOG_BUILD_OPTIONS = !endif
+
+!if gSiPkgTokenSpaceGuid.PcdOptimizeCompilerEnable == FALSE
+ DEFINE OPTIMIZE_DISABLE_OPTIONS = -Od -GL- !else
+ DEFINE OPTIMIZE_DISABLE_OPTIONS =
+!endif
+
+ DEFINE HSLE_BUILD_OPTIONS =
+
+
+DEFINE CPU_FLAGS = -DCPU_ADL
+
+
+DEFINE DSC_SIPKG_FEATURE_BUILD_OPTIONS = $(BDAT_BUILD_OPTION)
+$(DEBUG_BUILD_OPTIONS) DEFINE DSC_SIPKG_FEATURE_BUILD_OPTIONS =
+$(DSC_SIPKG_FEATURE_BUILD_OPTIONS) $(PCH_BUILD_OPTIONS) $(CPU_FLAGS)
+$(HSLE_BUILD_OPTIONS)
+
+!if gSiPkgTokenSpaceGuid.PcdSourceDebugEnable == TRUE
+ *_*_X64_GENFW_FLAGS = --keepexceptiontable !endif
+
+[BuildOptions.Common.EDKII]
+
+#
+# For IA32 Global Build Flag
+#
+ *_*_IA32_CC_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) -D PI_SPECIFICATION_VERSION=0x00010015 -DASF_PEI
+ *_*_IA32_VFRPP_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS)
+ *_*_IA32_APP_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS)
+ *_*_IA32_ASLPP_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS)
+ *_*_IA32_ASLCC_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS)
+
+#
+# For IA32 Specific Build Flag
+#
+CLANGPDB:*_*_IA32_CC_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) -D PI_SPECIFICATION_VERSION=0x00010015 -DASF_PEI -Wno-enum-conversion -Wno-incompatible-pointer-types-discards-qualifiers -Wno-sometimes-uninitialized -Wno-braced-scalar-init -Wno-nonportable-include-path -Wno-misleading-indentation
+GCC: *_*_IA32_PP_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS)
+MSFT: *_*_IA32_ASM_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS)
+MSFT: *_*_IA32_CC_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) $(OPTIMIZE_DISABLE_OPTIONS) -D PI_SPECIFICATION_VERSION=0x00010015 -DASF_PEI /w34668
+MSFT: *_*_IA32_VFRPP_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) $(OPTIMIZE_DISABLE_OPTIONS)
+MSFT: *_*_IA32_APP_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) $(OPTIMIZE_DISABLE_OPTIONS)
+MSFT: *_*_IA32_ASLPP_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) $(OPTIMIZE_DISABLE_OPTIONS)
+MSFT: *_*_IA32_ASLCC_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) $(OPTIMIZE_DISABLE_OPTIONS)
+
+#
+# For X64 Global Build Flag
+#
+ *_*_X64_CC_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) -D PI_SPECIFICATION_VERSION=0x00010015
+ *_*_X64_VFRPP_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS)
+ *_*_X64_APP_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS)
+ *_*_X64_ASLPP_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS)
+ *_*_X64_ASLCC_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS)
+
+#
+# For X64 Specific Build Flag
+#
+CLANGPDB:*_*_X64_CC_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) -D PI_SPECIFICATION_VERSION=0x00010015 -Wno-enum-conversion -Wno-main-return-type -Wno-incompatible-pointer-types -Wno-implicit-function-declaration -Wno-unused-variable -Wno-incompatible-pointer-types-discards-qualifiers -Wno-ignored-pragma-optimize -Wno-bitwise-op-parentheses -Wno-sometimes-uninitialized -Wno-unused-function -Wno-misleading-indentation
+GCC: *_*_X64_PP_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS)
+MSFT: *_*_X64_ASM_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS)
+MSFT: *_*_X64_CC_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) $(OPTIMIZE_DISABLE_OPTIONS) -D PI_SPECIFICATION_VERSION=0x00010015 /w34668
+MSFT: *_*_X64_VFRPP_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) $(OPTIMIZE_DISABLE_OPTIONS)
+MSFT: *_*_X64_APP_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) $(OPTIMIZE_DISABLE_OPTIONS)
+MSFT: *_*_X64_ASLPP_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS)
+MSFT: *_*_X64_ASLCC_FLAGS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS)
+
+#
+# For Xcode Specific Build Flag
+#
+# Override assembly code build order
+*_XCODE5_*_*_BUILDRULEORDER = nasm S s
+# Align 47bfbd7f8069e523798ef973c8eb0abd5c6b0746 to fix the usage of
+VA_START in undefined way *_XCODE5_*_CC_FLAGS = -Wno-varargs
+
+# Force PE/COFF sections to be aligned at 4KB boundaries to support
+page level protection of runtime modules [BuildOptions.common.EDKII.DXE_RUNTIME_DRIVER]
+ MSFT: *_*_*_DLINK_FLAGS = /ALIGN:4096
+ GCC: *_GCC*_*_DLINK_FLAGS = -z common-page-size=0x1000
+
+
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/SiPkgCommonLib.dsc b/Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/SiPkgCommonLib.dsc
new file mode 100644
index 0000000000..69eca2ecc1
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/SiPkgCommonLib
+++ .dsc
@@ -0,0 +1,36 @@
+## @file
+# Component description file for the AlderLake SiPkg both Pei and Dxe libraries DSC file.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+#
+#
+# FRUs
+#
+!include $(PLATFORM_SI_PACKAGE)/Fru/AdlCpu/CommonLib.dsc
+!include $(PLATFORM_SI_PACKAGE)/Fru/AdlPch/CommonLib.dsc
+#
+# Common
+#
+ PciSegmentLib|$(PLATFORM_SI_PACKAGE)/Library/BasePciSegmentMultiSegLib
+ PciSegmentLib|Pci/BasePciSegmentMultiSegLibPci.inf
+
+#
+# Cpu
+#
+ CpuPlatformLib|$(PLATFORM_SI_PACKAGE)/Cpu/Library/PeiDxeSmmCpuPlatform
+ CpuPlatformLib|Lib/PeiDxeSmmCpuPlatformLib.inf
+
+#
+# Pch
+#
+ PchCycleDecodingLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/PeiDxeSmmPchCyc
+ PchCycleDecodingLib|leDecodingLib/PeiDxeSmmPchCycleDecodingLib.inf
+
+ ResetSystemLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/BaseResetSystemLib/B
+ ResetSystemLib|aseResetSystemLib.inf
+#private
+ GpioPrivateLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Gpio/LibraryPrivate/PeiD
+ GpioPrivateLib|xeSmmGpioPrivateLib/PeiDxeSmmGpioPrivateLibVer2.inf
+ PchPciBdfLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/BasePchPciBdfLib/BaseP
+ PchPciBdfLib|chPciBdfLib.inf
+
+#
+# SA
+#
+ GraphicsInfoLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Graphics/Library/PeiDxe
+ GraphicsInfoLib|SmmGraphicsInfoLib/GraphicsInfoLibVer1.inf
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/SiPkgDxe.dsc b/Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/SiPkgDxe.dsc
new file mode 100644
index 0000000000..97e63dcc96
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/SiPkgDxe.dsc
@@ -0,0 +1,32 @@
+## @file
+# Component description file for the AlderLake SiPkg DXE drivers.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+#
+# FRUs
+#
+!include $(PLATFORM_SI_PACKAGE)/Fru/AdlPch/Dxe.dsc
+#
+# Common
+#
+
+#
+# Pch
+#
+ $(PLATFORM_SI_PACKAGE)/Pch/SmmControl/RuntimeDxe/SmmControl.inf
+
+ $(PLATFORM_SI_PACKAGE)/Pch/PchSmiDispatcher/Smm/PchSmiDispatcher.inf{
+ <LibraryClasses>
+
+ SmiHandlerProfileLib|MdePkg/Library/SmiHandlerProfileLibNull/SmiHandle
+ rProfileLibNull.inf
+ }
+
+#
+# SystemAgent
+#
+ $(PLATFORM_SI_PACKAGE)/SystemAgent/SaInit/Dxe/SaInitDxe.inf
+
+
+
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/SiPkgDxeLib.dsc b/Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/SiPkgDxeLib.dsc
new file mode 100644
index 0000000000..37876cbfc4
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/SiPkgDxeLib.ds
+++ c
@@ -0,0 +1,23 @@
+# @file
+# Component description file for the AlderLake SiPkg DXE libraries.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+#
+# FRUs
+#
+!include $(PLATFORM_SI_PACKAGE)/Fru/AdlCpu/DxeLib.dsc
+!include $(PLATFORM_SI_PACKAGE)/Fru/AdlPch/DxeLib.dsc
+
+#
+# Common
+#
+ AslUpdateLib|IntelSiliconPkg/Library/DxeAslUpdateLib/DxeAslUpdateLib.i
+ AslUpdateLib|nf
+ SiConfigBlockLib|$(PLATFORM_SI_PACKAGE)/Library/BaseSiConfigBlockLib/B
+ SiConfigBlockLib|aseSiConfigBlockLib.inf
+
+#
+# SystemAgent
+#
+ DxeSaPolicyLib|$(PLATFORM_SI_PACKAGE)/SystemAgent/Library/DxeSaPolicyL
+ DxeSaPolicyLib|ib/DxeSaPolicyLib.inf
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/SiPkgPeiLib.dsc b/Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/SiPkgPeiLib.dsc
new file mode 100644
index 0000000000..21e6ff3851
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/Product/Alderlake/SiPkgPeiLib.ds
+++ c
@@ -0,0 +1,19 @@
+## @file
+# Component description file for the AlderLake SiPkg PEI libraries.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+#
+# FRUs
+#
+!include $(PLATFORM_SI_PACKAGE)/Fru/AdlPch/PeiLib.dsc
+
+
+ SiPolicyLib|$(PLATFORM_SI_PACKAGE)/Product/Alderlake/Library/PeiSiPoli
+ SiPolicyLib|cyLib/PeiSiPolicyLib.inf
+ SiConfigBlockLib|$(PLATFORM_SI_PACKAGE)/Library/BaseSiConfigBlockLib/B
+ SiConfigBlockLib|aseSiConfigBlockLib.inf
+
+
+
+
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/SiPkg.dec b/Silicon/Intel/AlderlakeSiliconPkg/SiPkg.dec
new file mode 100644
index 0000000000..ce9cfe599a
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/SiPkg.dec
@@ -0,0 +1,625 @@
+## @file
+# Component description file for the Silicon Reference Code.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+
+[Defines]
+DEC_SPECIFICATION = 0x00010017
+PACKAGE_NAME = SiPkg
+PACKAGE_VERSION = 0.1
+PACKAGE_GUID = F245E276-44A0-46b3-AEB5-9898BBCF008D
+
+[Includes.Common.Private]
+
+#
+# AlderLake Fru
+#
+Fru/AdlCpu/IncludePrivate
+Fru/AdlPch/IncludePrivate
+
+##
+# IpBlock IncludePrivate
+#
+IpBlock/Pmc/IncludePrivate
+IpBlock/Graphics/IncludePrivate
+IpBlock/PchDmi/IncludePrivate
+IpBlock/P2sb/IncludePrivate
+IpBlock/Spi/IncludePrivate
+IpBlock/Gpio/IncludePrivate
+IpBlock/HostBridge/IncludePrivate
+
+# Cpu
+Cpu/IncludePrivate
+
+IncludePrivate
+
+[Includes]
+Product/Alderlake/Include
+#
+# AlderLake
+#
+Fru/AdlCpu/Include
+Fru/AdlPch/Include
+
+
+# CPU PCIe
+IpBlock/CpuPcieRp/Include
+
+#
+# - Memory
+Include/ConfigBlock/Memory/Ver2
+#
+# - Graphics
+Include/ConfigBlock/Graphics/Gen12
+IpBlock/Graphics/Include
+
+#
+# - CPU PCIe
+Include/ConfigBlock/CpuPcieRp/Gen4
+
+#
+# HostBridge
+#
+Include/ConfigBlock/HostBridge/Ver1
+
+Include
+#
+# SystemAgent
+#
+SystemAgent/Include
+Include/ConfigBlock/PcieRp
+Include/ConfigBlock/Vmd
+Include/ConfigBlock/CpuPcieRp/Gen4
+Include/ConfigBlock/CpuPcieRp/Gen3
+
+#
+# Cpu
+#
+Cpu/Include
+
+
+#
+# Pch
+#
+Pch/Include
+Include/ConfigBlock/Espi
+Include/ConfigBlock/Smbus
+Include/ConfigBlock/Pmc
+Include/ConfigBlock/PchDmi
+Include/ConfigBlock/Wdt
+Include/ConfigBlock/PcieRp/PchPcieRp
+Include/ConfigBlock/PcieRp
+Include/ConfigBlock/SerialIo
+
+[Guids.common.Private]
+#
+# PCH
+#
+gGpioLibUnlockHobGuid = { 0xA7892E49, 0x0F9F, 0x4166, { 0xB8, 0xD6, 0x8A, 0x9B, 0xD9, 0x8B, 0x17, 0x38 }}
+
+[Guids]
+gSmbiosProcessorInfoHobGuid = {0xe6d73d92, 0xff56, 0x4146, {0xaf, 0xac, 0x1c, 0x18, 0x81, 0x7d, 0x68, 0x71}}
+gSmbiosCacheInfoHobGuid = {0xd805b74e, 0x1460, 0x4755, {0xbb, 0x36, 0x1e, 0x8c, 0x8a, 0xd6, 0x78, 0xd7}}
+
+##
+## MdeModulePkg
+##
+gEfiMemoryTypeInformationGuid = {0x4c19049f, 0x4137, 0x4dd3, {0x9c,
+0x10, 0x8b, 0x97, 0xa8, 0x3f, 0xfd, 0xfa}} gEfiCapsuleVendorGuid =
+{0x711c703f, 0xc285, 0x4b10, {0xa3, 0xb0, 0x36, 0xec, 0xbd, 0x3c, 0x8b,
+0xe2}} gEfiConsoleOutDeviceGuid = { 0xd3b36f2c, 0xd551, 0x11d4, { 0x9a,
+0x46, 0x0, 0x90, 0x27, 0x3f, 0xc1, 0x4d}} ## ## Common ## ##
+Include/ConfigBlock/SiConfig.h gSiConfigGuid = {0x4ed6d282, 0x22f3,
+0x4fe1, {0xa6, 0x61, 0x6, 0x1a, 0x97, 0x38, 0x59, 0xd8}} ##
+gSiPreMemConfigGuid = {0xb94c004c, 0xa0ab, 0x40f0, {0x9b, 0x61, 0x0b,
+0x25, 0x88, 0xbe, 0xfd, 0xc6}} ## ## gPciePreMemConfigGuid =
+{0xd0f9c2a9, 0x7332, 0x4733, {0x8d, 0xb1, 0x98, 0x79, 0x27, 0x60, 0xda,
+0xe6}} ## gSiPkgTokenSpaceGuid = {0x977c97c1, 0x47e1, 0x4b6b, {0x96,
+0x69, 0x43, 0x66, 0x99, 0xcb, 0xe4, 0x5b}}
+
+gSiConfigHobGuid = {0xb3903068, 0x7482, 0x4424, {0xba, 0x4b, 0x40,
+0x5f, 0x8f, 0xd7, 0x65, 0x4e}}
+
+##
+##
+## SystemAgent
+##
+gSaDataHobGuid = {0xe07d0bda, 0xbf90, 0x46a9, { 0xb0, 0x0e, 0xb2,
+0xc4, 0x4a, 0x0e, 0xd6, 0xd0}} gSaConfigHobGuid = {0x762fa2e6, 0xea3b,
+0x41c8, { 0x8c, 0x52, 0x63, 0x76, 0x6d, 0x70, 0x39, 0xe0}}
+gSaMiscPeiPreMemConfigGuid = {0x4a525577, 0x3469, 0x4f11, { 0x99,
+0xcf, 0xfb, 0xcd, 0x5e, 0xf1, 0x84, 0xe4}} gCpuPciePeiPreMemConfigGuid = { 0x81baf3c9, 0xf295, 0x4572, { 0x8b, 0x21, 0x79, 0x3f, 0xa3, 0x1b, 0xa5, 0xdb}} gVmdPeiConfigGuid = { 0x79b52c74, 0xb9ba, 0x4f36, {0xa2, 0x40, 0xf2, 0x41, 0x0d, 0x20, 0x84, 0x8a}}
+gVmdInfoHobGuid = { 0xccd0306e, 0x7fa1, 0x4df5, {0x99, 0x99, 0xc1, 0xf8, 0x9a, 0x1d, 0x1b, 0xa9}}
+gMemoryConfigGuid = { 0x26cf084c, 0xc9db, 0x41bb, { 0x92, 0xc6, 0xd1,
+0x97, 0xb8, 0xa1, 0xe4, 0xbf}} gMemoryConfigNoCrcGuid = { 0xc56c73d0,
+0x1cdb, 0x4c0c, { 0xa9, 0x57, 0xea, 0x62, 0xa9, 0xe6, 0xf5, 0x0c}}
+gMemoryDxeConfigGuid = {0xa5c7dda8, 0x686b, 0x404f, {0x86, 0x40,
+0xf8, 0x2, 0xd, 0x84, 0x4c, 0x94}} gCpuPcieRpPrememConfigGuid = {
+0x41aef892, 0xc800, 0x4ac0, {0xa9, 0x30, 0x84, 0xac, 0x47, 0xca, 0xca, 0x7e}} gCpuPcieRpConfigGuid = { 0x9749a5fb, 0x9130, 0x44f0, {0x8f, 0x61, 0xdb, 0xff, 0x8e, 0xf2, 0xca, 0xc7}} ## IntelFsp2Pkg/IntelFsp2Pkg.dec gSiMemoryS3DataGuid is the same as gFspNonVolatileStorageHobGuid
+gSiMemoryS3DataGuid = { 0x721acf02, 0x4d77, 0x4c2a, { 0xb3, 0xdc, 0x27, 0x0b, 0x7b, 0xa9, 0xe4, 0xb0 } }
+gSiMemoryInfoDataGuid = { 0x9b2071d4, 0xb054, 0x4e0c, { 0x8d, 0x09, 0x11, 0xcf, 0x8b, 0x9f, 0x03, 0x23 } }
+gSiMemoryPlatformDataGuid = { 0x6210d62f, 0x418d, 0x4999, { 0xa2, 0x45,
+0x22, 0x10, 0x0a, 0x5d, 0xea, 0x44 } } gSaPciePeiConfigGuid = {
+0xdaa929a9, 0x5ec9, 0x486a, { 0xb0, 0xf7, 0x82, 0x3a, 0x55, 0xc7, 0xb5,
+0xb3}} gSaPciePeiPreMemConfigGuid = { 0xfc5e01a3, 0x69f6, 0x4e35, {
+0x9f, 0xcf, 0x6, 0x68, 0x7b, 0xab, 0x31, 0xd7}}
+
+#
+# Host Bridge
+#
+gHostBridgePeiPreMemConfigGuid = {0xbdef6805, 0x2080, 0x44ad, { 0x93,
+0x2e, 0x00, 0x04, 0xf5, 0x2c, 0xb7, 0xa1}} gHostBridgePeiConfigGuid =
+{0x3b6d998e, 0x8b6e, 0x4f53, { 0xbe, 0x41, 0x7, 0x41, 0x95, 0x53, 0x8a,
+0xaf}} gHostBridgeDataHobGuid = {0x3b682d57, 0xd402, 0x40a6, { 0xb1,
+0x34, 0xa0, 0xc4, 0xf6, 0x31, 0x1d, 0x9}}
+
+#
+# Graphics
+#
+gGraphicsPeiConfigGuid = {0x04249ac0, 0x0088, 0x439f, { 0xa7, 0x4e,
+0xa7, 0x04, 0x2a, 0x06, 0x2f, 0x5d}} gGraphicsDxeConfigGuid =
+{0x34d93161, 0xf78e, 0x4915, {0xad, 0xc4, 0xdb, 0x67, 0x16, 0x42, 0x39,
+0x24}}
+
+## Include/SsaCommonConfig.h
+gSsaPostcodeHookGuid = {0xADF0A27B, 0x61A6, 0x4F18, {0x9E, 0xAC, 0x46,
+0x87, 0xE7, 0x9E, 0x6F, 0xBB}} gSsaBiosVariablesGuid = {0x43eeffe8,
+0xa978, 0x41dc, {0x9d, 0xb6, 0x54, 0xc4, 0x27, 0xf2, 0x7e, 0x2a}}
+gSsaBiosResultsGuid = {0x8f4e928, 0xf5f, 0x46d4, {0x84, 0x10, 0x47,
+0x9f, 0xda, 0x27, 0x9d, 0xb6}} gHobUsageDataGuid = {0xc764a821, 0xec41,
+0x450d, { 0x9c, 0x99, 0x27, 0x20, 0xfc, 0x7c, 0xe1, 0xf6 }}
+
+##
+## Cpu
+##
+gCpuAcpiTableStorageGuid = {0xc38fb0e2, 0x0c43, 0x49c9, {0xb5, 0x44,
+0x9b, 0x17, 0xaa, 0x4d, 0xcb, 0xa3}} gCpuSecurityPreMemConfigGuid =
+{0xfd5c346, 0x8260, 0x4067, {0x94, 0x69, 0xcf, 0x91, 0x68, 0xa3, 0x42,
+0x90}} gCpuConfigLibPreMemConfigGuid = {0xfc1c0ec2, 0xc6b4, 0x4f05,
+{0xbb, 0x85, 0xc8, 0x0, 0x8d, 0x5b, 0x4a, 0xb7}} gCpuConfigGuid =
+{0x48c3aac9, 0xd66c, 0x42e4, {0x9b, 0x1d, 0x39, 0x4, 0x5f, 0x46, 0x53,
+0x41}} gCpuDataHobGuid = {0x1eec629f, 0xf3cf, 0x4b02, { 0xa9, 0xa5,
+0x27, 0xa2, 0x33, 0x20, 0xbe, 0x5d}} ## ## Me ## gPciImrHobGuid =
+{0x49b1eac3, 0x0cd6, 0x451e, {0x96, 0x30, 0x92, 0x4b, 0xc2, 0x69, 0x35,
+0x86}} gTpm2AcpiTableStorageGuid = {0x7d279373, 0xeecc, 0x4d4f,
+{0xae, 0x2f, 0xce, 0xc4, 0xb7, 0x06, 0xb0, 0x6a}} gEdkiiTouchPanelGuid
+= {0x91b1d27b, 0xe126, 0x48d1, {0x82, 0x34, 0xd2, 0x8b, 0x81, 0xc8,
+0x83, 0x62}} gMeDidSentHobGuid = {0x4c3d3af1, 0x1720, 0x4c3f, {0xab,
+0x7c, 0x36, 0x50, 0xbb, 0x5b, 0x85, 0x7e}}
+
+##
+## PCH
+##
+gPchGlobalResetGuid = { 0x9db31b4c, 0xf5ef, 0x48bb, { 0x94, 0x2b,
+0x18, 0x1f, 0x7e, 0x3a, 0x3e, 0x40 }}
+
+gPchGeneralPreMemConfigGuid = {0xC65F62FA, 0x52B9, 0x4837, {0x86,
+0xEB, 0x1A, 0xFB, 0xD4, 0xAD, 0xBB, 0x3E}} gWatchDogPreMemConfigGuid =
+{0xFBCE08CC, 0x60F2, 0x4BDF, {0xB7, 0x88, 0x09, 0xBB, 0x81, 0x65, 0x52,
+0x2B}} gPcieRpPreMemConfigGuid = {0x8377AB38, 0xF8B0, 0x476A, { 0x9C,
+0xA1, 0x68, 0xEA, 0x78, 0x57, 0xD8, 0x2A}} gSmbusPreMemConfigGuid =
+{0x77A6E62C, 0x716B, 0x4386, {0x9E, 0x9C, 0x23, 0xA0, 0x2E, 0x13, 0x7B,
+0x3A}} gLpcPreMemConfigGuid = {0xA6E6032F, 0x1E58, 0x407E, {0x9A,
+0xB8, 0xC6, 0x30, 0xC6, 0xC4, 0x11, 0x8E}} gPchDmiPreMemConfigGuid =
+{0x4DA4AA22, 0xB54A, 0x43D7, {0x87, 0xC8, 0xA3, 0xCF, 0x53, 0xE6, 0xC1,
+0x8A}}
+
+gPchGeneralConfigGuid = {0x6ED94C8C, 0x25F7, 0x4686, {0xB2, 0x46,
+0xCA, 0x4D, 0xE2, 0x95, 0x4B, 0x5D}} gPchPcieConfigGuid =
+{0x0A53B507, 0x988B, 0x475C, {0xBF, 0x76, 0x33, 0xDE, 0x10, 0x6D, 0x94,
+0x84}} gPchPcieRpDxeConfigGuid = {0x475530EA, 0xBD72, 0x416F, {0x98,
+0x9F,0x48, 0x70, 0x5F, 0x14, 0x4E, 0xD9}} gIoApicConfigGuid =
+{0x2873D0F1, 0x00F6, 0x40AB, {0xAC, 0x36, 0x9A, 0x68, 0xBA, 0x87, 0x3E,
+0x6C}} gPchDmiConfigGuid = {0xB3A61210, 0x1CD3, 0x4797, {0x8E, 0xE6,
+0xD3, 0x42, 0x9C, 0x4F, 0x17, 0xBD}} gSerialIoConfigGuid =
+{0x6CC06EBF, 0x0D34, 0x4340, {0xBC, 0x16, 0xDA, 0x09, 0xE5, 0x78, 0x3A,
+0xDB}}
+
+##
+## SecurityPkg
+##
+## GUID used to "Tcg2PhysicalPresence" variable and "Tcg2PhysicalPresenceFlags" variable for TPM2 request and response.
+# Include/Guid/Tcg2PhysicalPresenceData.h
+gEfiTcg2PhysicalPresenceGuid = { 0xaeb9c5c1, 0x94f1, 0x4d02, { 0xbf, 0xd9, 0x46, 0x2, 0xdb, 0x2d, 0x3c, 0x54 }}
+
+##
+## FSP
+##
+gFspSiliconFvGuid = { 0x1b5c27fe, 0xf01c, 0x4fbc, { 0xae, 0xae, 0x34, 0x1b, 0x2e, 0x99, 0x2a, 0x17 }}
+gFspTscFrequencyGuid = { 0x0e3b622a, 0xedbb, 0x4e30, { 0x93, 0x60, 0x69, 0x5c, 0xd4, 0xb3, 0x20, 0xc9 }}
+gFspInfoGuid = { 0x067e0f25, 0x374f, 0x47c2, { 0x17, 0x92, 0x86, 0xdc, 0xdb, 0xc4, 0x8a, 0xc9 }}
+
+[Protocols]
+##
+## MdeModulePkg
+##
+gEdkiiSmmExitBootServicesProtocolGuid = { 0x296eb418, 0xc4c8, 0x4e05, {
+0xab, 0x59, 0x39, 0xe8, 0xaf, 0x56, 0xf0, 0xa } }
+
+##
+## SystemAgent
+##
+gIgdOpRegionProtocolGuid = {0x9e67aecf, 0x4fbb, 0x4c84, {0x99, 0xa5, 0x10, 0x73, 0x40, 0x7, 0x6d, 0xb4}}
+gSaPolicyProtocolGuid = {0xc6aa1f27, 0x5597, 0x4802, {0x9f, 0x63, 0xd6, 0x28, 0x36, 0x59, 0x86, 0x35}}
+gGopPolicyProtocolGuid = {0xec2e931b, 0x3281, 0x48a5, {0x81, 0x07, 0xdf, 0x8a, 0x8b, 0xed, 0x3c, 0x5d}}
+
+##
+## PCH
+##
+gPchSpiProtocolGuid = { 0xc7d289, 0x1347, 0x4de0, {0xbf, 0x42, 0xe, 0x26, 0x9d, 0xe, 0xf3, 0x4a}}
+gWdtProtocolGuid = {0xb42b8d12, 0x2acb, 0x499a, {0xa9, 0x20, 0xdd, 0x5b, 0xe6, 0xcf, 0x09, 0xb1}}
+gEfiSmmSmbusProtocolGuid = {0x72e40094, 0x2ee1, 0x497a, {0x8f, 0x33, 0x4c, 0x93, 0x4a, 0x9e, 0x9c, 0x0c}}
+gPchSmmSpiProtocolGuid = {0x56521f06, 0xa62, 0x4822, {0x99, 0x63, 0xdf, 0x1, 0x9d, 0x72, 0xc7, 0xe1}}
+gPchSmmIoTrapControlGuid = {0x514d2afd, 0x2096, 0x4283, {0x9d, 0xa6, 0x70, 0x0c, 0xd2, 0x7d, 0xc7, 0xa5}}
+gPchTcoSmiDispatchProtocolGuid = {0x9e71d609, 0x6d24, 0x47fd, {0xb5, 0x72, 0x61, 0x40, 0xf8, 0xd9, 0xc2, 0xa4}}
+gPchPcieSmiDispatchProtocolGuid = {0x3e7d2b56, 0x3f47, 0x42aa, {0x8f, 0x6b, 0x22, 0xf5, 0x19, 0x81, 0x8d, 0xab}}
+gPchAcpiSmiDispatchProtocolGuid = {0xd52bb262, 0xf022, 0x49ec, {0x86, 0xd2, 0x7a, 0x29, 0x3a, 0x7a, 0x05, 0x4b}}
+gPchSmiDispatchProtocolGuid = {0xE6A81BBF, 0x873D, 0x47FD, {0xB6, 0xBE, 0x61, 0xB3, 0xE5, 0x72, 0x09, 0x93}}
+gPchEspiSmiDispatchProtocolGuid = {0xB3C14FF3, 0xBAE8, 0x456C, {0x86, 0x31, 0x27, 0xFE, 0x0C, 0xEB, 0x34, 0x0C}}
+gPchSmmPeriodicTimerControlGuid = {0x6906E93B, 0x603B, 0x4A0F, {0x86, 0x92, 0x83, 0x20, 0x04, 0xAA, 0xF2, 0xDB}}
+##
+## Silicon Policy
+##
+## Include/Protocol/SiPolicyProtocol.h
+gDxeSiPolicyProtocolGuid = { 0xeca27516, 0x306c, 0x4e28, { 0x8c, 0x94,
+0x4e, 0x52, 0x10, 0x96, 0x69, 0x5e }}
+
+[Ppis.common.Private]
+
+[Ppis]
+##
+## MdeModulePkg
+##
+gEdkiiPlatformSpecificResetFilterPpiGuid = { 0x8c9f4de3, 0x7b90,
+0x47ef, { 0x93, 0x8, 0x28, 0x7c, 0xec, 0xd6, 0x6d, 0xe8 } }
+
+##
+## SecurityPkg
+##
+gPeiTpmInitializationDonePpiGuid = {0xa030d115, 0x54dd, 0x447b, { 0x90,
+0x64, 0xf2, 0x6, 0x88, 0x3d, 0x7c, 0xcc}} ## ## Common ## ##
+Include/Ppi/SiPolicy.h gSiPolicyPpiGuid = {0xaebffa01, 0x7edc,
+0x49ff, {0x8d, 0x88, 0xcb, 0x84, 0x8c, 0x5e, 0x86, 0x70}} ##
+Include/Ppi/SiPolicy.h gSiPreMemPolicyPpiGuid = {0xc133fe57, 0x17c7,
+0x4b09, {0x8b, 0x3c, 0x97, 0xc1, 0x89, 0xd0, 0xab, 0x8d}} ## Silicon
+Initialization PPI is used to export End of Silicon init.
+gEndOfSiInitPpiGuid = {0xE2E3D5D1, 0x8356, 0x4F96, {0x9C, 0x9E, 0x2E, 0xC3, 0x48, 0x1D, 0xEA, 0x88}}
+gEfiEndOfPeiSignal2PpiGuid = {0x22918381, 0xd018, 0x4d7c, {0x9d, 0x62, 0xf5, 0xa5, 0x70, 0x1c, 0x66, 0x80}}
+gFspTempRamExitPpiGuid = {0xbc1cfbdb, 0x7e50, 0x42be, {0xb4, 0x87, 0x22, 0xe0, 0xa9, 0x0c, 0xb0, 0x52}}
+gFspmArchConfigPpiGuid = {0x824d5a3a, 0xaf92, 0x4c0c, {0x9f, 0x19, 0x19, 0x52, 0x6d, 0xca, 0x4a, 0xbb}}
+gSiPreMemDefaultPolicyInitPpiGuid = {0xfec36242, 0xf8d8, 0x4b43,
+{0x87, 0x94, 0x4f, 0x1f, 0x9f, 0x63, 0x8d, 0xdc}}
+gSiPreMemPolicyReadyPpiGuid = {0x85270bef, 0x6984, 0x4375, {0xa6, 0xea, 0xb5, 0xaa, 0x90, 0x6e, 0xdd, 0x4a}} gSiDefaultPolicyInitPpiGuid = {0xf69abf86, 0x4048, 0x44ef, { 0xa8, 0xef, 0x6c, 0x7f, 0x20, 0x4a, 0xc8, 0xda}}
+gSiPolicyReadyPpiGuid = {0xd570de8c, 0xb9c4, 0x4ffa, {0xad, 0xee, 0xa5, 0x82, 0x7c, 0xe3, 0x17, 0x79}}
+gPeiBeforeGraphicsDetectionPpiGuid = {0xa494060d, 0x98c5, 0x4948,
+{0x84, 0x57, 0x74, 0xd7, 0x1a, 0x3d, 0x0e, 0x85}}
+
+##
+## UEFI Variable Support (Override Until BP1.5) ##
+gEdkiiVariableStoragePpiGuid = { 0x90d915c5, 0xe4c1, 0x4da8, {0xa7,
+0x6f, 0x9, 0xe5, 0x78, 0x91, 0x65, 0x48}}
+gEdkiiVariableStorageSelectorPpiGuid = { 0x782546d1, 0x03ab, 0x41e4,
+{0xa0, 0x1d, 0x7a, 0x9b, 0x22, 0xba, 0x2e, 0x1e}}
+gReadOnlyVariablePreMemoryDescriptorPpiGuid = { 0xbe136fc9, 0xc277,
+0x4dd1, {0xbe, 0x42, 0xce, 0xf0, 0x9f, 0xf4, 0x3f, 0x55}}
+gEfiReadyToInstallEndOfPei2PpiGuid = {0xeef72924, 0x2db2, 0x4569, {
+0x86, 0x3f, 0xd4, 0x86, 0xae, 0x7a, 0xe4, 0x12}}
+
+##
+## SystemAgent
+##
+gEnablePeiGraphicsPpiGuid = {0x8e3bb474, 0x545, 0x4902, {0x86, 0xb0,
+0x6c, 0xb5, 0xe2, 0x64, 0xb4, 0xa5}}
+gPeiGraphicsFramebufferReadyPpiGuid = {0x590ad868, 0xb0b1, 0x4d20,
+{0x91, 0xff, 0xc2, 0xa9, 0xd6, 0x88, 0x81, 0x94}}
+gPeiGraphicsPlatformPpiGuid = {0x4eabcd09, 0x43d3, 0x4b4d, {0xb7, 0x3d, 0x43, 0xc8, 0xd9, 0x89, 0x99, 0x05}} ## X Compatibility support PPI gCompatibleMemoryInitPpiGuid = {0xca311f82, 0xf490, 0x4b12, {0x9e, 0xe1, 0x2b, 0x66, 0xa3, 0x6c, 0x3e, 0xa}}
+gVmdInitDonePpiGuid = {0x42a187c8, 0xca0a, 0x4750, {0x82, 0xfd, 0xc9, 0xa0, 0xd5, 0x9, 0xfe, 0xd1}}
+
+##
+## Cpu
+##
+gPeiCachePpiGuid = {0xC153205A, 0xE898, 0x4C24, {0x86, 0x89, 0xA4,
+0xB4, 0xBC, 0xC5, 0xC8, 0xA2}} gPeiTxtMemoryUnlockedPpiGuid =
+{0x38cdd10b, 0x767d, 0x4f6e, {0xa7, 0x44, 0x67, 0xee, 0x1d, 0xfe, 0x2f,
+0xa5}} gPeiTxtReadyToRunMemoryInitPpiGuid = {0x9ecafd30, 0x29e2,
+0x42f6, {0xba, 0xf3, 0x8b, 0x7d, 0xb8, 0xfe, 0x1f, 0x22}}
+gPeiReadyToInstallMpPpiGuid = { 0x1a266768, 0xfd43, 0x4e18, { 0xa8,
+0x8a, 0x35, 0xc7, 0x94, 0xc3, 0x91, 0x0e }}
+
+##
+## PCH
+##
+gWdtPpiGuid = {0xf38d1338, 0xaf7a, 0x4fb6, {0x91, 0xdb, 0x1a, 0x9c,
+0x21, 0x83, 0x57, 0x0d}} gPchSpiPpiGuid = {0xdade7ce3, 0x6971,
+0x4b75, {0x82, 0x5e, 0xe, 0xe0, 0xeb, 0x17, 0x72, 0x2d}}
+gPeiSmbusPolicyPpiGuid = {0x63b6e435, 0x32bc, 0x49c6, {0x81, 0xbd,
+0xb7, 0xa1, 0xa0, 0xfe, 0x1a, 0x6c}} gPchIoExpanderInfoPpiGuid = {
+0xf4a29776, 0x0ff9, 0x4b5c, { 0xb6, 0x9d, 0x88, 0x45, 0x09, 0x9b, 0x8d,
+0xa5 }}
+
+##
+## TCSS
+##
+gTcssPeiInitDonePpiGuid = {0x5ad291b8, 0xace4, 0x416a, {0xb7, 0x50,
+0x7, 0x63, 0x59, 0xfc, 0xc1, 0x5b}}
+
+##
+## ExtendedBiosDecodeReady PPI
+##
+gExtendedBiosDecodeReadyPpiGuid = {0x54b522bc, 0xbef2, 0x419b, {0xa9,
+0x66, 0x7e, 0xc4, 0xf0, 0x15, 0xe8, 0x21}}
+
+##
+## FSP##
+gFsptUpdLocationPpiGuid = { 0xfc4dd4f2, 0x179e, 0x41f8, { 0x9d, 0x6d, 0xfa, 0xd6, 0xf9, 0xd7, 0xb8, 0xb9 }}
+
+[LibraryClasses]
+## @libraryclass
+## Common
+##
+SiPolicyLib|Include/Library/SiPolicyLib.h
+PeiPolicyUpdateLib|Include/Library/PeiSiPolicyUpdateLib.h
+ProcessorTraceMemoryAllocationLib|Include/Library/ProcessorTraceMemoryA
+ProcessorTraceMemoryAllocationLib|llocationLib.h
+PlatformSecLib|Include/Library/SecPlatformLib.h
+SiAssertErrorHandlerLib|Include/Library/SiAssertErrorHandlerLib.h
+SiConfigBlockLib|Include/Library/SiConfigBlockLib.h
+## @libraryclass
+## SampleCode
+##
+## CPU
+##
+CpuPlatformLib|Cpu/Include/Library/CpuPlatformLib.h
+
+
+## @libraryclass
+## Pch
+##
+GpioLib|Include/Library/GpioLib.h
+GpioLib|Include/Library/GpioNativeLib.h
+PchCycleDecodingLib|Pch/Include/Library/PchCycleDecodingLib.h
+EspiLib|Include/Library/EspiLib.h
+PchInfoLib|Pch/Include/Library/PchInfoLib.h
+PchPcieRpLib|Include/Library/PchPcieRpLib.h
+PchPcrLib|Include/Library/PchPcrLib.h
+PchSbiAccessLib|IpBlock/P2sb/IncludePrivate/Library/PchSbiAccessLib.h
+PchPciBdfLib|Pch/Include/Library/PchPciBdfLib.h
+PchRasLib|Pch/Include/Library/PchRasLib.h
+PchRtcLib|Pch/Include/Library/PchRtcLib.h
+ResetSystemLib|Include/Library/ResetSystemLib.h
+## @libraryclass
+## Sa
+##
+DxeSaPolicyLib|SystemAgent/Include/Library/DxeSaPolicyLib.h
+## @libraryclass
+## Fru
+##
+CpuInfoFruLib|Cpu/IncludePrivate/Library/CpuInfoFruLib.h
+## @libraryclass
+## IpBlock
+##
+PmcPrivateLib|IpBlock/Pmc/IncludePrivate/Library/PmcPrivateLib.h
+IehInitLib|IpBlock/Ieh/IncludePrivate/Library/PeiIehInitLib.h
+PeiIehPolicyLib|IpBlock/Ieh/IncludePrivate/Library/PeiIehPolicyLib.h
+DxeGraphicsPolicyLib|IpBlock/Graphics/IncludePrivate/Library/DxeGraphic
+DxeGraphicsPolicyLib|sPolicyLib.h
+DxeIgdOpRegionInitLib|IpBlock/Graphics/IncludePrivate/Library/DxeIgdOpR
+DxeIgdOpRegionInitLib|egionInitLib.h
+PchDmiLib|IpBlock/PchDmi/IncludePrivate/Library/PchDmiLib.h
+P2SbSidebandAccessLib|IpBlock/P2sb/IncludePrivate/Library/P2SbSidebandA
+P2SbSidebandAccessLib|ccessLib.h
+SpiCommonLib|IpBlock/Spi/IncludePrivate/Library/SpiCommonLib.h
+GpioHelpersLib|IpBlock/Gpio/IncludePrivate/Library/GpioHelpersLib.h
+GpioPrivateLib|IpBlock/Gpio/IncludePrivate/Library/GpioPrivateLib.h
+PeiDmiSipInitLib|IpBlock/PcieRp/IncludePrivate/Library/PeiDmiSipInitLib
+PeiDmiSipInitLib|.h
+PeiEnterprisePcieRpInitLib|IpBlock/PcieRp/IncludePrivate/Library/PeiEnt
+PeiEnterprisePcieRpInitLib|erprisePcieRpInitLib.h
+PeiDpInInitLib|IpBlock/Tcss/IncludePrivate/Library/PeiDpInInitLib.h
+CpuPcieRpLib|IpBlock/CpuPcieRp/Include/Library/CpuPcieRpLib.h
+GpioGsxLib|Include/Library/GpioGsxLib.h
+GraphicsInfoLib|Include/Library/GraphicsInfoLib.h
+HeciCommonLib|Include/Library/HeciCommonLib.h
+HeciConfigureLib|Include/Library/HeciConfigureLib.h
+HeciTraceLib|Include/Library/HeciTraceLib.h
+HeciTransportCoreLib|Include/Library/HeciTransportCoreLib.h
+OcPlatformLib|Include/Library/OcPlatformLib.h
+PeiSpsPreMemPolicyLib|Include/Library/PeiSpsPreMemPolicyLib.h
+PmcLib|Include/Library/PmcLib.h
+PmcSsramLib|Include/Library/PmcSsramLib.h
+SpiLib|Include/Library/SpiLib.h
+SpsDxeLib|Include/Library/SpsDxeLib.h
+SpsGetDxeConfigBlockLib|Include/Library/SpsGetDxeConfigBlock.h
+MeGetPeiConfigBlock|Include/Library/MeGetConfigBlock.h
+## @libraryclass
+## Fsp
+##
+FspHelperLib|Fsp/Include/Library/FspHelperLib.h
+FspInfoLib|Fsp/Include/Library/FspInfoLib.h
+FspSerialIoUartDebugHelperLib|Fsp/Include/Library/FspSerialIoUartDebugH
+FspSerialIoUartDebugHelperLib|elperLib.h
+
+
+CpuPcieInfoFruLib|Fru/AdlCpu/Include/Library/CpuPcieInfoFruLib.h
+
+[PcdsFixedAtBuild]
+## From MdeModulePkg.dec
+## Progress Code for S3 Suspend start.
+## PROGRESS_CODE_S3_SUSPEND_START = (EFI_SOFTWARE_SMM_DRIVER | (EFI_OEM_SPECIFIC | 0x00000000)) = 0x03078000
+gSiPkgTokenSpaceGuid.PcdProgressCodeS3SuspendStart|0x03078000|UINT32|0x
+30001032
+## Progress Code for S3 Suspend end.
+## PROGRESS_CODE_S3_SUSPEND_END = (EFI_SOFTWARE_SMM_DRIVER | (EFI_OEM_SPECIFIC | 0x00000001)) = 0x03078001
+gSiPkgTokenSpaceGuid.PcdProgressCodeS3SuspendEnd|0x03078001|UINT32|0x30
+001033
+##
+## PcdNemCodeCacheBase is usally the same as PEI FV Base address, ##
+FLASH_BASE+FLASH_REGION_FV_RECOVERY_OFFSET from PlatformPkg.fdf.
+##
+## Restriction:
+## 1) PcdNemCodeCacheBase - (PcdTemporaryRamBase + PcdTemporaryRamSize)
+>= 4K ## 2) PcdTemporaryRamBase >= 4G - 64M ##
+gSiPkgTokenSpaceGuid.PcdNemCodeCacheBase|0xFFF80000|UINT32|0x20000009
+##
+## NemCodeCacheSize is usally the same as PEI FV Size, ##
+FLASH_REGION_FV_RECOVERY_SIZE from PlatformPkg.fdf.
+##
+## Restriction:
+## 1) PcdNemTotalCacheSize = NemCodeCacheSize + PcdTemporaryRamSize ##
+<= Maximun CPU NEM total size (Code + Data) ## = LLC size - 0.5M ## 2)
+PcdTemporaryRamSize <= Maximum CPU NEM data size ## = MLC size ##
+NOTE: The size restriction may be changed in next generation processor.
+## Please refer to Processor BWG for detail.
+##
+gSiPkgTokenSpaceGuid.PcdBiosAreaBaseAddress|0xFF800000|UINT32|0x1000000
+1
+gSiPkgTokenSpaceGuid.PcdBiosSize|0x00800000|UINT32|0x10000002
+gSiPkgTokenSpaceGuid.PcdTemporaryRamBase|0xfef00000|UINT32|0x00010028
+gSiPkgTokenSpaceGuid.PcdTemporaryRamSize|0x2000|UINT32|0x00010029
+gSiPkgTokenSpaceGuid.PcdTopMemoryCacheSize|0x0|UINT32|0x0001002A
+gSiPkgTokenSpaceGuid.PcdFlashMicrocodeOffset|0x00000060|UINT32|0x300000
+13
+
+gSiPkgTokenSpaceGuid.PcdFspWrapperEnable |FALSE|BOOLEAN|0x3000000F
+
+
+#
+# PCD is using for SOC core boot
+#
+
+#
+# PCD is using for AlderLakeL P/M/S
+# True: ADL-P/M
+# False: ADL-S
+#
+gSiPkgTokenSpaceGuid.PcdAdlLpSupport|TRUE|BOOLEAN|0x30000014
+
+#
+# PCD is using for AlderLakeL S
+#
+gSiPkgTokenSpaceGuid.PcdAdlSSupport|FALSE|BOOLEAN|0x30000015
+
+##
+## PcdEfiGcdAllocateType is using for EFI_GCD_ALLOCATE_TYPE selection
+## value of the struct ## 0x00 EfiGcdAllocateAnySearchBottomUp ##
+0x01 EfiGcdAllocateMaxAddressSearchBottomUp
+## 0x03 EfiGcdAllocateAnySearchTopDown ## 0x04
+EfiGcdAllocateMaxAddressSearchTopDown
+##
+## below value should not using in this situation ## 0x05
+EfiGcdMaxAllocateType : design for max value of struct ## 0x02
+EfiGcdAllocateAddress : design for speccification address allocate ##
+gSiPkgTokenSpaceGuid.PcdEfiGcdAllocateType|0x01|UINT8|0x40000000
+
+
+##
+## Those PCDs are used to control build process.
+##
+gSiPkgTokenSpaceGuid.PcdSmmVariableEnable |TRUE |BOOLEAN|0xF0000002
+gSiPkgTokenSpaceGuid.PcdAcpiEnable |TRUE |BOOLEAN|0xF0000009
+gSiPkgTokenSpaceGuid.PcdSourceDebugEnable |FALSE|BOOLEAN|0xF000000B
+gSiPkgTokenSpaceGuid.PcdTxtEnable |FALSE|BOOLEAN|0xF000000D
+
+gSiPkgTokenSpaceGuid.PcdSmbiosEnable |TRUE |BOOLEAN|0xF0000014
+gSiPkgTokenSpaceGuid.PcdIgdEnable |TRUE |BOOLEAN|0xF000001A
+gSiPkgTokenSpaceGuid.PcdSaDmiEnable |TRUE |BOOLEAN|0xF000001C
+gSiPkgTokenSpaceGuid.PcdBdatEnable |TRUE |BOOLEAN|0xF0000023
+gSiPkgTokenSpaceGuid.PcdOptimizeCompilerEnable |TRUE |BOOLEAN|0xF0000024
+gSiPkgTokenSpaceGuid.PcdPeiDisplayEnable |TRUE |BOOLEAN|0xF0000025
+gSiPkgTokenSpaceGuid.PcdSerialIoUartEnable |TRUE |BOOLEAN|0xF0000033
+gSiPkgTokenSpaceGuid.PcdSiCatalogDebugEnable |FALSE|BOOLEAN|0xF0000037
+
+gSiPkgTokenSpaceGuid.PcdCpuPcieEnable |TRUE |BOOLEAN|0xF0000043
+gSiPkgTokenSpaceGuid.PcdMrcTraceMessageSupported |TRUE |BOOLEAN|0xF0000045
+
+[PcdsDynamic, PcdsPatchableInModule]
+## Default OEM Table ID for ACPI table creation, it is "EDK2 ".
+gSiPkgTokenSpaceGuid.PcdAcpiDefaultOemTableId|0x20202020324B4445|UINT64
+|0x30001035
+
+[PcdsFixedAtBuild, PcdsPatchableInModule] ## This value is used to set
+the base address of PCH devices
+gSiPkgTokenSpaceGuid.PcdSmbusBaseAddress|0x0000EFA0|UINT16|0x00010031
+gSiPkgTokenSpaceGuid.PcdTcoBaseAddress|0x0400|UINT16|0x00010033
+gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress|0x1800|UINT16|0x00010035
+
+##
+## FSP
+##
+## The PCD value here are either dummy or generic for all platforms ##
+Some of them are expected to have different value in platform FSP package DSC.
+##
+## Examples:
+## PcdFspImageIdString, PcdFspVersionRevision, PcdFspVersionBuild, PcdFspVersionMinor
+##
+gSiPkgTokenSpaceGuid.PcdFspImageIdString |0x0|UINT64|0x0001005A
+gSiPkgTokenSpaceGuid.PcdFspVersionRevision |0x00|UINT8|0x0001005C
+gSiPkgTokenSpaceGuid.PcdFspVersionBuild |0x00|UINT8|0x0001005D
+gSiPkgTokenSpaceGuid.PcdFspVersionMinor |0x00|UINT8|0x0001005E
+
+
+## This value is used to set the base address of MCH
+gSiPkgTokenSpaceGuid.PcdMchBaseAddress|0xFEDC0000|UINT64|0x00010030
+
+##
+## Allocate 56 KB [0x2000..0xFFFF] of I/O space for Pci Devices ## If
+PcdPciReservedMemLimit =0 Pci Reserved default MMIO Limit is 0xE0000000 else use PcdPciReservedMemLimit .
+##
+gSiPkgTokenSpaceGuid.PcdPciReservedMemLimit |0x0000 |UINT32|0x00010043
+
+##
+## Default 8MB TSEG for Release build BIOS when IED disabled (Also a
+default) ##
+gSiPkgTokenSpaceGuid.PcdTsegSize|0x00800000|UINT32|0x00010046
+
+##
+## Silicon Reference Code versions
+##
+gSiPkgTokenSpaceGuid.PcdSiliconInitVersionMajor |0x0C|UINT8|0x00010049
+
+##Minor:the program that supported by same core generation.
+gSiPkgTokenSpaceGuid.PcdSiliconInitVersionMinor |0x00|UINT8|0x00010050
+
+##Revision:Weekly build number
+gSiPkgTokenSpaceGuid.PcdSiliconInitVersionRevision|0x82|UINT8|0x0001005
+1
+
+##Build[7:4]:Daily build number.
+##Build[3:0]:Patch build number.
+
+gSiPkgTokenSpaceGuid.PcdSiliconInitVersionBuild |0x30|UINT8|0x00010052
+
+
+
+##
+## This PCD specifies the base address of the HPET timer.
+## The acceptable values are 0xFED00000, 0xFED01000, 0xFED02000, and
+0xFED03000 ##
+gSiPkgTokenSpaceGuid.PcdSiHpetBaseAddress |0xFED00000|UINT32|0x00010057
+##
+## This PCD specifies the base address of the IO APIC.
+## The acceptable values are 0xFECxx000.
+##
+gSiPkgTokenSpaceGuid.PcdSiIoApicBaseAddress
+|0xFEC00000|UINT32|0x00010058
+
+[PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx]
+## ## SerialIo Uart Configuration ##
+gSiPkgTokenSpaceGuid.PcdSerialIoUartDebugEnable |0 |UINT8 |0x00210001 # 0:Disable, 1:Enable and Initialize, 2:Enable without Initializing
+gSiPkgTokenSpaceGuid.PcdSerialIoUartNumber |2 |UINT8 |0x00210002
+gSiPkgTokenSpaceGuid.PcdSerialIoUartMode |2 |UINT8 |0x00210003 # 0:Disabled, 1:Enabled, 2:Hidden, 3:COM, 4:SkipInit
+gSiPkgTokenSpaceGuid.PcdSerialIoUartBaudRate |115200 |UINT32|0x00210004 # 0:Default, Max:6000000
+gSiPkgTokenSpaceGuid.PcdSerialIoUartParity |1 |UINT8 |0x00210008 # 0:DefaultParity, 1:NoParity, 2:EvenParity, 3:OddParity
+gSiPkgTokenSpaceGuid.PcdSerialIoUartDataBits |8 |UINT8 |0x00210009 # 0:Default, 5,6,7,8
+gSiPkgTokenSpaceGuid.PcdSerialIoUartStopBits |1 |UINT8 |0x0021000A # 0:DefaultStopBits, 1:OneStopBit, 2:OneFiveStopBits, 3:TwoStopBits
+gSiPkgTokenSpaceGuid.PcdSerialIoUartAutoFlow |0 |UINT8 |0x0021000B # 0:No HW flow control, Only RX/TX Enabled; 1:HW Flow Control On, Rts/Cts lines enabled;
+gSiPkgTokenSpaceGuid.PcdSerialIoUartRxPinMux |0x0 |UINT32|0x0021000C # Pin muxing config for UART Rx pin
+gSiPkgTokenSpaceGuid.PcdSerialIoUartTxPinMux |0x0 |UINT32|0x00210010 # Pin muxing config for UART Tx pin
+gSiPkgTokenSpaceGuid.PcdSerialIoUartRtsPinMux |0x0 |UINT32|0x00210014 # Pin muxing config for UART Rts pin
+gSiPkgTokenSpaceGuid.PcdSerialIoUartCtsPinMux |0x0 |UINT32|0x00210018 # Pin muxing config for UART Cts pin
+gSiPkgTokenSpaceGuid.PcdSerialIoUartDebugMmioBase |0xFE036000
+|UINT32|0x0021001C # PcdSerialIoUartMode = Enabled, need to assign MMIO
+Resource in SEC/PEI Phase
+
+gSiPkgTokenSpaceGuid.PcdLpcUartDebugEnable |0x1 |UINT8 |0x00210026 # 0:Disable, 1:Enable
+gSiPkgTokenSpaceGuid.PcdDebugInterfaceFlags |0x12 |UINT8 |0x00210027 # BIT0-RAM, BIT1-UART, BIT3-USB3, BIT4-Serial IO, BIT5-TraceHub, BIT2 - Not used.
+gSiPkgTokenSpaceGuid.PcdSerialDebugLevel |0x3 |UINT8 |0x00210028 # {0:Disable, 1:Error Only, 2:Error and Warnings, 3:Load Error Warnings and Info, 4:Load Error Warnings and Info, 5:Load Error Warnings Info and Verbose
+gSiPkgTokenSpaceGuid.PcdIsaSerialUartBase |0x0 |UINT8 |0x00210029 # 0:0x3F8, 1:0x2F8
+
+
+##
+## SerialIo 2nd Uart Configuration
+##
+gSiPkgTokenSpaceGuid.PcdSerialIo2ndUartEnable |0 |UINT8 |0x0021002A # 0:Disable, 1:Enable and Initialize, 2:Enable without Initializing
+gSiPkgTokenSpaceGuid.PcdSerialIo2ndUartNumber |2 |UINT8 |0x0021002B
+gSiPkgTokenSpaceGuid.PcdSerialIo2ndUartMode |2 |UINT8 |0x0021002C # 0:Disabled, 1:Enabled, 2:Hidden, 3:COM, 4:SkipInit
+gSiPkgTokenSpaceGuid.PcdSerialIo2ndUartBaudRate |115200 |UINT32|0x0021002D # 0:Default, Max:6000000
+gSiPkgTokenSpaceGuid.PcdSerialIo2ndUartParity |1 |UINT8 |0x00210031 # 0:DefaultParity, 1:NoParity, 2:EvenParity, 3:OddParity
+gSiPkgTokenSpaceGuid.PcdSerialIo2ndUartDataBits |8 |UINT8 |0x00210032 # 0:Default, 5,6,7,8
+gSiPkgTokenSpaceGuid.PcdSerialIo2ndUartStopBits |1 |UINT8 |0x00210033 # 0:DefaultStopBits, 1:OneStopBit, 2:OneFiveStopBits, 3:TwoStopBits
+gSiPkgTokenSpaceGuid.PcdSerialIo2ndUartAutoFlow |0 |UINT8 |0x00210034 # 0:No HW flow control, Only RX/TX Enabled; 1:HW Flow Control On, Rts/Cts lines enabled;
+gSiPkgTokenSpaceGuid.PcdSerialIo2ndUartRxPinMux |0x0 |UINT32|0x00210035 # Pin muxing config for UART Rx pin
+gSiPkgTokenSpaceGuid.PcdSerialIo2ndUartTxPinMux |0x0 |UINT32|0x00210039 # Pin muxing config for UART Tx pin
+gSiPkgTokenSpaceGuid.PcdSerialIo2ndUartRtsPinMux |0x0 |UINT32|0x0021003D # Pin muxing config for UART Rts pin
+gSiPkgTokenSpaceGuid.PcdSerialIo2ndUartCtsPinMux |0x0 |UINT32|0x00210041 # Pin muxing config for UART Cts pin
+gSiPkgTokenSpaceGuid.PcdSerialIo2ndUartMmioBase |0xFE034000
+|UINT32|0x00210045 # PcdSerialIoUartMode = Enabled, need to assign MMIO
+Resource in SEC/PEI Phase
+
+##
+## PCI Express MMIO region length
+## Valid settings: 0x20000000/512MB, 0x10000000/256MB, 0x8000000/128MB,
+0x4000000/64MB ##
+gSiPkgTokenSpaceGuid.PcdPciExpressRegionLength|0x10000000|UINT32|0x0020
+0001
+##
+## Typically this should be the same with gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress.
+## This PCD is added for supporting different PCD type in different phases.
+##
+gSiPkgTokenSpaceGuid.PcdSiPciExpressBaseAddress
+|0xC0000000|UINT64|0x00200002 ## ## PCI Express MMIO temporary region
+length in SEC phase.
+## Valid settings: 0x20000000/512MB, 0x10000000/256MB, 0x8000000/128MB,
+0x4000000/64MB ##
+gSiPkgTokenSpaceGuid.PcdTemporaryPciExpressRegionLength|0x10000000|UINT
+32|0x00200005
--
2.36.1.windows.1
-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#108746): https://edk2.groups.io/g/devel/message/108746
Mute This Topic: https://groups.io/mt/101373955/7686176
Group Owner: devel+owner@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [rebecca@openfw.io]
-=-=-=-=-=-=-=-=-=-=-=-
^ permalink raw reply related [flat|nested] 41+ messages in thread
* Re: [edk2-devel] [PATCH v2 01/10] AlderlakeSiliconPkg/IpBlock: Add CpuPcieRp, Espi, Gpio components
2023-09-15 4:45 [edk2-devel] [PATCH v2 01/10] AlderlakeSiliconPkg/IpBlock: Add CpuPcieRp, Espi, Gpio components Saloni Kasbekar
` (10 preceding siblings ...)
2023-09-15 23:56 ` Nate DeSimone
@ 2023-09-16 0:26 ` Nate DeSimone
11 siblings, 0 replies; 41+ messages in thread
From: Nate DeSimone @ 2023-09-16 0:26 UTC (permalink / raw)
To: Kasbekar, Saloni, devel@edk2.groups.io
Cc: Chaganty, Rangasai V, Chuang, Rosen
The series has been pushed as 9c77b37~..6382836
-----Original Message-----
From: Kasbekar, Saloni <saloni.kasbekar@intel.com>
Sent: Thursday, September 14, 2023 9:46 PM
To: devel@edk2.groups.io
Cc: Kasbekar, Saloni <saloni.kasbekar@intel.com>; Chaganty, Rangasai V <rangasai.v.chaganty@intel.com>; Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>; Chuang, Rosen <rosen.chuang@intel.com>
Subject: [PATCH v2 01/10] AlderlakeSiliconPkg/IpBlock: Add CpuPcieRp, Espi, Gpio components
Adds the following modules:
- IpBlock/CpuPcieRp/Include
- IpBlock/Espi/Library
- IpBlock/Gpio/IncludePrivate
- IpBlock/Gpio/Library
- IpBlock/Gpio/LibraryPrivate
Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Rosen Chuang <rosen.chuang@intel.com>
Signed-off-by: Saloni Kasbekar <saloni.kasbekar@intel.com>
---
.../IpBlock/CpuPcieRp/Include/CpuPcieInfo.h | 25 +
.../Espi/Library/PeiDxeSmmEspiLib/EspiLib.c | 58 ++
.../PeiDxeSmmEspiLib/PeiDxeSmmEspiLib.inf | 38 ++
.../IncludePrivate/Library/GpioHelpersLib.h | 50 ++
.../IncludePrivate/Library/GpioNativePads.h | 245 ++++++++
.../IncludePrivate/Library/GpioPrivateLib.h | 350 +++++++++++
.../Gpio/Library/PeiDxeSmmGpioLib/GpioInit.c | 546 ++++++++++++++++++
.../Gpio/Library/PeiDxeSmmGpioLib/GpioLib.c | 522 +++++++++++++++++
.../Library/PeiDxeSmmGpioLib/GpioLibrary.h | 29 +
.../Library/PeiDxeSmmGpioLib/GpioNativeLib.c | 177 ++++++
.../PeiDxeSmmGpioLib/PeiDxeSmmGpioLib.inf | 44 ++
.../BaseGpioHelpersLibNull.c | 51 ++
.../BaseGpioHelpersLibNull.inf | 25 +
.../GpioNativePrivateLibInternal.h | 48 ++
.../PeiDxeSmmGpioPrivateLib/GpioPrivateLib.c | 267 +++++++++
.../GpioPrivateLibPch.c | 172 ++++++
.../GpioPrivateLibVer2.c | 81 +++
.../PeiDxeSmmGpioPrivateLibVer2.inf | 40 ++
.../PeiGpioHelpersLib/PeiGpioHelpersLib.c | 218 +++++++
.../PeiGpioHelpersLib/PeiGpioHelpersLib.inf | 46 ++
20 files changed, 3032 insertions(+)
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/CpuPcieRp/Include/CpuPcieInfo.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Espi/Library/PeiDxeSmmEspiLib/EspiLib.c
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Espi/Library/PeiDxeSmmEspiLib/PeiDxeSmmEspiLib.inf
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/IncludePrivate/Library/GpioHelpersLib.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/IncludePrivate/Library/GpioNativePads.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/IncludePrivate/Library/GpioPrivateLib.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/Library/PeiDxeSmmGpioLib/GpioInit.c
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/Library/PeiDxeSmmGpioLib/GpioLib.c
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/Library/PeiDxeSmmGpioLib/GpioLibrary.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/Library/PeiDxeSmmGpioLib/GpioNativeLib.c
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/Library/PeiDxeSmmGpioLib/PeiDxeSmmGpioLib.inf
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/BaseGpioHelpersLibNull/BaseGpioHelpersLibNull.c
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/BaseGpioHelpersLibNull/BaseGpioHelpersLibNull.inf
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiDxeSmmGpioPrivateLib/GpioNativePrivateLibInternal.h
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiDxeSmmGpioPrivateLib/GpioPrivateLib.c
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiDxeSmmGpioPrivateLib/GpioPrivateLibPch.c
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiDxeSmmGpioPrivateLib/GpioPrivateLibVer2.c
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiDxeSmmGpioPrivateLib/PeiDxeSmmGpioPrivateLibVer2.inf
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiGpioHelpersLib/PeiGpioHelpersLib.c
create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiGpioHelpersLib/PeiGpioHelpersLib.inf
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/CpuPcieRp/Include/CpuPcieInfo.h b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/CpuPcieRp/Include/CpuPcieInfo.h
new file mode 100644
index 0000000000..a6f8b16d10
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/CpuPcieRp/Include/CpuPcieInfo.h
@@ -0,0 +1,25 @@
+/** @file
+ This file contains definitions of PCIe controller information
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _CPU_PCIE_INFO_H_
+#define _CPU_PCIE_INFO_H_
+
+#define PCIE_HWEQ_COEFFS_MAX 5
+
+
+//
+// SA PCI Express* Port configuration
+//
+
+#define CPU_PCIE_MAX_ROOT_PORTS 4
+#define CPU_PCIE_MAX_CONTROLLERS 3
+
+#define SA_PEG_MAX_FUN 0x04
+#define SA_PEG_MAX_LANE 0x14
+
+
+
+#endif
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Espi/Library/PeiDxeSmmEspiLib/EspiLib.c b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Espi/Library/PeiDxeSmmEspiLib/EspiLib.c
new file mode 100644
index 0000000000..2e4d1375ca
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Espi/Library/PeiDxeSmmEspiLib/EspiLib.c
@@ -0,0 +1,58 @@
+/** @file
+ This file contains routines for eSPI
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#include <Base.h>
+#include <Uefi/UefiBaseType.h>
+#include <Library/IoLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/EspiLib.h>
+#include <Library/PchPcrLib.h>
+#include <Library/PchInfoLib.h>
+#include <Library/TimerLib.h>
+#include <PchLimits.h>
+#include <Register/PchPcrRegs.h>
+#include <Register/PchRegsLpc.h>
+
+
+/**
+ Checks if second device capability is enabled
+
+ @retval TRUE There's second device
+ @retval FALSE There's no second device
+**/
+BOOLEAN
+IsEspiSecondSlaveSupported (
+ VOID
+ )
+{
+ return ((PchPcrRead32 (PID_ESPISPI, R_ESPI_PCR_SOFTSTRAPS) & B_ESPI_PCR_SOFTSTRAPS_CS1_EN) != 0);
+}
+
+
+/**
+ Is eSPI enabled in strap.
+
+ @retval TRUE Espi is enabled in strap
+ @retval FALSE Espi is disabled in strap
+**/
+BOOLEAN
+IsEspiEnabled (
+ VOID
+ )
+{
+ return (PchPcrRead32 (PID_ESPISPI, R_ESPI_PCR_CFG_VAL) & B_ESPI_PCR_CFG_VAL_ESPI_EN) != 0;
+}
+
+typedef enum {
+ EspiSlaveOperationConfigRead,
+ EspiSlaveOperationConfigWrite,
+ EspiSlaveOperationStatusRead,
+ EspiSlaveOperationInBandReset
+} ESPI_SLAVE_OPERATION;
+
+
+
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Espi/Library/PeiDxeSmmEspiLib/PeiDxeSmmEspiLib.inf b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Espi/Library/PeiDxeSmmEspiLib/PeiDxeSmmEspiLib.inf
new file mode 100644
index 0000000000..e8db1e4e8d
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Espi/Library/PeiDxeSmmEspiLib/PeiDxeSmmEspiLib.inf
@@ -0,0 +1,38 @@
+## @file
+# Component description file for the PeiDxeSmmPchEspiLib
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+
+[Defines]
+INF_VERSION = 0x00010017
+BASE_NAME = PeiDxeSmmEspiLib
+FILE_GUID = 7F25F990-7989-4413-B414-1EDE557E9389
+VERSION_STRING = 1.0
+MODULE_TYPE = BASE
+LIBRARY_CLASS = EspiLib
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = IA32 X64 IPF EBC
+#
+
+
+
+[LibraryClasses]
+BaseLib
+IoLib
+DebugLib
+PchPcrLib
+TimerLib
+
+
+[Packages]
+MdePkg/MdePkg.dec
+AlderlakeSiliconPkg/SiPkg.dec
+
+
+[Sources]
+EspiLib.c
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/IncludePrivate/Library/GpioHelpersLib.h b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/IncludePrivate/Library/GpioHelpersLib.h
new file mode 100644
index 0000000000..cf67c81ed0
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/IncludePrivate/Library/GpioHelpersLib.h
@@ -0,0 +1,50 @@
+/** @file
+ Header file for GPIO Helpers Lib implementation.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _GPIO_HELPERS_LIB_H_
+#define _GPIO_HELPERS_LIB_H_
+
+#include <Library/GpioConfig.h>
+
+/**
+ This procedure stores GPIO group data about pads which PadConfig needs to be unlocked.
+
+ @param[in] GroupIndex GPIO group index
+ @param[in] DwNum DWORD index for a group.
+ For group which has less then 32 pads per group DwNum must be 0.
+ @param[in] PadsToLock DWORD bitmask for pads which are going to be left unlocked
+ Bit position - PadNumber
+ Bit value - 0: Skip, 1: Leave unlocked
+
+ @retval Status
+**/
+EFI_STATUS
+GpioStoreGroupDwUnlockPadConfigData (
+ IN UINT32 GroupIndex,
+ IN UINT32 DwNum,
+ IN UINT32 UnlockedPads
+ );
+
+/**
+ This procedure stores GPIO group data about pads which Output state needs to be unlocked.
+
+ @param[in] GroupIndex GPIO group index
+ @param[in] DwNum DWORD index for a group.
+ For group which has less then 32 pads per group DwNum must be 0.
+ @param[in] PadsToLock DWORD bitmask for pads which are going to be left unlocked
+ Bit position - PadNumber
+ Bit value - 0: Skip, 1: Leave unlocked
+
+ @retval Status
+**/
+EFI_STATUS
+GpioStoreGroupDwUnlockOutputData (
+ IN UINT32 GroupIndex,
+ IN UINT32 DwNum,
+ IN UINT32 UnlockedPads
+ );
+
+#endif // _GPIO_HELPERS_LIB_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/IncludePrivate/Library/GpioNativePads.h b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/IncludePrivate/Library/GpioNativePads.h
new file mode 100644
index 0000000000..dbd13963fa
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/IncludePrivate/Library/GpioNativePads.h
@@ -0,0 +1,245 @@
+/** @file
+ Header file for GPIO Native pads support
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _GPIO_NATIVE_PADS_H_
+#define _GPIO_NATIVE_PADS_H_
+
+//
+// GpioPad can contain additional information used to provide data on
+// native functions. Please refer to description of GPIO_NATIVE_PAD
+//
+// FFFF CCCC TTTG GGGG TTTT TTTP PPPP PPPP
+//
+// F - 2^4 = 16, native function number
+// C - 2^4 = 16, chipset ID
+// T - 2^10 = 1024 , abstract type representing native mode of a pad (e.g. SERIALIO_UART2_TX)
+// G - 2^5 = 32, group
+// P - 2^9 = 512, pad number
+//
+// F & T contain additional optional settings used for native pads
+//
+#define GPIO_NATIVE_PAD_DEF(GpioNativePad, NativeMode, NativeFunction) \
+ (GpioNativePad | (NativeMode << 28) | ((NativeFunction & 0x7F) << 9) | ((NativeFunction & 0x380) << 14))
+
+#define GPIO_NATIVE_GET_FUNCTION(GpioNativePad) ((((GpioNativePad) & 0xFE00) >> 9) | (((GpioNativePad) & 0xE00000) >> 14))
+#define GPIO_NATIVE_GET_PAD_FN(GpioNativePad) (((GpioNativePad) >> 28) & 0xF)
+#define GPIO_NATIVE_GET_PAD_MODE(GpioNativePad) ((GPIO_NATIVE_GET_PAD_FN(GpioNativePad) << 1) | 1)
+#define GPIO_NATIVE_TO_GPIO_PAD(GpioNativePad) (GpioNativePad & 0xF1F01FF)
+
+//
+// Below defines and macros are used to build abstract type
+// to help encode native pin information in GPIO_PAD
+//
+
+//
+// Macro used to define GPIO native function.
+// <Min,Max> defines range that can be used to encode given native signal.
+// Numbering must be unique and cannot overlap.
+// If there are many instances of similar signal (e.g. per controller) the lower
+// word will store value for a given instance in the form: Min + Instance
+// Upper word (Max) is left untouched and later used for verification
+//
+#define GPIO_NATIVE_FUNCTION_DEF(Min, Max) (((Max) << 16) + (Min))
+#define GPIO_NATIVE_FUNCTION_GET_MAX(NativeFunction) (((NativeFunction) >> 16) & 0xFFFF)
+#define GPIO_NATIVE_FUNCTION_GET_VALUE(NativeFunction) ((NativeFunction) & 0xFFFF)
+
+//
+// Macro GPIO_NATIVE_FUNCTION_GET_SIGNAL is created as synonym to macro GPIO_NATIVE_FUNCTION_GET_MAX
+// GPIO_NATIVE_FUNCTION_GET_SIGNAL used with below defines is more descriptive and easier to read
+// ex.
+// - GPIO_NATIVE_FUNCTION_GET_SIGNAL(GPIO_SERIAL_IO_UART_RX)
+// - GPIO_NATIVE_FUNCTION_GET_SIGNAL(GPIO_ISH_GP)
+// - ...
+//
+#define GPIO_NATIVE_FUNCTION_GET_SIGNAL(NativeFunction) (GPIO_NATIVE_FUNCTION_GET_MAX(NativeFunction))
+
+//
+// GPIO native modes
+// Those defines are internal to this header.
+// GPIO_FUNCTION_<IP>_<signal>(index) defines should be used by other modules instead.
+//
+#define GPIO_SERIAL_IO_UART_RX GPIO_NATIVE_FUNCTION_DEF(1,8)
+#define GPIO_SERIAL_IO_UART_TX GPIO_NATIVE_FUNCTION_DEF(9,16)
+#define GPIO_SERIAL_IO_UART_RTS GPIO_NATIVE_FUNCTION_DEF(17,24)
+#define GPIO_SERIAL_IO_UART_CTS GPIO_NATIVE_FUNCTION_DEF(25,31)
+#define GPIO_SERIAL_IO_SPI_MOSI GPIO_NATIVE_FUNCTION_DEF(32,39)
+#define GPIO_SERIAL_IO_SPI_MISO GPIO_NATIVE_FUNCTION_DEF(40,47)
+#define GPIO_SERIAL_IO_SPI_CLK GPIO_NATIVE_FUNCTION_DEF(48,55)
+#define GPIO_SERIAL_IO_SPI_CS GPIO_NATIVE_FUNCTION_DEF(56,71)
+#define GPIO_ISH_GP GPIO_NATIVE_FUNCTION_DEF(80,143)
+#define GPIO_ISH_UART_RX GPIO_NATIVE_FUNCTION_DEF(144,151)
+#define GPIO_ISH_UART_TX GPIO_NATIVE_FUNCTION_DEF(152,159)
+#define GPIO_ISH_UART_RTS GPIO_NATIVE_FUNCTION_DEF(160,167)
+#define GPIO_ISH_UART_CTS GPIO_NATIVE_FUNCTION_DEF(168,175)
+#define GPIO_ISH_SPI_MOSI GPIO_NATIVE_FUNCTION_DEF(184,191)
+#define GPIO_ISH_SPI_MISO GPIO_NATIVE_FUNCTION_DEF(192,199)
+#define GPIO_ISH_SPI_CLK GPIO_NATIVE_FUNCTION_DEF(200,207)
+#define GPIO_ISH_SPI_CS GPIO_NATIVE_FUNCTION_DEF(208,223)
+#define GPIO_ISH_I2C_SCL GPIO_NATIVE_FUNCTION_DEF(232,239)
+#define GPIO_ISH_I2C_SDA GPIO_NATIVE_FUNCTION_DEF(240,247)
+#define GPIO_THC_SPI_INT GPIO_NATIVE_FUNCTION_DEF(248,251)
+#define GPIO_DMIC_DATA GPIO_NATIVE_FUNCTION_DEF(258,261)
+#define GPIO_DMIC_CLKA GPIO_NATIVE_FUNCTION_DEF(262,265)
+#define GPIO_DMIC_CLKB GPIO_NATIVE_FUNCTION_DEF(266,269)
+#define GPIO_DDSP_HPD0 GPIO_NATIVE_FUNCTION_DEF(270,285)
+#define GPIO_PANEL_AVDD_EN GPIO_NATIVE_FUNCTION_DEF(286,289)
+#define GPIO_PANEL_BKLTEN GPIO_NATIVE_FUNCTION_DEF(290,293)
+#define GPIO_PANEL_BKLTCTL GPIO_NATIVE_FUNCTION_DEF(294,297)
+#define GPIO_PANEL_RESET GPIO_NATIVE_FUNCTION_DEF(298,301)
+#define GPIO_PANEL_AVEE_EN GPIO_NATIVE_FUNCTION_DEF(302,305)
+#define GPIO_PANEL_VIO_EN GPIO_NATIVE_FUNCTION_DEF(306,309)
+#define GPIO_PANEL_HPD GPIO_NATIVE_FUNCTION_DEF(310,313)
+#define GPIO_PANEL_TE_EN GPIO_NATIVE_FUNCTION_DEF(314,317)
+#define GPIO_HDMI_GMBUS_SCL GPIO_NATIVE_FUNCTION_DEF(318,325)
+#define GPIO_HDMI_GMBUS_SDA GPIO_NATIVE_FUNCTION_DEF(326,333)
+#define GPIO_SERIAL_IO_I2C_SCL GPIO_NATIVE_FUNCTION_DEF(338,353)
+#define GPIO_SERIAL_IO_I2C_SDA GPIO_NATIVE_FUNCTION_DEF(354,369)
+#define GPIO_SD_DATA GPIO_NATIVE_FUNCTION_DEF(374,377)
+#define GPIO_EMMC_DATA GPIO_NATIVE_FUNCTION_DEF(384,391)
+#define GPIO_THC_CLK_LOOPBACK GPIO_NATIVE_FUNCTION_DEF(395,396)
+#define GPIO_MIPI_PANEL_RESET GPIO_NATIVE_FUNCTION_DEF(401,404)
+#define GPIO_MIPI_SEC_POW_EN_AVEE GPIO_NATIVE_FUNCTION_DEF(405,408)
+#define GPIO_MIPI_SEC_POW_EN_AVDD GPIO_NATIVE_FUNCTION_DEF(409,412)
+#define GPIO_THC_WOT GPIO_NATIVE_FUNCTION_DEF(413,414)
+#define GPIO_SATA_DEVSLP GPIO_NATIVE_FUNCTION_DEF(415,446)
+#define GPIO_PCIE_CLKREQ GPIO_NATIVE_FUNCTION_DEF(447,478)
+
+//
+// Serial IO UART
+//
+
+#define GPIO_FUNCTION_SERIAL_IO_UART_RX(UartDev) (GPIO_SERIAL_IO_UART_RX + ((UINT32)UartDev))
+#define GPIO_FUNCTION_SERIAL_IO_UART_TX(UartDev) (GPIO_SERIAL_IO_UART_TX + ((UINT32)UartDev))
+#define GPIO_FUNCTION_SERIAL_IO_UART_RTS(UartDev) (GPIO_SERIAL_IO_UART_RTS + ((UINT32)UartDev))
+#define GPIO_FUNCTION_SERIAL_IO_UART_CTS(UartDev) (GPIO_SERIAL_IO_UART_CTS + ((UINT32)UartDev))
+
+//
+// Serial IO SPI
+//
+#define GPIO_SERIAL_IO_SPI_RANGE 8 // Number of SerialIo SPIx controllers supported in GPIO_NATIVE_PAD encoding
+
+#define GPIO_FUNCTION_SERIAL_IO_SPI_MOSI(SpiDev) (GPIO_SERIAL_IO_SPI_MOSI + ((UINT32)SpiDev))
+#define GPIO_FUNCTION_SERIAL_IO_SPI_MISO(SpiDev) (GPIO_SERIAL_IO_SPI_MISO + ((UINT32)SpiDev))
+#define GPIO_FUNCTION_SERIAL_IO_SPI_CLK(SpiDev) (GPIO_SERIAL_IO_SPI_CLK + ((UINT32)SpiDev))
+#define GPIO_FUNCTION_SERIAL_IO_SPI_CS(SpiDev, CsNum) (GPIO_SERIAL_IO_SPI_CS + ((UINT32)SpiDev) + ((UINT32)CsNum) * GPIO_SERIAL_IO_SPI_RANGE)
+
+//
+// Serial IO I2C
+//
+
+#define GPIO_FUNCTION_SERIAL_IO_I2C_SCL(I2cDev) (GPIO_SERIAL_IO_I2C_SCL + ((UINT32)I2cDev))
+#define GPIO_FUNCTION_SERIAL_IO_I2C_SDA(I2cDev) (GPIO_SERIAL_IO_I2C_SDA + ((UINT32)I2cDev))
+
+//
+// ISH GP
+//
+
+#define GPIO_FUNCTION_ISH_GP(GpNum) (GPIO_ISH_GP + ((UINT32)GpNum))
+
+//
+// ISH UART
+//
+
+#define GPIO_FUNCTION_ISH_UART_RX(UartDev) (GPIO_ISH_UART_RX + ((UINT32)UartDev))
+#define GPIO_FUNCTION_ISH_UART_TX(UartDev) (GPIO_ISH_UART_TX + ((UINT32)UartDev))
+#define GPIO_FUNCTION_ISH_UART_RTS(UartDev) (GPIO_ISH_UART_RTS + ((UINT32)UartDev))
+#define GPIO_FUNCTION_ISH_UART_CTS(UartDev) (GPIO_ISH_UART_CTS + ((UINT32)UartDev))
+
+//
+// ISH SPI
+//
+#define GPIO_ISH_SPI_RANGE 8 // Number of ISH SPI controllers supported in GPIO_NATIVE_PAD encoding
+
+#define GPIO_FUNCTION_ISH_SPI_MOSI(SpiDev) (GPIO_ISH_SPI_MOSI + ((UINT32)SpiDev))
+#define GPIO_FUNCTION_ISH_SPI_MISO(SpiDev) (GPIO_ISH_SPI_MISO + ((UINT32)SpiDev))
+#define GPIO_FUNCTION_ISH_SPI_CLK(SpiDev) (GPIO_ISH_SPI_CLK + ((UINT32)SpiDev))
+#define GPIO_FUNCTION_ISH_SPI_CS(SpiDev, CsNum) (GPIO_ISH_SPI_CS + ((UINT32)SpiDev) + ((UINT32)CsNum) * GPIO_ISH_SPI_RANGE)
+
+//
+// ISH I2C
+//
+
+#define GPIO_FUNCTION_ISH_I2C_SCL(I2cDev) (GPIO_ISH_I2C_SCL + ((UINT32)I2cDev))
+#define GPIO_FUNCTION_ISH_I2C_SDA(I2cDev) (GPIO_ISH_I2C_SDA + ((UINT32)I2cDev))
+
+//
+// SD Card
+//
+#define GPIO_FUNCTION_SD_DATA(Index) (GPIO_SD_DATA + ((UINT32)Index))
+
+//
+// EMMC
+//
+#define GPIO_FUNCTION_EMMC_DATA(Index) (GPIO_EMMC_DATA + ((UINT32)Index))
+
+//
+// THC SPI
+//
+
+#define GPIO_FUNCTION_THC_SPI_INT(SpiDev) (GPIO_THC_SPI_INT + ((UINT32)SpiDev))
+#define GPIO_FUNCTION_THC_CLK_LOOPBACK(SpiDev) (GPIO_THC_CLK_LOOPBACK + ((UINT32)SpiDev))
+#define GPIO_FUNCTION_THC_WOT(SpiDev) (GPIO_THC_WOT + ((UINT32)SpiDev))
+
+
+//
+// DMIC
+//
+
+#define GPIO_FUNCTION_DMIC_DATA(DmicDev) (GPIO_DMIC_DATA + ((UINT32)DmicDev))
+#define GPIO_FUNCTION_DMIC_CLKA(DmicDev) (GPIO_DMIC_CLKA + ((UINT32)DmicDev))
+#define GPIO_FUNCTION_DMIC_CLKB(DmicDev) (GPIO_DMIC_CLKB + ((UINT32)DmicDev))
+#define GPIO_FUNCTION_DMIC_CLK(DmicDev) (GPIO_DMIC_CLKA + ((UINT32)DmicDev)) // If there is no split between channel A/B use A range for such Clocks
+
+
+//
+// DDSP HPD
+//
+
+#define GPIO_FUNCTION_DDSP_HPD(HpdIndex) \
+ (HpdIndex > 7) ? GPIO_DDSP_HPD0 + 8 + (HpdIndex) - 'A' : GPIO_DDSP_HPD0 + HpdIndex
+
+//
+// HDMI_GMBUS
+//
+
+#define GPIO_FUNCTION_HDMI_SCL(DdiPort) (GPIO_HDMI_GMBUS_SCL + ((UINT32)DdiPort))
+#define GPIO_FUNCTION_HDMI_SDA(DdiPort) (GPIO_HDMI_GMBUS_SDA + ((UINT32)DdiPort))
+
+//
+// Panel
+//
+
+#define GPIO_FUNCTION_PANEL_AVDD_EN(PanelDev) (GPIO_PANEL_AVDD_EN + ((UINT32)PanelDev))
+#define GPIO_FUNCTION_PANEL_BKLTEN(PanelDev) (GPIO_PANEL_BKLTEN + ((UINT32)PanelDev))
+#define GPIO_FUNCTION_PANEL_BKLTCTL(PanelDev) (GPIO_PANEL_BKLTCTL + ((UINT32)PanelDev))
+#define GPIO_FUNCTION_PANEL_RESET(PanelDev) (GPIO_PANEL_RESET + ((UINT32)PanelDev))
+#define GPIO_FUNCTION_PANEL_AVEE_EN(PanelDev) (GPIO_PANEL_AVEE_EN + ((UINT32)PanelDev))
+#define GPIO_FUNCTION_PANEL_VIO_EN(PanelDev) (GPIO_PANEL_VIO_EN + ((UINT32)PanelDev))
+#define GPIO_FUNCTION_PANEL_HPD(PanelDev) (GPIO_PANEL_HPD + ((UINT32)PanelDev))
+#define GPIO_FUNCTION_PANEL_TE_EN(PanelDev) (GPIO_PANEL_TE_EN + ((UINT32)PanelDev))
+
+//
+// MIPI
+//
+#define GPIO_FUNCTION_MIPI_PANEL_RESET(PanelDev) (GPIO_MIPI_PANEL_RESET + ((UINT32)PanelDev))
+#define GPIO_FUNCTION_MIPI_SEC_POW_EN_AVEE(PanelDev) (GPIO_MIPI_SEC_POW_EN_AVEE + ((UINT32)PanelDev))
+#define GPIO_FUNCTION_MIPI_SEC_POW_EN_AVDD(PanelDev) (GPIO_MIPI_SEC_POW_EN_AVDD + ((UINT32)PanelDev))
+
+
+//
+// SATA DevSlp
+//
+#define GPIO_SATA_DEVSLP_RANGE 32 // Number of SATA DevSlp instances per controller supported in GPIO_NATIVE_PAD encoding
+
+#define GPIO_FUNCTION_SATA_DEVSLP(CsNum, SataDevSlpIndex) (GPIO_SATA_DEVSLP + ((UINT32)SataDevSlpIndex) + ((UINT32)CsNum) * GPIO_SATA_DEVSLP_RANGE)
+
+//
+// SRC CLKREQ
+//
+
+#define GPIO_FUNCTION_PCIE_CLKREQ(ClkReqIndex) (GPIO_PCIE_CLKREQ + ((UINT32)ClkReqIndex))
+
+#endif // _GPIO_NATIVE_PADS_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/IncludePrivate/Library/GpioPrivateLib.h b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/IncludePrivate/Library/GpioPrivateLib.h
new file mode 100644
index 0000000000..a757a4b057
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/IncludePrivate/Library/GpioPrivateLib.h
@@ -0,0 +1,350 @@
+/** @file
+ Header file for GpioPrivateLib.
+ All function in this library is available for PEI, DXE, and SMM,
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _GPIO_PRIVATE_LIB_H_
+#define _GPIO_PRIVATE_LIB_H_
+
+#include <Uefi/UefiBaseType.h>
+#include <Library/GpioConfig.h>
+#include <Library/PchPcrLib.h>
+
+/**
+ GPIO Standby State configuration
+ Standby State options for GPIO Pads
+**/
+typedef enum {
+ GpioIosStateDefault = 0x0,
+ GpioIosStateLatchLastValue = (0x0 << 1) | 0x01, ///< Latch last value driven on TX, TX Enable and RX Enable
+ GpioIosStateTx0Rx0RxDis = (0x1 << 1) | 0x01, ///< TX: 0, RX: 0 (internally), RX disabled
+ GpioIosStateTx0Rx1RxDis = (0x2 << 1) | 0x01, ///< TX: 0, RX: 1 (internally), RX disabled
+ GpioIosStateTx1Rx0RxDis = (0x3 << 1) | 0x01, ///< TX: 1, RX: 0 (internally), RX disabled
+ GpioIosStateTx1Rx1RxDis = (0x4 << 1) | 0x01, ///< TX: 1, RX: 1 (internally), RX disabled
+ GpioIosStateTx0RxEn = (0x5 << 1) | 0x01, ///< TX: 0, RX enabled
+ GpioIosStateTx1RxEn = (0x6 << 1) | 0x01, ///< TX: 1, RX enabled
+ GpioIosStateHizRx0 = (0x7 << 1) | 0x01, ///< Hi-Z, RX: 0 (internally)
+ GpioIosStateHizRx1 = (0x8 << 1) | 0x01, ///< Hi-Z, RX: 1 (internally)
+ GpioIosStateTxDisRxEn = (0x9 << 1) | 0x01, ///< TX Disabled and RX Enabled (i.e. wake or interrupt)
+ GpioIosStateMasked = (0xF << 1) | 0x01 ///< IO Standby signal is masked for this pad. In this mode, a pad operates as if IOStandby has not been asserted.
+} GPIO_IOSTANDBY_STATE;
+
+/**
+ GPIO Standby Term configuration
+ Standby Termination options for GPIO Pads
+**/
+typedef enum {
+ GpioIosTermDefault = 0x00,
+ GpioIosTermSame = (0x00 << 1) | 0x01, ///< Same as state specified in Term
+ GpioIosTermPuDisPdDis = (0x01 << 1) | 0x01, ///< Disable Pullup and Pulldown
+ GpioIosTermPuDisPdEn = (0x02 << 1) | 0x01, ///< Enable Pulldown
+ GpioIosTermPuEnPdDis = (0x03 << 1) | 0x01 ///< Enable Pullup
+} GPIO_IOSTANDBY_TERM;
+
+//
+// Structure for native pin data
+//
+typedef struct {
+ GPIO_PAD Pad;
+ GPIO_PAD_MODE Mode;
+ GPIO_IOSTANDBY_STATE IosState;
+ GPIO_IOSTANDBY_TERM IosTerm;
+} GPIO_PAD_NATIVE_FUNCTION;
+
+//
+// Structure for Serial GPIO pin definition
+//
+typedef struct {
+ GPIO_PAD_NATIVE_FUNCTION Sclock;
+ GPIO_PAD_NATIVE_FUNCTION Sload;
+ GPIO_PAD_NATIVE_FUNCTION Sdataout;
+} SGPIO_PINS;
+
+//
+// Structure for USB Virtual Wire OverCurrent Pad Mode group
+//
+typedef struct {
+ GPIO_PAD OcRxPad;
+ GPIO_PAD OcTxPad;
+} GPIO_VWOC_FUNCTION;
+
+//
+// Below defines are based on GPIO_CONFIG structure fields
+//
+#define B_GPIO_PAD_MODE_MASK 0xF
+#define N_GPIO_PAD_MODE_BIT_POS 0
+#define B_GPIO_DIRECTION_DIR_MASK 0x7
+#define N_GPIO_DIRECTION_DIR_BIT_POS 0
+#define B_GPIO_DIRECTION_INV_MASK 0x18
+#define N_GPIO_DIRECTION_INV_BIT_POS 3
+#define B_GPIO_OUTPUT_MASK 0x3
+#define N_GPIO_OUTPUT_BIT_POS 0
+#define N_GPIO_INT_CONFIG_INT_SOURCE_BIT_POS 0
+#define N_GPIO_INT_CONFIG_INT_TYPE_BIT_POS 5
+#define N_GPIO_ELECTRICAL_CONFIG_TERMINATION_BIT_POS 0
+#define N_GPIO_OTHER_CONFIG_RXRAW_BIT_POS 0
+
+//
+// Structure for storing information about registers offset, community,
+// maximal pad number for available groups
+//
+typedef struct {
+ PCH_SBI_PID Community;
+ UINT16 PadOwnOffset;
+ UINT16 HostOwnOffset;
+ UINT16 GpiIsOffset;
+ UINT16 GpiIeOffset;
+ UINT16 GpiGpeStsOffset;
+ UINT16 GpiGpeEnOffset;
+ UINT16 SmiStsOffset;
+ UINT16 SmiEnOffset;
+ UINT16 NmiStsOffset;
+ UINT16 NmiEnOffset;
+ UINT16 PadCfgLockOffset;
+ UINT16 PadCfgLockTxOffset;
+ UINT16 PadCfgOffset;
+ UINT16 PadPerGroup;
+} GPIO_GROUP_INFO;
+
+//
+// If in GPIO_GROUP_INFO structure certain register doesn't exist
+// it will have value equal to NO_REGISTER_FOR_PROPERTY
+//
+#define NO_REGISTER_FOR_PROPERTY 0xFFFF
+
+#define GPIO_PAD_DEF(Group,Pad) (UINT32)(((Group) << 16) + (Pad))
+#define GPIO_GROUP_DEF(GroupIndex,ChipsetId) ((GroupIndex) | ((ChipsetId) << 8))
+#define GPIO_GET_GROUP_INDEX(Group) ((Group) & 0x1F)
+#define GPIO_GET_GROUP_FROM_PAD(GpioPad) (((GpioPad) & 0x0F1F0000) >> 16)
+#define GPIO_GET_GROUP_INDEX_FROM_PAD(GpioPad) GPIO_GET_GROUP_INDEX (GPIO_GET_GROUP_FROM_PAD(GpioPad))
+#define GPIO_GET_PAD_NUMBER(GpioPad) ((GpioPad) & 0x1FF)
+#define GPIO_GET_CHIPSET_ID(GpioPad) (((GpioPad) >> 24) & 0xF)
+
+#define GPIO_GET_PAD_POSITION(PadNumber) ((PadNumber) % 32)
+#define GPIO_GET_DW_NUM(PadNumber) ((PadNumber) / 32u)
+
+/**
+ This procedure will retrieve address and length of GPIO info table
+
+ @param[out] GpioGroupInfoTableLength Length of GPIO group table
+
+ @retval Pointer to GPIO group table
+**/
+CONST GPIO_GROUP_INFO*
+GpioGetGroupInfoTable (
+ OUT UINT32 *GpioGroupInfoTableLength
+ );
+
+typedef struct {
+ CONST CHAR8* GpioGroupPrefix;
+ CONST GPIO_PAD FirstUniqueGpio;
+ CONST CHAR8** GroupUniqueNames;
+ CONST UINT32 UniqueNamesTableSize;
+} GPIO_GROUP_NAME_INFO;
+
+//
+// Helper macros for initializing GPIO_GROUP_NAME_INFO structures
+//
+#define GPIO_GROUP_NAME(GroupName,FirstUniqueGpio,GroupUniqueNamesTable) \
+ {GroupName, FirstUniqueGpio, GroupUniqueNamesTable, ARRAY_SIZE (GroupUniqueNamesTable)}
+
+#define GPIO_GROUP_NAME_BASIC(GroupName) \
+ {GroupName, 0, NULL, 0}
+
+/**
+ Get GPIO Chipset ID specific to PCH generation and series
+**/
+UINT32
+GpioGetThisChipsetId (
+ VOID
+ );
+
+/**
+ This procedure is used to check if GpioPad is valid for certain chipset
+
+ @param[in] GpioPad GPIO pad
+
+ @retval TRUE This pin is valid on this chipset
+ FALSE Incorrect pin
+**/
+BOOLEAN
+GpioIsCorrectPadForThisChipset (
+ IN GPIO_PAD GpioPad
+ );
+
+
+/**
+ This procedure is used by PchSmiDispatcher and will return information
+ needed to register GPI SMI.
+
+ @param[in] Index GPI SMI number
+ @param[out] GpioPin GPIO pin
+ @param[out] GpiSmiBitOffset GPI SMI bit position within GpiSmi Registers
+ @param[out] GpiHostSwOwnRegAddress Address of HOSTSW_OWN register
+ @param[out] GpiSmiStsRegAddress Address of GPI SMI status register
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid group or pad number
+**/
+EFI_STATUS
+GpioGetPadAndSmiRegs (
+ IN UINT32 Index,
+ OUT GPIO_PAD *GpioPin,
+ OUT UINT8 *GpiSmiBitOffset,
+ OUT UINT32 *GpiHostSwOwnRegAddress,
+ OUT UINT32 *GpiSmiStsRegAddress
+ );
+
+/**
+ This procedure calculates Pad Configuration Register DW offset
+
+ @param[in] GpioPad GPIO pad
+ @param[in] DwReg Index of the configuration register
+
+ @retval DW Register offset
+**/
+UINT32
+GpioGetGpioPadCfgAddressFromGpioPad (
+ IN GPIO_PAD GpioPad,
+ IN UINT32 DwReg
+ );
+
+
+/**
+ This procedure will check if GpioPad argument is valid.
+ Function will check below conditions:
+ - GpioPad represents a pad for current PCH
+ - GpioPad belongs to valid GpioGroup
+ - GPIO PadNumber is not greater than number of pads for this group
+
+ @param[in] GpioPad GPIO pad
+
+ @retval TRUE GPIO pad is valid and can be used with GPIO lib API
+ @retval FALSE GPIO pad is invalid and cannot be used with GPIO lib API
+**/
+BOOLEAN
+GpioIsPadValid (
+ IN GPIO_PAD GpioPad
+ );
+
+/**
+ This procedure will read GPIO Pad Configuration register
+
+ @param[in] GpioPad GPIO pad
+ @param[in] DwReg Choose PADCFG register: 0:DW0, 1:DW1
+
+ @retval PadCfgRegValue PADCFG_DWx value
+**/
+UINT32
+GpioReadPadCfgReg (
+ IN GPIO_PAD GpioPad,
+ IN UINT8 DwReg
+ );
+
+/**
+ Check if 0x13 opcode supported for writing to GPIO lock unlock register
+
+ @retval TRUE It's supported
+ @retval FALSE It's not supported
+**/
+BOOLEAN
+IsGpioLockOpcodeSupported (
+ VOID
+ );
+
+/**
+ Gpio Minimum Set
+
+ Set of Gpio Minimum function to use in Pre Mem phase.
+ To optimise execution and reduce memory footprint thse minimum version
+ of 'full' functions are stripped from:
+ - GpioPad PCH validation
+ - GpioPad Group belonging validation
+ - GpioPad Host ownership validation
+ - IoStandbyState configuration
+ The use of below functions has to be careful and with full
+ understanding of all pros and cons. Please refer to GpioPrivateLib.c
+ to familiarize with details of implementation.
+**/
+
+/**
+ This procedure reads GPIO register
+
+ @param[in] GpioGroupInfo Pointer to GPIO group table info
+ @param[in] Register Register offset
+
+ @retval Register value or "F"s in case of errors
+**/
+UINT32
+GpioRegisterAccessRead32 (
+ IN CONST GPIO_GROUP_INFO *GpioGroupInfo,
+ IN UINT32 Register
+ );
+
+/**
+ This procedure writes GPIO register
+
+ @param[in] GpioGroupInfo Pointer to GPIO group table info
+ @param[in] Register Register offset
+ @param[in] AndValue And value
+ @param[in] OrValue Or value
+
+ @retval EFI_DEVICE_ERROR vGPIO BAR not programmed
+ EFI_SUCCESS Operation completed successfully
+**/
+EFI_STATUS
+GpioRegisterAccessAndThenOr32 (
+ IN CONST GPIO_GROUP_INFO *GpioGroupInfo,
+ IN UINT32 Register,
+ IN UINT32 AndValue,
+ IN UINT32 OrValue
+ );
+
+/**
+ This procedure will calculate PADCFG register value based on GpioConfig data
+ The procedure can be various depending on chipset generation.
+ Available configuration options and corresponding registers fields
+ can distributed in different way in configuration registers.
+
+ @param[in] GpioPad GPIO Pad
+ @param[in] GpioConfig GPIO Configuration data
+ @param[out] PadCfgDwReg PADCFG DWx register value
+ @param[out] PadCfgDwRegMask Mask with PADCFG DWx register bits to be modified
+
+ @retval Status
+**/
+EFI_STATUS
+GpioPadCfgRegValueFromGpioConfig (
+ IN GPIO_PAD GpioPad,
+ IN CONST GPIO_CONFIG *GpioConfig,
+ OUT UINT32 *PadCfgDwReg,
+ OUT UINT32 *PadCfgDwRegMask
+ );
+
+/**
+ This procedure will write GPIO Lock/LockTx register
+ - For PCH SBI message is used.
+ - For IBL MMIO access is used.
+
+ @param[in] RegValue GPIO register (Lock or LockTx) value
+ @param[in] RegOffset GPIO register (Lock or LockTx) base offset
+ @param[in] DwNum Register number for current group.
+ For group which has less then 32 pads per group DwNum must be 0.
+ @param[in] GpioGroupInfo Pointer to GPIO group table info
+ @param[in] GroupIndex GPIO group index in the GpioGroupInfo table
+
+ @retval EFI_SUCCESS The function completed successfully
+ EFI_UNSUPPORTED Feature is not supported for this group or pad
+**/
+EFI_STATUS
+GpioInternalWriteLockRegister (
+ IN UINT32 RegValue,
+ IN UINT32 RegOffset,
+ IN UINT32 DwNum,
+ IN CONST GPIO_GROUP_INFO *GpioGroupInfo,
+ IN UINT32 GroupIndex
+ );
+
+#endif // _GPIO_PRIVATE_LIB_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/Library/PeiDxeSmmGpioLib/GpioInit.c b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/Library/PeiDxeSmmGpioLib/GpioInit.c
new file mode 100644
index 0000000000..cf6f92a50d
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/Library/PeiDxeSmmGpioLib/GpioInit.c
@@ -0,0 +1,546 @@
+/** @file
+ This file contains routines for GPIO initialization
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#include "GpioLibrary.h"
+
+//
+// GPIO_GROUP_DW_DATA structure is used by GpioConfigurePch function
+// to cache values which will be programmed into respective GPIO registers
+// after all GpioPads are processed. This way MMIO accesses are decreased
+// and instead of doing one programming for one GpioPad there is only
+// one access for whole register.
+//
+typedef struct {
+ UINT32 HostSoftOwnReg;
+ UINT32 HostSoftOwnRegMask;
+ UINT32 GpiGpeEnReg;
+ UINT32 GpiGpeEnRegMask;
+ UINT32 GpiNmiEnReg;
+ UINT32 GpiNmiEnRegMask;
+ UINT32 GpiSmiEnReg;
+ UINT32 GpiSmiEnRegMask;
+ UINT32 ConfigUnlockMask;
+ UINT32 OutputUnlockMask;
+} GPIO_GROUP_DW_DATA;
+
+//
+// GPIO_GROUP_DW_NUMBER contains number of DWords required to
+// store Pad data for all groups. Each pad uses one bit.
+//
+// For Cannonlake only vGPIO group has >32 pads but those pads
+// will not be accessed by this function so GPIO_GROUP_DW_NUMBER can be 1
+//
+#define GPIO_GROUP_DW_NUMBER 1
+
+/**
+ Get GPIO DW Register values (HOSTSW_OWN, GPE_EN, NMI_EN, Lock).
+
+ @param[in] PadNumber GPIO pad number
+ @param[in] GpioConfig GPIO Config data
+ @param[in out] DwRegsValues Values for GPIO DW Registers
+
+ @retval None
+**/
+STATIC
+VOID
+GpioDwRegValueFromGpioConfig (
+ IN UINT32 PadNumber,
+ IN CONST GPIO_CONFIG *GpioConfig,
+ IN OUT GPIO_GROUP_DW_DATA *GroupDwData
+ )
+{
+ UINT32 PadBitPosition;
+ UINT32 DwNum;
+
+ PadBitPosition = GPIO_GET_PAD_POSITION (PadNumber);
+ DwNum = GPIO_GET_DW_NUM (PadNumber);
+
+ if (DwNum >= GPIO_GROUP_DW_NUMBER) {
+ ASSERT (FALSE);
+ return;
+ }
+ //
+ // Update value to be programmed in HOSTSW_OWN register
+ //
+ GroupDwData[DwNum].HostSoftOwnRegMask |= (GpioConfig->HostSoftPadOwn & 0x1) << PadBitPosition;
+ GroupDwData[DwNum].HostSoftOwnReg |= (GpioConfig->HostSoftPadOwn >> 0x1) << PadBitPosition;
+
+ //
+ // Update value to be programmed in GPI_GPE_EN register
+ //
+ GroupDwData[DwNum].GpiGpeEnRegMask |= (GpioConfig->InterruptConfig & 0x1) << PadBitPosition;
+ GroupDwData[DwNum].GpiGpeEnReg |= ((GpioConfig->InterruptConfig & GpioIntSci) >> 3) << PadBitPosition;
+
+ //
+ // Update value to be programmed in GPI_NMI_EN register
+ //
+ GroupDwData[DwNum].GpiNmiEnRegMask |= (GpioConfig->InterruptConfig & 0x1) << PadBitPosition;
+ GroupDwData[DwNum].GpiNmiEnReg |= ((GpioConfig->InterruptConfig & GpioIntNmi) >> 1) << PadBitPosition;
+
+ //
+ // Update value to be programmed in GPI_SMI_EN register
+ GroupDwData[DwNum].GpiSmiEnRegMask |= (GpioConfig->InterruptConfig & 0x1) << PadBitPosition;
+ GroupDwData[DwNum].GpiSmiEnReg |= ((GpioConfig->InterruptConfig & GpioIntSmi) >> 2) << PadBitPosition;
+ if ((GpioConfig->InterruptConfig & GpioIntSmi) == GpioIntSmi) {
+ GroupDwData[DwNum].HostSoftOwnRegMask |= 1 << PadBitPosition;
+ GroupDwData[DwNum].HostSoftOwnReg |= 1 << PadBitPosition;
+ }
+
+ //
+ // Update information on Pad Configuration Lock
+ //
+ GroupDwData[DwNum].ConfigUnlockMask |= ((GpioConfig->LockConfig >> 1) & 0x1) << PadBitPosition;
+
+ //
+ // Update information on Pad Configuration Lock Tx
+ //
+ GroupDwData[DwNum].OutputUnlockMask |= ((GpioConfig->LockConfig >> 3) & 0x1) << PadBitPosition;
+
+ //
+ // if pad in GpioMode is an output default action should be to leave output unlocked
+ //
+ if ((GpioConfig->PadMode == GpioPadModeGpio) &&
+ (GpioConfig->Direction == GpioDirOut) &&
+ ((GpioConfig->LockConfig & B_GPIO_LOCK_CONFIG_OUTPUT_LOCK_MASK) == GpioLockDefault)) {
+ GroupDwData[DwNum].OutputUnlockMask |= 0x1 << PadBitPosition;
+ }
+}
+
+/**
+ This internal procedure will scan GPIO initialization table and unlock
+ all pads present in it
+
+ @param[in] NumberOfItem Number of GPIO pad records in table
+ @param[in] GpioInitTableAddress GPIO initialization table
+ @param[in] Index Index of GPIO Initialization table record
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid group or pad number
+**/
+STATIC
+EFI_STATUS
+GpioUnlockPadsForAGroup (
+ IN UINT32 NumberOfItems,
+ IN GPIO_INIT_CONFIG *GpioInitTableAddress,
+ IN UINT32 Index
+ )
+{
+ UINT32 PadsToUnlock[GPIO_GROUP_DW_NUMBER];
+ UINT32 DwNum;
+ UINT32 PadBitPosition;
+ CONST GPIO_GROUP_INFO *GpioGroupInfo;
+ UINT32 GpioGroupInfoLength;
+ CONST GPIO_INIT_CONFIG *GpioData;
+ GPIO_GROUP Group;
+ UINT32 GroupIndex;
+ UINT32 PadNumber;
+
+ GpioGroupInfo = GpioGetGroupInfoTable (&GpioGroupInfoLength);
+
+ GpioData = &GpioInitTableAddress[Index];
+ Group = GpioGetGroupFromGpioPad (GpioData->GpioPad);
+ GroupIndex = GpioGetGroupIndexFromGpioPad (GpioData->GpioPad);
+
+ ZeroMem (PadsToUnlock, sizeof (PadsToUnlock));
+ //
+ // Loop through pads for one group. If pad belongs to a different group then
+ // break and move to register programming.
+ //
+ while (Index < NumberOfItems) {
+
+ GpioData = &GpioInitTableAddress[Index];
+ if (GroupIndex != GpioGetGroupIndexFromGpioPad (GpioData->GpioPad)) {
+ //if next pad is from different group then break loop
+ break;
+ }
+
+ PadNumber = GpioGetPadNumberFromGpioPad (GpioData->GpioPad);
+ //
+ // Check if legal pin number
+ //
+ if (PadNumber >= GpioGroupInfo[GroupIndex].PadPerGroup) {
+ DEBUG ((DEBUG_ERROR, "GPIO ERROR: Pin number (%d) exceeds possible range for group %d\n", PadNumber, GroupIndex));
+ return EFI_INVALID_PARAMETER;
+ }
+
+ PadBitPosition = GPIO_GET_PAD_POSITION (PadNumber);
+ DwNum = GPIO_GET_DW_NUM (PadNumber);
+
+ if (DwNum >= GPIO_GROUP_DW_NUMBER) {
+ ASSERT (FALSE);
+ return EFI_UNSUPPORTED;
+ }
+ //
+ // Update pads which need to be unlocked
+ //
+ PadsToUnlock[DwNum] |= 0x1 << PadBitPosition;
+
+ //Move to next item
+ Index++;
+ }
+
+ for (DwNum = 0; DwNum <= GPIO_GET_DW_NUM (GpioGroupInfo[GroupIndex].PadPerGroup - 1); DwNum++) {
+ //
+ // Unlock pads
+ //
+ if (PadsToUnlock[DwNum] != 0) {
+ GpioUnlockPadCfgForGroupDw (Group, DwNum, PadsToUnlock[DwNum]);
+ GpioUnlockPadCfgTxForGroupDw (Group, DwNum, PadsToUnlock[DwNum]);
+ }
+ }
+
+ return EFI_SUCCESS;
+}
+
+/**
+ This procedure will initialize multiple PCH GPIO pins
+
+ @param[in] NumberofItem Number of GPIO pads to be updated
+ @param[in] GpioInitTableAddress GPIO initialization table
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid group or pad number
+**/
+STATIC
+EFI_STATUS
+GpioConfigurePch (
+ IN UINT32 NumberOfItems,
+ IN GPIO_INIT_CONFIG *GpioInitTableAddress
+ )
+{
+ UINT32 Index;
+ UINT32 PadCfgDwReg[GPIO_PADCFG_DW_REG_NUMBER];
+ UINT32 PadCfgDwRegMask[GPIO_PADCFG_DW_REG_NUMBER];
+ UINT32 PadCfgReg;
+ GPIO_GROUP_DW_DATA GroupDwData[GPIO_GROUP_DW_NUMBER];
+ UINT32 DwNum;
+ CONST GPIO_GROUP_INFO *GpioGroupInfo;
+ UINT32 GpioGroupInfoLength;
+ GPIO_PAD_OWN PadOwnVal;
+ CONST GPIO_INIT_CONFIG *GpioData;
+ UINT32 GroupIndex;
+ UINT32 PadNumber;
+ UINT32 DwRegIndex;
+
+ PadOwnVal = GpioPadOwnHost;
+
+ GpioGroupInfo = GpioGetGroupInfoTable (&GpioGroupInfoLength);
+
+ Index = 0;
+ while (Index < NumberOfItems) {
+
+ GpioData = &GpioInitTableAddress[Index];
+ GroupIndex = GpioGetGroupIndexFromGpioPad (GpioData->GpioPad);
+
+ DEBUG_CODE_BEGIN();
+ if (!GpioIsCorrectPadForThisChipset (GpioData->GpioPad)) {
+ DEBUG ((DEBUG_ERROR, "GPIO ERROR: Incorrect GpioPad (0x%08x) used on this chipset!\n", GpioData->GpioPad));
+ ASSERT (FALSE);
+ return EFI_UNSUPPORTED;
+ }
+ DEBUG_CODE_END ();
+
+ //
+ // Unlock pads for a given group which are going to be reconfigured
+ //
+ //
+ // Because PADCFGLOCK/LOCKTX register reset domain is Powergood, lock settings
+ // will get back to default only after G3 or DeepSx transition. On the other hand GpioPads
+ // configuration is controlled by a configurable type of reset - PadRstCfg. This means that if
+ // PadRstCfg != Powergood GpioPad will have its configuration locked despite it being not the
+ // one desired by BIOS. Before reconfiguring all pads they will get unlocked.
+ //
+ GpioUnlockPadsForAGroup (NumberOfItems, GpioInitTableAddress, Index);
+
+ ZeroMem (GroupDwData, sizeof (GroupDwData));
+ //
+ // Loop through pads for one group. If pad belongs to a different group then
+ // break and move to register programming.
+ //
+ while (Index < NumberOfItems) {
+
+ GpioData = &GpioInitTableAddress[Index];
+ if (GroupIndex != GpioGetGroupIndexFromGpioPad (GpioData->GpioPad)) {
+ //if next pad is from different group then break loop
+ break;
+ }
+
+ PadNumber = GpioGetPadNumberFromGpioPad (GpioData->GpioPad);
+
+ DEBUG_CODE_BEGIN ();
+ //
+ // Check if legal pin number
+ //
+ if (PadNumber >= GpioGroupInfo[GroupIndex].PadPerGroup) {
+ DEBUG ((DEBUG_ERROR, "GPIO ERROR: Pin number (%d) exceeds possible range for group %d\n", PadNumber, GroupIndex));
+ return EFI_INVALID_PARAMETER;
+ }
+
+ //
+ // Check if selected GPIO Pad is not owned by CSME/ISH
+ //
+ GpioGetPadOwnership (GpioData->GpioPad, &PadOwnVal);
+
+ if (PadOwnVal != GpioPadOwnHost) {
+ DEBUG ((DEBUG_ERROR, "GPIO ERROR: Accessing pad not owned by host (Group=%d, Pad=%d)!\n", GroupIndex, PadNumber));
+ DEBUG ((DEBUG_ERROR, "** Please make sure the GPIO usage in sync between CSME and BIOS configuration. \n"));
+ DEBUG ((DEBUG_ERROR, "** All the GPIO occupied by CSME should not do any configuration by BIOS.\n"));
+ //Move to next item
+ goto move_to_next_index;
+ }
+
+ //
+ // Check if Pad enabled for SCI is to be in unlocked state
+ //
+ if (((GpioData->GpioConfig.InterruptConfig & GpioIntSci) == GpioIntSci) &&
+ ((GpioData->GpioConfig.LockConfig & B_GPIO_LOCK_CONFIG_PAD_CONF_LOCK_MASK) != GpioPadConfigUnlock)){
+ DEBUG ((DEBUG_ERROR, "GPIO ERROR: GPIO used for SCI is not unlocked!\n"));
+ ASSERT (FALSE);
+ return EFI_INVALID_PARAMETER;
+ }
+ DEBUG_CODE_END ();
+
+ ZeroMem (PadCfgDwReg, sizeof (PadCfgDwReg));
+ ZeroMem (PadCfgDwRegMask, sizeof (PadCfgDwRegMask));
+ //
+ // Get GPIO PADCFG register value from GPIO config data
+ //
+ GpioPadCfgRegValueFromGpioConfig (
+ GpioData->GpioPad,
+ &GpioData->GpioConfig,
+ PadCfgDwReg,
+ PadCfgDwRegMask
+ );
+
+ //
+ // Write PADCFG DW0, DW1, DW2 registers
+ //
+ for (DwRegIndex = 0; DwRegIndex <= 2; DwRegIndex++) {
+ PadCfgReg = GpioGetGpioPadCfgAddressFromGpioPad (GpioData->GpioPad, DwRegIndex);
+ if (PadCfgReg != 0) {
+ GpioRegisterAccessAndThenOr32 (&GpioGroupInfo[GroupIndex], PadCfgReg, ~PadCfgDwRegMask[DwRegIndex], PadCfgDwReg[DwRegIndex]);
+ }
+ }
+
+ //
+ // Get GPIO DW register values from GPIO config data
+ //
+ GpioDwRegValueFromGpioConfig (
+ PadNumber,
+ &GpioData->GpioConfig,
+ GroupDwData
+ );
+
+ move_to_next_index:
+ //Move to next item
+ Index++;
+ }
+
+ for (DwNum = 0; DwNum <= GPIO_GET_DW_NUM (GpioGroupInfo[GroupIndex].PadPerGroup); DwNum++) {
+ //
+ // Write HOSTSW_OWN registers
+ //
+ if (GpioGroupInfo[GroupIndex].HostOwnOffset != NO_REGISTER_FOR_PROPERTY) {
+ GpioRegisterAccessAndThenOr32 (
+ &GpioGroupInfo[GroupIndex],
+ GpioGroupInfo[GroupIndex].HostOwnOffset + DwNum * 0x4,
+ ~GroupDwData[DwNum].HostSoftOwnRegMask,
+ GroupDwData[DwNum].HostSoftOwnReg
+ );
+ }
+
+ //
+ // Write GPI_GPE_EN registers
+ //
+ if (GpioGroupInfo[GroupIndex].GpiGpeEnOffset != NO_REGISTER_FOR_PROPERTY) {
+ GpioRegisterAccessAndThenOr32 (
+ &GpioGroupInfo[GroupIndex],
+ GpioGroupInfo[GroupIndex].GpiGpeEnOffset + DwNum * 0x4,
+ ~GroupDwData[DwNum].GpiGpeEnRegMask,
+ GroupDwData[DwNum].GpiGpeEnReg
+ );
+ }
+
+ //
+ // Write GPI_NMI_EN registers
+ //
+ if (GpioGroupInfo[GroupIndex].NmiEnOffset != NO_REGISTER_FOR_PROPERTY) {
+ GpioRegisterAccessAndThenOr32 (
+ &GpioGroupInfo[GroupIndex],
+ GpioGroupInfo[GroupIndex].NmiEnOffset + DwNum * 0x4,
+ ~GroupDwData[DwNum].GpiNmiEnRegMask,
+ GroupDwData[DwNum].GpiNmiEnReg
+ );
+ } else if (GroupDwData[DwNum].GpiNmiEnReg != 0x0) {
+ DEBUG ((DEBUG_ERROR, "GPIO ERROR: Group %d has no pads supporting NMI\n", GroupIndex));
+ ASSERT_EFI_ERROR (EFI_UNSUPPORTED);
+ }
+
+ //
+ // Write GPI_SMI_EN registers
+ //
+ if (GpioGroupInfo[GroupIndex].SmiEnOffset != NO_REGISTER_FOR_PROPERTY) {
+ GpioRegisterAccessAndThenOr32 (
+ &GpioGroupInfo[GroupIndex],
+ GpioGroupInfo[GroupIndex].SmiEnOffset + DwNum * 0x4,
+ ~GroupDwData[DwNum].GpiSmiEnRegMask,
+ GroupDwData[DwNum].GpiSmiEnReg
+ );
+ } else if (GroupDwData[DwNum].GpiSmiEnReg != 0x0) {
+ DEBUG ((DEBUG_ERROR, "GPIO ERROR: Group %d has no pads supporting SMI\n", GroupIndex));
+ ASSERT_EFI_ERROR (EFI_UNSUPPORTED);
+ }
+
+ //
+ // Update Pad Configuration unlock data
+ //
+ if (GroupDwData[DwNum].ConfigUnlockMask) {
+ GpioStoreGroupDwUnlockPadConfigData (GroupIndex, DwNum, GroupDwData[DwNum].ConfigUnlockMask);
+ }
+
+ //
+ // Update Pad Output unlock data
+ //
+ if (GroupDwData[DwNum].OutputUnlockMask) {
+ GpioStoreGroupDwUnlockOutputData (GroupIndex, DwNum, GroupDwData[DwNum].OutputUnlockMask);
+ }
+ }
+ }
+
+ return EFI_SUCCESS;
+}
+
+/**
+ This procedure will clear all status bits of any GPIO interrupts.
+
+ @param[in] none
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid group or pad number
+**/
+STATIC
+EFI_STATUS
+GpioClearAllGpioInterrupts (
+ VOID
+ )
+{
+ GPIO_GROUP Group;
+ CONST GPIO_GROUP_INFO *GpioGroupInfo;
+ GPIO_GROUP GpioGroupLowest;
+ GPIO_GROUP GpioGroupHighest;
+ UINT32 GroupIndex;
+ UINT32 GpioGroupInfoLength;
+ UINT32 DwNum;
+
+ GpioGroupInfo = GpioGetGroupInfoTable (&GpioGroupInfoLength);
+
+ GpioGroupLowest = GpioGetLowestGroup ();
+ GpioGroupHighest = GpioGetHighestGroup ();
+
+ for (Group = GpioGroupLowest; Group <= GpioGroupHighest; Group++) {
+ GroupIndex = GpioGetGroupIndexFromGroup (Group);
+ //
+ // Check if group has GPI IS register
+ //
+ if (GpioGroupInfo[GroupIndex].GpiIsOffset != NO_REGISTER_FOR_PROPERTY) {
+ //
+ // Clear all GPI_IS Status bits by writing '1'
+ //
+ for (DwNum = 0; DwNum <= GPIO_GET_DW_NUM (GpioGroupInfo[GroupIndex].PadPerGroup); DwNum++) {
+ GpioRegisterAccessAndThenOr32 (
+ &GpioGroupInfo[GroupIndex],
+ GpioGroupInfo[GroupIndex].GpiIsOffset + DwNum * 0x4,
+ ~(UINT32)0,
+ 0xFFFFFFFF
+ );
+ }
+ }
+
+ //
+ // Check if group has GPI_GPE_STS register
+ //
+ if (GpioGroupInfo[GroupIndex].GpiGpeStsOffset != NO_REGISTER_FOR_PROPERTY) {
+ //
+ // Clear all GPI_GPE_STS Status bits by writing '1'
+ //
+ for (DwNum = 0; DwNum <= GPIO_GET_DW_NUM (GpioGroupInfo[GroupIndex].PadPerGroup); DwNum++) {
+ GpioRegisterAccessAndThenOr32 (
+ &GpioGroupInfo[GroupIndex],
+ GpioGroupInfo[GroupIndex].GpiGpeStsOffset + DwNum * 0x4,
+ ~(UINT32)0,
+ 0xFFFFFFFF
+ );
+ }
+ }
+
+ //
+ // Check if group has SMI_STS register
+ //
+ if (GpioGroupInfo[GroupIndex].SmiStsOffset != NO_REGISTER_FOR_PROPERTY) {
+ //
+ // Clear all SMI_STS Status bits by writing '1'
+ //
+ for (DwNum = 0; DwNum <= GPIO_GET_DW_NUM (GpioGroupInfo[GroupIndex].PadPerGroup); DwNum++) {
+ GpioRegisterAccessAndThenOr32 (
+ &GpioGroupInfo[GroupIndex],
+ GpioGroupInfo[GroupIndex].SmiStsOffset + DwNum * 4,
+ ~(UINT32)0,
+ 0xFFFFFFFF
+ );
+ }
+ }
+
+ //
+ // Check if group has NMI_STS register
+ //
+ if (GpioGroupInfo[GroupIndex].NmiStsOffset != NO_REGISTER_FOR_PROPERTY) {
+ //
+ // Clear all NMI_STS Status bits by writing '1'
+ //
+ for (DwNum = 0; DwNum <= GPIO_GET_DW_NUM (GpioGroupInfo[GroupIndex].PadPerGroup); DwNum++) {
+ GpioRegisterAccessAndThenOr32 (
+ &GpioGroupInfo[GroupIndex],
+ GpioGroupInfo[GroupIndex].NmiStsOffset + DwNum * 4,
+ ~(UINT32)0,
+ 0xFFFFFFFF
+ );
+ }
+ }
+
+ }
+ return EFI_SUCCESS;
+}
+
+/**
+ This procedure will initialize multiple GPIO pins. Use GPIO_INIT_CONFIG structure.
+ Structure contains fields that can be used to configure each pad.
+ Pad not configured using GPIO_INIT_CONFIG will be left with hardware default values.
+ Separate fields could be set to hardware default if it does not matter, except
+ GpioPad and PadMode.
+ Function will work in most efficient way if pads which belong to the same group are
+ placed in adjacent records of the table.
+ Although function can enable pads for Native mode, such programming is done
+ by reference code when enabling related silicon feature.
+
+ @param[in] NumberofItem Number of GPIO pads to be updated
+ @param[in] GpioInitTableAddress GPIO initialization table
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid group or pad number
+**/
+EFI_STATUS
+GpioConfigurePads (
+ IN UINT32 NumberOfItems,
+ IN GPIO_INIT_CONFIG *GpioInitTableAddress
+ )
+{
+ EFI_STATUS Status;
+
+ Status = GpioConfigurePch (NumberOfItems, GpioInitTableAddress);
+
+ GpioClearAllGpioInterrupts ();
+ return Status;
+}
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/Library/PeiDxeSmmGpioLib/GpioLib.c b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/Library/PeiDxeSmmGpioLib/GpioLib.c
new file mode 100644
index 0000000000..19daed97c0
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/Library/PeiDxeSmmGpioLib/GpioLib.c
@@ -0,0 +1,522 @@
+/** @file
+ This file contains routines for GPIO
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#include "GpioLibrary.h"
+#include <Register/PchPcrRegs.h>
+
+/**
+ This procedure will check if GpioGroup argument is correct and
+ supplied DW reg number can be used for this group to access DW registers.
+ Function will check below conditions:
+ - Valid GpioGroup
+ - DwNum is has valid value for this group
+
+ @param[in] Group GPIO group
+ @param[in] DwNum Register number for current group (parameter applicable in accessing whole register).
+ For group which has less then 32 pads per group DwNum must be 0.
+
+ @retval TRUE DW Reg number and GpioGroup is valid
+ @retval FALSE DW Reg number and GpioGroup is invalid
+**/
+STATIC
+BOOLEAN
+GpioIsGroupAndDwNumValid (
+ IN GPIO_GROUP Group,
+ IN UINT32 DwNum
+ )
+{
+ UINT32 GroupIndex;
+ CONST GPIO_GROUP_INFO *GpioGroupInfo;
+ UINT32 GpioGroupInfoLength;
+
+ GpioGroupInfo = GpioGetGroupInfoTable (&GpioGroupInfoLength);
+
+ GroupIndex = GpioGetGroupIndexFromGroup (Group);
+
+ if ((Group < GpioGetLowestGroup ()) || (Group > GpioGetHighestGroup ()) || (GroupIndex >= GpioGroupInfoLength)) {
+ DEBUG ((DEBUG_ERROR, "GPIO ERROR: Group argument (%d) is not within range of possible groups for this PCH\n", GroupIndex));
+ goto Error;
+ }
+
+ //
+ // Check if DwNum argument does not exceed number of DWord registers
+ // resulting from available pads for certain group
+ //
+ if (DwNum > GPIO_GET_DW_NUM (GpioGroupInfo[GroupIndex].PadPerGroup - 1)){
+ goto Error;
+ }
+
+ return TRUE;
+Error:
+ ASSERT (FALSE);
+ return FALSE;
+}
+
+//
+// Possible registers to be accessed using GpioReadReg()/GpioWriteReg() functions
+//
+typedef enum {
+ GpioHostOwnershipRegister = 0,
+ GpioGpeEnableRegister,
+ GpioGpeStatusRegister,
+ GpioSmiEnableRegister,
+ GpioSmiStatusRegister,
+ GpioNmiEnableRegister,
+ GpioPadConfigLockRegister,
+ GpioPadLockOutputRegister
+} GPIO_REG;
+
+/**
+ This procedure will read GPIO register
+
+ @param[in] RegType GPIO register type
+ @param[in] Group GPIO group
+ @param[in] DwNum Register number for current group (parameter applicable in accessing whole register).
+ For group which has less then 32 pads per group DwNum must be 0.
+ @param[out] ReadVal Read data
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_UNSUPPORTED Feature is not supported for this group or pad
+**/
+STATIC
+EFI_STATUS
+GpioReadReg (
+ IN GPIO_REG RegType,
+ IN GPIO_GROUP Group,
+ IN UINT32 DwNum,
+ OUT UINT32 *ReadVal
+ )
+{
+ UINT32 RegOffset;
+ UINT32 GroupIndex;
+ CONST GPIO_GROUP_INFO *GpioGroupInfo;
+ UINT32 GpioGroupInfoLength;
+
+ RegOffset = NO_REGISTER_FOR_PROPERTY;
+ GroupIndex = GpioGetGroupIndexFromGroup (Group);
+
+ GpioGroupInfo = GpioGetGroupInfoTable (&GpioGroupInfoLength);
+
+ switch (RegType) {
+ case GpioHostOwnershipRegister:
+ RegOffset = GpioGroupInfo[GroupIndex].HostOwnOffset;
+ break;
+ case GpioGpeEnableRegister:
+ RegOffset = GpioGroupInfo[GroupIndex].GpiGpeEnOffset;
+ break;
+ case GpioGpeStatusRegister:
+ RegOffset = GpioGroupInfo[GroupIndex].GpiGpeStsOffset;
+ break;
+ case GpioSmiEnableRegister:
+ RegOffset = GpioGroupInfo[GroupIndex].SmiEnOffset;
+ break;
+ case GpioSmiStatusRegister:
+ RegOffset = GpioGroupInfo[GroupIndex].SmiStsOffset;
+ break;
+ case GpioNmiEnableRegister:
+ RegOffset = GpioGroupInfo[GroupIndex].NmiEnOffset;
+ break;
+ case GpioPadConfigLockRegister:
+ RegOffset = GpioGroupInfo[GroupIndex].PadCfgLockOffset;
+ break;
+ case GpioPadLockOutputRegister:
+ RegOffset = GpioGroupInfo[GroupIndex].PadCfgLockTxOffset;
+ break;
+ default:
+ break;
+ }
+
+ //
+ // Check if selected register exists
+ //
+ if (RegOffset == NO_REGISTER_FOR_PROPERTY) {
+ return EFI_UNSUPPORTED;
+ }
+
+ //
+ // If there are more then 32 pads per group then certain
+ // group information would be split into more then one DWord register.
+ //
+ if ((RegType == GpioPadConfigLockRegister) || (RegType == GpioPadLockOutputRegister)) {
+ //
+ // PadConfigLock and OutputLock registers when used for group containing more than 32 pads
+ // are not placed in a continuous way, e.g:
+ // 0x0 - PadConfigLock_DW0
+ // 0x4 - OutputLock_DW0
+ // 0x8 - PadConfigLock_DW1
+ // 0xC - OutputLock_DW1
+ //
+ RegOffset += DwNum * 0x8;
+ } else {
+ RegOffset += DwNum * 0x4;
+ }
+
+ *ReadVal = GpioRegisterAccessRead32 (&GpioGroupInfo[GroupIndex], RegOffset);
+
+ return EFI_SUCCESS;
+}
+
+/**
+ This procedure will write GPIO register
+
+ @param[in] RegType GPIO register type
+ @param[in] Group GPIO group
+ @param[in] DwNum Register number for current group (parameter applicable in accessing whole register).
+ For group which has less then 32 pads per group DwNum must be 0.
+ @param[in] RegAndMask Mask which will be AND'ed with register value
+ @param[in] RegOrMask Mask which will be OR'ed with register value
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_UNSUPPORTED Feature is not supported for this group or pad
+**/
+STATIC
+EFI_STATUS
+GpioWriteReg (
+ IN GPIO_REG RegType,
+ IN GPIO_GROUP Group,
+ IN UINT32 DwNum,
+ IN UINT32 RegAndMask,
+ IN UINT32 RegOrMask
+ )
+{
+ UINT32 RegOffset;
+ UINT32 GroupIndex;
+ CONST GPIO_GROUP_INFO *GpioGroupInfo;
+ UINT32 GpioGroupInfoLength;
+ UINT32 PadCfgLock;
+ BOOLEAN Lockable;
+
+ Lockable = FALSE;
+ PadCfgLock = 0;
+ RegOffset = NO_REGISTER_FOR_PROPERTY;
+ GroupIndex = GpioGetGroupIndexFromGroup (Group);
+
+ GpioGroupInfo = GpioGetGroupInfoTable (&GpioGroupInfoLength);
+
+ switch (RegType) {
+ case GpioHostOwnershipRegister:
+ RegOffset = GpioGroupInfo[GroupIndex].HostOwnOffset;
+ break;
+ case GpioGpeEnableRegister:
+ RegOffset = GpioGroupInfo[GroupIndex].GpiGpeEnOffset;
+ Lockable = TRUE;
+ break;
+ case GpioGpeStatusRegister:
+ RegOffset = GpioGroupInfo[GroupIndex].GpiGpeStsOffset;
+ break;
+ case GpioSmiEnableRegister:
+ RegOffset = GpioGroupInfo[GroupIndex].SmiEnOffset;
+ Lockable = TRUE;
+ break;
+ case GpioSmiStatusRegister:
+ RegOffset = GpioGroupInfo[GroupIndex].SmiStsOffset;
+ break;
+ case GpioNmiEnableRegister:
+ RegOffset = GpioGroupInfo[GroupIndex].NmiEnOffset;
+ Lockable = TRUE;
+ break;
+ case GpioPadConfigLockRegister:
+ case GpioPadLockOutputRegister:
+ default:
+ break;
+ }
+
+ //
+ // Check if selected register exists
+ //
+ if (RegOffset == NO_REGISTER_FOR_PROPERTY) {
+ return EFI_UNSUPPORTED;
+ }
+
+ if (Lockable) {
+ GpioGetPadCfgLockForGroupDw (Group, DwNum, &PadCfgLock);
+ if (PadCfgLock) {
+ //
+ // Check if for pads which are going to be reconfigured lock is set.
+ //
+ if ((~RegAndMask | RegOrMask) & PadCfgLock) {
+ //
+ // Unlock all pads for this Group DW reg for simplicity
+ // even if not all of those pads will have their settings reprogrammed
+ //
+ GpioUnlockPadCfgForGroupDw (Group, DwNum, PadCfgLock);
+ } else {
+ //
+ // No need to perform an unlock as pads which are going to be reconfigured
+ // are not in locked state
+ //
+ PadCfgLock = 0;
+ }
+ }
+ }
+
+ //
+ // If there are more then 32 pads per group then certain
+ // group information would be split into more then one DWord register.
+ //
+ RegOffset += DwNum * 0x4;
+
+ GpioRegisterAccessAndThenOr32 (&GpioGroupInfo[GroupIndex], RegOffset, RegAndMask,RegOrMask);
+
+ if (Lockable && PadCfgLock) {
+ //
+ // Lock previously unlocked pads
+ //
+ GpioLockPadCfgForGroupDw (Group, DwNum, PadCfgLock);
+ }
+
+ return EFI_SUCCESS;
+}
+
+/**
+ This procedure will write GPIO Lock/LockTx register using SBI.
+
+ @param[in] RegType GPIO register (Lock or LockTx)
+ @param[in] Group GPIO group number
+ @param[in] DwNum Register number for current group.
+ For group which has less then 32 pads per group DwNum must be 0.
+ @param[in] LockRegAndMask Mask which will be AND'ed with Lock register value
+ @param[in] LockRegOrMask Mask which will be Or'ed with Lock register value
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_UNSUPPORTED Feature is not supported for this group or pad
+**/
+STATIC
+EFI_STATUS
+GpioWriteLockReg (
+ IN GPIO_REG RegType,
+ IN GPIO_GROUP Group,
+ IN UINT32 DwNum,
+ IN UINT32 LockRegAndMask,
+ IN UINT32 LockRegOrMask
+ )
+{
+ CONST GPIO_GROUP_INFO *GpioGroupInfo;
+ UINT32 GpioGroupInfoLength;
+ UINT32 RegOffset;
+ UINT32 OldLockVal;
+ UINT32 NewLockVal;
+ UINT32 GroupIndex;
+
+ OldLockVal = 0;
+ NewLockVal = 0;
+
+ RegOffset = NO_REGISTER_FOR_PROPERTY;
+ GroupIndex = GpioGetGroupIndexFromGroup (Group);
+
+ GpioGroupInfo = GpioGetGroupInfoTable (&GpioGroupInfoLength);
+
+ switch (RegType) {
+ case GpioPadConfigLockRegister:
+ RegOffset = GpioGroupInfo[GroupIndex].PadCfgLockOffset;
+ GpioGetPadCfgLockForGroupDw (Group, DwNum, &OldLockVal);
+ break;
+ case GpioPadLockOutputRegister:
+ RegOffset = GpioGroupInfo[GroupIndex].PadCfgLockTxOffset;
+ GpioGetPadCfgLockTxForGroupDw (Group, DwNum, &OldLockVal);
+ break;
+ default:
+ break;
+ }
+
+ //
+ // Check if selected register exists
+ //
+ if (RegOffset == NO_REGISTER_FOR_PROPERTY) {
+ return EFI_UNSUPPORTED;
+ }
+
+ NewLockVal = (OldLockVal & LockRegAndMask) | LockRegOrMask;
+
+ return GpioInternalWriteLockRegister (NewLockVal, RegOffset, DwNum, GpioGroupInfo, GroupIndex);
+}
+
+/**
+ This procedure will get Gpio Pad Ownership
+
+ @param[in] GpioPad GPIO pad
+ @param[out] PadOwnVal Value of Pad Ownership
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid group or pad number
+**/
+EFI_STATUS
+GpioGetPadOwnership (
+ IN GPIO_PAD GpioPad,
+ OUT GPIO_PAD_OWN *PadOwnVal
+ )
+{
+ UINT32 Mask;
+ UINT32 RegOffset;
+ UINT32 GroupIndex;
+ UINT32 PadNumber;
+ CONST GPIO_GROUP_INFO *GpioGroupInfo;
+ UINT32 GpioGroupInfoLength;
+ UINT32 PadOwnRegValue;
+
+ if (!GpioIsPadValid (GpioPad)) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ GroupIndex = GpioGetGroupIndexFromGpioPad (GpioPad);
+ PadNumber = GpioGetPadNumberFromGpioPad (GpioPad);
+
+ GpioGroupInfo = GpioGetGroupInfoTable (&GpioGroupInfoLength);
+
+ //
+ // Check if selected register exists
+ //
+ if (GpioGroupInfo[GroupIndex].PadOwnOffset == NO_REGISTER_FOR_PROPERTY) {
+ *PadOwnVal = GpioPadOwnHost;
+ return EFI_UNSUPPORTED;
+ }
+ //
+ // Calculate RegOffset using Pad Ownership offset and GPIO Pad number.
+ // One DWord register contains information for 8 pads.
+ //
+ RegOffset = GpioGroupInfo[GroupIndex].PadOwnOffset + (PadNumber >> 3) * 0x4;
+
+ //
+ // Calculate pad bit position within DWord register
+ //
+ PadNumber %= 8;
+ Mask = (BIT1 | BIT0) << (PadNumber * 4);
+
+ PadOwnRegValue = GpioRegisterAccessRead32 (&GpioGroupInfo[GroupIndex], RegOffset);
+
+ *PadOwnVal = (GPIO_PAD_OWN) ((PadOwnRegValue & Mask) >> (PadNumber * 4));
+
+ return EFI_SUCCESS;
+}
+
+/**
+ This procedure will check state of Pad Config Lock for pads within one group
+
+ @param[in] Group GPIO group
+ @param[in] DwNum PadCfgLock register number for current group.
+ For group which has less then 32 pads per group DwNum must be 0.
+ @param[out] PadCfgLockRegVal Value of PadCfgLock register
+ Bit position - PadNumber
+ Bit value - 0: NotLocked, 1: Locked
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid group or DwNum parameter number
+**/
+EFI_STATUS
+GpioGetPadCfgLockForGroupDw (
+ IN GPIO_GROUP Group,
+ IN UINT32 DwNum,
+ OUT UINT32 *PadCfgLockRegVal
+ )
+{
+ if (!GpioIsGroupAndDwNumValid (Group, DwNum)) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ return GpioReadReg (
+ GpioPadConfigLockRegister,
+ Group,
+ DwNum,
+ PadCfgLockRegVal
+ );
+}
+/**
+ This procedure will check state of Pad Config Tx Lock for pads within one group
+
+ @param[in] Group GPIO group
+ @param[in] DwNum PadCfgLockTx register number for current group.
+ For group which has less then 32 pads per group DwNum must be 0.
+ @param[out] PadCfgLockTxRegVal Value of PadCfgLockTx register
+ Bit position - PadNumber
+ Bit value - 0: NotLockedTx, 1: LockedTx
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid group or DwNum parameter number
+**/
+EFI_STATUS
+GpioGetPadCfgLockTxForGroupDw (
+ IN GPIO_GROUP Group,
+ IN UINT32 DwNum,
+ OUT UINT32 *PadCfgLockTxRegVal
+ )
+{
+ if (!GpioIsGroupAndDwNumValid (Group, DwNum)) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ return GpioReadReg (
+ GpioPadLockOutputRegister,
+ Group,
+ DwNum,
+ PadCfgLockTxRegVal
+ );
+}
+/**
+ This procedure will clear PadCfgLock for selected pads within one group.
+ This function should be used only inside SMI.
+
+ @param[in] Group GPIO group
+ @param[in] DwNum PadCfgLock register number for current group.
+ For group which has less then 32 pads per group DwNum must be 0.
+ @param[in] PadsToUnlock Bitmask for pads which are going to be unlocked,
+ Bit position - PadNumber
+ Bit value - 0: DoNotUnlock, 1: Unlock
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid group or pad number
+**/
+EFI_STATUS
+GpioUnlockPadCfgForGroupDw (
+ IN GPIO_GROUP Group,
+ IN UINT32 DwNum,
+ IN UINT32 PadsToUnlock
+ )
+{
+ if (!GpioIsGroupAndDwNumValid (Group, DwNum)) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ return GpioWriteLockReg (
+ GpioPadConfigLockRegister,
+ Group,
+ DwNum,
+ ~PadsToUnlock,
+ 0
+ );
+}
+/**
+ This procedure will clear PadCfgLockTx for selected pads within one group.
+ This function should be used only inside SMI.
+
+ @param[in] Group GPIO group
+ @param[in] DwNum PadCfgLockTx register number for current group.
+ For group which has less then 32 pads per group DwNum must be 0.
+ @param[in] PadsToUnlockTx Bitmask for pads which are going to be unlocked,
+ Bit position - PadNumber
+ Bit value - 0: DoNotUnLockTx, 1: LockTx
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid group or pad number
+**/
+EFI_STATUS
+GpioUnlockPadCfgTxForGroupDw (
+ IN GPIO_GROUP Group,
+ IN UINT32 DwNum,
+ IN UINT32 PadsToUnlockTx
+ )
+{
+ if (!GpioIsGroupAndDwNumValid (Group, DwNum)) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ return GpioWriteLockReg (
+ GpioPadLockOutputRegister,
+ Group,
+ DwNum,
+ ~PadsToUnlockTx,
+ 0
+ );
+}
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/Library/PeiDxeSmmGpioLib/GpioLibrary.h b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/Library/PeiDxeSmmGpioLib/GpioLibrary.h
new file mode 100644
index 0000000000..2c2b4ee75c
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/Library/PeiDxeSmmGpioLib/GpioLibrary.h
@@ -0,0 +1,29 @@
+/** @file
+ Header file for GPIO Lib implementation.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _GPIO_LIBRARY_H_
+#define _GPIO_LIBRARY_H_
+
+#include <Base.h>
+#include <Uefi/UefiBaseType.h>
+#include <Library/IoLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/GpioLib.h>
+#include <Library/GpioNativeLib.h>
+#include <Library/GpioPrivateLib.h>
+#include <Library/PchInfoLib.h>
+#include <Library/PchCycleDecodingLib.h>
+#include <Library/PmcPrivateLib.h>
+#include <Library/GpioHelpersLib.h>
+#include <Register/GpioRegs.h>
+
+//
+// Number of PADCFG_DW registers
+//
+#define GPIO_PADCFG_DW_REG_NUMBER 4
+
+#endif // _GPIO_LIBRARY_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/Library/PeiDxeSmmGpioLib/GpioNativeLib.c b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/Library/PeiDxeSmmGpioLib/GpioNativeLib.c
new file mode 100644
index 0000000000..4e4c53e588
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/Library/PeiDxeSmmGpioLib/GpioNativeLib.c
@@ -0,0 +1,177 @@
+/** @file
+ This file contains routines for GPIO native and chipset specific usage
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#include "GpioLibrary.h"
+
+/**
+ This procedure will get number of pads for certain GPIO group
+
+ @param[in] Group GPIO group number
+
+ @retval Value Pad number for group
+ If illegal group number then return 0
+**/
+UINT32
+GpioGetPadPerGroup (
+ IN GPIO_GROUP Group
+ )
+{
+ CONST GPIO_GROUP_INFO *GpioGroupInfo;
+ UINT32 GpioGroupInfoLength;
+ UINT32 GroupIndex;
+ //
+ // Check if group argument exceeds GPIO GROUP INFO array
+ //
+ GpioGroupInfo = GpioGetGroupInfoTable (&GpioGroupInfoLength);
+ GroupIndex = GpioGetGroupIndexFromGroup (Group);
+
+ if ((UINTN) GroupIndex >= GpioGroupInfoLength) {
+ return 0;
+ } else {
+ return GpioGroupInfo[GroupIndex].PadPerGroup;
+ }
+}
+
+/**
+ This procedure will get number of groups
+
+ @param[in] none
+
+ @retval Value Group number
+**/
+UINT32
+GpioGetNumberOfGroups (
+ VOID
+ )
+{
+ UINT32 GpioGroupInfoLength;
+
+ GpioGetGroupInfoTable (&GpioGroupInfoLength);
+ return GpioGroupInfoLength;
+}
+/**
+ This procedure will get lowest group
+
+ @param[in] none
+
+ @retval Value Lowest Group
+**/
+GPIO_GROUP
+GpioGetLowestGroup (
+ VOID
+ )
+{
+ return GpioGetGroupFromGroupIndex (0);
+}
+/**
+ This procedure will get highest group
+
+ @param[in] none
+
+ @retval Value Highest Group
+**/
+GPIO_GROUP
+GpioGetHighestGroup (
+ VOID
+ )
+{
+ return GpioGetGroupFromGroupIndex (GpioGetNumberOfGroups () - 1);
+}
+
+/**
+ This procedure will get group number
+
+ @param[in] GpioPad Gpio Pad
+
+ @retval Value Group number
+**/
+GPIO_GROUP
+GpioGetGroupFromGpioPad (
+ IN GPIO_PAD GpioPad
+ )
+{
+ return GPIO_GET_GROUP_FROM_PAD (GpioPad);
+}
+
+/**
+ This procedure will get group index (0 based)
+
+ @param[in] GpioPad Gpio Pad
+
+ @retval Value Group Index
+**/
+UINT32
+GpioGetGroupIndexFromGpioPad (
+ IN GPIO_PAD GpioPad
+ )
+{
+ return (UINT32) GPIO_GET_GROUP_INDEX_FROM_PAD (GpioPad);
+}
+
+/**
+ This procedure will get group index (0 based) from group
+
+ @param[in] GpioGroup Gpio Group
+
+ @retval Value Group Index
+**/
+UINT32
+GpioGetGroupIndexFromGroup (
+ IN GPIO_GROUP GpioGroup
+ )
+{
+ return (UINT32) GPIO_GET_GROUP_INDEX (GpioGroup);
+}
+
+/**
+ This procedure will get group from group index (0 based)
+
+ @param[in] GroupIndex Group Index
+
+ @retval GpioGroup Gpio Group
+**/
+GPIO_GROUP
+GpioGetGroupFromGroupIndex (
+ IN UINT32 GroupIndex
+ )
+{
+ return GPIO_GROUP_DEF (GroupIndex, GpioGetThisChipsetId ());
+}
+
+/**
+ This procedure will get pad number (0 based) from Gpio Pad
+
+ @param[in] GpioPad Gpio Pad
+
+ @retval Value Pad Number
+**/
+UINT32
+GpioGetPadNumberFromGpioPad (
+ IN GPIO_PAD GpioPad
+ )
+{
+ return (UINT32) GPIO_GET_PAD_NUMBER (GpioPad);
+}
+/**
+ This procedure will return GpioPad from Group and PadNumber
+
+ @param[in] Group GPIO group
+ @param[in] PadNumber GPIO PadNumber
+
+ @retval GpioPad GpioPad
+**/
+GPIO_PAD
+GpioGetGpioPadFromGroupAndPadNumber (
+ IN GPIO_GROUP Group,
+ IN UINT32 PadNumber
+ )
+{
+ if (IsPchLp ()) {
+ return GPIO_PAD_DEF (Group,PadNumber);
+ } else {
+ return GPIO_PAD_DEF (Group,PadNumber);
+ }
+}
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/Library/PeiDxeSmmGpioLib/PeiDxeSmmGpioLib.inf b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/Library/PeiDxeSmmGpioLib/PeiDxeSmmGpioLib.inf
new file mode 100644
index 0000000000..21fb4417c1
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/Library/PeiDxeSmmGpioLib/PeiDxeSmmGpioLib.inf
@@ -0,0 +1,44 @@
+## @file
+# Component description file for the PeiDxeSmmGpioLib
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+
+[Defines]
+INF_VERSION = 0x00010017
+BASE_NAME = PeiDxeSmmGpioLib
+FILE_GUID = 16EC5CA8-8195-4847-B6CB-662BD7B763F2
+VERSION_STRING = 1.0
+MODULE_TYPE = BASE
+LIBRARY_CLASS = GpioLib
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = IA32 X64 IPF EBC
+#
+
+
+
+[LibraryClasses]
+BaseLib
+IoLib
+DebugLib
+PrintLib
+PchCycleDecodingLib
+PchSbiAccessLib
+PmcPrivateLib
+GpioPrivateLib
+GpioHelpersLib
+
+[Packages]
+MdePkg/MdePkg.dec
+AlderlakeSiliconPkg/SiPkg.dec
+
+
+[Sources]
+GpioLib.c
+GpioNativeLib.c
+GpioInit.c
+GpioLibrary.h
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/BaseGpioHelpersLibNull/BaseGpioHelpersLibNull.c b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/BaseGpioHelpersLibNull/BaseGpioHelpersLibNull.c
new file mode 100644
index 0000000000..b4b6c14329
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/BaseGpioHelpersLibNull/BaseGpioHelpersLibNull.c
@@ -0,0 +1,51 @@
+/** @file
+ This file contains NULL implementation for GPIO Helpers Lib
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#include <Uefi/UefiBaseType.h>
+#include <Library/GpioConfig.h>
+
+/**
+ This procedure stores GPIO group data about pads which PadConfig needs to be unlocked.
+
+ @param[in] GroupIndex GPIO group index
+ @param[in] DwNum DWORD index for a group.
+ For group which has less then 32 pads per group DwNum must be 0.
+ @param[in] UnlockedPads DWORD bitmask for pads which are going to be left unlocked
+ Bit position - PadNumber
+ Bit value - 0: Skip, 1: Leave unlocked
+
+ @retval Status
+**/
+EFI_STATUS
+GpioStoreGroupDwUnlockPadConfigData (
+ IN UINT32 GroupIndex,
+ IN UINT32 DwNum,
+ IN UINT32 UnlockedPads
+ )
+{
+ return EFI_SUCCESS;
+}
+
+/**
+ This procedure stores GPIO group data about pads which Output state needs to be unlocked.
+
+ @param[in] GroupIndex GPIO group index
+ @param[in] DwNum DWORD index for a group.
+ For group which has less then 32 pads per group DwNum must be 0.
+ @param[in] UnlockedPads DWORD bitmask for pads which are going to be left unlocked
+ Bit position - PadNumber
+ Bit value - 0: Skip, 1: Leave unlocked
+ @retval Status
+**/
+EFI_STATUS
+GpioStoreGroupDwUnlockOutputData (
+ IN UINT32 GroupIndex,
+ IN UINT32 DwNum,
+ IN UINT32 UnlockedPads
+ )
+{
+ return EFI_SUCCESS;
+}
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/BaseGpioHelpersLibNull/BaseGpioHelpersLibNull.inf b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/BaseGpioHelpersLibNull/BaseGpioHelpersLibNull.inf
new file mode 100644
index 0000000000..91d81af4b9
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/BaseGpioHelpersLibNull/BaseGpioHelpersLibNull.inf
@@ -0,0 +1,25 @@
+## @file
+# Component description file for the NULL GpioHelpersLib
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+
+[Defines]
+INF_VERSION = 0x00010017
+BASE_NAME = BaseGpioHelpersLib
+FILE_GUID = AB282608-2A50-4AE3-9242-64064ECF40D4
+VERSION_STRING = 1.0
+MODULE_TYPE = BASE
+LIBRARY_CLASS = GpioHelpersLib
+
+
+[Packages]
+MdePkg/MdePkg.dec
+AlderlakeSiliconPkg/SiPkg.dec
+
+
+[Sources]
+BaseGpioHelpersLibNull.c
+
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiDxeSmmGpioPrivateLib/GpioNativePrivateLibInternal.h b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiDxeSmmGpioPrivateLib/GpioNativePrivateLibInternal.h
new file mode 100644
index 0000000000..480990cb62
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiDxeSmmGpioPrivateLib/GpioNativePrivateLibInternal.h
@@ -0,0 +1,48 @@
+/** @file
+ Header file for GPIO Private Lib Internal functions.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _GPIO_NATIVE_PRIVATE_LIB_INTERNAL_H_
+#define _GPIO_NATIVE_PRIVATE_LIB_INTERNAL_H_
+
+#include <Library/GpioPrivateLib.h>
+
+
+/**
+ This function provides recommended GPIO IO Standby configuration for a given native function
+
+ @param[in] PadFunction PadFunction for a specific native signal. Please refer to GpioNativePads.h
+ @param[out] StandbyState IO Standby State for specified native function
+ @param[out] StandbyTerm IO Standby Termination for specified native function
+
+ @retval Status
+**/
+EFI_STATUS
+GpioGetFunctionIoStandbyConfig (
+ IN UINT32 PadFunction,
+ OUT GPIO_IOSTANDBY_STATE *StandbyState,
+ OUT GPIO_IOSTANDBY_TERM *StandbyTerm
+ );
+
+/**
+ This procedure will calculate PADCFG register value based on GpioConfig data
+ For physical/local/hard (not virtual) GPIO pads
+
+ @param[in] GpioPad GPIO Pad
+ @param[in] GpioConfig GPIO Configuration data
+ @param[out] PadCfgDwReg PADCFG DWx register value
+ @param[out] PadCfgDwRegMask Mask with PADCFG DWx register bits to be modified
+
+ @retval Status
+**/
+EFI_STATUS
+GpioPadCfgRegValueFromGpioConfigHardGpio (
+ IN GPIO_PAD GpioPad,
+ IN CONST GPIO_CONFIG *GpioConfig,
+ OUT UINT32 *PadCfgDwReg,
+ OUT UINT32 *PadCfgDwRegMask
+ );
+
+#endif // _GPIO_NATIVE_PRIVATE_LIB_INTERNAL_H_
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiDxeSmmGpioPrivateLib/GpioPrivateLib.c b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiDxeSmmGpioPrivateLib/GpioPrivateLib.c
new file mode 100644
index 0000000000..7d5fa9fafd
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiDxeSmmGpioPrivateLib/GpioPrivateLib.c
@@ -0,0 +1,267 @@
+/** @file
+ This file contains GPIO routines for RC usage
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#include <Base.h>
+#include <Uefi/UefiBaseType.h>
+#include <Library/IoLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/GpioLib.h>
+#include <Library/GpioNativeLib.h>
+#include <Library/GpioPrivateLib.h>
+#include <Library/GpioNativePads.h>
+#include <Register/GpioRegs.h>
+#include "GpioNativePrivateLibInternal.h"
+
+/**
+ This procedure is used to check if GpioPad is valid for certain chipset
+
+ @param[in] GpioPad GPIO pad
+
+ @retval TRUE This pin is valid on this chipset
+ FALSE Incorrect pin
+**/
+BOOLEAN
+GpioIsCorrectPadForThisChipset (
+ IN GPIO_PAD GpioPad
+ )
+{
+ return ((GPIO_GET_CHIPSET_ID (GpioPad) == GpioGetThisChipsetId ()) &&
+ (GpioGetGroupIndexFromGpioPad (GpioPad) < GpioGetNumberOfGroups ()));
+}
+
+/**
+ This procedure is used by PchSmiDispatcher and will return information
+ needed to register GPI SMI.
+
+ @param[in] Index GPI SMI number
+ @param[out] GpioPin GPIO pin
+ @param[out] GpiSmiBitOffset GPI SMI bit position within GpiSmi Registers
+ @param[out] GpiHostSwOwnRegAddress Address of HOSTSW_OWN register
+ @param[out] GpiSmiStsRegAddress Address of GPI SMI status register
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid group or pad number
+**/
+EFI_STATUS
+GpioGetPadAndSmiRegs (
+ IN UINT32 Index,
+ OUT GPIO_PAD *GpioPin,
+ OUT UINT8 *GpiSmiBitOffset,
+ OUT UINT32 *GpiHostSwOwnRegAddress,
+ OUT UINT32 *GpiSmiStsRegAddress
+ )
+{
+ UINT32 GroupIndex;
+ UINT32 PadNumber;
+ CONST GPIO_GROUP_INFO *GpioGroupInfo;
+ GPIO_GROUP GpioGroup;
+ UINT32 GpioGroupInfoLength;
+ UINT32 SmiStsRegOffset;
+ UINT32 HostSwOwnRegOffset;
+ GPIO_PAD_OWN PadOwnVal;
+
+ GpioGroupInfo = GpioGetGroupInfoTable (&GpioGroupInfoLength);
+
+ PadNumber = 0;
+ GroupIndex = 0;
+ for (GroupIndex = 0; GroupIndex < GpioGroupInfoLength; GroupIndex++) {
+ PadNumber = Index;
+ if (PadNumber < GpioGroupInfo[GroupIndex].PadPerGroup) {
+ //
+ // Found group and pad number
+ //
+ break;
+ }
+ Index = Index - GpioGroupInfo[GroupIndex].PadPerGroup;
+ }
+
+ //
+ // Check if legal pad number
+ //
+ if (PadNumber >= GpioGroupInfo[GroupIndex].PadPerGroup){
+ return EFI_INVALID_PARAMETER;
+ }
+
+ //
+ // Check if selected group has GPI SMI Enable and Status registers
+ //
+ if (GpioGroupInfo[GroupIndex].SmiEnOffset == NO_REGISTER_FOR_PROPERTY) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ GpioGroup = GpioGetGroupFromGroupIndex (GroupIndex);
+ *GpioPin = GpioGetGpioPadFromGroupAndPadNumber (GpioGroup, PadNumber);
+
+ DEBUG_CODE_BEGIN ();
+ //
+ // Check if selected GPIO Pad is not owned by CSME/ISH/IE
+ //
+ GpioGetPadOwnership (*GpioPin, &PadOwnVal);
+ if (PadOwnVal != GpioPadOwnHost) {
+ DEBUG ((DEBUG_ERROR, "GPIO ERROR: GPIO not owned by host!\n"));
+ return EFI_INVALID_PARAMETER;
+ }
+ DEBUG_CODE_END ();
+
+ *GpiSmiBitOffset = (UINT8)(PadNumber % 32);
+
+ HostSwOwnRegOffset = GpioGroupInfo[GroupIndex].HostOwnOffset + (PadNumber / 32) * 0x4;
+ *GpiHostSwOwnRegAddress = PCH_PCR_ADDRESS (GpioGroupInfo[GroupIndex].Community, HostSwOwnRegOffset);
+
+ SmiStsRegOffset = GpioGroupInfo[GroupIndex].SmiStsOffset + (PadNumber / 32) * 0x4;
+ *GpiSmiStsRegAddress = PCH_PCR_ADDRESS (GpioGroupInfo[GroupIndex].Community, SmiStsRegOffset);
+
+ return EFI_SUCCESS;
+}
+
+/**
+ This procedure will check if GpioPad argument is valid.
+ Function will check below conditions:
+ - GpioPad represents a pad for current PCH
+ - GpioPad belongs to valid GpioGroup
+ - GPIO PadNumber is not greater than number of pads for this group
+
+ @param[in] GpioPad GPIO pad
+
+ @retval TRUE GPIO pad is valid and can be used with GPIO lib API
+ @retval FALSE GPIO pad is invalid and cannot be used with GPIO lib API
+**/
+BOOLEAN
+GpioIsPadValid (
+ IN GPIO_PAD GpioPad
+ )
+{
+ CONST GPIO_GROUP_INFO *GpioGroupInfo;
+ UINT32 GpioGroupInfoLength;
+ UINT32 PadNumber;
+ UINT32 GroupIndex;
+
+ if (!GpioIsCorrectPadForThisChipset (GpioPad)) {
+ DEBUG ((DEBUG_ERROR, "GPIO ERROR: Incorrect GpioPad (0x%08x) used on this chipset!\n", GpioPad));
+ goto Error;
+ }
+
+ GpioGroupInfo = GpioGetGroupInfoTable (&GpioGroupInfoLength);
+
+ //
+ // Check if legal pin number
+ //
+ GroupIndex = GpioGetGroupIndexFromGpioPad (GpioPad);
+ PadNumber = GpioGetPadNumberFromGpioPad (GpioPad);
+ if (PadNumber >= GpioGroupInfo[GroupIndex].PadPerGroup) {
+ DEBUG ((DEBUG_ERROR, "GPIO ERROR: Pin number (%d) exceeds range of group (max: %d)\n",
+ PadNumber,
+ GpioGroupInfo[GroupIndex].PadPerGroup));
+ goto Error;
+ }
+
+ return TRUE;
+Error:
+ ASSERT (FALSE);
+ return FALSE;
+}
+
+/**
+ This procedure will read GPIO Pad Configuration register
+
+ @param[in] GpioPad GPIO pad
+ @param[in] DwReg Choose PADCFG register: 0:DW0, 1:DW1
+
+ @retval PadCfgRegValue PADCFG_DWx value
+**/
+UINT32
+GpioReadPadCfgReg (
+ IN GPIO_PAD GpioPad,
+ IN UINT8 DwReg
+ )
+{
+ UINT32 PadCfgReg;
+ CONST GPIO_GROUP_INFO *GpioGroupInfo;
+ UINT32 GpioGroupInfoLength;
+ UINT32 GroupIndex;
+
+ GroupIndex = GpioGetGroupIndexFromGpioPad (GpioPad);
+ GpioGroupInfo = GpioGetGroupInfoTable (&GpioGroupInfoLength);
+
+ //
+ // Create Pad Configuration register offset
+ //
+ PadCfgReg = GpioGetGpioPadCfgAddressFromGpioPad (GpioPad, DwReg);
+ return GpioRegisterAccessRead32 (&GpioGroupInfo[GroupIndex], PadCfgReg);
+}
+
+
+/**
+ This procedure will calculate PADCFG register value based on GpioConfig data
+ For physical/local/hard (not virtual) GPIO pads
+
+ @param[in] GpioPad GPIO Pad
+ @param[in] GpioConfig GPIO Configuration data
+ @param[out] PadCfgDwReg PADCFG DWx register value
+ @param[out] PadCfgDwRegMask Mask with PADCFG DWx register bits to be modified
+
+ @retval Status
+**/
+EFI_STATUS
+GpioPadCfgRegValueFromGpioConfigHardGpio (
+ IN GPIO_PAD GpioPad,
+ IN CONST GPIO_CONFIG *GpioConfig,
+ OUT UINT32 *PadCfgDwReg,
+ OUT UINT32 *PadCfgDwRegMask
+ )
+{
+ //
+ // Configure how interrupt is triggered (RxEvCfg)
+ //
+ PadCfgDwRegMask[0] |= ((((GpioConfig->InterruptConfig & B_GPIO_INT_CONFIG_INT_TYPE_MASK) >> N_GPIO_INT_CONFIG_INT_TYPE_BIT_POS) == GpioHardwareDefault) ? 0x0 : B_GPIO_PCR_RX_LVL_EDG);
+ PadCfgDwReg[0] |= (((GpioConfig->InterruptConfig & B_GPIO_INT_CONFIG_INT_TYPE_MASK) >> (N_GPIO_INT_CONFIG_INT_TYPE_BIT_POS + 1)) << N_GPIO_PCR_RX_LVL_EDG);
+
+ //
+ // Configure interrupt generation (GPIRoutIOxAPIC/SCI/SMI/NMI)
+ //
+ PadCfgDwRegMask[0] |= ((((GpioConfig->InterruptConfig & B_GPIO_INT_CONFIG_INT_SOURCE_MASK) >> N_GPIO_INT_CONFIG_INT_SOURCE_BIT_POS) == GpioHardwareDefault) ? 0x0 : (B_GPIO_PCR_RX_NMI_ROUTE | B_GPIO_PCR_RX_SCI_ROUTE | B_GPIO_PCR_RX_SMI_ROUTE | B_GPIO_PCR_RX_APIC_ROUTE));
+ PadCfgDwReg[0] |= (((GpioConfig->InterruptConfig & B_GPIO_INT_CONFIG_INT_SOURCE_MASK) >> (N_GPIO_INT_CONFIG_INT_SOURCE_BIT_POS + 1)) << N_GPIO_PCR_RX_NMI_ROUTE);
+
+ //
+ // Configure GPIO direction (GPIORxDis and GPIOTxDis)
+ //
+ PadCfgDwRegMask[0] |= ((((GpioConfig->Direction & B_GPIO_DIRECTION_DIR_MASK) >> N_GPIO_DIRECTION_DIR_BIT_POS) == GpioHardwareDefault) ? 0x0 : (B_GPIO_PCR_RXDIS | B_GPIO_PCR_TXDIS));
+ PadCfgDwReg[0] |= (((GpioConfig->Direction & B_GPIO_DIRECTION_DIR_MASK) >> (N_GPIO_DIRECTION_DIR_BIT_POS + 1)) << N_GPIO_PCR_TXDIS);
+
+ //
+ // Configure GPIO input inversion (RXINV)
+ //
+ PadCfgDwRegMask[0] |= ((((GpioConfig->Direction & B_GPIO_DIRECTION_INV_MASK) >> N_GPIO_DIRECTION_INV_BIT_POS) == GpioHardwareDefault) ? 0x0 : B_GPIO_PCR_RXINV);
+ PadCfgDwReg[0] |= (((GpioConfig->Direction & B_GPIO_DIRECTION_INV_MASK) >> (N_GPIO_DIRECTION_INV_BIT_POS + 1)) << N_GPIO_PCR_RXINV);
+
+ //
+ // Configure GPIO output state (GPIOTxState)
+ //
+ PadCfgDwRegMask[0] |= ((((GpioConfig->OutputState & B_GPIO_OUTPUT_MASK) >> N_GPIO_OUTPUT_BIT_POS) == GpioHardwareDefault) ? 0x0 : B_GPIO_PCR_TX_STATE);
+ PadCfgDwReg[0] |= (((GpioConfig->OutputState & B_GPIO_OUTPUT_MASK) >> (N_GPIO_OUTPUT_BIT_POS + 1)) << N_GPIO_PCR_TX_STATE);
+
+ //
+ // Configure GPIO RX raw override to '1' (RXRAW1)
+ //
+ PadCfgDwRegMask[0] |= ((((GpioConfig->OtherSettings & B_GPIO_OTHER_CONFIG_RXRAW_MASK) >> N_GPIO_OTHER_CONFIG_RXRAW_BIT_POS) == GpioHardwareDefault) ? 0x0 : B_GPIO_PCR_RX_RAW1);
+ PadCfgDwReg[0] |= (((GpioConfig->OtherSettings & B_GPIO_OTHER_CONFIG_RXRAW_MASK) >> (N_GPIO_OTHER_CONFIG_RXRAW_BIT_POS + 1)) << N_GPIO_PCR_RX_RAW1);
+
+ //
+ // Configure GPIO Pad Mode (PMode)
+ //
+ PadCfgDwRegMask[0] |= ((((GpioConfig->PadMode & B_GPIO_PAD_MODE_MASK) >> N_GPIO_PAD_MODE_BIT_POS) == GpioHardwareDefault) ? 0x0 : B_GPIO_PCR_PAD_MODE);
+ PadCfgDwReg[0] |= (((GpioConfig->PadMode & B_GPIO_PAD_MODE_MASK) >> (N_GPIO_PAD_MODE_BIT_POS + 1)) << N_GPIO_PCR_PAD_MODE);
+
+ //
+ // Configure GPIO termination (Term)
+ //
+ PadCfgDwRegMask[1] |= ((((GpioConfig->ElectricalConfig & B_GPIO_ELECTRICAL_CONFIG_TERMINATION_MASK) >> N_GPIO_ELECTRICAL_CONFIG_TERMINATION_BIT_POS) == GpioHardwareDefault) ? 0x0 : B_GPIO_PCR_TERM);
+ PadCfgDwReg[1] |= (((GpioConfig->ElectricalConfig & B_GPIO_ELECTRICAL_CONFIG_TERMINATION_MASK) >> (N_GPIO_ELECTRICAL_CONFIG_TERMINATION_BIT_POS + 1)) << N_GPIO_PCR_TERM);
+
+ return EFI_SUCCESS;
+}
+
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiDxeSmmGpioPrivateLib/GpioPrivateLibPch.c b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiDxeSmmGpioPrivateLib/GpioPrivateLibPch.c
new file mode 100644
index 0000000000..3d16fd2acd
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiDxeSmmGpioPrivateLib/GpioPrivateLibPch.c
@@ -0,0 +1,172 @@
+/** @file
+ This file contains hard/physical/local (not virtual) GPIO information
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#include <Uefi/UefiBaseType.h>
+#include <Library/GpioLib.h>
+#include <Library/GpioPrivateLib.h>
+#include <Library/GpioNativeLib.h>
+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+#include <Library/PchSbiAccessLib.h>
+#include <Register/GpioRegs.h>
+#include "GpioNativePrivateLibInternal.h"
+
+/**
+ This procedure calculates Pad Configuration Register DW offset
+
+ @param[in] GpioPad GPIO pad
+ @param[in] DwReg Index of the configuration register
+
+ @retval DW Register offset
+**/
+UINT32
+GpioGetGpioPadCfgAddressFromGpioPad (
+ IN GPIO_PAD GpioPad,
+ IN UINT32 DwReg
+ )
+{
+ UINT32 PadCfgRegAddress;
+ CONST GPIO_GROUP_INFO *GpioGroupInfo;
+ UINT32 GpioGroupInfoLength;
+ UINT32 GroupIndex;
+ UINT32 PadNumber;
+
+ GroupIndex = GpioGetGroupIndexFromGpioPad (GpioPad);
+ PadNumber = GpioGetPadNumberFromGpioPad (GpioPad);
+
+ GpioGroupInfo = GpioGetGroupInfoTable (&GpioGroupInfoLength);
+
+ //
+ // Create Pad Configuration register offset
+ //
+ PadCfgRegAddress = GpioGroupInfo[GroupIndex].PadCfgOffset + DwReg * 4 + S_GPIO_PCR_PADCFG * PadNumber;
+
+ return PadCfgRegAddress;
+}
+
+/**
+ This procedure reads GPIO register
+
+ @param[in] GpioGroupInfo Pointer to GPIO group table info
+ @param[in] Register Register offset
+
+ @retval Register value or "F"s in case of errors
+**/
+UINT32
+GpioRegisterAccessRead32 (
+ IN CONST GPIO_GROUP_INFO *GpioGroupInfo,
+ IN UINT32 Register
+ )
+{
+ return MmioRead32 (PCH_PCR_ADDRESS (GpioGroupInfo->Community, Register));
+}
+
+/**
+ This procedure writes GPIO register
+
+ @param[in] GpioGroupInfo Pointer to GPIO group table info
+ @param[in] Register Register offset
+ @param[in] AndValue And value
+ @param[in] OrValue Or value
+
+ @retval EFI_SUCCESS Operation completed successfully
+**/
+EFI_STATUS
+GpioRegisterAccessAndThenOr32 (
+ IN CONST GPIO_GROUP_INFO *GpioGroupInfo,
+ IN UINT32 Register,
+ IN UINT32 AndValue,
+ IN UINT32 OrValue
+ )
+{
+ MmioAndThenOr32 (
+ PCH_PCR_ADDRESS (GpioGroupInfo->Community, Register),
+ AndValue,
+ OrValue
+ );
+ return EFI_SUCCESS;
+}
+
+/**
+ This procedure will calculate PADCFG register value based on GpioConfig data
+
+ @param[in] GpioPad GPIO Pad
+ @param[in] GpioConfig GPIO Configuration data
+ @param[out] PadCfgDwReg PADCFG DWx register value
+ @param[out] PadCfgDwRegMask Mask with PADCFG DWx register bits to be modified
+
+ @retval Status
+**/
+EFI_STATUS
+GpioPadCfgRegValueFromGpioConfig (
+ IN GPIO_PAD GpioPad,
+ IN CONST GPIO_CONFIG *GpioConfig,
+ OUT UINT32 *PadCfgDwReg,
+ OUT UINT32 *PadCfgDwRegMask
+ )
+{
+ return GpioPadCfgRegValueFromGpioConfigHardGpio (GpioPad, GpioConfig, PadCfgDwReg, PadCfgDwRegMask);
+}
+
+/**
+ This procedure will write GPIO Lock/LockTx register
+ - For PCH SBI message is used.
+
+ @param[in] RegValue GPIO register (Lock or LockTx) value
+ @param[in] RegOffset GPIO register (Lock or LockTx) base offset
+ @param[in] DwNum Register number for current group.
+ For group which has less then 32 pads per group DwNum must be 0.
+ @param[in] GpioGroupInfo Pointer to GPIO group table info
+ @param[in] GroupIndex GPIO group index in the GpioGroupInfo table
+
+ @retval EFI_SUCCESS The function completed successfully
+ EFI_UNSUPPORTED Feature is not supported for this group or pad
+**/
+EFI_STATUS
+GpioInternalWriteLockRegister (
+ IN UINT32 RegValue,
+ IN UINT32 RegOffset,
+ IN UINT32 DwNum,
+ IN CONST GPIO_GROUP_INFO *GpioGroupInfo,
+ IN UINT32 GroupIndex
+ )
+{
+ EFI_STATUS Status;
+ PCH_SBI_OPCODE Opcode;
+ UINT8 Response;
+
+ //
+ // If there are more then 32 pads per group then certain
+ // group information would be split into more then one DWord register.
+ // PadConfigLock and OutputLock registers when used for group containing more than 32 pads
+ // are not placed in a continuous way, e.g:
+ // 0x0 - PadConfigLock_DW0
+ // 0x4 - OutputLock_DW0
+ // 0x8 - PadConfigLock_DW1
+ // 0xC - OutputLock_DW1
+ //
+ RegOffset += DwNum * 0x8;
+
+ if (IsGpioLockOpcodeSupported ()) {
+ Opcode = GpioLockUnlock;
+ } else {
+ Opcode = PrivateControlWrite;
+ }
+
+ Status = PchSbiExecutionEx (
+ GpioGroupInfo[GroupIndex].Community,
+ RegOffset,
+ Opcode,
+ FALSE,
+ 0x000F,
+ 0x0000,
+ 0x0000,
+ &RegValue,
+ &Response
+ );
+ ASSERT_EFI_ERROR (Status);
+ return Status;
+}
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiDxeSmmGpioPrivateLib/GpioPrivateLibVer2.c b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiDxeSmmGpioPrivateLib/GpioPrivateLibVer2.c
new file mode 100644
index 0000000000..1348643553
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiDxeSmmGpioPrivateLib/GpioPrivateLibVer2.c
@@ -0,0 +1,81 @@
+/** @file
+ This file contains VER2 specific GPIO information
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#include <Uefi/UefiBaseType.h>
+#include <Library/DebugLib.h>
+#include <Library/PchInfoLib.h>
+#include <Library/GpioLib.h>
+#include <Library/GpioNativeLib.h>
+#include <Library/GpioNativePads.h>
+#include <Library/GpioPrivateLib.h>
+#include <Library/GpioHelpersLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/IoLib.h>
+#include <Register/GpioRegsVer2.h>
+#include <Register/PchPcrRegs.h>
+#include <Register/GpioRegs.h>
+#include <Pins/GpioPinsVer2Lp.h>
+#include <GpioNativePrivateLibInternal.h>
+#include <Library/PcdLib.h>
+GLOBAL_REMOVE_IF_UNREFERENCED GPIO_GROUP_INFO mPchLpGpioGroupInfo[] = {
+ {PID_GPIOCOM0, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_PAD_OWN, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_HOSTSW_OWN, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_GPI_IS, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_GPI_IE, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_GPI_GPE_STS, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_GPI_GPE_EN, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_SMI_STS, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_SMI_EN, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_NMI_STS, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_NMI_EN, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_PADCFGLOCK, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_PADCFGLOCKTX, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_PADCFG_OFFSET, GPIO_VER2_PCH_LP_GPIO_GPP_B_PAD_MAX}, //TGL PCH-LP GPP_B
+ {PID_GPIOCOM0, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, 0},
+ {PID_GPIOCOM0, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_A_PAD_OWN, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_A_HOSTSW_OWN, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_A_GPI_IS, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_A_GPI_IE, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_A_GPI_GPE_STS, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_A_GPI_GPE_EN, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_A_PADCFGLOCK, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_A_PADCFGLOCKTX, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_A_PADCFG_OFFSET, GPIO_VER2_PCH_LP_GPIO_GPP_A_PAD_MAX}, //TGL PCH-LP GPP_A
+ {PID_GPIOCOM5, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_R_PAD_OWN, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_R_HOSTSW_OWN, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_R_GPI_IS, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_R_GPI_IE, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_R_GPI_GPE_STS, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_R_GPI_GPE_EN, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_R_PADCFGLOCK, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_R_PADCFGLOCKTX, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_R_PADCFG_OFFSET, GPIO_VER2_PCH_LP_GPIO_GPP_R_PAD_MAX}, //TGL PCH-LP GPP_R
+ {PID_GPIOCOM5, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, 0},
+ {PID_GPIOCOM2, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPD_PAD_OWN, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPD_HOSTSW_OWN, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPD_GPI_IS, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPD_GPI_IE, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPD_GPI_GPE_STS, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPD_GPI_GPE_EN, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPD_PADCFGLOCK, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPD_PADCFGLOCKTX, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPD_PADCFG_OFFSET, GPIO_VER2_PCH_LP_GPIO_GPD_PAD_MAX}, //TGL PCH-LP GPD
+ {PID_GPIOCOM1, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_S_PAD_OWN, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_S_HOSTSW_OWN, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_S_GPI_IS, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_S_GPI_IE, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_S_GPI_GPE_STS, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_S_GPI_GPE_EN, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_S_PADCFGLOCK, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_S_PADCFGLOCKTX, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_S_PADCFG_OFFSET, GPIO_VER2_PCH_LP_GPIO_GPP_S_PAD_MAX}, //TGL PCH-LP GPP_S
+ {PID_GPIOCOM1, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_H_PAD_OWN, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_H_HOSTSW_OWN, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_H_GPI_IS, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_H_GPI_IE, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_H_GPI_GPE_STS, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_H_GPI_GPE_EN, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_H_PADCFGLOCK, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_H_PADCFGLOCKTX, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_H_PADCFG_OFFSET, GPIO_VER2_PCH_LP_GPIO_GPP_H_PAD_MAX}, //TGL PCH-LP GPP_H
+ {PID_GPIOCOM1, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_PAD_OWN, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_HOSTSW_OWN, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_GPI_IS, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_GPI_IE, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_GPI_GPE_STS, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_GPI_GPE_EN, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_SMI_STS, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_SMI_EN, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_NMI_STS, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_NMI_EN, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_PADCFGLOCK, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_PADCFGLOCKTX, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_PADCFG_OFFSET, GPIO_VER2_PCH_LP_GPIO_GPP_D_PAD_MAX}, //TGL PCH-LP GPP_D
+ {PID_GPIOCOM1, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, 0},
+ {PID_GPIOCOM1, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, 0},
+ {PID_GPIOCOM4, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_PAD_OWN, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_HOSTSW_OWN, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_GPI_IS, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_GPI_IE, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_GPI_GPE_STS, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_GPI_GPE_EN, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_SMI_STS, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_SMI_EN, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_NMI_STS, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_NMI_EN, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_PADCFGLOCK, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_PADCFGLOCKTX, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_PADCFG_OFFSET, GPIO_VER2_PCH_LP_GPIO_GPP_C_PAD_MAX}, //TGL PCH-LP GPP_C
+ {PID_GPIOCOM4, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_F_PAD_OWN, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_F_HOSTSW_OWN, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_F_GPI_IS, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_F_GPI_IE, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_F_GPI_GPE_STS, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_F_GPI_GPE_EN, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_F_PADCFGLOCK, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_F_PADCFGLOCKTX, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_F_PADCFG_OFFSET, GPIO_VER2_PCH_LP_GPIO_GPP_F_PAD_MAX}, //TGL PCH-LP GPP_F
+ {PID_GPIOCOM4, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, 0},
+ {PID_GPIOCOM4, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_PAD_OWN, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_HOSTSW_OWN, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_GPI_IS, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_GPI_IE, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_GPI_GPE_STS, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_GPI_GPE_EN, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_SMI_STS, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_SMI_EN, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_NMI_STS, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_NMI_EN, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_PADCFGLOCK, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_PADCFGLOCKTX, R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_PADCFG_OFFSET, GPIO_VER2_PCH_LP_GPIO_GPP_E_PAD_MAX}, //TGL PCH-LP GPP_E
+};
+
+/**
+ This procedure will retrieve address and length of GPIO info table
+
+ @param[out] GpioGroupInfoTableLength Length of GPIO group table
+
+ @retval Pointer to GPIO group table
+
+**/
+CONST GPIO_GROUP_INFO*
+GpioGetGroupInfoTable (
+ OUT UINT32 *GpioGroupInfoTableLength
+ )
+{
+ *GpioGroupInfoTableLength = ARRAY_SIZE (mPchLpGpioGroupInfo);
+ return mPchLpGpioGroupInfo;
+}
+
+/**
+ Get GPIO Chipset ID specific to PCH generation and series
+**/
+UINT32
+GpioGetThisChipsetId (
+ VOID
+ )
+{
+ return GPIO_VER2_LP_CHIPSET_ID;
+}
+
+/**
+ Check if 0x13 opcode supported for writing to GPIO lock unlock register
+
+ @retval TRUE It's supported
+ @retval FALSE It's not supported
+**/
+BOOLEAN
+IsGpioLockOpcodeSupported (
+ VOID
+ )
+{
+ return TRUE;
+}
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiDxeSmmGpioPrivateLib/PeiDxeSmmGpioPrivateLibVer2.inf b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiDxeSmmGpioPrivateLib/PeiDxeSmmGpioPrivateLibVer2.inf
new file mode 100644
index 0000000000..2e9a6b7336
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiDxeSmmGpioPrivateLib/PeiDxeSmmGpioPrivateLibVer2.inf
@@ -0,0 +1,40 @@
+## @file
+# Component description file for the PeiDxeSmmGpioPrivateLib
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+[Defines]
+INF_VERSION = 0x00010017
+BASE_NAME = PeiDxeSmmGpioPrivateLibVer2
+FILE_GUID = 680A81B0-A087-4687-B5B4-146DA30042D6
+VERSION_STRING = 1.0
+MODULE_TYPE = BASE
+LIBRARY_CLASS = GpioPrivateLib
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = IA32 X64 IPF EBC
+#
+
+
+[LibraryClasses]
+ BaseLib
+ IoLib
+ DebugLib
+ PmcLib
+ PchInfoLib
+ GpioLib
+ GpioHelpersLib
+
+
+[Packages]
+ MdePkg/MdePkg.dec
+ AlderlakeSiliconPkg/SiPkg.dec
+
+
+[Sources]
+ GpioPrivateLib.c
+ GpioPrivateLibVer2.c
+ GpioPrivateLibPch.c
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiGpioHelpersLib/PeiGpioHelpersLib.c b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiGpioHelpersLib/PeiGpioHelpersLib.c
new file mode 100644
index 0000000000..9d47e6bfd5
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiGpioHelpersLib/PeiGpioHelpersLib.c
@@ -0,0 +1,218 @@
+/** @file
+ This file contains routines for PEI GPIO Helpers Lib
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#include <Library/HobLib.h>
+#include <Base.h>
+#include <Uefi/UefiBaseType.h>
+#include <Library/IoLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/GpioNativeLib.h>
+#include <Library/GpioPrivateLib.h>
+#include <Library/GpioHelpersLib.h>
+#include <Library/PeiServicesLib.h>
+#include <Library/ConfigBlockLib.h>
+#include <Ppi/SiPolicy.h>
+
+extern EFI_GUID gGpioLibUnlockHobGuid;
+
+//
+// GPIO Lock HOB
+// Stores information on GPIO pads that should be left unlocked
+//
+typedef struct {
+ //
+ // GPIO PadConfig unlock data
+ //
+ UINT32 PadConfig;
+ //
+ // GPIO Output unlock data
+ //
+ UINT32 OutputState;
+} GPIO_UNLOCK_HOB_DATA;
+
+/**
+ This procedure will get index of GPIO Unlock HOB structure for selected GroupIndex and DwNum.
+
+ @param[in] GroupIndex GPIO group index
+ @param[in] DwNum DWORD index for a group.
+ For group which has less then 32 pads per group DwNum must be 0.
+
+ @retval GpioUnlockHobIndex
+**/
+STATIC
+UINT32
+GpioUnlockDataIndex (
+ IN UINT32 GroupIndex,
+ IN UINT32 DwNum
+ )
+{
+ UINT32 GpioUnlockDataIndex;
+ UINT32 Index;
+
+ GpioUnlockDataIndex = 0;
+
+ for (Index = 0; Index < GroupIndex; Index++) {
+ GpioUnlockDataIndex += GPIO_GET_DW_NUM (GpioGetPadPerGroup (GpioGetGroupFromGroupIndex (Index))) + 1;
+ }
+
+ GpioUnlockDataIndex += DwNum;
+ return GpioUnlockDataIndex;
+}
+
+/**
+ This procedure will create GPIO HOB for storing unlock data
+
+ @retval Pointer to GPIO Unlock data structure
+**/
+STATIC
+GPIO_UNLOCK_HOB_DATA*
+GpioCreateUnlockData (
+ VOID
+ )
+{
+ VOID *HobData;
+ GPIO_GROUP Group;
+ GPIO_GROUP GroupMin;
+ GPIO_GROUP GroupMax;
+ UINT32 GpioUnlockDataRecords;
+
+ GroupMin = GpioGetLowestGroup ();
+ GroupMax = GpioGetHighestGroup ();
+ GpioUnlockDataRecords = 0;
+
+ for (Group = GroupMin; Group <= GroupMax; Group++) {
+ GpioUnlockDataRecords += GPIO_GET_DW_NUM (GpioGetPadPerGroup (Group)) + 1;
+ }
+
+ HobData = BuildGuidHob (&gGpioLibUnlockHobGuid, GpioUnlockDataRecords * sizeof (GPIO_UNLOCK_HOB_DATA));
+ if (HobData == NULL) {
+ return NULL;
+ }
+
+ ZeroMem (HobData, GpioUnlockDataRecords * sizeof (GPIO_UNLOCK_HOB_DATA));
+
+ return (GPIO_UNLOCK_HOB_DATA*)HobData;
+}
+
+/**
+ This procedure will Get GPIO Unlock data structure for storing unlock data.
+ If HOB doesn't exist it will be created.
+
+ @param[out] GpioUnlockData pointer to GPIO Unlock data structure
+
+ @retval Length number of GPIO unlock data records
+**/
+STATIC
+UINT32
+GpioGetUnlockData (
+ GPIO_UNLOCK_HOB_DATA **GpioUnlockData
+ )
+{
+ VOID *Hob;
+
+ Hob = GetFirstGuidHob (&gGpioLibUnlockHobGuid);
+ if (Hob == NULL) {
+ //
+ // It is the first time this function is used so create the HOB
+ //
+ *GpioUnlockData = GpioCreateUnlockData ();
+ if (*GpioUnlockData == NULL) {
+ return 0;
+ }
+ Hob = GetFirstGuidHob (&gGpioLibUnlockHobGuid);
+ } else {
+ *GpioUnlockData = (GPIO_UNLOCK_HOB_DATA*) GET_GUID_HOB_DATA (Hob);
+ }
+ return GET_GUID_HOB_DATA_SIZE (Hob) / sizeof (GPIO_UNLOCK_HOB_DATA);
+}
+
+/**
+ This procedure stores GPIO group data about pads which PadConfig needs to be unlocked.
+
+ @param[in] GroupIndex GPIO group index
+ @param[in] DwNum DWORD index for a group.
+ For group which has less then 32 pads per group DwNum must be 0.
+ @param[in] UnlockedPads DWORD bitmask for pads which are going to be left unlocked
+ Bit position - PadNumber
+ Bit value - 0: Skip, 1: Leave unlocked
+
+ @retval Status
+**/
+EFI_STATUS
+GpioStoreGroupDwUnlockPadConfigData (
+ IN UINT32 GroupIndex,
+ IN UINT32 DwNum,
+ IN UINT32 UnlockedPads
+ )
+{
+ GPIO_UNLOCK_HOB_DATA *GpioUnlockData;
+ UINT32 Length;
+ UINT32 Index;
+
+ if (UnlockedPads == 0) {
+ //
+ // No pads to be left unlocked
+ //
+ return EFI_SUCCESS;
+ }
+
+ Length = GpioGetUnlockData (&GpioUnlockData);
+ if (Length == 0) {
+ return EFI_NOT_FOUND;
+ }
+
+ Index = GpioUnlockDataIndex (GroupIndex, DwNum);
+ if (Index >= Length) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ GpioUnlockData[Index].PadConfig |= UnlockedPads;
+ return EFI_SUCCESS;
+}
+
+/**
+ This procedure stores GPIO group data about pads which Output state needs to be unlocked.
+
+ @param[in] GroupIndex GPIO group index
+ @param[in] DwNum DWORD index for a group.
+ For group which has less then 32 pads per group DwNum must be 0.
+ @param[in] UnlockedPads DWORD bitmask for pads which are going to be left unlocked
+ Bit position - PadNumber
+ Bit value - 0: Skip, 1: Leave unlocked
+ @retval Status
+**/
+EFI_STATUS
+GpioStoreGroupDwUnlockOutputData (
+ IN UINT32 GroupIndex,
+ IN UINT32 DwNum,
+ IN UINT32 UnlockedPads
+ )
+{
+ GPIO_UNLOCK_HOB_DATA *GpioUnlockData;
+ UINT32 Length;
+ UINT32 Index;
+
+ if (UnlockedPads == 0) {
+ //
+ // No pads to be left unlocked
+ //
+ return EFI_SUCCESS;
+ }
+
+ Length = GpioGetUnlockData (&GpioUnlockData);
+ if (Length == 0) {
+ return EFI_NOT_FOUND;
+ }
+
+ Index = GpioUnlockDataIndex (GroupIndex, DwNum);
+ if (Index >= Length) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ GpioUnlockData[Index].OutputState |= UnlockedPads;
+ return EFI_SUCCESS;
+}
diff --git a/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiGpioHelpersLib/PeiGpioHelpersLib.inf b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiGpioHelpersLib/PeiGpioHelpersLib.inf
new file mode 100644
index 0000000000..c1886b22f9
--- /dev/null
+++ b/Silicon/Intel/AlderlakeSiliconPkg/IpBlock/Gpio/LibraryPrivate/PeiGpioHelpersLib/PeiGpioHelpersLib.inf
@@ -0,0 +1,46 @@
+## @file
+# Component description file for the PeiGpioHelpersLib
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+
+[Defines]
+INF_VERSION = 0x00010017
+BASE_NAME = PeiGpioHelpersLib
+FILE_GUID = 1838E1E7-3CC4-4A74-90D9-B421EF2A579F
+VERSION_STRING = 1.0
+MODULE_TYPE = PEIM
+LIBRARY_CLASS = GpioHelpersLib
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = IA32 X64 IPF EBC
+#
+
+
+[LibraryClasses]
+BaseLib
+IoLib
+DebugLib
+HobLib
+GpioLib
+ConfigBlockLib
+PeiServicesLib
+
+
+[Packages]
+MdePkg/MdePkg.dec
+AlderlakeSiliconPkg/SiPkg.dec
+
+
+[Sources]
+PeiGpioHelpersLib.c
+
+
+[Guids]
+gGpioLibUnlockHobGuid
+
+[Ppis]
+gSiPreMemPolicyPpiGuid
--
2.36.1.windows.1
-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#108749): https://edk2.groups.io/g/devel/message/108749
Mute This Topic: https://groups.io/mt/101373944/7686176
Group Owner: devel+owner@edk2.groups.io
Unsubscribe: https://edk2.groups.io/g/devel/unsub [rebecca@openfw.io]
-=-=-=-=-=-=-=-=-=-=-=-
^ permalink raw reply related [flat|nested] 41+ messages in thread
end of thread, other threads:[~2023-09-16 0:26 UTC | newest]
Thread overview: 41+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2023-09-15 4:45 [edk2-devel] [PATCH v2 01/10] AlderlakeSiliconPkg/IpBlock: Add CpuPcieRp, Espi, Gpio components Saloni Kasbekar
2023-09-15 4:45 ` [edk2-devel] [PATCH v2 02/10] AlderlakeSiliconPkg/IpBlock: Add Graphics, HostBridge, PcieRp components Saloni Kasbekar
2023-09-15 5:42 ` Chaganty, Rangasai V
2023-09-15 13:27 ` Chuang, Rosen
2023-09-15 23:56 ` Nate DeSimone
2023-09-15 4:45 ` [edk2-devel] [PATCH v2 03/10] AlderlakeSiliconPkg/IpBlock: Add P2sb, PchDmi components Saloni Kasbekar
2023-09-15 5:42 ` Chaganty, Rangasai V
2023-09-15 13:28 ` Chuang, Rosen
2023-09-15 23:56 ` Nate DeSimone
2023-09-15 4:45 ` [edk2-devel] [PATCH v2 04/10] AlderlakeSiliconPkg/IpBlock: Add Pmc, Spi components Saloni Kasbekar
2023-09-15 5:42 ` Chaganty, Rangasai V
2023-09-15 13:28 ` Chuang, Rosen
2023-09-15 23:56 ` Nate DeSimone
2023-09-15 4:45 ` [edk2-devel] [PATCH v2 05/10] AlderlakeSiliconPkg/Include: Add ConfigBlock headers Saloni Kasbekar
2023-09-15 5:42 ` Chaganty, Rangasai V
2023-09-15 13:28 ` Chuang, Rosen
2023-09-15 23:56 ` Nate DeSimone
2023-09-15 4:45 ` [edk2-devel] [PATCH v2 06/10] AlderlakeSiliconPkg/Include: Add Library, Pins, Ppi Includes Saloni Kasbekar
2023-09-15 5:43 ` Chaganty, Rangasai V
2023-09-15 13:28 ` Chuang, Rosen
2023-09-15 23:56 ` Nate DeSimone
2023-09-15 4:45 ` [edk2-devel] [PATCH v2 07/10] AlderlakeSiliconPkg/Include: Add Protocol, Register, Other Includes Saloni Kasbekar
2023-09-15 5:43 ` Chaganty, Rangasai V
2023-09-15 13:28 ` Chuang, Rosen
2023-09-15 23:56 ` Nate DeSimone
2023-09-15 4:45 ` [edk2-devel] [PATCH v2 08/10] AlderlakeSiliconPkg/Fru: Add AdlCpu Fru Saloni Kasbekar
2023-09-15 5:43 ` Chaganty, Rangasai V
2023-09-15 13:29 ` Chuang, Rosen
2023-09-15 23:56 ` Nate DeSimone
2023-09-15 4:45 ` [edk2-devel] [PATCH v2 09/10] AlderlakeSiliconPkg: Add AdlPch Fru and IncludePrivate modules Saloni Kasbekar
2023-09-15 5:43 ` Chaganty, Rangasai V
2023-09-15 13:29 ` Chuang, Rosen
2023-09-15 23:57 ` Nate DeSimone
2023-09-15 4:45 ` [edk2-devel] [PATCH v2 10/10] AlderlakeSiliconPkg: Add Alderlake Product and SiPkg.dec Saloni Kasbekar
2023-09-15 5:43 ` Chaganty, Rangasai V
2023-09-15 13:29 ` Chuang, Rosen
2023-09-15 23:57 ` Nate DeSimone
2023-09-15 5:42 ` [edk2-devel] [PATCH v2 01/10] AlderlakeSiliconPkg/IpBlock: Add CpuPcieRp, Espi, Gpio components Chaganty, Rangasai V
2023-09-15 13:27 ` Chuang, Rosen
2023-09-15 23:56 ` Nate DeSimone
2023-09-16 0:26 ` Nate DeSimone
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox