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I see a long discussion on lore.kernel.org:<= /div>


This document also has some info on how CXL hotplug is handled:


Brian J. Johnson
Enterprise X86 Lab

Hewlett Packard Enterprise

Sent: Monday, November 6, 2023 at 5:20 AM
Subject: [edk2-devel] question about cxl device enumeration in pci bus driver

=20
Hi,
I have a question about cxl memory device hot-plug.

For example:
1. When cold boot, the platform has only 512GB cxl type-3 memory
2. During OS runtime, user hot-plug another cxl type-3  memory device expanding to 1TB.

So, how did OS identify another 512GB space newly added without a reboot?

Could anyone help to explain the procedure draftly?

Thanks




=E5=9C=A8 2023-10-27 09:29:31=EF=BC=8C"Yoshinoya" <yoshinoyatoko@163.com> =E5=86=99=E9=81=93=EF=BC=9A


Hi,
Thanks for reply!

I download code from this git&nbs= p;https://github.com/SayantaP-arm/edk2-platforms/

For this ARM edk2 sample package, it provided cxldxe driver which being executed after UEFI DXE PciBus enumeration finishes.

Intel also provied a CXL Type 3 memory device software guide.
This guide also describes system firmware boot sequence and uefi boot sequence.
But i could not match these describes with standard UEFI BIOS Boot flow, such as dxe phase's standard pci enumeration driver.
It sees needing add some cxl discovery code into dxe pci bus driver.

Thanks





At 2023-10-26 21:35:38, "Jonathan Cameron via groups.io" <jonathan.cameron=3Dhuawei.com@groups.io> wrote:
>On Thu, 26 Oct 2023 11:49:28 +0200
>"Laszlo Ersek" <lersek@redhat.com> wrote:
>
>> On 10/26/23 10:33, Gerd Hoffmann wrote:
>> > On Thu, Oct 26, 2023 at 10:36:35AM +0800, Yoshinoya wrote:
>> >  =20
>> >> CXL Host Bridge / Root Port / Switch / Device enumeration=
 / HDM Config, maybe could be integrated into pci drivers stack. =20
>> >=20
>> > Point being?  Can or should the firmware do anything useful w=
ith
>> > the CXL hardware?  If so, what exactly and why?
>> >=20
>> > Current state of affairs is that the PCI stack does the usual=
 PCI
>> > initialization (enumerate, assign resources to PCI bars) and =
leaves
>> > everything else to the OS. =20
>>=20
>> (I don't know what "HDM Config" stands for.)
>>=20
>> The only utility for driving CXL devices from the firmware could b=
e, AFAICT:
>>=20
>> - booting off of such a device (or at least "supporting OS bo=
ot" in some
>> manner)
>>=20
>> - using such a device for UEFI console purposes
>
>There are different models for how to use CXL devices and what's possib=
le depends on the
>version of CXL.  CXL 1.1 wasn't great for standards defined discovery, =
so
>EDK2 platform logic basically has to do everything.
>
>The one mostly expected for early CXL servers, for backwards compatibil=
ity, makes
>setting up the CXL memory decoders (Host managed Device Memory - HDM) i=
n all the
>components in the path to memory + locking them down an EDK2 problem.  =
They are then
>presented in the memory map and in SRAT, HMAT etc the same as normal DD=
R memory.
>Idea being that an old OS will be fine with that and doesn't have to be=
 CXL aware
>at all.  Note this also involves walking the CDAT tables via DOE mailbo=
xes in PCI
>config space to get the magic numbers needed to compute HMAT.
>
>The other model is to do very little in EDK2 and make entirely a proble=
m for the OS.
>The logic is necessary anyway if you want to support hotplug etc, so us=
e it for the
>cold plug paths 2.  That's all we've currently supported on QEMU.
>
>There was a presentation at Linux Plumbers last year on some out of tre=
e support
>from ARM for doing the setup on a CXL 2.0 platform (I think) in EDK2=20
>https://lpc.events/event/16/contributions/1254/
>But I guess it never went upstream.
>https://github.com/SayantaP-arm/edk2-pl=
atforms/tree/cxl-type-3
>
>+CC Sayanta
>
>Jonathan
>>=20
>> Laszlo
>>=20
>>=20
>>=20
>>=20
>>=20
>>=20
>
>
>
>
>
=20
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