public inbox for devel@edk2.groups.io
 help / color / mirror / Atom feed
From: "Abdul Lateef Attar" <abdattar@amd.com>
To: <devel@edk2.groups.io>
Cc: Abdul Lateef Attar <abdattar@amd.com>,
	Ard Biesheuvel <ardb+tianocore@kernel.org>,
	Leif Lindholm <quic_llindhol@quicinc.com>,
	"Abner Chang" <abner.chang@amd.com>,
	Michael D Kinney <michael.d.kinney@intel.com>
Subject: [PATCH v4 2/3] Platform/AMD/MinBoardPkg: Adds SetCacheMtrrLib library
Date: Mon, 3 Apr 2023 16:53:11 +0530	[thread overview]
Message-ID: <de853041f3ca33c74343aa847ac911bed25435f8.1680520788.git.abdattar@amd.com> (raw)
In-Reply-To: <cover.1680520788.git.abdattar@amd.com>

Adds SetCacheMtrrLib library for AmdMinBoardPkg,
which sets MTRR values for PEI phase and also
modifies the MTRR value at the end of PEI phase.

Signed-off-by: Abdul Lateef Attar <abdattar@amd.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Leif Lindholm <quic_llindhol@quicinc.com>
Cc: Abner Chang <abner.chang@amd.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
---
 .../AMD/AmdMinBoardPkg/AmdMinBoardPkg.dsc     |   9 ++
 .../SetCacheMtrrLib/SetCacheMtrrLib.inf       |  35 +++++
 .../Library/SetCacheMtrrLib/SetCacheMtrrLib.c | 133 ++++++++++++++++++
 3 files changed, 177 insertions(+)
 create mode 100644 Platform/AMD/AmdMinBoardPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib.inf
 create mode 100644 Platform/AMD/AmdMinBoardPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib.c

diff --git a/Platform/AMD/AmdMinBoardPkg/AmdMinBoardPkg.dsc b/Platform/AMD/AmdMinBoardPkg/AmdMinBoardPkg.dsc
index 74992a9a6b8c..2f17db5df5fb 100644
--- a/Platform/AMD/AmdMinBoardPkg/AmdMinBoardPkg.dsc
+++ b/Platform/AMD/AmdMinBoardPkg/AmdMinBoardPkg.dsc
@@ -18,4 +18,13 @@ [Defines]
 
 [Packages]
   AmdMinBoardPkg/AmdMinBoardPkg.dec
+  MdePkg/MdePkg.dec
+  MinPlatformPkg/MinPlatformPkg.dec
+  UefiCpuPkg/UefiCpuPkg.dec
+
+[LibraryClasses.common.PEIM]
+  SetCacheMtrrLib|AmdMinBoardPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib.inf
+
+[Components.IA32]
+  AmdMinBoardPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib.inf
 
diff --git a/Platform/AMD/AmdMinBoardPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib.inf b/Platform/AMD/AmdMinBoardPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib.inf
new file mode 100644
index 000000000000..b4c4b3e7de14
--- /dev/null
+++ b/Platform/AMD/AmdMinBoardPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib.inf
@@ -0,0 +1,35 @@
+## @file
+# Component information file for Platform SetCacheMtrr Library.
+# This library implementation is for AMD processor based platforms.
+#
+# Copyright (C) 2023 Advanced Micro Devices, Inc. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+  INF_VERSION                    = 1.29
+  BASE_NAME                      = PeiSetCacheMtrrLib
+  FILE_GUID                      = 1E8468E0-5EB4-4088-9B52-BFDC6E4DAE87
+  MODULE_TYPE                    = PEIM
+  VERSION_STRING                 = 1.0
+  LIBRARY_CLASS                  = SetCacheMtrrLib
+
+[LibraryClasses]
+  BaseLib
+  DebugLib
+  MtrrLib
+
+[Packages]
+  MdePkg/MdePkg.dec
+  MinPlatformPkg/MinPlatformPkg.dec
+  UefiCpuPkg/UefiCpuPkg.dec
+
+[Sources]
+  SetCacheMtrrLib.c
+
+[Pcd]
+  gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress
+  gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize
+
diff --git a/Platform/AMD/AmdMinBoardPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib.c b/Platform/AMD/AmdMinBoardPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib.c
new file mode 100644
index 000000000000..33b774fedbd3
--- /dev/null
+++ b/Platform/AMD/AmdMinBoardPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib.c
@@ -0,0 +1,133 @@
+/** @file
+
+SetCacheMtrr library functions.
+This library implementation is for AMD processor based platforms.
+
+Copyright (C) 2023 Advanced Micro Devices, Inc. All rights reserved.<BR>
+
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Uefi.h>
+#include <PiPei.h>
+#include <Library/DebugLib.h>
+#include <Library/MtrrLib.h>
+
+/**
+  This function sets the cache MTRR values for PEI phase.
+**/
+VOID
+EFIAPI
+SetCacheMtrr (
+  VOID
+  )
+{
+  EFI_STATUS  Status;
+
+  Status = MtrrSetMemoryAttribute (
+             0,
+             0xA0000,
+             CacheWriteBack
+             );
+  if (EFI_ERROR (Status)) {
+    DEBUG ((
+      DEBUG_ERROR,
+      "Error(%r) in setting CacheWriteBack for 0-0x9FFFF\n",
+      Status
+      ));
+  }
+
+  Status = MtrrSetMemoryAttribute (
+             0xA0000,
+             0x20000,
+             CacheUncacheable
+             );
+  if (EFI_ERROR (Status)) {
+    DEBUG ((
+      DEBUG_ERROR,
+      "Error(%r) in setting CacheUncacheable for 0xA0000-0xBFFFF\n",
+      Status
+      ));
+  }
+
+  Status = MtrrSetMemoryAttribute (
+             0xC0000,
+             0x40000,
+             CacheWriteProtected
+             );
+  if (EFI_ERROR (Status)) {
+    DEBUG ((
+      DEBUG_ERROR,
+      "Error(%r) in setting CacheWriteProtected for 0xC0000-0xFFFFF\n",
+      Status
+      ));
+  }
+
+  Status = MtrrSetMemoryAttribute (
+             0x100000,
+             0xAFF00000,
+             CacheWriteBack
+             );
+  if (EFI_ERROR (Status)) {
+    DEBUG ((
+      DEBUG_ERROR,
+      "Error(%r) in setting CacheWriteBack for 0x100000-0xAFFFFFFF\n",
+      Status
+      ));
+  }
+
+  Status = MtrrSetMemoryAttribute (
+             PcdGet32 (PcdFlashAreaBaseAddress),
+             PcdGet32 (PcdFlashAreaSize),
+             CacheWriteProtected
+             );
+  if (EFI_ERROR (Status)) {
+    DEBUG ((
+      DEBUG_ERROR,
+      "Error(%r) in setting CacheWriteProtected for 0x%X-0x%X\n",
+      Status,
+      PcdGet32 (PcdFlashAreaBaseAddress),
+      PcdGet32 (PcdFlashAreaBaseAddress) + PcdGet32 (PcdFlashAreaSize)
+      ));
+  }
+
+  MtrrDebugPrintAllMtrrs ();
+  return;
+}
+
+/**
+  Update MTRR setting in EndOfPei phase.
+  This function will set the MTRR value as CacheUncacheable
+  for Flash address.
+
+  @retval  EFI_SUCCESS  The function completes successfully.
+  @retval  Others       Some error occurs.
+**/
+EFI_STATUS
+EFIAPI
+SetCacheMtrrAfterEndOfPei (
+  VOID
+  )
+{
+  EFI_STATUS  Status;
+
+  Status = MtrrSetMemoryAttribute (
+             PcdGet32 (PcdFlashAreaBaseAddress),
+             PcdGet32 (PcdFlashAreaSize),
+             CacheUncacheable
+             );
+  if (EFI_ERROR (Status)) {
+    DEBUG ((
+      DEBUG_ERROR,
+      "Error(%r) in setting CacheUncacheable for 0x%X-0x%X\n",
+      Status,
+      PcdGet32 (PcdFlashAreaBaseAddress),
+      PcdGet32 (PcdFlashAreaBaseAddress) + PcdGet32 (PcdFlashAreaSize)
+      ));
+  }
+
+  MtrrDebugPrintAllMtrrs ();
+  return EFI_SUCCESS;
+}
+
-- 
2.25.1


  parent reply	other threads:[~2023-04-03 11:23 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-04-03 11:23 [PATCH v4 0/3] Adds Platform/AMD/AmdMinBoardPkg Abdul Lateef Attar
2023-04-03 11:23 ` [PATCH v4 1/3] Platform/AMD: Adds AmdMinBoardPkg to support MinPlatformPkg Abdul Lateef Attar
2023-04-10  2:32   ` Chang, Abner
2023-04-03 11:23 ` Abdul Lateef Attar [this message]
2023-04-10  2:32   ` [PATCH v4 2/3] Platform/AMD/MinBoardPkg: Adds SetCacheMtrrLib library Chang, Abner
2023-04-03 11:23 ` [PATCH v4 3/3] Maintainers.txt: Adds AMD/AmdMinBoardPkg maintainers Abdul Lateef Attar
2023-04-10  2:32   ` Chang, Abner
2023-04-11 11:04 ` [PATCH v4 0/3] Adds Platform/AMD/AmdMinBoardPkg Chang, Abner
2023-04-12  5:24   ` Chang, Abner
     [not found] ` <175268F40268DC52.3977@groups.io>
2023-04-17  5:56   ` [edk2-devel] [PATCH v4 3/3] Maintainers.txt: Adds AMD/AmdMinBoardPkg maintainers Attar, AbdulLateef (Abdul Lateef)
2023-04-17 11:44     ` Leif Lindholm
2023-04-18 17:35     ` Michael D Kinney

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-list from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=de853041f3ca33c74343aa847ac911bed25435f8.1680520788.git.abdattar@amd.com \
    --to=devel@edk2.groups.io \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox