From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by mx.groups.io with SMTP id smtpd.web12.20277.1581469589025147448 for ; Tue, 11 Feb 2020 17:06:29 -0800 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 192.55.52.88, mailfrom: liming.gao@intel.com) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga101.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 11 Feb 2020 17:06:28 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.70,428,1574150400"; d="scan'208";a="251744296" Received: from fmsmsx103.amr.corp.intel.com ([10.18.124.201]) by orsmga002.jf.intel.com with ESMTP; 11 Feb 2020 17:06:27 -0800 Received: from shsmsx606.ccr.corp.intel.com (10.109.6.216) by FMSMSX103.amr.corp.intel.com (10.18.124.201) with Microsoft SMTP Server (TLS) id 14.3.439.0; Tue, 11 Feb 2020 17:06:26 -0800 Received: from shsmsx606.ccr.corp.intel.com (10.109.6.216) by SHSMSX606.ccr.corp.intel.com (10.109.6.216) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1713.5; Wed, 12 Feb 2020 09:06:24 +0800 Received: from shsmsx606.ccr.corp.intel.com ([10.109.6.216]) by SHSMSX606.ccr.corp.intel.com ([10.109.6.216]) with mapi id 15.01.1713.004; Wed, 12 Feb 2020 09:06:24 +0800 From: "Liming Gao" To: Felix Polyudov , "'devel@edk2.groups.io'" Subject: Re: [PATCH] MdePkg: Add PCI Express 5.0 Header File Thread-Topic: [PATCH] MdePkg: Add PCI Express 5.0 Header File Thread-Index: AQHV26JeasSAuP4Z6Eiyq9BnKLVYHKgPMgfwgAEI4qCABmRnMIAAKgQQ Date: Wed, 12 Feb 2020 01:06:24 +0000 Message-ID: References: <20200204213012.67268-1-felixp@ami.com> <066f801dfccd49e5942241c51496d482@intel.com> <9333E191E0D52B4999CE63A99BA663A003FFBE5F12@atlms1.us.megatrends.com> <9333E191E0D52B4999CE63A99BA663A003FFBE80C0@atlms1.us.megatrends.com> In-Reply-To: <9333E191E0D52B4999CE63A99BA663A003FFBE80C0@atlms1.us.megatrends.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-version: 11.2.0.6 dlp-product: dlpe-windows dlp-reaction: no-action x-originating-ip: [10.239.127.36] MIME-Version: 1.0 Return-Path: liming.gao@intel.com Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Liming Gao PR https://github.com/tianocore/edk2/pull/366 > -----Original Message----- > From: Felix Polyudov > Sent: Wednesday, February 12, 2020 6:35 AM > To: Gao, Liming ; 'devel@edk2.groups.io' > Subject: RE: [PATCH] MdePkg: Add PCI Express 5.0 Header File >=20 > Liming, >=20 > Any update on this patch? >=20 > -----Original Message----- > From: Felix Polyudov > Sent: Friday, February 07, 2020 3:58 PM > To: 'Gao, Liming'; devel@edk2.groups.io > Cc: Kinney, Michael D; Manickavasakam Karpagavinayagam > Subject: RE: [PATCH] MdePkg: Add PCI Express 5.0 Header File >=20 > Yes, we did build tests on Windows/VS and Linux/GCC. >=20 > -----Original Message----- > From: Gao, Liming [mailto:liming.gao@intel.com] > Sent: Friday, February 07, 2020 12:10 AM > To: Felix Polyudov; devel@edk2.groups.io > Cc: Kinney, Michael D; Manickavasakam Karpagavinayagam > Subject: RE: [PATCH] MdePkg: Add PCI Express 5.0 Header File >=20 > Felix: > The patch is good. Is any test for the header file, such as build? >=20 > Thanks > Liming > > -----Original Message----- > > From: Felix Polyudov > > Sent: Wednesday, February 5, 2020 5:30 AM > > To: devel@edk2.groups.io > > Cc: Kinney, Michael D ; Gao, Liming ; manickavasakamk@ami.com > > Subject: [PATCH] MdePkg: Add PCI Express 5.0 Header File > > > > The header includes Physical Layer PCI Express Extended Capability > > definitions based on section 7.7.6 of PCI Express Base Specification 5.= 0. > > > > Signed-off-by: Felix Polyudov > > --- > > MdePkg/Include/IndustryStandard/PciExpress50.h | 136 +++++++++++++++++= ++++++++ > > 1 file changed, 136 insertions(+) > > create mode 100644 MdePkg/Include/IndustryStandard/PciExpress50.h > > > > diff --git a/MdePkg/Include/IndustryStandard/PciExpress50.h b/MdePkg/In= clude/IndustryStandard/PciExpress50.h > > new file mode 100644 > > index 0000000..26eae0b > > --- /dev/null > > +++ b/MdePkg/Include/IndustryStandard/PciExpress50.h > > @@ -0,0 +1,136 @@ > > +/** @file > > +Support for the PCI Express 5.0 standard. > > + > > +This header file may not define all structures. Please extend as requ= ired. > > + > > +Copyright (c) 2020, American Megatrends International LLC. All rights = reserved.
> > +SPDX-License-Identifier: BSD-2-Clause-Patent > > + > > +**/ > > + > > +#ifndef _PCIEXPRESS50_H_ > > +#define _PCIEXPRESS50_H_ > > + > > +#include > > + > > +#pragma pack(1) > > + > > +/// The Physical Layer PCI Express Extended Capability definitions. > > +/// > > +/// Based on section 7.7.6 of PCI Express Base Specification 5.0. > > +///@{ > > +#define PCI_EXPRESS_EXTENDED_CAPABILITY_PHYSICAL_LAYER_32_0_ID 0x00= 2A > > +#define PCI_EXPRESS_EXTENDED_CAPABILITY_PHYSICAL_LAYER_32_0_VER1 0x1 > > + > > +// Register offsets from Physical Layer PCI-E Ext Cap Header > > +#define PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_CAPABILITIES_OFFSET = 0x04 > > +#define PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_CONTROL_OFFSET = 0x08 > > +#define PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_STATUS_OFFSET = 0x0C > > +#define PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_RCVD_MODIFIED_TS_DATA1_OFF= SET 0x10 > > +#define PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_RCVD_MODIFIED_TS_DATA2_OFF= SET 0x14 > > +#define PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_TRANS_MODIFIED_TS_DATA1_OF= FSET 0x18 > > +#define PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_TRANS_MODIFIED_TS_DATA2_OF= FSET 0x1C > > +#define PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_LANE_EQUALIZATION_CONTROL_= OFFSET 0x20 > > + > > +typedef union { > > + struct { > > + UINT32 EqualizationByPassToHighestRateSupport : 1= ; // bit 0 > > + UINT32 NoEqualizationNeededSupport : 1= ; // bit 1 > > + UINT32 Reserved1 : 6= ; // Reserved bit 2:7 > > + UINT32 ModifiedTSUsageMode0Support : 1= ; // bit 8 > > + UINT32 ModifiedTSUsageMode1Support : 1= ; // bit 9 > > + UINT32 ModifiedTSUsageMode2Support : 1= ; // bit 10 > > + UINT32 ModifiedTSReservedUsageModes : 5= ; // bit 11:15 > > + UINT32 Reserved2 : 1= 6; // Reserved bit 16:31 > > + } Bits; > > + UINT32 Uint32; > > +} PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_CAPABILITIES; > > + > > +typedef union { > > + struct { > > + UINT32 EqualizationByPassToHighestRateDisable : 1= ; // bit 0 > > + UINT32 NoEqualizationNeededDisable : 1= ; // bit 1 > > + UINT32 Reserved1 : 6= ; // Reserved bit 2:7 > > + UINT32 ModifiedTSUsageModeSelected : 3= ; // bit 8:10 > > + UINT32 Reserved2 : 2= 1; // Reserved bit 11:31 > > + } Bits; > > + UINT32 Uint32; > > +} PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_CONTROL; > > + > > +typedef union { > > + struct { > > + UINT32 EqualizationComplete : 1; // bit 0 > > + UINT32 EqualizationPhase1Success : 1; // bit 1 > > + UINT32 EqualizationPhase2Success : 1; // bit 2 > > + UINT32 EqualizationPhase3Success : 1; // bit 3 > > + UINT32 LinkEqualizationRequest : 1; // bit 4 > > + UINT32 ModifiedTSRcvd : 1; // bit 5 > > + UINT32 RcvdEnhancedLinkControl : 2; // bit 6:7 > > + UINT32 TransmitterPrecodingOn : 1; // bit 8 > > + UINT32 TransmitterPrecodeRequest : 1; // bit 9 > > + UINT32 NoEqualizationNeededRcvd : 1; // bit 10 > > + UINT32 Reserved : 21; // Reserved bit 11:31 > > + } Bits; > > + UINT32 Uint32; > > +} PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_STATUS; > > + > > +typedef union { > > + struct { > > + UINT32 RcvdModifiedTSUsageMode : 3; // bit 0:2 > > + UINT32 RcvdModifiedTSUsageInfo1 : 13; // bit 3:15 > > + UINT32 RcvdModifiedTSVendorId : 16; // bit 16:31 > > + } Bits; > > + UINT32 Uint32; > > +} PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_RCVD_MODIFIED_TS_DATA1; > > + > > +typedef union { > > + struct { > > + UINT32 RcvdModifiedTSUsageInfo2 : 24; // bit 0:23 > > + UINT32 AltProtocolNegotiationStatus : 2; // bit 24:25 > > + UINT32 Reserved : 6; // Reserved bit 26:31 > > + } Bits; > > + UINT32 Uint32; > > +} PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_RCVD_MODIFIED_TS_DATA2; > > + > > +typedef union { > > + struct { > > + UINT32 TransModifiedTSUsageMode : 3; // bit 0:2 > > + UINT32 TransModifiedTSUsageInfo1 : 13; // bit 3:15 > > + UINT32 TransModifiedTSVendorId : 16; // bit 16:31 > > + } Bits; > > + UINT32 Uint32; > > +} PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_TRANS_MODIFIED_TS_DATA1; > > + > > +typedef union { > > + struct { > > + UINT32 TransModifiedTSUsageInfo2 : 24; // bit 0:23 > > + UINT32 AltProtocolNegotiationStatus : 2; // bit 24:25 > > + UINT32 Reserved : 6; // Reserved bit 26:31 > > + } Bits; > > + UINT32 Uint32; > > +} PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_TRANS_MODIFIED_TS_DATA2; > > + > > +typedef union { > > + struct { > > + UINT8 DownstreamPortTransmitterPreset : 4; //bit 0..3 > > + UINT8 UpstreamPortTransmitterPreset : 4; //bit 4..7 > > + } Bits; > > + UINT8 Uint8; > > +} PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_LANE_EQUALIZATION_CONTROL; > > + > > +typedef struct { > > + PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header= ; > > + PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_CAPABILITIES Capabl= ities; > > + PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_CONTROL Contro= l; > > + PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_STATUS Status= ; > > + PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_RCVD_MODIFIED_TS_DATA1 RcvdMo= difiedTs1Data; > > + PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_RCVD_MODIFIED_TS_DATA2 RcvdMo= difiedTs2Data; > > + PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_TRANS_MODIFIED_TS_DATA1 TransM= odifiedTs1Data; > > + PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_TRANS_MODIFIED_TS_DATA2 TransM= odifiedTs2Data; > > + PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_LANE_EQUALIZATION_CONTROL LaneEq= ualizationControl[1]; > > +} PCI_EXPRESS_EXTENDED_CAPABILITIES_PHYSICAL_LAYER_32_0; > > +///@} > > + > > +#pragma pack() > > + > > +#endif > > -- > > 2.10.0.windows.1 > > > > > > Please consider the environment before printing this email. > > > > The information contained in this message may be confidential and propr= ietary to American Megatrends (AMI). This communication is > > intended to be read only by the individual or entity to whom it is addr= essed or by their designee. If the reader of this message is not the > > intended recipient, you are on notice that any distribution of this mes= sage, in any form, is strictly prohibited. Please promptly notify > the > > sender by reply e-mail or by telephone at 770-246-8600, and then delete= or destroy all copies of the transmission. >=20 > Please consider the environment before printing this email. >=20 > The information contained in this message may be confidential and proprie= tary to American Megatrends (AMI). This communication is > intended to be read only by the individual or entity to whom it is addres= sed or by their designee. If the reader of this message is not the > intended recipient, you are on notice that any distribution of this messa= ge, in any form, is strictly prohibited. Please promptly notify the > sender by reply e-mail or by telephone at 770-246-8600, and then delete o= r destroy all copies of the transmission.