From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by spool.mail.gandi.net (Postfix) with ESMTPS id 8695C7803DE for ; Mon, 8 Jan 2024 13:00:46 +0000 (UTC) DKIM-Signature: a=rsa-sha256; bh=4dHD9NPm8ast+VCc/nrc/PS1do668cmJ4ibPf1fs/sM=; c=relaxed/simple; d=groups.io; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From:In-Reply-To:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Language:Content-Type:Content-Transfer-Encoding; s=20140610; t=1704718845; v=1; b=Ha9U+vd3n/EBPxnv3CEbaxTck4kOqpZA+pt97R6oR02fHdDD1bxdrhsZBkf7aXG200yHwTDk T2NFQwlFgUB6ojO8UTDjyyTaxpuSnkmHsLO+9EOeM8b0R+V6WmMMVfJ7TIyJI0Lo/7ltrPrCd9s KvKNx3Zd0h1ZI0AO1uY5CIMc= X-Received: by 127.0.0.2 with SMTP id A9f1YY7687511xxlHZVgeZha; Mon, 08 Jan 2024 05:00:45 -0800 X-Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.129.124]) by mx.groups.io with SMTP id smtpd.web11.5881.1704718844471242527 for ; Mon, 08 Jan 2024 05:00:44 -0800 X-Received: from mimecast-mx02.redhat.com (mimecast-mx02.redhat.com [66.187.233.88]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_256_GCM_SHA384) id us-mta-493-YnqzP9gHNreqv0viKFFBwA-1; Mon, 08 Jan 2024 08:00:42 -0500 X-MC-Unique: YnqzP9gHNreqv0viKFFBwA-1 X-Received: from smtp.corp.redhat.com (int-mx07.intmail.prod.int.rdu2.redhat.com [10.11.54.7]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id D52C1185A786; Mon, 8 Jan 2024 13:00:41 +0000 (UTC) X-Received: from [10.39.192.221] (unknown [10.39.192.221]) by smtp.corp.redhat.com (Postfix) with ESMTPS id D42211C060AF; Mon, 8 Jan 2024 13:00:40 +0000 (UTC) Message-ID: Date: Mon, 8 Jan 2024 14:00:39 +0100 MIME-Version: 1.0 Subject: Re: [edk2-devel] [PATCH v2 3/4] UefiCpuPkg/CpuTimerDxeRiscV64: Add support for Sstc To: Sunil V L , devel@edk2.groups.io Cc: Gerd Hoffmann , Rahul Kumar , Ray Ni , Andrei Warkentin References: <20240108113650.454940-1-sunilvl@ventanamicro.com> <20240108113650.454940-4-sunilvl@ventanamicro.com> From: "Laszlo Ersek" In-Reply-To: <20240108113650.454940-4-sunilvl@ventanamicro.com> X-Scanned-By: MIMEDefang 3.4.1 on 10.11.54.7 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,lersek@redhat.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: iabzuGQUQSv7AaUMebq3YsSqx7686176AA= Content-Language: en-US Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20140610 header.b=Ha9U+vd3; dmarc=fail reason="SPF not aligned (relaxed), DKIM not aligned (relaxed)" header.from=redhat.com (policy=none); spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce@groups.io On 1/8/24 12:36, Sunil V L wrote: > Sstc extension allows to program the timer and receive the interrupt > without using an SBI call. This reduces the latency to generate the timer > interrupt. So, detect whether Sstc extension is supported and use the > stimecmp register directly to program the timer interrupt. >=20 > Cc: Gerd Hoffmann > Cc: Rahul Kumar > Cc: Laszlo Ersek > Cc: Ray Ni > Cc: Andrei Warkentin > Signed-off-by: Sunil V L > --- > .../CpuTimerDxeRiscV64/CpuTimerDxeRiscV64.inf | 1 + > UefiCpuPkg/CpuTimerDxeRiscV64/Timer.h | 2 + > UefiCpuPkg/CpuTimerDxeRiscV64/Timer.c | 49 +++++++++++++++++-- > 3 files changed, 49 insertions(+), 3 deletions(-) >=20 > diff --git a/UefiCpuPkg/CpuTimerDxeRiscV64/CpuTimerDxeRiscV64.inf b/UefiC= puPkg/CpuTimerDxeRiscV64/CpuTimerDxeRiscV64.inf > index aba660186dc0..f2a2cf12caef 100644 > --- a/UefiCpuPkg/CpuTimerDxeRiscV64/CpuTimerDxeRiscV64.inf > +++ b/UefiCpuPkg/CpuTimerDxeRiscV64/CpuTimerDxeRiscV64.inf > @@ -41,6 +41,7 @@ [Sources.RISCV64] > Timer.c > =20 > [Pcd] > + gEfiMdePkgTokenSpaceGuid.PcdRiscVFeatureOverride ## CONSUMES > gUefiCpuPkgTokenSpaceGuid.PcdCpuCoreCrystalClockFrequency ## CONSUMES > =20 > [Protocols] > diff --git a/UefiCpuPkg/CpuTimerDxeRiscV64/Timer.h b/UefiCpuPkg/CpuTimerD= xeRiscV64/Timer.h > index 9b3542230cb5..067bbd29f377 100644 > --- a/UefiCpuPkg/CpuTimerDxeRiscV64/Timer.h > +++ b/UefiCpuPkg/CpuTimerDxeRiscV64/Timer.h > @@ -26,6 +26,8 @@ > // > #define DEFAULT_TIMER_TICK_DURATION 100000 > =20 > +#define RISCV_CPU_FEATURE_SSTC_BITMASK BIT1 > + > extern VOID > RiscvSetTimerPeriod ( > UINT32 TimerPeriod > diff --git a/UefiCpuPkg/CpuTimerDxeRiscV64/Timer.c b/UefiCpuPkg/CpuTimerD= xeRiscV64/Timer.c > index 30e48061cd06..216f48a52931 100644 > --- a/UefiCpuPkg/CpuTimerDxeRiscV64/Timer.c > +++ b/UefiCpuPkg/CpuTimerDxeRiscV64/Timer.c > @@ -44,6 +44,45 @@ STATIC EFI_TIMER_NOTIFY mTimerNotifyFunction; > STATIC UINT64 mTimerPeriod =3D 0; > STATIC UINT64 mLastPeriodStart =3D 0; > =20 > +// > +// Sstc support > +// > +STATIC BOOLEAN mSstcEnabled =3D FALSE; > + > +/** > + Program the timer. > + > + Program either using stimecmp (when Sstc extension is enabled) or usin= g SBI > + TIME call. > + > + @param NextValue Core tick value the timer should expire. > +**/ > +STATIC > +VOID > +RiscVProgramTimer ( > + UINT64 NextValue > + ) > +{ > + if (mSstcEnabled) { > + RiscVSetSupervisorTimeCompareRegister (NextValue); > + } else { > + SbiSetTimer (NextValue); > + } > +} > + > +/** > + Check whether Sstc is enabled in PCD. > + > +**/ > +STATIC > +BOOLEAN > +RiscVIsSstcEnabled ( > + VOID > + ) > +{ > + return ((PcdGet64 (PcdRiscVFeatureOverride) & RISCV_CPU_FEATURE_SSTC_B= ITMASK) !=3D 0); > +} > + > /** > Timer Interrupt Handler. > =20 > @@ -94,7 +133,7 @@ TimerInterruptHandler ( > ), > 1000000u > ); // convert to tick > - SbiSetTimer (PeriodStart); > + RiscVProgramTimer (PeriodStart); > RiscVEnableTimerInterrupt (); // enable SMode timer int > gBS->RestoreTPL (OriginalTPL); > } > @@ -197,8 +236,7 @@ TimerDriverSetTimerPeriod ( > ), > 1000000u > ); // convert to tick > - SbiSetTimer (PeriodStart); > - > + RiscVProgramTimer (PeriodStart); > mCpu->EnableInterrupt (mCpu); > RiscVEnableTimerInterrupt (); // enable SMode timer int > return EFI_SUCCESS; > @@ -282,6 +320,11 @@ TimerDriverInitialize ( > // > mTimerNotifyFunction =3D NULL; > =20 > + if (RiscVIsSstcEnabled ()) { > + mSstcEnabled =3D TRUE; > + DEBUG ((DEBUG_INFO, "TimerDriverInitialize: Timer interrupt is via S= stc extension\n")); > + } > + > // > // Make sure the Timer Architectural Protocol is not already installed= in the system > // Reviewed-by: Laszlo Ersek -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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