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Subject: Re: [edk2-devel] [PATCH] MdeModulePkg/PciHostBridge: Update Mem and PMem Limit Checks
To: devel@edk2.groups.io, wasim.khan@nxp.com,
 Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Varun Sethi <V.Sethi@nxp.com>, "Wu, Hao A" <hao.a.wu@intel.com>,
 "Ni, Ray" <ray.ni@intel.com>
References: <1587638612-13056-1-git-send-email-wasim.khan@nxp.com>
 <CAKv+Gu9WdRAq2yYvMgj-8QKY36tKDfCZZd0hkMkVMtdChc+iuw@mail.gmail.com>
 <VE1PR04MB6702CF99033B0CB4D8C6C16B90D00@VE1PR04MB6702.eurprd04.prod.outlook.com>
From: "Ard Biesheuvel" <ard.biesheuvel@arm.com>
Message-ID: <dfadc915-cfa5-89c6-6e37-1cc605bb71b0@arm.com>
Date: Fri, 24 Apr 2020 08:07:59 +0200
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On 4/24/20 6:35 AM, Wasim Khan via groups.io wrote:
> 
> 
>> -----Original Message-----
>> From: Ard Biesheuvel <ard.biesheuvel@linaro.org>
>> Sent: Friday, April 24, 2020 12:27 AM
>> To: Wasim Khan <wasim.khan@nxp.com>
>> Cc: edk2-devel-groups-io <devel@edk2.groups.io>; Varun Sethi
>> <V.Sethi@nxp.com>; Wu, Hao A <hao.a.wu@intel.com>; Ni, Ray
>> <ray.ni@intel.com>
>> Subject: Re: [PATCH] MdeModulePkg/PciHostBridge: Update Mem and PMem
>> Limit Checks
>>
>> On Thu, 23 Apr 2020 at 12:43, Wasim Khan <wasim.khan@nxp.com> wrote:
>>>
>>> With Address Translation Support, it is possible and also correct that
>>> Mem and Pmem Limit cross the 4GB boundary.
>>> Update the checks so that Mem/PMem Limit should not cross 4GB from the
>>> Mem/PMem Base address.
>>>
>>> Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
>>> ---
>>>   MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c | 8 ++++----
>>>   1 file changed, 4 insertions(+), 4 deletions(-)
>>>
>>> diff --git a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c
>>> b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c
>>> index d304fae..9cf7e98 100644
>>> --- a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c
>>> +++ b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c
>>> @@ -117,8 +117,8 @@ CreateRootBridge (
>>>     // Make sure Mem and MemAbove4G apertures are valid
>>>     //
>>>     if (RESOURCE_VALID (&Bridge->Mem)) {
>>> -    ASSERT (Bridge->Mem.Limit < SIZE_4GB);
>>> -    if (Bridge->Mem.Limit >= SIZE_4GB) {
>>> +    ASSERT (Bridge->Mem.Limit < (Bridge->Mem.Base + SIZE_4GB));
>>> +    if (Bridge->Mem.Limit >= (Bridge->Mem.Base + SIZE_4GB)) {
>>>         return NULL;
>>>       }
>>>     }
>>> @@ -129,8 +129,8 @@ CreateRootBridge (
>>>       }
>>>     }
>>>     if (RESOURCE_VALID (&Bridge->PMem)) {
>>> -    ASSERT (Bridge->PMem.Limit < SIZE_4GB);
>>> -    if (Bridge->PMem.Limit >= SIZE_4GB) {
>>> +    ASSERT (Bridge->PMem.Limit < (Bridge->PMem.Base + SIZE_4GB));
>>> +    if (Bridge->PMem.Limit >= (Bridge->PMem.Base + SIZE_4GB)) {
>>>         return NULL;
>>>       }
>>>     }
>>> --
>>> 2.7.4
>>>
>>
>> This is not the right fix.
>>
>> The translation offset should be taken into account for these checks
> 
> Thanks for the review Ard.
> device address = host address + translation offset.
> Mem and Pmem represents "device address" , so that are already taking translation offset into account.
> 

OK, apparently I am missing something.

For the MMIO32 window, the limit has to be < 4 GB, since the whole 
region needs to be 32-bit addressable. Otherwise, how are you going to 
allocate a 32-bit BAR from the part of the window that is > 4 GB ?