From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by mx.groups.io with SMTP id smtpd.web12.49718.1638785575990270604 for ; Mon, 06 Dec 2021 02:12:56 -0800 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 192.55.52.151, mailfrom: sebastien.boeuf@intel.com) X-IronPort-AV: E=McAfee;i="6200,9189,10189"; a="217974114" X-IronPort-AV: E=Sophos;i="5.87,291,1631602800"; d="scan'208";a="217974114" Received: from orsmga006.jf.intel.com ([10.7.209.51]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Dec 2021 02:12:54 -0800 X-IronPort-AV: E=Sophos;i="5.87,291,1631602800"; d="scan'208";a="461754729" Received: from deyangko-mobl1.ccr.corp.intel.com (HELO sboeuf-mobl.home) ([10.252.18.29]) by orsmga006-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Dec 2021 02:12:52 -0800 From: sebastien.boeuf@intel.com To: devel@edk2.groups.io Cc: jiewen.yao@intel.com, jordan.l.justen@intel.com, kraxel@redhat.com, sebastien.boeuf@intel.com Subject: [PATCH v3 1/5] OvmfPkg: Handle Cloud Hypervisor host bridge Date: Mon, 6 Dec 2021 11:12:18 +0100 Message-Id: X-Mailer: git-send-email 2.30.2 In-Reply-To: References: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable From: Sebastien Boeuf Handle things differently when the detected host bridge matches the Cloud Hypervisor PCI host bridge identifier. Signed-off-by: Rob Bradford Signed-off-by: Sebastien Boeuf --- OvmfPkg/Csm/CsmSupportLib/LegacyInterrupt.c | 3 ++ OvmfPkg/Csm/CsmSupportLib/LegacyInterrupt.h | 5 +-- OvmfPkg/Csm/CsmSupportLib/LegacyRegion.c | 5 +++ OvmfPkg/Csm/CsmSupportLib/LegacyRegion.h | 1 + OvmfPkg/Include/IndustryStandard/CloudHv.h | 35 +++++++++++++++++++ OvmfPkg/Include/OvmfPlatforms.h | 1 + .../Library/AcpiTimerLib/BaseAcpiTimerLib.c | 3 ++ .../AcpiTimerLib/BaseRomAcpiTimerLib.c | 4 +++ .../Library/AcpiTimerLib/DxeAcpiTimerLib.c | 3 ++ .../PlatformBootManagerLib/BdsPlatform.c | 1 + .../ResetSystemLib/BaseResetShutdown.c | 3 ++ .../Library/ResetSystemLib/DxeResetShutdown.c | 12 +++++-- OvmfPkg/PlatformPei/MemDetect.c | 9 ++++- OvmfPkg/PlatformPei/Platform.c | 6 ++++ 14 files changed, 86 insertions(+), 5 deletions(-) create mode 100644 OvmfPkg/Include/IndustryStandard/CloudHv.h diff --git a/OvmfPkg/Csm/CsmSupportLib/LegacyInterrupt.c b/OvmfPkg/Csm/CsmS= upportLib/LegacyInterrupt.c index 97ca21945f..a5680beed0 100644 --- a/OvmfPkg/Csm/CsmSupportLib/LegacyInterrupt.c +++ b/OvmfPkg/Csm/CsmSupportLib/LegacyInterrupt.c @@ -191,6 +191,9 @@ LegacyInterruptInstall ( case INTEL_Q35_MCH_DEVICE_ID: mLegacyInterruptDevice =3D LEGACY_INT_DEV_Q35; break; + case CLOUDHV_DEVICE_ID: + mLegacyInterruptDevice =3D LEGACY_INT_DEV_CLOUDHV; + break; default: DEBUG ((DEBUG_ERROR, "%a: Unknown Host Bridge Device ID: 0x%04x\n", __FUNCTION__, HostBridgeDevId)); diff --git a/OvmfPkg/Csm/CsmSupportLib/LegacyInterrupt.h b/OvmfPkg/Csm/CsmS= upportLib/LegacyInterrupt.h index 1e37a41a57..3c3c635d2d 100644 --- a/OvmfPkg/Csm/CsmSupportLib/LegacyInterrupt.h +++ b/OvmfPkg/Csm/CsmSupportLib/LegacyInterrupt.h @@ -22,8 +22,9 @@ = = #define LEGACY_INT_BUS 0 -#define LEGACY_INT_DEV_PIIX4 0x01 -#define LEGACY_INT_DEV_Q35 0x1f +#define LEGACY_INT_DEV_PIIX4 0x01 +#define LEGACY_INT_DEV_Q35 0x1f +#define LEGACY_INT_DEV_CLOUDHV 0x1f #define LEGACY_INT_FUNC 0 = #define PIRQN 0x00 // PIRQ Null diff --git a/OvmfPkg/Csm/CsmSupportLib/LegacyRegion.c b/OvmfPkg/Csm/CsmSupp= ortLib/LegacyRegion.c index fe9ae27c9d..dd68812a9d 100644 --- a/OvmfPkg/Csm/CsmSupportLib/LegacyRegion.c +++ b/OvmfPkg/Csm/CsmSupportLib/LegacyRegion.c @@ -77,6 +77,8 @@ STATIC PAM_REGISTER_VALUE mRegisterValuesQ35[] =3D { {DRAMC_REGISTER_Q35 (MCH_PAM0), 0x10, 0x20} }; = +STATIC PAM_REGISTER_VALUE mRegisterValuesCloudHv[] =3D mRegisterValuesQ35; + STATIC PAM_REGISTER_VALUE *mRegisterValues; = // @@ -476,6 +478,9 @@ LegacyRegionInit ( case INTEL_Q35_MCH_DEVICE_ID: mRegisterValues =3D mRegisterValuesQ35; break; + case CLOUDHV_DEVICE_ID: + mRegisterValues =3D mRegisterValuesCloudHv; + break; default: DEBUG ((DEBUG_ERROR, "%a: Unknown Host Bridge Device ID: 0x%04x\n", __FUNCTION__, HostBridgeDevId)); diff --git a/OvmfPkg/Csm/CsmSupportLib/LegacyRegion.h b/OvmfPkg/Csm/CsmSupp= ortLib/LegacyRegion.h index e18cb97949..71df8f5fb2 100644 --- a/OvmfPkg/Csm/CsmSupportLib/LegacyRegion.h +++ b/OvmfPkg/Csm/CsmSupportLib/LegacyRegion.h @@ -17,6 +17,7 @@ #include #include #include +#include = #include #include diff --git a/OvmfPkg/Include/IndustryStandard/CloudHv.h b/OvmfPkg/Include/I= ndustryStandard/CloudHv.h new file mode 100644 index 0000000000..6ab18ad50d --- /dev/null +++ b/OvmfPkg/Include/IndustryStandard/CloudHv.h @@ -0,0 +1,35 @@ +/** @file + Various defines related to Cloud Hypervisor + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ +#ifndef __CLOUDHV_H__ +#define __CLOUDHV_H__ + +// +// Host Bridge Device ID +// +#define CLOUDHV_DEVICE_ID 0x0d57 + +// +// ACPI timer address +// +#define CLOUDHV_ACPI_TIMER_IO_ADDRESS 0xb008 + +// +// ACPI shutdown device address +// +#define CLOUDHV_ACPI_SHUTDOWN_IO_ADDRESS 0x03c0 + +// +// 32-bit MMIO memory hole base address +// +#define CLOUDHV_MMIO_HOLE_ADDRESS 0xc0000000 + +// +// 32-bit MMIO memory hole size +// +#define CLOUDHV_MMIO_HOLE_SIZE 0x38000000 + +#endif // __CLOUDHV_H__ diff --git a/OvmfPkg/Include/OvmfPlatforms.h b/OvmfPkg/Include/OvmfPlatform= s.h index 3b85593b70..ad0b0d2803 100644 --- a/OvmfPkg/Include/OvmfPlatforms.h +++ b/OvmfPkg/Include/OvmfPlatforms.h @@ -16,6 +16,7 @@ #include #include #include +#include = // // OVMF Host Bridge DID Address diff --git a/OvmfPkg/Library/AcpiTimerLib/BaseAcpiTimerLib.c b/OvmfPkg/Libr= ary/AcpiTimerLib/BaseAcpiTimerLib.c index 7c593e8be1..e182ac2b7d 100644 --- a/OvmfPkg/Library/AcpiTimerLib/BaseAcpiTimerLib.c +++ b/OvmfPkg/Library/AcpiTimerLib/BaseAcpiTimerLib.c @@ -55,6 +55,9 @@ AcpiTimerLibConstructor ( AcpiCtlReg =3D POWER_MGMT_REGISTER_Q35 (ICH9_ACPI_CNTL); AcpiEnBit =3D ICH9_ACPI_CNTL_ACPI_EN; break; + case CLOUDHV_DEVICE_ID: + mAcpiTimerIoAddr =3D CLOUDHV_ACPI_TIMER_IO_ADDRESS; + return RETURN_SUCCESS; default: DEBUG ((DEBUG_ERROR, "%a: Unknown Host Bridge Device ID: 0x%04x\n", __FUNCTION__, HostBridgeDevId)); diff --git a/OvmfPkg/Library/AcpiTimerLib/BaseRomAcpiTimerLib.c b/OvmfPkg/L= ibrary/AcpiTimerLib/BaseRomAcpiTimerLib.c index 52f3ea2dbf..a223153b2b 100644 --- a/OvmfPkg/Library/AcpiTimerLib/BaseRomAcpiTimerLib.c +++ b/OvmfPkg/Library/AcpiTimerLib/BaseRomAcpiTimerLib.c @@ -53,6 +53,8 @@ AcpiTimerLibConstructor ( AcpiCtlReg =3D POWER_MGMT_REGISTER_Q35 (ICH9_ACPI_CNTL); AcpiEnBit =3D ICH9_ACPI_CNTL_ACPI_EN; break; + case CLOUDHV_DEVICE_ID: + return RETURN_SUCCESS; default: DEBUG ((DEBUG_ERROR, "%a: Unknown Host Bridge Device ID: 0x%04x\n", __FUNCTION__, HostBridgeDevId)); @@ -107,6 +109,8 @@ InternalAcpiGetTimerTick ( case INTEL_Q35_MCH_DEVICE_ID: Pmba =3D POWER_MGMT_REGISTER_Q35 (ICH9_PMBASE); break; + case CLOUDHV_DEVICE_ID: + return IoRead32 (CLOUDHV_ACPI_TIMER_IO_ADDRESS); default: DEBUG ((DEBUG_ERROR, "%a: Unknown Host Bridge Device ID: 0x%04x\n", __FUNCTION__, HostBridgeDevId)); diff --git a/OvmfPkg/Library/AcpiTimerLib/DxeAcpiTimerLib.c b/OvmfPkg/Libra= ry/AcpiTimerLib/DxeAcpiTimerLib.c index 09076c0ade..3c9efb926f 100644 --- a/OvmfPkg/Library/AcpiTimerLib/DxeAcpiTimerLib.c +++ b/OvmfPkg/Library/AcpiTimerLib/DxeAcpiTimerLib.c @@ -50,6 +50,9 @@ AcpiTimerLibConstructor ( case INTEL_Q35_MCH_DEVICE_ID: Pmba =3D POWER_MGMT_REGISTER_Q35 (ICH9_PMBASE); break; + case CLOUDHV_DEVICE_ID: + mAcpiTimerIoAddr =3D CLOUDHV_ACPI_TIMER_IO_ADDRESS; + return RETURN_SUCCESS; default: DEBUG ((DEBUG_ERROR, "%a: Unknown Host Bridge Device ID: 0x%04x\n", __FUNCTION__, HostBridgeDevId)); diff --git a/OvmfPkg/Library/PlatformBootManagerLib/BdsPlatform.c b/OvmfPkg= /Library/PlatformBootManagerLib/BdsPlatform.c index 186401296a..50bfb45351 100644 --- a/OvmfPkg/Library/PlatformBootManagerLib/BdsPlatform.c +++ b/OvmfPkg/Library/PlatformBootManagerLib/BdsPlatform.c @@ -1282,6 +1282,7 @@ PciAcpiInitialization ( PciWrite8 (PCI_LIB_ADDRESS (0, 0x1f, 0, 0x6b), PciHostIrqs[3]); // H break; case MICROVM_PSEUDO_DEVICE_ID: + case CLOUDHV_DEVICE_ID: return; default: if (XenDetected ()) { diff --git a/OvmfPkg/Library/ResetSystemLib/BaseResetShutdown.c b/OvmfPkg/L= ibrary/ResetSystemLib/BaseResetShutdown.c index 21c80e4323..ba92299a3c 100644 --- a/OvmfPkg/Library/ResetSystemLib/BaseResetShutdown.c +++ b/OvmfPkg/Library/ResetSystemLib/BaseResetShutdown.c @@ -40,6 +40,9 @@ ResetShutdown ( case INTEL_Q35_MCH_DEVICE_ID: AcpiPmBaseAddress =3D ICH9_PMBASE_VALUE; break; + case CLOUDHV_DEVICE_ID: + IoWrite8 (CLOUDHV_ACPI_SHUTDOWN_IO_ADDRESS, 5 << 2 | 1 << 5); + CpuDeadLoop (); default: ASSERT (FALSE); CpuDeadLoop (); diff --git a/OvmfPkg/Library/ResetSystemLib/DxeResetShutdown.c b/OvmfPkg/Li= brary/ResetSystemLib/DxeResetShutdown.c index 5a75c32df3..9a7f68c504 100644 --- a/OvmfPkg/Library/ResetSystemLib/DxeResetShutdown.c +++ b/OvmfPkg/Library/ResetSystemLib/DxeResetShutdown.c @@ -16,6 +16,7 @@ #include // PIIX4_PMBA_VALUE = STATIC UINT16 mAcpiPmBaseAddress; +STATIC UINT16 mAcpiHwReducedSleepCtl; = EFI_STATUS EFIAPI @@ -34,6 +35,9 @@ DxeResetInit ( case INTEL_Q35_MCH_DEVICE_ID: mAcpiPmBaseAddress =3D ICH9_PMBASE_VALUE; break; + case CLOUDHV_DEVICE_ID: + mAcpiHwReducedSleepCtl =3D CLOUDHV_ACPI_SHUTDOWN_IO_ADDRESS; + break; default: ASSERT (FALSE); CpuDeadLoop (); @@ -56,7 +60,11 @@ ResetShutdown ( VOID ) { - IoBitFieldWrite16 (mAcpiPmBaseAddress + 4, 10, 13, 0); - IoOr16 (mAcpiPmBaseAddress + 4, BIT13); + if (mAcpiHwReducedSleepCtl) { + IoWrite8 (mAcpiHwReducedSleepCtl, 5 << 2 | 1 << 5); + } else { + IoBitFieldWrite16 (mAcpiPmBaseAddress + 4, 10, 13, 0); + IoOr16 (mAcpiPmBaseAddress + 4, BIT13); + } CpuDeadLoop (); } diff --git a/OvmfPkg/PlatformPei/MemDetect.c b/OvmfPkg/PlatformPei/MemDetec= t.c index d736b85e0d..38f8141a2c 100644 --- a/OvmfPkg/PlatformPei/MemDetect.c +++ b/OvmfPkg/PlatformPei/MemDetect.c @@ -16,6 +16,7 @@ Module Name: #include #include #include +#include #include #include = @@ -152,6 +153,12 @@ QemuUc32BaseInitialization ( return; } = + if (mHostBridgeDevId =3D=3D CLOUDHV_DEVICE_ID) { + Uc32Size =3D CLOUDHV_MMIO_HOLE_SIZE; + mQemuUc32Base =3D CLOUDHV_MMIO_HOLE_ADDRESS; + return; + } + ASSERT (mHostBridgeDevId =3D=3D INTEL_82441_DEVICE_ID); // // On i440fx, start with the [LowerMemorySize, 4GB) range. Make sure one @@ -775,7 +782,7 @@ QemuInitializeRam ( // practically any alignment, and we may not have enough variable MTRRs = to // cover it exactly. // - if (IsMtrrSupported ()) { + if (IsMtrrSupported () && mHostBridgeDevId !=3D CLOUDHV_DEVICE_ID) { MtrrGetAllMtrrs (&MtrrSettings); = // diff --git a/OvmfPkg/PlatformPei/Platform.c b/OvmfPkg/PlatformPei/Platform.c index df2d9ad015..272cab7bcc 100644 --- a/OvmfPkg/PlatformPei/Platform.c +++ b/OvmfPkg/PlatformPei/Platform.c @@ -372,6 +372,12 @@ MiscInitialization ( MICROVM_PSEUDO_DEVICE_ID); ASSERT_RETURN_ERROR (PcdStatus); return; + case CLOUDHV_DEVICE_ID: + DEBUG ((DEBUG_INFO, "%a: Cloud Hypervisor host bridge\n", __FUNCTION= __)); + PcdStatus =3D PcdSet16S (PcdOvmfHostBridgePciDevId, + CLOUDHV_DEVICE_ID); + ASSERT_RETURN_ERROR (PcdStatus); + return; default: DEBUG ((DEBUG_ERROR, "%a: Unknown Host Bridge Device ID: 0x%04x\n", __FUNCTION__, mHostBridgeDevId)); -- = 2.30.2 --------------------------------------------------------------------- Intel Corporation SAS (French simplified joint stock company) Registered headquarters: "Les Montalets"- 2, rue de Paris, = 92196 Meudon Cedex, France Registration Number: 302 456 199 R.C.S. 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