[edk2-devel] [edk2-platforms][PATCH V1] Silicon/Synopsys/DesignWare: DwEmacSnpDxe: Fix bug in EmacGetDmaStatus

["wangy" <wangyzhaoz@163.com>]

From: Yang Wang <wangyzhaoz@163.com>

If IrqStat is NULL, the interrupt status will not be
read from the device.When the interrupt status is read,
it will also be cleared.

Cc: Leif Lindholm <quic_llindhol@quicinc.com>
Cc: Ard Biesheuvel <ardb@kernel.org>
Cc: Ran Wang <wangran@bosc.ac.cn>

Signed-off-by: Yang Wang <wangyzhaoz@163.com>
---
 .../Drivers/DwEmacSnpDxe/EmacDxeUtil.c        | 22 ++++++++++++-------
 1 file changed, 14 insertions(+), 8 deletions(-)

diff --git a/Silicon/Synopsys/DesignWare/Drivers/DwEmacSnpDxe/EmacDxeUtil.c b/Silicon/Synopsys/DesignWare/Drivers/DwEmacSnpDxe/EmacDxeUtil.c
index 3b982ce984..26d3ff6138 100755
--- a/Silicon/Synopsys/DesignWare/Drivers/DwEmacSnpDxe/EmacDxeUtil.c
+++ b/Silicon/Synopsys/DesignWare/Drivers/DwEmacSnpDxe/EmacDxeUtil.c
@@ -500,24 +500,30 @@ EmacGetDmaStatus (
   UINT32  ErrorBit;
   UINT32  Mask = 0;
 
+  if (IrqStat != NULL) {
+    *IrqStat = 0;
+  }
+
   DmaStatus = MmioRead32 (MacBaseAddress +
                            DW_EMAC_DMAGRP_STATUS_OFST);
   if (DmaStatus & DW_EMAC_DMAGRP_STATUS_NIS_SET_MSK) {
     Mask |= DW_EMAC_DMAGRP_STATUS_NIS_SET_MSK;
     // Rx interrupt
     if (DmaStatus & DW_EMAC_DMAGRP_STATUS_RI_SET_MSK) {
-      *IrqStat |= EFI_SIMPLE_NETWORK_RECEIVE_INTERRUPT;
-      Mask |= DW_EMAC_DMAGRP_STATUS_RI_SET_MSK;
-    } else {
-      *IrqStat &= ~EFI_SIMPLE_NETWORK_RECEIVE_INTERRUPT;
+      if (IrqStat != NULL) {
+        *IrqStat |= EFI_SIMPLE_NETWORK_RECEIVE_INTERRUPT;
+        Mask |= DW_EMAC_DMAGRP_STATUS_RI_SET_MSK;
+      }
     }
+
     // Tx interrupt
     if (DmaStatus & DW_EMAC_DMAGRP_STATUS_TI_SET_MSK) {
-      *IrqStat |= EFI_SIMPLE_NETWORK_TRANSMIT_INTERRUPT;
-      Mask |= DW_EMAC_DMAGRP_STATUS_TI_SET_MSK;
-    } else {
-      *IrqStat &= ~EFI_SIMPLE_NETWORK_TRANSMIT_INTERRUPT;
+      if (IrqStat != NULL) {
+        *IrqStat |= EFI_SIMPLE_NETWORK_TRANSMIT_INTERRUPT;
+        Mask |= DW_EMAC_DMAGRP_STATUS_TI_SET_MSK;
+      }
     }
+
     // Tx Buffer
     if (DmaStatus & DW_EMAC_DMAGRP_STATUS_TU_SET_MSK){
       Mask |= DW_EMAC_DMAGRP_STATUS_TU_SET_MSK;
-- 
2.25.1



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