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From: "PierreGondois" <pierre.gondois@arm.com>
To: Pranav Madhu <Pranav.Madhu@arm.com>,
	"devel@edk2.groups.io" <devel@edk2.groups.io>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>,
	Leif Lindholm <leif@nuviainc.com>,
	Sami Mujawar <Sami.Mujawar@arm.com>, nd <nd@arm.com>
Subject: Re: [edk2-devel] [edk2-platforms][PATCH V1 1/8] Platform/Sgi: Helper macros for PPTT Table
Date: Wed, 21 Apr 2021 14:29:45 +0100	[thread overview]
Message-ID: <e1aeb4fe-cb68-2ab0-55c3-a0c81922a0d4@arm.com> (raw)
In-Reply-To: <AM5PR0801MB17150D5015D98DCAAFC8D38A8A489@AM5PR0801MB1715.eurprd08.prod.outlook.com>

Hi Pranav,

@@ -20,6 +20,132 @@
>>> �#define EFI_ACPI_ARM_CREATOR_ID SIGNATURE_32('A','R','M',' ')
>>> �#define EFI_ACPI_ARM_CREATOR_REVISION 0x00000099
>>>
>>> +#define CORE_COUNT����� FixedPcdGet32 (PcdCoreCount)
>>> +#define CLUSTER_COUNT�� FixedPcdGet32 (PcdClusterCount)
>>> +
>>> +#pragma pack(1)
>>> +// PPTT processor core structure
>>> +typedef struct {
>>> +� EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR� Core; �
>>>
>> +UINT32��������������������ï¿
>> ½
>>> +����������� Offset[2];
>> I think there should be 3 entries (DCache, ICache, L2Cache). Updating this will
>> require updating the other PPTT tables written.
> As per ACPI spec 6.4, chapter '5.2.29.2 Cache Type Structure - Type 1', " Only
> the head of the list needs to be listed as a resource by a processor node (and
> counted toward Number of Private Resources), as the cache node itself
> contains a link to the next level of cache."
> Here L2 cache is represented as next level of L1, so no need to count it.
Yes indeed you are right.
>> Would it be also possible to rename the field 'PrivateResources' as in the
>> spec ?
> Yes, but in actual, it is not the private resource count.

This was nit picking, 'Offset' also works for me, and other PPTT tables 
are calling this field as 'Offset'.

>
>> Another question: what does 'RD_' stands for ?
> RD Stands for Reference Design, it is the convention we follow.
>
>>> +� EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE����� DCache; �
>>> +EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE����� ICache; �
>>> +EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE����� L2Cache; }
>>> +RD_PPTT_CORE;
>>> +
>>> +// PPTT processor cluster structure
>>> +typedef struct {
>>> +� EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR� Cluster; �
>>>
>> +UINT32��������������������ï¿
>> ½
>>> +����������� Offset; �
>>> +EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE����� L3Cache; �
>>> +RD_PPTT_CORE Core[CORE_COUNT]; } RD_PPTT_CLUSTER;
>>> +
>>> +// PPTT processor cluster structure without cache typedef struct {
>>> +� EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR� Cluster; �
>>>
>> +UINT32��������������������ï¿
>> ½
>>> +����������� Offset;
>> I think there is no need for an offset here. Updating this will require updating
>> the other PPTT tables written.
> Right. Will update.
>
>>> +� RD_PPTT_CORE Core[CORE_COUNT];
>>> +} RD_PPTT_MINIMAL_CLUSTER;
>>> +
>>> +// PPTT processor package structure
>>> +typedef struct {
>>> +� EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR� Package; �
>>>
>> +UINT32��������������������ï¿
>> ½
>>> +����������� Offset; �
>>> +EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE����� Slc; �
>>> +RD_PPTT_MINIMAL_CLUSTER Cluster[CLUSTER_COUNT]; }
>>> +RD_PPTT_SLC_PACKAGE; #pragma pack ()
>>> +
>>> +//
>>> +// PPTT processor structure flags for different SoC components as
>>> defined in
>>> +// ACPI 6.3 specification
>>> +//
>>> +
>> [...]
>>> +// EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR
>>> +#define EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT(Length, Flag,
>>> Parent,������ \
>>> +� ACPIProcessorID, NumberOfPrivateResource) \
>> I think it should be possible to remove the 'Length' parameter and compute it
>> as:
>> sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR) +
>> NumberOfPrivateResource * sizeof
>> (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE) + NumberOfPrivateResource *
>> sizeof (UINT32)
>>
> As per 6.4 specification, table 5.138, the Length is "Length of the local processor
> structure in bytes" It is just the length of local processor, not the entire structure.
Yes indeed you are right.

Thanks for the answer,
Pierre



  reply	other threads:[~2021-04-21 13:29 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-04-02  9:12 [edk2-platforms][PATCH V1 0/8] Platform/Sgi: Add PPTT table for SGI/RD platforms Pranav Madhu
2021-04-02  9:12 ` [edk2-platforms][PATCH V1 1/8] Platform/Sgi: Helper macros for PPTT Table Pranav Madhu
2021-04-13  9:18   ` [edk2-devel] " PierreGondois
2021-04-20  5:57     ` Pranav Madhu
2021-04-21 13:29       ` PierreGondois [this message]
2021-04-02  9:12 ` [edk2-platforms][PATCH V1 2/8] Platform/Sgi: ACPI PPTT table for SGI-575 platform Pranav Madhu
2021-04-02  9:12 ` [edk2-platforms][PATCH V1 3/8] Platform/Sgi: ACPI PPTT table for RD-N1-Edge platform Pranav Madhu
2021-04-02  9:12 ` [edk2-platforms][PATCH V1 4/8] Platform/Sgi: ACPI PPTT table for RD-N1-Edge dual-chip Pranav Madhu
2021-04-02  9:12 ` [edk2-platforms][PATCH V1 5/8] Platform/Sgi: ACPI PPTT table for RD-E1-Edge platform Pranav Madhu
2021-04-13  9:34   ` [edk2-devel] " PierreGondois
2021-04-20  6:02     ` Pranav Madhu
2021-04-02  9:12 ` [edk2-platforms][PATCH V1 6/8] Platform/Sgi: ACPI PPTT Table for RD-V1 platform Pranav Madhu
2021-04-02  9:12 ` [edk2-platforms][PATCH V1 7/8] Platform/Sgi: ACPI PPTT Table for RD-V1 quad-chip platform Pranav Madhu
2021-04-02  9:12 ` [edk2-platforms][PATCH V1 8/8] Platform/Sgi: ACPI PPTT table for RD-N2 platform Pranav Madhu

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