From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by mx.groups.io with SMTP id smtpd.web09.4317.1664231534983044702 for ; Mon, 26 Sep 2022 15:32:15 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=ZnJ+D249; spf=permerror, err=parse error for token &{10 18 %{ir}.%{v}.%{d}.spf.has.pphosted.com}: invalid domain name (domain: quicinc.com, ip: 205.220.180.131, mailfrom: quic_llindhol@quicinc.com) Received: from pps.filterd (m0279871.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 28QMF73e019200; Mon, 26 Sep 2022 22:32:09 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=message-id : date : mime-version : subject : to : cc : references : from : in-reply-to : content-type : content-transfer-encoding; s=qcppdkim1; bh=SxxjWsNsDkQkDqTdQufAhV2RVrP457g1RQV89EM3ALI=; b=ZnJ+D249oqxb0XyuCSd16l3C0BcTDAIqJSkRoEraCAChoy3IQbCJXfjy1xVr8W2EUY8u 53guN81Vrq7E5PD7F8e13/UK19wKeP6CsoW3+W6b3e7FeW3LqqsqwpOLefcE9UaPpWXi DGdrWAtuMjn5pvFI6i1gVG4XvipF353XnpHS/lataCWvNAyFbpbWNAQAynjehqop7/U3 LLEPaciFVD3zgNx7C5dqy/tCWY0E3F0PWkh72eb2LaooBkhDmABzbz79r7t7V6IS/cN/ 73rTFAKh0SIS7Fn6Mg66nhjS5mU3vJzetAtTFqtN9GPgdQDx/w2+q9QIvqEsAhC4JkqY ag== Received: from nasanppmta02.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3jssg6vry8-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 26 Sep 2022 22:32:08 +0000 Received: from nasanex01c.na.qualcomm.com (corens_vlan604_snip.qualcomm.com [10.53.140.1]) by NASANPPMTA02.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 28QMW7Mp029449 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 26 Sep 2022 22:32:07 GMT Received: from [10.110.26.2] (10.80.80.8) by nasanex01c.na.qualcomm.com (10.45.79.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.29; Mon, 26 Sep 2022 15:32:07 -0700 Message-ID: Date: Mon, 26 Sep 2022 15:32:06 -0700 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:91.0) Gecko/20100101 Thunderbird/91.13.0 Subject: Re: [PATCH v3 05/16] ArmPkg/ArmMmuLib: don't replace table entries with block entries To: Ard Biesheuvel , CC: Alexander Graf References: <20220926082511.2110797-1-ardb@kernel.org> <20220926082511.2110797-6-ardb@kernel.org> From: "Leif Lindholm" In-Reply-To: <20220926082511.2110797-6-ardb@kernel.org> X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01c.na.qualcomm.com (10.45.79.139) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: 4eNOJHZrzIxaZCds0WdW9-pgCOoXSnLr X-Proofpoint-ORIG-GUID: 4eNOJHZrzIxaZCds0WdW9-pgCOoXSnLr X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.528,FMLib:17.11.122.1 definitions=2022-09-26_11,2022-09-22_02,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 mlxscore=0 phishscore=0 mlxlogscore=968 spamscore=0 clxscore=1015 priorityscore=1501 lowpriorityscore=0 malwarescore=0 suspectscore=0 impostorscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2209130000 definitions=main-2209260139 Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit On 2022-09-26 01:25, Ard Biesheuvel wrote: > Drop the optimization that replaces table entries with block entries and > frees the page tables in the subhierarchy that is being replaced. This > rarely occurs in practice anyway, and will require more elaborate TLB > maintenance once we switch to a different approach when running at EL1, > where we no longer disable the MMU and nuke the TLB entirely every time > we update a descriptor in a way that requires break-before-make (BBM). > > Signed-off-by: Ard Biesheuvel Reviewed-by: Leif Lindholm / Leif > --- > ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c | 20 ++------------------ > 1 file changed, 2 insertions(+), 18 deletions(-) > > diff --git a/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c b/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c > index e5ecc7375153..34f1031c4de3 100644 > --- a/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c > +++ b/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c > @@ -197,12 +197,9 @@ UpdateRegionMappingRecursive ( > // than a block, and recurse to create the block or page entries at > > // the next level. No block mappings are allowed at all at level 0, > > // so in that case, we have to recurse unconditionally. > > - // If we are changing a table entry and the AttributeClearMask is non-zero, > > - // we cannot replace it with a block entry without potentially losing > > - // attribute information, so keep the table entry in that case. > > // > > if ((Level == 0) || (((RegionStart | BlockEnd) & BlockMask) != 0) || > > - (IsTableEntry (*Entry, Level) && (AttributeClearMask != 0))) > > + IsTableEntry (*Entry, Level)) > > { > > ASSERT (Level < 3); > > > > @@ -294,20 +291,7 @@ UpdateRegionMappingRecursive ( > EntryValue |= (Level == 3) ? TT_TYPE_BLOCK_ENTRY_LEVEL3 > > : TT_TYPE_BLOCK_ENTRY; > > > > - if (IsTableEntry (*Entry, Level)) { > > - // > > - // We are replacing a table entry with a block entry. This is only > > - // possible if we are keeping none of the original attributes. > > - // We can free the table entry's page table, and all the ones below > > - // it, since we are dropping the only possible reference to it. > > - // > > - ASSERT (AttributeClearMask == 0); > > - TranslationTable = (VOID *)(UINTN)(*Entry & TT_ADDRESS_MASK_BLOCK_ENTRY); > > - ReplaceTableEntry (Entry, EntryValue, RegionStart, TRUE); > > - FreePageTablesRecursive (TranslationTable, Level + 1); > > - } else { > > - ReplaceTableEntry (Entry, EntryValue, RegionStart, FALSE); > > - } > > + ReplaceTableEntry (Entry, EntryValue, RegionStart, FALSE); > > } > > } > > >