From: "Saloni Kasbekar" <saloni.kasbekar@intel.com>
To: devel@edk2.groups.io
Cc: Saloni Kasbekar <saloni.kasbekar@intel.com>,
Sai Chaganty <rangasai.v.chaganty@intel.com>,
Nate DeSimone <nathaniel.l.desimone@intel.com>,
Isaac Oram <isaac.w.oram@intel.com>,
Rosen Chuang <rosen.chuang@intel.com>
Subject: [PATCH 2/6] AlderlakeOpenBoardPkg: Add modules
Date: Wed, 14 Jun 2023 12:17:24 -0700 [thread overview]
Message-ID: <e2218c702b6c4418c63cff5d7bced7884e91054e.1686770061.git.saloni.kasbekar@intel.com> (raw)
In-Reply-To: <cover.1686770061.git.saloni.kasbekar@intel.com>
Adds the following modules:
-BiosInfo
-OpenBoardPlatformInit
-SBCVpdStructurePcd
-SmmMultiBoardAcpiSupportLib
Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Isaac Oram <isaac.w.oram@intel.com>
Cc: Rosen Chuang <rosen.chuang@intel.com>
Signed-off-by: Saloni Kasbekar <saloni.kasbekar@intel.com>
---
.../AlderlakeOpenBoardPkg/BiosInfo/BiosInfo.c | 196 +++++++
.../BiosInfo/BiosInfo.inf | 91 ++++
.../OpenBoardPlatformInitPostMem.c | 499 ++++++++++++++++++
.../OpenBoardPlatformInitPostMem.inf | 84 +++
.../OpenBoardPlatformInitPreMem.c | 192 +++++++
.../OpenBoardPlatformInitPreMem.inf | 59 +++
.../OpenBoardPlatformInitSmm.c | 250 +++++++++
.../OpenBoardPlatformInitSmm.h | 50 ++
.../OpenBoardPlatformInitSmm.inf | 60 +++
.../SBCVpdStructurePcd/AllStructPCD.dsc | 19 +
.../GpioTableAdlPPostMem.dsc | 40 ++
.../GpioTableAdlPPreMem.dsc | 29 +
.../MrcDqDqsSPD/AdlPSpdMap.dsc | 138 +++++
.../PcieClocks/AdlPPcieClocks.dsc | 32 ++
.../SmmAcpiEnableLib.c | 51 ++
.../SmmMultiBoardAcpiSupportLib.c | 89 ++++
.../SmmMultiBoardAcpiSupportLib.inf | 40 ++
.../SmmSiliconAcpiEnableLib.c | 157 ++++++
18 files changed, 2076 insertions(+)
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/BiosInfo/BiosInfo.c
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/BiosInfo/BiosInfo.inf
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/OpenBoardPlatformInit/OpenBoardPlatformInitPei/OpenBoardPlatformInitPostMem.c
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/OpenBoardPlatformInit/OpenBoardPlatformInitPei/OpenBoardPlatformInitPostMem.inf
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/OpenBoardPlatformInit/OpenBoardPlatformInitPei/OpenBoardPlatformInitPreMem.c
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/OpenBoardPlatformInit/OpenBoardPlatformInitPei/OpenBoardPlatformInitPreMem.inf
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/OpenBoardPlatformInit/OpenBoardPlatformInitSmm/OpenBoardPlatformInitSmm.c
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/OpenBoardPlatformInit/OpenBoardPlatformInitSmm/OpenBoardPlatformInitSmm.h
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/OpenBoardPlatformInit/OpenBoardPlatformInitSmm/OpenBoardPlatformInitSmm.inf
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/SBCVpdStructurePcd/AllStructPCD.dsc
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/SBCVpdStructurePcd/GpioTableAdlPPostMem.dsc
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/SBCVpdStructurePcd/GpioTableAdlPPreMem.dsc
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/SBCVpdStructurePcd/MrcDqDqsSPD/AdlPSpdMap.dsc
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/SBCVpdStructurePcd/PcieClocks/AdlPPcieClocks.dsc
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/SmmMultiBoardAcpiSupportLib/SmmAcpiEnableLib.c
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/SmmMultiBoardAcpiSupportLib/SmmMultiBoardAcpiSupportLib.c
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/SmmMultiBoardAcpiSupportLib/SmmMultiBoardAcpiSupportLib.inf
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/SmmMultiBoardAcpiSupportLib/SmmSiliconAcpiEnableLib.c
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/BiosInfo/BiosInfo.c b/Platform/Intel/AlderlakeOpenBoardPkg/BiosInfo/BiosInfo.c
new file mode 100644
index 0000000000..64462900de
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/BiosInfo/BiosInfo.c
@@ -0,0 +1,196 @@
+/** @file
+ PEIM to provide BiosInfo structure listing up all firmware volume's base addresses, sizes,
+ attributes, and information associated to the firmware volume.
+ Primarily the structure is used on FIT table creation and Bpm.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <PiPei.h>
+#include <Guid/BiosInfo.h>
+#include <Library/PeiServicesLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/HobLib.h>
+#include <Library/PcdLib.h>
+#include <IndustryStandard/FirmwareInterfaceTable.h>
+#include <Ppi/FirmwareVolumeInfoMeasurementExcluded.h>
+#include <Library/MemoryAllocationLib.h>
+
+#define BASE_FV_SIZE 10
+
+#define FSP_WRAPPER_FV_SIZE 3
+
+#define TSN_MAC_ADDRESS_FV_SIZE 0
+
+#define BIOS_INFO_STRUCT_SIZE (BASE_FV_SIZE + FSP_WRAPPER_FV_SIZE + TSN_MAC_ADDRESS_FV_SIZE)
+
+
+/*
+ BIOS_INFO structure is the base of the firmware volume layout for Intel platform BIOS implementation
+ so security checker module can run based on the structure and throw warnings, error or deadloop
+ when any unexpected firmware volumes are detected.
+
+ BIOS_INFO is recommended to support full entries of firmware volumes present in a flash
+ with right type, attribute, version, flash map base address and size,
+ all associated information which is defined by BIOS_INFO_STRUCT structure.
+ - IBB firmware volumes, which are expected to be measured or/and verified
+ by hardware base security solution to meet SecureBoot chain of trust
+ (Intel BootGuard for example), have attribute 0x0.
+ - Post IBB firmware volumes, which are expected to be measured or/and verified
+ by BIOS (TCG code for measurement, RSA2048SHA256Sign algorithm for verification for example),
+ have attribute BIOS_INFO_STRUCT_ATTRIBUTE_BIOS_POST_IBB.
+ - Else, follows Firmware Interface Table specification.
+*/
+#pragma pack (1)
+typedef struct {
+ BIOS_INFO_HEADER Header;
+ BIOS_INFO_STRUCT Entry[BIOS_INFO_STRUCT_SIZE];
+} BIOS_INFO;
+#pragma pack ()
+
+GLOBAL_REMOVE_IF_UNREFERENCED BIOS_INFO mBiosInfo = {
+ {
+ BIOS_INFO_SIGNATURE,
+ BIOS_INFO_STRUCT_SIZE,
+ 0,
+ },
+ {
+ {
+ FIT_TYPE_07_BIOS_STARTUP_MODULE,
+ BIOS_INFO_STRUCT_ATTRIBUTE_GENERAL_EXCLUDE_FROM_FIT,
+ 0x0100,
+ FixedPcdGet32 (PcdFlashNvStorageVariableSize) + FixedPcdGet32 (PcdFlashNvStorageFtwWorkingSize) + FixedPcdGet32 (PcdFlashNvStorageFtwSpareSize),
+ FixedPcdGet32 (PcdFlashNvStorageVariableBase)
+ },
+ {
+ FIT_TYPE_07_BIOS_STARTUP_MODULE,
+ BIOS_INFO_STRUCT_ATTRIBUTE_BIOS_POST_IBB,
+ 0x0100,
+ FixedPcdGet32 (PcdFlashFvAdvancedSize),
+ FixedPcdGet32 (PcdFlashFvAdvancedBase)
+ },
+ {
+ FIT_TYPE_07_BIOS_STARTUP_MODULE,
+ BIOS_INFO_STRUCT_ATTRIBUTE_BIOS_POST_IBB,
+ 0x0100,
+ FixedPcdGet32 (PcdFlashFvOptionalSize),
+ FixedPcdGet32 (PcdFlashFvOptionalBase)
+ },
+ {
+ FIT_TYPE_07_BIOS_STARTUP_MODULE,
+ BIOS_INFO_STRUCT_ATTRIBUTE_BIOS_POST_IBB,
+ 0x0100,
+ FixedPcdGet32 (PcdFlashFvSecuritySize),
+ FixedPcdGet32 (PcdFlashFvSecurityBase)
+ },
+ {
+ FIT_TYPE_07_BIOS_STARTUP_MODULE,
+ BIOS_INFO_STRUCT_ATTRIBUTE_BIOS_POST_IBB,
+ 0x0100,
+ FixedPcdGet32 (PcdFlashFvOsBootSize),
+ FixedPcdGet32 (PcdFlashFvOsBootBase)
+ },
+ {
+ FIT_TYPE_07_BIOS_STARTUP_MODULE,
+ BIOS_INFO_STRUCT_ATTRIBUTE_BIOS_POST_IBB,
+ 0x0100,
+ FixedPcdGet32 (PcdFlashFvUefiBootSize),
+ FixedPcdGet32 (PcdFlashFvUefiBootBase)
+ },
+ {
+ FIT_TYPE_07_BIOS_STARTUP_MODULE,
+ BIOS_INFO_STRUCT_ATTRIBUTE_BIOS_POST_IBB,
+ 0x0100,
+ FixedPcdGet32 (PcdFlashFvPostMemorySize),
+ FixedPcdGet32 (PcdFlashFvPostMemoryBase)
+ },
+ {
+ FIT_TYPE_07_BIOS_STARTUP_MODULE,
+ BIOS_INFO_STRUCT_ATTRIBUTE_GENERAL_EXCLUDE_FROM_FIT,
+ 0x0100,
+ FixedPcdGet32 (PcdFlashFvFirmwareBinariesSize),
+ FixedPcdGet32 (PcdFlashFvFirmwareBinariesBase)
+ },
+ {
+ FIT_TYPE_07_BIOS_STARTUP_MODULE,
+ BIOS_INFO_STRUCT_ATTRIBUTE_BIOS_POST_IBB,
+ 0x0100,
+ FixedPcdGet32 (PcdFlashFvFspSSize),
+ FixedPcdGet32 (PcdFlashFvFspSBase)
+ },
+ {
+ FIT_TYPE_07_BIOS_STARTUP_MODULE,
+ 0x00, // IBB FV
+ 0x0100,
+ FixedPcdGet32 (PcdFlashFvFspMSize),
+ FixedPcdGet32 (PcdFlashFvFspMBase)
+ },
+ {
+ FIT_TYPE_07_BIOS_STARTUP_MODULE,
+ 0x00, // IBB FV
+ 0x0100,
+ FixedPcdGet32 (PcdFlashFvFspTSize),
+ FixedPcdGet32 (PcdFlashFvFspTBase)
+ },
+ {
+ FIT_TYPE_07_BIOS_STARTUP_MODULE,
+ 0x00, // IBB FV
+ 0x0100,
+ FixedPcdGet32 (PcdFlashFvPreMemorySize),
+ FixedPcdGet32 (PcdFlashFvPreMemoryBase)
+ },
+ {
+ FIT_TYPE_01_MICROCODE,
+ BIOS_INFO_STRUCT_ATTRIBUTE_MICROCODE_WHOLE_REGION,
+ 0x0100,
+ FixedPcdGet32 (PcdFlashMicrocodeFvSize),
+ FixedPcdGet32 (PcdFlashMicrocodeFvBase)
+ },
+ }
+};
+
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_PEI_PPI_DESCRIPTOR mBiosInfoPpiList = {
+ EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,
+ &gBiosInfoGuid,
+ &mBiosInfo
+};
+
+/**
+ Installs BiosInfo Ppi.
+
+ @param FileHandle Handle of the file being invoked.
+ @param PeiServices Describes the list of possible PEI Services.
+
+ @retval EFI_SUCCESS Install the BiosInfo Ppi successfully.
+
+**/
+EFI_STATUS
+EFIAPI
+BiosInfoEntryPoint (
+ IN EFI_PEI_FILE_HANDLE FileHandle,
+ IN CONST EFI_PEI_SERVICES **PeiServices
+ )
+{
+ EFI_STATUS Status;
+ VOID *HobData;
+
+ //
+ // Install PPI, so that other PEI module can add dependency.
+ //
+ Status = PeiServicesInstallPpi (&mBiosInfoPpiList);
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Build hob, so that DXE module can also get the data.
+ //
+ HobData = BuildGuidHob (&gBiosInfoGuid, sizeof (mBiosInfo));
+ ASSERT (HobData != NULL);
+ if (HobData == NULL) {
+ return EFI_OUT_OF_RESOURCES;
+ }
+ CopyMem (HobData, &mBiosInfo, sizeof (mBiosInfo));
+ return EFI_SUCCESS;
+}
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/BiosInfo/BiosInfo.inf b/Platform/Intel/AlderlakeOpenBoardPkg/BiosInfo/BiosInfo.inf
new file mode 100644
index 0000000000..f020cb6432
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/BiosInfo/BiosInfo.inf
@@ -0,0 +1,91 @@
+### @file
+# Module Information description file for BIOS Info PEIM.
+# The module provides BiosInfo structure listing up all firmware volume's base addresses,
+# sizes, attributes, those information associated to each firmware volume.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+###
+
+[Defines]
+ INF_VERSION = 0x00010017
+ BASE_NAME = BiosInfo
+ FILE_GUID = 4A4CA1C6-871C-45BB-8801-6910A7AA5807
+ VERSION_STRING = 1.0
+ MODULE_TYPE = PEIM
+ ENTRY_POINT = BiosInfoEntryPoint
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES IA32 X64
+#
+
+[LibraryClasses]
+ PeimEntryPoint
+ PeiServicesLib
+ PeiServicesTablePointerLib
+ HobLib
+ BaseMemoryLib
+ MemoryAllocationLib
+ DebugLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ AlderlakeSiliconPkg/SiPkg.dec
+ IntelSiliconPkg/IntelSiliconPkg.dec
+ MinPlatformPkg/MinPlatformPkg.dec
+ AlderlakeOpenBoardPkg/OpenBoardPkg.dec
+ SecurityPkg/SecurityPkg.dec
+ BoardModulePkg/BoardModulePkg.dec
+
+[Pcd]
+ gIntelSiliconPkgTokenSpaceGuid.PcdBiosAreaBaseAddress ## CONSUMES
+ gIntelSiliconPkgTokenSpaceGuid.PcdBiosSize ## CONSUMES
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase ## CONSUMES
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize ## CONSUMES
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase ## CONSUMES
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize ## CONSUMES
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase ## CONSUMES
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdFlashFvFirmwareBinariesBase ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdFlashFvFirmwareBinariesSize ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedBase ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdFlashFvOptionalBase ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdFlashFvOptionalSize ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityBase ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootBase ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootBase ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryBase ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize ## CONSUMES
+ gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase ## CONSUMES
+ gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSBase ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMBase ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTBase ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSize ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryBase ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemorySize ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdFlashFvExtendedPostMemorySize ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdFlashFvExtendedPostMemoryBase ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdFlashFvExtendedAdvancedSize ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdFlashFvExtendedAdvancedBase ## CONSUMES
+
+[Sources]
+ BiosInfo.c
+
+[Ppis]
+ gEfiPeiFirmwareVolumeInfoMeasurementExcludedPpiGuid ## PRODUCES
+
+[Guids]
+ gBiosInfoGuid ## PRODUCES
+
+[Depex]
+ gEfiPeiMasterBootModePpiGuid
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/OpenBoardPlatformInit/OpenBoardPlatformInitPei/OpenBoardPlatformInitPostMem.c b/Platform/Intel/AlderlakeOpenBoardPkg/OpenBoardPlatformInit/OpenBoardPlatformInitPei/OpenBoardPlatformInitPostMem.c
new file mode 100644
index 0000000000..a1bbb5c179
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/OpenBoardPlatformInit/OpenBoardPlatformInitPei/OpenBoardPlatformInitPostMem.c
@@ -0,0 +1,499 @@
+/** @file
+ Source code file for OpenBoard Platform Init PEI module
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Register/Msr.h>
+#include <CpuRegs.h>
+#include <Library/IoLib.h>
+#include <Library/HobLib.h>
+#include <Library/DebugLib.h>
+#include <Library/PchInfoLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/PeiServicesLib.h>
+#include <Ppi/EndOfPeiPhase.h>
+#include <Library/MtrrLib.h>
+#include <Ppi/ReadOnlyVariable2.h>
+#include <Guid/SmramMemoryReserve.h>
+#include <Library/ConfigBlockLib.h>
+#include <Ppi/SiPolicy.h>
+#include <PchPolicyCommon.h>
+#include <Library/SiPolicyLib.h>
+#include <Guid/FirmwareFileSystem2.h>
+#include <Protocol/FirmwareVolumeBlock.h>
+#include <Library/PostCodeLib.h>
+#include <PlatformPostCode.h>
+#include <Ppi/Spi.h>
+#include <Library/MtrrLib.h>
+#include <Library/PciSegmentLib.h>
+#include <Register/PchRegs.h>
+#include <PlatformBoardId.h>
+#include <Core/Pei/PeiMain.h>
+#include <Library/PchPciBdfLib.h>
+#include <Ppi/GraphicsPlatformPolicyPpi.h>
+#include <Library/PeiGetFvInfoLib.h>
+
+/**
+ Initializes the valid bits mask and valid address mask for MTRRs.
+
+ This function initializes the valid bits mask and valid address mask for MTRRs.
+
+ @param[out] MtrrValidBitsMask The mask for the valid bit of the MTRR
+ @param[out] MtrrValidAddressMask The valid address mask for the MTRR
+
+**/
+VOID
+MtrrLibInitializeMtrrMask (
+ OUT UINT64 *MtrrValidBitsMask,
+ OUT UINT64 *MtrrValidAddressMask
+ );
+
+/**
+ Convert variable MTRRs to a RAW MTRR_MEMORY_RANGE array.
+ One MTRR_MEMORY_RANGE element is created for each MTRR setting.
+ The routine doesn't remove the overlap or combine the near-by region.
+
+ @param[in] VariableSettings The variable MTRR values to shadow
+ @param[in] VariableMtrrCount The number of variable MTRRs
+ @param[in] MtrrValidBitsMask The mask for the valid bit of the MTRR
+ @param[in] MtrrValidAddressMask The valid address mask for MTRR
+ @param[out] VariableMtrr The array to shadow variable MTRRs content
+
+ @return Number of MTRRs which has been used.
+
+**/
+UINT32
+MtrrLibGetRawVariableRanges (
+ IN MTRR_VARIABLE_SETTINGS *VariableSettings,
+ IN UINTN VariableMtrrCount,
+ IN UINT64 MtrrValidBitsMask,
+ IN UINT64 MtrrValidAddressMask,
+ OUT MTRR_MEMORY_RANGE *VariableMtrr
+ );
+
+/**
+ Apply the variable MTRR settings to memory range array.
+
+ @param[in] VariableMtrr The variable MTRR array.
+ @param[in] VariableMtrrCount The count of variable MTRRs.
+ @param[in, out] Ranges Return the memory range array with new MTRR settings applied.
+ @param[in] RangeCapacity The capacity of memory range array.
+ @param[in, out] RangeCount Return the count of memory range.
+
+ @retval RETURN_SUCCESS The memory range array is returned successfully.
+ @retval RETURN_OUT_OF_RESOURCES The count of memory ranges exceeds capacity.
+**/
+RETURN_STATUS
+MtrrLibApplyVariableMtrrs (
+ IN CONST MTRR_MEMORY_RANGE *VariableMtrr,
+ IN UINT32 VariableMtrrCount,
+ IN OUT MTRR_MEMORY_RANGE *Ranges,
+ IN UINTN RangeCapacity,
+ IN OUT UINTN *RangeCount
+ );
+
+/**
+ This function attempts to set the attributes into MTRR setting buffer.
+
+ @param[in, out] MtrrSetting - A buffer holding all MTRRs content.
+ @param[in] Ranges - Array holding memory type settings.
+ @param[in] RangeCount - Memory range count in the array.
+
+ @retval Count of used variable Mtrrs
+**/
+EFI_STATUS
+EFIAPI
+EOPSetMemoryAttributesInMtrrSettings (
+ IN OUT MTRR_SETTINGS *MtrrSetting,
+ IN MTRR_MEMORY_RANGE *Ranges,
+ IN UINTN RangeCount
+ )
+{
+ EFI_STATUS Status;
+ UINTN Index;
+ UINTN HighIndex;
+ UINT64 TopHighMemory;
+
+ Status = EFI_NOT_FOUND;
+
+ for (Index = 0, HighIndex = 0xFF; Index < RangeCount; Index++) {
+ //
+ // Set Mtrr variables from 1M.
+ //
+ if (Ranges[Index].BaseAddress < 0x100000) {
+ Ranges[Index].Length -= 0x100000;
+ Ranges[Index].BaseAddress = 0x100000;
+ }
+ if ((Ranges[Index].BaseAddress >= SIZE_4GB) && (Ranges[Index].Type == CacheWriteBack)) {
+ HighIndex = Index; // Set above 4G attributes at the latest step.
+ } else {
+ Status = MtrrSetMemoryAttributeInMtrrSettings (
+ MtrrSetting,
+ Ranges[Index].BaseAddress,
+ Ranges[Index].Length,
+ Ranges[Index].Type
+ );
+ ASSERT_EFI_ERROR (Status);
+ }
+ }
+ if (HighIndex != 0xFF) {
+ TopHighMemory = Ranges[HighIndex].BaseAddress + Ranges[HighIndex].Length;
+ //
+ // Try to cover memory as mmuch as we can.
+ // In later phase boot loader code can re-configure MTRR to exclude flash region and get back above 4GB coverage.
+ //
+ do {
+ Status = MtrrSetMemoryAttributeInMtrrSettings (
+ MtrrSetting,
+ SIZE_4GB,
+ TopHighMemory - SIZE_4GB,
+ CacheWriteBack
+ );
+ if (TopHighMemory > SIZE_4GB) {
+ TopHighMemory = RShiftU64 (TopHighMemory, 1);
+ }
+ } while ((EFI_SUCCESS != Status) && (TopHighMemory > SIZE_4GB));
+ }
+
+ return Status;
+}
+
+
+EFI_STATUS
+EFIAPI
+OpenBoardPlatformInitEndOfPei (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
+ IN VOID *Ppi
+ );
+
+static EFI_PEI_NOTIFY_DESCRIPTOR mEndOfPeiNotifyList = {
+ (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
+ &gEfiEndOfPeiSignalPpiGuid,
+ (EFI_PEIM_NOTIFY_ENTRY_POINT) OpenBoardPlatformInitEndOfPei
+};
+
+EFI_STATUS
+EFIAPI
+GetPeiPlatformLidStatus (
+ OUT LID_STATUS *CurrentLidStatus
+ );
+
+EFI_STATUS
+EFIAPI
+GetVbtData (
+ OUT EFI_PHYSICAL_ADDRESS *VbtAddress,
+ OUT UINT32 *VbtSize
+ );
+
+PEI_GRAPHICS_PLATFORM_POLICY_PPI PeiGraphicsPlatform = {
+ PEI_GRAPHICS_PLATFORM_POLICY_REVISION,
+ GetPeiPlatformLidStatus,
+ GetVbtData
+};
+
+EFI_PEI_PPI_DESCRIPTOR mPeiGraphicsPlatformPpi = {
+ (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
+ &gPeiGraphicsPlatformPpiGuid,
+ &PeiGraphicsPlatform
+};
+
+EFI_STATUS
+EFIAPI
+GetVbtData (
+ OUT EFI_PHYSICAL_ADDRESS *VbtAddress,
+ OUT UINT32 *VbtSize
+ )
+{
+ EFI_GUID FileGuid;
+ EFI_GUID BmpImageGuid;
+ VOID *Buffer;
+ UINT32 Size;
+
+ Size = 0;
+ Buffer = NULL;
+
+
+ DEBUG((DEBUG_INFO, "GetVbtData Entry\n"));
+
+ CopyMem (&BmpImageGuid, PcdGetPtr(PcdIntelGraphicsVbtFileGuid), sizeof(BmpImageGuid));
+
+ CopyMem(&FileGuid, &BmpImageGuid, sizeof(FileGuid));
+ PeiGetSectionFromFv(FileGuid, &Buffer, &Size);
+ if (Buffer == NULL) {
+ DEBUG((DEBUG_ERROR, "Could not locate VBT\n"));
+ } else {
+ DEBUG ((DEBUG_INFO, "GetVbtData Buffer is 0x%x\n", Buffer));
+ DEBUG ((DEBUG_INFO, "GetVbtData Size is 0x%x\n", Size));
+ *VbtAddress = (EFI_PHYSICAL_ADDRESS)(UINTN)Buffer;
+ *VbtSize = Size;
+ }
+ DEBUG((DEBUG_INFO, "GetVbtData exit\n"));
+
+ return EFI_SUCCESS;
+}
+
+
+/**
+ This function will return Lid Status in PEI phase.
+
+ @param[out] CurrentLidStatus
+
+ @retval EFI_SUCCESS
+ @retval EFI_UNSUPPORTED
+**/
+
+EFI_STATUS
+EFIAPI
+GetPeiPlatformLidStatus (
+ OUT LID_STATUS *CurrentLidStatus
+ )
+{
+ DEBUG ((DEBUG_INFO, "LidStatus Entry\n"));
+ //
+ // If the platform does not support a lid, the function must return EFI_UNSUPPORTED
+ //
+ if (PcdGet8 (PcdPlatformType) == TypeTrad && PcdGet8 (PcdPlatformFlavor) == FlavorDesktop) {
+ DEBUG ((DEBUG_INFO, "Returning Lid status as unsupported to GOP for DT/AIO board\n"));
+ return EFI_UNSUPPORTED;
+ }
+
+ DEBUG ((DEBUG_INFO, "LidStatus UnSupported\n"));
+ return EFI_UNSUPPORTED;
+}
+
+/**
+ Update MTRR setting in EndOfPei phase.
+
+ @retval EFI_SUCCESS The function completes successfully.
+ @retval Others Some error occurs.
+**/
+EFI_STATUS
+EFIAPI
+SetCacheMtrrAfterEndOfPei (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+ EFI_PEI_HOB_POINTERS Hob;
+ UINTN Index;
+ UINT64 SmramSize;
+ UINT64 SmramBase;
+ EFI_SMRAM_HOB_DESCRIPTOR_BLOCK *SmramHobDescriptorBlock;
+ MTRR_SETTINGS MtrrSetting;
+ UINTN RangeCount;
+ UINT32 VariableMtrrCount;
+ UINT64 MtrrValidBitsMask;
+ UINT64 MtrrValidAddressMask;
+ MTRR_MEMORY_RANGE RawVariableRanges[MTRR_NUMBER_OF_VARIABLE_MTRR];
+ MTRR_MEMORY_RANGE Ranges[MTRR_NUMBER_OF_VARIABLE_MTRR];
+ MTRR_SETTINGS UCMtrrSetting;
+ //
+ // PI SMM IPL can't set SMRAM to WB because at that time CPU ARCH protocol is not available.
+ // Set cacheability of SMRAM to WB here to improve SMRAM initialization performance.
+ //
+ SmramSize = 0;
+ SmramBase = 0;
+ Status = PeiServicesGetHobList ((VOID **) &Hob.Raw);
+ while (!END_OF_HOB_LIST (Hob)) {
+ if (Hob.Header->HobType == EFI_HOB_TYPE_GUID_EXTENSION) {
+ if (CompareGuid (&Hob.Guid->Name, &gEfiSmmSmramMemoryGuid)) {
+ SmramHobDescriptorBlock = (EFI_SMRAM_HOB_DESCRIPTOR_BLOCK *) (Hob.Guid + 1);
+ for (Index = 0; Index < SmramHobDescriptorBlock->NumberOfSmmReservedRegions; Index++) {
+ if (SmramHobDescriptorBlock->Descriptor[Index].PhysicalStart > 0x100000) {
+ SmramSize += SmramHobDescriptorBlock->Descriptor[Index].PhysicalSize;
+ if (SmramBase == 0 || SmramBase > SmramHobDescriptorBlock->Descriptor[Index].CpuStart) {
+ SmramBase = SmramHobDescriptorBlock->Descriptor[Index].CpuStart;
+ }
+ }
+ }
+ break;
+ }
+ }
+ Hob.Raw = GET_NEXT_HOB (Hob);
+ }
+
+ MtrrGetAllMtrrs (&MtrrSetting);
+ VariableMtrrCount = GetVariableMtrrCount ();
+ MtrrLibInitializeMtrrMask (&MtrrValidBitsMask, &MtrrValidAddressMask);
+
+ Ranges[0].BaseAddress = 0;
+ Ranges[0].Length = MtrrValidBitsMask + 1;
+ Ranges[0].Type = (MTRR_MEMORY_CACHE_TYPE)(MtrrSetting.MtrrDefType & 0x07); //[Bits 2:0] Default Memory Type.
+ RangeCount = 1;
+
+ MtrrLibGetRawVariableRanges (
+ &MtrrSetting.Variables, VariableMtrrCount,
+ MtrrValidBitsMask, MtrrValidAddressMask, RawVariableRanges
+ );
+
+ MtrrLibApplyVariableMtrrs (
+ RawVariableRanges, VariableMtrrCount,
+ Ranges, ARRAY_SIZE (Ranges), &RangeCount
+ );
+
+ //
+ // Set SMRAM as CacheWriteBack for performance.
+ //
+ Ranges[RangeCount].BaseAddress = SmramBase;
+ Ranges[RangeCount].Length = SmramSize;
+ Ranges[RangeCount].Type = CacheWriteBack;
+ RangeCount++;
+
+ ZeroMem (&UCMtrrSetting, sizeof (MTRR_SETTINGS));
+ UCMtrrSetting.MtrrDefType = MtrrSetting.MtrrDefType;
+ Status = EOPSetMemoryAttributesInMtrrSettings (&UCMtrrSetting, Ranges, RangeCount);
+
+ CopyMem (&MtrrSetting.Variables, &UCMtrrSetting.Variables, sizeof (MTRR_VARIABLE_SETTINGS));
+ MtrrSetting.MtrrDefType = UCMtrrSetting.MtrrDefType;
+ return Status;
+}
+
+/**
+ Configure PciHostBridge related PCDs
+**/
+VOID
+ConfigurePciHostBridgePcds (
+ VOID
+ )
+{
+ EFI_PHYSICAL_ADDRESS PciBaseAddress;
+ UINT32 Tolud;
+ UINT64 Length;
+ UINT64 McD0BaseAddress;
+ UINTN ResMemLimit1;
+ //
+ // Allocate 56 KB of I/O space [0x2000..0xFFFF]
+ //
+ DEBUG ((DEBUG_INFO, " Assign IO resource for PCI_ROOT_BRIDGE from 0x%X to 0x%X\n", PcdGet16 (PcdPciReservedIobase) ,PcdGet16 (PcdPciReservedIoLimit)));
+
+ //
+ // Read memory map registers
+ //
+ McD0BaseAddress = PCI_SEGMENT_LIB_ADDRESS (SA_SEG_NUM, SA_MC_BUS, 0, 0, 0);
+ Tolud = PciSegmentRead32 (McD0BaseAddress + R_SA_TOLUD) & B_SA_TOLUD_TOLUD_MASK;
+ PciBaseAddress = Tolud;
+
+ ResMemLimit1 = PcdGet32 (PcdPciReservedMemLimit);
+ if (ResMemLimit1 == 0) {
+ ResMemLimit1 = (UINTN) PcdGet64 (PcdPciExpressBaseAddress);
+ }
+
+ Length = ResMemLimit1 - PciBaseAddress;
+
+ if (Length != 0) {
+ PcdSet32S (PcdPciReservedMemBase, (UINT32) PciBaseAddress);
+ PcdSet32S (PcdPciReservedMemLimit, (UINT32) (PciBaseAddress + Length - 1));
+ DEBUG ((DEBUG_INFO, " Assign Memory Resource for PCI_ROOT_BRIDGE from 0x%X", PcdGet32 (PcdPciReservedMemBase)));
+ DEBUG ((DEBUG_INFO, " to 0x%X\n", PcdGet32 (PcdPciReservedMemLimit)));
+ }
+
+ //
+ // Provide 256GB available above 4GB MMIO resource
+ // limited to use single variable MTRR to cover this above 4GB MMIO region.
+ //
+ PcdSet64S (PcdPciReservedMemAbove4GBBase, BASE_256GB);
+ PcdSet64S (PcdPciReservedMemAbove4GBLimit, BASE_256GB + SIZE_256GB - 1);
+ if (PcdGet64 (PcdPciReservedMemAbove4GBBase) < PcdGet64 (PcdPciReservedMemAbove4GBLimit)) {
+ DEBUG ((DEBUG_INFO, " PCI space that above 4GB MMIO is from 0x%lX", PcdGet64 (PcdPciReservedMemAbove4GBBase)));
+ DEBUG ((DEBUG_INFO, " to 0x%lX\n", PcdGet64 (PcdPciReservedMemAbove4GBLimit)));
+ }
+}
+
+/**
+ This function handles PlatformInit task at the end of PEI
+
+ @param[in] PeiServices Pointer to PEI Services Table.
+ @param[in] NotifyDesc Pointer to the descriptor for the Notification event that
+ caused this function to execute.
+ @param[in] Ppi Pointer to the PPI data associated with this function.
+
+ @retval EFI_SUCCESS The function completes successfully
+ @retval others
+**/
+EFI_STATUS
+EFIAPI
+OpenBoardPlatformInitEndOfPei (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
+ IN VOID *Ppi
+ )
+{
+ EFI_STATUS Status;
+
+ Status = SetCacheMtrrAfterEndOfPei ();
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Configure PciHostBridge related PCDs before DXE phase
+ //
+ ConfigurePciHostBridgePcds ();
+
+ return Status;
+}
+
+
+/**
+ Platform Init PEI module entry point
+
+ @param[in] FileHandle Not used.
+ @param[in] PeiServices General purpose services available to every PEIM.
+
+ @retval EFI_SUCCESS The function completes successfully
+ @retval EFI_OUT_OF_RESOURCES Insufficient resources to create database
+**/
+EFI_STATUS
+EFIAPI
+OpenBoardPlatformInitPostMemEntryPoint (
+ IN EFI_PEI_FILE_HANDLE FileHandle,
+ IN CONST EFI_PEI_SERVICES **PeiServices
+ )
+{
+ EFI_STATUS Status;
+ PEI_CORE_INSTANCE *PrivateData;
+ UINTN CurrentFv;
+ PEI_CORE_FV_HANDLE *CoreFvHandle;
+ VOID *HobData;
+
+ PostCode (PLATFORM_INIT_POSTMEM_ENTRY);
+
+
+ //
+ // Build a HOB to show current FV location for SA policy update code to consume.
+ //
+ PrivateData = PEI_CORE_INSTANCE_FROM_PS_THIS(PeiServices);
+ CurrentFv = PrivateData->CurrentPeimFvCount;
+ CoreFvHandle = &(PrivateData->Fv[CurrentFv]);
+
+ HobData = BuildGuidHob (
+ &gPlatformInitFvLocationGuid,
+ sizeof (VOID *)
+ );
+ ASSERT (HobData != NULL);
+ CopyMem (HobData, (VOID *) &CoreFvHandle, sizeof (VOID *));
+
+#if FixedPcdGetBool(PcdAdlLpSupport) == 1
+ //
+ // Install mPeiGraphicsPlatformPpi
+ //
+ DEBUG ((DEBUG_INFO, "Install mPeiGraphicsPlatformPpi \n"));
+ Status = PeiServicesInstallPpi (&mPeiGraphicsPlatformPpi);
+#else
+ //
+ // Notify mPeiGraphicsPlatformNotifyList
+ //
+ DEBUG ((DEBUG_INFO, "Notify mPeiGraphicsPlatformNotifyList \n"));
+ Status = PeiServicesNotifyPpi (&mPeiGraphicsPlatformNotifyList);
+#endif
+
+ //
+ // Performing PlatformInitEndOfPei after EndOfPei PPI produced
+ //
+ Status = PeiServicesNotifyPpi (&mEndOfPeiNotifyList);
+ PostCode (PLATFORM_INIT_POSTMEM_EXIT);
+
+ return Status;
+}
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/OpenBoardPlatformInit/OpenBoardPlatformInitPei/OpenBoardPlatformInitPostMem.inf b/Platform/Intel/AlderlakeOpenBoardPkg/OpenBoardPlatformInit/OpenBoardPlatformInitPei/OpenBoardPlatformInitPostMem.inf
new file mode 100644
index 0000000000..ff8e8fc60b
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/OpenBoardPlatformInit/OpenBoardPlatformInitPei/OpenBoardPlatformInitPostMem.inf
@@ -0,0 +1,84 @@
+### @file
+# Component information file for the OpenBoard Platform Init PEI module.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+###
+
+[Defines]
+ INF_VERSION = 0x00010017
+ BASE_NAME = OpenBoardPlatformInitPostMem
+ FILE_GUID = 314EE04C-1106-4DC6-ACBC-CF19C0DBC5CC
+ VERSION_STRING = 1.0
+ MODULE_TYPE = PEIM
+ ENTRY_POINT = OpenBoardPlatformInitPostMemEntryPoint
+
+[LibraryClasses]
+ PeimEntryPoint
+ DebugLib
+ IoLib
+ MemoryAllocationLib
+ BaseMemoryLib
+ HobLib
+ PeiServicesLib
+ PciSegmentLib
+ MtrrLib
+ PchInfoLib
+ PostCodeLib
+ SiPolicyLib
+ FspCommonLib
+ PcdLib
+ PchPciBdfLib
+ GpioLib
+ PeiGetFvInfoLib
+
+[Packages]
+ AlderlakeSiliconPkg/SiPkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ MdePkg/MdePkg.dec
+ UefiCpuPkg/UefiCpuPkg.dec
+ IntelFsp2Pkg/IntelFsp2Pkg.dec
+ IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec
+ AlderLakeFspBinPkg/Client/AlderLakeP/AlderLakeFspBinPkg.dec
+ SecurityPkg/SecurityPkg.dec
+ AlderlakeOpenBoardPkg/OpenBoardPkg.dec
+ MinPlatformPkg/MinPlatformPkg.dec
+ IntelSiliconPkg/IntelSiliconPkg.dec
+
+[Sources]
+ OpenBoardPlatformInitPostMem.c
+
+[Ppis]
+ gEfiEndOfPeiSignalPpiGuid ## CONSUMES
+ gEfiPeiReadOnlyVariable2PpiGuid ## CONSUMES
+ gPeiGraphicsPlatformPpiGuid ## PRODUCES
+ gFspSiliconInitDonePpiGuid ## CONSUMES
+
+[Protocols]
+
+[Guids]
+ gEfiSmmSmramMemoryGuid ## CONSUMES
+ gPlatformInitFvLocationGuid ## PRODUCES
+
+[Depex]
+ gEfiPeiMemoryDiscoveredPpiGuid
+
+[Pcd]
+ gEfiSecurityPkgTokenSpaceGuid.PcdFirmwareDebuggerInitialized ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdPlatformFlavor ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdPlatformType ## CONSUMES
+ gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdPciReservedIobase ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdPciReservedIoLimit ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdPciReservedMemBase ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdPciReservedMemLimit ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdPciReservedMemAbove4GBBase ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdPciReservedMemAbove4GBLimit ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdPciSegmentCount ## CONSUMES
+
+ gIntelSiliconPkgTokenSpaceGuid.PcdIntelGraphicsVbtFileGuid ## CONSUMES
+
+[FixedPcd]
+ gSiPkgTokenSpaceGuid.PcdAdlLpSupport ## CONSUMES
+ gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection ## CONSUMES
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/OpenBoardPlatformInit/OpenBoardPlatformInitPei/OpenBoardPlatformInitPreMem.c b/Platform/Intel/AlderlakeOpenBoardPkg/OpenBoardPlatformInit/OpenBoardPlatformInitPei/OpenBoardPlatformInitPreMem.c
new file mode 100644
index 0000000000..21c3e6a221
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/OpenBoardPlatformInit/OpenBoardPlatformInitPei/OpenBoardPlatformInitPreMem.c
@@ -0,0 +1,192 @@
+/** @file
+ Source code file for OpenBoard Platform Init Pre-Memory PEI module
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <PiPei.h>
+#include <Ppi/Reset.h>
+#include <Ppi/ReadOnlyVariable2.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/HobLib.h>
+#include <Library/IoLib.h>
+#include <Library/PcdLib.h>
+#include <Library/PciSegmentLib.h>
+#include <Library/PostCodeLib.h>
+#include <Register/PchRegs.h>
+#include <PlatformPostCode.h>
+#include <Library/PeiServicesLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <CpuRegs.h>
+
+
+///
+/// Reset Generator I/O Port
+///
+#define RESET_GENERATOR_PORT 0xCF9
+
+EFI_STATUS
+EFIAPI
+PlatformInitPreMem (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
+ IN VOID *Ppi
+ );
+
+EFI_STATUS
+EFIAPI
+MemoryDiscoveredPpiNotifyCallback (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
+ IN VOID *Ppi
+ );
+
+EFI_STATUS
+EFIAPI
+PchReset (
+ IN CONST EFI_PEI_SERVICES **PeiServices
+ );
+
+static EFI_PEI_NOTIFY_DESCRIPTOR mPreMemNotifyList = {
+ (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
+ &gEfiPeiReadOnlyVariable2PpiGuid,
+ (EFI_PEIM_NOTIFY_ENTRY_POINT) PlatformInitPreMem
+};
+
+static EFI_PEI_NOTIFY_DESCRIPTOR mMemDiscoveredNotifyList = {
+ (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
+ &gEfiPeiMemoryDiscoveredPpiGuid,
+ (EFI_PEIM_NOTIFY_ENTRY_POINT) MemoryDiscoveredPpiNotifyCallback
+};
+
+static EFI_PEI_RESET_PPI mResetPpi = {
+ PchReset
+};
+
+static EFI_PEI_PPI_DESCRIPTOR mPreMemPpiList[] = {
+ {
+ (EFI_PEI_PPI_DESCRIPTOR_PPI| EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
+ &gEfiPeiResetPpiGuid,
+ &mResetPpi
+ }
+};
+
+
+/**
+ Callback once there is main memory
+
+ @param[in] PeiServices General purpose services available to every PEIM.
+ @param[in] NotifyDescriptor Notify that this module published.
+ @param[in] Ppi PPI that was installed.
+
+ @retval EFI_SUCCESS The function completed successfully.
+**/
+EFI_STATUS
+EFIAPI
+MemoryDiscoveredPpiNotifyCallback (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
+ IN VOID *Ppi
+ )
+{
+ return EFI_SUCCESS;
+}
+
+//@todo it should be performed in Si Pkg.
+/**
+ Provide hard reset PPI service.
+ To generate full hard reset, write 0x0E to PCH RESET_GENERATOR_PORT (0xCF9).
+
+ @param[in] PeiServices General purpose services available to every PEIM.
+
+ @retval Not return System reset occured.
+ @retval EFI_DEVICE_ERROR Device error, could not reset the system.
+**/
+EFI_STATUS
+EFIAPI
+PchReset (
+ IN CONST EFI_PEI_SERVICES **PeiServices
+ )
+{
+ DEBUG ((DEBUG_INFO, "Perform Cold Reset\n"));
+ IoWrite8 (RESET_GENERATOR_PORT, 0x0E);
+
+ CpuDeadLoop ();
+
+ ///
+ /// System reset occured, should never reach at this line.
+ ///
+ ASSERT_EFI_ERROR (EFI_DEVICE_ERROR);
+
+ return EFI_DEVICE_ERROR;
+}
+
+/**
+ This function handles PlatformInit task after PeiReadOnlyVariable2 PPI produced
+
+ @param[in] PeiServices Pointer to PEI Services Table.
+ @param[in] NotifyDesc Pointer to the descriptor for the Notification event that
+ caused this function to execute.
+ @param[in] Ppi Pointer to the PPI data associated with this function.
+
+ @retval EFI_SUCCESS The function completes successfully
+ @retval others
+**/
+EFI_STATUS
+EFIAPI
+PlatformInitPreMem (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
+ IN VOID *Ppi
+ )
+{
+ EFI_STATUS Status;
+
+ PostCode(PLATFORM_INIT_PREMEM_ENTRY);
+
+ ///
+ /// Install Pre Memory PPIs
+ ///
+ Status = PeiServicesInstallPpi (&mPreMemPpiList[0]);
+ ASSERT_EFI_ERROR (Status);
+
+ PostCode(PLATFORM_INIT_PREMEM_EXIT);
+
+ return Status;
+}
+
+/**
+ Platform Init before memory PEI module entry point
+
+ @param[in] FileHandle Not used.
+ @param[in] PeiServices General purpose services available to every PEIM.
+
+ @retval EFI_SUCCESS The function completes successfully
+ @retval EFI_OUT_OF_RESOURCES Insufficient resources to create database
+**/
+EFI_STATUS
+EFIAPI
+OpenBoardPlatformInitPreMemEntryPoint (
+ IN EFI_PEI_FILE_HANDLE FileHandle,
+ IN CONST EFI_PEI_SERVICES **PeiServices
+ )
+{
+ EFI_STATUS Status;
+
+ ///
+ /// Performing PlatformInitPreMem after PeiReadOnlyVariable2 PPI produced
+ ///
+ Status = PeiServicesNotifyPpi (&mPreMemNotifyList);
+
+ ///
+ /// After code reorangized, memorycallback will run because the PPI is already
+ /// installed when code run to here, it is supposed that the InstallEfiMemory is
+ /// done before.
+ ///
+ Status = PeiServicesNotifyPpi (&mMemDiscoveredNotifyList);
+
+ return Status;
+}
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/OpenBoardPlatformInit/OpenBoardPlatformInitPei/OpenBoardPlatformInitPreMem.inf b/Platform/Intel/AlderlakeOpenBoardPkg/OpenBoardPlatformInit/OpenBoardPlatformInitPei/OpenBoardPlatformInitPreMem.inf
new file mode 100644
index 0000000000..e92ef0279a
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/OpenBoardPlatformInit/OpenBoardPlatformInitPei/OpenBoardPlatformInitPreMem.inf
@@ -0,0 +1,59 @@
+### @file
+# Component information file for the OpenBoard Platform Init Pre-Memory PEI module.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+###
+
+[Defines]
+ INF_VERSION = 0x00010017
+ BASE_NAME = OpenBoardPlatformInitPreMem
+ FILE_GUID = 56BBC314-B442-4D5A-BA5C-D842DAFDBB24
+ VERSION_STRING = 1.0
+ MODULE_TYPE = PEIM
+ ENTRY_POINT = OpenBoardPlatformInitPreMemEntryPoint
+
+[LibraryClasses]
+ PeimEntryPoint
+ BaseMemoryLib
+ DebugLib
+ HobLib
+ IoLib
+ PcdLib
+ PciSegmentLib
+ PostCodeLib
+ PostCodeMapLib
+ PeiServicesLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ UefiCpuPkg/UefiCpuPkg.dec
+ IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec
+ BoardModulePkg/BoardModulePkg.dec
+ PostCodeDebugFeaturePkg/PostCodeDebugFeaturePkg.dec
+ AlderlakeSiliconPkg/SiPkg.dec
+ AlderlakeOpenBoardPkg/OpenBoardPkg.dec
+ MinPlatformPkg/MinPlatformPkg.dec
+ SecurityPkg/SecurityPkg.dec
+
+[Pcd]
+ gPlatformModuleTokenSpaceGuid.PcdRamDebugEnable ## CONSUMES
+ gPlatformModuleTokenSpaceGuid.PcdSerialPortEnable ## CONSUMES
+ gSiPkgTokenSpaceGuid.PcdSerialIoUartEnable ## CONSUMES
+ gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial ## PRODUCES
+
+[Sources]
+ OpenBoardPlatformInitPreMem.c
+
+[Ppis]
+ gEfiPeiReadOnlyVariable2PpiGuid ## SOMETIMES_CONSUMES ## NOTIFY
+ gEfiPeiMemoryDiscoveredPpiGuid ## NOTIFY
+ gEfiPeiResetPpiGuid ## NOTIFY
+
+[Guids]
+ gDebugConfigVariableGuid ## CONSUMES ## Variable
+
+[Depex]
+ gEfiPeiReadOnlyVariable2PpiGuid
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/OpenBoardPlatformInit/OpenBoardPlatformInitSmm/OpenBoardPlatformInitSmm.c b/Platform/Intel/AlderlakeOpenBoardPkg/OpenBoardPlatformInit/OpenBoardPlatformInitSmm/OpenBoardPlatformInitSmm.c
new file mode 100644
index 0000000000..4ae8995bf1
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/OpenBoardPlatformInit/OpenBoardPlatformInitSmm/OpenBoardPlatformInitSmm.c
@@ -0,0 +1,250 @@
+/** @file
+ OpenBoard Platform SMM Driver.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "OpenBoardPlatformInitSmm.h"
+#include <CpuRegs.h>
+#include <PchPolicyCommon.h>
+#include "AcpiCommon.h"
+#include <Library/PmcLib.h>
+#include <Library/PciSegmentLib.h>
+#include <Library/PostCodeLib.h>
+#include <PlatformPostCode.h>
+#include <Register/PchRegs.h>
+#include <Register/PmcRegs.h>
+#include <Register/RtcRegs.h>
+
+//
+// Global variables
+//
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_SMM_SYSTEM_TABLE2 *mSmst;
+GLOBAL_REMOVE_IF_UNREFERENCED UINT16 mAcpiBaseAddr;
+GLOBAL_REMOVE_IF_UNREFERENCED PLATFORM_NVS_AREA *mPlatformNvsAreaPtr = 0;
+
+/**
+ Clear Port 80h
+
+ SMI handler to enable ACPI mode
+
+ Dispatched on reads from APM port with value EFI_ACPI_ENABLE_SW_SMI
+
+ Disables the SW SMI Timer.
+ ACPI events are disabled and ACPI event status is cleared.
+ SCI mode is then enabled.
+
+ Clear SLP SMI status
+ Enable SLP SMI
+
+ Disable SW SMI Timer
+
+ Clear all ACPI event status and disable all ACPI events
+
+ Disable PM sources except power button
+ Clear status bits
+
+ Disable GPE0 sources
+ Clear status bits
+
+ Disable GPE1 sources
+ Clear status bits
+
+ Guarantee day-of-month alarm is invalid (ACPI 1.0 section 4.7.2.4)
+
+ Enable SCI
+
+ Set 8254 timer clock gate enable if it's not set in early phase
+
+ @param[in] DispatchHandle - The handle of this callback, obtained when registering
+ @param[in] DispatchContext - Pointer to the EFI_SMM_SW_DISPATCH_CONTEXT
+ @param[in] CommBuffer - A pointer to a collection of data in memory that will
+ be conveyed from a non-SMM environment into an SMM environment.
+ @param[in] CommBufferSize - The size of the CommBuffer.
+**/
+EFI_STATUS
+EFIAPI
+EnableAcpiCallback (
+ IN EFI_HANDLE DispatchHandle,
+ IN CONST VOID *DispatchContext,
+ IN OUT VOID *CommBuffer OPTIONAL,
+ IN OUT UINTN *CommBufferSize OPTIONAL
+ )
+{
+ UINT32 OutputValue;
+ UINT32 Pm1Cnt;
+ EFI_STATUS Status;
+
+ Status = EFI_SUCCESS;
+ //
+ // BIOS must also ensure that CF9GR is cleared and locked before handing control to the
+ // OS in order to prevent the host from issuing global resets and resetting ME
+ //
+ // EDK2: To match PCCG current BIOS behavior, do not lock CF9 Global Reset
+ // MmioWrite32 (
+ // PmcBaseAddress + R_PCH_PMC_ETR3),
+ // PmInit);
+
+ //
+ // Clear Port 80h
+ //
+ OutputValue = 0;
+ mSmst->SmmIo.Io.Write (&mSmst->SmmIo, SMM_IO_UINT16, 0x80, 1, &OutputValue);
+
+ //
+ // Disable PM sources except power button
+ //
+ OutputValue = B_ACPI_IO_PM1_EN_PWRBTN;
+ mSmst->SmmIo.Io.Write (&mSmst->SmmIo, SMM_IO_UINT16, mAcpiBaseAddr + R_ACPI_IO_PM1_EN, 1, &OutputValue);
+ //
+ // Clear PM status except Power Button status for RapidStart Resume
+ //
+ // OutputValue = 0xFFFF;
+ OutputValue = 0xFEFF;
+ mSmst->SmmIo.Io.Write (&mSmst->SmmIo, SMM_IO_UINT16, mAcpiBaseAddr + R_ACPI_IO_PM1_STS, 1, &OutputValue);
+
+ //
+ // Guarantee day-of-month alarm is invalid (ACPI 1.0 section 4.7.2.4)
+ //
+ OutputValue = R_RTC_IO_REGD;
+ mSmst->SmmIo.Io.Write (&mSmst->SmmIo, SMM_IO_UINT8, R_RTC_IO_INDEX_ALT, 1, &OutputValue);
+ OutputValue = 0x0;
+ mSmst->SmmIo.Io.Write (&mSmst->SmmIo, SMM_IO_UINT8, R_RTC_IO_TARGET_ALT, 1, &OutputValue);
+
+ //
+ // Enable SCI
+ //
+ mSmst->SmmIo.Io.Read (&mSmst->SmmIo, SMM_IO_UINT32, mAcpiBaseAddr + R_ACPI_IO_PM1_CNT, 1, &Pm1Cnt);
+ Pm1Cnt |= B_ACPI_IO_PM1_CNT_SCI_EN;
+ mSmst->SmmIo.Io.Write (&mSmst->SmmIo, SMM_IO_UINT32, mAcpiBaseAddr + R_ACPI_IO_PM1_CNT, 1, &Pm1Cnt);
+ //
+ // Write ALT_GPI_SMI_EN to disable GPI1 (SMC_EXTSMI#)
+ //
+ OutputValue = 0;
+ mSmst->SmmIo.Io.Read (&mSmst->SmmIo, SMM_IO_UINT32, mAcpiBaseAddr + 0x38, 1, &OutputValue);
+ OutputValue = OutputValue & ~(1 << (UINTN) PcdGet8 (PcdSmcExtSmiBitPosition));
+ mSmst->SmmIo.Io.Write (&mSmst->SmmIo, SMM_IO_UINT32, mAcpiBaseAddr + 0x38, 1, &OutputValue);
+
+
+ return Status;
+}
+
+/**
+ Disable SCI
+
+ @param[in] DispatchHandle - The handle of this callback, obtained when registering
+ @param[in] DispatchContext - Pointer to the EFI_SMM_SW_DISPATCH_CONTEXT
+ @param[in] CommBuffer - A pointer to a collection of data in memory that will
+ be conveyed from a non-SMM environment into an SMM environment.
+ @param[in] CommBufferSize - The size of the CommBuffer.
+**/
+EFI_STATUS
+EFIAPI
+DisableAcpiCallback (
+ IN EFI_HANDLE DispatchHandle,
+ IN CONST VOID *DispatchContext,
+ IN OUT VOID *CommBuffer OPTIONAL,
+ IN UINTN *CommBufferSize OPTIONAL
+ )
+{
+ UINT32 Pm1Cnt;
+
+ //
+ // Disable SCI
+ //
+ mSmst->SmmIo.Io.Read (&mSmst->SmmIo, SMM_IO_UINT32, mAcpiBaseAddr + R_ACPI_IO_PM1_CNT, 1, &Pm1Cnt);
+ Pm1Cnt &= ~B_ACPI_IO_PM1_CNT_SCI_EN;
+ mSmst->SmmIo.Io.Write (&mSmst->SmmIo, SMM_IO_UINT32, mAcpiBaseAddr + R_ACPI_IO_PM1_CNT, 1, &Pm1Cnt);
+
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Initializes the SMM Platform Driver
+
+ @param[in] ImageHandle - Pointer to the loaded image protocol for this driver
+ @param[in] SystemTable - Pointer to the EFI System Table
+
+ @retval Status - EFI_SUCCESS
+ @retval Assert, otherwise.
+
+**/
+EFI_STATUS
+EFIAPI
+InitializePlatformSmm (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUS Status;
+ EFI_HANDLE Handle;
+ EFI_HANDLE SwHandle;
+ EFI_SMM_SW_DISPATCH2_PROTOCOL *SwDispatch;
+ EFI_SMM_SW_REGISTER_CONTEXT SwContext;
+ PLATFORM_NVS_AREA_PROTOCOL *PlatformNvsAreaProtocol;
+
+
+ Handle = NULL;
+ SwHandle = NULL;
+
+ PostCode (PLATFORM_SMM_INIT_ENTRY);
+
+ //
+ // Great! We're now in SMM!
+ //
+
+ //
+ // Initialize global variables
+ //
+ mSmst = gSmst;
+
+ //
+ // Get the ACPI Base Address
+ //
+ mAcpiBaseAddr = PmcGetAcpiBase ();
+
+ //
+ // Locate the ICH SMM SW dispatch protocol
+ //
+ Status = mSmst->SmmLocateProtocol (&gEfiSmmSwDispatch2ProtocolGuid, NULL, (VOID**)&SwDispatch);
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Locate our shared data area
+ //
+ Status = gBS->LocateProtocol (&gPlatformNvsAreaProtocolGuid, NULL, (VOID **) &PlatformNvsAreaProtocol);
+ ASSERT_EFI_ERROR (Status);
+ mPlatformNvsAreaPtr = PlatformNvsAreaProtocol->Area;
+
+ //
+ // Register ACPI enable handler
+ //
+ SwContext.SwSmiInputValue = (UINTN) PcdGet8 (PcdAcpiEnableSwSmi);
+ Status = SwDispatch->Register (
+ SwDispatch,
+ EnableAcpiCallback,
+ &SwContext,
+ &SwHandle
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Register ACPI disable handler
+ //
+ SwContext.SwSmiInputValue = (UINTN) PcdGet8 (PcdAcpiDisableSwSmi);
+ Status = SwDispatch->Register (
+ SwDispatch,
+ DisableAcpiCallback,
+ &SwContext,
+ &SwHandle
+ );
+ ASSERT_EFI_ERROR (Status);
+
+
+ PostCode(PLATFORM_SMM_INIT_EXIT);
+
+ return EFI_SUCCESS;
+}
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/OpenBoardPlatformInit/OpenBoardPlatformInitSmm/OpenBoardPlatformInitSmm.h b/Platform/Intel/AlderlakeOpenBoardPkg/OpenBoardPlatformInit/OpenBoardPlatformInitSmm/OpenBoardPlatformInitSmm.h
new file mode 100644
index 0000000000..f8949f613f
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/OpenBoardPlatformInit/OpenBoardPlatformInitSmm/OpenBoardPlatformInitSmm.h
@@ -0,0 +1,50 @@
+/** @file
+ Header file for the OpenBoard Platform SMM Driver.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _OPEN_BOARD_PLATFORM_INIT_SMM_H_
+#define _OPEN_BOARD_PLATFORM_INIT_SMM_H_
+
+#include "Platform.h"
+#include <Uefi/UefiBaseType.h>
+#include <Library/IoLib.h>
+#include <Library/PcdLib.h>
+#include <Library/DebugLib.h>
+#include <Library/SmmServicesTableLib.h>
+#include <Library/ReportStatusCodeLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/UefiRuntimeServicesTableLib.h>
+#include <PlatformBoardType.h>
+#include <Protocol/PciRootBridgeIo.h>
+#include <Protocol/SmmBase2.h>
+#include <Protocol/SmmSwDispatch2.h>
+#include <Protocol/PlatformNvsArea.h>
+#include <IndustryStandard/Pci30.h>
+
+//
+// Callback function prototypes
+//
+EFI_STATUS
+EFIAPI
+EnableAcpiCallback (
+ IN EFI_HANDLE DispatchHandle,
+ IN CONST VOID *DispatchContext,
+ IN OUT VOID *CommBuffer OPTIONAL,
+ IN UINTN *CommBufferSize OPTIONAL
+ );
+
+EFI_STATUS
+EFIAPI
+DisableAcpiCallback (
+ IN EFI_HANDLE DispatchHandle,
+ IN CONST VOID *DispatchContext,
+ IN OUT VOID *CommBuffer OPTIONAL,
+ IN UINTN *CommBufferSize OPTIONAL
+ );
+
+#endif
+
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/OpenBoardPlatformInit/OpenBoardPlatformInitSmm/OpenBoardPlatformInitSmm.inf b/Platform/Intel/AlderlakeOpenBoardPkg/OpenBoardPlatformInit/OpenBoardPlatformInitSmm/OpenBoardPlatformInitSmm.inf
new file mode 100644
index 0000000000..f426090a46
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/OpenBoardPlatformInit/OpenBoardPlatformInitSmm/OpenBoardPlatformInitSmm.inf
@@ -0,0 +1,60 @@
+### @file
+# Component information file for OpenBoard Platform SMM Driver
+#
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+###
+
+[Defines]
+ INF_VERSION = 0x00010017
+ BASE_NAME = OpenBoardPlatformInitSmm
+ FILE_GUID = CB73C3D9-2F01-4342-AE67-04DDE5264092
+ VERSION_STRING = 1.0
+ MODULE_TYPE = DXE_SMM_DRIVER
+ PI_SPECIFICATION_VERSION = 1.20
+ ENTRY_POINT = InitializePlatformSmm
+
+[LibraryClasses]
+ UefiDriverEntryPoint
+ BaseMemoryLib
+ BasePciLibPciExpress
+ DebugLib
+ ReportStatusCodeLib
+ SmmServicesTableLib
+ PmcLib
+ UefiRuntimeServicesTableLib
+ PciSegmentLib
+ PostCodeLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ AlderlakeSiliconPkg/SiPkg.dec
+ AlderlakeOpenBoardPkg/OpenBoardPkg.dec
+ UefiCpuPkg/UefiCpuPkg.dec
+
+[Pcd]
+ gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ## CONSUMES
+ gPlatformModuleTokenSpaceGuid.PcdAcpiEnableSwSmi ## CONSUMES
+ gPlatformModuleTokenSpaceGuid.PcdAcpiDisableSwSmi ## CONSUMES
+ gPlatformModuleTokenSpaceGuid.PcdSmcExtSmiBitPosition ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdPlatformFlavor
+
+[Sources]
+ OpenBoardPlatformInitSmm.h
+ OpenBoardPlatformInitSmm.c
+
+[Protocols]
+ gPlatformNvsAreaProtocolGuid ## CONSUMES
+ gEfiSmmBase2ProtocolGuid ## CONSUMES
+ gEfiSmmSwDispatch2ProtocolGuid ## CONSUMES
+
+[Depex]
+ gEfiSmmBase2ProtocolGuid AND
+ gEfiSmmSwDispatch2ProtocolGuid AND
+ gPlatformNvsAreaProtocolGuid
+
+
+
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/SBCVpdStructurePcd/AllStructPCD.dsc b/Platform/Intel/AlderlakeOpenBoardPkg/SBCVpdStructurePcd/AllStructPCD.dsc
new file mode 100644
index 0000000000..9215a026ae
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/SBCVpdStructurePcd/AllStructPCD.dsc
@@ -0,0 +1,19 @@
+## @file
+# Include All Board Gpio configuration file.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+!include $(PLATFORM_BOARD_PACKAGE)/SBCVpdStructurePcd/GpioTableAdlPPostMem.dsc
+!include $(PLATFORM_BOARD_PACKAGE)/SBCVpdStructurePcd/GpioTableAdlPPreMem.dsc
+
+
+# PCIe clock mapping
+!include $(PLATFORM_BOARD_PACKAGE)/SBCVpdStructurePcd/PcieClocks/AdlPPcieClocks.dsc
+
+# MRC DQS DQ and SPD mapping
+!include $(PLATFORM_BOARD_PACKAGE)/SBCVpdStructurePcd/MrcDqDqsSPD/AdlPSpdMap.dsc
+
+
+
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/SBCVpdStructurePcd/GpioTableAdlPPostMem.dsc b/Platform/Intel/AlderlakeOpenBoardPkg/SBCVpdStructurePcd/GpioTableAdlPPostMem.dsc
new file mode 100644
index 0000000000..3eb8c276b5
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/SBCVpdStructurePcd/GpioTableAdlPPostMem.dsc
@@ -0,0 +1,40 @@
+## @file
+# GPIO definition table for Alderlake P
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+###
+### !!! GPIOs designated to Native Functions shall not be configured by Platform Code.
+### Native Pins shall be configured by Silicon Code (based on BIOS policies setting) or soft straps(set by CSME in FITc).
+###
+###
+
+
+#mGpioTableAdlPDdr5Rvp
+[PcdsDynamicExVpd.common.SkuIdAdlPDdr5Rvp]
+gBoardModuleTokenSpaceGuid.VpdPcdBoardGpioTable|*|{CODE({
+ // CPU M.2 SSD1
+ {GPIO_VER2_LP_GPP_F20, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis,GpioPlatformReset, GpioTermNone}}, //CPU SSD1 RESET
+
+ // CPU M.2 SSD2
+ {GPIO_VER2_LP_GPP_C2, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis,GpioPlatformReset, GpioTermNone}}, //CPU SSD2 PWREN
+ {GPIO_VER2_LP_GPP_H1, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis,GpioPlatformReset, GpioTermNone}}, // CPU SSD2 RESET
+
+ // X4 Pcie Slot for Gen3 and Gen 4
+ {GPIO_VER2_LP_GPP_F10, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis,GpioPlatformReset, GpioTermNone}},//ONBOARD_X4_PCIE_SLOT1_RESET_N
+
+ // PCH M.2 SSD
+ {GPIO_VER2_LP_GPP_D16, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis,GpioPlatformReset, GpioTermNone}}, //M2_PCH_SSD_PWREN
+ {GPIO_VER2_LP_GPP_H0, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis,GpioPlatformReset, GpioTermNone}}, //M2_SSD_RST_N
+
+ // EC
+ {GPIO_VER2_LP_GPP_E7, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault,GpioIntLevel|GpioIntSmi,GpioPlatformReset, GpioTermNone, GpioPadConfigUnlock }}, //EC_SMI_N
+ {GPIO_VER2_LP_GPP_F9, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis,GpioPlatformReset, GpioTermNone}}, //EC_SLP_S0_CS_N
+
+ {0x0} // terminator
+})}
+
+
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/SBCVpdStructurePcd/GpioTableAdlPPreMem.dsc b/Platform/Intel/AlderlakeOpenBoardPkg/SBCVpdStructurePcd/GpioTableAdlPPreMem.dsc
new file mode 100644
index 0000000000..3e147894c7
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/SBCVpdStructurePcd/GpioTableAdlPPreMem.dsc
@@ -0,0 +1,29 @@
+## @file
+# Alderlake P RVP GPIO definition table for Pre-Memory Initialization
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+###
+### !!! GPIOs designated to Native Functions shall not be configured by Platform Code.
+### Native Pins shall be configured by Silicon Code (based on BIOS policies setting) or soft straps(set by CSME in FITc).
+###
+###
+
+# mGpioTablePreMemAdlPDdr5Rvp
+[PcdsDynamicExVpd.common.SkuIdAdlPDdr5Rvp]
+gBoardModuleTokenSpaceGuid.VpdPcdBoardGpioTablePreMem|*|{CODE({
+ // CPU M.2 SSD
+ { GPIO_VER2_LP_GPP_F20, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis, GpioPlatformReset, GpioTermNone } }, //CPU SSD RESET
+
+ // CPU M.2 SSD2
+ {GPIO_VER2_LP_GPP_C2, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis,GpioPlatformReset, GpioTermNone}}, //CPU SSD2 PWREN
+ {GPIO_VER2_LP_GPP_H1, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis,GpioPlatformReset, GpioTermNone}}, //CPU SSD2 RESET
+
+ // X4 Pcie Slot for Gen3 and Gen 4
+ {GPIO_VER2_LP_GPP_F10, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis,GpioPlatformReset, GpioTermNone}},//ONBOARD_X4_PCIE_SLOT1_RESET_N
+
+ {0x0} // terminator
+})}
\ No newline at end of file
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/SBCVpdStructurePcd/MrcDqDqsSPD/AdlPSpdMap.dsc b/Platform/Intel/AlderlakeOpenBoardPkg/SBCVpdStructurePcd/MrcDqDqsSPD/AdlPSpdMap.dsc
new file mode 100644
index 0000000000..096cc380cd
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/SBCVpdStructurePcd/MrcDqDqsSPD/AdlPSpdMap.dsc
@@ -0,0 +1,138 @@
+## @file
+# ADL P SPD DATA configuration file.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+
+[PcdsDynamicExVpd.common.SkuIdAdlPDdr5Rvp]
+gBoardModuleTokenSpaceGuid.VpdPcdMrcSpdData|*|{CODE(
+{
+// DDR5 1Rx16 - 4800 MHz
+ 1,
+ {0x30, ///< 0 1024 SPD bytes total
+ 0x08, ///< 1 SPD Revision 0.8
+ 0x12, ///< 2 DRAM Type: DDR5 SDRAM
+ 0x03, ///< 3 Module Type: Not Hybrid (DRAM only) / SO-DIMM Solution
+ 0x04, ///< 4 Monolithic SDRAM, 16 Gb SDRAM density
+ 0x00, ///< 5 16 Rows, 10 Columns
+ 0x40, ///< 6 x16 SDRAM I/O Width
+ 0x42, ///< 7 4 Bank Groups, 4 Banks per Bank Group
+ 0x00, ///< 8 Secondary SDRAM Density and Package
+ 0x00, ///< 9 Secondary SDRAM Addressing
+ 0x00, ///< 10 Secondary SDRAM I/O Width
+ 0x00, ///< 11 Secondary BankGroups and Banks per Bank Group
+ 0x60, ///< 12 PPR Supported, One row per bank group, Soft PPR Supported
+ 0x00, ///< 13 Commercial Temperature Grade, 0 to 85 C
+ 0x00, ///< 14 Reserved
+ 0x00, ///< 15 Reserved
+ 0x00, ///< 16 SDRAM Nominal Voltage VDD: 1.1V
+ 0x00, ///< 17 SDRAM Nominal Voltage VDDQ: 1.1V
+ 0x00, ///< 18 SDRAM Nominal Voltage VPP: 1.8V
+ 0x00, ///< 19 Reserved
+ 0xA1, ///< 20 tCKAVGmin LSB
+ 0x01, ///< 21 tCKAVGmin MSB
+ 0xE8, ///< 22 tCKAVGmax LSB
+ 0x03, ///< 23 tCKAVGmax MSB
+ 0x72, ///< 24 CAS Latencies supported (First Byte) : 32, 30, 28, 22
+ 0x15, ///< 25 CAS Latencies supported (Second Byte): 44, 40, 36
+ 0x00, ///< 26 CAS Latencies supported (Third Byte) :
+ 0x00, ///< 27 CAS Latencies supported (Fourth Byte):
+ 0x00, ///< 28 CAS Latencies supported (Fifth Byte) :
+ 0x00, ///< 29 Reserved
+ 0x1E, ///< 30 Minimum CAS Latency (tAAmin) LSB
+ 0x41, ///< 31 Minimum CAS Latency (tAAmin) MSB
+ 0x1E, ///< 32 Minimum RAS-to-CAS delay (tRCDmin) LSB
+ 0x41, ///< 33 Minimum RAS-to-CAS delay (tRCDmin) MSB
+ 0x1E, ///< 34 Minimum Row Precharge delay (tRPmin) LSB
+ 0x41, ///< 35 Minimum Row Precharge delay (tRPmin) MSB
+ 0x00, ///< 36 Minimum Active to Precharge delay (tRASmin) LSB
+ 0x7D, ///< 37 Minimum Active to Precharge delay (tRASmin) MSB
+ 0x1E, ///< 38 Minimum Active to Active/Refresh delay (tRCmin) LSB
+ 0xBE, ///< 39 Minimum Active to Active/Refresh delay (tRCmin) MSB
+ 0x30, ///< 40 Minimum Write Recovery time (tWRmin) LSB
+ 0x75, ///< 41 Minimum Write Recovery time (tWRmin) MSB
+ 0x27, ///< 42 Refresh Recovery Delay (tRFC1min) LSB
+ 0x01, ///< 43 Refresh Recovery Delay (tRFC1min) MSB
+ 0xA0, ///< 44 Refresh Recovery Delay (tRFC2min) MSB
+ 0x00, ///< 45 Refresh Recovery Delay (tRFC2min) MSB
+ 0x82, ///< 46 Refresh Recovery Delay (tRFCsbmin) MSB
+ 0x00, ///< 47 Refresh Recovery Delay (tRFCsbmin) MSB
+ 0, 0, ///< 48 - 49
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 50 - 59
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 60 - 69
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 70 - 79
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 80 - 89
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 90 - 99
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 100 - 109
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 110 - 119
+ 0, 0, 0, 0, 0, 0, ///< 120 - 125
+ 0x47, ///< 126 CRC Bytes 0 - 127 LSB
+ 0xAE, ///< 127 CRC Bytes 0 - 127 MSB
+ 0, 0, ///< 128 - 129
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 130 - 139
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 140 - 149
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 150 - 159
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 160 - 169
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 170 - 179
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 180 - 189
+ 0, 0, ///< 190 - 191
+ 0x08, ///< 192 SPD Revision for Module Information: 0.8
+ 0x00, ///< 193 Reserved
+ 0xC2, ///< 194 SPD Manufacturer ID First Byte
+ 0xC4, ///< 195 SPD Manufacturer ID Second Byte
+ 0x80, ///< 196 SPD Device Type
+ 0x00, ///< 197 SPD Device Revision
+ 0x80, ///< 198 PMIC0 Manufacturer ID First Byte
+ 0xB3, ///< 199 PMIC0 Manufacturer ID Second Byte
+ 0x80, ///< 200 PMIC0 Device Type
+ 0x11, ///< 201 PMIC0 Device Revision
+ 0, 0, 0, 0, ///< 202 - 205 PMIC1
+ 0, 0, 0, 0, ///< 206 - 209 PMIC2
+ 0x80, ///< 210 Thermal Sensors Manufacturer ID First Byte
+ 0xB3, ///< 211 Thermal Sensors Manufacturer ID First Byte
+ 0x80, ///< 212 Thermal Sensors Device Type
+ 0x11, ///< 213 Thermal Sensors Device Revision
+ 0, 0, 0, 0, 0, 0, ///< 214 - 219
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 220 - 229
+ 0x0F, ///< 230 Module Nominal Height
+ 0x10, ///< 231 Module Nominal Thickness
+ 0x00, ///< 232 Reference Raw Card Used
+ 0x01, ///< 233 1 Row of DRAM on Module
+ 0x01, ///< 234 1 Rank, 8 bits SDRAM data width per channel
+ 0x22, ///< 235 2 Channels per DIMM, 32 bits per Channel
+ 0, 0, 0, 0, ///< 236 - 239
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 240 - 249
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 250 - 259
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 260 - 269
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 270 - 279
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 280 - 289
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 290 - 299
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 300 - 309
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 310 - 319
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 320 - 329
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 330 - 339
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 340 - 349
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 350 - 359
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 360 - 369
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 370 - 379
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 380 - 389
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 390 - 399
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 400 - 409
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 410 - 419
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 420 - 429
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 430 - 439
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ///< 440 - 445
+ 0x9C, ///< 446 CRC for Bytes 128 - 253 LSB
+ 0xAD, ///< 447 CRC for Bytes 128 - 253 MSB
+ 0, 0, ///< 448 - 449
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 450 - 459
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 460 - 469
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 470 - 479
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 480 - 489
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 490 - 499
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 500 - 509
+ 0, 0 ///< 510 - 511
+ ///< Ignore bytes 512-1023, @todo_adl: support 1024 bytes SPD array
+}})}
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/SBCVpdStructurePcd/PcieClocks/AdlPPcieClocks.dsc b/Platform/Intel/AlderlakeOpenBoardPkg/SBCVpdStructurePcd/PcieClocks/AdlPPcieClocks.dsc
new file mode 100644
index 0000000000..9871bb0c87
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/SBCVpdStructurePcd/PcieClocks/AdlPPcieClocks.dsc
@@ -0,0 +1,32 @@
+## @file
+# Alderlake P Pcie Clock configuration file.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+
+[PcdsDynamicExVpd.common.SkuIdAdlPDdr5Rvp]
+gBoardModuleTokenSpaceGuid.VpdPcdPcieClkUsageMap|*|{CODE(
+{{
+ PCIE_PEG, // CPU M.2 SSD 1
+ PCIE_PCH + 8, // PCH M.2 SSD
+ PCIE_PCH + 4,
+ PCIE_PEG + 1, // X8 DG/DG2
+ PCIE_PEG + 2, // CPU M.2 SSD 2
+ PCIE_PCH + 5, // M.2 KEY B WWAN - PCIe P6
+ LAN_CLOCK,
+ // Default Case:
+ // - PCIe P7 mapped to GBELAN
+ // - PCIe P8 mapped to x4 PCIe DT Slot (Pair 1)
+ PCIE_PCH + 7, // x4 PCIe DT Slot (x1)
+ // Reworked Case: with rework and soft strap changes
+ // - PCIe P7 mapped to x4 PCIe DT Slot (Pair 2)
+ // - PCIe P8 mapped to x4 PCIe DT Slot (Pair 1)
+ // @todo: To support reworked case, enable the below code.
+ // PCIE_PCH + 6, // x4 PCIe DT Slot (x2)
+ NOT_USED,
+ NOT_USED
+}}
+)}
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/SmmMultiBoardAcpiSupportLib/SmmAcpiEnableLib.c b/Platform/Intel/AlderlakeOpenBoardPkg/SmmMultiBoardAcpiSupportLib/SmmAcpiEnableLib.c
new file mode 100644
index 0000000000..d5a51cbc14
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/SmmMultiBoardAcpiSupportLib/SmmAcpiEnableLib.c
@@ -0,0 +1,51 @@
+/** @file
+ SMM Board ACPI Enable Library
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Base.h>
+#include <Uefi.h>
+#include <PiDxe.h>
+#include <Library/BaseLib.h>
+#include <Library/IoLib.h>
+#include <Library/BoardAcpiTableLib.h>
+#include <Library/PcdLib.h>
+#include <Library/DebugLib.h>
+#include <PlatformBoardId.h>
+
+/**
+ Enable Board Acpi
+
+ @param[in] EnableSci Enable SCI if EnableSci parameters is True.
+
+ @retval EFI_SUCCESS The function always return successfully.
+**/
+EFI_STATUS
+EFIAPI
+BoardEnableAcpi (
+ IN BOOLEAN EnableSci
+ )
+{
+ // @todo:enable additional board register
+ return EFI_SUCCESS;
+}
+
+/**
+ Disable Board Acpi
+
+ @param[in] DisableSci Disable SCI if DisableSci parameters is True.
+
+ @retval EFI_SUCCESS The function always return successfully.
+**/
+EFI_STATUS
+EFIAPI
+BoardDisableAcpi (
+ IN BOOLEAN DisableSci
+ )
+{
+ // @todo: enable additional board register
+ return EFI_SUCCESS;
+}
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/SmmMultiBoardAcpiSupportLib/SmmMultiBoardAcpiSupportLib.c b/Platform/Intel/AlderlakeOpenBoardPkg/SmmMultiBoardAcpiSupportLib/SmmMultiBoardAcpiSupportLib.c
new file mode 100644
index 0000000000..c278409e7b
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/SmmMultiBoardAcpiSupportLib/SmmMultiBoardAcpiSupportLib.c
@@ -0,0 +1,89 @@
+/** @file
+ SMM Multi-Board ACPI Support Library
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Base.h>
+#include <Uefi.h>
+#include <PiDxe.h>
+#include <Library/BaseLib.h>
+#include <Library/IoLib.h>
+#include <Library/BoardAcpiEnableLib.h>
+#include <Library/MultiBoardAcpiSupportLib.h>
+#include <Library/PcdLib.h>
+#include <Library/DebugLib.h>
+
+#include <PlatformBoardId.h>
+
+EFI_STATUS
+EFIAPI
+BoardEnableAcpi (
+ IN BOOLEAN EnableSci
+ );
+
+EFI_STATUS
+EFIAPI
+BoardDisableAcpi (
+ IN BOOLEAN DisableSci
+ );
+
+EFI_STATUS
+EFIAPI
+SiliconEnableAcpi (
+ IN BOOLEAN EnableSci
+ );
+
+EFI_STATUS
+EFIAPI
+SiliconDisableAcpi (
+ IN BOOLEAN DisableSci
+ );
+
+EFI_STATUS
+EFIAPI
+MultiBoardEnableAcpi (
+ IN BOOLEAN EnableSci
+ )
+{
+ SiliconEnableAcpi (EnableSci);
+ return BoardEnableAcpi (EnableSci);
+}
+
+EFI_STATUS
+EFIAPI
+MultiBoardDisableAcpi (
+ IN BOOLEAN DisableSci
+ )
+{
+ SiliconDisableAcpi (DisableSci);
+ return BoardDisableAcpi (DisableSci);
+}
+
+BOARD_ACPI_ENABLE_FUNC mBoardAcpiEnableFunc = {
+ MultiBoardEnableAcpi,
+ MultiBoardDisableAcpi,
+};
+
+/**
+ The constructor function to register mBoardAcpiEnableFunc function.
+
+ @param[in] ImageHandle The firmware allocated handle for the EFI image.
+ @param[in] SystemTable A pointer to the EFI System Table.
+
+ @retval EFI_SUCCESS This constructor always return EFI_SUCCESS.
+ It will ASSERT on errors.
+**/
+EFI_STATUS
+EFIAPI
+SmmMultiBoardAcpiSupportLibConstructor (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ DEBUG ((DEBUG_INFO, "SKU_ID: 0x%x\n", LibPcdGetSku()));
+ return RegisterBoardAcpiEnableFunc (&mBoardAcpiEnableFunc);
+}
+
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/SmmMultiBoardAcpiSupportLib/SmmMultiBoardAcpiSupportLib.inf b/Platform/Intel/AlderlakeOpenBoardPkg/SmmMultiBoardAcpiSupportLib/SmmMultiBoardAcpiSupportLib.inf
new file mode 100644
index 0000000000..ecea111b41
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/SmmMultiBoardAcpiSupportLib/SmmMultiBoardAcpiSupportLib.inf
@@ -0,0 +1,40 @@
+### @file
+# SMM Multi-Board ACPI Support Library
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+###
+
+[Defines]
+ INF_VERSION = 0x00010017
+ BASE_NAME = SmmMultiBoardAcpiSupportLib
+ FILE_GUID = 8929A54E-7ED8-4AB3-BEBB-C0367BDBBFF5
+ VERSION_STRING = 1.0
+ MODULE_TYPE = DXE_SMM_DRIVER
+ LIBRARY_CLASS = NULL
+ CONSTRUCTOR = SmmMultiBoardAcpiSupportLibConstructor
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = IA32 X64 IPF EBC
+#
+
+[LibraryClasses]
+ BaseLib
+ IoLib
+ PciLib
+ PchCycleDecodingLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ MinPlatformPkg/MinPlatformPkg.dec
+ AlderlakeOpenBoardPkg/OpenBoardPkg.dec
+ AlderlakeSiliconPkg/SiPkg.dec
+
+[Sources]
+ SmmAcpiEnableLib.c
+ SmmSiliconAcpiEnableLib.c
+ SmmMultiBoardAcpiSupportLib.c
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/SmmMultiBoardAcpiSupportLib/SmmSiliconAcpiEnableLib.c b/Platform/Intel/AlderlakeOpenBoardPkg/SmmMultiBoardAcpiSupportLib/SmmSiliconAcpiEnableLib.c
new file mode 100644
index 0000000000..38390305c4
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/SmmMultiBoardAcpiSupportLib/SmmSiliconAcpiEnableLib.c
@@ -0,0 +1,157 @@
+/** @file
+ SMM Silicon ACPI Support Library
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Base.h>
+#include <Uefi.h>
+#include <PiDxe.h>
+#include <Library/BaseLib.h>
+#include <Library/SmmServicesTableLib.h>
+#include <Library/IoLib.h>
+#include <Library/BoardAcpiEnableLib.h>
+#include <Library/PcdLib.h>
+#include <Library/DebugLib.h>
+#include <Library/PciSegmentLib.h>
+#include <Library/PchCycleDecodingLib.h>
+#include <Library/PmcLib.h>
+#include <Register/PchRegs.h>
+#include <Register/PchRegsLpc.h>
+#include <Register/PmcRegs.h>
+#include <Register/RtcRegs.h>
+#include <Library/PchPciBdfLib.h>
+
+//
+// Global variables
+//
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_SMM_SYSTEM_TABLE2 *mSmst;
+
+GLOBAL_REMOVE_IF_UNREFERENCED UINT16 mAcpiBaseAddr;
+
+/**
+
+**/
+EFI_STATUS
+EFIAPI
+SiliconEnableAcpi (
+ IN BOOLEAN EnableSci
+ )
+{
+ UINT32 OutputValue;
+ UINT32 SmiEn;
+ UINT32 SmiSts;
+ UINT32 ULKMC;
+ UINT32 Pm1Cnt;
+ EFI_STATUS Status;
+ UINT64 LpcBaseAddress;
+
+ LpcBaseAddress = LpcPciCfgBase ();
+
+ //
+ // Initialize global variables
+ //
+ mSmst = gSmst;
+
+ //
+ // Get the ACPI Base Address
+ //
+ mAcpiBaseAddr = PmcGetAcpiBase ();
+
+ Status = EFI_SUCCESS;
+ //
+ // BIOS must also ensure that CF9GR is cleared and locked before handing control to the
+ // OS in order to prevent the host from issuing global resets and resetting ME
+ //
+ // EDK2: To match PCCG current BIOS behavior, do not lock CF9 Global Reset
+ // MmioWrite32 (
+ // PmcBaseAddress + R_PCH_PMC_ETR3),
+ // PmInit);
+
+ //
+ // Clear Port 80h
+ //
+ OutputValue = 0;
+ mSmst->SmmIo.Io.Write (&mSmst->SmmIo, SMM_IO_UINT16, 0x80, 1, &OutputValue);
+ //
+ // Disable SW SMI Timer and clean the status
+ //
+ mSmst->SmmIo.Io.Read (&mSmst->SmmIo, SMM_IO_UINT32, mAcpiBaseAddr + R_ACPI_IO_SMI_EN, 1, &SmiEn);
+ SmiEn &= ~(B_ACPI_IO_SMI_EN_LEGACY_USB2 | B_ACPI_IO_SMI_EN_SWSMI_TMR | B_ACPI_IO_SMI_EN_LEGACY_USB);
+ mSmst->SmmIo.Io.Write (&mSmst->SmmIo, SMM_IO_UINT32, mAcpiBaseAddr + R_ACPI_IO_SMI_EN, 1, &SmiEn);
+
+ mSmst->SmmIo.Io.Read (&mSmst->SmmIo, SMM_IO_UINT32, mAcpiBaseAddr + R_ACPI_IO_SMI_STS, 1, &SmiSts);
+ SmiSts |= B_ACPI_IO_SMI_EN_LEGACY_USB2 | B_ACPI_IO_SMI_EN_SWSMI_TMR | B_ACPI_IO_SMI_EN_LEGACY_USB;
+ mSmst->SmmIo.Io.Write (&mSmst->SmmIo, SMM_IO_UINT32, mAcpiBaseAddr + R_ACPI_IO_SMI_STS, 1, &SmiSts);
+
+ //
+ // Disable port 60/64 SMI trap if they are enabled
+ //
+ ULKMC = PciSegmentRead32 (LpcBaseAddress + R_LPC_CFG_ULKMC);
+ ULKMC &= ~(B_LPC_CFG_ULKMC_60REN | B_LPC_CFG_ULKMC_60WEN | B_LPC_CFG_ULKMC_64REN | B_LPC_CFG_ULKMC_64WEN | B_LPC_CFG_ULKMC_A20PASSEN);
+ PciSegmentWrite32 (LpcBaseAddress + R_LPC_CFG_ULKMC, ULKMC);
+
+ //
+ // Disable PM sources except power button
+ //
+ OutputValue = B_ACPI_IO_PM1_EN_PWRBTN;
+ mSmst->SmmIo.Io.Write (&mSmst->SmmIo, SMM_IO_UINT16, mAcpiBaseAddr + R_ACPI_IO_PM1_EN, 1, &OutputValue);
+ //
+ // Clear PM status except Power Button status for RapidStart Resume
+ //
+ // OutputValue = 0xFFFF;
+ OutputValue = 0xFEFF;
+ mSmst->SmmIo.Io.Write (&mSmst->SmmIo, SMM_IO_UINT16, mAcpiBaseAddr + R_ACPI_IO_PM1_STS, 1, &OutputValue);
+
+ //
+ // Guarantee day-of-month alarm is invalid (ACPI 1.0 section 4.7.2.4)
+ //
+ OutputValue = R_RTC_IO_REGD;
+ mSmst->SmmIo.Io.Write (&mSmst->SmmIo, SMM_IO_UINT8, R_RTC_IO_INDEX_ALT, 1, &OutputValue);
+ OutputValue = 0x0;
+ mSmst->SmmIo.Io.Write (&mSmst->SmmIo, SMM_IO_UINT8, R_RTC_IO_TARGET_ALT, 1, &OutputValue);
+
+ //
+ // Enable SCI
+ //
+ if (EnableSci) {
+ mSmst->SmmIo.Io.Read (&mSmst->SmmIo, SMM_IO_UINT32, mAcpiBaseAddr + R_ACPI_IO_PM1_CNT, 1, &Pm1Cnt);
+ Pm1Cnt |= B_ACPI_IO_PM1_CNT_SCI_EN;
+ mSmst->SmmIo.Io.Write (&mSmst->SmmIo, SMM_IO_UINT32, mAcpiBaseAddr + R_ACPI_IO_PM1_CNT, 1, &Pm1Cnt);
+ }
+
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+EFIAPI
+SiliconDisableAcpi (
+ IN BOOLEAN DisableSci
+ )
+{
+ UINT32 Pm1Cnt;
+
+ //
+ // Initialize global variables
+ //
+ mSmst = gSmst;
+
+ //
+ // Get the ACPI Base Address
+ //
+ mAcpiBaseAddr = PmcGetAcpiBase ();
+
+
+ //
+ // Disable SCI
+ //
+ if (DisableSci) {
+ mSmst->SmmIo.Io.Read (&mSmst->SmmIo, SMM_IO_UINT32, mAcpiBaseAddr + R_ACPI_IO_PM1_CNT, 1, &Pm1Cnt);
+ Pm1Cnt &= ~B_ACPI_IO_PM1_CNT_SCI_EN;
+ mSmst->SmmIo.Io.Write (&mSmst->SmmIo, SMM_IO_UINT32, mAcpiBaseAddr + R_ACPI_IO_PM1_CNT, 1, &Pm1Cnt);
+ }
+
+ return EFI_SUCCESS;
+}
--
2.36.1.windows.1
next prev parent reply other threads:[~2023-06-14 19:17 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <cover.1686770061.git.saloni.kasbekar@intel.com>
2023-06-14 19:17 ` [PATCH 1/6] AlderlakeOpenBoardPkg: Add package and headers Saloni Kasbekar
2023-06-14 19:17 ` Saloni Kasbekar [this message]
2023-06-14 19:17 ` [PATCH 3/6] AlderlakeOpenBoardPkg/AlderlakePRvp: Add library instances Saloni Kasbekar
2023-06-14 19:17 ` [PATCH 4/6] AlderlakeOpenBoardPkg: Add ACPI module Saloni Kasbekar
2023-06-14 19:17 ` [PATCH 5/6] AlderlakeOpenBoardPkg: Adds the Policy Module Saloni Kasbekar
2023-06-14 19:17 ` [PATCH 6/6] AlderlakeOpenBoardPkg: Add Library Instances Saloni Kasbekar
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