* [PATCH 1/6] AlderlakeOpenBoardPkg: Add package and headers
[not found] <cover.1686770061.git.saloni.kasbekar@intel.com>
@ 2023-06-14 19:17 ` Saloni Kasbekar
2023-06-14 19:17 ` [PATCH 2/6] AlderlakeOpenBoardPkg: Add modules Saloni Kasbekar
` (4 subsequent siblings)
5 siblings, 0 replies; 6+ messages in thread
From: Saloni Kasbekar @ 2023-06-14 19:17 UTC (permalink / raw)
To: devel
Cc: Saloni Kasbekar, Sai Chaganty, Nate DeSimone, Isaac Oram,
Rosen Chuang
Create the AlderlakeOpenBoardPkg to provide board support code. The
package may support Alderlake boards. The package serves as a board
support package in the EDK II Minimum Platform design.
Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Isaac Oram <isaac.w.oram@intel.com>
Cc: Rosen Chuang <rosen.chuang@intel.com>
Signed-off-by: Saloni Kasbekar <saloni.kasbekar@intel.com>
---
.../Include/Library/BoardConfigLib.h | 157 ++++
.../Include/Library/DxeAcpiGnvsInitLib.h | 26 +
.../Include/Library/PeiGetFvInfoLib.h | 29 +
.../Include/Library/PeiPolicyBoardConfigLib.h | 108 +++
.../Include/Library/SpiFlashCommon.h | 99 +++
.../AlderlakeOpenBoardPkg/Include/Platform.h | 24 +
.../Include/PlatformBoardConfig.h | 130 +++
.../Include/PlatformBoardId.h | 30 +
.../Include/PlatformBoardType.h | 15 +
.../Include/PlatformGpioConfig.h | 18 +
.../Include/PlatformNvsAreaDef.h | 751 ++++++++++++++++++
.../Include/PlatformPostCode.h | 39 +
.../Include/PolicyUpdateMacro.h | 48 ++
.../Include/Protocol/PlatformNvsArea.h | 36 +
.../AlderlakeOpenBoardPkg/OpenBoardPkg.dec | 605 ++++++++++++++
15 files changed, 2115 insertions(+)
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Include/Library/BoardConfigLib.h
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Include/Library/DxeAcpiGnvsInitLib.h
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Include/Library/PeiGetFvInfoLib.h
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Include/Library/PeiPolicyBoardConfigLib.h
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Include/Library/SpiFlashCommon.h
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Include/Platform.h
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Include/PlatformBoardConfig.h
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Include/PlatformBoardId.h
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Include/PlatformBoardType.h
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Include/PlatformGpioConfig.h
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Include/PlatformNvsAreaDef.h
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Include/PlatformPostCode.h
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Include/PolicyUpdateMacro.h
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Include/Protocol/PlatformNvsArea.h
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/OpenBoardPkg.dec
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Include/Library/BoardConfigLib.h b/Platform/Intel/AlderlakeOpenBoardPkg/Include/Library/BoardConfigLib.h
new file mode 100644
index 0000000000..e782028bed
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Include/Library/BoardConfigLib.h
@@ -0,0 +1,157 @@
+/** @file
+ Function prototype of BoardConfigLib.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _BOARD_CONFIG_LIB_H_
+#define _BOARD_CONFIG_LIB_H_
+
+#include <Library/GpioLib.h>
+#include <PlatformBoardConfig.h>
+
+#define SIZE_OF_FIELD(TYPE, Field) (sizeof (((TYPE *)0)->Field))
+
+#define SIZE_OF_TABLE(TABLE, TYPE) (sizeof (TABLE) / sizeof (TYPE))
+
+//
+// @todo Define BOARD_CONFIG
+//
+#define BOARD_CONFIG PLATFORM_INFO
+
+#define PRE_MEM 0
+#define POST_MEM 1
+#define EARLY_PRE_MEM 2
+
+/**
+ Procedure to detect current board HW configuration.
+
+**/
+VOID
+EFIAPI
+GetBoardConfig (
+ VOID
+ );
+
+
+/**
+ Count the number of GPIO settings in the Table.
+
+ @param[in] GpioTable The pointer of GPIO config table
+ @param[out] GpioCount The number of GPIO config entries
+**/
+VOID
+GetGpioTableSize (
+ GPIO_INIT_CONFIG *GpioTable,
+ OUT UINT16 *GpioCount
+ );
+
+/**
+ Configure GPIO Table setting to PcdBoardGpioTablePreMem && PcdBoardGpioTable
+
+ @param[in] GpioTable The pointer of GPIO config table
+ @param[in] IsPostMem Is call from PostMem/PreMem
+ True - PostMem, False - PreMem
+**/
+VOID
+ConfigureGpioTabletoPCD(
+ IN GPIO_INIT_CONFIG *GpioTable,
+ IN UINT16 IsPostMem
+ );
+
+/**
+ Configure GPIO pads in PEI phase.
+
+ @param[in] GpioTable Pointer to Gpio table
+**/
+VOID
+GpioInit (
+ IN GPIO_INIT_CONFIG *GpioTable
+ );
+
+/**
+ Check if given rootport has device connected and enable wake capability
+
+ @param[in] RpNum An unsigned integer represent the root port number.
+
+ @retval TRUE if endpoint was connected
+ @retval FALSE if no endpoint was detected
+**/
+BOOLEAN
+IsPcieEndPointPresent (
+ IN UINT8 RpNum
+ );
+
+// LPDDR4 200b 8Gb die, DDP, 2 channels per die, x16
+// Samsung K4F6E304Hx-MGCJ
+// or Hynix H9HCNNNBUUxLHR-NMx
+// or Micron MT53B512M32D2NP-053
+// 3733, 32-34-34-79
+// 2 ranks per channel, 2 SDRAMs per channel, 2x2x8Gb = 4GB total per channel
+extern const UINT8 mLpddr4Ddp8Gb200bSpd;
+
+// LPDDR4X 432b 16Gb die, QDP 2x16
+// Samsung K3UH7H70MM-JGCJ
+// 3733, 32-34-34-79
+// 2 ranks per channel, 1 SDRAMs per rank, 4x16Gb = 8GB total per channel
+extern const UINT8 mLpddr4xQdp16Gb432bSpd;
+
+// LPDDR4X 556b 8Gb die, ODP, 1 channel per die, x16
+// Micron MT53D1G64D8SQ-046
+// 4266
+// 2 ranks per channel, 2 SDRAMs per channel, 2x4x8Gb = 8GB total per channel
+extern const UINT8 mLpddr4xOdp8Gb556bSpd;
+
+// LPDDR4X 556b 4Gb die, QDP, 1 channel per die, x16
+// Micron MT53D512M64D4RQ-046 WT:E
+// 4266
+// 2 ranks per channel, 2 SDRAMs per channel, 2x4x8Gb = 4GB total per channel
+extern const UINT8 mLpddr4xQdp4Gb556bSpd;
+
+extern const UINT8 mLpddr4Ddp16Gb200b1rSpd;
+
+// LPDDR5 496b 12Gb die, QDP 1x16
+// Samsung K3LK2K20BM-BGCN
+// 5500, ??-??-??-??
+// 16 Banks, 4 bank groups, 12Gb SDRAM density
+// 16 Row bits, 10 Column bits
+// Non-Monolithic DRAM Device, 4 dies, 4 Channels per die,
+extern const UINT8 mLpddr5xQdp12Gb496bSpd;
+
+// LPDDR4X 200b 16Gb die, DDP, 2 channel per die, 2x8
+// Samsung K4U6E3S4AA-MGCL
+// 4267, 36-39-39-90
+// 1 rank per channel, 2 SDRAMs per channel, 2x8GB = 16GB total per channel
+extern const UINT8 mLpddr4xDdp16Gb200bSpd;
+
+// LPDDR4X 200b 16Gb die, 2 channel per die, 2x8
+// Micron MT53E1G32D4NQ-046
+// 3200
+extern const UINT8 mLpddr4xQdp16Gb200bSpd;
+
+// LPDDR4X 200b 8Gb die, 4 die, 2 Channels per package
+// Micron MT53E1G32D4NQ-046
+// 4267
+extern const UINT8 mLpddr4xQdp8Gb200b2r4267Spd;
+
+extern const UINT8 mDdr5Spd_1Rx8[];
+extern const UINT8 mDdr5Spd_2Rx8[];
+
+// Default USB2 OC mapping
+extern USB_OC_MAP_TABLE mUsb2OverCurrentMappingTable;
+// Default USB3 OC mapping
+extern USB_OC_MAP_TABLE mUsb3OverCurrentMappingTable;
+
+/**
+ Update Cpu Xhci Port Enable Map PCD from SaSetup data.
+
+**/
+VOID
+EFIAPI
+TcssUpdateCpuXhciPortEnableMapPcd (
+ VOID
+ );
+
+#endif // _BOARD_CONFIG_LIB_H_
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Include/Library/DxeAcpiGnvsInitLib.h b/Platform/Intel/AlderlakeOpenBoardPkg/Include/Library/DxeAcpiGnvsInitLib.h
new file mode 100644
index 0000000000..2695bd4eec
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Include/Library/DxeAcpiGnvsInitLib.h
@@ -0,0 +1,26 @@
+/** @file
+ Acpi Gnvs Init Library header file.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Base.h>
+
+
+/**
+@brief
+ Global NVS initialize.
+
+ @param[in] PlatformNvsAreaPtr - Pointer of global NVS area
+
+ @retval EFI_SUCCESS - Allocate Global NVS completed.
+ @retval EFI_OUT_OF_RESOURCES - Failed to allocate required page for PlatformNvsAreaProtocol.
+**/
+EFI_STATUS
+EFIAPI
+AcpiGnvsInit (
+ IN OUT VOID **PlatformNvsAreaPtr
+ );
+
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Include/Library/PeiGetFvInfoLib.h b/Platform/Intel/AlderlakeOpenBoardPkg/Include/Library/PeiGetFvInfoLib.h
new file mode 100644
index 0000000000..5ec9c47b4e
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Include/Library/PeiGetFvInfoLib.h
@@ -0,0 +1,29 @@
+/** @file
+ Header file for PeiGetFvInfoLib..
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _PEI_GET_FV_INFO_LIB_H_
+#define _PEI_GET_FV_INFO_LIB_H_
+
+/**
+ PeiGetSectionFromFv finds the file in FV and gets file Address and Size
+
+ @param[in] NameGuid - File GUID
+ @param[out] Address - Pointer to the File Address
+ @param[out] Size - Pointer to File Size
+
+ @retval EFI_SUCCESS Successfull in reading the section from FV
+**/
+EFI_STATUS
+EFIAPI
+PeiGetSectionFromFv (
+ IN CONST EFI_GUID NameGuid,
+ OUT VOID **Address,
+ OUT UINT32 *Size
+ );
+
+#endif
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Include/Library/PeiPolicyBoardConfigLib.h b/Platform/Intel/AlderlakeOpenBoardPkg/Include/Library/PeiPolicyBoardConfigLib.h
new file mode 100644
index 0000000000..1de17dabd2
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Include/Library/PeiPolicyBoardConfigLib.h
@@ -0,0 +1,108 @@
+/** @file
+ Header file for the PeiPolicyBoardConfig Library.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+#ifndef _PEI_POLICY_BOARD_CONFIG_LIB_H_
+#define _PEI_POLICY_BOARD_CONFIG_LIB_H_
+
+
+/**
+ This function performs PEI CPU Pre-Memory Policy update by board configuration.
+
+ @retval EFI_SUCCESS The SI Policy is successfully updated.
+ @retval Others The SI Policy is not successfully updated.
+**/
+EFI_STATUS
+EFIAPI
+UpdatePeiCpuPolicyBoardConfigPreMem (
+ VOID
+ );
+
+/**
+ This function performs PEI ME Pre-Memory Policy update by board configuration.
+
+ @retval EFI_SUCCESS The SI Policy is successfully updated.
+ @retval Others The SI Policy is not successfully updated.
+**/
+EFI_STATUS
+EFIAPI
+UpdatePeiMePolicyBoardConfigPreMem (
+ VOID
+ );
+
+/**
+ This function performs PEI PCH Pre-Memory Policy update by board configuration.
+
+ @retval EFI_SUCCESS The SI Policy is successfully updated.
+ @retval Others The SI Policy is not successfully updated.
+**/
+EFI_STATUS
+EFIAPI
+UpdatePeiPchPolicyBoardConfigPreMem (
+ VOID
+ );
+
+/**
+ This function performs PEI SA Pre-Memory Policy update by board configuration.
+
+ @retval EFI_SUCCESS The SI Policy is successfully updated.
+ @retval Others The SI Policy is not successfully updated.
+**/
+EFI_STATUS
+EFIAPI
+UpdatePeiSaPolicyBoardConfigPreMem (
+ VOID
+ );
+
+/**
+ This function performs PEI ME Policy update by board configuration.
+
+ @retval EFI_SUCCESS The SI Policy is successfully updated.
+ @retval Others The SI Policy is not successfully updated.
+**/
+EFI_STATUS
+EFIAPI
+UpdatePeiMePolicyBoardConfig (
+ VOID
+ );
+
+/**
+ This function performs PEI SA Policy update by board configuration.
+
+ @retval EFI_SUCCESS The SI Policy is successfully updated.
+ @retval Others The SI Policy is not successfully updated.
+**/
+EFI_STATUS
+EFIAPI
+UpdatePeiSaPolicyBoardConfig (
+ VOID
+ );
+
+/**
+ This function performs PEI TBT Policy update by board configuration.
+
+ @retval EFI_SUCCESS The SI Policy is successfully updated.
+ @retval Others The SI Policy is not successfully updated.
+**/
+EFI_STATUS
+EFIAPI
+UpdatePeiTbtPolicyBoardConfig (
+ VOID
+ );
+
+/**
+ This function performs PEI SI Policy update by board configuration.
+
+ @retval EFI_SUCCESS The SI Policy is successfully updated.
+ @retval Others The SI Policy is not successfully updated.
+**/
+EFI_STATUS
+EFIAPI
+UpdatePeiSiPolicyBoardConfig (
+ VOID
+ );
+
+#endif
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Include/Library/SpiFlashCommon.h b/Platform/Intel/AlderlakeOpenBoardPkg/Include/Library/SpiFlashCommon.h
new file mode 100644
index 0000000000..685d2b95a3
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Include/Library/SpiFlashCommon.h
@@ -0,0 +1,99 @@
+/** @file
+ The header file includes the common header files, defines
+ internal structure and functions used by SpiFlashCommonLib.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __SPI_FLASH_COMMON_H__
+#define __SPI_FLASH_COMMON_H__
+
+#include <Uefi.h>
+#include <Library/BaseLib.h>
+#include <Library/PcdLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/UefiDriverEntryPoint.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Protocol/Spi.h>
+
+#define SECTOR_SIZE_4KB 0x1000 // Common 4kBytes sector size
+/**
+ Enable block protection on the Serial Flash device.
+
+ @retval EFI_SUCCESS Opertion is successful.
+ @retval EFI_DEVICE_ERROR If there is any device errors.
+
+**/
+EFI_STATUS
+EFIAPI
+SpiFlashLock (
+ VOID
+ );
+
+/**
+ Read NumBytes bytes of data from the address specified by
+ PAddress into Buffer.
+
+ @param[in] Address The starting physical address of the read.
+ @param[in,out] NumBytes On input, the number of bytes to read. On output, the number
+ of bytes actually read.
+ @param[out] Buffer The destination data buffer for the read.
+
+ @retval EFI_SUCCESS Opertion is successful.
+ @retval EFI_DEVICE_ERROR If there is any device errors.
+
+**/
+EFI_STATUS
+EFIAPI
+SpiFlashRead (
+ IN UINTN Address,
+ IN OUT UINT32 *NumBytes,
+ OUT UINT8 *Buffer
+ );
+
+/**
+ Write NumBytes bytes of data from Buffer to the address specified by
+ PAddresss.
+
+ @param[in] Address The starting physical address of the write.
+ @param[in,out] NumBytes On input, the number of bytes to write. On output,
+ the actual number of bytes written.
+ @param[in] Buffer The source data buffer for the write.
+
+ @retval EFI_SUCCESS Opertion is successful.
+ @retval EFI_DEVICE_ERROR If there is any device errors.
+
+**/
+EFI_STATUS
+EFIAPI
+SpiFlashWrite (
+ IN UINTN Address,
+ IN OUT UINT32 *NumBytes,
+ IN UINT8 *Buffer
+ );
+
+/**
+ Erase the block starting at Address.
+
+ @param[in] Address The starting physical address of the block to be erased.
+ This library assume that caller garantee that the PAddress
+ is at the starting address of this block.
+ @param[in] NumBytes On input, the number of bytes of the logical block to be erased.
+ On output, the actual number of bytes erased.
+
+ @retval EFI_SUCCESS. Opertion is successful.
+ @retval EFI_DEVICE_ERROR If there is any device errors.
+
+**/
+EFI_STATUS
+EFIAPI
+SpiFlashBlockErase (
+ IN UINTN Address,
+ IN UINTN *NumBytes
+ );
+
+#endif
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Include/Platform.h b/Platform/Intel/AlderlakeOpenBoardPkg/Include/Platform.h
new file mode 100644
index 0000000000..f4b15520c0
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Include/Platform.h
@@ -0,0 +1,24 @@
+/** @file
+ This header file provides platform specific definitions used
+ by other modules for platform specific initialization.
+ This is not suitable for consumption by ASL or VRF files.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _PLATFORM_H_
+#define _PLATFORM_H_
+
+
+//
+// Need minimum of 48MB during PEI phase for IAG and some buffer for boot.
+//
+#define PEI_MIN_MEMORY_SIZE (10 * 0x800000) // 80MB
+#define PEI_RECOVERY_MIN_MEMORY_SIZE (10 * 0x800000) // 80MB
+
+#define FLASH_BLOCK_SIZE 0x10000
+
+
+#endif
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Include/PlatformBoardConfig.h b/Platform/Intel/AlderlakeOpenBoardPkg/Include/PlatformBoardConfig.h
new file mode 100644
index 0000000000..d411dfc50c
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Include/PlatformBoardConfig.h
@@ -0,0 +1,130 @@
+/** @file
+ Header file for Platform Boards Configurations.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _PLATFORM_BOARD_CONFIG_H
+#define _PLATFORM_BOARD_CONFIG_H
+
+#include <ConfigBlock.h>
+#include <PchPolicyCommon.h>
+#include <MemoryConfig.h>
+#include <Library/GpioConfig.h>
+
+#define MAX_GPIO_PINS 130
+#define MAX_PRE_MEM_GPIO_PINS 60
+#define MAX_PMAX_DEVICE_STRING_LENGTH 31
+
+#define IS_ALIGNED(addr, size) (((addr) & (size - 1)) ? 0 : 1)
+#define ALIGN16(size) (IS_ALIGNED(size, 16) ? size : ((size + 16) & 0xFFF0))
+
+#define BOARD_REAL_BATTERY_SUPPORTED BIT0
+#define BOARD_VIRTUAL_BATTERY_SUPPORTED BIT1
+
+//
+// ACPI table information used to update tables thru PCD
+//
+#define ACPI_OEM_TABLE_ID_ADL_P_M 0x4D2D502D4C4441 //ADL-P-M
+
+//
+// GPIO states mapping
+//
+#define PIN_GPIO_ACTIVE_LOW 0
+#define PIN_GPIO_ACTIVE_HIGH 1
+
+//#
+//#
+
+#pragma pack(1)
+
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Block Header
+} BOARD_CONFIG_BLOCK;
+
+typedef struct {
+ UINT8 ClkReqNumber : 4;
+ UINT8 ClkReqSupported : 1;
+ UINT8 DeviceResetPadActiveHigh : 1;
+ UINT32 DeviceResetPad;
+} ROOT_PORT_CLK_INFO;
+
+typedef struct {
+ UINT8 Section;
+ UINT8 Pin;
+} EXPANDER_GPIO_CONFIG;
+
+typedef enum {
+ BoardGpioTypePch,
+ BoardGpioTypeExpander,
+ BoardGpioTypeNotSupported = 0xFF
+} BOARD_GPIO_TYPE;
+
+typedef struct {
+ UINT8 Type;
+ UINT8 Reserved[3]; // alignment for COMMON_GPIO_CONFIG
+ union {
+ UINT32 Pin;
+ EXPANDER_GPIO_CONFIG Expander;
+ } u;
+} BOARD_GPIO_CONFIG;
+
+// Do not change the encoding. It must correspond with PCH_PCIE_CLOCK_USAGE from PCH RC.
+#define NOT_USED 0xFF
+#define LAN_CLOCK 0x70
+#define PCIE_PEG 0x40
+#define PCIE_PCH 0x00
+
+typedef struct {
+ UINT32 ClockUsage;
+ UINT32 ClkReqSupported;
+} PCIE_CLOCK_CONFIG;
+
+typedef union {
+ UINT64 Blob;
+ BOARD_GPIO_CONFIG BoardGpioConfig;
+ ROOT_PORT_CLK_INFO Info;
+ PCIE_CLOCK_CONFIG PcieClock;
+} PCD64_BLOB;
+
+// Having Max CLK config to support both ADL P and ALD S
+#define PCH_MAX_PCIE_CLOCKS_SBC 18
+
+//seamless board configurations
+typedef struct {
+ UINT32 ClockUsage[PCH_MAX_PCIE_CLOCKS_SBC];
+} PCIE_CLOCKS_USAGE;
+
+#define SPD_DATA_SIZE 1024
+
+/**
+ This is a helper structure that's used to updating Config Block data according to board design
+**/
+#define USB_OC_MAX_PINS 16
+
+typedef struct {
+ UINT8 Size;
+ UINT8 Data[USB_OC_MAX_PINS];
+} USB_OC_MAP_TABLE;
+
+//SBC MRC DQS
+typedef struct {
+ UINT8 DqsMapCpu2Dram[8][2];
+} MRC_DQS;
+
+//SBC MRC DQ
+typedef struct {
+ UINT8 DqMapCpu2Dram[8][2][8];
+} MRC_DQ;
+
+//SBC SPD DATA
+typedef struct {
+ BOOLEAN OverrideSpd;
+ UINT8 SpdData[SPD_DATA_SIZE];
+} SPD_DATA;
+
+#pragma pack()
+
+#endif // _PLATFORM_BOARD_CONFIG_H
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Include/PlatformBoardId.h b/Platform/Intel/AlderlakeOpenBoardPkg/Include/PlatformBoardId.h
new file mode 100644
index 0000000000..eb72b1d9b2
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Include/PlatformBoardId.h
@@ -0,0 +1,30 @@
+/** @file
+Defines Platform BoardIds
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _PLATFORM_BOARD_ID_H_
+#define _PLATFORM_BOARD_ID_H_
+
+#define FlavorUnknown 0x0
+#define FlavorMobile 0x1
+#define FlavorDesktop 0x2
+#define FlavorWorkstation 0x3
+#define FlavorUpServer 0x4
+
+#define TypeUnknown 0x0
+#define TypeTrad 0x1
+#define TypeUltUlx 0x2
+//
+// Alderlake Sku IDs
+//
+#define SkuIdAdlPDdr5Rvp 0x000012
+#define AdlPSkuType 2
+
+// Alderlake P Board IDs
+#define BoardIdAdlPDdr5Rvp 0x12
+
+#endif // _PLATFORM_BOARD_ID_H_
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Include/PlatformBoardType.h b/Platform/Intel/AlderlakeOpenBoardPkg/Include/PlatformBoardType.h
new file mode 100644
index 0000000000..1d42f8a083
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Include/PlatformBoardType.h
@@ -0,0 +1,15 @@
+/** @file
+ BoardType used for Platform Info Data entries in the SBIOS/Setup/AcpiASL.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _PLATFORM_BOARD_TYPE_H_
+#define _PLATFORM_BOARD_TYPE_H_
+
+#define BoardTypeRvp 0x00 // Reference Validation Platform
+#define BoardTypeMax 0x0A
+
+#endif
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Include/PlatformGpioConfig.h b/Platform/Intel/AlderlakeOpenBoardPkg/Include/PlatformGpioConfig.h
new file mode 100644
index 0000000000..6384766917
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Include/PlatformGpioConfig.h
@@ -0,0 +1,18 @@
+/** @file
+Defines Platform GPIO Configuration Arrary
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Library/GpioLib.h>
+
+#ifndef _PLATFORM_GPIO_CONFIG_H_
+#define _PLATFORM_GPIO_CONFIG_H_
+
+typedef struct {
+ GPIO_INIT_CONFIG GpioConfig[0];
+} GPIO_INIT_CONFIG_ARRAY;
+
+#endif
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Include/PlatformNvsAreaDef.h b/Platform/Intel/AlderlakeOpenBoardPkg/Include/PlatformNvsAreaDef.h
new file mode 100644
index 0000000000..e65d3fa37c
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Include/PlatformNvsAreaDef.h
@@ -0,0 +1,751 @@
+/** @file
+ ACPI DSDT table
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+ // Define a Global region of ACPI NVS Region that may be used for any
+ // type of implementation. The starting offset and size will be fixed
+ // up by the System BIOS during POST. Note that the Size must be a word
+ // in size to be fixed up correctly.
+
+#ifndef _PLATFORM_NVS_AREA_DEF_H_
+#define _PLATFORM_NVS_AREA_DEF_H_
+
+#pragma pack (push,1)
+typedef struct {
+ //
+ // Miscellaneous Dynamic Registers:
+ //
+ UINT16 OperatingSystem; ///< Offset 0 Operating System
+ UINT8 SmiFunction; ///< Offset 2 SMI Function Call (ASL to SMI via I/O Trap)
+ UINT8 SmiParameter0; ///< Offset 3 SMIF - Parameter 0
+ UINT8 SmiParameter1; ///< Offset 4 SMIF - Parameter 1
+ UINT8 SciFunction; ///< Offset 5 SCI Function Call (SMI to ASL via _L00)
+ UINT8 SciParameter0; ///< Offset 6 SCIF - Parameter 0
+ UINT8 SciParameter1; ///< Offset 7 SCIF - Parameter 1
+ UINT8 GlobalLock; ///< Offset 8 Global Lock Function Call (EC Communication)
+ UINT8 LockParameter0; ///< Offset 9 LCKF - Parameter 0
+ UINT8 LockParameter1; ///< Offset 10 LCKF - Parameter 1
+ UINT8 PowerState; ///< Offset 11 Power State (AC Mode = 1)
+ UINT8 DebugState; ///< Offset 12 Debug State
+ //
+ // Thermal Policy Registers:
+ //
+ UINT8 EnableThermalKSC; ///< Offset 13 Enable Thermal Offset for KSC
+ UINT8 Ac1TripPoint; ///< Offset 14 Active Trip Point 1
+ UINT8 Ac0TripPoint; ///< Offset 15 Active Trip Point
+ UINT8 PassiveThermalTripPoint; ///< Offset 16 Passive Trip Point
+ UINT8 PassiveTc1Value; ///< Offset 17 Passive Trip Point TC1 Value
+ UINT8 PassiveTc2Value; ///< Offset 18 Passive Trip Point TC2 Value
+ UINT8 PassiveTspValue; ///< Offset 19 Passive Trip Point TSP Value
+ UINT8 CriticalThermalTripPoint; ///< Offset 20 Critical Trip Point
+ //
+ // Revision Field:
+ //
+ UINT8 Revision; ///< Offset 21 Revison of GlobalNvsArea
+ //
+ // CPU Identification Registers:
+ //
+ UINT8 ApicEnable; ///< Offset 22 APIC Enabled by SBIOS (APIC Enabled = 1)
+ UINT8 ThreadCount; ///< Offset 23 Number of Enabled Threads
+ UINT8 CurentPdcState0; ///< Offset 24 PDC Settings, Processor 0
+ UINT8 CurentPdcState1; ///< Offset 25 PDC Settings, Processor 1
+ UINT8 MaximumPpcState; ///< Offset 26 Maximum PPC state
+ UINT32 PpmFlags; ///< Offset 27 PPM Flags (Same as CFGD)
+ UINT8 C6C7Latency; ///< Offset 31 C6/C7 Entry/Exit latency
+ //
+ // SIO Configuration Registers:
+ //
+ UINT8 DockedSioPresent; ///< Offset 32 National SIO Present
+ UINT8 DockComA; ///< Offset 33 COM A Port
+ UINT8 DockComB; ///< Offset 34 COM B Port
+ UINT8 DockLpt; ///< Offset 35 LPT Port
+ UINT8 DockFdc; ///< Offset 36 FDC Port
+ UINT8 OnboardCom; ///< Offset 37 SMSC Com Port
+ UINT8 OnboardComCir; ///< Offset 38 SMSC Com CIR Port
+ UINT8 SMSC1007; ///< Offset 39 SMSC1007 SIO Present
+ UINT8 WPCN381U; ///< Offset 40 WPCN381U SIO Present
+ UINT8 SMSC1000; ///< Offset 41 SMSC1000 SIO Present
+ //
+ // Extended Mobile Access Values
+ //
+ UINT8 EmaEnable; ///< Offset 42 EMA Enable
+ UINT16 EmaPointer; ///< Offset 43 EMA Pointer
+ UINT16 EmaLength; ///< Offset 45 EMA Length
+ //
+ // MEF Registers:
+ //
+ UINT8 MefEnable; ///< Offset 47 MEF Enable
+ //
+ // PCIe Dock Status:
+ //
+ UINT8 PcieDockStatus; ///< Offset 48 PCIe Dock Status
+ //
+ // TPM Registers
+ //
+ UINT8 MorData; ///< Offset 49 Memory Overwrite Request Data
+ UINT8 TcgParamter; ///< Offset 50 Used for save the Mor and/or physical presence paramter
+ UINT32 PPResponse; ///< Offset 51 Physical Presence request operation response
+ UINT8 PPRequest; ///< Offset 55 Physical Presence request operation
+ UINT8 LastPPRequest; ///< Offset 56 Last Physical Presence request operation
+ //
+ // SATA Registers:
+ //
+ UINT8 IdeMode; ///< Offset 57 IDE Mode (Compatible\Enhanced)
+ //
+ // Board Id
+ //
+ UINT8 PlatformId; ///< Offset 58 Platform id
+ UINT8 BoardType; ///< Offset 59 Board Type
+ //
+ // PCIe Hot Plug
+ //
+ UINT8 PcieOSCControl; ///< Offset 60 PCIE OSC Control
+ UINT8 NativePCIESupport; ///< Offset 61 Native PCIE Setup Value
+ //
+ // USB Sideband Deferring Support
+ //
+ UINT8 HostAlertVector1; ///< Offset 62 USB Sideband Deferring GPE Vector (HOST_ALERT#1)
+ UINT8 HostAlertVector2; ///< Offset 63 USB Sideband Deferring GPE Vector (HOST_ALERT#2)
+ //
+ // Embedded Controller Availability Flag.
+ //
+ UINT8 EcAvailable; ///< Offset 64 Embedded Controller Availability Flag.
+ //
+ // Global Variables
+ //
+ UINT8 DisplaySupportFlag; ///< Offset 65 _DOS Display Support Flag.
+ UINT8 InterruptModeFlag; ///< Offset 66 Global IOAPIC/8259 Interrupt Mode Flag.
+ UINT8 CoolingTypeFlag; ///< Offset 67 Global Cooling Type Flag.
+ UINT8 L01Counter; ///< Offset 68 Global L01 Counter.
+ //
+ // Thermal
+ //
+ UINT32 PlatformCpuId; ///< Offset 69 CPUID Feature Information [EAX]
+ UINT8 TsOnDimmEnabled; ///< Offset 73 TS-on-DIMM is chosen in SETUP and present on the DIMM
+ //
+ // Board info
+ //
+ UINT8 PlatformFlavor; ///< Offset 74 Platform Flavor
+ UINT16 BoardRev; ///< Offset 75 Board Rev
+ //
+ // XTU 3.0 Specification
+ //
+ UINT32 XTUBaseAddress; ///< Offset 77 XTU Continous structure Base Address
+ UINT32 XTUSize; ///< Offset 81 XMP Size
+ UINT32 XMPBaseAddress; ///< Offset 85 XMP Base Address
+ UINT8 DDRReferenceFreq; ///< Offset 89 DDR Reference Frequency
+ //
+ // DPPM Policies
+ //
+ UINT8 EnableActivePolicy; ///< Offset 90 EnableActivePolicy @deprecated. Intel(R) Dynamic Tuning can dynamically enable/disable policies
+ UINT8 EnablePassivePolicy; ///< Offset 91 EnablePassivePolicy @deprecated. Intel(R) Dynamic Tuning can dynamically enable/disable policies
+ UINT8 EnableCriticalPolicy; ///< Offset 92 EnableCriticalPolicy @deprecated. Intel(R) Dynamic Tuning can dynamically enable/disable policies
+ UINT8 EnablePIDPolicy; ///< Offset 93 EnablePIDPolicy @deprecated. Intel(R) Dynamic Tuning can dynamically enable/disable policies
+ //
+ // Miscellaneous Intel(R) Dynamic Tuning Technology
+ //
+ UINT32 PpccStepSize; ///< Offset 94 PPCC Step Size
+ UINT8 Reserved0[58]; ///< Offset 98:155
+ //
+ // Comms Hub
+ //
+ UINT8 CommsHubEnable; ///< Offset 156 Comms Hub Enable/Disable
+ //
+ // BIOS only version of Config TDP
+ //
+ UINT8 ConfigTdpBios; ///< Offset 157 enable/disable BIOS only version of Config TDP
+ UINT8 DockSmi; ///< Offset 158 Dock SMI number
+ //
+ // LPC SIO configuration
+ //
+ UINT16 LpcSioPort1; ///< Offset 159 SIO config port 1
+ UINT16 LpcSioPort2; ///< Offset 161 SIO config port 2
+ UINT16 LpcSioPmeBar; ///< Offset 163 SIO PME Base Address
+ UINT8 Reserved1[334]; ///< Offset 165:498
+ UINT16 DPTFRsvd0; ///< Offset 499 DPTFRsvd0
+ UINT8 EnablePowerBossPolicy; ///< Offset 501 EnablePowerBossPolicy @deprecated. Intel(R) Dynamic Tuning can dynamically enable/disable policies
+ UINT8 EnableVSPolicy; ///< Offset 502 EnableVSPolicy @deprecated. Intel(R) Dynamic Tuning can dynamically enable/disable policies
+ UINT8 EnableRFIMPolicy; ///< Offset 503 RFI Mitigation @deprecated. Intel(R) Dynamic Tuning can dynamically enable/disable policies
+ UINT8 Reserved2[11]; ///< Offset 504:514
+ UINT8 VirtualGpioButtonSxBitmask; ///< Offset 515 Virtual GPIO button Notify Sleep State Change
+ UINT8 IuerButtonEnable; ///< Offset 516 IUER Button Enable
+ UINT8 IuerConvertibleEnable; ///< Offset 517 IUER Convertible Enable
+ UINT8 IuerDockEnable; ///< Offset 518 IUER Dock Enable
+ UINT8 Ps2MouseEnable; ///< Offset 519 Ps2 Mouse Enable
+ UINT16 M0C6; ///< Offset 520 M0D3 for SPI0
+ UINT16 M1C6; ///< Offset 522 M1D3 for SPI0
+ UINT16 M0C7; ///< Offset 524 M0D3 for SPI1
+ UINT16 M1C7; ///< Offset 526 M1D3 for SPI1
+ UINT16 M0C8; ///< Offset 528 M0D3 for SPI2
+ UINT16 M1C8; ///< Offset 530 M1D3 for SPI2
+ UINT8 Reserved3[203]; ///< Offset 532:734
+ UINT16 M0C9; ///< Offset 735 M0D3 for UART0
+ UINT16 M1C9; ///< Offset 737 M1D3 for UART0
+ UINT16 M0CA; ///< Offset 739 M0D3 for UART1
+ UINT16 M1CA; ///< Offset 741 M1D3 for UART1
+ UINT16 M0CB; ///< Offset 743 M0D3 for UART2
+ UINT16 M1CB; ///< Offset 745 M1D3 for UART2
+ UINT8 Reserved4[1]; ///< Offset 747:747
+ //
+ // Driver Mode
+ //
+ UINT32 GpioIrqRoute; ///< Offset 748 GPIO IRQ
+ UINT8 DriverModeSensorHub; ///< Offset 752 PIRQM 28,14(GPIO)
+ UINT8 EnableCpuVrTempSensorDevice; ///< Offset 753 EnableCpuVrTempSensorDevice
+ UINT8 EnableSsdTempSensorDevice; ///< Offset 754 EnableSsdTempSensorDevice
+ UINT8 BCV4; ///< Offset 755 Broadcom's Bluetooth adapter's revision
+ UINT8 AtmelPanelFwUpdate; ///< Offset 756 Atmel panel FW update Enable/Disable
+ UINT8 Reserved5[21]; ///< Offset 757:777
+ UINT64 LowPowerS0IdleConstraint; ///< Offset 778 PEP Constraints
+ // Bit[1:0] - Storage (0:None, 1:Storage Controller, 2:Raid)
+ // Bit[2] - En/Dis UART0
+ // Bit[3] - En/Dis UART1
+ // Bit[4] - En/Dis I2C0
+ // Bit[5] - En/Dis I2C1
+ // Bit[6] - En/Dis XHCI
+ // Bit[8:7] - HD Audio (includes ADSP) (0: No Constraints or 1: D0/F1 or 3:D3)
+ // Bit[9] - En/Dis Gfx
+ // Bit[10] - En/Dis CPU
+ // Bit[11] - En/Dis EMMC
+ // Bit[12] - En/Dis SDXC
+ // Bit[13] - En/Dis I2C2
+ // Bit[14] - En/Dis I2C3
+ // Bit[15] - En/Dis I2C4
+ // Bit[16] - En/Dis I2C5
+ // Bit[17] - En/Dis UART2
+ // Bit[18] - En/Dis SPI0
+ // Bit[19] - En/Dis SPI1
+ // Bit[20] - En/Dis SPI2
+ // Bit[21] - En/Dis IPU0
+ // Bit[22] - En/Dis CSME
+ // Bit[23] - En/Dis LAN(GBE)
+ // Bit[24] - En/Dis PEG0
+ // Bit[25] - En/Dis THC0
+ // Bit[26] - En/Dis THC1
+ // Bit[27] - Reserved
+ // Bit[28] - En/Dis I2C6
+ // Bit[29] - En/Dis TCSS IPs/DTBT
+ // Bit[30] - En/Dis GNA
+ // Bit[31] - En/Dis VMD0
+ // Bit[32] - En/Dis HECI3
+ // Bit[34:33] - PCIe Storage RP(0: No Constraints or 1: D0/F1 or 3:D3)
+ // Bit[36:35] - Pcie Lan (0:No Constraint or 1:D0/F1 or 3:D3)
+ // Bit[38:37] - Pcie Wlan (0:No Constraint or 1:D0/F1 or 3:D3)
+ // Bit[40:39] - Pcie Gfx (0:No Constraint or 1:D0/F1 or 3:D3)
+ // Bit[42:41] - Pcie Other (0:No Constraint or 1:D0/F1 or 3:D3)
+ // Bit[43] - En/Dis DG on x8 PEG port (PEG1)
+ // Bit[44] - En/Dis UFS0
+ // Bit[45] - En/Dis UFS1
+ // Bit[46] - En/Dis I2C7
+ UINT16 VRStaggeringDelay; ///< Offset 786 VR Staggering delay
+ UINT8 TenSecondPowerButtonEnable; ///< Offset 788 10sec Power button support
+ // Bit0: 10 sec P-button Enable/Disable
+ // Bit1: Internal Flag
+ // Bit2: Rotation Lock flag, 0:unlock, 1:lock
+ // Bit3: Slate/Laptop Mode Flag, 0: Slate, 1: Laptop
+ // Bit4: Undock / Dock Flag, 0: Undock, 1: Dock
+ // Bit5: VBDL Flag. 0: VBDL is not called, 1: VBDL is called, Virtual Button Driver is loaded.
+ // Bit7-6: Reserved for future use.
+ //
+ // Generation Id(Tock/Tick)
+ //
+ UINT8 GenerationId; ///< Offset 789 Generation Id(0=Shark bay, 1=Crescent Bay)
+ UINT8 Reserved6[10]; ///< Offset 790:799
+ UINT32 AuxPowerLimit; ///< Offset 800 Maximum aux power available for PCIe root ports
+ //
+ // Intel(R) Dynamic Tuning Technology
+ //
+ UINT8 Reserved7[3]; ///< Offset 804:806
+ UINT8 EnumerateSataPortConstraints; ///< Offset 807 Set to indicate to PEP that constraints at SATA ports should be enumerated
+ //
+ // Intel(R) Dynamic Tuning Technology
+ //
+ UINT8 Reserved8[210]; ///< Offset 808:1017
+ UINT8 EnableAPPolicy; ///< Offset 1018 Adaptive Performance Policy @deprecated. Intel(R) Dynamic Tuning can dynamically enable/disable policies
+ //
+ // Intel Serial(R) IO Sensor Device Selection
+ //
+ UINT8 SDS0; ///< Offset 1019 SerialIo Devices for controller0
+ UINT8 SDS1; ///< Offset 1020 SerialIo Devices for controller1
+ UINT8 SDS2; ///< Offset 1021 SerialIo Devices for controller2
+ UINT8 SDS3; ///< Offset 1022 SerialIo Devices for controller3
+ UINT8 SDS4; ///< Offset 1023 SerialIo Devices for controller4
+ UINT8 SDS5; ///< Offset 1024 SerialIo Devices for controller5
+ UINT8 SDS6; ///< Offset 1025 SerialIo Devices for controller6
+ UINT8 SDS7; ///< Offset 1026 SerialIo Devices for controller7
+ UINT8 SDS8; ///< Offset 1027 SerialIo Devices for controller8
+ UINT8 SDS9; ///< Offset 1028 SerialIo Devices for controller9
+ UINT8 SDSA; ///< Offset 1029 SerialIo Devices for controller10
+ UINT8 WTVX; ///< Offset 1030 WITT test devices' version
+ UINT8 WITX; ///< Offset 1031 WITT test devices' connection point
+ UINT8 GPTD; ///< Offset 1032 GPIO test devices
+ UINT16 GDBT; ///< Offset 1033 GPIO test devices' debounce value,
+ UINT8 UTKX; ///< Offset 1035 UTK test devices' connection point
+ UINT8 SPTD; ///< Offset 1036 SerialIo additional test devices
+ UINT8 Reserved9[29]; ///< Offset 1037:1065
+ UINT32 TableLoadBuffer; ///< Offset 1066 Buffer for runtime ACPI Table loading
+ UINT8 SDM0; ///< Offset 1070 interrupt mode for controller0 devices
+ UINT8 SDM1; ///< Offset 1071 interrupt mode for controller1 devices
+ UINT8 SDM2; ///< Offset 1072 interrupt mode for controller2 devices
+ UINT8 SDM3; ///< Offset 1073 interrupt mode for controller3 devices
+ UINT8 SDM4; ///< Offset 1074 interrupt mode for controller4 devices
+ UINT8 SDM5; ///< Offset 1075 interrupt mode for controller5 devices
+ UINT8 SDM6; ///< Offset 1076 interrupt mode for controller6 devices
+ UINT8 SDM7; ///< Offset 1077 interrupt mode for controller7 devices
+ UINT8 SDM8; ///< Offset 1078 interrupt mode for controller8 devices
+ UINT8 SDM9; ///< Offset 1079 interrupt mode for controller9 devices
+ UINT8 SDMA; ///< Offset 1080 interrupt mode for controller10 devices
+ UINT8 SDMB; ///< Offset 1081 interrupt mode for controller11 devices
+ UINT8 Reserved10[1]; ///< Offset 1082:1082
+ UINT8 USTP; ///< Offset 1083 use SerialIo timing parameters
+ UINT8 Reserved11[41]; ///< Offset 1084:1124
+ //
+ // MipiCam specific
+ //
+ UINT8 MipiCamControlLogic0; ///< Offset 1125
+ UINT8 MipiCamControlLogic1; ///< Offset 1126
+ UINT8 MipiCamControlLogic2; ///< Offset 1127
+ UINT8 MipiCamControlLogic3; ///< Offset 1128
+ UINT8 MipiCamControlLogic4; ///< Offset 1129
+ UINT8 MipiCamControlLogic5; ///< Offset 1130
+ UINT8 MipiCamLink0Enabled; ///< Offset 1131
+ UINT8 MipiCamLink1Enabled; ///< Offset 1132
+ UINT8 MipiCamLink2Enabled; ///< Offset 1133
+ UINT8 MipiCamLink3Enabled; ///< Offset 1134
+ UINT8 MipiCamLink4Enabled; ///< Offset 1135
+ UINT8 MipiCamLink5Enabled; ///< Offset 1136
+ UINT8 MipiCamLanesClkDiv; ///< Offset 1137 MipiCamLanesClkDiv is @deprecated as the Laneclockdivision option is added and now can be set uniquely for all the links.
+ // Control Logic 0 options
+ UINT8 MipiCamCtrlLogic0_Version; ///< Offset 1138 Version of CLDB structure
+ UINT8 MipiCamCtrlLogic0_Type; ///< Offset 1139 Type
+ UINT8 MipiCamCtrlLogic0_CrdVersion; ///< Offset 1140 Version of CRD
+ UINT32 MipiCamCtrlLogic0_InputClock; ///< Offset 1141 Input Clock
+ UINT8 MipiCamCtrlLogic0_GpioPinsEnabled; ///< Offset 1145 Number of GPIO Pins enabled
+ UINT8 MipiCamCtrlLogic0_GpioGroupPadNumber[6]; ///< Offset 1146 GPIO Group Pad Number
+ UINT8 MipiCamCtrlLogic0_GpioGroupNumber[6]; ///< Offset 1152 GPIO Group Number
+ UINT8 MipiCamCtrlLogic0_GpioFunction[6]; ///< Offset 1158 GPIO Function
+ UINT8 MipiCamCtrlLogic0_GpioActiveValue[6]; ///< Offset 1164 GPIO Active Value
+ UINT8 MipiCamCtrlLogic0_GpioInitialValue[6]; ///< Offset 1170 GPIO Initial Value
+ UINT8 MipiCamCtrlLogic0_PchClockSource; ///< Offset 1176 PCH Clock source
+ // Control Logic 1 options
+ UINT8 MipiCamCtrlLogic1_Version; ///< Offset 1177 Version of CLDB structure
+ UINT8 MipiCamCtrlLogic1_Type; ///< Offset 1178 Type
+ UINT8 MipiCamCtrlLogic1_CrdVersion; ///< Offset 1179 Version of CRD
+ UINT32 MipiCamCtrlLogic1_InputClock; ///< Offset 1180 Input Clock
+ UINT8 MipiCamCtrlLogic1_GpioPinsEnabled; ///< Offset 1184 Number of GPIO Pins enabled
+ UINT8 MipiCamCtrlLogic1_GpioGroupPadNumber[6]; ///< Offset 1185 GPIO Group Pad Number
+ UINT8 MipiCamCtrlLogic1_GpioGroupNumber[6]; ///< Offset 1191 GPIO Group Number
+ UINT8 MipiCamCtrlLogic1_GpioFunction[6]; ///< Offset 1197 GPIO Function
+ UINT8 MipiCamCtrlLogic1_GpioActiveValue[6]; ///< Offset 1203 GPIO Active Value
+ UINT8 MipiCamCtrlLogic1_GpioInitialValue[6]; ///< Offset 1209 GPIO Initial Value
+ UINT8 MipiCamCtrlLogic1_PchClockSource; ///< Offset 1215 PCH Clock source
+ // Control Logic 2 options
+ UINT8 MipiCamCtrlLogic2_Version; ///< Offset 1216 Version of CLDB structure
+ UINT8 MipiCamCtrlLogic2_Type; ///< Offset 1217 Type
+ UINT8 MipiCamCtrlLogic2_CrdVersion; ///< Offset 1218 Version of CRD
+ UINT32 MipiCamCtrlLogic2_InputClock; ///< Offset 1219 Input Clock
+ UINT8 MipiCamCtrlLogic2_GpioPinsEnabled; ///< Offset 1223 Number of GPIO Pins enabled
+ UINT8 MipiCamCtrlLogic2_GpioGroupPadNumber[6]; ///< Offset 1224 GPIO Group Pad Number
+ UINT8 MipiCamCtrlLogic2_GpioGroupNumber[6]; ///< Offset 1230 GPIO Group Number
+ UINT8 MipiCamCtrlLogic2_GpioFunction[6]; ///< Offset 1236 GPIO Function
+ UINT8 MipiCamCtrlLogic2_GpioActiveValue[6]; ///< Offset 1242 GPIO Active Value
+ UINT8 MipiCamCtrlLogic2_GpioInitialValue[6]; ///< Offset 1248 GPIO Initial Value
+ UINT8 MipiCamCtrlLogic2_PchClockSource; ///< Offset 1254 PCH Clock source
+ // Control Logic 3 options
+ UINT8 MipiCamCtrlLogic3_Version; ///< Offset 1255 Version of CLDB structure
+ UINT8 MipiCamCtrlLogic3_Type; ///< Offset 1256 Type
+ UINT8 MipiCamCtrlLogic3_CrdVersion; ///< Offset 1257 Version of CRD
+ UINT32 MipiCamCtrlLogic3_InputClock; ///< Offset 1258 Input Clock
+ UINT8 MipiCamCtrlLogic3_GpioPinsEnabled; ///< Offset 1262 Number of GPIO Pins enabled
+ UINT8 MipiCamCtrlLogic3_GpioGroupPadNumber[6]; ///< Offset 1263 GPIO Group Pad Number
+ UINT8 MipiCamCtrlLogic3_GpioGroupNumber[6]; ///< Offset 1269 GPIO Group Number
+ UINT8 MipiCamCtrlLogic3_GpioFunction[6]; ///< Offset 1275 GPIO Function
+ UINT8 MipiCamCtrlLogic3_GpioActiveValue[6]; ///< Offset 1281 GPIO Active Value
+ UINT8 MipiCamCtrlLogic3_GpioInitialValue[6]; ///< Offset 1287 GPIO Initial Value
+ UINT8 MipiCamCtrlLogic3_PchClockSource; ///< Offset 1293 PCH Clock source
+ // Control Logic 4 options
+ UINT8 MipiCamCtrlLogic4_Version; ///< Offset 1294 Version of CLDB structure
+ UINT8 MipiCamCtrlLogic4_Type; ///< Offset 1295 Type
+ UINT8 MipiCamCtrlLogic4_CrdVersion; ///< Offset 1296 Version of CRD
+ UINT32 MipiCamCtrlLogic4_InputClock; ///< Offset 1297 Input Clock
+ UINT8 MipiCamCtrlLogic4_GpioPinsEnabled; ///< Offset 1301 Number of GPIO Pins enabled
+ UINT8 MipiCamCtrlLogic4_GpioGroupPadNumber[6]; ///< Offset 1302 GPIO Group Pad Number
+ UINT8 MipiCamCtrlLogic4_GpioGroupNumber[6]; ///< Offset 1308 GPIO Group Number
+ UINT8 MipiCamCtrlLogic4_GpioFunction[6]; ///< Offset 1314 GPIO Function
+ UINT8 MipiCamCtrlLogic4_GpioActiveValue[6]; ///< Offset 1320 GPIO Active Value
+ UINT8 MipiCamCtrlLogic4_GpioInitialValue[6]; ///< Offset 1326 GPIO Initial Value
+ UINT8 MipiCamCtrlLogic4_PchClockSource; ///< Offset 1332 PCH Clock source
+ // Control Logic 5 options
+ UINT8 MipiCamCtrlLogic5_Version; ///< Offset 1333 Version of CLDB structure
+ UINT8 MipiCamCtrlLogic5_Type; ///< Offset 1334 Type
+ UINT8 MipiCamCtrlLogic5_CrdVersion; ///< Offset 1335 Version of CRD
+ UINT32 MipiCamCtrlLogic5_InputClock; ///< Offset 1336 Input Clock
+ UINT8 MipiCamCtrlLogic5_GpioPinsEnabled; ///< Offset 1340 Number of GPIO Pins enabled
+ UINT8 MipiCamCtrlLogic5_GpioGroupPadNumber[6]; ///< Offset 1341 GPIO Group Pad Number
+ UINT8 MipiCamCtrlLogic5_GpioGroupNumber[6]; ///< Offset 1347 GPIO Group Number
+ UINT8 MipiCamCtrlLogic5_GpioFunction[6]; ///< Offset 1353 GPIO Function
+ UINT8 MipiCamCtrlLogic5_GpioActiveValue[6]; ///< Offset 1359 GPIO Active Value
+ UINT8 MipiCamCtrlLogic5_GpioInitialValue[6]; ///< Offset 1365 GPIO Initial Value
+ UINT8 MipiCamCtrlLogic5_PchClockSource; ///< Offset 1371 PCH Clock source
+ // Mipi Cam Link0 options
+ UINT8 MipiCamLink0SensorModel; ///< Offset 1372 Sensor Model
+ UINT8 MipiCamLink0DD_Version; ///< Offset 1373 Version of SSDB structure
+ UINT8 MipiCamLink0DD_CrdVersion; ///< Offset 1374 Version of CRD
+ UINT8 MipiCamLink0DD_LinkUsed; ///< Offset 1375 CSI2 Link used
+ UINT8 MipiCamLink0DD_LaneUsed; ///< Offset 1376 MIPI-CSI2 Data Lane
+ UINT8 MipiCamLink0DD_EepromType; ///< Offset 1377 EEPROM Type
+ UINT8 MipiCamLink0DD_VcmType; ///< Offset 1378 VCM Type
+ UINT8 MipiCamLink0DD_FlashSupport; ///< Offset 1379 Flash Support
+ UINT8 MipiCamLink0DD_Degree; ///< Offset 1380 Degree
+ UINT32 MipiCamLink0DD_Mclk; ///< Offset 1381 MCLK
+ UINT8 MipiCamLink0DD_ControlLogic; ///< Offset 1385 Control Logic
+ UINT8 MipiCamLink0DD_PmicPosition; ///< Offset 1386 PMIC Position
+ UINT8 MipiCamLink0DD_VoltageRail; ///< Offset 1387 Voltage Rail
+ UINT8 MipiCamLink0_FlashDriverSelection; ///< Offset 1388 Flash Driver Selection
+ // Mipi Cam Link1 options
+ UINT8 MipiCamLink1SensorModel; ///< Offset 1389 Sensor Model
+ UINT8 MipiCamLink1DD_Version; ///< Offset 1390 Version of SSDB structure
+ UINT8 MipiCamLink1DD_CrdVersion; ///< Offset 1391 Version of CRD
+ UINT8 MipiCamLink1DD_LinkUsed; ///< Offset 1392 CSI2 Link used
+ UINT8 MipiCamLink1DD_LaneUsed; ///< Offset 1393 MIPI-CSI2 Data Lane
+ UINT8 MipiCamLink1DD_EepromType; ///< Offset 1394 EEPROM Type
+ UINT8 MipiCamLink1DD_VcmType; ///< Offset 1395 VCM Type
+ UINT8 MipiCamLink1DD_FlashSupport; ///< Offset 1396 Flash Support
+ UINT8 MipiCamLink1DD_Degree; ///< Offset 1397 Degree
+ UINT32 MipiCamLink1DD_Mclk; ///< Offset 1398 MCLK
+ UINT8 MipiCamLink1DD_ControlLogic; ///< Offset 1402 Control Logic
+ UINT8 MipiCamLink1DD_PmicPosition; ///< Offset 1403 PMIC Position
+ UINT8 MipiCamLink1DD_VoltageRail; ///< Offset 1404 Voltage Rail
+ UINT8 MipiCamLink1_FlashDriverSelection; ///< Offset 1405 Flash Driver Selection
+ // Mipi Cam Link2 options
+ UINT8 MipiCamLink2SensorModel; ///< Offset 1406 Sensor Model
+ UINT8 MipiCamLink2DD_Version; ///< Offset 1407 Version of SSDB structure
+ UINT8 MipiCamLink2DD_CrdVersion; ///< Offset 1408 Version of CRD
+ UINT8 MipiCamLink2DD_LinkUsed; ///< Offset 1409 CSI2 Link used
+ UINT8 MipiCamLink2DD_LaneUsed; ///< Offset 1410 MIPI-CSI2 Data Lane
+ UINT8 MipiCamLink2DD_EepromType; ///< Offset 1411 EEPROM Type
+ UINT8 MipiCamLink2DD_VcmType; ///< Offset 1412 VCM Type
+ UINT8 MipiCamLink2DD_FlashSupport; ///< Offset 1413 Flash Support
+ UINT8 MipiCamLink2DD_Degree; ///< Offset 1414 Degree
+ UINT32 MipiCamLink2DD_Mclk; ///< Offset 1415 MCLK
+ UINT8 MipiCamLink2DD_ControlLogic; ///< Offset 1419 Control Logic
+ UINT8 MipiCamLink2DD_PmicPosition; ///< Offset 1420 PMIC Position
+ UINT8 MipiCamLink2DD_VoltageRail; ///< Offset 1421 Voltage Rail
+ UINT8 MipiCamLink2_FlashDriverSelection; ///< Offset 1422 Flash Driver Selection
+ // Mipi Cam Link3 options
+ UINT8 MipiCamLink3SensorModel; ///< Offset 1423 Sensor Model
+ UINT8 MipiCamLink3DD_Version; ///< Offset 1424 Version of SSDB structure
+ UINT8 MipiCamLink3DD_CrdVersion; ///< Offset 1425 Version of CRD
+ UINT8 MipiCamLink3DD_LinkUsed; ///< Offset 1426 CSI2 Link used
+ UINT8 MipiCamLink3DD_LaneUsed; ///< Offset 1427 MIPI-CSI2 Data Lane
+ UINT8 MipiCamLink3DD_EepromType; ///< Offset 1428 EEPROM Type
+ UINT8 MipiCamLink3DD_VcmType; ///< Offset 1429 VCM Type
+ UINT8 MipiCamLink3DD_FlashSupport; ///< Offset 1430 Flash Support
+ UINT8 MipiCamLink3DD_Degree; ///< Offset 1431 Degree
+ UINT32 MipiCamLink3DD_Mclk; ///< Offset 1432 MCLK
+ UINT8 MipiCamLink3DD_ControlLogic; ///< Offset 1436 Control Logic
+ UINT8 MipiCamLink3DD_PmicPosition; ///< Offset 1437 PMIC Position
+ UINT8 MipiCamLink3DD_VoltageRail; ///< Offset 1438 Voltage Rail
+ UINT8 MipiCamLink3_FlashDriverSelection; ///< Offset 1439 Flash Driver Selection
+ // Mipi Cam Link4 options
+ UINT8 MipiCamLink4SensorModel; ///< Offset 1440 Sensor Model
+ UINT8 MipiCamLink4DD_Version; ///< Offset 1441 Version of SSDB structure
+ UINT8 MipiCamLink4DD_CrdVersion; ///< Offset 1442 Version of CRD
+ UINT8 MipiCamLink4DD_LinkUsed; ///< Offset 1443 CSI2 Link used
+ UINT8 MipiCamLink4DD_LaneUsed; ///< Offset 1444 MIPI-CSI2 Data Lane
+ UINT8 MipiCamLink4DD_EepromType; ///< Offset 1445 EEPROM Type
+ UINT8 MipiCamLink4DD_VcmType; ///< Offset 1446 VCM Type
+ UINT8 MipiCamLink4DD_FlashSupport; ///< Offset 1447 Flash Support
+ UINT8 MipiCamLink4DD_Degree; ///< Offset 1448 Degree
+ UINT32 MipiCamLink4DD_Mclk; ///< Offset 1449 MCLK
+ UINT8 MipiCamLink4DD_ControlLogic; ///< Offset 1453 Control Logic
+ UINT8 MipiCamLink4DD_PmicPosition; ///< Offset 1454 PMIC Position
+ UINT8 MipiCamLink4DD_VoltageRail; ///< Offset 1455 Voltage Rail
+ UINT8 MipiCamLink4_FlashDriverSelection; ///< Offset 1456 Flash Driver Selection
+ // Mipi Cam Link5 options
+ UINT8 MipiCamLink5SensorModel; ///< Offset 1457 Sensor Model
+ UINT8 MipiCamLink5DD_Version; ///< Offset 1458 Version of SSDB structure
+ UINT8 MipiCamLink5DD_CrdVersion; ///< Offset 1459 Version of CRD
+ UINT8 MipiCamLink5DD_LinkUsed; ///< Offset 1460 CSI2 Link used
+ UINT8 MipiCamLink5DD_LaneUsed; ///< Offset 1461 MIPI-CSI2 Data Lane
+ UINT8 MipiCamLink5DD_EepromType; ///< Offset 1462 EEPROM Type
+ UINT8 MipiCamLink5DD_VcmType; ///< Offset 1463 VCM Type
+ UINT8 MipiCamLink5DD_FlashSupport; ///< Offset 1464 Flash Support
+ UINT8 MipiCamLink5DD_Degree; ///< Offset 1465 Degree
+ UINT32 MipiCamLink5DD_Mclk; ///< Offset 1466 MCLK
+ UINT8 MipiCamLink5DD_ControlLogic; ///< Offset 1470 Control Logic
+ UINT8 MipiCamLink5DD_PmicPosition; ///< Offset 1471 PMIC Position
+ UINT8 MipiCamLink5DD_VoltageRail; ///< Offset 1472 Voltage Rail
+ UINT8 MipiCamLink5_FlashDriverSelection; ///< Offset 1473 Flash Driver Selection
+ UINT8 MipiCamFlash0Model; ///< Offset 1474 Flash Driver Model
+ UINT8 MipiCamFlash0Mode; ///< Offset 1475 Flash Mode Selection
+ UINT8 MipiCamFlash0ModuleName[16]; ///< Offset 1476 Flash Module Name ASCII character 0
+ ///< Offset 1491 Flash Module Name ASCII character 15
+ UINT8 MipiCamFlash0GpioGroupPadNumber; ///< Offset 1492 GPIO Group Pad Number
+ UINT16 MipiCamFlash0GpioGroupNumber; ///< Offset 1493 GPIO Group Number
+ UINT8 MipiCamFlash0GpioActiveValue; ///< Offset 1495 GPIO Active Value
+ UINT8 MipiCamFlash0GpioInitialValue; ///< Offset 1496 GPIO Initial Value
+ UINT8 MipiCamFlash0OperatingMode; ///< Offset 1497 Flash Driver Operating Mode
+ UINT8 MipiCamFlash1Model; ///< Offset 1498 Flash Driver Model
+ UINT8 MipiCamFlash1Mode; ///< Offset 1499 Flash Mode Selection
+ UINT8 MipiCamFlash1ModuleName[16]; ///< Offset 1500 Flash Module Name ASCII character 0
+ ///< Offset 1515 Flash Module Name ASCII character 15
+ UINT8 MipiCamFlash1GpioGroupPadNumber; ///< Offset 1516 GPIO Group Pad Number
+ UINT16 MipiCamFlash1GpioGroupNumber; ///< Offset 1517 GPIO Group Number
+ UINT8 MipiCamFlash1GpioActiveValue; ///< Offset 1519 GPIO Active Value
+ UINT8 MipiCamFlash1GpioInitialValue; ///< Offset 1520 GPIO Initial Value
+ UINT8 MipiCamFlash1OperatingMode; ///< Offset 1521 Flash Driver Operating Mode
+ UINT8 MipiCamFlash2Model; ///< Offset 1522 Flash Driver Model
+ UINT8 MipiCamFlash2Mode; ///< Offset 1523 Flash Mode Selection
+ UINT8 MipiCamFlash2ModuleName[16]; ///< Offset 1524 Flash Module Name ASCII character 0
+ ///< Offset 1539 Flash Module Name ASCII character 15
+ UINT8 MipiCamFlash2GpioGroupPadNumber; ///< Offset 1540 GPIO Group Pad Number
+ UINT16 MipiCamFlash2GpioGroupNumber; ///< Offset 1541 GPIO Group Number
+ UINT8 MipiCamFlash2GpioActiveValue; ///< Offset 1543 GPIO Active Value
+ UINT8 MipiCamFlash2GpioInitialValue; ///< Offset 1544 GPIO Initial Value
+ UINT8 MipiCamFlash2OperatingMode; ///< Offset 1545 Flash Driver Operating Mode
+ UINT8 MipiCamFlash3Model; ///< Offset 1546 Flash Driver Model
+ UINT8 MipiCamFlash3Mode; ///< Offset 1547 Flash Mode Selection
+ UINT8 MipiCamFlash3ModuleName[16]; ///< Offset 1548 Flash Module Name ASCII character 0
+ ///< Offset 1563 Flash Module Name ASCII character 15
+ UINT8 MipiCamFlash3GpioGroupPadNumber; ///< Offset 1564 GPIO Group Pad Number
+ UINT16 MipiCamFlash3GpioGroupNumber; ///< Offset 1565 GPIO Group Number
+ UINT8 MipiCamFlash3GpioActiveValue; ///< Offset 1567 GPIO Active Value
+ UINT8 MipiCamFlash3GpioInitialValue; ///< Offset 1568 GPIO Initial Value
+ UINT8 MipiCamFlash3OperatingMode; ///< Offset 1569 Flash Driver Operating Mode
+ UINT8 MipiCamFlash4Model; ///< Offset 1570 Flash Driver Model
+ UINT8 MipiCamFlash4Mode; ///< Offset 1571 Flash Mode Selection
+ UINT8 MipiCamFlash4ModuleName[16]; ///< Offset 1572 Flash Module Name ASCII character 0
+ ///< Offset 1587 Flash Module Name ASCII character 15
+ UINT8 MipiCamFlash4GpioGroupPadNumber; ///< Offset 1588 GPIO Group Pad Number
+ UINT16 MipiCamFlash4GpioGroupNumber; ///< Offset 1589 GPIO Group Number
+ UINT8 MipiCamFlash4GpioActiveValue; ///< Offset 1591 GPIO Active Value
+ UINT8 MipiCamFlash4GpioInitialValue; ///< Offset 1592 GPIO Initial Value
+ UINT8 MipiCamFlash4OperatingMode; ///< Offset 1593 Flash Driver Operating Mode
+ UINT8 MipiCamFlash5Model; ///< Offset 1594 Flash Driver Model
+ UINT8 MipiCamFlash5Mode; ///< Offset 1595 Flash Mode Selection
+ UINT8 MipiCamFlash5ModuleName[16]; ///< Offset 1596 Flash Module Name ASCII character 0
+ ///< Offset 1611 Flash Module Name ASCII character 15
+ UINT8 MipiCamFlash5GpioGroupPadNumber; ///< Offset 1612 GPIO Group Pad Number
+ UINT16 MipiCamFlash5GpioGroupNumber; ///< Offset 1613 GPIO Group Number
+ UINT8 MipiCamFlash5GpioActiveValue; ///< Offset 1615 GPIO Active Value
+ UINT8 MipiCamFlash5GpioInitialValue; ///< Offset 1616 GPIO Initial Value
+ UINT8 MipiCamFlash5OperatingMode; ///< Offset 1617 Flash Driver Operating Mode
+ UINT8 Reserved12[502]; ///< Offset 1618:2119
+ // RTD3 Settings
+ UINT8 Reserved13[24]; ///< Offset 2120:2143
+ UINT8 HidEventFilterEnable; ///< Offset 2144 HID Event Filter Driver enable
+ UINT8 XdciFnEnable; ///< Offset 2145 XDCI Enable/Disable status
+ UINT8 EnableVoltageMargining; ///< Offset 2146 Enable Voltage Margining
+ UINT16 DStateHSPort; ///< Offset 2147 D-State for xHCI HS port(BIT0:USB HS Port0 ~ BIT15:USB HS Port15)
+ UINT16 DStateSSPort; ///< Offset 2149 D-State for xHCI SS port(BIT0:USB SS Port0 ~ BIT15:USB SS Port15)
+ UINT8 DStateSataPort; ///< Offset 2151 D-State for SATA port(BIT0:SATA Port0 ~ BIT7:SATA Port7)
+ UINT8 Reserved14[154]; ///< Offset 2152:2305
+ // Reserved for Groups 4 to 9, each needs 6 bytes and total 36 bytes reserved
+ UINT8 Reserved15[11]; ///< Offset 2306:2316
+ // Reserved for Bluetooth Sar future use
+ UINT8 RunTimeVmControl; ///< Offset 2317 RunTime VM Control
+ //
+ //Feature Specific Data Bits
+ //
+ UINT32 HebcValue; ///< Offset 2318 HebcValue
+ UINT8 PcdBatteryPresent; ///< Offset 2322 Battery Present - Bit0: Real Battery is supported on this platform. Bit1: Virtual Battery is supported on this platform.
+ UINT8 PcdTsOnDimmTemperature; ///< Offset 2323 TS-on-DIMM temperature
+ UINT8 Reserved16[5]; ///< Offset 2324:2328
+ UINT8 PcdRealBattery1Control; ///< Offset 2329 Real Battery 1 Control
+ UINT8 PcdRealBattery2Control; ///< Offset 2330 Real Battery 2 Control
+ UINT8 PcdNCT6776FCOM; ///< Offset 2331 NCT6776F COM
+ UINT8 PcdNCT6776FSIO; ///< Offset 2332 NCT6776F SIO
+ UINT8 PcdNCT6776FHWMON; ///< Offset 2333 NCT6776F HWMON
+ UINT8 PcdH8S2113SIO; ///< Offset 2334 H8S2113 SIO
+ UINT8 PcdZPoddConfig; ///< Offset 2335 ZPODD
+ UINT32 PcdSmcRuntimeSciPin; ///< Offset 2336 SMC Runtime Sci Pin
+ UINT8 PcdConvertableDockSupport; ///< Offset 2340 Convertable Dock Support
+ UINT8 PcdEcHotKeyF3Support; ///< Offset 2341 Ec Hotkey F3 Support
+ UINT8 PcdEcHotKeyF4Support; ///< Offset 2342 Ec Hotkey F4 Support
+ UINT8 PcdEcHotKeyF5Support; ///< Offset 2343 Ec Hotkey F5 Support
+ UINT8 PcdEcHotKeyF6Support; ///< Offset 2344 Ec Hotkey F6 Support
+ UINT8 PcdEcHotKeyF7Support; ///< Offset 2345 Ec Hotkey F7 Support
+ UINT8 PcdEcHotKeyF8Support; ///< Offset 2346 Ec Hotkey F8 Support
+ UINT8 PcdVirtualButtonVolumeUpSupport; ///< Offset 2347 Virtual Button Volume Up Support
+ UINT8 PcdVirtualButtonVolumeDownSupport; ///< Offset 2348 Virtual Button Volume Down Support
+ UINT8 PcdVirtualButtonHomeButtonSupport; ///< Offset 2349 Virtual Button Home Button Support
+ UINT8 PcdVirtualButtonRotationLockSupport; ///< Offset 2350 Virtual Button Rotation Lock Support
+ UINT8 PcdSlateModeSwitchSupport; ///< Offset 2351 Slate Mode Switch Support
+ UINT8 PcdVirtualGpioButtonSupport; ///< Offset 2352 Virtual Button Support
+ UINT8 PcdAcDcAutoSwitchSupport; ///< Offset 2353 Ac Dc Auto Switch Support
+ UINT32 PcdPmPowerButtonGpioPin; ///< Offset 2354 Pm Power Button Gpio Pin
+ UINT8 PcdAcpiEnableAllButtonSupport; ///< Offset 2358 Acpi Enable All Button Support
+ UINT8 PcdAcpiHidDriverButtonSupport; ///< Offset 2359 Acpi Hid Driver Button Support
+ UINT32 EcLowPowerModeGpioPin; ///< Offset 2360 EcLowPowerModeGpioPin
+ UINT32 EcSmiGpioPin; ///< Offset 2364 EcSmiGpioPin
+ //
+ // UCMC setup option, GPIO Pad
+ //
+ UINT8 UCMS; ///< Offset 2368 Option to select UCSI/UCMC device
+ UINT32 UcmcPort1Gpio; ///< Offset 2369 Gpio for UCMC Port 1 Interrupt
+ UINT32 UcmcPort2Gpio; ///< Offset 2373 Gpio for UCMC Port 2 Interrupt
+ UINT32 UcmcPort3Gpio; ///< Offset 2377 Gpio for UCMC Port 3 Interrupt
+ UINT32 UcmcPort4Gpio; ///< Offset 2381 Gpio for UCMC Port 4 Interrupt
+ UINT8 Reserved17[24]; ///< Offset 2385:2408
+ UINT8 Reserved18[4]; ///< Offset 2409:2412
+ UINT8 Ufp2DfpGlobalFlag; ///< Offset 2413 Upstream Facing port or Downstream Facing port Global Flag from LPC EC
+ UINT8 Ufp2DfpUsbPort; ///< Offset 2414 Upstream Facing port or Downstream Facing port number from LPC EC
+ UINT8 DbcGlobalFlag; ///< Offset 2415 Debug Mode Global Flag from LPC EC
+ UINT8 DbcUsbPort; ///< Offset 2416 Debug Mode USB Port Number from LPC EC
+ UINT32 PcieSlot1WakeGpio; ///< Offset 2417 Pcie Slot Wake Gpio pin
+ UINT8 PcieSlot1RpNumber; ///< Offset 2421 Pcie Slot Root Port Number
+ UINT32 PcieSlot2WakeGpio; ///< Offset 2422 Pcie Slot 2 Wake Gpio pin
+ UINT8 PcieSlot2RpNumber; ///< Offset 2426 Pcie Slot 2 Root Port Number
+ UINT32 PcieSlot1PowerEnableGpio; ///< Offset 2427 Pcie Slot 1 Power Enable Gpio pin
+ UINT8 PcieSlot1PowerEnableGpioPolarity; ///< Offset 2431 Pcie Slot 1 Power Enable Gpio pin polarity
+ UINT32 PcieSlot1RstGpio; ///< Offset 2432 Pcie Slot 1 Rest Gpio pin
+ UINT8 PcieSlot1RstGpioPolarity; ///< Offset 2436 Pcie Slot 1 Rest Gpio pin polarity
+ UINT32 PcieSlot2PowerEnableGpio; ///< Offset 2437 Pcie Slot 2 Power Enable Gpio pin
+ UINT8 PcieSlot2PowerEnableGpioPolarity; ///< Offset 2441 Pcie Slot 2 Power Enable Gpio pin polarity
+ UINT32 PcieSlot2RstGpio; ///< Offset 2442 Pcie Slot 2 Rest Gpio pin
+ UINT8 PcieSlot2RstGpioPolarity; ///< Offset 2446 Pcie Slot 2 Rest Gpio pin polarity
+ UINT32 SataPortPowerEnableGpio; ///< Offset 2447 Sata port Power Enable Gpio pin
+ UINT8 SataPortPowerEnableGpioPolarity; ///< Offset 2451 Sata port Power Enable Gpio pin polarity
+ UINT32 PchM2SsdPowerEnableGpio; ///< Offset 2452 Pch M.2 SSD Power Enable Gpio pin
+ UINT8 PchM2SsdPowerEnableGpioPolarity; ///< Offset 2456 Pch M.2 SSD Power Enable Gpio pin polarity
+ UINT32 PchM2SsdRstGpio; ///< Offset 2457 Pch M.2 SSD Reset Gpio pin
+ UINT8 PchM2SsdRstGpioPolarity; ///< Offset 2461 Pch M.2 SSD Reset Gpio pin polarity
+ UINT32 M2Ssd2PowerEnableGpio; ///< Offset 2462 PCIe x4 M.2 SSD Power Enable Gpio pin
+ UINT8 M2Ssd2PowerEnableGpioPolarity; ///< Offset 2466 PCIe x4 M.2 SSD Power Enable Gpio pin polarity
+ UINT32 M2Ssd2RstGpio; ///< Offset 2467 PCIe x4 M.2 SSD Reset Gpio pin
+ UINT8 M2Ssd2RstGpioPolarity; ///< Offset 2471 PCIe x4 M.2 SSD Reset Gpio pin polarity
+ UINT32 M2Ssd3PowerEnableGpio; ///< Offset 2472 PCIe x4 M.2 SSD Power Enable Gpio pin
+ UINT8 M2Ssd3PowerEnableGpioPolarity; ///< Offset 2476 PCIe x4 M.2 SSD Power Enable Gpio pin polarity
+ UINT32 M2Ssd3RstGpio; ///< Offset 2477 PCIe x4 M.2 SSD Reset Gpio pin
+ UINT8 M2Ssd3RstGpioPolarity; ///< Offset 2481 PCIe x4 M.2 SSD Reset Gpio pin polarity
+ UINT32 M2DG2PowerEnableGpio; ///< Offset 2482 PCIe x5 M.2 Discrete Graphics Power Enable Gpio Pin
+ UINT8 M2DG2PowerEnableGpioPolarity; ///< Offset 2486 PCIe x5 M.2 Discrete Graphics Power Enable Gpio Pin polarity
+ UINT32 M2DG2RstGpio; ///< Offset 2487 PCIe x5 M.2 Discrete Graphics Reset Gpio Pin
+ UINT8 M2DG2RstGpioPolarity; ///< Offset 2491 PCIe x5 M.2 Discrete Graphics Reset Gpio Pin Polarity
+ UINT32 M2DG2WakeGpioPin; ///< Offset 2492 PEG X8 DG/DG2 Wake Gpio pin
+ UINT8 SdevXhciRootPortNumber1; ///< Offset 2496 SDEV xHCI Root Port Number for device 1
+ UINT8 SdevXhciRootPortNumber2; ///< Offset 2497 SDEV xHCI Root Port Number for device 2
+ UINT8 TsnPcsEnabled; ///< Offset 2498 TSN PCS device Enable
+ UINT8 CpuWakeEnFlag; ///< Offset 2499 CPU_WAKE_EN value
+ UINT32 Dg1VramSRGpio; ///< Offset 2500 DG1 VRAM Self Refresh Gpio pin
+ UINT32 LpmReqRegAddr; ///< Offset 2504 Low Power Mode required register Address
+ UINT32 PegSlot1PwrEnableGpioNo; ///< Offset 2508 PEG slot 1 Power Enable Gpio pin
+ UINT8 PegSlot1PwrEnableGpioPolarity; ///< Offset 2512 PEG slot 1 Power Enable Gpio pin polarity
+ UINT32 PegSlot1RstGpioNo; ///< Offset 2513 PEG slot 1 Reset Gpio pin
+ UINT8 PegSlot1RstGpioPolarity; ///< Offset 2517 PEG slot 1 Reset Gpio pin polarity
+ UINT32 PegSlot1WakeGpioPin; ///< Offset 2518 PEG slot 1 Wake Gpio pin
+ UINT8 PegSlot1RootPort; ///< Offset 2522 PEG slot 1 Root Port
+ UINT32 PegSlot2PwrEnableGpioNo; ///< Offset 2523 PEG slot 2 Power Enable Gpio pin
+ UINT8 PegSlot2PwrEnableGpioPolarity; ///< Offset 2527 PEG slot 2 Power Enable Gpio pin polarity
+ UINT32 PegSlot2RstGpioNo; ///< Offset 2528 PEG slot 2 Reset Gpio pin
+ UINT8 PegSlot2RstGpioPolarity; ///< Offset 2532 PEG slot 2 Reset Gpio pin polarity
+ UINT32 PegSlot2WakeGpioPin; ///< Offset 2533 PEG slot 2 Wake Gpio pin
+ UINT8 PegSlot2RootPort; ///< Offset 2537 PEG slot 2 Root Port
+ UINT32 PcieSlot3PowerEnableGpio; ///< Offset 2538 Pcie Slot 3 Power Enable Gpio pin
+ UINT8 PcieSlot3PowerEnableGpioPolarity; ///< Offset 2542 Pcie Slot 3 Power Enable Gpio pin polarity
+ UINT32 PcieSlot3RstGpio; ///< Offset 2543 Pcie Slot 3 Rest Gpio pin
+ UINT8 PcieSlot3RstGpioPolarity; ///< Offset 2547 Pcie Slot 3 Rest Gpio pin polarity
+ UINT32 PcieSlot3WakeGpio; ///< Offset 2548 Pcie Slot 3 Wake Gpio pin
+ UINT8 PcieSlot3RpNumber; ///< Offset 2552 Pcie Slot 3 Root Port Number
+ UINT32 PchM2Ssd2PowerEnableGpio; ///< Offset 2553 Pch M.2 SSD2 Power Enable Gpio pin
+ UINT8 PchM2Ssd2PowerEnableGpioPolarity; ///< Offset 2557 Pch M.2 SSD2 Power Enable Gpio pin polarity
+ UINT32 PchM2Ssd2RstGpio; ///< Offset 2558 Pch M.2 SSD2 Reset Gpio pin
+ UINT8 PchM2Ssd2RstGpioPolarity; ///< Offset 2562 Pch M.2 SSD2 Reset Gpio pin polarity
+ UINT32 PchM2Ssd3PowerEnableGpio; ///< Offset 2563 Pch M.2 SSD3 Power Enable Gpio pin
+ UINT8 PchM2Ssd3PowerEnableGpioPolarity; ///< Offset 2567 Pch M.2 SSD3 Power Enable Gpio pin polarity
+ UINT32 PchM2Ssd3RstGpio; ///< Offset 2568 Pch M.2 SSD3 Reset Gpio pin
+ UINT8 PchM2Ssd3RstGpioPolarity; ///< Offset 2572 Pch M.2 SSD3 Reset Gpio pin polarity
+ //
+ // XTU SMI base address
+ //
+ UINT32 XtuSmiMemoryAddress; ///< Offset 2573 XTU SMI memory in ACPI NVS
+ UINT8 Reserved19[285]; ///< Offset 2577:2861
+ UINT8 MipiCamLink0DD_LanesClkDivision; ///< Offset 2862 LanesClockDivision
+ UINT8 MipiCamLink1DD_LanesClkDivision; ///< Offset 2863 LanesClockDivision
+ UINT8 MipiCamLink2DD_LanesClkDivision; ///< Offset 2864 LanesClockDivision
+ UINT8 MipiCamLink3DD_LanesClkDivision; ///< Offset 2865 LanesClockDivision
+ UINT8 MipiCamLink4DD_LanesClkDivision; ///< Offset 2866 LanesClockDivision
+ UINT8 MipiCamLink5DD_LanesClkDivision; ///< Offset 2867 LanesClockDivision
+ UINT32 POVP; ///< Offset 2868 USBC_PSON_OVERRIDE_N Input pin
+ UINT32 PSG1; ///< Offset 2872 S0IX_EN_TRY_REQ Output pin
+ UINT32 PSG2; ///< Offset 2876 S0IX_EN_TRY_ACK Input pin
+ UINT32 PPOE; ///< Offset 2880 Option to enable/disable TCSS PD PS_ON
+ UINT8 CvfUsbPort; ///< Offset 2884 CVF USB port number
+ UINT64 DgBaseAddress; ///< Offset 2885 DG PCIe Base Address
+ UINT32 DgOpRegionAddress; ///< Offset 2893 DG OpRegion Base Address
+ UINT32 LidSwitchWakeGpio; ///< Offset 2897 Lid Switch Wake Gpio
+ UINT8 PreBootCmMode; ///< Offset 2901 USB4 CM mode information in Pre-Boot
+ UINT8 CmTbtMask; ///< Offset 2902 Indicate enabled dTBT and iTBT for CM
+ // UCSI/UCMX Driver Support. 0: Force Disable, 1: UCSI Driver support, 2: UCMX Driver support.
+ UINT32 FoxLanWakeGpio; ///< Offset 2903 Foxville I225 Wake Gpio pin
+ UINT32 FoxLanRstGpio; ///< Offset 2907 Foxville I225 Reset Gpio pin
+ UINT8 FoxLanRstGpioPolarity; ///< Offset 2911 Foxville I225 Reset Gpio pin polarity
+ UINT32 FoxLanDisableNGpio; ///< Offset 2912 Foxville I225 Disable N Gpio pin
+ UINT8 FoxLanDisableNGpioPolarity; ///< Offset 2916 Foxville I225 Disable N Gpio pin polarity
+ UINT8 FoxLanSupport; ///< Offset 2917 Foxville I225 support configuration
+ UINT8 FoxLanRpNumber; ///< Offset 2918 Foxville I225 PCIe Root Port Number
+ UINT8 DPIW; ///< Offset 2919 DPin Dynamic Switch
+ UINT32 DPG1; ///< Offset 2920 PcdDpMuxGpio
+ //
+ // Data Role Swap:
+ //
+ UINT8 UsbcDataRoleSwap; ///< Offset 2924 Usbc Data Role Swap
+ UINT8 Usb4CmSwitchEnable; ///< Offset 2925 USB4 CM mode switch is enabled/disabled
+ //Flash ID support for discrete flash solution
+ UINT8 MipiCamLink0DD_FlashID; ///< Offset 2926 Flash ID for Link0
+ UINT8 MipiCamLink1DD_FlashID; ///< Offset 2927 Flash ID for Link1
+ UINT8 MipiCamLink2DD_FlashID; ///< Offset 2928 Flash ID for Link2
+ UINT8 MipiCamLink3DD_FlashID; ///< Offset 2929 Flash ID for Link3
+ UINT8 MipiCamLink4DD_FlashID; ///< Offset 2930 Flash ID for Link4
+ UINT8 MipiCamLink5DD_FlashID; ///< Offset 2931 Flash ID for Link5
+ //ZPODD support
+ UINT32 ZpoddDAGpio; ///< Offset 2932 ZPODD device attention gpio
+ UINT32 ZpoddPRGpio; ///< Offset 2936 ZPODD device present gpio
+ UINT32 ZpoddPWGpio; ///< Offset 2940 ZPODD device power gpio
+ UINT8 ZpoddPWGpioPolarity; ///< Offset 2944 ZPODD device power gpio polarity
+ UINT8 PcdH8S2113UAR; ///< Offset 2945 H8S2113 UAR
+ // Onboard MR support (for ADL S8 only)
+ UINT32 OnBoardMr1PowerEnableGpio; ///< Offset 2946 Onboard MR 1 Power Enable Gpio pin
+ UINT8 OnBoardMr1PowerEnableGpioPolarity; ///< Offset 2950 Onboard MR 1 Power Enable Gpio pin polarity
+ UINT32 OnBoardMr1RstGpio; ///< Offset 2951 Onboard MR 1 Rest Gpio pin
+ UINT8 OnBoardMr1RstGpioPolarity; ///< Offset 2955 Onboard MR 1 Rest Gpio pin polarity
+ UINT32 OnBoardMr1WakeGpio; ///< Offset 2956 Onboard MR 1 Wake Gpio pin
+ UINT8 OnBoardMr1RpNumber; ///< Offset 2960 Onboard MR 1 Root Port Number
+ // Onboard MR support
+ UINT32 OnBoardMr2PowerEnableGpio; ///< Offset 2961 Onboard MR 2 Power Enable Gpio pin
+ UINT8 OnBoardMr2PowerEnableGpioPolarity; ///< Offset 2965 Onboard MR 2 Power Enable Gpio pin polarity
+ UINT32 OnBoardMr2RstGpio; ///< Offset 2966 Onboard MR 2 Rest Gpio pin
+ UINT8 OnBoardMr2RstGpioPolarity; ///< Offset 2970 Onboard MR 2 Rest Gpio pin polarity
+ UINT32 OnBoardMr2WakeGpio; ///< Offset 2971 Onboard MR 2 Wake Gpio pin
+ UINT8 OnBoardMr2RpNumber; ///< Offset 2975 Onboard MR 2 Root Port Number
+ UINT8 Rp08D3ColdSupport; ///< Offset 2976 RP08 D3Cold Support
+ UINT32 DisplayMuxGpioNo; ///< Offset 2977 Display Mux GPIO pin
+ UINT8 DgBrightnessPercentage; ///< Offset 2981 DG eDP Brightness Level Percentage
+ UINT8 DgNumberOfValidDeviceId; ///< Offset 2982 DG Number of Valid Device IDs
+ UINT32 DgDeviceId1; ///< Offset 2983 DG Device ID 1
+ UINT32 DgDeviceId2; ///< Offset 2987 DG Device ID 2
+ UINT32 DgDeviceId3; ///< Offset 2991 DG Device ID 3
+ UINT32 DgDeviceId4; ///< Offset 2995 DG Device ID 4
+ UINT32 DgDeviceId5; ///< Offset 2999 DG Device ID 5
+ UINT32 DgDeviceId6; ///< Offset 3003 DG Device ID 6
+ UINT32 DgDeviceId7; ///< Offset 3007 DG Device ID 7
+ UINT32 DgDeviceId8; ///< Offset 3011 DG Device ID 8
+ UINT32 DgDeviceId9; ///< Offset 3015 DG Device ID 9
+ UINT32 DgDeviceId10; ///< Offset 3019 DG Device ID 10
+ UINT32 DgDeviceId11; ///< Offset 3023 DG Device ID 11
+ UINT32 DgDeviceId12; ///< Offset 3027 DG Device ID 12
+ UINT32 DgDeviceId13; ///< Offset 3031 DG Device ID 13
+ UINT32 DgDeviceId14; ///< Offset 3035 DG Device ID 14
+ UINT32 DgDeviceId15; ///< Offset 3039 DG Device ID 15
+ UINT32 DgDeviceIdX; ///< Offset 3043 DG Device ID for eDP device
+ UINT8 DgDisplaySupportFlag; ///< Offset 3047 _DOS DG Display Support Flag.
+ UINT8 ZpoddPortBitmask; ///< Offset 3048 Bitmask of port support zpodd
+} PLATFORM_NVS_AREA;
+
+#pragma pack(pop)
+#endif
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Include/PlatformPostCode.h b/Platform/Intel/AlderlakeOpenBoardPkg/Include/PlatformPostCode.h
new file mode 100644
index 0000000000..07657c219f
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Include/PlatformPostCode.h
@@ -0,0 +1,39 @@
+/** @file
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+#ifndef _PLATFORMPOSTCODE_H_
+#define _PLATFORMPOSTCODE_H_
+
+//
+// GENERAL USAGE GUIDELINES
+//
+
+/**
+[definition]
+PostCode = XYZZ
+X - "D"=premem, "9"=postmem, "8"=SMM, "7"=DXE
+Y - "6"=platform driver, "5"=board driver
+ZZ - "00"=entry, "7F"=exit
+ - 1 - board init premem: entry/exit (0xD500/0xD57F)
+ - 2 - platform init premem: entry/exit (0xD600/0xD67F)
+ - 3 - board init postmem: entry/exit (0x9500/0x957F)
+ - 4 - platform init postmem: entry/exit (0x9600/0x967F)
+ - 5 - board init DXE: entry/exit (0x7500/0x757F)
+ - 6 - platform init DXE: entry/exit (0x7600/0x767F)
+ - 7 - platform SMM init: entry/exit (0x8600/0x867F)
+ - 8 - BIOS S3 entry (0xB503) means BioS PC 03, to differentiate with ACPI _PTS PC
+ - 9 - BIOS S4 entry (0xB504) means BioS PC 04, to differentiate with ACPI _PTS PC
+ - 10 - BIOS S5 entry (0B505) means BioS PC 05, to differentiate with ACPI _PTS PC
+*/
+
+#define PLATFORM_INIT_PREMEM_ENTRY 0xD600
+#define PLATFORM_INIT_PREMEM_EXIT 0xD67F
+#define PLATFORM_INIT_POSTMEM_ENTRY 0x9600
+#define PLATFORM_INIT_POSTMEM_EXIT 0x967F
+#define PLATFORM_SMM_INIT_ENTRY 0x8600
+#define PLATFORM_SMM_INIT_EXIT 0x867F
+
+#endif
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Include/PolicyUpdateMacro.h b/Platform/Intel/AlderlakeOpenBoardPkg/Include/PolicyUpdateMacro.h
new file mode 100644
index 0000000000..c9ace9d910
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Include/PolicyUpdateMacro.h
@@ -0,0 +1,48 @@
+/** @file
+ Macros for platform to update different types of policy.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _POLICY_UPDATE_MACRO_H_
+#define _POLICY_UPDATE_MACRO_H_
+
+#ifdef UPDATE_POLICY
+#undef UPDATE_POLICY
+#endif
+
+#ifdef COPY_POLICY
+#undef COPY_POLICY
+#endif
+
+#ifdef GET_POLICY
+#undef GET_POLICY
+#endif
+
+#ifdef AND_POLICY
+#undef AND_POLICY
+#endif
+
+#ifdef OR_POLICY
+#undef OR_POLICY
+#endif
+
+#define UPDATE_POLICY(UpdField, ConfigField, Value) ConfigField = Value;
+#define COPY_POLICY(UpdField, ConfigField, Value, Size) CopyMem (ConfigField, Value, Size);
+#define GET_POLICY(UpdField, ConfigField, Value) Value = ConfigField;
+#define AND_POLICY(UpdField, ConfigField, Value) ConfigField &= Value;
+#define OR_POLICY(UpdField, ConfigField, Value) ConfigField |= Value;
+//
+// Compare Policy Default and Setup Default when FirstBoot and RvpSupport
+//
+
+#define COMPARE_AND_UPDATE_POLICY(UpdField, ConfigField, Value) {\
+ UPDATE_POLICY(UpdField, ConfigField, Value);\
+}
+#define COMPARE_UPDATE_POLICY_ARRAY(UpdField, ConfigField, Value, ArrayIndex) {\
+ UPDATE_POLICY(UpdField, ConfigField, Value);\
+}
+
+#endif //_POLICY_UPDATE_MACRO_H_
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Include/Protocol/PlatformNvsArea.h b/Platform/Intel/AlderlakeOpenBoardPkg/Include/Protocol/PlatformNvsArea.h
new file mode 100644
index 0000000000..6efd40c2b6
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Include/Protocol/PlatformNvsArea.h
@@ -0,0 +1,36 @@
+/** @file
+ This file defines the Platform NVS Area Protocol.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _PLATFORM_NVS_AREA_H_
+#define _PLATFORM_NVS_AREA_H_
+
+//
+// Platform NVS Area definition
+//
+#include <PlatformNvsAreaDef.h>
+
+//
+// Includes
+//
+#define PLATFORM_NVS_DEVICE_ENABLE 1
+#define PLATFORM_NVS_DEVICE_DISABLE 0
+
+//
+// Forward reference for pure ANSI compatibility
+//
+typedef struct _PLATFORM_NVS_AREA_PROTOCOL PLATFORM_NVS_AREA_PROTOCOL;
+
+
+//
+// Platform NVS Area Protocol
+//
+typedef struct _PLATFORM_NVS_AREA_PROTOCOL {
+ PLATFORM_NVS_AREA *Area;
+} PLATFORM_NVS_AREA_PROTOCOL;
+
+#endif // _PLATFORM_NVS_AREA_H_
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/OpenBoardPkg.dec b/Platform/Intel/AlderlakeOpenBoardPkg/OpenBoardPkg.dec
new file mode 100644
index 0000000000..d24daf30b5
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/OpenBoardPkg.dec
@@ -0,0 +1,605 @@
+## @file
+#
+# The DEC files are used by the utilities that parse DSC and
+# INF files to generate AutoGen.c and AutoGen.h files
+# for the build infrastructure.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+DEC_SPECIFICATION = 0x00010017
+PACKAGE_NAME = BoardPkg
+PACKAGE_VERSION = 0.1
+PACKAGE_GUID = A840FA72-FBF7-4357-B301-DAE2233F14AB
+
+[Includes]
+Include
+Acpi/AcpiTables
+Acpi/AcpiTables/Include
+Acpi/AcpiTables/Dsdt
+Acpi/AcpiTables/Mcfg
+
+[Guids]
+ gBoardModuleTokenSpaceGuid = {0x72d1fff7, 0xa42a, 0x4219, {0xb9, 0x95, 0x5a, 0x67, 0x53, 0x6e, 0xa4, 0x2a}}
+ gPlatformModuleTokenSpaceGuid = {0x69d13bf0, 0xaf91, 0x4d96, {0xaa, 0x9f, 0x21, 0x84, 0xc5, 0xce, 0x3b, 0xc0}}
+ gPlatformInitFvLocationGuid = {0xa564010a, 0x1d90, 0x4b1c, {0x8d, 0x10, 0xcb, 0xba, 0xff, 0xb2, 0x55, 0x42}}
+ gAcpiTableStorageGuid = {0x7e374e25, 0x8e01, 0x4fee, {0x87, 0xf2, 0x39, 0x0c, 0x23, 0xc6, 0x06, 0xcd}}
+ gRcAcpiTableStorageGuid = {0x6b5c8fe5, 0x70dd, 0x4e17, {0xbf, 0xf4, 0xd2, 0x1c, 0x26, 0x58, 0x6e, 0xb3}}
+ gVpdFfsGuid = {0x338FA35A, 0xCA4A, 0x4DBC, {0xA6, 0xF4, 0x9B, 0xD1, 0x59, 0x3B, 0x61, 0xBC}}
+ gS3MemoryVariableGuid = {0x973218b9, 0x1697, 0x432a, {0x8b, 0x34, 0x48, 0x84, 0xb5, 0xdf, 0xb3, 0x59}}
+ gSetupDataHobGuid = {0x822a9b23, 0x2386, 0x4377, { 0xb7, 0x05, 0x87, 0x78, 0xc1, 0xb8, 0xb3, 0x95}}
+ gBoardInfoVariableGuid = {0x1E785E1A, 0x8EC4, 0x49E4, {0x82, 0x75, 0xFB, 0xBD, 0xED, 0xED, 0x18, 0xE7}}
+ gDebugConfigVariableGuid = {0xDE0A5E74, 0x4E3E, 0x3D96, {0xA4, 0x40, 0x2C, 0x96, 0xEC, 0xBD, 0x3C, 0x97}}
+ gBiosInfoRecoveryGuid = {0x230f6679, 0xf703, 0x4dc2, {0xb2, 0xb7, 0x41, 0xc6, 0x70, 0xbc, 0xc0, 0xd1}}
+ gMemoryConfigVariableGuid = {0xc94f8c4d, 0x9b9a, 0x45fe, {0x8a, 0x55, 0x23, 0x8b, 0x67, 0x30, 0x26, 0x43}}
+
+## Include/BootState.h
+ gBootStateGuid = {0x60b5e939, 0x0fcf, 0x4227, {0xba, 0x83, 0x6b, 0xbe, 0xd4, 0x5b, 0xc0, 0xe3}}
+
+#
+# FvImage File
+#
+ gFvAdvancedFileGuid = {0xAD198BA5, 0xC330, 0x41CD, {0xB0, 0x97, 0x16, 0x48, 0x83, 0x28, 0xB7, 0x98}}
+ gFvOsBootFileGuid = {0xB9020753, 0x84A8, 0x4BB6, {0x94, 0x7C, 0xCE, 0x7D, 0x41, 0xF5, 0xCE, 0x39}}
+ gFvUefiBootFileGuid = {0x9E21FD93, 0x9C72, 0x4c15, {0x8C, 0x4B, 0xE7, 0x7F, 0x1D, 0xB2, 0xD7, 0x92}}
+ gTianoLogoGuid = {0x7BB28B99, 0x61BB, 0x11D5, {0x9A, 0x5D, 0x00, 0x90, 0x27, 0x3F, 0xC1, 0x4D}}
+
+ # gUefiShellFileGuid is FILE GUID for MinUefiShell.inf/UefiShell.inf/Shell.inf.
+ gUefiShellFileGuid = {0x7c04a583, 0x9e3e, 0x4f1c, {0xad, 0x65, 0xe0, 0x52, 0x68, 0xd0, 0xb4, 0xd1}}
+
+[Protocols]
+ gPlatformNvsAreaProtocolGuid = {0xc77ae556, 0x40a3, 0x41c0, {0xac, 0xe6, 0x71, 0x43, 0x8c, 0x60, 0xf8, 0x71}}
+ gFvAppDispatchFlagProtocolGuid = {0x47458821, 0x44a3, 0x43f6, {0x90, 0xda, 0xdf, 0xdf, 0xce, 0x62, 0xf4, 0xfc}}
+
+[Ppis]
+ gReadyForGopConfigPpiGuid = {0x5f252c18, 0x1781, 0x4290, {0xa7, 0xb6, 0xfd, 0x99, 0x63, 0x4c, 0x6a, 0x8a}}
+ gPeiFvCnvDispatchFlagPpiGuid = {0x2ea45093, 0xa4e6, 0x42ac, {0x86, 0xcf, 0x5e, 0xc6, 0xbf, 0xfb, 0x88, 0x85}}
+ gPatchConfigurationDataPreMemPpiGuid = {0xa09b1a0c, 0x690c, 0x4d48, {0xa8, 0x98, 0xa1, 0x2c, 0x94, 0x26, 0xd7, 0x06}}
+ gSetupVariablesReadyPpiGuid = {0xda549f2b, 0xb2ed, 0x43a2, {0xb2, 0x4d, 0xc3, 0x67, 0x67, 0xa8, 0xcf, 0x27}}
+
+
+[LibraryClasses]
+
+[PcdsFixedAtBuild, PcdsPatchableInModule]
+##
+## PcdSmbiosOemTypeFirmwareVersionInfo determines the SMBIOS OEM type (0x80 to 0xFF) defined in SMBIOS,
+## values 0-0x7F will be treated as disable FVI reporting.
+## FVI structure uses it as SMBIOS OEM type to provide version information.
+##
+gPlatformModuleTokenSpaceGuid.PcdSmbiosOemTypeFirmwareVersionInfo|0xDD|UINT8|0x20000001
+
+[PcdsFixedAtBuild]
+ gBoardModuleTokenSpaceGuid.PcdDefaultBoardId|0|UINT16|0x10101009
+
+ gBoardModuleTokenSpaceGuid.PcdLpcIoDecodeRange|0x0010|UINT16|0x10001010
+ gBoardModuleTokenSpaceGuid.PchLpcIoEnableDecoding|0x3c03|UINT16|0x10001011
+
+ gBoardModuleTokenSpaceGuid.PcdLpcSioIndexPort|0x4e|UINT16|0x90000018
+ gBoardModuleTokenSpaceGuid.PcdLpcSioDataPort|0x4f|UINT16|0x9000001F
+
+ gBoardModuleTokenSpaceGuid.PcdLpcSioConfigDefaultPort|0x164E|UINT16|0x9000001C
+ gBoardModuleTokenSpaceGuid.PcdSioBaseAddress|0x0680|UINT16|0x9000001D
+
+ gBoardModuleTokenSpaceGuid.PcdSetupEnable |FALSE|BOOLEAN|0xF0000027
+ gBoardModuleTokenSpaceGuid.PcdModularCryptoEnable |FALSE|BOOLEAN|0xF000001B
+
+ ##
+ ## The Flash PCDs will be patched based on FDF definitions during build.
+ ## Set them to 0 here to prevent confusion.
+ ##
+
+ gBoardModuleTokenSpaceGuid.PcdFlashFvFirmwareBinariesBase|0x00000000|UINT32|0x20000040
+ gBoardModuleTokenSpaceGuid.PcdFlashFvFirmwareBinariesSize|0x00000000|UINT32|0x20000041
+ gBoardModuleTokenSpaceGuid.PcdFlashFvFirmwareBinariesOffset|0x00000000|UINT32|0x20000042
+ gBoardModuleTokenSpaceGuid.PcdFlashFvOptionalBase|0x00000000|UINT32|0x2000004C
+ gBoardModuleTokenSpaceGuid.PcdFlashFvOptionalSize|0x00000000|UINT32|0x2000004D
+ gBoardModuleTokenSpaceGuid.PcdFlashFvOptionalOffset|0x00000000|UINT32|0x2000004E
+ gBoardModuleTokenSpaceGuid.PcdFlashExtendRegionOffset|0x00000000|UINT32|0x20000050
+ gBoardModuleTokenSpaceGuid.PcdFlashExtendRegionSizeInUse|0x00000000|UINT32|0x20000051
+ gBoardModuleTokenSpaceGuid.PcdFlashFvExtendedPostMemoryBase|0x00000000|UINT32|0x20000052
+ gBoardModuleTokenSpaceGuid.PcdFlashFvExtendedPostMemorySize|0x00000000|UINT32|0x20000054
+ gBoardModuleTokenSpaceGuid.PcdFlashFvExtendedAdvancedBase|0x00000000|UINT32|0x20000055
+ gBoardModuleTokenSpaceGuid.PcdFlashFvExtendedAdvancedSize|0x00000000|UINT32|0x20000057
+
+ gBoardModuleTokenSpaceGuid.PcdSipkgBinaryEnable |FALSE|BOOLEAN|0xF0000A50
+ gBoardModuleTokenSpaceGuid.PcdFlashObbSize|0x00000000|UINT32|0xF0000A53
+ gBoardModuleTokenSpaceGuid.PcdFlashIbbOffset|0x00000000|UINT32|0xF0000A58
+ gBoardModuleTokenSpaceGuid.PcdFlashIbbSize|0x00000000|UINT32|0xF0000A59
+ gBoardModuleTokenSpaceGuid.PcdFlashFvRsvdOffset|0x00000000|UINT32|0x20000A5E
+ gBoardModuleTokenSpaceGuid.PcdFlashFvRsvdSize|0x00000000|UINT32|0x20000A5F
+ gBoardModuleTokenSpaceGuid.PcdFlashIbbROffset|0x00000000|UINT32|0x20000A61
+
+#(ACPI.inf)
+ gPlatformModuleTokenSpaceGuid.PcdApicLocalAddress|0xFEE00000|UINT64|0x9000000B
+ gPlatformModuleTokenSpaceGuid.PcdApicIoAddress|0xFEC00000|UINT64|0x9000000D
+ gPlatformModuleTokenSpaceGuid.PcdAcpiEnableSwSmi|0xF0|UINT8|0x90000012
+ gPlatformModuleTokenSpaceGuid.PcdAcpiDisableSwSmi|0xF1|UINT8|0x90000013
+ gPlatformModuleTokenSpaceGuid.PcdApicIoIdPch|0x02|UINT8|0x9000001E
+
+#(PeiMultiBoardInitPreMemLib.inf)
+ gPlatformModuleTokenSpaceGuid.PcdDesktopLpcSioDataDefaultPort|0x2F|UINT16|0x9000001A
+ gPlatformModuleTokenSpaceGuid.PcdDesktopLpcSioIndexDefaultPort|0x2E|UINT16|0x9000001B
+
+#(BaseMmioInitLib.inf)
+gPlatformModuleTokenSpaceGuid.PcdDmiBaseAddress|0xFEDA0000|UINT64|0x90000003
+## From Client SNB EDS 0.7v3, 4KB window
+gPlatformModuleTokenSpaceGuid.PcdEpBaseAddress|0xFEDA1000|UINT64|0x90000005
+
+#(OpenBoardPlatformInitPreMem.inf)
+gPlatformModuleTokenSpaceGuid.PcdRamDebugEnable |FALSE|BOOLEAN|0xF0000094
+gPlatformModuleTokenSpaceGuid.PcdSerialPortEnable |FALSE|BOOLEAN|0xF000002D
+
+#(OpenBoardPlatformInitSmm.inf)
+gPlatformModuleTokenSpaceGuid.PcdSmcExtSmiBitPosition|0x01|UINT8|0x90000015
+
+## This PCD specifies whether StatusCode is reported via SerialIoUart
+gPlatformModuleTokenSpaceGuid.PcdStatusCodeUseSerialIoUart|FALSE|BOOLEAN|0xFF000002
+
+## This flag is used to initialize debug output interface.
+# BIT0 - RAM debug interface.
+# BIT1 - UART debug interface.
+# BIT2 - USB debug interface.
+# BIT3 - USB3 debug interface.
+# BIT4 - Serial IO debug interface.
+# BIT5 - TraceHub debug interface.
+# BIT6 - Reserved.
+# BIT7 - CMOS control.
+gPlatformModuleTokenSpaceGuid.PcdStatusCodeFlags|0x82|UINT8|0xF0000111
+
+gPlatformModuleTokenSpaceGuid.PcdGttMmAddress|0xAF000000|UINT64|0x9000000F
+gPlatformModuleTokenSpaceGuid.PcdGmAdrAddress|0xB0000000|UINT64|0x90000010
+
+gPlatformModuleTokenSpaceGuid.PcdEdramBaseAddress|0xFED80000|UINT64|0x90000009
+gPlatformModuleTokenSpaceGuid.PcdExtendedBiosRegionSupport|FALSE|BOOLEAN|0xF00000A3
+
+gPlatformModuleTokenSpaceGuid.PcdLzmaEnable |FALSE|BOOLEAN|0xF000002B
+gPlatformModuleTokenSpaceGuid.PcdSymbolInReleaseEnable |FALSE|BOOLEAN|0xF0000063
+gPlatformModuleTokenSpaceGuid.PcdDeprecatedFunctionRemove |TRUE|BOOLEAN|0xF000008D
+
+## Enable/Disable the ECC feature in openssl library. The default is disabled.
+# If ECC feature is disabled, all related source files will not be compiled.
+gEfiCryptoPkgTokenSpaceGuid.PcdOpensslEcEnabled|FALSE|BOOLEAN|0x0000003
+
+
+[PcdsDynamic, PcdsPatchableInModule]
+
+[PcdsDynamic]
+
+ # PCH Misc Configuration
+ gBoardModuleTokenSpaceGuid.PcdMipiCamGpioEnable|FALSE|BOOLEAN|0x00000065
+ gBoardModuleTokenSpaceGuid.PcdUsbcEcPdNegotiation|FALSE|BOOLEAN|0x00000110
+
+ # DRAM Configuration
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdData00|0|UINT32|0x00000170
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdData01|0|UINT32|0x00000171
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdData10|0|UINT32|0x00000172
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdData11|0|UINT32|0x00000173
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdData|0|UINT32|0x00000174
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdDataSize|0|UINT16|0x00000175
+ gBoardModuleTokenSpaceGuid.PcdMrcDqMapCpu2Dram|0|UINT32|0x00000072
+ gBoardModuleTokenSpaceGuid.PcdMrcDqMapCpu2DramSize|0|UINT16|0x00000073
+
+ # SPD Address Table
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable0|0|UINT8|0x00000199
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable1|0|UINT8|0x0000019A
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable2|0|UINT8|0x0000019B
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable3|0|UINT8|0x0000019C
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable4|0|UINT8|0x0000019D
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable5|0|UINT8|0x0000019E
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable6|0|UINT8|0x0000019F
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable7|0|UINT8|0x000001A0
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable8|0|UINT8|0x000001A1
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable9|0|UINT8|0x000001A2
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable10|0|UINT8|0x000001A3
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable11|0|UINT8|0x000001A4
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable12|0|UINT8|0x000001A5
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable13|0|UINT8|0x000001A6
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable14|0|UINT8|0x000001A7
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable15|0|UINT8|0x000001A8
+
+ # CA Vref Configuration
+ gBoardModuleTokenSpaceGuid.PcdMrcCaVrefConfig|0|UINT8|0x0000009D
+
+ # Root Port Clock Info
+ gBoardModuleTokenSpaceGuid.PcdPcieClock0|0|UINT64|0x0000009E
+ gBoardModuleTokenSpaceGuid.PcdPcieClock1|0|UINT64|0x0000009F
+ gBoardModuleTokenSpaceGuid.PcdPcieClock2|0|UINT64|0x000000A0
+ gBoardModuleTokenSpaceGuid.PcdPcieClock3|0|UINT64|0x000000A1
+ gBoardModuleTokenSpaceGuid.PcdPcieClock4|0|UINT64|0x000000A2
+ gBoardModuleTokenSpaceGuid.PcdPcieClock5|0|UINT64|0x000000A3
+ gBoardModuleTokenSpaceGuid.PcdPcieClock6|0|UINT64|0x000000A4
+ gBoardModuleTokenSpaceGuid.PcdPcieClock7|0|UINT64|0x000000A5
+ gBoardModuleTokenSpaceGuid.PcdPcieClock8|0|UINT64|0x000000A6
+ gBoardModuleTokenSpaceGuid.PcdPcieClock9|0|UINT64|0x000000A7
+ gBoardModuleTokenSpaceGuid.PcdPcieClock10|0|UINT64|0x000000A8
+ gBoardModuleTokenSpaceGuid.PcdPcieClock11|0|UINT64|0x000000A9
+ gBoardModuleTokenSpaceGuid.PcdPcieClock12|0|UINT64|0x000000AA
+ gBoardModuleTokenSpaceGuid.PcdPcieClock13|0|UINT64|0x000000AB
+ gBoardModuleTokenSpaceGuid.PcdPcieClock14|0|UINT64|0x000000AC
+ gBoardModuleTokenSpaceGuid.PcdPcieClock15|0|UINT64|0x000000AD
+ gBoardModuleTokenSpaceGuid.PcdPcieClock16|0|UINT64|0x000000AE
+ gBoardModuleTokenSpaceGuid.PcdPcieClock17|0|UINT64|0x000000AF
+
+
+ # GPIO Group Tier
+ gBoardModuleTokenSpaceGuid.PcdGpioGroupToGpeDw0|0|UINT32|0x000000E9
+ gBoardModuleTokenSpaceGuid.PcdGpioGroupToGpeDw1|0|UINT32|0x000000EA
+ gBoardModuleTokenSpaceGuid.PcdGpioGroupToGpeDw2|0|UINT32|0x000000EB
+
+
+ # USB 3.0 Port Over Current Pin
+ gBoardModuleTokenSpaceGuid.PcdCpuXhciPortSupportMap|0|UINT8|0x00100031
+ gBoardModuleTokenSpaceGuid.PcdCpuUsb30PortEnable|0|UINT8|0x00100032
+
+ # Display DDI
+ gBoardModuleTokenSpaceGuid.PcdSaDisplayConfigTable|0|UINT32|0x00100033
+ gBoardModuleTokenSpaceGuid.PcdSaDisplayConfigTableSize|0|UINT16|0x00100034
+
+ # MISC
+ gBoardModuleTokenSpaceGuid.PcdPc8374SioKbcPresent|FALSE|BOOLEAN|0x000000ED
+ gBoardModuleTokenSpaceGuid.PcdOddPowerInitEnable|FALSE|BOOLEAN|0x000000EE
+ gBoardModuleTokenSpaceGuid.PcdSmbusAlertEnable|FALSE|BOOLEAN|0x0010101E
+ gBoardModuleTokenSpaceGuid.PcdGpioTier2WakeEnable|FALSE|BOOLEAN|0x00000100
+
+ # STAT
+ gBoardModuleTokenSpaceGuid.PcdSataPortsEnable0|0|UINT8|0x000000F0
+
+ # CPU
+ gBoardModuleTokenSpaceGuid.PcdCpuRatio|0x0|UINT8|0x00000200
+
+ # MISC
+ gBoardModuleTokenSpaceGuid.PcdPs2KbMsEnable|1|UINT8|0x40000A09
+ gBoardModuleTokenSpaceGuid.PcdStackBase|0x0|UINT32|0x40000A10
+ gBoardModuleTokenSpaceGuid.PcdStackSize|0x0|UINT32|0x40000A11
+ gBoardModuleTokenSpaceGuid.PcdNvsBufferPtr|0x0|UINT32|0x40000A12
+ gBoardModuleTokenSpaceGuid.PcdCleanMemory|0x0|UINT8|0x40000A13
+
+ #
+ # The PCD which is defined to enable/disable the SATA LED function.
+ #
+ gBoardModuleTokenSpaceGuid.PcdSataLedEnable|FALSE|BOOLEAN|0x0010111F
+
+ #
+ # The PCD which is defined to enable/disable the VR Alert function.
+ #
+ gBoardModuleTokenSpaceGuid.PcdVrAlertEnable|FALSE|BOOLEAN|0x00101020
+
+ #
+ # This PCD is defined to enable/disable TCSS BIOS handshake for PMC-PD solution
+ #
+ gBoardModuleTokenSpaceGuid.PcdBoardPmcPdEnable|TRUE|BOOLEAN|0x00101024
+
+ # TouchPanel
+ gBoardModuleTokenSpaceGuid.PcdBoardGpioTableTouchPanel1|0|UINT32|0x00000048
+ gBoardModuleTokenSpaceGuid.PcdBoardGpioTableTouchPanel1Size|0|UINT16|0x00000049
+
+
+ # SA Misc Configuration
+ gBoardModuleTokenSpaceGuid.PcdSaMiscUserBd|0|UINT8|0x00000066
+ gBoardModuleTokenSpaceGuid.PcdSaMiscMmioSizeAdjustment|0|UINT16|0x00000067
+ gBoardModuleTokenSpaceGuid.PcdSaDdrFreqLimit|0|UINT16|0x0000A101
+ gBoardModuleTokenSpaceGuid.PcdSaMiscFirstDimmBitMask|0|UINT8|0x0000A103
+ gBoardModuleTokenSpaceGuid.PcdSaMiscFirstDimmBitMaskEcc|0|UINT8|0x0000A104
+ gBoardModuleTokenSpaceGuid.PcdSaMiscDisableMrcRetrainingOnRtcPowerLoss|0|UINT8|0x0000A105
+
+ #CVF GPIO configuration
+ gBoardModuleTokenSpaceGuid.PcdBoardGpioTableCvf|0|UINT32|0x0000B101
+ gBoardModuleTokenSpaceGuid.PcdBoardGpioTableCvfSize|0|UINT16|0x0000B102
+
+ gBoardModuleTokenSpaceGuid.PcdGraphicsVbtGuid|{0x22, 0x61, 0xd4, 0x4a, 0xeb, 0xff, 0x52, 0x4a, 0xbf, 0xb0, 0x51, 0x8c, 0xfc, 0xa0, 0x2d, 0xb0}|VOID*|0x40000014
+
+ # Board Information
+ gBoardModuleTokenSpaceGuid.PcdPlatformGeneration|0x0|UINT8|0x00101011
+ gBoardModuleTokenSpaceGuid.PcdSpdPresent|FALSE|BOOLEAN|0x00101012
+ gBoardModuleTokenSpaceGuid.PcdPlatformType|0x0|UINT8|0x00101014
+ gBoardModuleTokenSpaceGuid.PcdPlatformFlavor|0x0|UINT8|0x00101015
+ gBoardModuleTokenSpaceGuid.PcdBoardRev|0x0|UINT16|0x00101016
+ gBoardModuleTokenSpaceGuid.PcdBoardBomId|0x0|UINT16|0x00101017
+ gBoardModuleTokenSpaceGuid.PcdBoardId|0|UINT16|0x00101018
+ gBoardModuleTokenSpaceGuid.PcdBoardType|0x0|UINT8|0x00101019
+ gBoardModuleTokenSpaceGuid.PcdSkuType|0x0|UINT8|0x0010101F
+ gBoardModuleTokenSpaceGuid.PcdWakeupType|0x0|UINT8|0x00101004
+ gBoardModuleTokenSpaceGuid.PcdDisplayId|0x0|UINT16|0x00101032
+
+ # MRC Config
+ gBoardModuleTokenSpaceGuid.PcdMrcRcompResistor|0|UINT32|0x00000A68
+ gBoardModuleTokenSpaceGuid.PcdMrcRcompTarget|0|UINT32|0x00000A69
+ gBoardModuleTokenSpaceGuid.PcdMrcDqByteMap|0|UINT32|0x00000A6A
+ gBoardModuleTokenSpaceGuid.PcdMrcDqByteMapSize|0|UINT16|0x00000A6B
+ gBoardModuleTokenSpaceGuid.PcdMrcDqsMapCpu2Dram|0|UINT32|0x00000A6C
+ gBoardModuleTokenSpaceGuid.PcdMrcDqsMapCpu2DramSize|0|UINT16|0x00000A6D
+ gBoardModuleTokenSpaceGuid.PcdMrcDqPinsInterleavedControl|FALSE|BOOLEAN|0x00000A6E
+ gBoardModuleTokenSpaceGuid.PcdMrcDqPinsInterleaved|FALSE|BOOLEAN|0x00000A6F
+ gBoardModuleTokenSpaceGuid.PcdMrcLp5CccConfig|0|UINT8|0x00000A73
+ gBoardModuleTokenSpaceGuid.PcdMrcCmdMirror|0|UINT8|0x00000A74
+ gBoardModuleTokenSpaceGuid.PcdRootPortIndex|0xFF|UINT8|0x00000A78
+
+ # USB 2.0 Port Over Current Pin
+ gBoardModuleTokenSpaceGuid.PcdUsb2OverCurrentPinTable|0|UINT32|0x000000BC
+
+ # USB 3.0 Port Over Current Pin
+ gBoardModuleTokenSpaceGuid.PcdUsb3OverCurrentPinTable|0|UINT32|0x000000BE
+
+ # Pch SerialIo I2c Pads Termination
+ gBoardModuleTokenSpaceGuid.PcdPchSerialIoI2c0PadInternalTerm|0x1|UINT8|0x00000020
+ gBoardModuleTokenSpaceGuid.PcdPchSerialIoI2c1PadInternalTerm|0x1|UINT8|0x00000021
+ gBoardModuleTokenSpaceGuid.PcdPchSerialIoI2c2PadInternalTerm|0x1|UINT8|0x00000022
+ gBoardModuleTokenSpaceGuid.PcdPchSerialIoI2c3PadInternalTerm|0x1|UINT8|0x00000023
+ gBoardModuleTokenSpaceGuid.PcdPchSerialIoI2c4PadInternalTerm|0x1|UINT8|0x00000030
+ gBoardModuleTokenSpaceGuid.PcdPchSerialIoI2c5PadInternalTerm|0x1|UINT8|0x00000031
+ gBoardModuleTokenSpaceGuid.PcdPchSerialIoI2c6PadInternalTerm|0x1|UINT8|0x00000032
+ gBoardModuleTokenSpaceGuid.PcdPchSerialIoI2c7PadInternalTerm|0x1|UINT8|0x00000033
+
+ # UCMC GPIO Table
+ gBoardModuleTokenSpaceGuid.PcdBoardUcmcGpio1|0|UINT32|0x0000011B
+ gBoardModuleTokenSpaceGuid.PcdBoardUcmcGpio2|0|UINT32|0x0000011C
+ gBoardModuleTokenSpaceGuid.PcdBoardUcmcGpio3|0|UINT32|0x0000011D
+ gBoardModuleTokenSpaceGuid.PcdBoardUcmcGpio4|0|UINT32|0x0000011E
+
+
+ gBoardModuleTokenSpaceGuid.PcdPreferredPmProfile|0x0|UINT8|0x00100205
+
+ #PlatformInfoPcd
+ gBoardModuleTokenSpaceGuid.PcdEnableVoltageMargining|FALSE|BOOLEAN|0x00101000
+
+ #
+ # The PCD defines the I2C bus number to which PSS chip connected.
+ #
+ gBoardModuleTokenSpaceGuid.PcdPssReadSN|FALSE|BOOLEAN|0x00101025
+ gBoardModuleTokenSpaceGuid.PcdPssI2cBusNumber|0x05|UINT8|0x00101026
+ gBoardModuleTokenSpaceGuid.PcdPssI2cSlaveAddress|0x6E|UINT8|0x00101027
+
+ # PCIE SLOT 1 - X4 CONNECTOR RTD3
+ gBoardModuleTokenSpaceGuid.PcdPcieSlot1GpioSupport|0|UINT8|0x00000A79
+ gBoardModuleTokenSpaceGuid.PcdPcieSlot1PwrEnableExpanderNo|0|UINT8|0x00000A7D
+ gBoardModuleTokenSpaceGuid.PcdPcieSlot1PwrEnableGpioNo|0|UINT32|0x00000A7E
+ gBoardModuleTokenSpaceGuid.PcdPcieSlot1WakeGpioPin|0x0|UINT32|0x00000A80
+ gBoardModuleTokenSpaceGuid.PcdDg1VramSRGpio|0x0|UINT32|0x00000A82
+
+
+ # PCIE SLOT 2 - X4 CONNECTOR RTD3
+ gBoardModuleTokenSpaceGuid.PcdPchPCIeSlot2PwrEnableGpioNo|0|UINT32|0x00000084
+ gBoardModuleTokenSpaceGuid.PcdPchPCIeSlot2PwrEnableGpioPolarity|0|BOOLEAN|0x00000085
+ gBoardModuleTokenSpaceGuid.PcdPcieSlot2WakeGpioPin|0|UINT32|0x00000088
+ gBoardModuleTokenSpaceGuid.PcdPcieSlot2RootPort|0|UINT8|0x0000008A
+
+ # CPU M.2 SSD Slot RTD3
+ gBoardModuleTokenSpaceGuid.PcdPcieSsd2PwrEnableGpioNo|0|UINT32|0x0000008B
+ gBoardModuleTokenSpaceGuid.PcdPcieSsd2PwrEnableGpioPolarity|0|BOOLEAN|0x0000008D
+ gBoardModuleTokenSpaceGuid.PcdPcieSsd3PwrEnableGpioNo|0|UINT32|0x00000101
+ gBoardModuleTokenSpaceGuid.PcdPcieSsd3PwrEnableGpioPolarity|0|BOOLEAN|0x00000109
+
+ # CPU Peg DG Slot RTD3
+ gBoardModuleTokenSpaceGuid.PcdPcieDG2PwrEnableGpioNo|0|UINT32|0x00000105
+ gBoardModuleTokenSpaceGuid.PcdPcieDG2PwrEnableGpioPolarity|0|BOOLEAN|0x00000107
+ gBoardModuleTokenSpaceGuid.PcdPcieDG2WakeGpioPin|0|UINT32|0x00000113
+
+ # PCH SATA port RTD3
+ gBoardModuleTokenSpaceGuid.PcdPchSataPortPwrEnableGpioNo|0|UINT32|0x0000008F
+ gBoardModuleTokenSpaceGuid.PcdPchSataPortPwrEnableGpioPolarity|0|BOOLEAN|0x00000400
+
+
+ # DXE PCDs
+ gBoardModuleTokenSpaceGuid.PcdBoardRtd3TableSignature|0x0|UINT64|0x00100250
+ gBoardModuleTokenSpaceGuid.PcdSpdAddressOverride|FALSE|BOOLEAN|0x00100203
+ gBoardModuleTokenSpaceGuid.PcdXhciAcpiTableSignature|0x0|UINT64|0x00100204
+ gBoardModuleTokenSpaceGuid.PcdTsOnDimmTemperature|FALSE|BOOLEAN|0x00100123
+ gBoardModuleTokenSpaceGuid.PcdDimmPopulationError|FALSE|BOOLEAN|0x00100221
+
+
+ # ASL PCDs
+ gBoardModuleTokenSpaceGuid.PcdBatteryPresent |0x0|UINT8|0x00100124
+ gBoardModuleTokenSpaceGuid.PcdRealBattery1Control |0x00|UINT8|0x00100103
+ gBoardModuleTokenSpaceGuid.PcdRealBattery2Control |0x00|UINT8|0x00100104
+ gBoardModuleTokenSpaceGuid.PcdNCT6776FCOM |FALSE|BOOLEAN|0x00100107
+ gBoardModuleTokenSpaceGuid.PcdNCT6776FSIO |FALSE|BOOLEAN|0x00100108
+ gBoardModuleTokenSpaceGuid.PcdNCT6776FHWMON |FALSE|BOOLEAN|0x00100109
+ gBoardModuleTokenSpaceGuid.PcdH8S2113SIO |FALSE|BOOLEAN|0x0010010A
+ gBoardModuleTokenSpaceGuid.PcdH8S2113UAR |FALSE|BOOLEAN|0x0010010B
+ gBoardModuleTokenSpaceGuid.PcdSmcRuntimeSciPin |0x00|UINT32|0x00100111
+ gBoardModuleTokenSpaceGuid.PcdVirtualButtonVolumeUpSupport |FALSE|BOOLEAN|0x00100119
+ gBoardModuleTokenSpaceGuid.PcdVirtualButtonVolumeDownSupport |FALSE|BOOLEAN|0x0010011A
+ gBoardModuleTokenSpaceGuid.PcdVirtualButtonHomeButtonSupport |FALSE|BOOLEAN|0x0010011B
+ gBoardModuleTokenSpaceGuid.PcdVirtualButtonRotationLockSupport |FALSE|BOOLEAN|0x0010011C
+ gBoardModuleTokenSpaceGuid.PcdSlateModeSwitchSupport |FALSE|BOOLEAN|0x0010011D
+ gBoardModuleTokenSpaceGuid.PcdVirtualGpioButtonSupport |FALSE|BOOLEAN|0x0010011E
+ gBoardModuleTokenSpaceGuid.PcdPmPowerButtonGpioPin |0x00|UINT32|0x00100120
+ gBoardModuleTokenSpaceGuid.PcdAcpiEnableAllButtonSupport |FALSE|BOOLEAN|0x00100121
+ gBoardModuleTokenSpaceGuid.PcdAcpiHidDriverButtonSupport |FALSE|BOOLEAN|0x00100122
+
+ # Policy Default Check with Setup Necessary
+ gBoardModuleTokenSpaceGuid.PcdPolicyCheckIsFirstBoot|0|BOOLEAN|0x00000275
+ gBoardModuleTokenSpaceGuid.PcdPolicyCheckIsRvpSupport|0|BOOLEAN|0x00000276
+ gBoardModuleTokenSpaceGuid.PcdPolicyCheckPcdInitDone|0|BOOLEAN|0x00000277
+
+[PcdsDynamicEx]
+# Flag to Disable Vpd Gpio
+gBoardModuleTokenSpaceGuid.PcdDisableVpdGpioTable|FALSE|BOOLEAN|0x50000015
+# Pre-Mem GPIO table
+ gBoardModuleTokenSpaceGuid.PcdBoardGpioTablePreMem|{0}|GPIO_INIT_CONFIG_ARRAY|0x50000017 {
+ <HeaderFiles>
+ Pins/GpioPinsVer2Lp.h
+ Library/GpioLib.h
+ PlatformGpioConfig.h
+ <Packages>
+ MdePkg/MdePkg.dec
+ AlderlakeSiliconPkg/SiPkg.dec
+ AlderlakeOpenBoardPkg/OpenBoardPkg.dec
+}
+
+ gBoardModuleTokenSpaceGuid.VpdPcdBoardGpioTablePreMem|{0}|GPIO_INIT_CONFIG[]|0x50000018 {
+ <HeaderFiles>
+ Pins/GpioPinsVer2Lp.h
+ Library/GpioLib.h
+ Library/GpioConfig.h
+ <Packages>
+ MdePkg/MdePkg.dec
+ AlderlakeSiliconPkg/SiPkg.dec
+ AlderlakeOpenBoardPkg/OpenBoardPkg.dec
+}
+
+# GPIO table
+ gBoardModuleTokenSpaceGuid.PcdBoardGpioTable|{0}|GPIO_INIT_CONFIG_ARRAY|0x50000019 {
+ <HeaderFiles>
+ Pins/GpioPinsVer2Lp.h
+ Library/GpioLib.h
+ PlatformGpioConfig.h
+ <Packages>
+ MdePkg/MdePkg.dec
+ AlderlakeSiliconPkg/SiPkg.dec
+ AlderlakeOpenBoardPkg/OpenBoardPkg.dec
+}
+ gBoardModuleTokenSpaceGuid.VpdPcdBoardGpioTable|{0}|GPIO_INIT_CONFIG[]|0x5000001C {
+ <HeaderFiles>
+ Pins/GpioPinsVer2Lp.h
+ Library/GpioConfig.h
+ <Packages>
+ MdePkg/MdePkg.dec
+ AlderlakeSiliconPkg/SiPkg.dec
+ AlderlakeOpenBoardPkg/OpenBoardPkg.dec
+}
+
+# PCIE CLOCKS USAGE
+ gBoardModuleTokenSpaceGuid.VpdPcdPcieClkUsageMap|{0}|PCIE_CLOCKS_USAGE|0x50000022 {
+ <HeaderFiles>
+ PlatformBoardConfig.h
+ <Packages>
+ MdePkg/MdePkg.dec
+ AlderlakeOpenBoardPkg/OpenBoardPkg.dec
+}
+
+# USB2 OC MAPPING
+ gBoardModuleTokenSpaceGuid.VpdPcdUSB2OCMap|{0}|USB_OC_MAP_TABLE|0x50000023 {
+ <HeaderFiles>
+ PlatformBoardConfig.h
+ <Packages>
+ MdePkg/MdePkg.dec
+ AlderlakeSiliconPkg/SiPkg.dec
+ AlderlakeOpenBoardPkg/OpenBoardPkg.dec
+}
+
+# USB3 OC MAPPING
+ gBoardModuleTokenSpaceGuid.VpdPcdUSB3OCMap|{0}|USB_OC_MAP_TABLE|0x50000024 {
+ <HeaderFiles>
+ PlatformBoardConfig.h
+ <Packages>
+ MdePkg/MdePkg.dec
+ AlderlakeSiliconPkg/SiPkg.dec
+ AlderlakeOpenBoardPkg/OpenBoardPkg.dec
+}
+
+
+#SBC SPD DATA
+ gBoardModuleTokenSpaceGuid.VpdPcdMrcSpdData|{0}|SPD_DATA|0x50000025 {
+ <HeaderFiles>
+ PlatformBoardConfig.h
+ <Packages>
+ MdePkg/MdePkg.dec
+ AlderlakeOpenBoardPkg/OpenBoardPkg.dec
+}
+
+# SBC MRC DQS MAPPING
+ gBoardModuleTokenSpaceGuid.VpdPcdMrcDqsMapCpu2Dram|{0}|MRC_DQS|0x50000026 {
+ <HeaderFiles>
+ PlatformBoardConfig.h
+ <Packages>
+ MdePkg/MdePkg.dec
+ AlderlakeSiliconPkg/SiPkg.dec
+ AlderlakeOpenBoardPkg/OpenBoardPkg.dec
+}
+
+# SBC MRC DQ MAPPING
+ gBoardModuleTokenSpaceGuid.VpdPcdMrcDqMapCpu2Dram|{0}|MRC_DQ|0x50000027 {
+ <HeaderFiles>
+ PlatformBoardConfig.h
+ <Packages>
+ MdePkg/MdePkg.dec
+ AlderlakeSiliconPkg/SiPkg.dec
+ AlderlakeOpenBoardPkg/OpenBoardPkg.dec
+}
+
+# CPU USB3 OC MAPPING
+ gBoardModuleTokenSpaceGuid.VpdPcdCpuUsb3OcMap|{0}|USB_OC_MAP_TABLE|0x50000028 {
+ <HeaderFiles>
+ PlatformBoardConfig.h
+ <Packages>
+ MdePkg/MdePkg.dec
+ AlderlakeSiliconPkg/SiPkg.dec
+ AlderlakeOpenBoardPkg/OpenBoardPkg.dec
+}
+
+# ACPI data
+ gBoardModuleTokenSpaceGuid.PcdBoardAcpiData|{0}|VOID*|0x5000001A
+
+# Early Pre-Mem GPIO table
+ gBoardModuleTokenSpaceGuid.PcdBoardGpioTableEarlyPreMem|{0}|GPIO_INIT_CONFIG_ARRAY|0x5000001B {
+ <HeaderFiles>
+ Pins/GpioPinsVer2Lp.h
+ Library/GpioLib.h
+ PlatformGpioConfig.h
+ <Packages>
+ MdePkg/MdePkg.dec
+ AlderlakeSiliconPkg/SiPkg.dec
+ AlderLakeOpenBoardPkg/OpenBoardPkg.dec
+}
+
+ # Onboard MR 1 RTD3 (for ADL S8 only, used when dTBT is enabled)
+ gBoardModuleTokenSpaceGuid.PcdOnBoardMr1PowerEnableGpioNo|0|UINT32|0x00000149
+ gBoardModuleTokenSpaceGuid.PcdOnBoardMr1PowerEnableGpioPolarity|0|BOOLEAN|0x00000150
+ gBoardModuleTokenSpaceGuid.PcdOnBoardMr1WakeGpioPin|0|UINT32|0x00000153
+ gBoardModuleTokenSpaceGuid.PcdOnBoardMr1RootPort|0|UINT8|0x00000154
+
+ # Onboard MR 2 RTD3 (Used when dTBT is enabled)
+ gBoardModuleTokenSpaceGuid.PcdOnBoardMr2PowerEnableGpioNo|0|UINT32|0x00000155
+ gBoardModuleTokenSpaceGuid.PcdOnBoardMr2PowerEnableGpioPolarity|0|BOOLEAN|0x00000156
+ gBoardModuleTokenSpaceGuid.PcdOnBoardMr2WakeGpioPin|0|UINT32|0x00000159
+ gBoardModuleTokenSpaceGuid.PcdOnBoardMr2RootPort|0|UINT8|0x00000160
+
+[PcdsDynamic, PcdsDynamicEx]
+
+[PcdsPatchableInModule]
+
+[PcdsFeatureFlag]
+ gBoardModuleTokenSpaceGuid.PcdUefiShellEnable |FALSE|BOOLEAN|0xF0000B53
+ gBoardModuleTokenSpaceGuid.PcdIntelGopEnable |FALSE|BOOLEAN|0xF0000B54
+
+[PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx]
+ ## This is the GUID of the FFS which contains the Graphics Video BIOS Table (VBT)
+ # The VBT content is stored as a RAW section which is consumed by GOP PEI/UEFI driver.
+ # This MIPI GUID can be updated by patching or runtime if platform support multiple VBT configurations.
+ # @Prompt GUID of the FFS which contains the Graphics Video BIOS Table (VBT)
+ # { 0x8958d092, 0x7b26, 0x4e47, 0xbb, 0x98, 0x16, 0xae, 0x2d, 0xc3, 0x15, 0xa2 }
+ gBoardModuleTokenSpaceGuid.PcdVbtMipiGuid|{ 0x92, 0xd0, 0x58, 0x89, 0x26, 0x7b, 0x47, 0x4e, 0xbb, 0x98, 0x16, 0xae, 0x2d, 0xc3, 0x15, 0xa2 }|VOID*|0x00000001
+
+ ## PCDs for the MMIO base address range (default 1M) for ATA AHCI host controller used in PEI phase
+ gPlatformModuleTokenSpaceGuid.PcdAhciPeiMmioBase|0xD1000000|UINT32|0x0000C10E
+ gPlatformModuleTokenSpaceGuid.PcdAhciPeiMmioLimit|0xD10FFFFF|UINT32|0x0000C10F
+
+ # PCDs for the MMIO base address range (default 4M) for NVM Express host controller used in PEI phase
+ # @Prompt Temporary mmio base address of NVME host controller.
+ gPlatformModuleTokenSpaceGuid.PcdNvmeHcPeiMmioBase |0xFFFFFFFF|UINT32|0x0000C110
+ # @Prompt Temporary mmio address limitation of NVME host controller.
+ gPlatformModuleTokenSpaceGuid.PcdNvmeHcPeiMmioLimit|0xFFFFFFFF|UINT32|0x0000C111
+
+ # PCDs for the MMIO base address range (default 4M) for UFS host controller used in PEI phase
+ # @Prompt Temporary mmio base address of UFS host controller.
+ gPlatformModuleTokenSpaceGuid.PcdUfsPeiHcMmioBase |0xFFFFFFFF|UINT32|0x0000C112
+
+ #
+ # This PCD use for UFS BlockIo maximum read size from deivce in PEI phase.
+ # Value need to take the Dma Buffer Size into account.
+ # Must be a multiple of the intrinsic block size of the device.
+ #
+ gPlatformModuleTokenSpaceGuid.PcdUfsReadPeiMaxTransferSize|0x00001000|UINT32|0x0000C113
+
+
+ ## This PCD defines initial setting of TCG2 Persistent Firmware Management Flags
+ # PCD can be configured for different settings in different scenarios
+ # Default setting is TCG2_BIOS_TPM_MANAGEMENT_FLAG_DEFAULT | TCG2_BIOS_STORAGE_MANAGEMENT_FLAG_DEFAULT
+ # @Prompt Initial setting of TCG2 Persistent Firmware Management Flags
+ # Enabled PPI for PPRequiredForTurnOff, PPRequiredForChangeEPS, PPRequiredForChangePCRs, PPRequiredForEnable_BlockSIDFunc, PPRequiredForDisable_BlockSIDFunc
+ gEfiSecurityPkgTokenSpaceGuid.PcdTcg2PhysicalPresenceFlags|0x300E0|UINT32|0x0001001B
+
--
2.36.1.windows.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 2/6] AlderlakeOpenBoardPkg: Add modules
[not found] <cover.1686770061.git.saloni.kasbekar@intel.com>
2023-06-14 19:17 ` [PATCH 1/6] AlderlakeOpenBoardPkg: Add package and headers Saloni Kasbekar
@ 2023-06-14 19:17 ` Saloni Kasbekar
2023-06-14 19:17 ` [PATCH 3/6] AlderlakeOpenBoardPkg/AlderlakePRvp: Add library instances Saloni Kasbekar
` (3 subsequent siblings)
5 siblings, 0 replies; 6+ messages in thread
From: Saloni Kasbekar @ 2023-06-14 19:17 UTC (permalink / raw)
To: devel
Cc: Saloni Kasbekar, Sai Chaganty, Nate DeSimone, Isaac Oram,
Rosen Chuang
Adds the following modules:
-BiosInfo
-OpenBoardPlatformInit
-SBCVpdStructurePcd
-SmmMultiBoardAcpiSupportLib
Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Isaac Oram <isaac.w.oram@intel.com>
Cc: Rosen Chuang <rosen.chuang@intel.com>
Signed-off-by: Saloni Kasbekar <saloni.kasbekar@intel.com>
---
.../AlderlakeOpenBoardPkg/BiosInfo/BiosInfo.c | 196 +++++++
.../BiosInfo/BiosInfo.inf | 91 ++++
.../OpenBoardPlatformInitPostMem.c | 499 ++++++++++++++++++
.../OpenBoardPlatformInitPostMem.inf | 84 +++
.../OpenBoardPlatformInitPreMem.c | 192 +++++++
.../OpenBoardPlatformInitPreMem.inf | 59 +++
.../OpenBoardPlatformInitSmm.c | 250 +++++++++
.../OpenBoardPlatformInitSmm.h | 50 ++
.../OpenBoardPlatformInitSmm.inf | 60 +++
.../SBCVpdStructurePcd/AllStructPCD.dsc | 19 +
.../GpioTableAdlPPostMem.dsc | 40 ++
.../GpioTableAdlPPreMem.dsc | 29 +
.../MrcDqDqsSPD/AdlPSpdMap.dsc | 138 +++++
.../PcieClocks/AdlPPcieClocks.dsc | 32 ++
.../SmmAcpiEnableLib.c | 51 ++
.../SmmMultiBoardAcpiSupportLib.c | 89 ++++
.../SmmMultiBoardAcpiSupportLib.inf | 40 ++
.../SmmSiliconAcpiEnableLib.c | 157 ++++++
18 files changed, 2076 insertions(+)
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/BiosInfo/BiosInfo.c
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/BiosInfo/BiosInfo.inf
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/OpenBoardPlatformInit/OpenBoardPlatformInitPei/OpenBoardPlatformInitPostMem.c
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/OpenBoardPlatformInit/OpenBoardPlatformInitPei/OpenBoardPlatformInitPostMem.inf
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/OpenBoardPlatformInit/OpenBoardPlatformInitPei/OpenBoardPlatformInitPreMem.c
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/OpenBoardPlatformInit/OpenBoardPlatformInitPei/OpenBoardPlatformInitPreMem.inf
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/OpenBoardPlatformInit/OpenBoardPlatformInitSmm/OpenBoardPlatformInitSmm.c
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/OpenBoardPlatformInit/OpenBoardPlatformInitSmm/OpenBoardPlatformInitSmm.h
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/OpenBoardPlatformInit/OpenBoardPlatformInitSmm/OpenBoardPlatformInitSmm.inf
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/SBCVpdStructurePcd/AllStructPCD.dsc
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/SBCVpdStructurePcd/GpioTableAdlPPostMem.dsc
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/SBCVpdStructurePcd/GpioTableAdlPPreMem.dsc
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/SBCVpdStructurePcd/MrcDqDqsSPD/AdlPSpdMap.dsc
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/SBCVpdStructurePcd/PcieClocks/AdlPPcieClocks.dsc
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/SmmMultiBoardAcpiSupportLib/SmmAcpiEnableLib.c
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/SmmMultiBoardAcpiSupportLib/SmmMultiBoardAcpiSupportLib.c
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/SmmMultiBoardAcpiSupportLib/SmmMultiBoardAcpiSupportLib.inf
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/SmmMultiBoardAcpiSupportLib/SmmSiliconAcpiEnableLib.c
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/BiosInfo/BiosInfo.c b/Platform/Intel/AlderlakeOpenBoardPkg/BiosInfo/BiosInfo.c
new file mode 100644
index 0000000000..64462900de
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/BiosInfo/BiosInfo.c
@@ -0,0 +1,196 @@
+/** @file
+ PEIM to provide BiosInfo structure listing up all firmware volume's base addresses, sizes,
+ attributes, and information associated to the firmware volume.
+ Primarily the structure is used on FIT table creation and Bpm.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <PiPei.h>
+#include <Guid/BiosInfo.h>
+#include <Library/PeiServicesLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/HobLib.h>
+#include <Library/PcdLib.h>
+#include <IndustryStandard/FirmwareInterfaceTable.h>
+#include <Ppi/FirmwareVolumeInfoMeasurementExcluded.h>
+#include <Library/MemoryAllocationLib.h>
+
+#define BASE_FV_SIZE 10
+
+#define FSP_WRAPPER_FV_SIZE 3
+
+#define TSN_MAC_ADDRESS_FV_SIZE 0
+
+#define BIOS_INFO_STRUCT_SIZE (BASE_FV_SIZE + FSP_WRAPPER_FV_SIZE + TSN_MAC_ADDRESS_FV_SIZE)
+
+
+/*
+ BIOS_INFO structure is the base of the firmware volume layout for Intel platform BIOS implementation
+ so security checker module can run based on the structure and throw warnings, error or deadloop
+ when any unexpected firmware volumes are detected.
+
+ BIOS_INFO is recommended to support full entries of firmware volumes present in a flash
+ with right type, attribute, version, flash map base address and size,
+ all associated information which is defined by BIOS_INFO_STRUCT structure.
+ - IBB firmware volumes, which are expected to be measured or/and verified
+ by hardware base security solution to meet SecureBoot chain of trust
+ (Intel BootGuard for example), have attribute 0x0.
+ - Post IBB firmware volumes, which are expected to be measured or/and verified
+ by BIOS (TCG code for measurement, RSA2048SHA256Sign algorithm for verification for example),
+ have attribute BIOS_INFO_STRUCT_ATTRIBUTE_BIOS_POST_IBB.
+ - Else, follows Firmware Interface Table specification.
+*/
+#pragma pack (1)
+typedef struct {
+ BIOS_INFO_HEADER Header;
+ BIOS_INFO_STRUCT Entry[BIOS_INFO_STRUCT_SIZE];
+} BIOS_INFO;
+#pragma pack ()
+
+GLOBAL_REMOVE_IF_UNREFERENCED BIOS_INFO mBiosInfo = {
+ {
+ BIOS_INFO_SIGNATURE,
+ BIOS_INFO_STRUCT_SIZE,
+ 0,
+ },
+ {
+ {
+ FIT_TYPE_07_BIOS_STARTUP_MODULE,
+ BIOS_INFO_STRUCT_ATTRIBUTE_GENERAL_EXCLUDE_FROM_FIT,
+ 0x0100,
+ FixedPcdGet32 (PcdFlashNvStorageVariableSize) + FixedPcdGet32 (PcdFlashNvStorageFtwWorkingSize) + FixedPcdGet32 (PcdFlashNvStorageFtwSpareSize),
+ FixedPcdGet32 (PcdFlashNvStorageVariableBase)
+ },
+ {
+ FIT_TYPE_07_BIOS_STARTUP_MODULE,
+ BIOS_INFO_STRUCT_ATTRIBUTE_BIOS_POST_IBB,
+ 0x0100,
+ FixedPcdGet32 (PcdFlashFvAdvancedSize),
+ FixedPcdGet32 (PcdFlashFvAdvancedBase)
+ },
+ {
+ FIT_TYPE_07_BIOS_STARTUP_MODULE,
+ BIOS_INFO_STRUCT_ATTRIBUTE_BIOS_POST_IBB,
+ 0x0100,
+ FixedPcdGet32 (PcdFlashFvOptionalSize),
+ FixedPcdGet32 (PcdFlashFvOptionalBase)
+ },
+ {
+ FIT_TYPE_07_BIOS_STARTUP_MODULE,
+ BIOS_INFO_STRUCT_ATTRIBUTE_BIOS_POST_IBB,
+ 0x0100,
+ FixedPcdGet32 (PcdFlashFvSecuritySize),
+ FixedPcdGet32 (PcdFlashFvSecurityBase)
+ },
+ {
+ FIT_TYPE_07_BIOS_STARTUP_MODULE,
+ BIOS_INFO_STRUCT_ATTRIBUTE_BIOS_POST_IBB,
+ 0x0100,
+ FixedPcdGet32 (PcdFlashFvOsBootSize),
+ FixedPcdGet32 (PcdFlashFvOsBootBase)
+ },
+ {
+ FIT_TYPE_07_BIOS_STARTUP_MODULE,
+ BIOS_INFO_STRUCT_ATTRIBUTE_BIOS_POST_IBB,
+ 0x0100,
+ FixedPcdGet32 (PcdFlashFvUefiBootSize),
+ FixedPcdGet32 (PcdFlashFvUefiBootBase)
+ },
+ {
+ FIT_TYPE_07_BIOS_STARTUP_MODULE,
+ BIOS_INFO_STRUCT_ATTRIBUTE_BIOS_POST_IBB,
+ 0x0100,
+ FixedPcdGet32 (PcdFlashFvPostMemorySize),
+ FixedPcdGet32 (PcdFlashFvPostMemoryBase)
+ },
+ {
+ FIT_TYPE_07_BIOS_STARTUP_MODULE,
+ BIOS_INFO_STRUCT_ATTRIBUTE_GENERAL_EXCLUDE_FROM_FIT,
+ 0x0100,
+ FixedPcdGet32 (PcdFlashFvFirmwareBinariesSize),
+ FixedPcdGet32 (PcdFlashFvFirmwareBinariesBase)
+ },
+ {
+ FIT_TYPE_07_BIOS_STARTUP_MODULE,
+ BIOS_INFO_STRUCT_ATTRIBUTE_BIOS_POST_IBB,
+ 0x0100,
+ FixedPcdGet32 (PcdFlashFvFspSSize),
+ FixedPcdGet32 (PcdFlashFvFspSBase)
+ },
+ {
+ FIT_TYPE_07_BIOS_STARTUP_MODULE,
+ 0x00, // IBB FV
+ 0x0100,
+ FixedPcdGet32 (PcdFlashFvFspMSize),
+ FixedPcdGet32 (PcdFlashFvFspMBase)
+ },
+ {
+ FIT_TYPE_07_BIOS_STARTUP_MODULE,
+ 0x00, // IBB FV
+ 0x0100,
+ FixedPcdGet32 (PcdFlashFvFspTSize),
+ FixedPcdGet32 (PcdFlashFvFspTBase)
+ },
+ {
+ FIT_TYPE_07_BIOS_STARTUP_MODULE,
+ 0x00, // IBB FV
+ 0x0100,
+ FixedPcdGet32 (PcdFlashFvPreMemorySize),
+ FixedPcdGet32 (PcdFlashFvPreMemoryBase)
+ },
+ {
+ FIT_TYPE_01_MICROCODE,
+ BIOS_INFO_STRUCT_ATTRIBUTE_MICROCODE_WHOLE_REGION,
+ 0x0100,
+ FixedPcdGet32 (PcdFlashMicrocodeFvSize),
+ FixedPcdGet32 (PcdFlashMicrocodeFvBase)
+ },
+ }
+};
+
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_PEI_PPI_DESCRIPTOR mBiosInfoPpiList = {
+ EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,
+ &gBiosInfoGuid,
+ &mBiosInfo
+};
+
+/**
+ Installs BiosInfo Ppi.
+
+ @param FileHandle Handle of the file being invoked.
+ @param PeiServices Describes the list of possible PEI Services.
+
+ @retval EFI_SUCCESS Install the BiosInfo Ppi successfully.
+
+**/
+EFI_STATUS
+EFIAPI
+BiosInfoEntryPoint (
+ IN EFI_PEI_FILE_HANDLE FileHandle,
+ IN CONST EFI_PEI_SERVICES **PeiServices
+ )
+{
+ EFI_STATUS Status;
+ VOID *HobData;
+
+ //
+ // Install PPI, so that other PEI module can add dependency.
+ //
+ Status = PeiServicesInstallPpi (&mBiosInfoPpiList);
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Build hob, so that DXE module can also get the data.
+ //
+ HobData = BuildGuidHob (&gBiosInfoGuid, sizeof (mBiosInfo));
+ ASSERT (HobData != NULL);
+ if (HobData == NULL) {
+ return EFI_OUT_OF_RESOURCES;
+ }
+ CopyMem (HobData, &mBiosInfo, sizeof (mBiosInfo));
+ return EFI_SUCCESS;
+}
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/BiosInfo/BiosInfo.inf b/Platform/Intel/AlderlakeOpenBoardPkg/BiosInfo/BiosInfo.inf
new file mode 100644
index 0000000000..f020cb6432
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/BiosInfo/BiosInfo.inf
@@ -0,0 +1,91 @@
+### @file
+# Module Information description file for BIOS Info PEIM.
+# The module provides BiosInfo structure listing up all firmware volume's base addresses,
+# sizes, attributes, those information associated to each firmware volume.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+###
+
+[Defines]
+ INF_VERSION = 0x00010017
+ BASE_NAME = BiosInfo
+ FILE_GUID = 4A4CA1C6-871C-45BB-8801-6910A7AA5807
+ VERSION_STRING = 1.0
+ MODULE_TYPE = PEIM
+ ENTRY_POINT = BiosInfoEntryPoint
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES IA32 X64
+#
+
+[LibraryClasses]
+ PeimEntryPoint
+ PeiServicesLib
+ PeiServicesTablePointerLib
+ HobLib
+ BaseMemoryLib
+ MemoryAllocationLib
+ DebugLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ AlderlakeSiliconPkg/SiPkg.dec
+ IntelSiliconPkg/IntelSiliconPkg.dec
+ MinPlatformPkg/MinPlatformPkg.dec
+ AlderlakeOpenBoardPkg/OpenBoardPkg.dec
+ SecurityPkg/SecurityPkg.dec
+ BoardModulePkg/BoardModulePkg.dec
+
+[Pcd]
+ gIntelSiliconPkgTokenSpaceGuid.PcdBiosAreaBaseAddress ## CONSUMES
+ gIntelSiliconPkgTokenSpaceGuid.PcdBiosSize ## CONSUMES
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase ## CONSUMES
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize ## CONSUMES
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase ## CONSUMES
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize ## CONSUMES
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase ## CONSUMES
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdFlashFvFirmwareBinariesBase ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdFlashFvFirmwareBinariesSize ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedBase ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdFlashFvOptionalBase ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdFlashFvOptionalSize ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityBase ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootBase ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootBase ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryBase ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize ## CONSUMES
+ gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase ## CONSUMES
+ gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSBase ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMBase ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTBase ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSize ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryBase ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemorySize ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdFlashFvExtendedPostMemorySize ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdFlashFvExtendedPostMemoryBase ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdFlashFvExtendedAdvancedSize ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdFlashFvExtendedAdvancedBase ## CONSUMES
+
+[Sources]
+ BiosInfo.c
+
+[Ppis]
+ gEfiPeiFirmwareVolumeInfoMeasurementExcludedPpiGuid ## PRODUCES
+
+[Guids]
+ gBiosInfoGuid ## PRODUCES
+
+[Depex]
+ gEfiPeiMasterBootModePpiGuid
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/OpenBoardPlatformInit/OpenBoardPlatformInitPei/OpenBoardPlatformInitPostMem.c b/Platform/Intel/AlderlakeOpenBoardPkg/OpenBoardPlatformInit/OpenBoardPlatformInitPei/OpenBoardPlatformInitPostMem.c
new file mode 100644
index 0000000000..a1bbb5c179
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/OpenBoardPlatformInit/OpenBoardPlatformInitPei/OpenBoardPlatformInitPostMem.c
@@ -0,0 +1,499 @@
+/** @file
+ Source code file for OpenBoard Platform Init PEI module
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Register/Msr.h>
+#include <CpuRegs.h>
+#include <Library/IoLib.h>
+#include <Library/HobLib.h>
+#include <Library/DebugLib.h>
+#include <Library/PchInfoLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/PeiServicesLib.h>
+#include <Ppi/EndOfPeiPhase.h>
+#include <Library/MtrrLib.h>
+#include <Ppi/ReadOnlyVariable2.h>
+#include <Guid/SmramMemoryReserve.h>
+#include <Library/ConfigBlockLib.h>
+#include <Ppi/SiPolicy.h>
+#include <PchPolicyCommon.h>
+#include <Library/SiPolicyLib.h>
+#include <Guid/FirmwareFileSystem2.h>
+#include <Protocol/FirmwareVolumeBlock.h>
+#include <Library/PostCodeLib.h>
+#include <PlatformPostCode.h>
+#include <Ppi/Spi.h>
+#include <Library/MtrrLib.h>
+#include <Library/PciSegmentLib.h>
+#include <Register/PchRegs.h>
+#include <PlatformBoardId.h>
+#include <Core/Pei/PeiMain.h>
+#include <Library/PchPciBdfLib.h>
+#include <Ppi/GraphicsPlatformPolicyPpi.h>
+#include <Library/PeiGetFvInfoLib.h>
+
+/**
+ Initializes the valid bits mask and valid address mask for MTRRs.
+
+ This function initializes the valid bits mask and valid address mask for MTRRs.
+
+ @param[out] MtrrValidBitsMask The mask for the valid bit of the MTRR
+ @param[out] MtrrValidAddressMask The valid address mask for the MTRR
+
+**/
+VOID
+MtrrLibInitializeMtrrMask (
+ OUT UINT64 *MtrrValidBitsMask,
+ OUT UINT64 *MtrrValidAddressMask
+ );
+
+/**
+ Convert variable MTRRs to a RAW MTRR_MEMORY_RANGE array.
+ One MTRR_MEMORY_RANGE element is created for each MTRR setting.
+ The routine doesn't remove the overlap or combine the near-by region.
+
+ @param[in] VariableSettings The variable MTRR values to shadow
+ @param[in] VariableMtrrCount The number of variable MTRRs
+ @param[in] MtrrValidBitsMask The mask for the valid bit of the MTRR
+ @param[in] MtrrValidAddressMask The valid address mask for MTRR
+ @param[out] VariableMtrr The array to shadow variable MTRRs content
+
+ @return Number of MTRRs which has been used.
+
+**/
+UINT32
+MtrrLibGetRawVariableRanges (
+ IN MTRR_VARIABLE_SETTINGS *VariableSettings,
+ IN UINTN VariableMtrrCount,
+ IN UINT64 MtrrValidBitsMask,
+ IN UINT64 MtrrValidAddressMask,
+ OUT MTRR_MEMORY_RANGE *VariableMtrr
+ );
+
+/**
+ Apply the variable MTRR settings to memory range array.
+
+ @param[in] VariableMtrr The variable MTRR array.
+ @param[in] VariableMtrrCount The count of variable MTRRs.
+ @param[in, out] Ranges Return the memory range array with new MTRR settings applied.
+ @param[in] RangeCapacity The capacity of memory range array.
+ @param[in, out] RangeCount Return the count of memory range.
+
+ @retval RETURN_SUCCESS The memory range array is returned successfully.
+ @retval RETURN_OUT_OF_RESOURCES The count of memory ranges exceeds capacity.
+**/
+RETURN_STATUS
+MtrrLibApplyVariableMtrrs (
+ IN CONST MTRR_MEMORY_RANGE *VariableMtrr,
+ IN UINT32 VariableMtrrCount,
+ IN OUT MTRR_MEMORY_RANGE *Ranges,
+ IN UINTN RangeCapacity,
+ IN OUT UINTN *RangeCount
+ );
+
+/**
+ This function attempts to set the attributes into MTRR setting buffer.
+
+ @param[in, out] MtrrSetting - A buffer holding all MTRRs content.
+ @param[in] Ranges - Array holding memory type settings.
+ @param[in] RangeCount - Memory range count in the array.
+
+ @retval Count of used variable Mtrrs
+**/
+EFI_STATUS
+EFIAPI
+EOPSetMemoryAttributesInMtrrSettings (
+ IN OUT MTRR_SETTINGS *MtrrSetting,
+ IN MTRR_MEMORY_RANGE *Ranges,
+ IN UINTN RangeCount
+ )
+{
+ EFI_STATUS Status;
+ UINTN Index;
+ UINTN HighIndex;
+ UINT64 TopHighMemory;
+
+ Status = EFI_NOT_FOUND;
+
+ for (Index = 0, HighIndex = 0xFF; Index < RangeCount; Index++) {
+ //
+ // Set Mtrr variables from 1M.
+ //
+ if (Ranges[Index].BaseAddress < 0x100000) {
+ Ranges[Index].Length -= 0x100000;
+ Ranges[Index].BaseAddress = 0x100000;
+ }
+ if ((Ranges[Index].BaseAddress >= SIZE_4GB) && (Ranges[Index].Type == CacheWriteBack)) {
+ HighIndex = Index; // Set above 4G attributes at the latest step.
+ } else {
+ Status = MtrrSetMemoryAttributeInMtrrSettings (
+ MtrrSetting,
+ Ranges[Index].BaseAddress,
+ Ranges[Index].Length,
+ Ranges[Index].Type
+ );
+ ASSERT_EFI_ERROR (Status);
+ }
+ }
+ if (HighIndex != 0xFF) {
+ TopHighMemory = Ranges[HighIndex].BaseAddress + Ranges[HighIndex].Length;
+ //
+ // Try to cover memory as mmuch as we can.
+ // In later phase boot loader code can re-configure MTRR to exclude flash region and get back above 4GB coverage.
+ //
+ do {
+ Status = MtrrSetMemoryAttributeInMtrrSettings (
+ MtrrSetting,
+ SIZE_4GB,
+ TopHighMemory - SIZE_4GB,
+ CacheWriteBack
+ );
+ if (TopHighMemory > SIZE_4GB) {
+ TopHighMemory = RShiftU64 (TopHighMemory, 1);
+ }
+ } while ((EFI_SUCCESS != Status) && (TopHighMemory > SIZE_4GB));
+ }
+
+ return Status;
+}
+
+
+EFI_STATUS
+EFIAPI
+OpenBoardPlatformInitEndOfPei (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
+ IN VOID *Ppi
+ );
+
+static EFI_PEI_NOTIFY_DESCRIPTOR mEndOfPeiNotifyList = {
+ (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
+ &gEfiEndOfPeiSignalPpiGuid,
+ (EFI_PEIM_NOTIFY_ENTRY_POINT) OpenBoardPlatformInitEndOfPei
+};
+
+EFI_STATUS
+EFIAPI
+GetPeiPlatformLidStatus (
+ OUT LID_STATUS *CurrentLidStatus
+ );
+
+EFI_STATUS
+EFIAPI
+GetVbtData (
+ OUT EFI_PHYSICAL_ADDRESS *VbtAddress,
+ OUT UINT32 *VbtSize
+ );
+
+PEI_GRAPHICS_PLATFORM_POLICY_PPI PeiGraphicsPlatform = {
+ PEI_GRAPHICS_PLATFORM_POLICY_REVISION,
+ GetPeiPlatformLidStatus,
+ GetVbtData
+};
+
+EFI_PEI_PPI_DESCRIPTOR mPeiGraphicsPlatformPpi = {
+ (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
+ &gPeiGraphicsPlatformPpiGuid,
+ &PeiGraphicsPlatform
+};
+
+EFI_STATUS
+EFIAPI
+GetVbtData (
+ OUT EFI_PHYSICAL_ADDRESS *VbtAddress,
+ OUT UINT32 *VbtSize
+ )
+{
+ EFI_GUID FileGuid;
+ EFI_GUID BmpImageGuid;
+ VOID *Buffer;
+ UINT32 Size;
+
+ Size = 0;
+ Buffer = NULL;
+
+
+ DEBUG((DEBUG_INFO, "GetVbtData Entry\n"));
+
+ CopyMem (&BmpImageGuid, PcdGetPtr(PcdIntelGraphicsVbtFileGuid), sizeof(BmpImageGuid));
+
+ CopyMem(&FileGuid, &BmpImageGuid, sizeof(FileGuid));
+ PeiGetSectionFromFv(FileGuid, &Buffer, &Size);
+ if (Buffer == NULL) {
+ DEBUG((DEBUG_ERROR, "Could not locate VBT\n"));
+ } else {
+ DEBUG ((DEBUG_INFO, "GetVbtData Buffer is 0x%x\n", Buffer));
+ DEBUG ((DEBUG_INFO, "GetVbtData Size is 0x%x\n", Size));
+ *VbtAddress = (EFI_PHYSICAL_ADDRESS)(UINTN)Buffer;
+ *VbtSize = Size;
+ }
+ DEBUG((DEBUG_INFO, "GetVbtData exit\n"));
+
+ return EFI_SUCCESS;
+}
+
+
+/**
+ This function will return Lid Status in PEI phase.
+
+ @param[out] CurrentLidStatus
+
+ @retval EFI_SUCCESS
+ @retval EFI_UNSUPPORTED
+**/
+
+EFI_STATUS
+EFIAPI
+GetPeiPlatformLidStatus (
+ OUT LID_STATUS *CurrentLidStatus
+ )
+{
+ DEBUG ((DEBUG_INFO, "LidStatus Entry\n"));
+ //
+ // If the platform does not support a lid, the function must return EFI_UNSUPPORTED
+ //
+ if (PcdGet8 (PcdPlatformType) == TypeTrad && PcdGet8 (PcdPlatformFlavor) == FlavorDesktop) {
+ DEBUG ((DEBUG_INFO, "Returning Lid status as unsupported to GOP for DT/AIO board\n"));
+ return EFI_UNSUPPORTED;
+ }
+
+ DEBUG ((DEBUG_INFO, "LidStatus UnSupported\n"));
+ return EFI_UNSUPPORTED;
+}
+
+/**
+ Update MTRR setting in EndOfPei phase.
+
+ @retval EFI_SUCCESS The function completes successfully.
+ @retval Others Some error occurs.
+**/
+EFI_STATUS
+EFIAPI
+SetCacheMtrrAfterEndOfPei (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+ EFI_PEI_HOB_POINTERS Hob;
+ UINTN Index;
+ UINT64 SmramSize;
+ UINT64 SmramBase;
+ EFI_SMRAM_HOB_DESCRIPTOR_BLOCK *SmramHobDescriptorBlock;
+ MTRR_SETTINGS MtrrSetting;
+ UINTN RangeCount;
+ UINT32 VariableMtrrCount;
+ UINT64 MtrrValidBitsMask;
+ UINT64 MtrrValidAddressMask;
+ MTRR_MEMORY_RANGE RawVariableRanges[MTRR_NUMBER_OF_VARIABLE_MTRR];
+ MTRR_MEMORY_RANGE Ranges[MTRR_NUMBER_OF_VARIABLE_MTRR];
+ MTRR_SETTINGS UCMtrrSetting;
+ //
+ // PI SMM IPL can't set SMRAM to WB because at that time CPU ARCH protocol is not available.
+ // Set cacheability of SMRAM to WB here to improve SMRAM initialization performance.
+ //
+ SmramSize = 0;
+ SmramBase = 0;
+ Status = PeiServicesGetHobList ((VOID **) &Hob.Raw);
+ while (!END_OF_HOB_LIST (Hob)) {
+ if (Hob.Header->HobType == EFI_HOB_TYPE_GUID_EXTENSION) {
+ if (CompareGuid (&Hob.Guid->Name, &gEfiSmmSmramMemoryGuid)) {
+ SmramHobDescriptorBlock = (EFI_SMRAM_HOB_DESCRIPTOR_BLOCK *) (Hob.Guid + 1);
+ for (Index = 0; Index < SmramHobDescriptorBlock->NumberOfSmmReservedRegions; Index++) {
+ if (SmramHobDescriptorBlock->Descriptor[Index].PhysicalStart > 0x100000) {
+ SmramSize += SmramHobDescriptorBlock->Descriptor[Index].PhysicalSize;
+ if (SmramBase == 0 || SmramBase > SmramHobDescriptorBlock->Descriptor[Index].CpuStart) {
+ SmramBase = SmramHobDescriptorBlock->Descriptor[Index].CpuStart;
+ }
+ }
+ }
+ break;
+ }
+ }
+ Hob.Raw = GET_NEXT_HOB (Hob);
+ }
+
+ MtrrGetAllMtrrs (&MtrrSetting);
+ VariableMtrrCount = GetVariableMtrrCount ();
+ MtrrLibInitializeMtrrMask (&MtrrValidBitsMask, &MtrrValidAddressMask);
+
+ Ranges[0].BaseAddress = 0;
+ Ranges[0].Length = MtrrValidBitsMask + 1;
+ Ranges[0].Type = (MTRR_MEMORY_CACHE_TYPE)(MtrrSetting.MtrrDefType & 0x07); //[Bits 2:0] Default Memory Type.
+ RangeCount = 1;
+
+ MtrrLibGetRawVariableRanges (
+ &MtrrSetting.Variables, VariableMtrrCount,
+ MtrrValidBitsMask, MtrrValidAddressMask, RawVariableRanges
+ );
+
+ MtrrLibApplyVariableMtrrs (
+ RawVariableRanges, VariableMtrrCount,
+ Ranges, ARRAY_SIZE (Ranges), &RangeCount
+ );
+
+ //
+ // Set SMRAM as CacheWriteBack for performance.
+ //
+ Ranges[RangeCount].BaseAddress = SmramBase;
+ Ranges[RangeCount].Length = SmramSize;
+ Ranges[RangeCount].Type = CacheWriteBack;
+ RangeCount++;
+
+ ZeroMem (&UCMtrrSetting, sizeof (MTRR_SETTINGS));
+ UCMtrrSetting.MtrrDefType = MtrrSetting.MtrrDefType;
+ Status = EOPSetMemoryAttributesInMtrrSettings (&UCMtrrSetting, Ranges, RangeCount);
+
+ CopyMem (&MtrrSetting.Variables, &UCMtrrSetting.Variables, sizeof (MTRR_VARIABLE_SETTINGS));
+ MtrrSetting.MtrrDefType = UCMtrrSetting.MtrrDefType;
+ return Status;
+}
+
+/**
+ Configure PciHostBridge related PCDs
+**/
+VOID
+ConfigurePciHostBridgePcds (
+ VOID
+ )
+{
+ EFI_PHYSICAL_ADDRESS PciBaseAddress;
+ UINT32 Tolud;
+ UINT64 Length;
+ UINT64 McD0BaseAddress;
+ UINTN ResMemLimit1;
+ //
+ // Allocate 56 KB of I/O space [0x2000..0xFFFF]
+ //
+ DEBUG ((DEBUG_INFO, " Assign IO resource for PCI_ROOT_BRIDGE from 0x%X to 0x%X\n", PcdGet16 (PcdPciReservedIobase) ,PcdGet16 (PcdPciReservedIoLimit)));
+
+ //
+ // Read memory map registers
+ //
+ McD0BaseAddress = PCI_SEGMENT_LIB_ADDRESS (SA_SEG_NUM, SA_MC_BUS, 0, 0, 0);
+ Tolud = PciSegmentRead32 (McD0BaseAddress + R_SA_TOLUD) & B_SA_TOLUD_TOLUD_MASK;
+ PciBaseAddress = Tolud;
+
+ ResMemLimit1 = PcdGet32 (PcdPciReservedMemLimit);
+ if (ResMemLimit1 == 0) {
+ ResMemLimit1 = (UINTN) PcdGet64 (PcdPciExpressBaseAddress);
+ }
+
+ Length = ResMemLimit1 - PciBaseAddress;
+
+ if (Length != 0) {
+ PcdSet32S (PcdPciReservedMemBase, (UINT32) PciBaseAddress);
+ PcdSet32S (PcdPciReservedMemLimit, (UINT32) (PciBaseAddress + Length - 1));
+ DEBUG ((DEBUG_INFO, " Assign Memory Resource for PCI_ROOT_BRIDGE from 0x%X", PcdGet32 (PcdPciReservedMemBase)));
+ DEBUG ((DEBUG_INFO, " to 0x%X\n", PcdGet32 (PcdPciReservedMemLimit)));
+ }
+
+ //
+ // Provide 256GB available above 4GB MMIO resource
+ // limited to use single variable MTRR to cover this above 4GB MMIO region.
+ //
+ PcdSet64S (PcdPciReservedMemAbove4GBBase, BASE_256GB);
+ PcdSet64S (PcdPciReservedMemAbove4GBLimit, BASE_256GB + SIZE_256GB - 1);
+ if (PcdGet64 (PcdPciReservedMemAbove4GBBase) < PcdGet64 (PcdPciReservedMemAbove4GBLimit)) {
+ DEBUG ((DEBUG_INFO, " PCI space that above 4GB MMIO is from 0x%lX", PcdGet64 (PcdPciReservedMemAbove4GBBase)));
+ DEBUG ((DEBUG_INFO, " to 0x%lX\n", PcdGet64 (PcdPciReservedMemAbove4GBLimit)));
+ }
+}
+
+/**
+ This function handles PlatformInit task at the end of PEI
+
+ @param[in] PeiServices Pointer to PEI Services Table.
+ @param[in] NotifyDesc Pointer to the descriptor for the Notification event that
+ caused this function to execute.
+ @param[in] Ppi Pointer to the PPI data associated with this function.
+
+ @retval EFI_SUCCESS The function completes successfully
+ @retval others
+**/
+EFI_STATUS
+EFIAPI
+OpenBoardPlatformInitEndOfPei (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
+ IN VOID *Ppi
+ )
+{
+ EFI_STATUS Status;
+
+ Status = SetCacheMtrrAfterEndOfPei ();
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Configure PciHostBridge related PCDs before DXE phase
+ //
+ ConfigurePciHostBridgePcds ();
+
+ return Status;
+}
+
+
+/**
+ Platform Init PEI module entry point
+
+ @param[in] FileHandle Not used.
+ @param[in] PeiServices General purpose services available to every PEIM.
+
+ @retval EFI_SUCCESS The function completes successfully
+ @retval EFI_OUT_OF_RESOURCES Insufficient resources to create database
+**/
+EFI_STATUS
+EFIAPI
+OpenBoardPlatformInitPostMemEntryPoint (
+ IN EFI_PEI_FILE_HANDLE FileHandle,
+ IN CONST EFI_PEI_SERVICES **PeiServices
+ )
+{
+ EFI_STATUS Status;
+ PEI_CORE_INSTANCE *PrivateData;
+ UINTN CurrentFv;
+ PEI_CORE_FV_HANDLE *CoreFvHandle;
+ VOID *HobData;
+
+ PostCode (PLATFORM_INIT_POSTMEM_ENTRY);
+
+
+ //
+ // Build a HOB to show current FV location for SA policy update code to consume.
+ //
+ PrivateData = PEI_CORE_INSTANCE_FROM_PS_THIS(PeiServices);
+ CurrentFv = PrivateData->CurrentPeimFvCount;
+ CoreFvHandle = &(PrivateData->Fv[CurrentFv]);
+
+ HobData = BuildGuidHob (
+ &gPlatformInitFvLocationGuid,
+ sizeof (VOID *)
+ );
+ ASSERT (HobData != NULL);
+ CopyMem (HobData, (VOID *) &CoreFvHandle, sizeof (VOID *));
+
+#if FixedPcdGetBool(PcdAdlLpSupport) == 1
+ //
+ // Install mPeiGraphicsPlatformPpi
+ //
+ DEBUG ((DEBUG_INFO, "Install mPeiGraphicsPlatformPpi \n"));
+ Status = PeiServicesInstallPpi (&mPeiGraphicsPlatformPpi);
+#else
+ //
+ // Notify mPeiGraphicsPlatformNotifyList
+ //
+ DEBUG ((DEBUG_INFO, "Notify mPeiGraphicsPlatformNotifyList \n"));
+ Status = PeiServicesNotifyPpi (&mPeiGraphicsPlatformNotifyList);
+#endif
+
+ //
+ // Performing PlatformInitEndOfPei after EndOfPei PPI produced
+ //
+ Status = PeiServicesNotifyPpi (&mEndOfPeiNotifyList);
+ PostCode (PLATFORM_INIT_POSTMEM_EXIT);
+
+ return Status;
+}
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/OpenBoardPlatformInit/OpenBoardPlatformInitPei/OpenBoardPlatformInitPostMem.inf b/Platform/Intel/AlderlakeOpenBoardPkg/OpenBoardPlatformInit/OpenBoardPlatformInitPei/OpenBoardPlatformInitPostMem.inf
new file mode 100644
index 0000000000..ff8e8fc60b
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/OpenBoardPlatformInit/OpenBoardPlatformInitPei/OpenBoardPlatformInitPostMem.inf
@@ -0,0 +1,84 @@
+### @file
+# Component information file for the OpenBoard Platform Init PEI module.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+###
+
+[Defines]
+ INF_VERSION = 0x00010017
+ BASE_NAME = OpenBoardPlatformInitPostMem
+ FILE_GUID = 314EE04C-1106-4DC6-ACBC-CF19C0DBC5CC
+ VERSION_STRING = 1.0
+ MODULE_TYPE = PEIM
+ ENTRY_POINT = OpenBoardPlatformInitPostMemEntryPoint
+
+[LibraryClasses]
+ PeimEntryPoint
+ DebugLib
+ IoLib
+ MemoryAllocationLib
+ BaseMemoryLib
+ HobLib
+ PeiServicesLib
+ PciSegmentLib
+ MtrrLib
+ PchInfoLib
+ PostCodeLib
+ SiPolicyLib
+ FspCommonLib
+ PcdLib
+ PchPciBdfLib
+ GpioLib
+ PeiGetFvInfoLib
+
+[Packages]
+ AlderlakeSiliconPkg/SiPkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ MdePkg/MdePkg.dec
+ UefiCpuPkg/UefiCpuPkg.dec
+ IntelFsp2Pkg/IntelFsp2Pkg.dec
+ IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec
+ AlderLakeFspBinPkg/Client/AlderLakeP/AlderLakeFspBinPkg.dec
+ SecurityPkg/SecurityPkg.dec
+ AlderlakeOpenBoardPkg/OpenBoardPkg.dec
+ MinPlatformPkg/MinPlatformPkg.dec
+ IntelSiliconPkg/IntelSiliconPkg.dec
+
+[Sources]
+ OpenBoardPlatformInitPostMem.c
+
+[Ppis]
+ gEfiEndOfPeiSignalPpiGuid ## CONSUMES
+ gEfiPeiReadOnlyVariable2PpiGuid ## CONSUMES
+ gPeiGraphicsPlatformPpiGuid ## PRODUCES
+ gFspSiliconInitDonePpiGuid ## CONSUMES
+
+[Protocols]
+
+[Guids]
+ gEfiSmmSmramMemoryGuid ## CONSUMES
+ gPlatformInitFvLocationGuid ## PRODUCES
+
+[Depex]
+ gEfiPeiMemoryDiscoveredPpiGuid
+
+[Pcd]
+ gEfiSecurityPkgTokenSpaceGuid.PcdFirmwareDebuggerInitialized ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdPlatformFlavor ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdPlatformType ## CONSUMES
+ gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdPciReservedIobase ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdPciReservedIoLimit ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdPciReservedMemBase ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdPciReservedMemLimit ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdPciReservedMemAbove4GBBase ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdPciReservedMemAbove4GBLimit ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdPciSegmentCount ## CONSUMES
+
+ gIntelSiliconPkgTokenSpaceGuid.PcdIntelGraphicsVbtFileGuid ## CONSUMES
+
+[FixedPcd]
+ gSiPkgTokenSpaceGuid.PcdAdlLpSupport ## CONSUMES
+ gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection ## CONSUMES
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/OpenBoardPlatformInit/OpenBoardPlatformInitPei/OpenBoardPlatformInitPreMem.c b/Platform/Intel/AlderlakeOpenBoardPkg/OpenBoardPlatformInit/OpenBoardPlatformInitPei/OpenBoardPlatformInitPreMem.c
new file mode 100644
index 0000000000..21c3e6a221
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/OpenBoardPlatformInit/OpenBoardPlatformInitPei/OpenBoardPlatformInitPreMem.c
@@ -0,0 +1,192 @@
+/** @file
+ Source code file for OpenBoard Platform Init Pre-Memory PEI module
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <PiPei.h>
+#include <Ppi/Reset.h>
+#include <Ppi/ReadOnlyVariable2.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/HobLib.h>
+#include <Library/IoLib.h>
+#include <Library/PcdLib.h>
+#include <Library/PciSegmentLib.h>
+#include <Library/PostCodeLib.h>
+#include <Register/PchRegs.h>
+#include <PlatformPostCode.h>
+#include <Library/PeiServicesLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <CpuRegs.h>
+
+
+///
+/// Reset Generator I/O Port
+///
+#define RESET_GENERATOR_PORT 0xCF9
+
+EFI_STATUS
+EFIAPI
+PlatformInitPreMem (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
+ IN VOID *Ppi
+ );
+
+EFI_STATUS
+EFIAPI
+MemoryDiscoveredPpiNotifyCallback (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
+ IN VOID *Ppi
+ );
+
+EFI_STATUS
+EFIAPI
+PchReset (
+ IN CONST EFI_PEI_SERVICES **PeiServices
+ );
+
+static EFI_PEI_NOTIFY_DESCRIPTOR mPreMemNotifyList = {
+ (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
+ &gEfiPeiReadOnlyVariable2PpiGuid,
+ (EFI_PEIM_NOTIFY_ENTRY_POINT) PlatformInitPreMem
+};
+
+static EFI_PEI_NOTIFY_DESCRIPTOR mMemDiscoveredNotifyList = {
+ (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
+ &gEfiPeiMemoryDiscoveredPpiGuid,
+ (EFI_PEIM_NOTIFY_ENTRY_POINT) MemoryDiscoveredPpiNotifyCallback
+};
+
+static EFI_PEI_RESET_PPI mResetPpi = {
+ PchReset
+};
+
+static EFI_PEI_PPI_DESCRIPTOR mPreMemPpiList[] = {
+ {
+ (EFI_PEI_PPI_DESCRIPTOR_PPI| EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
+ &gEfiPeiResetPpiGuid,
+ &mResetPpi
+ }
+};
+
+
+/**
+ Callback once there is main memory
+
+ @param[in] PeiServices General purpose services available to every PEIM.
+ @param[in] NotifyDescriptor Notify that this module published.
+ @param[in] Ppi PPI that was installed.
+
+ @retval EFI_SUCCESS The function completed successfully.
+**/
+EFI_STATUS
+EFIAPI
+MemoryDiscoveredPpiNotifyCallback (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
+ IN VOID *Ppi
+ )
+{
+ return EFI_SUCCESS;
+}
+
+//@todo it should be performed in Si Pkg.
+/**
+ Provide hard reset PPI service.
+ To generate full hard reset, write 0x0E to PCH RESET_GENERATOR_PORT (0xCF9).
+
+ @param[in] PeiServices General purpose services available to every PEIM.
+
+ @retval Not return System reset occured.
+ @retval EFI_DEVICE_ERROR Device error, could not reset the system.
+**/
+EFI_STATUS
+EFIAPI
+PchReset (
+ IN CONST EFI_PEI_SERVICES **PeiServices
+ )
+{
+ DEBUG ((DEBUG_INFO, "Perform Cold Reset\n"));
+ IoWrite8 (RESET_GENERATOR_PORT, 0x0E);
+
+ CpuDeadLoop ();
+
+ ///
+ /// System reset occured, should never reach at this line.
+ ///
+ ASSERT_EFI_ERROR (EFI_DEVICE_ERROR);
+
+ return EFI_DEVICE_ERROR;
+}
+
+/**
+ This function handles PlatformInit task after PeiReadOnlyVariable2 PPI produced
+
+ @param[in] PeiServices Pointer to PEI Services Table.
+ @param[in] NotifyDesc Pointer to the descriptor for the Notification event that
+ caused this function to execute.
+ @param[in] Ppi Pointer to the PPI data associated with this function.
+
+ @retval EFI_SUCCESS The function completes successfully
+ @retval others
+**/
+EFI_STATUS
+EFIAPI
+PlatformInitPreMem (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
+ IN VOID *Ppi
+ )
+{
+ EFI_STATUS Status;
+
+ PostCode(PLATFORM_INIT_PREMEM_ENTRY);
+
+ ///
+ /// Install Pre Memory PPIs
+ ///
+ Status = PeiServicesInstallPpi (&mPreMemPpiList[0]);
+ ASSERT_EFI_ERROR (Status);
+
+ PostCode(PLATFORM_INIT_PREMEM_EXIT);
+
+ return Status;
+}
+
+/**
+ Platform Init before memory PEI module entry point
+
+ @param[in] FileHandle Not used.
+ @param[in] PeiServices General purpose services available to every PEIM.
+
+ @retval EFI_SUCCESS The function completes successfully
+ @retval EFI_OUT_OF_RESOURCES Insufficient resources to create database
+**/
+EFI_STATUS
+EFIAPI
+OpenBoardPlatformInitPreMemEntryPoint (
+ IN EFI_PEI_FILE_HANDLE FileHandle,
+ IN CONST EFI_PEI_SERVICES **PeiServices
+ )
+{
+ EFI_STATUS Status;
+
+ ///
+ /// Performing PlatformInitPreMem after PeiReadOnlyVariable2 PPI produced
+ ///
+ Status = PeiServicesNotifyPpi (&mPreMemNotifyList);
+
+ ///
+ /// After code reorangized, memorycallback will run because the PPI is already
+ /// installed when code run to here, it is supposed that the InstallEfiMemory is
+ /// done before.
+ ///
+ Status = PeiServicesNotifyPpi (&mMemDiscoveredNotifyList);
+
+ return Status;
+}
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/OpenBoardPlatformInit/OpenBoardPlatformInitPei/OpenBoardPlatformInitPreMem.inf b/Platform/Intel/AlderlakeOpenBoardPkg/OpenBoardPlatformInit/OpenBoardPlatformInitPei/OpenBoardPlatformInitPreMem.inf
new file mode 100644
index 0000000000..e92ef0279a
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/OpenBoardPlatformInit/OpenBoardPlatformInitPei/OpenBoardPlatformInitPreMem.inf
@@ -0,0 +1,59 @@
+### @file
+# Component information file for the OpenBoard Platform Init Pre-Memory PEI module.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+###
+
+[Defines]
+ INF_VERSION = 0x00010017
+ BASE_NAME = OpenBoardPlatformInitPreMem
+ FILE_GUID = 56BBC314-B442-4D5A-BA5C-D842DAFDBB24
+ VERSION_STRING = 1.0
+ MODULE_TYPE = PEIM
+ ENTRY_POINT = OpenBoardPlatformInitPreMemEntryPoint
+
+[LibraryClasses]
+ PeimEntryPoint
+ BaseMemoryLib
+ DebugLib
+ HobLib
+ IoLib
+ PcdLib
+ PciSegmentLib
+ PostCodeLib
+ PostCodeMapLib
+ PeiServicesLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ UefiCpuPkg/UefiCpuPkg.dec
+ IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec
+ BoardModulePkg/BoardModulePkg.dec
+ PostCodeDebugFeaturePkg/PostCodeDebugFeaturePkg.dec
+ AlderlakeSiliconPkg/SiPkg.dec
+ AlderlakeOpenBoardPkg/OpenBoardPkg.dec
+ MinPlatformPkg/MinPlatformPkg.dec
+ SecurityPkg/SecurityPkg.dec
+
+[Pcd]
+ gPlatformModuleTokenSpaceGuid.PcdRamDebugEnable ## CONSUMES
+ gPlatformModuleTokenSpaceGuid.PcdSerialPortEnable ## CONSUMES
+ gSiPkgTokenSpaceGuid.PcdSerialIoUartEnable ## CONSUMES
+ gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial ## PRODUCES
+
+[Sources]
+ OpenBoardPlatformInitPreMem.c
+
+[Ppis]
+ gEfiPeiReadOnlyVariable2PpiGuid ## SOMETIMES_CONSUMES ## NOTIFY
+ gEfiPeiMemoryDiscoveredPpiGuid ## NOTIFY
+ gEfiPeiResetPpiGuid ## NOTIFY
+
+[Guids]
+ gDebugConfigVariableGuid ## CONSUMES ## Variable
+
+[Depex]
+ gEfiPeiReadOnlyVariable2PpiGuid
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/OpenBoardPlatformInit/OpenBoardPlatformInitSmm/OpenBoardPlatformInitSmm.c b/Platform/Intel/AlderlakeOpenBoardPkg/OpenBoardPlatformInit/OpenBoardPlatformInitSmm/OpenBoardPlatformInitSmm.c
new file mode 100644
index 0000000000..4ae8995bf1
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/OpenBoardPlatformInit/OpenBoardPlatformInitSmm/OpenBoardPlatformInitSmm.c
@@ -0,0 +1,250 @@
+/** @file
+ OpenBoard Platform SMM Driver.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "OpenBoardPlatformInitSmm.h"
+#include <CpuRegs.h>
+#include <PchPolicyCommon.h>
+#include "AcpiCommon.h"
+#include <Library/PmcLib.h>
+#include <Library/PciSegmentLib.h>
+#include <Library/PostCodeLib.h>
+#include <PlatformPostCode.h>
+#include <Register/PchRegs.h>
+#include <Register/PmcRegs.h>
+#include <Register/RtcRegs.h>
+
+//
+// Global variables
+//
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_SMM_SYSTEM_TABLE2 *mSmst;
+GLOBAL_REMOVE_IF_UNREFERENCED UINT16 mAcpiBaseAddr;
+GLOBAL_REMOVE_IF_UNREFERENCED PLATFORM_NVS_AREA *mPlatformNvsAreaPtr = 0;
+
+/**
+ Clear Port 80h
+
+ SMI handler to enable ACPI mode
+
+ Dispatched on reads from APM port with value EFI_ACPI_ENABLE_SW_SMI
+
+ Disables the SW SMI Timer.
+ ACPI events are disabled and ACPI event status is cleared.
+ SCI mode is then enabled.
+
+ Clear SLP SMI status
+ Enable SLP SMI
+
+ Disable SW SMI Timer
+
+ Clear all ACPI event status and disable all ACPI events
+
+ Disable PM sources except power button
+ Clear status bits
+
+ Disable GPE0 sources
+ Clear status bits
+
+ Disable GPE1 sources
+ Clear status bits
+
+ Guarantee day-of-month alarm is invalid (ACPI 1.0 section 4.7.2.4)
+
+ Enable SCI
+
+ Set 8254 timer clock gate enable if it's not set in early phase
+
+ @param[in] DispatchHandle - The handle of this callback, obtained when registering
+ @param[in] DispatchContext - Pointer to the EFI_SMM_SW_DISPATCH_CONTEXT
+ @param[in] CommBuffer - A pointer to a collection of data in memory that will
+ be conveyed from a non-SMM environment into an SMM environment.
+ @param[in] CommBufferSize - The size of the CommBuffer.
+**/
+EFI_STATUS
+EFIAPI
+EnableAcpiCallback (
+ IN EFI_HANDLE DispatchHandle,
+ IN CONST VOID *DispatchContext,
+ IN OUT VOID *CommBuffer OPTIONAL,
+ IN OUT UINTN *CommBufferSize OPTIONAL
+ )
+{
+ UINT32 OutputValue;
+ UINT32 Pm1Cnt;
+ EFI_STATUS Status;
+
+ Status = EFI_SUCCESS;
+ //
+ // BIOS must also ensure that CF9GR is cleared and locked before handing control to the
+ // OS in order to prevent the host from issuing global resets and resetting ME
+ //
+ // EDK2: To match PCCG current BIOS behavior, do not lock CF9 Global Reset
+ // MmioWrite32 (
+ // PmcBaseAddress + R_PCH_PMC_ETR3),
+ // PmInit);
+
+ //
+ // Clear Port 80h
+ //
+ OutputValue = 0;
+ mSmst->SmmIo.Io.Write (&mSmst->SmmIo, SMM_IO_UINT16, 0x80, 1, &OutputValue);
+
+ //
+ // Disable PM sources except power button
+ //
+ OutputValue = B_ACPI_IO_PM1_EN_PWRBTN;
+ mSmst->SmmIo.Io.Write (&mSmst->SmmIo, SMM_IO_UINT16, mAcpiBaseAddr + R_ACPI_IO_PM1_EN, 1, &OutputValue);
+ //
+ // Clear PM status except Power Button status for RapidStart Resume
+ //
+ // OutputValue = 0xFFFF;
+ OutputValue = 0xFEFF;
+ mSmst->SmmIo.Io.Write (&mSmst->SmmIo, SMM_IO_UINT16, mAcpiBaseAddr + R_ACPI_IO_PM1_STS, 1, &OutputValue);
+
+ //
+ // Guarantee day-of-month alarm is invalid (ACPI 1.0 section 4.7.2.4)
+ //
+ OutputValue = R_RTC_IO_REGD;
+ mSmst->SmmIo.Io.Write (&mSmst->SmmIo, SMM_IO_UINT8, R_RTC_IO_INDEX_ALT, 1, &OutputValue);
+ OutputValue = 0x0;
+ mSmst->SmmIo.Io.Write (&mSmst->SmmIo, SMM_IO_UINT8, R_RTC_IO_TARGET_ALT, 1, &OutputValue);
+
+ //
+ // Enable SCI
+ //
+ mSmst->SmmIo.Io.Read (&mSmst->SmmIo, SMM_IO_UINT32, mAcpiBaseAddr + R_ACPI_IO_PM1_CNT, 1, &Pm1Cnt);
+ Pm1Cnt |= B_ACPI_IO_PM1_CNT_SCI_EN;
+ mSmst->SmmIo.Io.Write (&mSmst->SmmIo, SMM_IO_UINT32, mAcpiBaseAddr + R_ACPI_IO_PM1_CNT, 1, &Pm1Cnt);
+ //
+ // Write ALT_GPI_SMI_EN to disable GPI1 (SMC_EXTSMI#)
+ //
+ OutputValue = 0;
+ mSmst->SmmIo.Io.Read (&mSmst->SmmIo, SMM_IO_UINT32, mAcpiBaseAddr + 0x38, 1, &OutputValue);
+ OutputValue = OutputValue & ~(1 << (UINTN) PcdGet8 (PcdSmcExtSmiBitPosition));
+ mSmst->SmmIo.Io.Write (&mSmst->SmmIo, SMM_IO_UINT32, mAcpiBaseAddr + 0x38, 1, &OutputValue);
+
+
+ return Status;
+}
+
+/**
+ Disable SCI
+
+ @param[in] DispatchHandle - The handle of this callback, obtained when registering
+ @param[in] DispatchContext - Pointer to the EFI_SMM_SW_DISPATCH_CONTEXT
+ @param[in] CommBuffer - A pointer to a collection of data in memory that will
+ be conveyed from a non-SMM environment into an SMM environment.
+ @param[in] CommBufferSize - The size of the CommBuffer.
+**/
+EFI_STATUS
+EFIAPI
+DisableAcpiCallback (
+ IN EFI_HANDLE DispatchHandle,
+ IN CONST VOID *DispatchContext,
+ IN OUT VOID *CommBuffer OPTIONAL,
+ IN UINTN *CommBufferSize OPTIONAL
+ )
+{
+ UINT32 Pm1Cnt;
+
+ //
+ // Disable SCI
+ //
+ mSmst->SmmIo.Io.Read (&mSmst->SmmIo, SMM_IO_UINT32, mAcpiBaseAddr + R_ACPI_IO_PM1_CNT, 1, &Pm1Cnt);
+ Pm1Cnt &= ~B_ACPI_IO_PM1_CNT_SCI_EN;
+ mSmst->SmmIo.Io.Write (&mSmst->SmmIo, SMM_IO_UINT32, mAcpiBaseAddr + R_ACPI_IO_PM1_CNT, 1, &Pm1Cnt);
+
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Initializes the SMM Platform Driver
+
+ @param[in] ImageHandle - Pointer to the loaded image protocol for this driver
+ @param[in] SystemTable - Pointer to the EFI System Table
+
+ @retval Status - EFI_SUCCESS
+ @retval Assert, otherwise.
+
+**/
+EFI_STATUS
+EFIAPI
+InitializePlatformSmm (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUS Status;
+ EFI_HANDLE Handle;
+ EFI_HANDLE SwHandle;
+ EFI_SMM_SW_DISPATCH2_PROTOCOL *SwDispatch;
+ EFI_SMM_SW_REGISTER_CONTEXT SwContext;
+ PLATFORM_NVS_AREA_PROTOCOL *PlatformNvsAreaProtocol;
+
+
+ Handle = NULL;
+ SwHandle = NULL;
+
+ PostCode (PLATFORM_SMM_INIT_ENTRY);
+
+ //
+ // Great! We're now in SMM!
+ //
+
+ //
+ // Initialize global variables
+ //
+ mSmst = gSmst;
+
+ //
+ // Get the ACPI Base Address
+ //
+ mAcpiBaseAddr = PmcGetAcpiBase ();
+
+ //
+ // Locate the ICH SMM SW dispatch protocol
+ //
+ Status = mSmst->SmmLocateProtocol (&gEfiSmmSwDispatch2ProtocolGuid, NULL, (VOID**)&SwDispatch);
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Locate our shared data area
+ //
+ Status = gBS->LocateProtocol (&gPlatformNvsAreaProtocolGuid, NULL, (VOID **) &PlatformNvsAreaProtocol);
+ ASSERT_EFI_ERROR (Status);
+ mPlatformNvsAreaPtr = PlatformNvsAreaProtocol->Area;
+
+ //
+ // Register ACPI enable handler
+ //
+ SwContext.SwSmiInputValue = (UINTN) PcdGet8 (PcdAcpiEnableSwSmi);
+ Status = SwDispatch->Register (
+ SwDispatch,
+ EnableAcpiCallback,
+ &SwContext,
+ &SwHandle
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Register ACPI disable handler
+ //
+ SwContext.SwSmiInputValue = (UINTN) PcdGet8 (PcdAcpiDisableSwSmi);
+ Status = SwDispatch->Register (
+ SwDispatch,
+ DisableAcpiCallback,
+ &SwContext,
+ &SwHandle
+ );
+ ASSERT_EFI_ERROR (Status);
+
+
+ PostCode(PLATFORM_SMM_INIT_EXIT);
+
+ return EFI_SUCCESS;
+}
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/OpenBoardPlatformInit/OpenBoardPlatformInitSmm/OpenBoardPlatformInitSmm.h b/Platform/Intel/AlderlakeOpenBoardPkg/OpenBoardPlatformInit/OpenBoardPlatformInitSmm/OpenBoardPlatformInitSmm.h
new file mode 100644
index 0000000000..f8949f613f
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/OpenBoardPlatformInit/OpenBoardPlatformInitSmm/OpenBoardPlatformInitSmm.h
@@ -0,0 +1,50 @@
+/** @file
+ Header file for the OpenBoard Platform SMM Driver.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _OPEN_BOARD_PLATFORM_INIT_SMM_H_
+#define _OPEN_BOARD_PLATFORM_INIT_SMM_H_
+
+#include "Platform.h"
+#include <Uefi/UefiBaseType.h>
+#include <Library/IoLib.h>
+#include <Library/PcdLib.h>
+#include <Library/DebugLib.h>
+#include <Library/SmmServicesTableLib.h>
+#include <Library/ReportStatusCodeLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/UefiRuntimeServicesTableLib.h>
+#include <PlatformBoardType.h>
+#include <Protocol/PciRootBridgeIo.h>
+#include <Protocol/SmmBase2.h>
+#include <Protocol/SmmSwDispatch2.h>
+#include <Protocol/PlatformNvsArea.h>
+#include <IndustryStandard/Pci30.h>
+
+//
+// Callback function prototypes
+//
+EFI_STATUS
+EFIAPI
+EnableAcpiCallback (
+ IN EFI_HANDLE DispatchHandle,
+ IN CONST VOID *DispatchContext,
+ IN OUT VOID *CommBuffer OPTIONAL,
+ IN UINTN *CommBufferSize OPTIONAL
+ );
+
+EFI_STATUS
+EFIAPI
+DisableAcpiCallback (
+ IN EFI_HANDLE DispatchHandle,
+ IN CONST VOID *DispatchContext,
+ IN OUT VOID *CommBuffer OPTIONAL,
+ IN UINTN *CommBufferSize OPTIONAL
+ );
+
+#endif
+
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/OpenBoardPlatformInit/OpenBoardPlatformInitSmm/OpenBoardPlatformInitSmm.inf b/Platform/Intel/AlderlakeOpenBoardPkg/OpenBoardPlatformInit/OpenBoardPlatformInitSmm/OpenBoardPlatformInitSmm.inf
new file mode 100644
index 0000000000..f426090a46
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/OpenBoardPlatformInit/OpenBoardPlatformInitSmm/OpenBoardPlatformInitSmm.inf
@@ -0,0 +1,60 @@
+### @file
+# Component information file for OpenBoard Platform SMM Driver
+#
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+###
+
+[Defines]
+ INF_VERSION = 0x00010017
+ BASE_NAME = OpenBoardPlatformInitSmm
+ FILE_GUID = CB73C3D9-2F01-4342-AE67-04DDE5264092
+ VERSION_STRING = 1.0
+ MODULE_TYPE = DXE_SMM_DRIVER
+ PI_SPECIFICATION_VERSION = 1.20
+ ENTRY_POINT = InitializePlatformSmm
+
+[LibraryClasses]
+ UefiDriverEntryPoint
+ BaseMemoryLib
+ BasePciLibPciExpress
+ DebugLib
+ ReportStatusCodeLib
+ SmmServicesTableLib
+ PmcLib
+ UefiRuntimeServicesTableLib
+ PciSegmentLib
+ PostCodeLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ AlderlakeSiliconPkg/SiPkg.dec
+ AlderlakeOpenBoardPkg/OpenBoardPkg.dec
+ UefiCpuPkg/UefiCpuPkg.dec
+
+[Pcd]
+ gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ## CONSUMES
+ gPlatformModuleTokenSpaceGuid.PcdAcpiEnableSwSmi ## CONSUMES
+ gPlatformModuleTokenSpaceGuid.PcdAcpiDisableSwSmi ## CONSUMES
+ gPlatformModuleTokenSpaceGuid.PcdSmcExtSmiBitPosition ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdPlatformFlavor
+
+[Sources]
+ OpenBoardPlatformInitSmm.h
+ OpenBoardPlatformInitSmm.c
+
+[Protocols]
+ gPlatformNvsAreaProtocolGuid ## CONSUMES
+ gEfiSmmBase2ProtocolGuid ## CONSUMES
+ gEfiSmmSwDispatch2ProtocolGuid ## CONSUMES
+
+[Depex]
+ gEfiSmmBase2ProtocolGuid AND
+ gEfiSmmSwDispatch2ProtocolGuid AND
+ gPlatformNvsAreaProtocolGuid
+
+
+
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/SBCVpdStructurePcd/AllStructPCD.dsc b/Platform/Intel/AlderlakeOpenBoardPkg/SBCVpdStructurePcd/AllStructPCD.dsc
new file mode 100644
index 0000000000..9215a026ae
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/SBCVpdStructurePcd/AllStructPCD.dsc
@@ -0,0 +1,19 @@
+## @file
+# Include All Board Gpio configuration file.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+!include $(PLATFORM_BOARD_PACKAGE)/SBCVpdStructurePcd/GpioTableAdlPPostMem.dsc
+!include $(PLATFORM_BOARD_PACKAGE)/SBCVpdStructurePcd/GpioTableAdlPPreMem.dsc
+
+
+# PCIe clock mapping
+!include $(PLATFORM_BOARD_PACKAGE)/SBCVpdStructurePcd/PcieClocks/AdlPPcieClocks.dsc
+
+# MRC DQS DQ and SPD mapping
+!include $(PLATFORM_BOARD_PACKAGE)/SBCVpdStructurePcd/MrcDqDqsSPD/AdlPSpdMap.dsc
+
+
+
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/SBCVpdStructurePcd/GpioTableAdlPPostMem.dsc b/Platform/Intel/AlderlakeOpenBoardPkg/SBCVpdStructurePcd/GpioTableAdlPPostMem.dsc
new file mode 100644
index 0000000000..3eb8c276b5
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/SBCVpdStructurePcd/GpioTableAdlPPostMem.dsc
@@ -0,0 +1,40 @@
+## @file
+# GPIO definition table for Alderlake P
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+###
+### !!! GPIOs designated to Native Functions shall not be configured by Platform Code.
+### Native Pins shall be configured by Silicon Code (based on BIOS policies setting) or soft straps(set by CSME in FITc).
+###
+###
+
+
+#mGpioTableAdlPDdr5Rvp
+[PcdsDynamicExVpd.common.SkuIdAdlPDdr5Rvp]
+gBoardModuleTokenSpaceGuid.VpdPcdBoardGpioTable|*|{CODE({
+ // CPU M.2 SSD1
+ {GPIO_VER2_LP_GPP_F20, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis,GpioPlatformReset, GpioTermNone}}, //CPU SSD1 RESET
+
+ // CPU M.2 SSD2
+ {GPIO_VER2_LP_GPP_C2, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis,GpioPlatformReset, GpioTermNone}}, //CPU SSD2 PWREN
+ {GPIO_VER2_LP_GPP_H1, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis,GpioPlatformReset, GpioTermNone}}, // CPU SSD2 RESET
+
+ // X4 Pcie Slot for Gen3 and Gen 4
+ {GPIO_VER2_LP_GPP_F10, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis,GpioPlatformReset, GpioTermNone}},//ONBOARD_X4_PCIE_SLOT1_RESET_N
+
+ // PCH M.2 SSD
+ {GPIO_VER2_LP_GPP_D16, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis,GpioPlatformReset, GpioTermNone}}, //M2_PCH_SSD_PWREN
+ {GPIO_VER2_LP_GPP_H0, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis,GpioPlatformReset, GpioTermNone}}, //M2_SSD_RST_N
+
+ // EC
+ {GPIO_VER2_LP_GPP_E7, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault,GpioIntLevel|GpioIntSmi,GpioPlatformReset, GpioTermNone, GpioPadConfigUnlock }}, //EC_SMI_N
+ {GPIO_VER2_LP_GPP_F9, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis,GpioPlatformReset, GpioTermNone}}, //EC_SLP_S0_CS_N
+
+ {0x0} // terminator
+})}
+
+
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/SBCVpdStructurePcd/GpioTableAdlPPreMem.dsc b/Platform/Intel/AlderlakeOpenBoardPkg/SBCVpdStructurePcd/GpioTableAdlPPreMem.dsc
new file mode 100644
index 0000000000..3e147894c7
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/SBCVpdStructurePcd/GpioTableAdlPPreMem.dsc
@@ -0,0 +1,29 @@
+## @file
+# Alderlake P RVP GPIO definition table for Pre-Memory Initialization
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+###
+### !!! GPIOs designated to Native Functions shall not be configured by Platform Code.
+### Native Pins shall be configured by Silicon Code (based on BIOS policies setting) or soft straps(set by CSME in FITc).
+###
+###
+
+# mGpioTablePreMemAdlPDdr5Rvp
+[PcdsDynamicExVpd.common.SkuIdAdlPDdr5Rvp]
+gBoardModuleTokenSpaceGuid.VpdPcdBoardGpioTablePreMem|*|{CODE({
+ // CPU M.2 SSD
+ { GPIO_VER2_LP_GPP_F20, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis, GpioPlatformReset, GpioTermNone } }, //CPU SSD RESET
+
+ // CPU M.2 SSD2
+ {GPIO_VER2_LP_GPP_C2, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis,GpioPlatformReset, GpioTermNone}}, //CPU SSD2 PWREN
+ {GPIO_VER2_LP_GPP_H1, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis,GpioPlatformReset, GpioTermNone}}, //CPU SSD2 RESET
+
+ // X4 Pcie Slot for Gen3 and Gen 4
+ {GPIO_VER2_LP_GPP_F10, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis,GpioPlatformReset, GpioTermNone}},//ONBOARD_X4_PCIE_SLOT1_RESET_N
+
+ {0x0} // terminator
+})}
\ No newline at end of file
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/SBCVpdStructurePcd/MrcDqDqsSPD/AdlPSpdMap.dsc b/Platform/Intel/AlderlakeOpenBoardPkg/SBCVpdStructurePcd/MrcDqDqsSPD/AdlPSpdMap.dsc
new file mode 100644
index 0000000000..096cc380cd
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/SBCVpdStructurePcd/MrcDqDqsSPD/AdlPSpdMap.dsc
@@ -0,0 +1,138 @@
+## @file
+# ADL P SPD DATA configuration file.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+
+[PcdsDynamicExVpd.common.SkuIdAdlPDdr5Rvp]
+gBoardModuleTokenSpaceGuid.VpdPcdMrcSpdData|*|{CODE(
+{
+// DDR5 1Rx16 - 4800 MHz
+ 1,
+ {0x30, ///< 0 1024 SPD bytes total
+ 0x08, ///< 1 SPD Revision 0.8
+ 0x12, ///< 2 DRAM Type: DDR5 SDRAM
+ 0x03, ///< 3 Module Type: Not Hybrid (DRAM only) / SO-DIMM Solution
+ 0x04, ///< 4 Monolithic SDRAM, 16 Gb SDRAM density
+ 0x00, ///< 5 16 Rows, 10 Columns
+ 0x40, ///< 6 x16 SDRAM I/O Width
+ 0x42, ///< 7 4 Bank Groups, 4 Banks per Bank Group
+ 0x00, ///< 8 Secondary SDRAM Density and Package
+ 0x00, ///< 9 Secondary SDRAM Addressing
+ 0x00, ///< 10 Secondary SDRAM I/O Width
+ 0x00, ///< 11 Secondary BankGroups and Banks per Bank Group
+ 0x60, ///< 12 PPR Supported, One row per bank group, Soft PPR Supported
+ 0x00, ///< 13 Commercial Temperature Grade, 0 to 85 C
+ 0x00, ///< 14 Reserved
+ 0x00, ///< 15 Reserved
+ 0x00, ///< 16 SDRAM Nominal Voltage VDD: 1.1V
+ 0x00, ///< 17 SDRAM Nominal Voltage VDDQ: 1.1V
+ 0x00, ///< 18 SDRAM Nominal Voltage VPP: 1.8V
+ 0x00, ///< 19 Reserved
+ 0xA1, ///< 20 tCKAVGmin LSB
+ 0x01, ///< 21 tCKAVGmin MSB
+ 0xE8, ///< 22 tCKAVGmax LSB
+ 0x03, ///< 23 tCKAVGmax MSB
+ 0x72, ///< 24 CAS Latencies supported (First Byte) : 32, 30, 28, 22
+ 0x15, ///< 25 CAS Latencies supported (Second Byte): 44, 40, 36
+ 0x00, ///< 26 CAS Latencies supported (Third Byte) :
+ 0x00, ///< 27 CAS Latencies supported (Fourth Byte):
+ 0x00, ///< 28 CAS Latencies supported (Fifth Byte) :
+ 0x00, ///< 29 Reserved
+ 0x1E, ///< 30 Minimum CAS Latency (tAAmin) LSB
+ 0x41, ///< 31 Minimum CAS Latency (tAAmin) MSB
+ 0x1E, ///< 32 Minimum RAS-to-CAS delay (tRCDmin) LSB
+ 0x41, ///< 33 Minimum RAS-to-CAS delay (tRCDmin) MSB
+ 0x1E, ///< 34 Minimum Row Precharge delay (tRPmin) LSB
+ 0x41, ///< 35 Minimum Row Precharge delay (tRPmin) MSB
+ 0x00, ///< 36 Minimum Active to Precharge delay (tRASmin) LSB
+ 0x7D, ///< 37 Minimum Active to Precharge delay (tRASmin) MSB
+ 0x1E, ///< 38 Minimum Active to Active/Refresh delay (tRCmin) LSB
+ 0xBE, ///< 39 Minimum Active to Active/Refresh delay (tRCmin) MSB
+ 0x30, ///< 40 Minimum Write Recovery time (tWRmin) LSB
+ 0x75, ///< 41 Minimum Write Recovery time (tWRmin) MSB
+ 0x27, ///< 42 Refresh Recovery Delay (tRFC1min) LSB
+ 0x01, ///< 43 Refresh Recovery Delay (tRFC1min) MSB
+ 0xA0, ///< 44 Refresh Recovery Delay (tRFC2min) MSB
+ 0x00, ///< 45 Refresh Recovery Delay (tRFC2min) MSB
+ 0x82, ///< 46 Refresh Recovery Delay (tRFCsbmin) MSB
+ 0x00, ///< 47 Refresh Recovery Delay (tRFCsbmin) MSB
+ 0, 0, ///< 48 - 49
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 50 - 59
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 60 - 69
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 70 - 79
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 80 - 89
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 90 - 99
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 100 - 109
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 110 - 119
+ 0, 0, 0, 0, 0, 0, ///< 120 - 125
+ 0x47, ///< 126 CRC Bytes 0 - 127 LSB
+ 0xAE, ///< 127 CRC Bytes 0 - 127 MSB
+ 0, 0, ///< 128 - 129
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 130 - 139
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 140 - 149
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 150 - 159
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 160 - 169
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 170 - 179
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 180 - 189
+ 0, 0, ///< 190 - 191
+ 0x08, ///< 192 SPD Revision for Module Information: 0.8
+ 0x00, ///< 193 Reserved
+ 0xC2, ///< 194 SPD Manufacturer ID First Byte
+ 0xC4, ///< 195 SPD Manufacturer ID Second Byte
+ 0x80, ///< 196 SPD Device Type
+ 0x00, ///< 197 SPD Device Revision
+ 0x80, ///< 198 PMIC0 Manufacturer ID First Byte
+ 0xB3, ///< 199 PMIC0 Manufacturer ID Second Byte
+ 0x80, ///< 200 PMIC0 Device Type
+ 0x11, ///< 201 PMIC0 Device Revision
+ 0, 0, 0, 0, ///< 202 - 205 PMIC1
+ 0, 0, 0, 0, ///< 206 - 209 PMIC2
+ 0x80, ///< 210 Thermal Sensors Manufacturer ID First Byte
+ 0xB3, ///< 211 Thermal Sensors Manufacturer ID First Byte
+ 0x80, ///< 212 Thermal Sensors Device Type
+ 0x11, ///< 213 Thermal Sensors Device Revision
+ 0, 0, 0, 0, 0, 0, ///< 214 - 219
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 220 - 229
+ 0x0F, ///< 230 Module Nominal Height
+ 0x10, ///< 231 Module Nominal Thickness
+ 0x00, ///< 232 Reference Raw Card Used
+ 0x01, ///< 233 1 Row of DRAM on Module
+ 0x01, ///< 234 1 Rank, 8 bits SDRAM data width per channel
+ 0x22, ///< 235 2 Channels per DIMM, 32 bits per Channel
+ 0, 0, 0, 0, ///< 236 - 239
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 240 - 249
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 250 - 259
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 260 - 269
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 270 - 279
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 280 - 289
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 290 - 299
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 300 - 309
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 310 - 319
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 320 - 329
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 330 - 339
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 340 - 349
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 350 - 359
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 360 - 369
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 370 - 379
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 380 - 389
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 390 - 399
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 400 - 409
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 410 - 419
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 420 - 429
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 430 - 439
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ///< 440 - 445
+ 0x9C, ///< 446 CRC for Bytes 128 - 253 LSB
+ 0xAD, ///< 447 CRC for Bytes 128 - 253 MSB
+ 0, 0, ///< 448 - 449
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 450 - 459
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 460 - 469
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 470 - 479
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 480 - 489
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 490 - 499
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 500 - 509
+ 0, 0 ///< 510 - 511
+ ///< Ignore bytes 512-1023, @todo_adl: support 1024 bytes SPD array
+}})}
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/SBCVpdStructurePcd/PcieClocks/AdlPPcieClocks.dsc b/Platform/Intel/AlderlakeOpenBoardPkg/SBCVpdStructurePcd/PcieClocks/AdlPPcieClocks.dsc
new file mode 100644
index 0000000000..9871bb0c87
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/SBCVpdStructurePcd/PcieClocks/AdlPPcieClocks.dsc
@@ -0,0 +1,32 @@
+## @file
+# Alderlake P Pcie Clock configuration file.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+
+[PcdsDynamicExVpd.common.SkuIdAdlPDdr5Rvp]
+gBoardModuleTokenSpaceGuid.VpdPcdPcieClkUsageMap|*|{CODE(
+{{
+ PCIE_PEG, // CPU M.2 SSD 1
+ PCIE_PCH + 8, // PCH M.2 SSD
+ PCIE_PCH + 4,
+ PCIE_PEG + 1, // X8 DG/DG2
+ PCIE_PEG + 2, // CPU M.2 SSD 2
+ PCIE_PCH + 5, // M.2 KEY B WWAN - PCIe P6
+ LAN_CLOCK,
+ // Default Case:
+ // - PCIe P7 mapped to GBELAN
+ // - PCIe P8 mapped to x4 PCIe DT Slot (Pair 1)
+ PCIE_PCH + 7, // x4 PCIe DT Slot (x1)
+ // Reworked Case: with rework and soft strap changes
+ // - PCIe P7 mapped to x4 PCIe DT Slot (Pair 2)
+ // - PCIe P8 mapped to x4 PCIe DT Slot (Pair 1)
+ // @todo: To support reworked case, enable the below code.
+ // PCIE_PCH + 6, // x4 PCIe DT Slot (x2)
+ NOT_USED,
+ NOT_USED
+}}
+)}
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/SmmMultiBoardAcpiSupportLib/SmmAcpiEnableLib.c b/Platform/Intel/AlderlakeOpenBoardPkg/SmmMultiBoardAcpiSupportLib/SmmAcpiEnableLib.c
new file mode 100644
index 0000000000..d5a51cbc14
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/SmmMultiBoardAcpiSupportLib/SmmAcpiEnableLib.c
@@ -0,0 +1,51 @@
+/** @file
+ SMM Board ACPI Enable Library
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Base.h>
+#include <Uefi.h>
+#include <PiDxe.h>
+#include <Library/BaseLib.h>
+#include <Library/IoLib.h>
+#include <Library/BoardAcpiTableLib.h>
+#include <Library/PcdLib.h>
+#include <Library/DebugLib.h>
+#include <PlatformBoardId.h>
+
+/**
+ Enable Board Acpi
+
+ @param[in] EnableSci Enable SCI if EnableSci parameters is True.
+
+ @retval EFI_SUCCESS The function always return successfully.
+**/
+EFI_STATUS
+EFIAPI
+BoardEnableAcpi (
+ IN BOOLEAN EnableSci
+ )
+{
+ // @todo:enable additional board register
+ return EFI_SUCCESS;
+}
+
+/**
+ Disable Board Acpi
+
+ @param[in] DisableSci Disable SCI if DisableSci parameters is True.
+
+ @retval EFI_SUCCESS The function always return successfully.
+**/
+EFI_STATUS
+EFIAPI
+BoardDisableAcpi (
+ IN BOOLEAN DisableSci
+ )
+{
+ // @todo: enable additional board register
+ return EFI_SUCCESS;
+}
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/SmmMultiBoardAcpiSupportLib/SmmMultiBoardAcpiSupportLib.c b/Platform/Intel/AlderlakeOpenBoardPkg/SmmMultiBoardAcpiSupportLib/SmmMultiBoardAcpiSupportLib.c
new file mode 100644
index 0000000000..c278409e7b
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/SmmMultiBoardAcpiSupportLib/SmmMultiBoardAcpiSupportLib.c
@@ -0,0 +1,89 @@
+/** @file
+ SMM Multi-Board ACPI Support Library
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Base.h>
+#include <Uefi.h>
+#include <PiDxe.h>
+#include <Library/BaseLib.h>
+#include <Library/IoLib.h>
+#include <Library/BoardAcpiEnableLib.h>
+#include <Library/MultiBoardAcpiSupportLib.h>
+#include <Library/PcdLib.h>
+#include <Library/DebugLib.h>
+
+#include <PlatformBoardId.h>
+
+EFI_STATUS
+EFIAPI
+BoardEnableAcpi (
+ IN BOOLEAN EnableSci
+ );
+
+EFI_STATUS
+EFIAPI
+BoardDisableAcpi (
+ IN BOOLEAN DisableSci
+ );
+
+EFI_STATUS
+EFIAPI
+SiliconEnableAcpi (
+ IN BOOLEAN EnableSci
+ );
+
+EFI_STATUS
+EFIAPI
+SiliconDisableAcpi (
+ IN BOOLEAN DisableSci
+ );
+
+EFI_STATUS
+EFIAPI
+MultiBoardEnableAcpi (
+ IN BOOLEAN EnableSci
+ )
+{
+ SiliconEnableAcpi (EnableSci);
+ return BoardEnableAcpi (EnableSci);
+}
+
+EFI_STATUS
+EFIAPI
+MultiBoardDisableAcpi (
+ IN BOOLEAN DisableSci
+ )
+{
+ SiliconDisableAcpi (DisableSci);
+ return BoardDisableAcpi (DisableSci);
+}
+
+BOARD_ACPI_ENABLE_FUNC mBoardAcpiEnableFunc = {
+ MultiBoardEnableAcpi,
+ MultiBoardDisableAcpi,
+};
+
+/**
+ The constructor function to register mBoardAcpiEnableFunc function.
+
+ @param[in] ImageHandle The firmware allocated handle for the EFI image.
+ @param[in] SystemTable A pointer to the EFI System Table.
+
+ @retval EFI_SUCCESS This constructor always return EFI_SUCCESS.
+ It will ASSERT on errors.
+**/
+EFI_STATUS
+EFIAPI
+SmmMultiBoardAcpiSupportLibConstructor (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ DEBUG ((DEBUG_INFO, "SKU_ID: 0x%x\n", LibPcdGetSku()));
+ return RegisterBoardAcpiEnableFunc (&mBoardAcpiEnableFunc);
+}
+
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/SmmMultiBoardAcpiSupportLib/SmmMultiBoardAcpiSupportLib.inf b/Platform/Intel/AlderlakeOpenBoardPkg/SmmMultiBoardAcpiSupportLib/SmmMultiBoardAcpiSupportLib.inf
new file mode 100644
index 0000000000..ecea111b41
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/SmmMultiBoardAcpiSupportLib/SmmMultiBoardAcpiSupportLib.inf
@@ -0,0 +1,40 @@
+### @file
+# SMM Multi-Board ACPI Support Library
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+###
+
+[Defines]
+ INF_VERSION = 0x00010017
+ BASE_NAME = SmmMultiBoardAcpiSupportLib
+ FILE_GUID = 8929A54E-7ED8-4AB3-BEBB-C0367BDBBFF5
+ VERSION_STRING = 1.0
+ MODULE_TYPE = DXE_SMM_DRIVER
+ LIBRARY_CLASS = NULL
+ CONSTRUCTOR = SmmMultiBoardAcpiSupportLibConstructor
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = IA32 X64 IPF EBC
+#
+
+[LibraryClasses]
+ BaseLib
+ IoLib
+ PciLib
+ PchCycleDecodingLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ MinPlatformPkg/MinPlatformPkg.dec
+ AlderlakeOpenBoardPkg/OpenBoardPkg.dec
+ AlderlakeSiliconPkg/SiPkg.dec
+
+[Sources]
+ SmmAcpiEnableLib.c
+ SmmSiliconAcpiEnableLib.c
+ SmmMultiBoardAcpiSupportLib.c
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/SmmMultiBoardAcpiSupportLib/SmmSiliconAcpiEnableLib.c b/Platform/Intel/AlderlakeOpenBoardPkg/SmmMultiBoardAcpiSupportLib/SmmSiliconAcpiEnableLib.c
new file mode 100644
index 0000000000..38390305c4
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/SmmMultiBoardAcpiSupportLib/SmmSiliconAcpiEnableLib.c
@@ -0,0 +1,157 @@
+/** @file
+ SMM Silicon ACPI Support Library
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Base.h>
+#include <Uefi.h>
+#include <PiDxe.h>
+#include <Library/BaseLib.h>
+#include <Library/SmmServicesTableLib.h>
+#include <Library/IoLib.h>
+#include <Library/BoardAcpiEnableLib.h>
+#include <Library/PcdLib.h>
+#include <Library/DebugLib.h>
+#include <Library/PciSegmentLib.h>
+#include <Library/PchCycleDecodingLib.h>
+#include <Library/PmcLib.h>
+#include <Register/PchRegs.h>
+#include <Register/PchRegsLpc.h>
+#include <Register/PmcRegs.h>
+#include <Register/RtcRegs.h>
+#include <Library/PchPciBdfLib.h>
+
+//
+// Global variables
+//
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_SMM_SYSTEM_TABLE2 *mSmst;
+
+GLOBAL_REMOVE_IF_UNREFERENCED UINT16 mAcpiBaseAddr;
+
+/**
+
+**/
+EFI_STATUS
+EFIAPI
+SiliconEnableAcpi (
+ IN BOOLEAN EnableSci
+ )
+{
+ UINT32 OutputValue;
+ UINT32 SmiEn;
+ UINT32 SmiSts;
+ UINT32 ULKMC;
+ UINT32 Pm1Cnt;
+ EFI_STATUS Status;
+ UINT64 LpcBaseAddress;
+
+ LpcBaseAddress = LpcPciCfgBase ();
+
+ //
+ // Initialize global variables
+ //
+ mSmst = gSmst;
+
+ //
+ // Get the ACPI Base Address
+ //
+ mAcpiBaseAddr = PmcGetAcpiBase ();
+
+ Status = EFI_SUCCESS;
+ //
+ // BIOS must also ensure that CF9GR is cleared and locked before handing control to the
+ // OS in order to prevent the host from issuing global resets and resetting ME
+ //
+ // EDK2: To match PCCG current BIOS behavior, do not lock CF9 Global Reset
+ // MmioWrite32 (
+ // PmcBaseAddress + R_PCH_PMC_ETR3),
+ // PmInit);
+
+ //
+ // Clear Port 80h
+ //
+ OutputValue = 0;
+ mSmst->SmmIo.Io.Write (&mSmst->SmmIo, SMM_IO_UINT16, 0x80, 1, &OutputValue);
+ //
+ // Disable SW SMI Timer and clean the status
+ //
+ mSmst->SmmIo.Io.Read (&mSmst->SmmIo, SMM_IO_UINT32, mAcpiBaseAddr + R_ACPI_IO_SMI_EN, 1, &SmiEn);
+ SmiEn &= ~(B_ACPI_IO_SMI_EN_LEGACY_USB2 | B_ACPI_IO_SMI_EN_SWSMI_TMR | B_ACPI_IO_SMI_EN_LEGACY_USB);
+ mSmst->SmmIo.Io.Write (&mSmst->SmmIo, SMM_IO_UINT32, mAcpiBaseAddr + R_ACPI_IO_SMI_EN, 1, &SmiEn);
+
+ mSmst->SmmIo.Io.Read (&mSmst->SmmIo, SMM_IO_UINT32, mAcpiBaseAddr + R_ACPI_IO_SMI_STS, 1, &SmiSts);
+ SmiSts |= B_ACPI_IO_SMI_EN_LEGACY_USB2 | B_ACPI_IO_SMI_EN_SWSMI_TMR | B_ACPI_IO_SMI_EN_LEGACY_USB;
+ mSmst->SmmIo.Io.Write (&mSmst->SmmIo, SMM_IO_UINT32, mAcpiBaseAddr + R_ACPI_IO_SMI_STS, 1, &SmiSts);
+
+ //
+ // Disable port 60/64 SMI trap if they are enabled
+ //
+ ULKMC = PciSegmentRead32 (LpcBaseAddress + R_LPC_CFG_ULKMC);
+ ULKMC &= ~(B_LPC_CFG_ULKMC_60REN | B_LPC_CFG_ULKMC_60WEN | B_LPC_CFG_ULKMC_64REN | B_LPC_CFG_ULKMC_64WEN | B_LPC_CFG_ULKMC_A20PASSEN);
+ PciSegmentWrite32 (LpcBaseAddress + R_LPC_CFG_ULKMC, ULKMC);
+
+ //
+ // Disable PM sources except power button
+ //
+ OutputValue = B_ACPI_IO_PM1_EN_PWRBTN;
+ mSmst->SmmIo.Io.Write (&mSmst->SmmIo, SMM_IO_UINT16, mAcpiBaseAddr + R_ACPI_IO_PM1_EN, 1, &OutputValue);
+ //
+ // Clear PM status except Power Button status for RapidStart Resume
+ //
+ // OutputValue = 0xFFFF;
+ OutputValue = 0xFEFF;
+ mSmst->SmmIo.Io.Write (&mSmst->SmmIo, SMM_IO_UINT16, mAcpiBaseAddr + R_ACPI_IO_PM1_STS, 1, &OutputValue);
+
+ //
+ // Guarantee day-of-month alarm is invalid (ACPI 1.0 section 4.7.2.4)
+ //
+ OutputValue = R_RTC_IO_REGD;
+ mSmst->SmmIo.Io.Write (&mSmst->SmmIo, SMM_IO_UINT8, R_RTC_IO_INDEX_ALT, 1, &OutputValue);
+ OutputValue = 0x0;
+ mSmst->SmmIo.Io.Write (&mSmst->SmmIo, SMM_IO_UINT8, R_RTC_IO_TARGET_ALT, 1, &OutputValue);
+
+ //
+ // Enable SCI
+ //
+ if (EnableSci) {
+ mSmst->SmmIo.Io.Read (&mSmst->SmmIo, SMM_IO_UINT32, mAcpiBaseAddr + R_ACPI_IO_PM1_CNT, 1, &Pm1Cnt);
+ Pm1Cnt |= B_ACPI_IO_PM1_CNT_SCI_EN;
+ mSmst->SmmIo.Io.Write (&mSmst->SmmIo, SMM_IO_UINT32, mAcpiBaseAddr + R_ACPI_IO_PM1_CNT, 1, &Pm1Cnt);
+ }
+
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+EFIAPI
+SiliconDisableAcpi (
+ IN BOOLEAN DisableSci
+ )
+{
+ UINT32 Pm1Cnt;
+
+ //
+ // Initialize global variables
+ //
+ mSmst = gSmst;
+
+ //
+ // Get the ACPI Base Address
+ //
+ mAcpiBaseAddr = PmcGetAcpiBase ();
+
+
+ //
+ // Disable SCI
+ //
+ if (DisableSci) {
+ mSmst->SmmIo.Io.Read (&mSmst->SmmIo, SMM_IO_UINT32, mAcpiBaseAddr + R_ACPI_IO_PM1_CNT, 1, &Pm1Cnt);
+ Pm1Cnt &= ~B_ACPI_IO_PM1_CNT_SCI_EN;
+ mSmst->SmmIo.Io.Write (&mSmst->SmmIo, SMM_IO_UINT32, mAcpiBaseAddr + R_ACPI_IO_PM1_CNT, 1, &Pm1Cnt);
+ }
+
+ return EFI_SUCCESS;
+}
--
2.36.1.windows.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 3/6] AlderlakeOpenBoardPkg/AlderlakePRvp: Add library instances
[not found] <cover.1686770061.git.saloni.kasbekar@intel.com>
2023-06-14 19:17 ` [PATCH 1/6] AlderlakeOpenBoardPkg: Add package and headers Saloni Kasbekar
2023-06-14 19:17 ` [PATCH 2/6] AlderlakeOpenBoardPkg: Add modules Saloni Kasbekar
@ 2023-06-14 19:17 ` Saloni Kasbekar
2023-06-14 19:17 ` [PATCH 4/6] AlderlakeOpenBoardPkg: Add ACPI module Saloni Kasbekar
` (2 subsequent siblings)
5 siblings, 0 replies; 6+ messages in thread
From: Saloni Kasbekar @ 2023-06-14 19:17 UTC (permalink / raw)
To: devel
Cc: Saloni Kasbekar, Sai Chaganty, Nate DeSimone, Isaac Oram,
Rosen Chuang
Adds the following library instances:
* AlderlakePRvp/Library/BoardAcpiLib
* AlderlakePRvp/Library/BoardInitLib
Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Isaac Oram <isaac.w.oram@intel.com>
Cc: Rosen Chuang <rosen.chuang@intel.com>
Signed-off-by: Saloni Kasbekar <saloni.kasbekar@intel.com>
---
.../Library/BoardAcpiLib/BaseAcpiTableLib.c | 30 ++
.../BaseMultiBoardAcpiSupportLib.c | 53 ++++
.../BaseMultiBoardAcpiSupportLib.inf | 43 +++
.../Library/BoardInitLib/Dxe/DxeInitLib.c | 164 +++++++++++
.../BoardInitLib/Dxe/DxeMultiBoardInitLib.c | 65 +++++
.../BoardInitLib/Dxe/DxeMultiBoardInitlib.inf | 91 ++++++
.../BoardInitLib/Pei/BoardPchInitPreMemLib.c | 131 +++++++++
.../BoardInitLib/Pei/BoardSaConfigPreMem.h | 81 ++++++
.../BoardInitLib/Pei/BoardSaInitPreMemLib.c | 244 ++++++++++++++++
.../BoardInitLib/Pei/GpioTableAdlPPostMem.h | 25 ++
.../Library/BoardInitLib/Pei/PeiDetect.c | 63 +++++
.../BoardInitLib/Pei/PeiInitPostMemLib.c | 245 ++++++++++++++++
.../BoardInitLib/Pei/PeiInitPreMemLib.c | 261 ++++++++++++++++++
.../Pei/PeiMultiBoardInitPostMemLib.c | 50 ++++
.../Pei/PeiMultiBoardInitPostMemLib.inf | 111 ++++++++
.../Pei/PeiMultiBoardInitPreMemLib.c | 88 ++++++
.../Pei/PeiMultiBoardInitPreMemLib.inf | 210 ++++++++++++++
17 files changed, 1955 insertions(+)
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardAcpiLib/BaseAcpiTableLib.c
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardAcpiLib/BaseMultiBoardAcpiSupportLib.c
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardAcpiLib/BaseMultiBoardAcpiSupportLib.inf
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Dxe/DxeInitLib.c
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Dxe/DxeMultiBoardInitLib.c
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Dxe/DxeMultiBoardInitlib.inf
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/BoardPchInitPreMemLib.c
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/BoardSaConfigPreMem.h
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/BoardSaInitPreMemLib.c
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/GpioTableAdlPPostMem.h
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/PeiDetect.c
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/PeiInitPostMemLib.c
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/PeiInitPreMemLib.c
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/PeiMultiBoardInitPostMemLib.c
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/PeiMultiBoardInitPostMemLib.inf
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/PeiMultiBoardInitPreMemLib.c
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/PeiMultiBoardInitPreMemLib.inf
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardAcpiLib/BaseAcpiTableLib.c b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardAcpiLib/BaseAcpiTableLib.c
new file mode 100644
index 0000000000..c8154b84c7
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardAcpiLib/BaseAcpiTableLib.c
@@ -0,0 +1,30 @@
+/** @file
+ Board ACPI Table Library
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Base.h>
+#include <Uefi.h>
+#include <Library/BoardAcpiTableLib.h>
+
+/**
+ Update ACPI Table
+
+ @param[in, out] Table Pointer to table, need to be update in Acpi table.
+ @param[in, out] Version ACPI table version
+
+ @retval EFI_SUCCESS The function always return successfully.
+**/
+EFI_STATUS
+EFIAPI
+AdlPBoardUpdateAcpiTable (
+ IN OUT EFI_ACPI_COMMON_HEADER *Table,
+ IN OUT EFI_ACPI_TABLE_VERSION *Version
+ )
+{
+ return EFI_SUCCESS;
+}
+
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardAcpiLib/BaseMultiBoardAcpiSupportLib.c b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardAcpiLib/BaseMultiBoardAcpiSupportLib.c
new file mode 100644
index 0000000000..c78bee4b0a
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardAcpiLib/BaseMultiBoardAcpiSupportLib.c
@@ -0,0 +1,53 @@
+/** @file
+ Multi-Board ACPI Support Library
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Base.h>
+#include <Uefi.h>
+#include <PiDxe.h>
+#include <Library/BaseLib.h>
+#include <Library/IoLib.h>
+#include <Library/BoardAcpiTableLib.h>
+#include <Library/MultiBoardAcpiSupportLib.h>
+#include <Library/PcdLib.h>
+#include <Library/DebugLib.h>
+
+#include <PlatformBoardId.h>
+
+EFI_STATUS
+EFIAPI
+AdlPBoardUpdateAcpiTable (
+ IN OUT EFI_ACPI_COMMON_HEADER *Table,
+ IN OUT EFI_ACPI_TABLE_VERSION *Version
+ );
+
+BOARD_ACPI_TABLE_FUNC mAdlPBoardAcpiTableFunc = {
+ AdlPBoardUpdateAcpiTable
+};
+
+/**
+ The constructor function to register mAdlPBoardAcpiTableFunc function.
+
+ @retval EFI_SUCCESS This constructor always return EFI_SUCCESS.
+ It will ASSERT on errors.
+**/
+EFI_STATUS
+EFIAPI
+AdlPBaseMultiBoardAcpiSupportLibConstructor (
+ VOID
+ )
+{
+ UINT8 SkuType;
+ SkuType = PcdGet8 (PcdSkuType);
+
+ if (SkuType==AdlPSkuType) {
+ DEBUG ((DEBUG_INFO, "SKU_ID: 0x%x\n", LibPcdGetSku()));
+ return RegisterBoardAcpiTableFunc (&mAdlPBoardAcpiTableFunc);
+ }
+ return EFI_SUCCESS;
+}
+
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardAcpiLib/BaseMultiBoardAcpiSupportLib.inf b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardAcpiLib/BaseMultiBoardAcpiSupportLib.inf
new file mode 100644
index 0000000000..6289b23a96
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardAcpiLib/BaseMultiBoardAcpiSupportLib.inf
@@ -0,0 +1,43 @@
+### @file
+# Multi-Board ACPI Support Library
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+###
+
+[Defines]
+ INF_VERSION = 0x00010017
+ BASE_NAME = AdlPBaseMultiBoardAcpiTableLib
+ FILE_GUID = 8E6A3B38-53E0-48C0-970F-058F380FCB80
+ VERSION_STRING = 1.0
+ MODULE_TYPE = BASE
+ LIBRARY_CLASS = NULL
+ CONSTRUCTOR = AdlPBaseMultiBoardAcpiSupportLibConstructor
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = IA32 X64 IPF EBC
+#
+
+[LibraryClasses]
+ BaseLib
+ IoLib
+ PciLib
+ AslUpdateLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ MinPlatformPkg/MinPlatformPkg.dec
+ AlderlakeOpenBoardPkg/OpenBoardPkg.dec
+ AlderlakeSiliconPkg/SiPkg.dec
+ IntelSiliconPkg/IntelSiliconPkg.dec
+
+[Sources]
+ BaseAcpiTableLib.c
+ BaseMultiBoardAcpiSupportLib.c
+
+[Pcd]
+ gBoardModuleTokenSpaceGuid.PcdSkuType
\ No newline at end of file
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Dxe/DxeInitLib.c b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Dxe/DxeInitLib.c
new file mode 100644
index 0000000000..dfc2f51979
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Dxe/DxeInitLib.c
@@ -0,0 +1,164 @@
+/** @file
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Uefi.h>
+
+#include <Library/HobLib.h>
+#include <Library/PcdLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <MemInfoHob.h>
+#include <PlatformBoardConfig.h>
+#include <PlatformBoardId.h>
+#include <Pins/GpioPinsVer2Lp.h>
+#include <Register/PchRegs.h>
+#include <Library/PciSegmentLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/BoardConfigLib.h>
+#include <Library/DebugLib.h>
+
+VOID
+AdlPInitCommonPlatformPcd (
+ VOID
+ )
+{
+
+ PcdSetBoolS (PcdPssReadSN, TRUE);
+ PcdSet8S (PcdPssI2cSlaveAddress, 0x6E);
+ PcdSet8S (PcdPssI2cBusNumber, 0x05);
+ PcdSetBoolS (PcdSpdAddressOverride, FALSE);
+
+}
+
+VOID
+AdlPUpdateDimmPopulation (
+ VOID
+ )
+{
+ MEMORY_INFO_DATA_HOB *MemInfo;
+ UINT8 Slot0;
+ UINT8 Slot1;
+ UINT8 Slot2;
+ UINT8 Slot3;
+ CONTROLLER_INFO *ControllerInfo;
+ EFI_HOB_GUID_TYPE *GuidHob;
+
+ GuidHob = NULL;
+ MemInfo = NULL;
+ GuidHob = GetFirstGuidHob (&gSiMemoryInfoDataGuid);
+ ASSERT (GuidHob != NULL);
+ if (GuidHob != NULL) {
+ MemInfo = (MEMORY_INFO_DATA_HOB *) GET_GUID_HOB_DATA (GuidHob);
+ }
+ if (MemInfo != NULL) {
+ if ( PcdGet8 (PcdPlatformFlavor) == FlavorDesktop ||
+ PcdGet8 (PcdPlatformFlavor) == FlavorUpServer ||
+ PcdGet8 (PcdPlatformFlavor) == FlavorWorkstation
+ ) {
+ ControllerInfo = &MemInfo->Controller[0];
+ Slot0 = ControllerInfo->ChannelInfo[0].DimmInfo[0].Status;
+ Slot1 = ControllerInfo->ChannelInfo[0].DimmInfo[1].Status;
+ Slot2 = ControllerInfo->ChannelInfo[1].DimmInfo[0].Status;
+ Slot3 = ControllerInfo->ChannelInfo[1].DimmInfo[1].Status;
+
+ //
+ // Channel 0 Channel 1
+ // Slot0 Slot1 Slot0 Slot1 - Population AIO board
+ // 0 0 0 0 - Invalid - Invalid
+ // 0 0 0 1 - Valid - Invalid
+ // 0 0 1 0 - Invalid - Valid
+ // 0 0 1 1 - Valid - Valid
+ // 0 1 0 0 - Valid - Invalid
+ // 0 1 0 1 - Valid - Invalid
+ // 0 1 1 0 - Invalid - Invalid
+ // 0 1 1 1 - Valid - Invalid
+ // 1 0 0 0 - Invalid - Valid
+ // 1 0 0 1 - Invalid - Invalid
+ // 1 0 1 0 - Invalid - Valid
+ // 1 0 1 1 - Invalid - Valid
+ // 1 1 0 0 - Valid - Valid
+ // 1 1 0 1 - Valid - Invalid
+ // 1 1 1 0 - Invalid - Valid
+ // 1 1 1 1 - Valid - Valid
+ //
+ if ((Slot0 && (Slot1 == 0)) || (Slot2 && (Slot3 == 0))) {
+ PcdSetBoolS (PcdDimmPopulationError, TRUE);
+ }
+ }
+ }
+}
+
+/**
+ Enable Tier2 GPIO Sci wake capability.
+
+ @retval EFI_SUCCESS The function completed successfully.
+**/
+EFI_STATUS
+AdlPTier2GpioWakeSupport (
+ VOID
+ )
+{
+ BOOLEAN Tier2GpioWakeEnable;
+
+ Tier2GpioWakeEnable = FALSE;
+ PcdSetBoolS (PcdGpioTier2WakeEnable, Tier2GpioWakeEnable);
+
+ return EFI_SUCCESS;
+}
+
+
+/**
+ A hook for board-specific initialization after PCI enumeration.
+
+ @retval EFI_SUCCESS The board initialization was successful.
+**/
+EFI_STATUS
+EFIAPI
+AdlPBoardInitAfterPciEnumeration (
+ VOID
+ )
+{
+ DEBUG ((DEBUG_INFO, "AdlPBoardInitAfterPciEnumeration\n"));
+
+ AdlPTier2GpioWakeSupport ();
+ AdlPInitCommonPlatformPcd ();
+
+ return EFI_SUCCESS;
+}
+
+/**
+ A hook for board-specific functionality for the ReadyToBoot event.
+
+ @retval EFI_SUCCESS The board initialization was successful.
+**/
+EFI_STATUS
+EFIAPI
+AdlPBoardInitReadyToBoot (
+ VOID
+ )
+{
+ DEBUG ((DEBUG_INFO, "AdlPBoardInitReadyToBoot\n"));
+
+ AdlPUpdateDimmPopulation ();
+
+ return EFI_SUCCESS;
+}
+
+/**
+ A hook for board-specific functionality for the ExitBootServices event.
+
+ @retval EFI_SUCCESS The board initialization was successful.
+**/
+EFI_STATUS
+EFIAPI
+AdlPBoardInitEndOfFirmware (
+ VOID
+ )
+{
+ DEBUG ((DEBUG_INFO, "AdlPBoardInitEndOfFirmware\n"));
+
+ return EFI_SUCCESS;
+}
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Dxe/DxeMultiBoardInitLib.c b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Dxe/DxeMultiBoardInitLib.c
new file mode 100644
index 0000000000..0cdf405502
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Dxe/DxeMultiBoardInitLib.c
@@ -0,0 +1,65 @@
+/** @file
+ DXE Multi-Board Initilialization Library
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+@par Specification Reference:
+**/
+
+#include <Uefi.h>
+#include <Library/BaseLib.h>
+#include <Library/DebugLib.h>
+#include <Library/MultiBoardInitSupportLib.h>
+#include <PlatformBoardId.h>
+#include <Library/PcdLib.h>
+
+EFI_STATUS
+EFIAPI
+AdlPBoardInitAfterPciEnumeration (
+ VOID
+ );
+
+EFI_STATUS
+EFIAPI
+AdlPBoardInitReadyToBoot (
+ VOID
+ );
+
+EFI_STATUS
+EFIAPI
+AdlPBoardInitEndOfFirmware (
+ VOID
+ );
+
+BOARD_NOTIFICATION_INIT_FUNC mAdlPBoardDxeInitFunc = {
+ AdlPBoardInitAfterPciEnumeration,
+ AdlPBoardInitReadyToBoot,
+ AdlPBoardInitEndOfFirmware
+};
+
+/**
+ The constructor determines which board init functions should be registered.
+
+ @param ImageHandle The firmware allocated handle for the EFI image.
+ @param SystemTable A pointer to the EFI System Table.
+
+ @retval EFI_SUCCESS The constructor always returns EFI_SUCCESS.
+
+**/
+EFI_STATUS
+EFIAPI
+DxeAdlPMultiBoardInitLibConstructor (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ UINT8 SkuType;
+ SkuType = PcdGet8 (PcdSkuType);
+
+ if (SkuType==AdlPSkuType) {
+ DEBUG ((DEBUG_INFO, "SKU_ID: 0x%x\n", LibPcdGetSku()));
+ return RegisterBoardNotificationInit (&mAdlPBoardDxeInitFunc);
+ }
+ return EFI_SUCCESS;
+}
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Dxe/DxeMultiBoardInitlib.inf b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Dxe/DxeMultiBoardInitlib.inf
new file mode 100644
index 0000000000..ead75eb91d
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Dxe/DxeMultiBoardInitlib.inf
@@ -0,0 +1,91 @@
+## @file
+# Component information file for Alderlake Multi-Board Initialization in DXE phase.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+###
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = DxeAdlPMultiBoardInitLib
+ FILE_GUID = E7D21F79-1126-4B45-987C-41FF30AC0EC2
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = NULL
+ CONSTRUCTOR = DxeAdlPMultiBoardInitLibConstructor
+
+[LibraryClasses]
+ BaseLib
+ DebugLib
+ PcdLib
+ BaseMemoryLib
+ MemoryAllocationLib
+ HobLib
+ UefiBootServicesTableLib
+ UefiRuntimeServicesTableLib
+ PchPcieRpLib
+ PciSegmentLib
+
+[Packages]
+ MinPlatformPkg/MinPlatformPkg.dec
+ AlderlakeOpenBoardPkg/OpenBoardPkg.dec
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ AlderlakeSiliconPkg/SiPkg.dec
+
+[Sources]
+ DxeInitLib.c
+ DxeMultiBoardInitLib.c
+
+[Protocols]
+
+[Guids]
+ gSiMemoryInfoDataGuid ## CONSUMES
+
+[Pcd]
+ # Board Init Table List
+ gBoardModuleTokenSpaceGuid.PcdXhciAcpiTableSignature
+ gBoardModuleTokenSpaceGuid.PcdPreferredPmProfile
+
+ gBoardModuleTokenSpaceGuid.PcdBoardRtd3TableSignature
+
+ gBoardModuleTokenSpaceGuid.PcdSpdAddressOverride
+
+ gBoardModuleTokenSpaceGuid.PcdBatteryPresent
+ gBoardModuleTokenSpaceGuid.PcdRealBattery1Control
+ gBoardModuleTokenSpaceGuid.PcdRealBattery2Control
+
+ gBoardModuleTokenSpaceGuid.PcdH8S2113SIO
+ gBoardModuleTokenSpaceGuid.PcdNCT6776FCOM
+ gBoardModuleTokenSpaceGuid.PcdNCT6776FSIO
+ gBoardModuleTokenSpaceGuid.PcdNCT6776FHWMON
+
+ gBoardModuleTokenSpaceGuid.PcdSmcRuntimeSciPin
+
+ gBoardModuleTokenSpaceGuid.PcdVirtualButtonVolumeUpSupport
+ gBoardModuleTokenSpaceGuid.PcdVirtualButtonVolumeDownSupport
+ gBoardModuleTokenSpaceGuid.PcdVirtualButtonHomeButtonSupport
+ gBoardModuleTokenSpaceGuid.PcdVirtualButtonRotationLockSupport
+
+ gBoardModuleTokenSpaceGuid.PcdSlateModeSwitchSupport
+ gBoardModuleTokenSpaceGuid.PcdVirtualGpioButtonSupport
+ gBoardModuleTokenSpaceGuid.PcdPmPowerButtonGpioPin
+ gBoardModuleTokenSpaceGuid.PcdAcpiEnableAllButtonSupport
+ gBoardModuleTokenSpaceGuid.PcdAcpiHidDriverButtonSupport
+
+ gBoardModuleTokenSpaceGuid.PcdPlatformFlavor ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdBoardId ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdBoardBomId
+ gBoardModuleTokenSpaceGuid.PcdSkuType
+
+ gBoardModuleTokenSpaceGuid.PcdGpioTier2WakeEnable ## PRODUCES
+
+ gBoardModuleTokenSpaceGuid.PcdPssReadSN
+ gBoardModuleTokenSpaceGuid.PcdPssI2cBusNumber
+ gBoardModuleTokenSpaceGuid.PcdPssI2cSlaveAddress
+
+ gBoardModuleTokenSpaceGuid.PcdGpioTier2WakeEnable
+ gBoardModuleTokenSpaceGuid.PcdDimmPopulationError
+
+ gSiPkgTokenSpaceGuid.PcdAdlSSupport ## CONSUMES
\ No newline at end of file
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/BoardPchInitPreMemLib.c b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/BoardPchInitPreMemLib.c
new file mode 100644
index 0000000000..753b686de5
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/BoardPchInitPreMemLib.c
@@ -0,0 +1,131 @@
+/** @file
+ Source code for the board PCH configuration Pcd init functions for Pre-Memory Init phase.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Uefi.h>
+#include <Library/BaseLib.h>
+#include <Library/PcdLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BoardConfigLib.h>
+#include <Include/PlatformBoardId.h>
+#include <PlatformBoardConfig.h>
+#include <Library/PcdLib.h>
+#include <PlatformBoardId.h>
+#include <Library/PchInfoLib.h>
+/**
+ Board Root Port Clock Info configuration init function for PEI pre-memory phase.
+
+ @retval EFI_SUCCESS The function completed successfully.
+**/
+EFI_STATUS
+AdlPRootPortClkInfoInit (
+ VOID
+ )
+{
+ PCD64_BLOB Clock[PCH_MAX_PCIE_CLOCKS];
+ UINT32 Index;
+ PCIE_CLOCKS_USAGE *PcieClocks;
+
+ PcieClocks = NULL;
+
+ //
+ //The default clock assignment will be NOT_USED, which corresponds to PchClockUsageNotUsed. This will prevent clocks drawing Power by default.
+ //If Platform code doesn't contain port-clock map for a given board, the clocks will be NOT_USED, preventing PCIe devices not to operate.
+ //To prevent this, remember to provide port-clock map for every board.
+ //
+ for (Index = 0; Index < PCH_MAX_PCIE_CLOCKS; Index++) {
+ Clock[Index].PcieClock.ClkReqSupported = TRUE;
+ Clock[Index].PcieClock.ClockUsage = NOT_USED;
+ }
+
+ ///
+ /// Assign ClkReq signal to root port. (Base 0)
+ /// For LP, Set 0 - 5
+ /// For H, Set 0 - 15
+ /// Note that if GbE is enabled, ClkReq assigned to GbE will not be available for Root Port.
+ ///
+
+ PcieClocks = PcdGetPtr(VpdPcdPcieClkUsageMap);
+ if (PcieClocks == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ Clock[0].PcieClock.ClockUsage = PcieClocks->ClockUsage[0];
+ Clock[1].PcieClock.ClockUsage = PcieClocks->ClockUsage[1];
+ Clock[2].PcieClock.ClockUsage = PcieClocks->ClockUsage[2];
+ Clock[3].PcieClock.ClockUsage = PcieClocks->ClockUsage[3];
+ Clock[4].PcieClock.ClockUsage = PcieClocks->ClockUsage[4];
+ Clock[5].PcieClock.ClockUsage = PcieClocks->ClockUsage[5];
+ Clock[6].PcieClock.ClockUsage = PcieClocks->ClockUsage[6];
+ Clock[7].PcieClock.ClockUsage = PcieClocks->ClockUsage[7];
+ Clock[8].PcieClock.ClockUsage = PcieClocks->ClockUsage[8];
+ Clock[9].PcieClock.ClockUsage = PcieClocks->ClockUsage[9];
+
+ PcdSet64S (PcdPcieClock0, Clock[ 0].Blob); // @todo Those individual PCDs should probably be replaced with something like a VOID* that can be iterated over
+ PcdSet64S (PcdPcieClock1, Clock[ 1].Blob); // @todo Those individual PCDs should probably be replaced with something like a VOID* that can be iterated over
+ PcdSet64S (PcdPcieClock2, Clock[ 2].Blob); // @todo Those individual PCDs should probably be replaced with something like a VOID* that can be iterated over
+ PcdSet64S (PcdPcieClock3, Clock[ 3].Blob); // @todo Those individual PCDs should probably be replaced with something like a VOID* that can be iterated over
+ PcdSet64S (PcdPcieClock4, Clock[ 4].Blob); // @todo Those individual PCDs should probably be replaced with something like a VOID* that can be iterated over
+ PcdSet64S (PcdPcieClock5, Clock[ 5].Blob); // @todo Those individual PCDs should probably be replaced with something like a VOID* that can be iterated over
+ PcdSet64S (PcdPcieClock6, Clock[ 6].Blob); // @todo Those individual PCDs should probably be replaced with something like a VOID* that can be iterated over
+ PcdSet64S (PcdPcieClock7, Clock[ 7].Blob); // @todo Those individual PCDs should probably be replaced with something like a VOID* that can be iterated over
+ PcdSet64S (PcdPcieClock8, Clock[ 8].Blob); // @todo Those individual PCDs should probably be replaced with something like a VOID* that can be iterated over
+ PcdSet64S (PcdPcieClock9, Clock[ 9].Blob); // @todo Those individual PCDs should probably be replaced with something like a VOID* that can be iterated over
+ PcdSet64S (PcdPcieClock10, Clock[10].Blob); // @todo Those individual PCDs should probably be replaced with something like a VOID* that can be iterated over
+ PcdSet64S (PcdPcieClock11, Clock[11].Blob); // @todo Those individual PCDs should probably be replaced with something like a VOID* that can be iterated over
+ PcdSet64S (PcdPcieClock12, Clock[12].Blob); // @todo Those individual PCDs should probably be replaced with something like a VOID* that can be iterated over
+ PcdSet64S (PcdPcieClock13, Clock[13].Blob); // @todo Those individual PCDs should probably be replaced with something like a VOID* that can be iterated over
+ PcdSet64S (PcdPcieClock14, Clock[14].Blob); // @todo Those individual PCDs should probably be replaced with something like a VOID* that can be iterated over
+ PcdSet64S (PcdPcieClock15, Clock[15].Blob); // @todo Those individual PCDs should probably be replaced with something like a VOID* that can be iterated over
+ return EFI_SUCCESS;
+}
+
+/**
+ Board USB related configuration init function for PEI pre-memory phase.
+
+ @param[in] VOID
+
+ @retval EFI_SUCCESS The function completed successfully.
+**/
+EFI_STATUS
+AdlPUsbConfigInit (
+ VOID
+ )
+{
+ USB_OC_MAP_TABLE *Usb2OcMappingTable;
+ USB_OC_MAP_TABLE *Usb3OcMappingTable;
+
+ //
+ // USB Port Over Current Pin
+ //
+ Usb2OcMappingTable = PcdGetPtr(VpdPcdUSB2OCMap);
+ Usb3OcMappingTable = PcdGetPtr(VpdPcdUSB3OCMap);
+
+ PcdSet32S (PcdUsb2OverCurrentPinTable, (UINT32) Usb2OcMappingTable);
+ PcdSet32S (PcdUsb3OverCurrentPinTable, (UINT32) Usb3OcMappingTable);
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Board GPIO Group Tier configuration init function for PEI pre-memory phase.
+**/
+VOID
+AdlPGpioGroupTierInit (
+ VOID
+ )
+{
+ //
+ // GPIO Group Tier
+ //
+ PcdSet32S (PcdGpioGroupToGpeDw0, 0);
+ PcdSet32S (PcdGpioGroupToGpeDw1, 0);
+ PcdSet32S (PcdGpioGroupToGpeDw2, 0);
+
+ return;
+}
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/BoardSaConfigPreMem.h b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/BoardSaConfigPreMem.h
new file mode 100644
index 0000000000..372897705d
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/BoardSaConfigPreMem.h
@@ -0,0 +1,81 @@
+/** @file
+ PEI Boards Configurations for PreMem phase.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _BOARD_SA_CONFIG_PRE_MEM_H_
+#define _BOARD_SA_CONFIG_PRE_MEM_H_
+
+#include <Ppi/SiPolicy.h>
+#include <Library/BoardConfigLib.h>
+
+//
+// LPDDR3 / LPDDR4 RVP boards (memory soldered down)
+// Single SPD EEPROM at 0xA2 serves both C0D0 and C1D0 (LPDDR3/4 is 1DPC only)
+//
+#define DIMM_SMB_SPD_P0C0D0_STP 0xA2
+#define DIMM_SMB_SPD_P0C0D1_STP 0xA0
+#define DIMM_SMB_SPD_P0C1D0_STP 0xA2
+#define DIMM_SMB_SPD_P0C1D1_STP 0xA0
+#define SA_MRC_MAX_RCOMP_TARGETS (5)
+
+//
+// Reference RCOMP resistors on motherboard - MRC will set automatically
+//
+GLOBAL_REMOVE_IF_UNREFERENCED const UINT16 AdlPRcompResistorZero = 0;
+
+//
+// RCOMP target values for RdOdt, WrDS, WrDSCmd, WrDSCtl, WrDSClk - MRC will set automatically
+//
+GLOBAL_REMOVE_IF_UNREFERENCED const UINT16 RcompTargetAdlP[SA_MRC_MAX_RCOMP_TARGETS] = { 0, 0, 0, 0, 0 };
+
+//
+// DQ byte mapping to CMD/CTL/CLK, from the CPU side
+//
+GLOBAL_REMOVE_IF_UNREFERENCED const UINT8 DqByteMapAdlP[2][6][2] = {
+ // Channel 0:
+ {
+ { 0x0F, 0xF0 }, // CLK0 goes to package 0 - Bytes[3:0], CLK1 goes to package 1 - Bytes[7:4]
+ { 0x0F, 0xF0 }, // Cmd CAA goes to Bytes[3:0], Cmd CAB goes to Byte[7:4]
+ { 0xFF, 0x00 }, // CTL (CS) goes to all bytes
+ { 0x00, 0x00 }, // Unused in ICL MRC
+ { 0x00, 0x00 }, // Unused in ICL MRC
+ { 0x00, 0x00 }, // Unused in ICL MRC
+ },
+ // Channel 1:
+ {
+ { 0x0F, 0xF0 }, // CLK0 goes to package 0 - Bytes[3:0], CLK1 goes to package 1 - Bytes[7:4]
+ { 0x0F, 0xF0 }, // Cmd CAA goes to Bytes[3:0], Cmd CAB goes to Byte[7:4]
+ { 0xFF, 0x00 }, // CTL (CS) goes to all bytes
+ { 0x00, 0x00 }, // Unused in ICL MRC
+ { 0x00, 0x00 }, // Unused in ICL MRC
+ { 0x00, 0x00 }, // Unused in ICL MRC
+ }
+};
+
+//
+// Display DDI settings for Adl-P Ddr5 Rvp Edp + DP
+//
+GLOBAL_REMOVE_IF_UNREFERENCED const UINT8 mAdlPDdr5RvpDisplayDdiConfig[16] = {
+ DdiPortEdp, // DDI Port A Config : DdiPortDisabled = No LFP is Connected, DdiPortEdp = eDP, DdiPortMipiDsi = MIPI DSI
+ DdiPortDisabled, // DDI Port B Config : DdiPortDisabled = No LFP is Connected, DdiPortEdp = eDP, DdiPortMipiDsi = MIPI DSI
+ DdiHpdDisable, // DDI Port A HPD : DdiHpdDisable = Disable, DdiHpdEnable = Enable HPD
+ DdiHpdEnable, // DDI Port B HPD : DdiHpdDisable = Disable, DdiHpdEnable = Enable HPD
+ DdiHpdDisable, // DDI Port C HPD : DdiHpdDisable = Disable, DdiHpdEnable = Enable HPD
+ DdiHpdDisable, // DDI Port 1 HPD : DdiHpdDisable = Disable, DdiHpdEnable = Enable HPD
+ DdiHpdDisable, // DDI Port 2 HPD : DdiHpdDisable = Disable, DdiHpdEnable = Enable HPD
+ DdiHpdDisable, // DDI Port 3 HPD : DdiHpdDisable = Disable, DdiHpdEnable = Enable HPD
+ DdiHpdDisable, // DDI Port 4 HPD : DdiHpdDisable = Disable, DdiHpdEnable = Enable HPD
+ DdiDisable, // DDI Port A DDC : DdiDisable = Disable, DdiDdcEnable = Enable DDC
+ DdiDisable, // DDI Port B DDC : DdiDisable = Disable, DdiDdcEnable = Enable DDC
+ DdiDisable, // DDI Port C DDC : DdiDisable = Disable, DdiDdcEnable = Enable DDC
+ DdiDisable, // DDI Port 1 DDC : DdiDisable = Disable, DdiDdcEnable = Enable DDC
+ DdiDisable, // DDI Port 2 DDC : DdiDisable = Disable, DdiDdcEnable = Enable DDC
+ DdiDisable, // DDI Port 3 DDC : DdiDisable = Disable, DdiDdcEnable = Enable DDC
+ DdiDisable // DDI Port 4 DDC : DdiDisable = Disable, DdiDdcEnable = Enable DDC
+};
+
+#endif // _BOARD_SA_CONFIG_PRE_MEM_H_
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/BoardSaInitPreMemLib.c b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/BoardSaInitPreMemLib.c
new file mode 100644
index 0000000000..bb1d21995e
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/BoardSaInitPreMemLib.c
@@ -0,0 +1,244 @@
+/** @file
+ Source code for the board SA configuration Pcd init functions in Pre-Memory init phase.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "BoardSaConfigPreMem.h"
+#include <Library/CpuPlatformLib.h>
+#include <Pins/GpioPinsVer2Lp.h>
+#include <PlatformBoardId.h>
+#include <PlatformBoardConfig.h>
+#include <Library/PcdLib.h>
+#include <Library/DebugLib.h>
+#include <Ppi/ReadOnlyVariable2.h>
+/**
+ MRC configuration init function for PEI pre-memory phase.
+
+ @param[in] VOID
+
+ @retval VOID
+**/
+VOID
+AdlPSaMiscConfigInit (
+ VOID
+ )
+{
+ // Type4 RVP
+ PcdSet8S (PcdSaMiscUserBd, 6); // btUlxUltType4
+ PcdSet16S (PcdSaDdrFreqLimit, 0);
+
+ return;
+}
+
+/**
+ Board Memory Init related configuration init function for PEI pre-memory phase.
+
+ @param[in] VOID
+
+ @retval VOID
+**/
+VOID
+AdlPMrcConfigInit (
+ VOID
+ )
+{
+ UINT16 BoardId;
+ BOOLEAN ExternalSpdPresent;
+ MRC_DQS *MrcDqs;
+ MRC_DQ *MrcDq;
+ SPD_DATA *SpdData;
+
+ BoardId = PcdGet16(PcdBoardId);
+
+ // SPD is the same size for all boards
+ PcdSet16S (PcdMrcSpdDataSize, 512);
+
+ ExternalSpdPresent = PcdGetBool (PcdSpdPresent);
+
+ // Assume internal SPD is used
+ PcdSet8S (PcdMrcSpdAddressTable0, 0);
+ PcdSet8S (PcdMrcSpdAddressTable1, 0);
+ PcdSet8S (PcdMrcSpdAddressTable2, 0);
+ PcdSet8S (PcdMrcSpdAddressTable3, 0);
+ PcdSet8S (PcdMrcSpdAddressTable4, 0);
+ PcdSet8S (PcdMrcSpdAddressTable5, 0);
+ PcdSet8S (PcdMrcSpdAddressTable6, 0);
+ PcdSet8S (PcdMrcSpdAddressTable7, 0);
+ PcdSet8S (PcdMrcSpdAddressTable8, 0);
+ PcdSet8S (PcdMrcSpdAddressTable9, 0);
+ PcdSet8S (PcdMrcSpdAddressTable10, 0);
+ PcdSet8S (PcdMrcSpdAddressTable11, 0);
+ PcdSet8S (PcdMrcSpdAddressTable12, 0);
+ PcdSet8S (PcdMrcSpdAddressTable13, 0);
+ PcdSet8S (PcdMrcSpdAddressTable14, 0);
+ PcdSet8S (PcdMrcSpdAddressTable15, 0);
+
+ // Check for external SPD presence
+ if (ExternalSpdPresent) {
+ switch (BoardId) {
+ case BoardIdAdlPDdr5Rvp:
+ PcdSet8S (PcdMrcSpdAddressTable0, 0xA0);
+ PcdSet8S (PcdMrcSpdAddressTable1, 0xA2);
+ PcdSet8S (PcdMrcSpdAddressTable8, 0xA4);
+ PcdSet8S (PcdMrcSpdAddressTable9, 0xA6);
+ break;
+ default:
+ break;
+ }
+ }
+
+ // Setting the default DQ Byte Map. It may be overriden to board specific settings below.
+ PcdSet32S (PcdMrcDqByteMap, (UINTN) DqByteMapAdlP);
+ PcdSet16S (PcdMrcDqByteMapSize, sizeof (DqByteMapAdlP));
+
+ // ADL uses the same RCOMP resistors for all DDR types
+ PcdSet32S (PcdMrcRcompResistor, (UINTN) AdlPRcompResistorZero);
+
+ // Use default RCOMP target values for all boards
+ PcdSet32S (PcdMrcRcompTarget, (UINTN) RcompTargetAdlP);
+
+ // Default is NIL
+ PcdSetBoolS (PcdMrcDqPinsInterleavedControl, TRUE);
+ PcdSetBoolS (PcdMrcDqPinsInterleaved, FALSE);
+
+ // DqsMapCpu2Dram is the same size for all boards
+ PcdSet16S (PcdMrcDqsMapCpu2DramSize, sizeof (MRC_DQS));
+ // DqMapCpu2Dram is the same size for all boards
+ PcdSet16S (PcdMrcDqMapCpu2DramSize, sizeof (MRC_DQ));
+ PcdSet8S (PcdMrcLp5CccConfig, 0x0);
+
+ // CPU-DRAM DQ mapping
+ MrcDq = PcdGetPtr (VpdPcdMrcDqMapCpu2Dram);
+ if (MrcDq != NULL) {
+ PcdSet32S (PcdMrcDqMapCpu2Dram, (UINTN)MrcDq->DqMapCpu2Dram);
+ }
+
+ // CPU-DRAM DQS mapping
+ MrcDqs = PcdGetPtr (VpdPcdMrcDqsMapCpu2Dram);
+ if (MrcDqs != NULL) {
+ PcdSet32S (PcdMrcDqsMapCpu2Dram, (UINTN)MrcDqs->DqsMapCpu2Dram);
+ }
+
+ // DRAM SPD Data
+ SpdData = PcdGetPtr (VpdPcdMrcSpdData);
+ if (SpdData != NULL) {
+ if (SpdData->OverrideSpd == TRUE) {
+ PcdSet32S (PcdMrcSpdData, (UINTN)SpdData->SpdData);
+ }
+ }
+
+ //
+ // CA Vref routing: board-dependent
+ // 0 - VREF_CA goes to both CH_A and CH_B (LPDDR3/DDR3L)
+ // 1 - VREF_CA to CH_A, VREF_DQ_A to CH_B (should not be used)
+ // 2 - VREF_CA to CH_A, VREF_DQ_B to CH_B (DDR4)
+ //
+ // Set it to 2 for all our DDR4 boards; it is ignored for LPDDR4
+ //
+ PcdSet8S (PcdMrcCaVrefConfig, 2);
+
+ return;
+}
+
+/**
+ Board SA related GPIO configuration init function for PEI pre-memory phase.
+
+ @param[in] VOID
+
+ @retval VOID
+**/
+VOID
+AdlPSaGpioConfigInit (
+ VOID
+ )
+{
+ UINT16 BoardId;
+ BoardId = PcdGet16(PcdBoardId);
+ //
+ // Assigning default values to PCIE RTD3 GPIOs
+ //
+ switch (BoardId) {
+ case BoardIdAdlPDdr5Rvp:
+ PcdSet8S (PcdRootPortIndex, 4);
+ PcdSet8S (PcdPcieSlot1GpioSupport, 1);
+ PcdSet8S (PcdPcieSlot1PwrEnableExpanderNo, 0);
+ //
+ // Configure CPU M.2 SSD 1 GPIO PCDs
+ //
+ PcdSetBoolS (PcdPcieSsd2PwrEnableGpioPolarity, PIN_GPIO_ACTIVE_HIGH);
+ //
+ // Configure CPU M.2 SSD 2 GPIO PCDs
+ //
+ PcdSet32S (PcdPcieSsd3PwrEnableGpioNo, GPIO_VER2_LP_GPP_C2);
+ PcdSetBoolS (PcdPcieSsd3PwrEnableGpioPolarity, PIN_GPIO_ACTIVE_HIGH);
+ break;
+ default:
+ break;
+ }
+ return;
+}
+
+/**
+ SA Display DDI configuration init function for PEI pre-memory phase.
+
+ @param[in] VOID
+
+ @retval VOID
+**/
+VOID
+AdlPSaDisplayConfigInit (
+ VOID
+ )
+{
+ UINT16 BoardId;
+ UINT16 DisplayId;
+
+ BoardId = PcdGet16 (PcdBoardId);
+ DisplayId = PcdGet16 (PcdDisplayId);
+
+ DEBUG ((DEBUG_INFO, "BoardId = 0x%x DisplayId = 0x%x\n",BoardId,DisplayId));
+
+ switch (BoardId) {
+ case BoardIdAdlPDdr5Rvp:
+ DEBUG ((DEBUG_INFO, "DDI Configuration ADLP Edp DP\n"));
+ PcdSet32S (PcdSaDisplayConfigTable, (UINTN) mAdlPDdr5RvpDisplayDdiConfig);
+ PcdSet16S (PcdSaDisplayConfigTableSize, sizeof (mAdlPDdr5RvpDisplayDdiConfig));
+ break;
+ default:
+ break;
+ }
+
+ return;
+}
+
+/**
+ Board USB related configuration init function for PEI pre-memory phase.
+
+ @param[in] VOID
+
+ @retval VOID
+**/
+VOID
+AdlPSaUsbConfigInit (
+ VOID
+ )
+{
+ UINT16 BoardId;
+ BoardId = PcdGet16(PcdBoardId);
+
+ switch (BoardId) {
+ //
+ // Override ALL port setting if required.
+ //
+ case BoardIdAdlPDdr5Rvp:
+ PcdSet8S (PcdCpuXhciPortSupportMap, 0x0F);
+ break;
+ }
+ //
+ // Update Cpu Xhci Port Enable Map PCD
+ //
+ TcssUpdateCpuXhciPortEnableMapPcd ();
+}
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/GpioTableAdlPPostMem.h b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/GpioTableAdlPPostMem.h
new file mode 100644
index 0000000000..e40e2f860e
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/GpioTableAdlPPostMem.h
@@ -0,0 +1,25 @@
+/** @file
+ GPIO definition table for AlderLake P
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+#ifndef _ALDERLAKE_P_GPIO_TABLE_H_
+#define _ALDERLAKE_P_GPIO_TABLE_H_
+
+///
+
+/// !!! For those GPIO pins are designed as native function, BIOS CAN NOT configure the pins to Native function in GPIO init table!!!
+
+/// BIOS has to leave the native pins programming to Silicon Code(based on BIOS policies setting) or soft strap(set by CSME in FITc).
+
+/// Configuring pins to native function in GPIO table would cause BIOS perform multiple programming the pins and then related function might be abnormal.
+
+///
+
+#include <Pins/GpioPinsVer2Lp.h>
+#include <Library/GpioLib.h>
+#include <Library/GpioConfig.h>
+
+#endif // _ALDERLAKE_P_GPIO_TABLE_H_
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/PeiDetect.c b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/PeiDetect.c
new file mode 100644
index 0000000000..452c291753
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/PeiDetect.c
@@ -0,0 +1,63 @@
+/** @file
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <PiPei.h>
+#include <Library/PcdLib.h>
+#include <Library/DebugLib.h>
+#include <PlatformBoardType.h>
+#include <PlatformBoardId.h>
+#include <PlatformBoardConfig.h>
+#include <Pins/GpioPinsVer2Lp.h>
+#include <Library/BoardConfigLib.h>
+
+BOOLEAN
+IsAdlP (
+ VOID
+ )
+{
+ UINT16 BoardId;
+ BoardId = PcdGet16 (PcdBoardId);
+ if (BoardId == 0) {
+ DEBUG ((DEBUG_INFO, "Let's get Board information first ...\n"));
+ GetBoardConfig ();
+ BoardId = PcdGet16 (PcdBoardId);
+ }
+ switch (BoardId) {
+ case BoardIdAdlPDdr5Rvp:
+ DEBUG ((DEBUG_INFO, "AlderLake P Board detected\n"));
+
+ // set sku type to ADL P
+ PcdSet8S (PcdSkuType, AdlPSkuType);
+ return TRUE;
+ break;
+ default:
+ return FALSE;
+ }
+}
+
+EFI_STATUS
+EFIAPI
+AdlPBoardDetect (
+ VOID
+ )
+{
+ UINTN SkuId;
+ SkuId = 0;
+
+ if (LibPcdGetSku () != 0) {
+ return EFI_SUCCESS;
+ }
+
+ DEBUG ((DEBUG_INFO, "AlderLakeP Board Detection Callback\n"));
+
+ if (IsAdlP ()) {
+ SkuId = (UINTN) (PcdGet16 (PcdBoardBomId) << 16) | (PcdGet16 (PcdBoardRev) << 8) | (PcdGet16 (PcdBoardId));
+ LibPcdSetSku (SkuId);
+ DEBUG ((DEBUG_INFO, "SKU_ID: 0x%x\n", LibPcdGetSku()));
+ }
+ return EFI_SUCCESS;
+}
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/PeiInitPostMemLib.c b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/PeiInitPostMemLib.c
new file mode 100644
index 0000000000..9660e65b37
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/PeiInitPostMemLib.c
@@ -0,0 +1,245 @@
+/** @file
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <PiPei.h>
+#include <Library/DebugLib.h>
+#include <Library/PcdLib.h>
+
+#include <Library/BoardConfigLib.h>
+#include "GpioTableAdlPPostMem.h"
+#include <Library/GpioLib.h>
+#include <Library/IoLib.h>
+#include <PlatformBoardId.h>
+#include <PlatformBoardConfig.h>
+#include <Ppi/ReadOnlyVariable2.h>
+#include <Library/PchInfoLib.h>
+#include <Library/HobLib.h>
+
+
+
+/**
+ Alderlake P boards configuration init function for PEI post memory phase.
+
+ @retval EFI_SUCCESS The function completed successfully.
+**/
+EFI_STATUS
+EFIAPI
+AdlPInit (
+ VOID
+ )
+{
+ UINT16 GpioCount;
+ UINTN Size;
+ EFI_STATUS Status;
+ GPIO_INIT_CONFIG *GpioTable;
+ //
+ // GPIO Table Init
+ //
+ Status = EFI_SUCCESS;
+ GpioCount = 0;
+ Size = 0;
+ GpioTable = NULL;
+ //
+ // GPIO Table Init
+ //
+ //
+ // GPIO Table Init, Update PostMem GPIO table to PcdBoardGpioTable
+ //
+ GpioTable = (GPIO_INIT_CONFIG *)PcdGetPtr(VpdPcdBoardGpioTable);
+
+ GetGpioTableSize (GpioTable, &GpioCount);
+ //
+ // Increase GpioCount for the zero terminator.
+ //
+ GpioCount ++;
+ Size = (UINTN) (GpioCount * sizeof (GPIO_INIT_CONFIG));
+ Status = PcdSetPtrS (PcdBoardGpioTable, &Size, GpioTable);
+ ASSERT_EFI_ERROR (Status);
+
+ PcdSet8S (PcdSataPortsEnable0, 0x1);
+
+ return Status;
+}
+
+/**
+ Board I2C pads termination configuration init function for PEI pre-memory phase.
+**/
+VOID
+AdlPSerialIoI2cPadsTerminationInit (
+ VOID
+ )
+{
+}
+
+/**
+ Configures GPIO
+
+ @param[in] GpioTable Point to Platform Gpio table
+ @param[in] GpioTableCount Number of Gpio table entries
+
+**/
+VOID
+ConfigureGpio (
+ IN GPIO_INIT_CONFIG *GpioDefinition,
+ IN UINT16 GpioTableCount
+ )
+{
+ DEBUG ((DEBUG_INFO, "ConfigureGpio() Start\n"));
+
+ GpioConfigurePads (GpioTableCount, GpioDefinition);
+
+ DEBUG ((DEBUG_INFO, "ConfigureGpio() End\n"));
+}
+
+/**
+ Misc. init function for PEI post memory phase.
+**/
+VOID
+AdlPBoardMiscInit (
+ VOID
+ )
+{
+ UINT16 BoardId;
+ BoardId = PcdGet16 (PcdBoardId);
+
+ PcdSetBoolS (PcdSataLedEnable, FALSE);
+ PcdSetBoolS (PcdVrAlertEnable, FALSE);
+
+ //
+ // MIPI CAM
+ //
+ PcdSetBoolS (PcdMipiCamGpioEnable, TRUE);
+
+ return;
+}
+
+/**
+ PMC-PD solution enable init lib
+**/
+VOID
+AdlPBoardPmcPdInit (
+ VOID
+ )
+{
+ PcdSetBoolS (PcdBoardPmcPdEnable, 1);
+}
+
+
+/**
+ Configure GPIO, TouchPanel, HDA, PMC, TBT etc.
+
+ @retval EFI_SUCCESS Operation success.
+**/
+EFI_STATUS
+EFIAPI
+AdlPBoardInitBeforeSiliconInit (
+ VOID
+ )
+{
+ AdlPInit ();
+
+ AdlPSerialIoI2cPadsTerminationInit ();
+ AdlPBoardMiscInit ();
+ AdlPBoardPmcPdInit ();
+ GpioInit (PcdGetPtr (PcdBoardGpioTable));
+
+ return EFI_SUCCESS;
+}
+
+VOID
+AdlPInitCommonPlatformPcdPostMem (
+ VOID
+ )
+{
+ UINT16 BoardId;
+ BoardId = PcdGet16(PcdBoardId);
+
+ PcdSetBoolS (PcdPssReadSN, TRUE);
+ PcdSet8S (PcdPssI2cSlaveAddress, 0x6E);
+ PcdSet8S (PcdPssI2cBusNumber, 0x05);
+ PcdSetBoolS (PcdSpdAddressOverride, FALSE);
+
+ //
+ // Battery Present
+ // Real & Virtual battery is need to supported in all except Desktop
+ //
+ PcdSet8S (PcdBatteryPresent, BOARD_REAL_BATTERY_SUPPORTED | BOARD_VIRTUAL_BATTERY_SUPPORTED);
+ //
+ // Real Battery 1 Control & Real Battery 2 Control
+ //
+ PcdSet8S (PcdRealBattery1Control, 1);
+ PcdSet8S (PcdRealBattery2Control, 2);
+
+
+ //
+ // H8S2113 SIO, UART
+ //
+ PcdSetBoolS (PcdH8S2113SIO, FALSE);
+ PcdSetBoolS (PcdH8S2113UAR, FALSE);
+ //
+ // NCT6776F COM, SIO & HWMON
+ //
+ PcdSetBoolS (PcdNCT6776FCOM, FALSE);
+ PcdSetBoolS (PcdNCT6776FSIO, FALSE);
+ PcdSetBoolS (PcdNCT6776FHWMON, FALSE);
+ //
+ // SMC Runtime Sci Pin
+ // EC will use eSpi interface to generate SCI
+ //
+ PcdSet32S (PcdSmcRuntimeSciPin, 0x00);
+
+ //
+ // Virtual Button Volume Up & Done Support
+ // Virtual Button Home Button Support
+ // Virtual Button Rotation Lock Support
+ //
+ PcdSetBoolS (PcdVirtualButtonVolumeUpSupport, TRUE);
+ PcdSetBoolS (PcdVirtualButtonVolumeDownSupport, TRUE);
+ PcdSetBoolS (PcdVirtualButtonHomeButtonSupport, TRUE);
+ PcdSetBoolS (PcdVirtualButtonRotationLockSupport, TRUE);
+ //
+ // Slate Mode Switch Support
+ //
+ PcdSetBoolS (PcdSlateModeSwitchSupport, TRUE);
+ //
+ // Virtual Gpio Button Support
+ //
+ PcdSetBoolS (PcdVirtualGpioButtonSupport, TRUE);
+
+ //
+ // Acpi Enable All Button Support
+ //
+ PcdSetBoolS (PcdAcpiEnableAllButtonSupport, TRUE);
+ //
+ // Acpi Hid Driver Button Support
+ //
+ PcdSetBoolS (PcdAcpiHidDriverButtonSupport, TRUE);
+
+ //
+ // ADL-P supports EC-PD design, for communication between EC and PD.
+ //
+ PcdSetBoolS (PcdUsbcEcPdNegotiation, TRUE);
+
+
+}
+
+/**
+ Board init for PEI after Silicon initialized
+
+ @retval EFI_SUCCESS Operation success.
+**/
+EFI_STATUS
+EFIAPI
+AdlPBoardInitAfterSiliconInit (
+ VOID
+ )
+{
+ DEBUG ((DEBUG_INFO, "ADLPBoardInitAfterSiliconInit \n"));
+ AdlPInitCommonPlatformPcdPostMem ();
+
+ return EFI_SUCCESS;
+}
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/PeiInitPreMemLib.c b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/PeiInitPreMemLib.c
new file mode 100644
index 0000000000..719dab97a6
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/PeiInitPreMemLib.c
@@ -0,0 +1,261 @@
+/** @file
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <PiPei.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/BiosIdLib.h>
+#include <Library/PcdLib.h>
+#include <Library/DebugLib.h>
+#include <Library/PciLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/PeiLib.h>
+#include <Guid/MemoryOverwriteControl.h>
+#include <PlatformBoardConfig.h>
+#include <Library/PchCycleDecodingLib.h>
+#include <Register/PmcRegs.h>
+#include <Library/PmcLib.h>
+#include <Ppi/ReadOnlyVariable2.h>
+#include <Library/PeiServicesLib.h>
+#include <Library/GpioLib.h>
+#include <Library/BoardConfigLib.h>
+#include <Library/TimerLib.h>
+#include <PlatformBoardId.h>
+#include <Library/IoLib.h>
+#include <Pins/GpioPinsVer2Lp.h>
+#include <Library/PchInfoLib.h>
+
+/**
+ Get Vpd binary address
+
+ Parse through each FV for VPD FFS file and return the address
+
+ @retval Address on VPD FFS detection else returns 0
+
+**/
+UINTN
+EFIAPI
+GetVpdFfsAddress (
+ )
+{
+ EFI_STATUS Status;
+ VOID *Address;
+ UINTN Instance;
+ EFI_PEI_FV_HANDLE VolumeHandle;
+ EFI_PEI_FILE_HANDLE FileHandle;
+
+ Address = NULL;
+
+ VolumeHandle = NULL;
+ Instance = 0;
+ while (TRUE) {
+ //
+ // Traverse all firmware volume instances.
+ //
+ Status = PeiServicesFfsFindNextVolume (Instance, &VolumeHandle);
+ if (EFI_ERROR (Status)) {
+ break;
+ }
+
+ FileHandle = NULL;
+ Status = PeiServicesFfsFindFileByName (&gVpdFfsGuid, VolumeHandle, &FileHandle);
+ if (!EFI_ERROR (Status)) {
+ //
+ // Search RAW section.
+ //
+ Status = PeiServicesFfsFindSectionData (EFI_SECTION_RAW, FileHandle, &Address);
+ if (!EFI_ERROR (Status)) {
+ return (UINTN)Address;
+ }
+ }
+
+ //
+ // Search the next volume.
+ //
+ Instance++;
+ }
+
+ DEBUG ((EFI_D_ERROR, " PEI get VPD address: %r\n", EFI_NOT_FOUND));
+ return 0;
+}
+
+/**
+ Alderlake P boards configuration init function for PEI pre-memory phase.
+
+ @retval EFI_SUCCESS The function completed successfully.
+**/
+EFI_STATUS
+EFIAPI
+AdlPInitPreMem (
+ VOID
+ )
+{
+ UINT8 MorControl;
+ UINTN VpdBaseAddress;
+
+ VpdBaseAddress = (UINTN) PcdGet64 (PcdVpdBaseAddress64);
+ DEBUG ((EFI_D_INFO, "VpdFfsAddress: %x\n", VpdBaseAddress));
+ if (VpdBaseAddress == 0) {
+ VpdBaseAddress= (UINTN) GetVpdFfsAddress();
+ PcdSet64S (PcdVpdBaseAddress64,VpdBaseAddress);
+ DEBUG ((EFI_D_INFO, "VpdFfsAddress updated: %x\n", VpdBaseAddress));
+ }
+ //
+ // MOR
+ //
+ MorControl = 0;
+ if (MOR_CLEAR_MEMORY_VALUE (MorControl)) {
+ PcdSet8S (PcdCleanMemory, MorControl & MOR_CLEAR_MEMORY_BIT_MASK);
+ }
+
+ PcdSet32S (PcdStackBase, PcdGet32 (PcdTemporaryRamBase) + PcdGet32 (PcdTemporaryRamSize) - (PcdGet32 (PcdFspTemporaryRamSize) + PcdGet32 (PcdFspReservedBufferSize)));
+ PcdSet32S (PcdStackSize, PcdGet32 (PcdFspTemporaryRamSize));
+
+ PcdSet8S (PcdCpuRatio, 0x0);
+
+ return EFI_SUCCESS;
+}
+
+
+VOID
+AdlPMrcConfigInit (
+ VOID
+ );
+
+VOID
+AdlPSaMiscConfigInit (
+ VOID
+ );
+
+VOID
+AdlPSaGpioConfigInit (
+ VOID
+ );
+
+VOID
+AdlPSaDisplayConfigInit (
+ VOID
+ );
+
+VOID
+AdlPSaUsbConfigInit (
+ VOID
+ );
+
+EFI_STATUS
+AdlPRootPortClkInfoInit (
+ VOID
+ );
+
+EFI_STATUS
+AdlPUsbConfigInit (
+ VOID
+ );
+
+VOID
+AdlPGpioGroupTierInit (
+ VOID
+ );
+
+/**
+ Board Misc init function for PEI pre-memory phase.
+**/
+VOID
+AdlPBoardMiscInitPreMem (
+ VOID
+ )
+{
+ UINT16 BoardId;
+ BoardId = PcdGet16(PcdBoardId);
+
+ //
+ // OddPower Init
+ //
+ PcdSetBoolS (PcdOddPowerInitEnable, FALSE);
+
+ //
+ // Pc8374SioKbc Present
+ //
+ PcdSetBoolS (PcdPc8374SioKbcPresent, FALSE);
+
+ //
+ // Smbus Alert function Init.
+ //
+ PcdSetBoolS (PcdSmbusAlertEnable, FALSE);
+}
+
+
+/**
+ A hook for board-specific initialization prior to memory initialization.
+
+ @retval EFI_SUCCESS The board initialization was successful.
+**/
+EFI_STATUS
+EFIAPI
+AdlPBoardInitBeforeMemoryInit (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+
+ DEBUG ((DEBUG_INFO, "AdlPBoardInitBeforeMemoryInit\n"));
+
+ AdlPInitPreMem ();
+
+ AdlPBoardMiscInitPreMem ();
+
+ AdlPGpioGroupTierInit ();
+
+
+ AdlPMrcConfigInit ();
+ AdlPSaGpioConfigInit ();
+ AdlPSaMiscConfigInit ();
+ Status = AdlPRootPortClkInfoInit ();
+ Status = AdlPUsbConfigInit ();
+ AdlPSaDisplayConfigInit ();
+ AdlPSaUsbConfigInit ();
+ if (PcdGetPtr (PcdBoardGpioTableEarlyPreMem) != 0) {
+ GpioInit (PcdGetPtr (PcdBoardGpioTableEarlyPreMem));
+
+ MicroSecondDelay (15 * 1000); // 15 ms Delay
+ }
+ // Configure GPIO Before Memory
+ GpioInit (PcdGetPtr (PcdBoardGpioTablePreMem));
+
+ return EFI_SUCCESS;
+}
+
+
+/**
+ This board service initializes board-specific debug devices.
+
+ @retval EFI_SUCCESS Board-specific debug initialization was successful.
+**/
+EFI_STATUS
+EFIAPI
+AdlPBoardDebugInit (
+ VOID
+ )
+{
+ DEBUG ((DEBUG_INFO, "AdlPBoardDebugInit\n"));
+
+ return EFI_SUCCESS;
+}
+
+/**
+ This board service detects the boot mode.
+
+ @retval EFI_BOOT_MODE The boot mode.
+**/
+EFI_BOOT_MODE
+EFIAPI
+AdlPBoardBootModeDetect (
+ VOID
+ )
+{
+ DEBUG ((DEBUG_INFO, "AdlPBoardBootModeDetect\n"));
+ return BOOT_WITH_FULL_CONFIGURATION;
+}
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/PeiMultiBoardInitPostMemLib.c b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/PeiMultiBoardInitPostMemLib.c
new file mode 100644
index 0000000000..f47fc473f2
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/PeiMultiBoardInitPostMemLib.c
@@ -0,0 +1,50 @@
+/** @file
+ PEI Multi-Board Initialization in Post-Memory PEI Library
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <PiPei.h>
+#include <Library/BaseLib.h>
+#include <Library/IoLib.h>
+#include <Library/BoardInitLib.h>
+#include <Library/MultiBoardInitSupportLib.h>
+#include <Library/PcdLib.h>
+#include <Library/DebugLib.h>
+
+#include <PlatformBoardId.h>
+
+EFI_STATUS
+EFIAPI
+AdlPBoardInitBeforeSiliconInit (
+ VOID
+ );
+
+EFI_STATUS
+EFIAPI
+AdlPBoardInitAfterSiliconInit (
+ VOID
+ );
+
+BOARD_POST_MEM_INIT_FUNC mAdlPBoardInitFunc = {
+ AdlPBoardInitBeforeSiliconInit,
+ AdlPBoardInitAfterSiliconInit,
+};
+
+EFI_STATUS
+EFIAPI
+PeiAdlPMultiBoardInitLibConstructor (
+ VOID
+ )
+{
+ UINT8 SkuType;
+ SkuType = PcdGet8 (PcdSkuType);
+
+ if (SkuType==AdlPSkuType) {
+ DEBUG ((DEBUG_INFO, "SKU_ID: 0x%x\n", LibPcdGetSku()));
+ return RegisterBoardPostMemInit (&mAdlPBoardInitFunc);
+ }
+ return EFI_SUCCESS;
+}
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/PeiMultiBoardInitPostMemLib.inf b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/PeiMultiBoardInitPostMemLib.inf
new file mode 100644
index 0000000000..e13cae7143
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/PeiMultiBoardInitPostMemLib.inf
@@ -0,0 +1,111 @@
+## @file
+# Component information file for Alderlake Multi-Board Initialization in PEI post memory phase.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+###
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = PeiAdlPMultiBoardInitLib
+ FILE_GUID = C7D39F17-E5BA-41D9-8DFE-FF9017499280
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = NULL
+ CONSTRUCTOR = PeiAdlPMultiBoardInitLibConstructor
+
+[LibraryClasses]
+ BaseLib
+ DebugLib
+ BaseMemoryLib
+ MemoryAllocationLib
+ PcdLib
+ MultiBoardInitSupportLib
+ PciSegmentLib
+ GpioLib
+ HobLib
+ BoardConfigLib
+
+[Packages]
+ MinPlatformPkg/MinPlatformPkg.dec
+ AlderlakeOpenBoardPkg/OpenBoardPkg.dec
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ AlderlakeSiliconPkg/SiPkg.dec
+ SecurityPkg/SecurityPkg.dec
+
+[Sources]
+ PeiInitPostMemLib.c
+ PeiMultiBoardInitPostMemLib.c
+
+[FixedPcd]
+ gBoardModuleTokenSpaceGuid.PcdSetupEnable
+
+[Pcd]
+ # Board GPIO Table
+ gBoardModuleTokenSpaceGuid.PcdBoardGpioTable
+ gBoardModuleTokenSpaceGuid.PcdSataPortsEnable0
+ gBoardModuleTokenSpaceGuid.PcdPreferredPmProfile
+ gBoardModuleTokenSpaceGuid.PcdPlatformFlavor ## CONSUMES
+
+ gBoardModuleTokenSpaceGuid.PcdBoardPmcPdEnable
+ gBoardModuleTokenSpaceGuid.PcdMipiCamGpioEnable
+
+ # CPU USB 3.0 Port Over Current Pin
+ gBoardModuleTokenSpaceGuid.VpdPcdCpuUsb3OcMap
+
+
+ gBoardModuleTokenSpaceGuid.PcdUsbcEcPdNegotiation
+
+ # TPM interrupt
+ gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable ## CONSUMES
+ gEfiSecurityPkgTokenSpaceGuid.PcdTpm2CurrentIrqNum
+
+ gBoardModuleTokenSpaceGuid.PcdBatteryPresent ## PRODUCE
+ gBoardModuleTokenSpaceGuid.PcdRealBattery1Control ## PRODUCE
+ gBoardModuleTokenSpaceGuid.PcdRealBattery2Control ## PRODUCE
+ #Misc Config
+ gBoardModuleTokenSpaceGuid.PcdSataLedEnable
+ gBoardModuleTokenSpaceGuid.PcdVrAlertEnable
+ gBoardModuleTokenSpaceGuid.PcdBoardBomId
+
+ #TouchPanel Config
+ gBoardModuleTokenSpaceGuid.PcdBoardGpioTableTouchPanel1
+ gBoardModuleTokenSpaceGuid.PcdBoardGpioTableTouchPanel1Size
+
+ #CVF Config
+ gBoardModuleTokenSpaceGuid.PcdBoardGpioTableCvf
+ gBoardModuleTokenSpaceGuid.PcdBoardGpioTableCvfSize
+
+ # I2C Touch Panel 0 & 1 RTD3
+ gBoardModuleTokenSpaceGuid.PcdPssI2cSlaveAddress ## PRODUC
+ gBoardModuleTokenSpaceGuid.PcdPssReadSN
+ gBoardModuleTokenSpaceGuid.PcdPssI2cBusNumber
+ gBoardModuleTokenSpaceGuid.PcdSpdAddressOverride
+
+ gBoardModuleTokenSpaceGuid.PcdBoardId
+ gBoardModuleTokenSpaceGuid.PcdSkuType
+ gBoardModuleTokenSpaceGuid.VpdPcdBoardGpioTable
+
+ gBoardModuleTokenSpaceGuid.PcdBoardRtd3TableSignature
+ gBoardModuleTokenSpaceGuid.PcdXhciAcpiTableSignature
+
+ gBoardModuleTokenSpaceGuid.PcdH8S2113SIO
+ gBoardModuleTokenSpaceGuid.PcdH8S2113UAR
+ gBoardModuleTokenSpaceGuid.PcdNCT6776FCOM
+ gBoardModuleTokenSpaceGuid.PcdNCT6776FSIO
+ gBoardModuleTokenSpaceGuid.PcdNCT6776FHWMON
+
+ gBoardModuleTokenSpaceGuid.PcdSmcRuntimeSciPin
+
+ gBoardModuleTokenSpaceGuid.PcdVirtualButtonVolumeUpSupport
+ gBoardModuleTokenSpaceGuid.PcdVirtualButtonVolumeDownSupport
+ gBoardModuleTokenSpaceGuid.PcdVirtualButtonHomeButtonSupport
+ gBoardModuleTokenSpaceGuid.PcdVirtualButtonRotationLockSupport
+
+ gBoardModuleTokenSpaceGuid.PcdSlateModeSwitchSupport
+ gBoardModuleTokenSpaceGuid.PcdVirtualGpioButtonSupport
+ gBoardModuleTokenSpaceGuid.PcdPmPowerButtonGpioPin
+ gBoardModuleTokenSpaceGuid.PcdAcpiEnableAllButtonSupport
+ gBoardModuleTokenSpaceGuid.PcdAcpiHidDriverButtonSupport
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/PeiMultiBoardInitPreMemLib.c b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/PeiMultiBoardInitPreMemLib.c
new file mode 100644
index 0000000000..d3a5299b07
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/PeiMultiBoardInitPreMemLib.c
@@ -0,0 +1,88 @@
+/** @file
+ PEI Multi-Board Initialization in Pre-Memory PEI Library
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <PiPei.h>
+#include <Library/BaseLib.h>
+#include <Library/IoLib.h>
+#include <Library/BoardInitLib.h>
+#include <Library/MultiBoardInitSupportLib.h>
+#include <Library/PcdLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BoardConfigLib.h>
+#include <PlatformBoardId.h>
+
+EFI_STATUS
+EFIAPI
+AdlPBoardDetect (
+ VOID
+ );
+
+EFI_STATUS
+EFIAPI
+AdlPMultiBoardDetect (
+ VOID
+ );
+
+EFI_BOOT_MODE
+EFIAPI
+AdlPBoardBootModeDetect (
+ VOID
+ );
+
+EFI_STATUS
+EFIAPI
+AdlPBoardDebugInit (
+ VOID
+ );
+
+EFI_STATUS
+EFIAPI
+AdlPBoardInitBeforeMemoryInit (
+ VOID
+ );
+
+BOARD_DETECT_FUNC mAdlPBoardDetectFunc = {
+ AdlPMultiBoardDetect
+};
+
+BOARD_PRE_MEM_INIT_FUNC mAdlPBoardPreMemInitFunc = {
+ AdlPBoardDebugInit,
+ AdlPBoardBootModeDetect,
+ AdlPBoardInitBeforeMemoryInit,
+ NULL, // BoardInitBeforeTempRamExit
+ NULL, // BoardInitAfterTempRamExit
+};
+
+EFI_STATUS
+EFIAPI
+AdlPMultiBoardDetect (
+ VOID
+ )
+{
+ UINT8 SkuType;
+ DEBUG ((DEBUG_INFO, " In AdlPMultiBoardDetect \n"));
+
+ AdlPBoardDetect ();
+
+ SkuType = PcdGet8 (PcdSkuType);
+ if (SkuType==AdlPSkuType) {
+ RegisterBoardPreMemInit (&mAdlPBoardPreMemInitFunc);
+ } else {
+ DEBUG ((DEBUG_WARN,"Not a Valid Alderlake P Board\n"));
+ }
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+EFIAPI
+PeiAdlPMultiBoardInitPreMemLibConstructor (
+ VOID
+ )
+{
+ return RegisterBoardDetect (&mAdlPBoardDetectFunc);
+}
\ No newline at end of file
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/PeiMultiBoardInitPreMemLib.inf b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/PeiMultiBoardInitPreMemLib.inf
new file mode 100644
index 0000000000..3dfbe75e4e
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/AlderlakePRvp/Library/BoardInitLib/Pei/PeiMultiBoardInitPreMemLib.inf
@@ -0,0 +1,210 @@
+## @file
+# Component information file for PEI Alderlake P Board Init Pre-Mem Library
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+###
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = PeiAdlPMultiBoardInitPreMemLib
+ FILE_GUID = EA05BD43-136F-45EE-BBBA-27D75817574F
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = NULL
+ CONSTRUCTOR = PeiAdlPMultiBoardInitPreMemLibConstructor
+
+[LibraryClasses]
+ BaseLib
+ DebugLib
+ BaseMemoryLib
+ MemoryAllocationLib
+ PcdLib
+ MultiBoardInitSupportLib
+ PeiLib
+ BoardConfigLib
+ PchInfoLib
+
+[Packages]
+ MinPlatformPkg/MinPlatformPkg.dec
+ AlderlakeOpenBoardPkg/OpenBoardPkg.dec
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ IntelFsp2Pkg/IntelFsp2Pkg.dec
+ AlderlakeSiliconPkg/SiPkg.dec
+ BoardModulePkg/BoardModulePkg.dec
+
+[Sources]
+ PeiInitPreMemLib.c
+ PeiMultiBoardInitPreMemLib.c
+ PeiDetect.c
+ BoardSaInitPreMemLib.c
+ BoardPchInitPreMemLib.c
+
+[Pcd]
+ gBoardModuleTokenSpaceGuid.PcdLpcSioConfigDefaultPort
+
+ # SA Misc Config
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdData
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdData00
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdData01
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdData10
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdData11
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdDataSize
+
+ # SPD Address Table
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable0
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable1
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable2
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable3
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable4
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable5
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable6
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable7
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable8
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable9
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable10
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable11
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable12
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable13
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable14
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable15
+
+ #MRC Config
+ gBoardModuleTokenSpaceGuid.PcdMrcDqByteMap
+ gBoardModuleTokenSpaceGuid.PcdMrcDqByteMapSize
+ gBoardModuleTokenSpaceGuid.PcdMrcRcompResistor
+ gBoardModuleTokenSpaceGuid.PcdMrcRcompTarget
+ gBoardModuleTokenSpaceGuid.PcdMrcDqPinsInterleavedControl
+ gBoardModuleTokenSpaceGuid.PcdMrcDqPinsInterleaved
+ gBoardModuleTokenSpaceGuid.PcdMrcDqsMapCpu2DramSize
+ gBoardModuleTokenSpaceGuid.PcdMrcDqMapCpu2DramSize
+ gBoardModuleTokenSpaceGuid.PcdMrcDqsMapCpu2Dram
+ gBoardModuleTokenSpaceGuid.PcdMrcDqMapCpu2Dram
+ gBoardModuleTokenSpaceGuid.PcdMrcCaVrefConfig
+ gBoardModuleTokenSpaceGuid.PcdMrcLp5CccConfig
+ gBoardModuleTokenSpaceGuid.PcdSaMiscUserBd
+ gBoardModuleTokenSpaceGuid.PcdSaDdrFreqLimit
+
+ #MISC
+ gBoardModuleTokenSpaceGuid.PcdOddPowerInitEnable
+ gBoardModuleTokenSpaceGuid.PcdPc8374SioKbcPresent
+ gBoardModuleTokenSpaceGuid.PcdSmbusAlertEnable
+ gBoardModuleTokenSpaceGuid.PcdWakeupType
+ gBoardModuleTokenSpaceGuid.PcdSetupEnable
+
+ # USB 2.0 Port Over Current Pin
+ gBoardModuleTokenSpaceGuid.PcdUsb2OverCurrentPinTable
+
+ # USB 3.0 Port Over Current Pin
+ gBoardModuleTokenSpaceGuid.PcdUsb3OverCurrentPinTable
+
+ #Board Information
+ gBoardModuleTokenSpaceGuid.PcdPlatformGeneration
+ gBoardModuleTokenSpaceGuid.PcdSpdPresent
+ gBoardModuleTokenSpaceGuid.PcdPlatformType
+ gBoardModuleTokenSpaceGuid.PcdPlatformFlavor
+ gBoardModuleTokenSpaceGuid.PcdBoardRev
+ gBoardModuleTokenSpaceGuid.PcdBoardId
+ gBoardModuleTokenSpaceGuid.PcdSkuType
+ gBoardModuleTokenSpaceGuid.PcdBoardBomId
+ gBoardModuleTokenSpaceGuid.PcdBoardType
+ gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemTableId
+ gBoardModuleTokenSpaceGuid.VpdPcdBoardGpioTablePreMem
+ gBoardModuleTokenSpaceGuid.VpdPcdPcieClkUsageMap
+ gBoardModuleTokenSpaceGuid.VpdPcdUSB2OCMap
+ gBoardModuleTokenSpaceGuid.VpdPcdUSB3OCMap
+ gBoardModuleTokenSpaceGuid.VpdPcdMrcSpdData
+ gBoardModuleTokenSpaceGuid.VpdPcdMrcDqsMapCpu2Dram
+ gBoardModuleTokenSpaceGuid.VpdPcdMrcDqMapCpu2Dram
+ gBoardModuleTokenSpaceGuid.PcdDisplayId ## CONSUMES
+
+ gBoardModuleTokenSpaceGuid.PcdCpuRatio
+
+ gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase ## CONSUMES
+ gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamSize ## CONSUMES
+ gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize ## CONSUMES
+ gIntelFsp2PkgTokenSpaceGuid.PcdFspReservedBufferSize ## CONSUMES
+
+ gBoardModuleTokenSpaceGuid.PcdStackBase
+ gBoardModuleTokenSpaceGuid.PcdStackSize
+ gBoardModuleTokenSpaceGuid.PcdNvsBufferPtr
+ gBoardModuleTokenSpaceGuid.PcdCleanMemory
+
+ #SA GPIO Config
+ gBoardModuleTokenSpaceGuid.PcdRootPortIndex
+
+ # PCIE Slot1 (x4 Connector) GPIO PCDs
+ gBoardModuleTokenSpaceGuid.PcdPcieSlot1GpioSupport
+ gBoardModuleTokenSpaceGuid.PcdPcieSlot1PwrEnableExpanderNo
+ gBoardModuleTokenSpaceGuid.PcdPcieSlot1PwrEnableGpioNo
+
+ # PCIe x4 M.2 SSD1 RTD3
+ gBoardModuleTokenSpaceGuid.PcdPcieSsd2PwrEnableGpioNo
+ gBoardModuleTokenSpaceGuid.PcdPcieSsd2PwrEnableGpioPolarity
+
+ # PCIe x4 M.2 SSD2 RTD3
+ gBoardModuleTokenSpaceGuid.PcdPcieSsd3PwrEnableGpioNo
+ gBoardModuleTokenSpaceGuid.PcdPcieSsd3PwrEnableGpioPolarity
+
+ # CPU PCIe x8 DG RTD3
+ gBoardModuleTokenSpaceGuid.PcdPcieDG2PwrEnableGpioNo
+ gBoardModuleTokenSpaceGuid.PcdPcieDG2PwrEnableGpioPolarity
+ gBoardModuleTokenSpaceGuid.PcdPcieDG2WakeGpioPin
+
+ #SA USB Config
+ gBoardModuleTokenSpaceGuid.PcdCpuXhciPortSupportMap
+
+
+ # PCIe Clock Info
+ gBoardModuleTokenSpaceGuid.PcdPcieClock0
+ gBoardModuleTokenSpaceGuid.PcdPcieClock1
+ gBoardModuleTokenSpaceGuid.PcdPcieClock2
+ gBoardModuleTokenSpaceGuid.PcdPcieClock3
+ gBoardModuleTokenSpaceGuid.PcdPcieClock4
+ gBoardModuleTokenSpaceGuid.PcdPcieClock5
+ gBoardModuleTokenSpaceGuid.PcdPcieClock6
+ gBoardModuleTokenSpaceGuid.PcdPcieClock7
+ gBoardModuleTokenSpaceGuid.PcdPcieClock8
+ gBoardModuleTokenSpaceGuid.PcdPcieClock9
+ gBoardModuleTokenSpaceGuid.PcdPcieClock10
+ gBoardModuleTokenSpaceGuid.PcdPcieClock11
+ gBoardModuleTokenSpaceGuid.PcdPcieClock12
+ gBoardModuleTokenSpaceGuid.PcdPcieClock13
+ gBoardModuleTokenSpaceGuid.PcdPcieClock14
+ gBoardModuleTokenSpaceGuid.PcdPcieClock15
+
+
+ # GPIO Group Tier
+ gBoardModuleTokenSpaceGuid.PcdGpioGroupToGpeDw0
+ gBoardModuleTokenSpaceGuid.PcdGpioGroupToGpeDw1
+ gBoardModuleTokenSpaceGuid.PcdGpioGroupToGpeDw2
+
+
+
+ # WWAN Full Card Power Off and reset pins
+ gBoardModuleTokenSpaceGuid.PcdDisableVpdGpioTable
+ gBoardModuleTokenSpaceGuid.PcdBoardGpioTablePreMem ## PRODUCES
+ gBoardModuleTokenSpaceGuid.PcdBoardGpioTableEarlyPreMem ## PRODUCES
+
+
+ # Display DDI
+ gBoardModuleTokenSpaceGuid.PcdSaDisplayConfigTable ## PRODUCES
+ gBoardModuleTokenSpaceGuid.PcdSaDisplayConfigTableSize ## PRODUCES
+
+ gPlatformModuleTokenSpaceGuid.PcdDesktopLpcSioDataDefaultPort ## CONSUMES
+ gPlatformModuleTokenSpaceGuid.PcdDesktopLpcSioIndexDefaultPort ## CONSUMES
+
+ gSiPkgTokenSpaceGuid.PcdAdlSSupport ## CONSUMES
+ gEfiMdeModulePkgTokenSpaceGuid.PcdVpdBaseAddress64 ## CONSUMES
+
+[Guids]
+ gFspNonVolatileStorageHobGuid
+ gEfiMemoryOverwriteControlDataGuid
+ gVpdFfsGuid
+
+[Ppis]
+ gPatchConfigurationDataPreMemPpiGuid ## NOTIFY
+ gEfiPeiReadOnlyVariable2PpiGuid ## CONSUMES
+ gSetupVariablesReadyPpiGuid ## PRODUCES
--
2.36.1.windows.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 4/6] AlderlakeOpenBoardPkg: Add ACPI module
[not found] <cover.1686770061.git.saloni.kasbekar@intel.com>
` (2 preceding siblings ...)
2023-06-14 19:17 ` [PATCH 3/6] AlderlakeOpenBoardPkg/AlderlakePRvp: Add library instances Saloni Kasbekar
@ 2023-06-14 19:17 ` Saloni Kasbekar
2023-06-14 19:17 ` [PATCH 5/6] AlderlakeOpenBoardPkg: Adds the Policy Module Saloni Kasbekar
2023-06-14 19:17 ` [PATCH 6/6] AlderlakeOpenBoardPkg: Add Library Instances Saloni Kasbekar
5 siblings, 0 replies; 6+ messages in thread
From: Saloni Kasbekar @ 2023-06-14 19:17 UTC (permalink / raw)
To: devel
Cc: Saloni Kasbekar, Sai Chaganty, Nate DeSimone, Isaac Oram,
Rosen Chuang
Adds AcpiTables and AdvancedAcpiDxe drivers
Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Isaac Oram <isaac.w.oram@intel.com>
Cc: Rosen Chuang <rosen.chuang@intel.com>
Signed-off-by: Saloni Kasbekar <saloni.kasbekar@intel.com>
---
.../Acpi/AcpiTables/AcpiTables.inf | 68 +
.../Acpi/AcpiTables/Dsdt/Dsdt.asl | 32 +
.../Acpi/AcpiTables/Dsdt/PciTree.asl | 17 +
.../Acpi/AcpiTables/Ecdt/Ecdt.act | 103 +
.../Acpi/AcpiTables/Ecdt/Ecdt.h | 26 +
.../Acpi/AcpiTables/Facs/Facs.act | 91 +
.../Acpi/AcpiTables/Facs/Facs.h | 34 +
.../Acpi/AcpiTables/Fadt/Fadt6.3.act | 236 +++
.../Acpi/AcpiTables/Fadt/Fadt6.3.h | 184 ++
.../Acpi/AcpiTables/Hpet/Hpet.act | 77 +
.../Acpi/AcpiTables/Hpet/Hpet.h | 43 +
.../Acpi/AcpiTables/Include/AcpiCommon.h | 16 +
.../Acpi/AcpiTables/Madt/Madt.act | 573 ++++++
.../Acpi/AcpiTables/Madt/Madt.h | 226 +++
.../Acpi/AcpiTables/Madt/MadtX2Apic.act | 522 +++++
.../Acpi/AcpiTables/Mcfg/Mcfg.act | 91 +
.../Acpi/AcpiTables/Mcfg/Mcfg.h | 53 +
.../Acpi/AdvancedAcpiDxe/AcpiByteStream.h | 137 ++
.../Acpi/AdvancedAcpiDxe/AcpiPlatform.c | 1716 +++++++++++++++++
.../Acpi/AdvancedAcpiDxe/AcpiPlatform.h | 142 ++
.../Acpi/AdvancedAcpiDxe/AdvancedAcpiDxe.inf | 154 ++
.../Acpi/AdvancedAcpiDxe/GenSsdtLib.c | 474 +++++
.../Acpi/AdvancedAcpiDxe/GenSsdtLib.h | 17 +
23 files changed, 5032 insertions(+)
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AcpiTables/AcpiTables.inf
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AcpiTables/Dsdt/Dsdt.asl
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AcpiTables/Dsdt/PciTree.asl
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AcpiTables/Ecdt/Ecdt.act
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AcpiTables/Ecdt/Ecdt.h
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AcpiTables/Facs/Facs.act
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AcpiTables/Facs/Facs.h
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AcpiTables/Fadt/Fadt6.3.act
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AcpiTables/Fadt/Fadt6.3.h
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AcpiTables/Hpet/Hpet.act
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AcpiTables/Hpet/Hpet.h
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AcpiTables/Include/AcpiCommon.h
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AcpiTables/Madt/Madt.act
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AcpiTables/Madt/Madt.h
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AcpiTables/Madt/MadtX2Apic.act
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AcpiTables/Mcfg/Mcfg.act
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AcpiTables/Mcfg/Mcfg.h
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AdvancedAcpiDxe/AcpiByteStream.h
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AdvancedAcpiDxe/AcpiPlatform.c
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AdvancedAcpiDxe/AcpiPlatform.h
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AdvancedAcpiDxe/AdvancedAcpiDxe.inf
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AdvancedAcpiDxe/GenSsdtLib.c
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AdvancedAcpiDxe/GenSsdtLib.h
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AcpiTables/AcpiTables.inf b/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AcpiTables/AcpiTables.inf
new file mode 100644
index 0000000000..ccf1f3f69b
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AcpiTables/AcpiTables.inf
@@ -0,0 +1,68 @@
+### @file
+# Component information file for the ACPI tables
+#
+# Copyright (c) 1999 - 2021, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+###
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = AcpiTables
+ FILE_GUID = 7E374E25-8E01-4FEE-87F2-390C23C606CD
+ MODULE_TYPE = USER_DEFINED
+ VERSION_STRING = 1.0
+
+[Sources]
+ Fadt/Fadt6.3.act
+ Facs/Facs.act
+ Hpet/Hpet.act
+ Madt/Madt.act
+ Madt/MadtX2Apic.act
+ Mcfg/Mcfg.act
+ Ecdt/Ecdt.act
+ Dsdt/Dsdt.asl
+
+################################################################################
+#
+# Package Dependency Section - list of Package files that are required for
+# this module.
+#
+################################################################################
+[Packages]
+ MdePkg/MdePkg.dec
+ AlderlakeSiliconPkg/SiPkg.dec
+ AlderlakeOpenBoardPkg/OpenBoardPkg.dec
+ PcAtChipsetPkg/PcAtChipsetPkg.dec
+
+################################################################################
+#
+# Library Class Section - list of Library Classes that are required for
+# this module.
+#
+################################################################################
+
+[LibraryClasses]
+
+[FixedPcd]
+ gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress ## CONSUMES
+ gSiPkgTokenSpaceGuid.PcdTcoBaseAddress ## CONSUMES
+ gPlatformModuleTokenSpaceGuid.PcdApicLocalAddress ## CONSUMES
+ gPlatformModuleTokenSpaceGuid.PcdApicIoAddress ## CONSUMES
+ gPlatformModuleTokenSpaceGuid.PcdAcpiEnableSwSmi ## CONSUMES
+ gPlatformModuleTokenSpaceGuid.PcdAcpiDisableSwSmi ## CONSUMES
+ gPlatformModuleTokenSpaceGuid.PcdApicIoIdPch ## CONSUMES
+
+################################################################################
+#
+# Protocol C Name Section - list of Protocol and Protocol Notify C Names
+# that this module uses or produces.
+#
+################################################################################
+[Protocols]
+
+[PPIs]
+
+[Guids]
+
+[Depex]
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AcpiTables/Dsdt/Dsdt.asl b/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AcpiTables/Dsdt/Dsdt.asl
new file mode 100644
index 0000000000..5a5a8698d6
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AcpiTables/Dsdt/Dsdt.asl
@@ -0,0 +1,32 @@
+/** @file
+ ACPI DSDT table
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "PlatformBoardId.h"
+#include <Include/AcpiDebug.h>
+
+
+DefinitionBlock (
+ "DSDT.aml",
+ "DSDT",
+ 0x02, // DSDT revision.
+ // A Revision field value greater than or equal to 2 signifies that integers
+ // declared within the Definition Block are to be evaluated as 64-bit values
+ "INTEL", // OEM ID (6 byte string)
+ "SKL ",// OEM table ID (8 byte string)
+ 0x0 // OEM version of DSDT table (4 byte Integer)
+)
+
+// BEGIN OF ASL SCOPE
+{
+ Name (SANB, 0xFFFF0000) // SA NVS Base address
+ Name (SANL, 0xAA55) // SA NVS Length
+
+ Include ("SaNvs.asl")
+ Include ("PciTree.asl")
+
+}// End of ASL File
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AcpiTables/Dsdt/PciTree.asl b/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AcpiTables/Dsdt/PciTree.asl
new file mode 100644
index 0000000000..bef0b6cccd
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AcpiTables/Dsdt/PciTree.asl
@@ -0,0 +1,17 @@
+/** @file
+ ACPI DSDT table
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+Scope(\_SB) {
+//---------------------------------------------------------------------------
+// Begin PCI tree object scope
+//---------------------------------------------------------------------------
+ Device(PC00) { // PCI Bridge "Host Bridge"
+ Name(_HID, EISAID("PNP0A08")) // Indicates PCI Express/PCI-X Mode2 host hierarchy
+ Include("HostBus.asl")
+ } // end PC00 Bridge "Host Bridge"
+} // end _SB scope
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AcpiTables/Ecdt/Ecdt.act b/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AcpiTables/Ecdt/Ecdt.act
new file mode 100644
index 0000000000..3e30b41d11
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AcpiTables/Ecdt/Ecdt.act
@@ -0,0 +1,103 @@
+/** @file
+ This file contains a structure definition for the ACPI Embedded Controller Boot
+ Resources Table (ECDT). The contents of this file should only be modified
+ for bug fixes, no porting is required.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+//
+// Statements that include other files
+//
+
+#include "Ecdt.h"
+
+//
+// Embedded Controller Boot Resources Table Structure
+//
+#pragma pack(1)
+typedef struct {
+ EFI_ACPI_5_0_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE ActionTable;
+ //
+ // ASCII, null terminated, string that contains a fully qualified
+ // reference to the namespace object that is this embedded controller device.
+ //
+ CHAR8 Ec_Id[40];
+} EFI_ACPI_EMBEDDED_CONTROLLER_BOOT_RESOURCES_ENTIRE_TABLE;
+#pragma pack()
+
+EFI_ACPI_EMBEDDED_CONTROLLER_BOOT_RESOURCES_ENTIRE_TABLE Ecdt = {
+ {
+ {
+ EFI_ACPI_5_0_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE_SIGNATURE,
+ sizeof (EFI_ACPI_5_0_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE) + 40,
+ EFI_ACPI_5_0_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE_REVISION,
+
+ //
+ // Checksum will be updated at runtime
+ //
+ 0x00,
+
+ //
+ // It is expected that these values will be updated at runtime
+ //
+ { ' ', ' ', ' ', ' ', ' ', ' ' },
+
+ 0,
+ EFI_ACPI_OEM_ECDT_REVISION,
+ 0,
+ 0
+ },
+
+ //
+ // EC_CONTROL Register Block
+ //
+ {
+ EFI_ACPI_5_0_SYSTEM_IO,
+ 8,
+ 0,
+ EFI_ACPI_RESERVED_BYTE,
+ 0x66
+ },
+
+ //
+ // EC_DATA Register Block
+ //
+ {
+ EFI_ACPI_5_0_SYSTEM_IO,
+ 8,
+ 0,
+ EFI_ACPI_RESERVED_BYTE,
+ 0x62
+ },
+
+ 1, // UID
+ 0 // GPE_BIT
+ },
+ "\\_SB.PC00.LPCB.H_EC" //EC_ID
+};
+
+#ifdef __GNUC__
+VOID*
+ReferenceAcpiTable (
+ VOID
+ )
+
+{
+ //
+ // Reference the table being generated to prevent the optimizer from removing the
+ // data structure from the exeutable
+ //
+ return (VOID*)&Ecdt;
+}
+#else
+VOID
+main (
+ VOID
+ )
+
+{
+}
+#endif
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AcpiTables/Ecdt/Ecdt.h b/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AcpiTables/Ecdt/Ecdt.h
new file mode 100644
index 0000000000..4afa4874d2
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AcpiTables/Ecdt/Ecdt.h
@@ -0,0 +1,26 @@
+/** @file
+ This file describes the contents of the ACPI Embedded Controller Boot
+ Resources Table (ECDT). All changes to the ECDT contents should be done
+ in this file.
+
+ Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+
+**/
+
+#ifndef _ECDT_H_
+#define _ECDT_H_
+
+//
+// Statements that include other files
+//
+
+#include <IndustryStandard/Acpi.h>
+
+//
+// ECDT Definitions
+//
+#define EFI_ACPI_OEM_ECDT_REVISION 0x00000001
+
+#endif
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AcpiTables/Facs/Facs.act b/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AcpiTables/Facs/Facs.act
new file mode 100644
index 0000000000..fde17b577c
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AcpiTables/Facs/Facs.act
@@ -0,0 +1,91 @@
+/** @file
+ This file contains a structure definition for the ACPI 5.0 Firmware ACPI
+ Control Structure (FACS). The contents of this file should only be modified
+ for bug fixes, no porting is required.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+//
+// Statements that include other files
+//
+
+#include "Facs.h"
+
+//
+// Firmware ACPI Control Structure
+// Please modify all values in Facs.h only.
+//
+
+EFI_ACPI_5_0_FIRMWARE_ACPI_CONTROL_STRUCTURE Facs = {
+ EFI_ACPI_5_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE,
+ sizeof (EFI_ACPI_5_0_FIRMWARE_ACPI_CONTROL_STRUCTURE),
+
+ //
+ // Hardware Signature will be updated at runtime
+ //
+ 0x00000000,
+
+ EFI_ACPI_FIRMWARE_WAKING_VECTOR,
+ EFI_ACPI_GLOBAL_LOCK,
+ EFI_ACPI_FIRMWARE_CONTROL_STRUCTURE_FLAGS,
+ EFI_ACPI_X_FIRMWARE_WAKING_VECTOR,
+ EFI_ACPI_5_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_VERSION,
+ {
+ EFI_ACPI_RESERVED_BYTE,
+ EFI_ACPI_RESERVED_BYTE,
+ EFI_ACPI_RESERVED_BYTE
+ },
+ EFI_ACPI_RESERVED_DWORD, //EFI_ACPI_5_0_OSPM_64BIT_WAKE_F
+ {
+ EFI_ACPI_RESERVED_BYTE,
+ EFI_ACPI_RESERVED_BYTE,
+ EFI_ACPI_RESERVED_BYTE,
+ EFI_ACPI_RESERVED_BYTE,
+ EFI_ACPI_RESERVED_BYTE,
+ EFI_ACPI_RESERVED_BYTE,
+ EFI_ACPI_RESERVED_BYTE,
+ EFI_ACPI_RESERVED_BYTE,
+ EFI_ACPI_RESERVED_BYTE,
+ EFI_ACPI_RESERVED_BYTE,
+ EFI_ACPI_RESERVED_BYTE,
+ EFI_ACPI_RESERVED_BYTE,
+ EFI_ACPI_RESERVED_BYTE,
+ EFI_ACPI_RESERVED_BYTE,
+ EFI_ACPI_RESERVED_BYTE,
+ EFI_ACPI_RESERVED_BYTE,
+ EFI_ACPI_RESERVED_BYTE,
+ EFI_ACPI_RESERVED_BYTE,
+ EFI_ACPI_RESERVED_BYTE,
+ EFI_ACPI_RESERVED_BYTE,
+ EFI_ACPI_RESERVED_BYTE,
+ EFI_ACPI_RESERVED_BYTE,
+ EFI_ACPI_RESERVED_BYTE,
+ EFI_ACPI_RESERVED_BYTE
+ }
+};
+
+#ifdef __GNUC__
+VOID*
+ReferenceAcpiTable (
+ VOID
+ )
+
+{
+ //
+ // Reference the table being generated to prevent the optimizer from removing the
+ // data structure from the exeutable
+ //
+ return (VOID*)&Facs;
+}
+#else
+VOID
+main (
+ VOID
+ )
+
+{
+}
+#endif
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AcpiTables/Facs/Facs.h b/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AcpiTables/Facs/Facs.h
new file mode 100644
index 0000000000..711d952583
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AcpiTables/Facs/Facs.h
@@ -0,0 +1,34 @@
+/** @file
+ This file describes the contents of the ACPI Firmware ACPI Control
+ Structure (FACS). All changes to the FACS contents should be done
+ in this file.
+
+ Copyright (c) 1999 - 2017, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _FACS_H_
+#define _FACS_H_
+
+//
+// Statements that include other files
+//
+
+#include <IndustryStandard/Acpi.h>
+
+//
+// FACS Definitions
+//
+
+#define EFI_ACPI_FIRMWARE_WAKING_VECTOR 0x00000000
+#define EFI_ACPI_GLOBAL_LOCK 0x00000000
+
+//
+// Firmware Control Structure Feature Flags are defined in AcpiX.0.h
+//
+#define EFI_ACPI_FIRMWARE_CONTROL_STRUCTURE_FLAGS 0x00000000
+
+#define EFI_ACPI_X_FIRMWARE_WAKING_VECTOR 0x0000000000000000
+
+#endif
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AcpiTables/Fadt/Fadt6.3.act b/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AcpiTables/Fadt/Fadt6.3.act
new file mode 100644
index 0000000000..5acc63d744
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AcpiTables/Fadt/Fadt6.3.act
@@ -0,0 +1,236 @@
+/** @file
+ This file contains a structure definition for the ACPI 6.1 Fixed ACPI
+ Description Table (FADT). The contents of this file should only be modified
+ for bug fixes, no porting is required.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+//
+// Statements that include other files
+//
+
+#include "Fadt6.3.h"
+
+//
+// Fixed ACPI Description Table
+// Please modify all values in Fadt.h only.
+//
+
+EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE Fadt = {
+ {
+ EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE,
+ sizeof (EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE),
+ EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE_REVISION,
+
+ //
+ // Checksum will be updated at runtime
+ //
+ 0x00,
+
+ //
+ // It is expected that these values will be updated at runtime
+ //
+ { ' ', ' ', ' ', ' ', ' ', ' ' },
+
+ 0,
+ EFI_ACPI_OEM_FADT_REVISION,
+ 0,
+ 0
+ },
+
+ //
+ // These addresses will be updated at runtime
+ //
+ 0x00000000,
+ 0x00000000,
+
+ EFI_ACPI_RESERVED_BYTE,
+ EFI_ACPI_PREFERRED_PM_PROFILE,
+ EFI_ACPI_SCI_INT,
+ EFI_ACPI_SMI_CMD,
+ FixedPcdGet8 (PcdAcpiEnableSwSmi),
+ FixedPcdGet8 (PcdAcpiDisableSwSmi),
+ EFI_ACPI_S4_BIOS_REQ,
+ EFI_ACPI_PSTATE_CNT,
+
+ EFI_ACPI_PM1A_EVT_BLK_ADDRESS,
+ EFI_ACPI_PM1B_EVT_BLK_ADDRESS,
+ EFI_ACPI_PM1A_CNT_BLK_ADDRESS,
+ EFI_ACPI_PM1B_CNT_BLK_ADDRESS,
+ EFI_ACPI_PM2_CNT_BLK_ADDRESS,
+ EFI_ACPI_PM_TMR_BLK_ADDRESS,
+ EFI_ACPI_GPE0_BLK_ADDRESS,
+ EFI_ACPI_GPE1_BLK_ADDRESS,
+ EFI_ACPI_PM1_EVT_LEN,
+ EFI_ACPI_PM1_CNT_LEN,
+ EFI_ACPI_PM2_CNT_LEN,
+ EFI_ACPI_PM_TMR_LEN,
+ EFI_ACPI_GPE0_BLK_LEN,
+ EFI_ACPI_GPE1_BLK_LEN,
+ EFI_ACPI_GPE1_BASE,
+
+ //
+ // Latest OS have C-State capability and CST_CNT SMI doesn't need to be defined.
+ // CST_CNT SMI is not handled in BIOS and it can be removed safely.
+ //
+ EFI_ACPI_CST_CNT,
+ EFI_ACPI_P_LVL2_LAT,
+ EFI_ACPI_P_LVL3_LAT,
+ EFI_ACPI_FLUSH_SIZE,
+ EFI_ACPI_FLUSH_STRIDE,
+ EFI_ACPI_DUTY_OFFSET,
+ EFI_ACPI_DUTY_WIDTH,
+ EFI_ACPI_DAY_ALRM,
+ EFI_ACPI_MON_ALRM,
+ EFI_ACPI_CENTURY,
+ EFI_ACPI_IAPC_BOOT_ARCH,
+ EFI_ACPI_RESERVED_BYTE,
+ EFI_ACPI_FIXED_FEATURE_FLAGS,
+
+ //
+ // Reset Register Block
+ //
+ {
+ EFI_ACPI_RESET_REG_ADDRESS_SPACE_ID,
+ EFI_ACPI_RESET_REG_BIT_WIDTH,
+ EFI_ACPI_RESET_REG_BIT_OFFSET,
+ EFI_ACPI_6_3_BYTE,
+ EFI_ACPI_RESET_REG_ADDRESS
+ },
+ EFI_ACPI_RESET_VALUE,
+ 0, // ArmBootArch
+ EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE_MINOR_REVISION,
+
+ //
+ // These addresses will be updated at runtime
+ //
+ 0x0000000000000000, // X_FIRMWARE_CTRL
+ 0x0000000000000000, // X_DSDT
+
+ {
+ //
+ // X_PM1a Event Register Block
+ //
+ EFI_ACPI_PM1A_EVT_BLK_ADDRESS_SPACE_ID,
+ EFI_ACPI_PM1A_EVT_BLK_BIT_WIDTH,
+ EFI_ACPI_PM1A_EVT_BLK_BIT_OFFSET,
+ EFI_ACPI_6_3_WORD,
+ EFI_ACPI_PM1A_EVT_BLK_ADDRESS
+ },
+ {
+ //
+ // X_PM1b Event Register Block
+ //
+ EFI_ACPI_PM1B_EVT_BLK_ADDRESS_SPACE_ID,
+ EFI_ACPI_PM1B_EVT_BLK_BIT_WIDTH,
+ EFI_ACPI_PM1B_EVT_BLK_BIT_OFFSET,
+ EFI_ACPI_6_3_WORD,
+ EFI_ACPI_PM1B_EVT_BLK_ADDRESS
+ },
+ {
+ //
+ // X_PM1a Control Register Block
+ //
+ EFI_ACPI_PM1A_CNT_BLK_ADDRESS_SPACE_ID,
+ EFI_ACPI_PM1A_CNT_BLK_BIT_WIDTH,
+ EFI_ACPI_PM1A_CNT_BLK_BIT_OFFSET,
+ EFI_ACPI_6_3_WORD,
+ EFI_ACPI_PM1A_CNT_BLK_ADDRESS
+ },
+ {
+ //
+ // X_PM1b Control Register Block
+ //
+ EFI_ACPI_PM1B_CNT_BLK_ADDRESS_SPACE_ID,
+ EFI_ACPI_PM1B_CNT_BLK_BIT_WIDTH,
+ EFI_ACPI_PM1B_CNT_BLK_BIT_OFFSET,
+ EFI_ACPI_6_3_WORD,
+ EFI_ACPI_PM1B_CNT_BLK_ADDRESS
+ },
+ {
+ //
+ // X_PM2 Control Register Block
+ //
+ EFI_ACPI_PM2_CNT_BLK_ADDRESS_SPACE_ID,
+ EFI_ACPI_PM2_CNT_BLK_BIT_WIDTH,
+ EFI_ACPI_PM2_CNT_BLK_BIT_OFFSET,
+ EFI_ACPI_6_3_BYTE,
+ EFI_ACPI_PM2_CNT_BLK_ADDRESS
+ },
+ {
+ //
+ // X_PM Timer Control Register Block
+ //
+ EFI_ACPI_PM_TMR_BLK_ADDRESS_SPACE_ID,
+ EFI_ACPI_PM_TMR_BLK_BIT_WIDTH,
+ EFI_ACPI_PM_TMR_BLK_BIT_OFFSET,
+ EFI_ACPI_6_3_DWORD,
+ EFI_ACPI_PM_TMR_BLK_ADDRESS
+ },
+ {
+ //
+ // X_General Purpose Event 0 Register Block
+ //
+ EFI_ACPI_GPE0_BLK_ADDRESS_SPACE_ID,
+ 0x0,
+ EFI_ACPI_GPE0_BLK_BIT_OFFSET,
+ EFI_ACPI_6_3_BYTE,
+ EFI_ACPI_GPE0_BLK_ADDRESS
+ },
+ {
+ //
+ // X_General Purpose Event 1 Register Block
+ //
+ EFI_ACPI_GPE1_BLK_ADDRESS_SPACE_ID,
+ EFI_ACPI_GPE1_BLK_BIT_WIDTH,
+ EFI_ACPI_GPE1_BLK_BIT_OFFSET,
+ EFI_ACPI_6_3_BYTE,
+ EFI_ACPI_GPE1_BLK_ADDRESS
+ },
+ {
+ //
+ // Sleep Control Reg - update in DXE driver
+ //
+ 0,
+ 0,
+ 0,
+ 0,
+ 0
+ },
+ {
+ //
+ // Sleep Status Reg - update in DXE driver
+ //
+ 0,
+ 0,
+ 0,
+ 0,
+ 0
+ },
+ 0 // HypervisorVendorIdentity
+};
+
+#ifdef __GNUC__
+VOID*
+ReferenceAcpiTable (
+ VOID
+ )
+
+{
+ //
+ // Reference the table being generated to prevent the optimizer from removing the
+ // data structure from the exeutable
+ //
+ return (VOID*)&Fadt;
+}
+#else
+VOID
+main (
+ VOID
+ )
+{
+}
+#endif
\ No newline at end of file
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AcpiTables/Fadt/Fadt6.3.h b/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AcpiTables/Fadt/Fadt6.3.h
new file mode 100644
index 0000000000..e2dffeb13c
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AcpiTables/Fadt/Fadt6.3.h
@@ -0,0 +1,184 @@
+/** @file
+ This file describes the contents of the ACPI Fixed ACPI Description Table
+ (FADT). All changes to the FADT contents should be done in this file.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _FADT_H_
+#define _FADT_H_
+
+//
+// Statements that include other files
+//
+
+#include <IndustryStandard/Acpi.h>
+
+#include "Register/PmcRegs.h"
+#include "Register/TcoRegs.h"
+
+//
+// FADT Definitions
+//
+#ifndef EFI_ACPI_OEM_FADT_REVISION
+#define EFI_ACPI_OEM_FADT_REVISION 0x00000000
+#endif
+
+//
+// For ACPI 1.0 support
+//
+/*
+1 Desktop
+2 Mobile
+3 Workstation
+4 Enterprise Server
+5 SOHO Server
+6 Appliance PC
+7 Performance Server
+*/
+#define EFI_ACPI_PREFERRED_PM_PROFILE 0x01
+#define EFI_ACPI_SCI_INT 0x0009
+#define EFI_ACPI_SMI_CMD 0x000000B2
+#define EFI_ACPI_S4_BIOS_REQ 0xF2
+#define EFI_ACPI_PSTATE_CNT 0x00
+#define EFI_ACPI_GPE1_BASE 0x10
+#define EFI_ACPI_CST_CNT 0x0
+#define EFI_ACPI_P_LVL2_LAT 101
+#define EFI_ACPI_P_LVL3_LAT 1001
+#define EFI_ACPI_FLUSH_SIZE 0x0000
+#define EFI_ACPI_FLUSH_STRIDE 0x0000
+#define EFI_ACPI_DUTY_OFFSET 0x01
+#define EFI_ACPI_DUTY_WIDTH 0x03
+#define EFI_ACPI_DAY_ALRM 0x0D
+#define EFI_ACPI_MON_ALRM 0x00
+#define EFI_ACPI_CENTURY 0x32
+
+//
+// IA-PC Boot Architecture Flags, see ACPI 6.3 table specification and Acpi61.h
+// We should not use EFI_ACPI_6_3_8042 for legacy free platform, or XP reset fail. No impact to mobile.
+//
+#define EFI_ACPI_IAPC_BOOT_ARCH (EFI_ACPI_6_3_LEGACY_DEVICES)
+
+//
+// Fixed Feature Flags, see ACPI 6.3 table specification and Acpi6_3.h
+//
+#define EFI_ACPI_FIXED_FEATURE_FLAGS (\
+ EFI_ACPI_6_3_USE_PLATFORM_CLOCK | \
+ EFI_ACPI_6_3_WBINVD | \
+ EFI_ACPI_6_3_DCK_CAP | \
+ EFI_ACPI_6_3_FIX_RTC | \
+ EFI_ACPI_6_3_RTC_S4 | \
+ EFI_ACPI_6_3_SLP_BUTTON | \
+ EFI_ACPI_6_3_PROC_C1 | \
+ EFI_ACPI_6_3_RESET_REG_SUP \
+ )
+
+//
+// PM1A Event Register Block Generic Address Information
+//
+#define EFI_ACPI_PM1A_EVT_BLK_ADDRESS_SPACE_ID EFI_ACPI_6_3_SYSTEM_IO
+#define EFI_ACPI_PM1A_EVT_BLK_BIT_WIDTH 0x20
+#define EFI_ACPI_PM1A_EVT_BLK_BIT_OFFSET 0x00
+#define EFI_ACPI_PM1A_EVT_BLK_ADDRESS FixedPcdGet16 (PcdAcpiBaseAddress)
+
+//
+// PM1B Event Register Block Generic Address Information
+//
+#define EFI_ACPI_PM1B_EVT_BLK_ADDRESS_SPACE_ID EFI_ACPI_6_3_SYSTEM_IO
+#define EFI_ACPI_PM1B_EVT_BLK_BIT_WIDTH 0x00
+#define EFI_ACPI_PM1B_EVT_BLK_BIT_OFFSET 0x00
+#define EFI_ACPI_PM1B_EVT_BLK_ADDRESS 0x0000000000000000
+
+//
+// PM1A Control Register Block Generic Address Information
+//
+#define EFI_ACPI_PM1A_CNT_BLK_ADDRESS_SPACE_ID EFI_ACPI_6_3_SYSTEM_IO
+#define EFI_ACPI_PM1A_CNT_BLK_BIT_WIDTH 0x10
+#define EFI_ACPI_PM1A_CNT_BLK_BIT_OFFSET 0x00
+#define EFI_ACPI_PM1A_CNT_BLK_ADDRESS (EFI_ACPI_PM1A_EVT_BLK_ADDRESS + 0x04)
+
+//
+// PM1B Control Register Block Generic Address Information
+//
+#define EFI_ACPI_PM1B_CNT_BLK_ADDRESS_SPACE_ID EFI_ACPI_6_3_SYSTEM_IO
+#define EFI_ACPI_PM1B_CNT_BLK_BIT_WIDTH 0x00
+#define EFI_ACPI_PM1B_CNT_BLK_BIT_OFFSET 0x00
+#define EFI_ACPI_PM1B_CNT_BLK_ADDRESS 0x0000000000000000
+
+//
+// PM2 Control Register Block Generic Address Information
+//
+#define EFI_ACPI_PM2_CNT_BLK_ADDRESS_SPACE_ID EFI_ACPI_6_3_SYSTEM_IO
+#define EFI_ACPI_PM2_CNT_BLK_BIT_WIDTH 0x08
+#define EFI_ACPI_PM2_CNT_BLK_BIT_OFFSET 0x00
+#define EFI_ACPI_PM2_CNT_BLK_ADDRESS (EFI_ACPI_PM1A_EVT_BLK_ADDRESS + 0x50)
+
+//
+// Power Management Timer Control Register Block Generic Address
+// Information
+//
+#define EFI_ACPI_PM_TMR_BLK_ADDRESS_SPACE_ID EFI_ACPI_6_3_SYSTEM_IO
+#define EFI_ACPI_PM_TMR_BLK_BIT_WIDTH 0x20
+#define EFI_ACPI_PM_TMR_BLK_BIT_OFFSET 0x00
+#define EFI_ACPI_PM_TMR_BLK_ADDRESS (EFI_ACPI_PM1A_EVT_BLK_ADDRESS + 0x08)
+
+//
+// General Purpose Event 0 Register Block Generic Address
+// Information
+//
+#define EFI_ACPI_GPE0_BLK_ADDRESS_SPACE_ID EFI_ACPI_6_3_SYSTEM_IO
+#define EFI_ACPI_GPE0_BLK_BIT_WIDTH 0x100
+#define EFI_ACPI_GPE0_BLK_BIT_OFFSET 0x00
+#define EFI_ACPI_GPE0_BLK_ADDRESS 0x00
+
+//
+// General Purpose Event 1 Register Block Generic Address
+// Information
+//
+#define EFI_ACPI_GPE1_BLK_ADDRESS_SPACE_ID EFI_ACPI_6_3_SYSTEM_IO
+#define EFI_ACPI_GPE1_BLK_BIT_WIDTH 0x00
+#define EFI_ACPI_GPE1_BLK_BIT_OFFSET 0x00
+#define EFI_ACPI_GPE1_BLK_ADDRESS 0x0000000000000000
+
+//
+// Reset Register Generic Address Information
+//
+#define EFI_ACPI_RESET_REG_ADDRESS_SPACE_ID EFI_ACPI_6_3_SYSTEM_IO
+#define EFI_ACPI_RESET_REG_BIT_WIDTH 0x08
+#define EFI_ACPI_RESET_REG_BIT_OFFSET 0x00
+#define EFI_ACPI_RESET_REG_ADDRESS 0x0000000000000CF9
+#define EFI_ACPI_RESET_VALUE 0x06
+
+//
+// Number of bytes decoded by PM1 event blocks (a and b)
+//
+#define EFI_ACPI_PM1_EVT_LEN ((EFI_ACPI_PM1A_EVT_BLK_BIT_WIDTH + EFI_ACPI_PM1B_EVT_BLK_BIT_WIDTH) / 8)
+
+//
+// Number of bytes decoded by PM1 control blocks (a and b)
+//
+#define EFI_ACPI_PM1_CNT_LEN ((EFI_ACPI_PM1A_CNT_BLK_BIT_WIDTH + EFI_ACPI_PM1B_CNT_BLK_BIT_WIDTH) / 8)
+
+//
+// Number of bytes decoded by PM2 control block
+//
+#define EFI_ACPI_PM2_CNT_LEN (EFI_ACPI_PM2_CNT_BLK_BIT_WIDTH / 8)
+
+//
+// Number of bytes decoded by PM timer block
+//
+#define EFI_ACPI_PM_TMR_LEN (EFI_ACPI_PM_TMR_BLK_BIT_WIDTH / 8)
+
+//
+// Number of bytes decoded by GPE0 block
+//
+#define EFI_ACPI_GPE0_BLK_LEN (EFI_ACPI_GPE0_BLK_BIT_WIDTH / 8)
+
+//
+// Number of bytes decoded by GPE1 block
+//
+#define EFI_ACPI_GPE1_BLK_LEN (EFI_ACPI_GPE1_BLK_BIT_WIDTH / 8)
+
+#endif
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AcpiTables/Hpet/Hpet.act b/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AcpiTables/Hpet/Hpet.act
new file mode 100644
index 0000000000..c4b87cecdd
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AcpiTables/Hpet/Hpet.act
@@ -0,0 +1,77 @@
+/** @file
+ This file contains a structure definition for the ACPI 1.0 High Precision Event Timer
+ Description Table (HPET). The contents of this file should only be modified
+ for bug fixes, no porting is required.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+//
+// Statements that include other files
+//
+
+#include "Hpet.h"
+
+//
+// High Precision Event Timer Table
+// Please modify all values in Hpet.h only.
+//
+
+EFI_ACPI_HIGH_PRECISION_EVENT_TIMER_TABLE_HEADER Fadt = {
+ {
+ EFI_ACPI_3_0_HIGH_PRECISION_EVENT_TIMER_TABLE_SIGNATURE,
+ sizeof (EFI_ACPI_HIGH_PRECISION_EVENT_TIMER_TABLE_HEADER),
+ EFI_ACPI_HIGH_PRECISION_EVENT_TIMER_TABLE_REVISION,
+
+ //
+ // Checksum will be updated at runtime
+ //
+ 0x00,
+
+ //
+ // It is expected that these values will be updated at runtime
+ //
+ { ' ', ' ', ' ', ' ', ' ', ' ' },
+
+ 0,
+ EFI_ACPI_OEM_HPET_REVISION,
+ 0,
+ 0
+ },
+
+ EFI_ACPI_EVENT_TIMER_BLOCK_ID,
+ {
+ EFI_ACPI_EVENT_TIMER_BLOCK_ADDRESS_SPACE_ID,
+ EFI_ACPI_EVENT_TIMER_BLOCK_BIT_WIDTH,
+ EFI_ACPI_EVENT_TIMER_BLOCK_BIT_OFFSET,
+ EFI_ACPI_EVENT_TIMER_ACCESS_SIZE,
+ EFI_ACPI_EVENT_TIMER_BLOCK_ADDRESS
+ },
+ EFI_ACPI_HPET_NUMBER,
+ EFI_ACPI_MIN_CLOCK_TICK,
+ EFI_ACPI_HPET_ATTRIBUTES
+};
+
+#ifdef __GNUC__
+VOID*
+ReferenceAcpiTable (
+ VOID
+ )
+
+{
+ //
+ // Reference the table being generated to prevent the optimizer from removing the
+ // data structure from the exeutable
+ //
+ return (VOID*)&Fadt;
+}
+#else
+VOID
+main (
+ VOID
+ )
+{
+}
+#endif
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AcpiTables/Hpet/Hpet.h b/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AcpiTables/Hpet/Hpet.h
new file mode 100644
index 0000000000..7a0b3b7a59
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AcpiTables/Hpet/Hpet.h
@@ -0,0 +1,43 @@
+/** @file
+ This file describes the contents of the ACPI High Precision Event Timer Description Table
+ (HPET). All changes to the HPET contents should be done in this file.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _HPET_H_
+#define _HPET_H_
+
+//
+// Statements that include other files
+//
+
+#include <IndustryStandard/Acpi30.h>
+#include <IndustryStandard/HighPrecisionEventTimerTable.h>
+
+//
+// HPET Definitions
+//
+
+#define EFI_ACPI_OEM_HPET_REVISION 0x00000001
+
+#define EFI_ACPI_EVENT_TIMER_BLOCK_ID 0x8086A201
+
+//
+// Event Timer Block Base Address Information
+//
+#define EFI_ACPI_EVENT_TIMER_BLOCK_ADDRESS_SPACE_ID EFI_ACPI_3_0_SYSTEM_MEMORY
+#define EFI_ACPI_EVENT_TIMER_BLOCK_BIT_WIDTH 0x40
+#define EFI_ACPI_EVENT_TIMER_BLOCK_BIT_OFFSET 0x00
+#define EFI_ACPI_EVENT_TIMER_ACCESS_SIZE 0x00
+#define EFI_ACPI_EVENT_TIMER_BLOCK_ADDRESS 0x00000000FED00000
+
+#define EFI_ACPI_HPET_NUMBER 0x00
+
+#define EFI_ACPI_MIN_CLOCK_TICK 0x0080
+
+#define EFI_ACPI_HPET_ATTRIBUTES 0x00
+
+#endif
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AcpiTables/Include/AcpiCommon.h b/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AcpiTables/Include/AcpiCommon.h
new file mode 100644
index 0000000000..f689c7e339
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AcpiTables/Include/AcpiCommon.h
@@ -0,0 +1,16 @@
+/** @file
+ Header file for ACPI common Initialization Driver.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _ACPI_COMMON_H_
+#define _ACPI_COMMON_H_
+
+
+
+
+
+#endif
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AcpiTables/Madt/Madt.act b/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AcpiTables/Madt/Madt.act
new file mode 100644
index 0000000000..9bb0884219
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AcpiTables/Madt/Madt.act
@@ -0,0 +1,573 @@
+/** @file
+ This file contains a structure definition for the ACPI 2.0 Multiple APIC
+ Description Table (MADT). Any changes to the MADT table require updating the
+ respective structure count in Madt.h and then adding the structure to the
+ MADT defined in this file.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+//
+// Statements that include other files
+//
+
+#include "Madt.h"
+
+//
+// Multiple APIC Description Table
+//
+
+EFI_ACPI_6_3_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = {
+ {
+ {
+ EFI_ACPI_6_3_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE,
+ sizeof (EFI_ACPI_6_3_MULTIPLE_APIC_DESCRIPTION_TABLE),
+ EFI_ACPI_6_3_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION,
+
+ //
+ // Checksum will be updated at runtime
+ //
+ 0x00,
+
+ //
+ // It is expected that these values will be programmed at runtime
+ //
+ { ' ', ' ', ' ', ' ', ' ', ' ' },
+
+ 0,
+ EFI_ACPI_OEM_MADT_REVISION,
+ 0,
+ 0
+ },
+
+ //
+ // MADT specific fields
+ //
+ FixedPcdGet64 (PcdApicLocalAddress),
+ EFI_ACPI_6_3_MULTIPLE_APIC_FLAGS
+ },
+
+ //
+ // Sample Processor Local APIC Structure
+ //
+ //EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC, // Type
+ //sizeof (EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC_STRUCTURE), // Length
+ //0x00 // Processor ID
+ //0x00 // Local APIC ID
+ //0x00000000, // Flags - Disabled (until initialized by platform driver)
+ {
+ {
+ EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC, // Type
+ sizeof (EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC_STRUCTURE), // Length
+ 0x01, // Processor ID
+ 0xFF, // Local APIC ID
+ 0x00000000 // Flags - Disabled (until initialized by platform driver)
+ },
+ {
+ EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC, // Type
+ sizeof (EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC_STRUCTURE), // Length
+ 0x02, // Processor ID
+ 0xFF, // Local APIC ID
+ 0x00000000 // Flags - Disabled (until initialized by platform driver)
+ },
+ {
+ EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC, // Type
+ sizeof (EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC_STRUCTURE), // Length
+ 0x03, // Processor ID
+ 0xFF, // Local APIC ID
+ 0x00000000 // Flags - Disabled (until initialized by platform driver)
+ },
+ {
+ EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC, // Type
+ sizeof (EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC_STRUCTURE), // Length
+ 0x04, // Processor ID
+ 0xFF, // Local APIC ID
+ 0x00000000 // Flags - Disabled (until initialized by platform driver)
+ },
+ {
+ EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC, // Type
+ sizeof (EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC_STRUCTURE), // Length
+ 0x05, // Processor ID
+ 0xFF, // Local APIC ID
+ 0x00000000 // Flags - Disabled (until initialized by platform driver)
+ },
+ {
+ EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC, // Type
+ sizeof (EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC_STRUCTURE), // Length
+ 0x06, // Processor ID
+ 0xFF, // Local APIC ID
+ 0x00000000 // Flags - Disabled (until initialized by platform driver)
+ },
+ {
+ EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC, // Type
+ sizeof (EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC_STRUCTURE), // Length
+ 0x07, // Processor ID
+ 0xFF, // Local APIC ID
+ 0x00000000 // Flags - Disabled (until initialized by platform driver)
+ },
+ {
+ EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC, // Type
+ sizeof (EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC_STRUCTURE), // Length
+ 0x08, // Processor ID
+ 0xFF, // Local APIC ID
+ 0x00000000 // Flags - Disabled (until initialized by platform driver)
+ },
+ {
+ EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC, // Type
+ sizeof (EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC_STRUCTURE), // Length
+ 0x09, // Processor ID
+ 0xFF, // Local APIC ID
+ 0x00000000 // Flags - Disabled (until initialized by platform driver)
+ },
+ {
+ EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC, // Type
+ sizeof (EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC_STRUCTURE), // Length
+ 0x0A, // Processor ID
+ 0xFF, // Local APIC ID
+ 0x00000000 // Flags - Disabled (until initialized by platform driver)
+ },
+ {
+ EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC, // Type
+ sizeof (EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC_STRUCTURE), // Length
+ 0x0B, // Processor ID
+ 0xFF, // Local APIC ID
+ 0x00000000 // Flags - Disabled (until initialized by platform driver)
+ },
+ {
+ EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC, // Type
+ sizeof (EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC_STRUCTURE), // Length
+ 0x0C, // Processor ID
+ 0xFF, // Local APIC ID
+ 0x00000000 // Flags - Disabled (until initialized by platform driver)
+ },
+ {
+ EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC, // Type
+ sizeof (EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC_STRUCTURE), // Length
+ 0x0D, // Processor ID
+ 0xFF, // Local APIC ID
+ 0x00000000 // Flags - Disabled (until initialized by platform driver)
+ },
+ {
+ EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC, // Type
+ sizeof (EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC_STRUCTURE), // Length
+ 0x0E, // Processor ID
+ 0xFF, // Local APIC ID
+ 0x00000000 // Flags - Disabled (until initialized by platform driver)
+ },
+ {
+ EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC, // Type
+ sizeof (EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC_STRUCTURE), // Length
+ 0x0F, // Processor ID
+ 0xFF, // Local APIC ID
+ 0x00000000 // Flags - Disabled (until initialized by platform driver)
+ },
+ {
+ EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC, // Type
+ sizeof (EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC_STRUCTURE), // Length
+ 0x10, // Processor ID
+ 0xFF, // Local APIC ID
+ 0x00000000 // Flags - Disabled (until initialized by platform driver)
+ },
+ {
+ EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC, // Type
+ sizeof (EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC_STRUCTURE), // Length
+ 0x11, // Processor ID
+ 0xFF, // Local APIC ID
+ 0x00000000 // Flags - Disabled (until initialized by platform driver)
+ },
+ {
+ EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC, // Type
+ sizeof (EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC_STRUCTURE), // Length
+ 0x12, // Processor ID
+ 0xFF, // Local APIC ID
+ 0x00000000 // Flags - Disabled (until initialized by platform driver)
+ },
+ {
+ EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC, // Type
+ sizeof (EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC_STRUCTURE), // Length
+ 0x13, // Processor ID
+ 0xFF, // Local APIC ID
+ 0x00000000 // Flags - Disabled (until initialized by platform driver)
+ },
+ {
+ EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC, // Type
+ sizeof (EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC_STRUCTURE), // Length
+ 0x14, // Processor ID
+ 0xFF, // Local APIC ID
+ 0x00000000 // Flags - Disabled (until initialized by platform driver)
+ },
+ {
+ EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC, // Type
+ sizeof (EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC_STRUCTURE), // Length
+ 0x15, // Processor ID
+ 0xFF, // Local APIC ID
+ 0x00000000 // Flags - Disabled (until initialized by platform driver)
+ },
+ {
+ EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC, // Type
+ sizeof (EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC_STRUCTURE), // Length
+ 0x16, // Processor ID
+ 0xFF, // Local APIC ID
+ 0x00000000 // Flags - Disabled (until initialized by platform driver)
+ },
+ {
+ EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC, // Type
+ sizeof (EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC_STRUCTURE), // Length
+ 0x17, // Processor ID
+ 0xFF, // Local APIC ID
+ 0x00000000 // Flags - Disabled (until initialized by platform driver)
+ },
+ {
+ EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC, // Type
+ sizeof (EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC_STRUCTURE), // Length
+ 0x18, // Processor ID
+ 0xFF, // Local APIC ID
+ 0x00000000 // Flags - Disabled (until initialized by platform driver)
+ },
+ {
+ EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC, // Type
+ sizeof (EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC_STRUCTURE), // Length
+ 0x19, // Processor ID
+ 0xFF, // Local APIC ID
+ 0x00000000 // Flags - Disabled (until initialized by platform driver)
+ },
+ {
+ EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC, // Type
+ sizeof (EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC_STRUCTURE), // Length
+ 0x1A, // Processor ID
+ 0xFF, // Local APIC ID
+ 0x00000000 // Flags - Disabled (until initialized by platform driver)
+ },
+ {
+ EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC, // Type
+ sizeof (EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC_STRUCTURE), // Length
+ 0x1B, // Processor ID
+ 0xFF, // Local APIC ID
+ 0x00000000 // Flags - Disabled (until initialized by platform driver)
+ },
+ {
+ EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC, // Type
+ sizeof (EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC_STRUCTURE), // Length
+ 0x1C, // Processor ID
+ 0xFF, // Local APIC ID
+ 0x00000000 // Flags - Disabled (until initialized by platform driver)
+ },
+ {
+ EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC, // Type
+ sizeof (EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC_STRUCTURE), // Length
+ 0x1D, // Processor ID
+ 0xFF, // Local APIC ID
+ 0x00000000 // Flags - Disabled (until initialized by platform driver)
+ },
+ {
+ EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC, // Type
+ sizeof (EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC_STRUCTURE), // Length
+ 0x1E, // Processor ID
+ 0xFF, // Local APIC ID
+ 0x00000000 // Flags - Disabled (until initialized by platform driver)
+ },
+ {
+ EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC, // Type
+ sizeof (EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC_STRUCTURE), // Length
+ 0x1F, // Processor ID
+ 0xFF, // Local APIC ID
+ 0x00000000 // Flags - Disabled (until initialized by platform driver)
+ },
+ {
+ EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC, // Type
+ sizeof (EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC_STRUCTURE), // Length
+ 0x20, // Processor ID
+ 0xFF, // Local APIC ID
+ 0x00000000 // Flags - Disabled (until initialized by platform driver)
+ }
+ },
+
+ //
+ // Sample IO APIC Structure
+ //
+ //EFI_ACPI_6_3_IO_APIC, // Type
+ //sizeof (EFI_ACPI_6_3_IO_APIC_STRUCTURE), // Length
+ //0x00, // IO APIC ID
+ //EFI_ACPI_RESERVED_BYTE, // Reserved
+ //0x00000000, // IO APIC Address (physical)
+ //0x00000000, // Global System Interrupt Base
+ {
+ {
+ //
+ // I/O SAPIC (ICH)
+ //
+ EFI_ACPI_6_3_IO_APIC, // Type
+ sizeof (EFI_ACPI_6_3_IO_APIC_STRUCTURE), // Length
+ FixedPcdGet8 (PcdApicIoIdPch), // IO APIC ID
+ EFI_ACPI_RESERVED_BYTE, // Reserved
+ FixedPcdGet64 (PcdApicIoAddress), // IO APIC Address (physical)
+ 0x18 * 0 // Global System Interrupt Base
+ }
+ },
+ //
+ // Sample Interrupt Source Override Structure
+ //
+ //EFI_ACPI_6_3_INTERRUPT_SOURCE_OVERRIDE, // Type
+ //sizeof (EFI_ACPI_6_3_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE), // Length
+ //0x00, // Bus
+ //0x00, // Source
+ //0x00000000, // Global System Interrupt
+ //0x0000, // Flags
+ {
+ {
+ //
+ // IRQ0=>IRQ2 Interrupt Source Override Structure
+ //
+ EFI_ACPI_6_3_INTERRUPT_SOURCE_OVERRIDE, // Type
+ sizeof (EFI_ACPI_6_3_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE),// Length
+ 0x00, // Bus - ISA
+ 0x00, // Source - IRQ0
+ 0x00000002, // Global System Interrupt - IRQ2
+ 0x0000 // Flags - Conforms to specifications of the bus
+ },
+ {
+ //
+ // ISO (SCI Active High) Interrupt Source Override Structure
+ //
+ EFI_ACPI_6_3_INTERRUPT_SOURCE_OVERRIDE, // Type
+ sizeof (EFI_ACPI_6_3_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE),// Length
+ 0x00, // Bus - ISA
+ 0x09, // Source - IRQ9
+ 0x00000009, // Global System Interrupt - IRQ9
+ 0x000D // Flags - Level-tiggered, Active High
+ }
+ },
+ //
+ // Sample Non-Maskable Interrupt Source Structure
+ //
+ //EFI_ACPI_6_3_NON_MASKABLE_INTERRUPT_SOURCE, // Type
+ //sizeof (EFI_ACPI_6_3_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE), // Length
+ //0x0000, // Flags
+ //0x00000000, // Global System Interrupt
+
+ //
+ // Sample Local APIC NMI Structure
+ //
+ //EFI_ACPI_6_3_LOCAL_APIC_NMI, // Type
+ //sizeof (EFI_ACPI_6_3_LOCAL_APIC_NMI_STRUCTURE), // Length
+ //0x00, // ACPI Processor ID
+ //0x0000, // Flags
+ //0x00, // Local APIC LINT#
+
+ {
+ {
+ EFI_ACPI_6_3_LOCAL_APIC_NMI, // Type
+ sizeof (EFI_ACPI_6_3_LOCAL_APIC_NMI_STRUCTURE), // Length
+ 0x01, // ACPI Processor ID
+ 0x0005, // Flags - Edge-tiggered, Active High
+ 0x01 // Local APIC LINT#
+ },
+ {
+ EFI_ACPI_6_3_LOCAL_APIC_NMI, // Type
+ sizeof (EFI_ACPI_6_3_LOCAL_APIC_NMI_STRUCTURE), // Length
+ 0x02, // ACPI Processor ID
+ 0x0005, // Flags - Edge-tiggered, Active High
+ 0x01 // Local APIC LINT#
+ },
+ {
+ EFI_ACPI_6_3_LOCAL_APIC_NMI, // Type
+ sizeof (EFI_ACPI_6_3_LOCAL_APIC_NMI_STRUCTURE), // Length
+ 0x03, // ACPI Processor ID
+ 0x0005, // Flags - Edge-tiggered, Active High
+ 0x01 // Local APIC LINT#
+ },
+ {
+ EFI_ACPI_6_3_LOCAL_APIC_NMI, // Type
+ sizeof (EFI_ACPI_6_3_LOCAL_APIC_NMI_STRUCTURE), // Length
+ 0x04, // ACPI Processor ID
+ 0x0005, // Flags - Edge-tiggered, Active High
+ 0x01 // Local APIC LINT#
+ },
+ {
+ EFI_ACPI_6_3_LOCAL_APIC_NMI, // Type
+ sizeof (EFI_ACPI_6_3_LOCAL_APIC_NMI_STRUCTURE), // Length
+ 0x05, // ACPI Processor ID
+ 0x0005, // Flags - Edge-tiggered, Active High
+ 0x01 // Local APIC LINT#
+ },
+ {
+ EFI_ACPI_6_3_LOCAL_APIC_NMI, // Type
+ sizeof (EFI_ACPI_6_3_LOCAL_APIC_NMI_STRUCTURE), // Length
+ 0x06, // ACPI Processor ID
+ 0x0005, // Flags - Edge-tiggered, Active High
+ 0x01 // Local APIC LINT#
+ },
+ {
+ EFI_ACPI_6_3_LOCAL_APIC_NMI, // Type
+ sizeof (EFI_ACPI_6_3_LOCAL_APIC_NMI_STRUCTURE), // Length
+ 0x07, // ACPI Processor ID
+ 0x0005, // Flags - Edge-tiggered, Active High
+ 0x01 // Local APIC LINT#
+ },
+ {
+ EFI_ACPI_6_3_LOCAL_APIC_NMI, // Type
+ sizeof (EFI_ACPI_6_3_LOCAL_APIC_NMI_STRUCTURE), // Length
+ 0x08, // ACPI Processor ID
+ 0x0005, // Flags - Edge-tiggered, Active High
+ 0x01 // Local APIC LINT#
+ },
+ {
+ EFI_ACPI_6_3_LOCAL_APIC_NMI, // Type
+ sizeof (EFI_ACPI_6_3_LOCAL_APIC_NMI_STRUCTURE), // Length
+ 0x09, // ACPI Processor ID
+ 0x0005, // Flags - Edge-tiggered, Active High
+ 0x01 // Local APIC LINT#
+ },
+ {
+ EFI_ACPI_6_3_LOCAL_APIC_NMI, // Type
+ sizeof (EFI_ACPI_6_3_LOCAL_APIC_NMI_STRUCTURE), // Length
+ 0x0A, // ACPI Processor ID
+ 0x0005, // Flags - Edge-tiggered, Active High
+ 0x01 // Local APIC LINT#
+ },
+ {
+ EFI_ACPI_6_3_LOCAL_APIC_NMI, // Type
+ sizeof (EFI_ACPI_6_3_LOCAL_APIC_NMI_STRUCTURE), // Length
+ 0x0B, // ACPI Processor ID
+ 0x0005, // Flags - Edge-tiggered, Active High
+ 0x01 // Local APIC LINT#
+ },
+ {
+ EFI_ACPI_6_3_LOCAL_APIC_NMI, // Type
+ sizeof (EFI_ACPI_6_3_LOCAL_APIC_NMI_STRUCTURE), // Length
+ 0x0C, // ACPI Processor ID
+ 0x0005, // Flags - Edge-tiggered, Active High
+ 0x01 // Local APIC LINT#
+ },
+ {
+ EFI_ACPI_6_3_LOCAL_APIC_NMI, // Type
+ sizeof (EFI_ACPI_6_3_LOCAL_APIC_NMI_STRUCTURE), // Length
+ 0x0D, // ACPI Processor ID
+ 0x0005, // Flags - Edge-tiggered, Active High
+ 0x01 // Local APIC LINT#
+ },
+ {
+ EFI_ACPI_6_3_LOCAL_APIC_NMI, // Type
+ sizeof (EFI_ACPI_6_3_LOCAL_APIC_NMI_STRUCTURE), // Length
+ 0x0E, // ACPI Processor ID
+ 0x0005, // Flags - Edge-tiggered, Active High
+ 0x01 // Local APIC LINT#
+ },
+ {
+ EFI_ACPI_6_3_LOCAL_APIC_NMI, // Type
+ sizeof (EFI_ACPI_6_3_LOCAL_APIC_NMI_STRUCTURE), // Length
+ 0x0F, // ACPI Processor ID
+ 0x0005, // Flags - Edge-tiggered, Active High
+ 0x01 // Local APIC LINT#
+ },
+ {
+ EFI_ACPI_6_3_LOCAL_APIC_NMI, // Type
+ sizeof (EFI_ACPI_6_3_LOCAL_APIC_NMI_STRUCTURE), // Length
+ 0x10, // ACPI Processor ID
+ 0x0005, // Flags - Edge-tiggered, Active High
+ 0x01 // Local APIC LINT#
+ },
+ {
+ EFI_ACPI_6_3_LOCAL_APIC_NMI, // Type
+ sizeof (EFI_ACPI_6_3_LOCAL_APIC_NMI_STRUCTURE), // Length
+ 0x11, // ACPI Processor ID
+ 0x0005, // Flags - Edge-tiggered, Active High
+ 0x01 // Local APIC LINT#
+ },
+ {
+ EFI_ACPI_6_3_LOCAL_APIC_NMI, // Type
+ sizeof (EFI_ACPI_6_3_LOCAL_APIC_NMI_STRUCTURE), // Length
+ 0x12, // ACPI Processor ID
+ 0x0005, // Flags - Edge-tiggered, Active High
+ 0x01 // Local APIC LINT#
+ },
+ {
+ EFI_ACPI_6_3_LOCAL_APIC_NMI, // Type
+ sizeof (EFI_ACPI_6_3_LOCAL_APIC_NMI_STRUCTURE), // Length
+ 0x13, // ACPI Processor ID
+ 0x0005, // Flags - Edge-tiggered, Active High
+ 0x01 // Local APIC LINT#
+ },
+ {
+ EFI_ACPI_6_3_LOCAL_APIC_NMI, // Type
+ sizeof (EFI_ACPI_6_3_LOCAL_APIC_NMI_STRUCTURE), // Length
+ 0x14, // ACPI Processor ID
+ 0x0005, // Flags - Edge-tiggered, Active High
+ 0x01 // Local APIC LINT#
+ },
+ {
+ EFI_ACPI_6_3_LOCAL_APIC_NMI, // Type
+ sizeof (EFI_ACPI_6_3_LOCAL_APIC_NMI_STRUCTURE), // Length
+ 0x15, // ACPI Processor ID
+ 0x0005, // Flags - Edge-tiggered, Active High
+ 0x01 // Local APIC LINT#
+ },
+ {
+ EFI_ACPI_6_3_LOCAL_APIC_NMI, // Type
+ sizeof (EFI_ACPI_6_3_LOCAL_APIC_NMI_STRUCTURE), // Length
+ 0x16, // ACPI Processor ID
+ 0x0005, // Flags - Edge-tiggered, Active High
+ 0x01 // Local APIC LINT#
+ },
+ {
+ EFI_ACPI_6_3_LOCAL_APIC_NMI, // Type
+ sizeof (EFI_ACPI_6_3_LOCAL_APIC_NMI_STRUCTURE), // Length
+ 0x17, // ACPI Processor ID
+ 0x0005, // Flags - Edge-tiggered, Active High
+ 0x01 // Local APIC LINT#
+ },
+ {
+ EFI_ACPI_6_3_LOCAL_APIC_NMI, // Type
+ sizeof (EFI_ACPI_6_3_LOCAL_APIC_NMI_STRUCTURE), // Length
+ 0x00, // ACPI Processor ID
+ 0x0005, // Flags - Edge-tiggered, Active High
+ 0x01 // Local APIC LINT#
+ }
+ }
+
+ //
+ // Sample Local APIC Address Override Structure
+ //
+ //EFI_ACPI_6_3_LOCAL_APIC_ADDRESS_OVERRIDE, // Type
+ //sizeof (EFI_ACPI_6_3_LOCAL_APIC_ADDRESS_OVERRIDE_STRUCTURE), // Length
+ //EFI_ACPI_RESERVED_WORD, // Reserved
+ //0x0000000000000000, // Local APIC Address
+
+ //
+ // Sample Platform Interrupt Sources Structure
+ //
+ //EFI_ACPI_6_3_PLATFORM_INTERRUPT_SOURCES, // Type
+ //sizeof (EFI_ACPI_6_3_PLATFORM_INTERRUPT_SOURCES_STRUCTURE), // Length
+ //0x0000, // Flags
+ //0x00, // Interrupt Type
+ //0x00, // Processor ID
+ //0x00, // Processor EID
+ //0x00, // IO SAPIC Vector
+ //0x00000000, // Global System Interrupt
+ //EFI_ACPI_RESERVED_DWORD, // Reserved
+
+};
+
+#ifdef __GNUC__
+VOID*
+ReferenceAcpiTable (
+ VOID
+ )
+
+{
+ //
+ // Reference the table being generated to prevent the optimizer from removing the
+ // data structure from the executable
+ //
+ return (VOID*)&Madt;
+}
+#else
+VOID
+main (
+ VOID
+ )
+{
+}
+#endif
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AcpiTables/Madt/Madt.h b/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AcpiTables/Madt/Madt.h
new file mode 100644
index 0000000000..b06b6efecd
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AcpiTables/Madt/Madt.h
@@ -0,0 +1,226 @@
+/** @file
+ This file describes the contents of the ACPI Multiple APIC Description
+ Table (MADT).
+ To make changes to the MADT, it is necessary to update the count for the
+ APIC structure being updated, and to modify table found in Madt.c.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _MADT_H_
+#define _MADT_H_
+
+//
+// Statements that include other files
+//
+
+#include <IndustryStandard/Acpi.h>
+
+//
+// MADT Definitions
+//
+
+#define EFI_ACPI_OEM_MADT_REVISION 0x00000001
+
+
+//
+// Multiple APIC Flags are defined in AcpiX.0.h
+//
+#define EFI_ACPI_6_3_MULTIPLE_APIC_FLAGS (EFI_ACPI_6_3_PCAT_COMPAT)
+
+//
+// Define the number of each table type.
+// This is where the table layout is modified.
+//
+
+#define EFI_ACPI_PROCESSOR_LOCAL_APIC_COUNT 32
+#define EFI_ACPI_IO_APIC_COUNT 1
+#define EFI_ACPI_INTERRUPT_SOURCE_OVERRIDE_COUNT 2
+#define EFI_ACPI_NON_MASKABLE_INTERRUPT_SOURCE_COUNT 0
+#define EFI_ACPI_LOCAL_APIC_NMI_COUNT 24
+#define EFI_ACPI_LOCAL_APIC_ADDRESS_OVERRIDE_COUNT 0
+#define EFI_ACPI_IO_SAPIC_COUNT 0
+#define EFI_ACPI_PROCESSOR_LOCAL_SAPIC_COUNT 0
+#define EFI_ACPI_PLATFORM_INTERRUPT_SOURCES_COUNT 0
+#define EFI_ACPI_PROCESSOR_LOCAL_X2APIC_COUNT 32
+#define EFI_ACPI_LOCAL_X2APIC_NMI_COUNT 1
+
+//
+// MADT structure
+//
+
+//
+// Ensure proper structure formats
+//
+#pragma pack (1)
+
+//
+// ACPI 1.0 Table structure
+//
+typedef struct {
+ EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header;
+
+#if EFI_ACPI_PROCESSOR_LOCAL_APIC_COUNT > 0
+ EFI_ACPI_1_0_PROCESSOR_LOCAL_APIC_STRUCTURE LocalApic[EFI_ACPI_PROCESSOR_LOCAL_APIC_COUNT];
+#endif
+
+#if EFI_ACPI_IO_APIC_COUNT > 0
+ EFI_ACPI_1_0_IO_APIC_STRUCTURE IoApic[EFI_ACPI_IO_APIC_COUNT];
+#endif
+
+#if EFI_ACPI_INTERRUPT_SOURCE_OVERRIDE_COUNT > 0
+ EFI_ACPI_1_0_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE Iso[EFI_ACPI_INTERRUPT_SOURCE_OVERRIDE_COUNT];
+#endif
+
+#if EFI_ACPI_NON_MASKABLE_INTERRUPT_SOURCE_COUNT > 0
+ EFI_ACPI_1_0_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE NmiSource[EFI_ACPI_NON_MASKABLE_INTERRUPT_SOURCE_COUNT];
+#endif
+
+#if EFI_ACPI_LOCAL_APIC_NMI_COUNT > 0
+ EFI_ACPI_1_0_LOCAL_APIC_NMI_STRUCTURE LocalApicNmi[EFI_ACPI_LOCAL_APIC_NMI_COUNT];
+#endif
+
+#if EFI_ACPI_LOCAL_APIC_ADDRESS_OVERRIDE_COUNT > 0
+ EFI_ACPI_1_0_LOCAL_APIC_ADDRESS_OVERRIDE_STRUCTURE LocalApicOverride[EFI_ACPI_LOCAL_APIC_OVERRIDE_COUNT];
+#endif
+
+} EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE;
+
+//
+// ACPI 2.0 Table structure
+//
+typedef struct {
+ EFI_ACPI_2_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header;
+
+#if EFI_ACPI_PROCESSOR_LOCAL_APIC_COUNT > 0
+ EFI_ACPI_2_0_PROCESSOR_LOCAL_APIC_STRUCTURE LocalApic[EFI_ACPI_PROCESSOR_LOCAL_APIC_COUNT];
+#endif
+
+#if EFI_ACPI_IO_APIC_COUNT > 0
+ EFI_ACPI_2_0_IO_APIC_STRUCTURE IoApic[EFI_ACPI_IO_APIC_COUNT];
+#endif
+
+#if EFI_ACPI_INTERRUPT_SOURCE_OVERRIDE_COUNT > 0
+ EFI_ACPI_2_0_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE Iso[EFI_ACPI_INTERRUPT_SOURCE_OVERRIDE_COUNT];
+#endif
+
+#if EFI_ACPI_NON_MASKABLE_INTERRUPT_SOURCE_COUNT > 0
+ EFI_ACPI_2_0_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE NmiSource[EFI_ACPI_NON_MASKABLE_INTERRUPT_SOURCE_COUNT];
+#endif
+
+#if EFI_ACPI_LOCAL_APIC_NMI_COUNT > 0
+ EFI_ACPI_2_0_LOCAL_APIC_NMI_STRUCTURE LocalApicNmi[EFI_ACPI_LOCAL_APIC_NMI_COUNT];
+#endif
+
+#if EFI_ACPI_LOCAL_APIC_ADDRESS_OVERRIDE_COUNT > 0
+ EFI_ACPI_2_0_LOCAL_APIC_ADDRESS_OVERRIDE_STRUCTURE LocalApicOverride[EFI_ACPI_LOCAL_APIC_OVERRIDE_COUNT];
+#endif
+
+#if EFI_ACPI_IO_SAPIC_COUNT > 0
+ EFI_ACPI_2_0_IO_SAPIC_STRUCTURE IoSapic[EFI_ACPI_IO_SAPIC_COUNT];
+#endif
+
+#if EFI_ACPI_PROCESSOR_LOCAL_SAPIC_COUNT > 0
+ EFI_ACPI_2_0_PROCESSOR_LOCAL_SAPIC_STRUCTURE LocalSapic[EFI_ACPI_PROCESSOR_LOCAL_SAPIC_COUNT];
+#endif
+
+#if EFI_ACPI_PLATFORM_INTERRUPT_SOURCES_COUNT > 0
+ EFI_ACPI_2_0_PLATFORM_INTERRUPT_SOURCES_STRUCTURE PlatformInterruptSources[EFI_ACPI_PLATFORM_INTERRUPT_SOURCES_COUNT];
+#endif
+
+} EFI_ACPI_2_0_MULTIPLE_APIC_DESCRIPTION_TABLE;
+
+//
+// ACPI 6.3 APIC Table structure
+//
+typedef struct {
+ EFI_ACPI_6_3_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header;
+
+#if EFI_ACPI_PROCESSOR_LOCAL_APIC_COUNT > 0 // Type 0x09
+ EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC_STRUCTURE LocalApic[EFI_ACPI_PROCESSOR_LOCAL_APIC_COUNT];
+#endif
+
+#if EFI_ACPI_IO_APIC_COUNT > 0 // Type 0x01
+ EFI_ACPI_6_3_IO_APIC_STRUCTURE IoApic[EFI_ACPI_IO_APIC_COUNT];
+#endif
+
+#if EFI_ACPI_INTERRUPT_SOURCE_OVERRIDE_COUNT > 0 // Type 0x02
+ EFI_ACPI_6_3_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE Iso[EFI_ACPI_INTERRUPT_SOURCE_OVERRIDE_COUNT];
+#endif
+
+#if EFI_ACPI_NON_MASKABLE_INTERRUPT_SOURCE_COUNT > 0 // Type 0x03
+ EFI_ACPI_6_3_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE NmiSource[EFI_ACPI_NON_MASKABLE_INTERRUPT_SOURCE_COUNT];
+#endif
+
+#if EFI_ACPI_LOCAL_APIC_NMI_COUNT > 0 // Type 0x0A
+ EFI_ACPI_6_3_LOCAL_APIC_NMI_STRUCTURE LocalApicNmi[EFI_ACPI_LOCAL_APIC_NMI_COUNT];
+#endif
+
+#if EFI_ACPI_LOCAL_APIC_ADDRESS_OVERRIDE_COUNT > 0 // Type 0x05
+ EFI_ACPI_6_3_LOCAL_APIC_ADDRESS_OVERRIDE_STRUCTURE LocalApicOverride[EFI_ACPI_LOCAL_APIC_OVERRIDE_COUNT];
+#endif
+
+#if EFI_ACPI_IO_SAPIC_COUNT > 0 // Type 0x06
+ EFI_ACPI_6_3_IO_SAPIC_STRUCTURE IoSapic[EFI_ACPI_IO_SAPIC_COUNT];
+#endif
+
+#if EFI_ACPI_PROCESSOR_LOCAL_SAPIC_COUNT > 0 // Type 0x07 : This table changes in madt 2.0
+ EFI_ACPI_6_3_PROCESSOR_LOCAL_SAPIC_STRUCTURE LocalSapic[EFI_ACPI_PROCESSOR_LOCAL_SAPIC_COUNT];
+#endif
+
+#if EFI_ACPI_PLATFORM_INTERRUPT_SOURCES_COUNT > 0 // Type 0x08
+ EFI_ACPI_6_3_PLATFORM_INTERRUPT_SOURCES_STRUCTURE PlatformInterruptSources[EFI_ACPI_PLATFORM_INTERRUPT_SOURCES_COUNT];
+#endif
+
+} EFI_ACPI_6_3_MULTIPLE_APIC_DESCRIPTION_TABLE;
+
+
+//
+// ACPI 6.3 X2APIC Table structure
+//
+typedef struct {
+ EFI_ACPI_6_3_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header;
+
+#if EFI_ACPI_PROCESSOR_LOCAL_X2APIC_COUNT > 0 // Type 0x09
+ EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC_STRUCTURE LocalX2Apic[EFI_ACPI_PROCESSOR_LOCAL_X2APIC_COUNT];
+#endif
+
+#if EFI_ACPI_IO_APIC_COUNT > 0 // Type 0x01
+ EFI_ACPI_6_3_IO_APIC_STRUCTURE IoApic[EFI_ACPI_IO_APIC_COUNT];
+#endif
+
+#if EFI_ACPI_INTERRUPT_SOURCE_OVERRIDE_COUNT > 0 // Type 0x02
+ EFI_ACPI_6_3_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE Iso[EFI_ACPI_INTERRUPT_SOURCE_OVERRIDE_COUNT];
+#endif
+
+#if EFI_ACPI_NON_MASKABLE_INTERRUPT_SOURCE_COUNT > 0 // Type 0x03
+ EFI_ACPI_6_3_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE NmiSource[EFI_ACPI_NON_MASKABLE_INTERRUPT_SOURCE_COUNT];
+#endif
+
+#if EFI_ACPI_LOCAL_X2APIC_NMI_COUNT > 0 // Type 0x0A
+ EFI_ACPI_6_3_LOCAL_X2APIC_NMI_STRUCTURE X2ApicNmi[EFI_ACPI_LOCAL_X2APIC_NMI_COUNT];
+#endif
+
+#if EFI_ACPI_LOCAL_APIC_ADDRESS_OVERRIDE_COUNT > 0 // Type 0x05
+ EFI_ACPI_6_3_LOCAL_APIC_ADDRESS_OVERRIDE_STRUCTURE LocalApicOverride[EFI_ACPI_LOCAL_APIC_OVERRIDE_COUNT];
+#endif
+
+#if EFI_ACPI_IO_SAPIC_COUNT > 0 // Type 0x06
+ EFI_ACPI_6_3_IO_SAPIC_STRUCTURE IoSapic[EFI_ACPI_IO_SAPIC_COUNT];
+#endif
+
+#if EFI_ACPI_PROCESSOR_LOCAL_SAPIC_COUNT > 0 // Type 0x07 : This table changes in madt 2.0
+ EFI_ACPI_6_3_PROCESSOR_LOCAL_SAPIC_STRUCTURE LocalSapic[EFI_ACPI_PROCESSOR_LOCAL_SAPIC_COUNT];
+#endif
+
+#if EFI_ACPI_PLATFORM_INTERRUPT_SOURCES_COUNT > 0 // Type 0x08
+ EFI_ACPI_6_3_PLATFORM_INTERRUPT_SOURCES_STRUCTURE PlatformInterruptSources[EFI_ACPI_PLATFORM_INTERRUPT_SOURCES_COUNT];
+#endif
+
+} EFI_ACPI_6_3_MULTIPLE_X2APIC_DESCRIPTION_TABLE;
+
+#pragma pack ()
+
+#endif
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AcpiTables/Madt/MadtX2Apic.act b/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AcpiTables/Madt/MadtX2Apic.act
new file mode 100644
index 0000000000..b6d4b6bd11
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AcpiTables/Madt/MadtX2Apic.act
@@ -0,0 +1,522 @@
+/** @file
+ This file contains a structure definition for the ACPI 6.3 Multiple APIC
+ Description Table (MADT). Any changes to the MADT table require updating the
+ respective structure count in Madt.h and then adding the structure to the
+ MADT defined in this file.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+//
+// Statements that include other files
+//
+
+#include "Madt.h"
+
+//
+// Multiple APIC Description Table
+//
+
+EFI_ACPI_6_3_MULTIPLE_X2APIC_DESCRIPTION_TABLE Madtx2Apic = {
+ {
+ {
+ EFI_ACPI_6_3_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE,
+ sizeof (EFI_ACPI_6_3_MULTIPLE_APIC_DESCRIPTION_TABLE),
+ EFI_ACPI_6_3_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION,
+
+ //
+ // Checksum will be updated at runtime
+ //
+ 0x00,
+
+ //
+ // It is expected that these values will be programmed at runtime
+ //
+ { ' ', ' ', ' ', ' ', ' ', ' ' },
+
+ 0,
+ EFI_ACPI_OEM_MADT_REVISION,
+ 0,
+ 0
+ },
+
+ //
+ // MADT specific fields
+ //
+ FixedPcdGet64 (PcdApicLocalAddress),
+ EFI_ACPI_6_3_MULTIPLE_APIC_FLAGS
+ },
+
+ //
+ // Sample Processor Local X2APIC Structure
+ //
+ //EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC, // Type 0x09
+ //sizeof (EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC_STRUCTURE), // Length
+ //EFI_ACPI_RESERVED_BYTE, // Reserved
+ //EFI_ACPI_RESERVED_BYTE, // Reserved
+ //0xFFFFFFFF, // Local X2APIC ID
+ //0x00000000, // Flags - Disabled (until initialized by platform driver)
+ //0x00000000, // Processor ID
+ {
+ {
+ EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC, // Type
+ sizeof (EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC_STRUCTURE), // Length
+ {
+ EFI_ACPI_RESERVED_BYTE, // Reserved
+ EFI_ACPI_RESERVED_BYTE // Reserved
+ },
+ 0xFFFFFFFF, // Local X2APIC ID
+ 0x00000000, // Flags - Disabled (until initialized by platform driver)
+ 0x00000001, // Processor ID
+ },
+ {
+ EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC, // Type
+ sizeof (EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC_STRUCTURE), // Length
+ {
+ EFI_ACPI_RESERVED_BYTE, // Reserved
+ EFI_ACPI_RESERVED_BYTE // Reserved
+ },
+ 0xFFFFFFFF, // Local X2APIC ID
+ 0x00000000, // Flags - Disabled (until initialized by platform driver)
+ 0x00000002, // Processor ID
+ },
+ {
+ EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC, // Type
+ sizeof (EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC_STRUCTURE), // Length
+ {
+ EFI_ACPI_RESERVED_BYTE, // Reserved
+ EFI_ACPI_RESERVED_BYTE // Reserved
+ },
+ 0xFFFFFFFF, // Local X2APIC ID
+ 0x00000000, // Flags - Disabled (until initialized by platform driver)
+ 0x00000003, // Processor ID
+ },
+ {
+ EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC, // Type
+ sizeof (EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC_STRUCTURE), // Length
+ {
+ EFI_ACPI_RESERVED_BYTE, // Reserved
+ EFI_ACPI_RESERVED_BYTE // Reserved
+ },
+ 0xFFFFFFFF, // Local X2APIC ID
+ 0x00000000, // Flags - Disabled (until initialized by platform driver)
+ 0x00000004, // Processor ID
+ },
+ {
+ EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC, // Type
+ sizeof (EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC_STRUCTURE), // Length
+ {
+ EFI_ACPI_RESERVED_BYTE, // Reserved
+ EFI_ACPI_RESERVED_BYTE // Reserved
+ },
+ 0xFFFFFFFF, // Local X2APIC ID
+ 0x00000000, // Flags - Disabled (until initialized by platform driver)
+ 0x00000005, // Processor ID
+ },
+ {
+ EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC, // Type
+ sizeof (EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC_STRUCTURE), // Length
+ {
+ EFI_ACPI_RESERVED_BYTE, // Reserved
+ EFI_ACPI_RESERVED_BYTE // Reserved
+ },
+ 0xFFFFFFFF, // Local X2APIC ID
+ 0x00000000, // Flags - Disabled (until initialized by platform driver)
+ 0x00000006, // Processor ID
+ },
+ {
+ EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC, // Type
+ sizeof (EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC_STRUCTURE), // Length
+ {
+ EFI_ACPI_RESERVED_BYTE, // Reserved
+ EFI_ACPI_RESERVED_BYTE // Reserved
+ },
+ 0xFFFFFFFF, // Local X2APIC ID
+ 0x00000000, // Flags - Disabled (until initialized by platform driver)
+ 0x00000007, // Processor ID
+ },
+ {
+ EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC, // Type
+ sizeof (EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC_STRUCTURE), // Length
+ {
+ EFI_ACPI_RESERVED_BYTE, // Reserved
+ EFI_ACPI_RESERVED_BYTE // Reserved
+ },
+ 0xFFFFFFFF, // Local X2APIC ID
+ 0x00000000, // Flags - Disabled (until initialized by platform driver)
+ 0x00000008, // Processor ID
+ },
+ {
+ EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC, // Type
+ sizeof (EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC_STRUCTURE), // Length
+ {
+ EFI_ACPI_RESERVED_BYTE, // Reserved
+ EFI_ACPI_RESERVED_BYTE // Reserved
+ },
+ 0xFFFFFFFF, // Local X2APIC ID
+ 0x00000000, // Flags - Disabled (until initialized by platform driver)
+ 0x00000009, // Processor ID
+ },
+ {
+ EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC, // Type
+ sizeof (EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC_STRUCTURE), // Length
+ {
+ EFI_ACPI_RESERVED_BYTE, // Reserved
+ EFI_ACPI_RESERVED_BYTE // Reserved
+ },
+ 0xFFFFFFFF, // Local X2APIC ID
+ 0x00000000, // Flags - Disabled (until initialized by platform driver)
+ 0x0000000A, // Processor ID
+ },
+ {
+ EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC, // Type
+ sizeof (EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC_STRUCTURE), // Length
+ {
+ EFI_ACPI_RESERVED_BYTE, // Reserved
+ EFI_ACPI_RESERVED_BYTE // Reserved
+ },
+ 0xFFFFFFFF, // Local X2APIC ID
+ 0x00000000, // Flags - Disabled (until initialized by platform driver)
+ 0x0000000B, // Processor ID
+ },
+ {
+ EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC, // Type
+ sizeof (EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC_STRUCTURE), // Length
+ {
+ EFI_ACPI_RESERVED_BYTE, // Reserved
+ EFI_ACPI_RESERVED_BYTE // Reserved
+ },
+ 0xFFFFFFFF, // Local X2APIC ID
+ 0x00000000, // Flags - Disabled (until initialized by platform driver)
+ 0x0000000C, // Processor ID
+ },
+ {
+ EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC, // Type
+ sizeof (EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC_STRUCTURE), // Length
+ {
+ EFI_ACPI_RESERVED_BYTE, // Reserved
+ EFI_ACPI_RESERVED_BYTE // Reserved
+ },
+ 0xFFFFFFFF, // Local X2APIC ID
+ 0x00000000, // Flags - Disabled (until initialized by platform driver)
+ 0x0000000D, // Processor ID
+ },
+ {
+ EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC, // Type
+ sizeof (EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC_STRUCTURE), // Length
+ {
+ EFI_ACPI_RESERVED_BYTE, // Reserved
+ EFI_ACPI_RESERVED_BYTE // Reserved
+ },
+ 0xFFFFFFFF, // Local X2APIC ID
+ 0x00000000, // Flags - Disabled (until initialized by platform driver)
+ 0x0000000E, // Processor ID
+ },
+ {
+ EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC, // Type
+ sizeof (EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC_STRUCTURE), // Length
+ {
+ EFI_ACPI_RESERVED_BYTE, // Reserved
+ EFI_ACPI_RESERVED_BYTE // Reserved
+ },
+ 0xFFFFFFFF, // Local X2APIC ID
+ 0x00000000, // Flags - Disabled (until initialized by platform driver)
+ 0x0000000F, // Processor ID
+ },
+ {
+ EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC, // Type
+ sizeof (EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC_STRUCTURE), // Length
+ {
+ EFI_ACPI_RESERVED_BYTE, // Reserved
+ EFI_ACPI_RESERVED_BYTE // Reserved
+ },
+ 0xFFFFFFFF, // Local X2APIC ID
+ 0x00000000, // Flags - Disabled (until initialized by platform driver)
+ 0x00000010, // Processor ID
+ },
+ {
+ EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC, // Type
+ sizeof (EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC_STRUCTURE), // Length
+ {
+ EFI_ACPI_RESERVED_BYTE, // Reserved
+ EFI_ACPI_RESERVED_BYTE // Reserved
+ },
+ 0xFFFFFFFF, // Local X2APIC ID
+ 0x00000000, // Flags - Disabled (until initialized by platform driver)
+ 0x00000011, // Processor ID
+ },
+ {
+ EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC, // Type
+ sizeof (EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC_STRUCTURE), // Length
+ {
+ EFI_ACPI_RESERVED_BYTE, // Reserved
+ EFI_ACPI_RESERVED_BYTE // Reserved
+ },
+ 0xFFFFFFFF, // Local X2APIC ID
+ 0x00000000, // Flags - Disabled (until initialized by platform driver)
+ 0x00000012, // Processor ID
+ },
+ {
+ EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC, // Type
+ sizeof (EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC_STRUCTURE), // Length
+ {
+ EFI_ACPI_RESERVED_BYTE, // Reserved
+ EFI_ACPI_RESERVED_BYTE // Reserved
+ },
+ 0xFFFFFFFF, // Local X2APIC ID
+ 0x00000000, // Flags - Disabled (until initialized by platform driver)
+ 0x00000013, // Processor ID
+ },
+ {
+ EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC, // Type
+ sizeof (EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC_STRUCTURE), // Length
+ {
+ EFI_ACPI_RESERVED_BYTE, // Reserved
+ EFI_ACPI_RESERVED_BYTE // Reserved
+ },
+ 0xFFFFFFFF, // Local X2APIC ID
+ 0x00000000, // Flags - Disabled (until initialized by platform driver)
+ 0x00000014, // Processor ID
+ },
+ {
+ EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC, // Type
+ sizeof (EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC_STRUCTURE), // Length
+ {
+ EFI_ACPI_RESERVED_BYTE, // Reserved
+ EFI_ACPI_RESERVED_BYTE // Reserved
+ },
+ 0xFFFFFFFF, // Local X2APIC ID
+ 0x00000000, // Flags - Disabled (until initialized by platform driver)
+ 0x00000015, // Processor ID
+ },
+ {
+ EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC, // Type
+ sizeof (EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC_STRUCTURE), // Length
+ {
+ EFI_ACPI_RESERVED_BYTE, // Reserved
+ EFI_ACPI_RESERVED_BYTE // Reserved
+ },
+ 0xFFFFFFFF, // Local X2APIC ID
+ 0x00000000, // Flags - Disabled (until initialized by platform driver)
+ 0x00000016, // Processor ID
+ },
+ {
+ EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC, // Type
+ sizeof (EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC_STRUCTURE), // Length
+ {
+ EFI_ACPI_RESERVED_BYTE, // Reserved
+ EFI_ACPI_RESERVED_BYTE // Reserved
+ },
+ 0xFFFFFFFF, // Local X2APIC ID
+ 0x00000000, // Flags - Disabled (until initialized by platform driver)
+ 0x00000017, // Processor ID
+ },
+ {
+ EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC, // Type
+ sizeof (EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC_STRUCTURE), // Length
+ {
+ EFI_ACPI_RESERVED_BYTE, // Reserved
+ EFI_ACPI_RESERVED_BYTE // Reserved
+ },
+ 0xFFFFFFFF, // Local X2APIC ID
+ 0x00000000, // Flags - Disabled (until initialized by platform driver)
+ 0x00000018, // Processor ID
+ },
+ {
+ EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC, // Type
+ sizeof (EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC_STRUCTURE), // Length
+ {
+ EFI_ACPI_RESERVED_BYTE, // Reserved
+ EFI_ACPI_RESERVED_BYTE // Reserved
+ },
+ 0xFFFFFFFF, // Local X2APIC ID
+ 0x00000000, // Flags - Disabled (until initialized by platform driver)
+ 0x00000019, // Processor ID
+ },
+ {
+ EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC, // Type
+ sizeof (EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC_STRUCTURE), // Length
+ {
+ EFI_ACPI_RESERVED_BYTE, // Reserved
+ EFI_ACPI_RESERVED_BYTE // Reserved
+ },
+ 0xFFFFFFFF, // Local X2APIC ID
+ 0x00000000, // Flags - Disabled (until initialized by platform driver)
+ 0x0000001A, // Processor ID
+ },
+ {
+ EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC, // Type
+ sizeof (EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC_STRUCTURE), // Length
+ {
+ EFI_ACPI_RESERVED_BYTE, // Reserved
+ EFI_ACPI_RESERVED_BYTE // Reserved
+ },
+ 0xFFFFFFFF, // Local X2APIC ID
+ 0x00000000, // Flags - Disabled (until initialized by platform driver)
+ 0x0000001B, // Processor ID
+ },
+ {
+ EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC, // Type
+ sizeof (EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC_STRUCTURE), // Length
+ {
+ EFI_ACPI_RESERVED_BYTE, // Reserved
+ EFI_ACPI_RESERVED_BYTE // Reserved
+ },
+ 0xFFFFFFFF, // Local X2APIC ID
+ 0x00000000, // Flags - Disabled (until initialized by platform driver)
+ 0x0000001C, // Processor ID
+ },
+ {
+ EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC, // Type
+ sizeof (EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC_STRUCTURE), // Length
+ {
+ EFI_ACPI_RESERVED_BYTE, // Reserved
+ EFI_ACPI_RESERVED_BYTE // Reserved
+ },
+ 0xFFFFFFFF, // Local X2APIC ID
+ 0x00000000, // Flags - Disabled (until initialized by platform driver)
+ 0x0000001D, // Processor ID
+ },
+ {
+ EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC, // Type
+ sizeof (EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC_STRUCTURE), // Length
+ {
+ EFI_ACPI_RESERVED_BYTE, // Reserved
+ EFI_ACPI_RESERVED_BYTE // Reserved
+ },
+ 0xFFFFFFFF, // Local X2APIC ID
+ 0x00000000, // Flags - Disabled (until initialized by platform driver)
+ 0x0000001E, // Processor ID
+ },
+ {
+ EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC, // Type
+ sizeof (EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC_STRUCTURE), // Length
+ {
+ EFI_ACPI_RESERVED_BYTE, // Reserved
+ EFI_ACPI_RESERVED_BYTE // Reserved
+ },
+ 0xFFFFFFFF, // Local X2APIC ID
+ 0x00000000, // Flags - Disabled (until initialized by platform driver)
+ 0x0000001F, // Processor ID
+ },
+ {
+ EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC, // Type
+ sizeof (EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC_STRUCTURE), // Length
+ {
+ EFI_ACPI_RESERVED_BYTE, // Reserved
+ EFI_ACPI_RESERVED_BYTE // Reserved
+ },
+ 0xFFFFFFFF, // Local X2APIC ID
+ 0x00000000, // Flags - Disabled (until initialized by platform driver)
+ 0x00000020, // Processor ID
+ }
+ },
+
+ //
+ // Sample IO APIC Structure
+ //
+ //EFI_ACPI_6_3_IO_APIC, // Type
+ //sizeof (EFI_ACPI_6_3_IO_APIC_STRUCTURE), // Length
+ //0x00, // IO APIC ID
+ //EFI_ACPI_RESERVED_BYTE, // Reserved
+ //0x00000000, // IO APIC Address (physical)
+ //0x00000000, // Global System Interrupt Base
+ {
+ {
+ //
+ // I/O SAPIC (ICH)
+ //
+ EFI_ACPI_6_3_IO_APIC, // Type
+ sizeof (EFI_ACPI_6_3_IO_APIC_STRUCTURE), // Length
+ FixedPcdGet8 (PcdApicIoIdPch), // IO APIC ID
+ EFI_ACPI_RESERVED_BYTE, // Reserved
+ FixedPcdGet64 (PcdApicIoAddress), // IO APIC Address (physical)
+ 0x18 * 0 // Global System Interrupt Base
+ }
+ },
+
+ //
+ // Sample Interrupt Source Override Structure
+ //
+ //EFI_ACPI_6_3_INTERRUPT_SOURCE_OVERRIDE, // Type
+ //sizeof (EFI_ACPI_6_3_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE), // Length
+ //0x00, // Bus
+ //0x00, // Source
+ //0x00000000, // Global System Interrupt
+ //0x0000, // Flags
+ {
+ {
+ //
+ // IRQ0=>IRQ2 Interrupt Source Override Structure
+ //
+ EFI_ACPI_6_3_INTERRUPT_SOURCE_OVERRIDE, // Type
+ sizeof (EFI_ACPI_6_3_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE),// Length
+ 0x00, // Bus - ISA
+ 0x00, // Source - IRQ0
+ 0x00000002, // Global System Interrupt - IRQ2
+ 0x0000 // Flags - Conforms to specifications of the bus
+ },
+ {
+ //
+ // ISO (SCI Active High) Interrupt Source Override Structure
+ //
+ EFI_ACPI_6_3_INTERRUPT_SOURCE_OVERRIDE, // Type
+ sizeof (EFI_ACPI_6_3_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE),// Length
+ 0x00, // Bus - ISA
+ 0x09, // Source - IRQ9
+ 0x00000009, // Global System Interrupt - IRQ9
+ 0x000D // Flags - Level-tiggered, Active High
+ }
+ },
+
+ //
+ // Sample Local X2APIC NMI Structure
+ //
+ //EFI_ACPI_6_3_LOCAL_X2APIC_NMI, // Type 0x0A
+ //sizeof (EFI_ACPI_6_3_LOCAL_X2APIC_NMI_STRUCTURE), // Length 0x0C
+ //0x000D, // Flags - Level-tiggered, Active High
+ //0xFFFFFFFF, // Processor ID
+ //0x01, // Local APIC LINT#
+ //EFI_ACPI_RESERVED_BYTE, // Reserved
+ //EFI_ACPI_RESERVED_BYTE, // Reserved
+ //EFI_ACPI_RESERVED_BYTE, // Reserved
+ {
+ {
+ EFI_ACPI_6_3_LOCAL_X2APIC_NMI, // Type
+ sizeof (EFI_ACPI_6_3_LOCAL_X2APIC_NMI_STRUCTURE), // Length
+ 0x000D, // Flags - Level-tiggered, Active High
+ 0xFFFFFFFF, // Processor ID
+ 0x01, // Local APIC LINT#
+ {
+ EFI_ACPI_RESERVED_BYTE, // Reserved
+ EFI_ACPI_RESERVED_BYTE, // Reserved
+ EFI_ACPI_RESERVED_BYTE // Reserved
+ }
+ }
+ }
+
+};
+
+#ifdef __GNUC__
+VOID*
+ReferenceAcpiTable (
+ VOID
+ )
+
+{
+ //
+ // Reference the table being generated to prevent the optimizer from removing the
+ // data structure from the executable
+ //
+ return (VOID*)&Madtx2Apic;
+}
+#else
+VOID
+main (
+ VOID
+ )
+{
+}
+#endif
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AcpiTables/Mcfg/Mcfg.act b/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AcpiTables/Mcfg/Mcfg.act
new file mode 100644
index 0000000000..47f2a15336
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AcpiTables/Mcfg/Mcfg.act
@@ -0,0 +1,91 @@
+/** @file
+ This file contains a structure definition for the ACPI Memory Mapped Configuration
+ Address Space table (MCFG). Any changes to the number of entries in the table require
+ updating the structure count in Mcfg.h and then adding the structure to the
+ MCFG defined in this file. The table layout is defined in Mcfg.h and the
+ table contents are defined in the MemoryMappedConfigurationSpaceAccessTable.h.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+//
+// Statements that include other files
+//
+
+#include "Mcfg.h"
+
+//
+// Multiple APIC Description Table
+//
+
+EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_DESCRIPTION_TABLE Madt = {
+ {
+ EFI_ACPI_3_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE,
+ sizeof (EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_DESCRIPTION_TABLE),
+ EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_TABLE_REVISION,
+
+ //
+ // Checksum will be updated at runtime
+ //
+ 0x00,
+
+ //
+ // It is expected that these values will be programmed at runtime
+ //
+ { ' ', ' ', ' ', ' ', ' ', ' ' },
+
+ 0,
+ EFI_ACPI_OEM_MCFG_REVISION,
+ 0,
+ 0
+ },
+
+ //
+ // Reserved
+ //
+ 0x0000000000000000,
+
+ //
+ // MCFG specific fields
+ //
+ {
+ {
+ 0x0000000000000000, // BaseAddress, will be updated by AcpiPlatform
+ 0x0000, // PciSegmentGroupNumber
+ 0x00, // StartBusNumber
+ 0x00, // EndBusNumber, will be updated by AcpiPlatform
+ 0x00000000 // Reserved
+ },
+ {
+ 0x0000000000000000, // BaseAddress, will be updated by AcpiPlatform
+ 0x0001, // PciSegmentGroupNumber
+ 0x00, // StartBusNumber
+ 0xFF, // EndBusNumber, If extra segment is presented, it must support Bus Number from 0x00 ~ 0xFF
+ 0x00000000 // Reserved
+ }
+ }
+};
+
+#ifdef __GNUC__
+VOID*
+ReferenceAcpiTable (
+ VOID
+ )
+
+{
+ //
+ // Reference the table being generated to prevent the optimizer from removing the
+ // data structure from the exeutable
+ //
+ return (VOID*)&Madt;
+}
+#else
+VOID
+main (
+ VOID
+ )
+{
+}
+#endif
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AcpiTables/Mcfg/Mcfg.h b/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AcpiTables/Mcfg/Mcfg.h
new file mode 100644
index 0000000000..627d66a81d
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AcpiTables/Mcfg/Mcfg.h
@@ -0,0 +1,53 @@
+/** @file
+ This file describes the contents of the ACPI Memory Mapped Configuration
+ Space Access Table (MCFG).
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _MCFG_H_
+#define _MCFG_H_
+
+//
+// Statements that include other files
+//
+
+#include <IndustryStandard/Acpi30.h>
+#include <IndustryStandard/MemoryMappedConfigurationSpaceAccessTable.h>
+
+//
+// MCFG Definitions
+//
+
+#define EFI_ACPI_OEM_MCFG_REVISION 0x00000001
+
+//
+// Define the number of allocation structures so that we can build the table structure.
+//
+#define EFI_ACPI_ALLOCATION_STRUCTURE_COUNT 2
+
+//
+// MCFG structure
+//
+
+//
+// Ensure proper structure formats
+//
+#pragma pack (1)
+
+//
+// MCFG Table structure
+//
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT64 Reserved;
+#if EFI_ACPI_ALLOCATION_STRUCTURE_COUNT > 0
+ EFI_ACPI_MEMORY_MAPPED_ENHANCED_CONFIGURATION_SPACE_BASE_ADDRESS_ALLOCATION_STRUCTURE AllocationStructure[EFI_ACPI_ALLOCATION_STRUCTURE_COUNT];
+#endif
+} EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_DESCRIPTION_TABLE;
+
+#pragma pack ()
+
+#endif
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AdvancedAcpiDxe/AcpiByteStream.h b/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AdvancedAcpiDxe/AcpiByteStream.h
new file mode 100644
index 0000000000..b2b6cdf77c
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AdvancedAcpiDxe/AcpiByteStream.h
@@ -0,0 +1,137 @@
+/**@file
+ Byte stream structures for ACPI
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _ACPI_BYTE_STREAM_H_
+#define _ACPI_BYTE_STREAM_H_
+
+#include <IndustryStandard/Acpi.h>
+
+// @todo: Push these macros to Acpi.h file in Edk2 core.
+
+//
+// Definition block ecoding
+//
+
+//
+// External byte stream values and offsets
+//
+#define ACPI_EXTERNAL_PCI_BUS_NUMBER_OFFSET 0xA
+
+
+#define ACPI_SCOPE_PCI_BUS_NUMBER_OFFSET 0x9
+
+
+
+#define ACPI_NAME_OBJECT_STRING_OFFSET 0x6
+
+
+#define ACPI_UNIQUE_ID_NUMBER_OFFSET 0x5
+
+
+#define ACPI_BYTE_PREFIX_OPCODE 0x0A
+#define ACPI_WORD_PREFIX_OPCODE 0x0B
+
+#define ACPI_I2C_RESOURCE_CONTROLLER_NUMBER_OFFSET 0x1F
+
+#define ACPI_STA_RETURN_VALUE_OFFSET 0x9
+#define ACPI_STA_RETURN_VALUE_DEVICE_ENABLED 0xF
+#define ACPI_STA_RETURN_VALUE_DEVICE_DISABLED 0x0
+
+#define ACPI_GPIO_RESOURCE_TYPE 0x1
+#define ACPI_GPIO_RESOURCE_TYPE_INTERRUPT 0x1
+#define ACPI_GPIO_RESOURCE_TYPE_IO 0x2
+
+#define ACPI_I2C_RESOURCE_TYPE 0x2
+
+#define ASCII_0_ORDINAL ((UINT32) '0')
+
+typedef struct {
+ UINT8 GpioConnectionDescriptor; // 0x8C
+ UINT8 Length1;
+ UINT8 Length2;
+ UINT8 RevisionId;
+ UINT8 GpioConnectionType; // 0x0 - Interrupt, 0x01 - IO Connection, 0x02-0xFF reserved
+ UINT8 GeneralFlags1;
+ UINT8 GeneralFlags2;
+ UINT8 InterruptAndIoFlags1;
+ UINT8 InterruptAndIoFlags2;
+ UINT8 PinConfiguration;
+ UINT8 OutputDriveStrength1;
+ UINT8 OutputDriveStrength2;
+ UINT8 DebounceTimeOut1;
+ UINT8 DebounceTimeOut2;
+ UINT8 PinTableOffset1;
+ UINT8 PinTableOffset2;
+ UINT8 ResourceSourceIndex;
+ UINT8 ResourceSourceNameOffset1;
+ UINT8 ResourceSourceNameOffset2;
+ UINT8 VendorDataOffset1;
+ UINT8 VendorDataOffset2;
+ UINT8 VendorDataLength1;
+ UINT8 VendorDataLength2;
+ UINT8 PinNumber1;
+ UINT8 PinNumber2;
+ CHAR8 ResourceSource[15];
+} GPIO_RESOURCE;
+
+typedef enum {
+ GpioInterrupt,
+ GpioIo
+} GPIO_CONNECTION_TYPE;
+
+typedef struct {
+ UINT8 I2cBusConnectionDescriptor; // 0x8E
+ UINT8 Length1;
+ UINT8 Length2;
+ UINT8 RevisionId;
+ UINT8 ResourceSourceIndex;
+ UINT8 SerialBusType; // 0x1 for I2C
+ UINT8 GeneralFlags;
+ UINT8 TypeSpecificFlags1;
+ UINT8 TypeSpecificFlags2;
+ UINT8 TypeSpecificRevisionId; // 0x1 for I2C
+ UINT8 TypeDataLength1; // minimum value 0x6
+ UINT8 TypeDataLength2; // minimum value 0x0
+ UINT32 ConnectionSpeed;
+ UINT16 SlaveAddress;
+ CHAR8 ResourceSource[15];
+} I2C_SERIAL_BUS_RESOURCE;
+
+typedef struct {
+ UINT8 ResourceType;
+ UINT16 GpioNumber;
+ UINT8 GpioResourceType;
+ BOOLEAN Shared;
+} GPIO_RESOURCE_DATA;
+
+typedef struct {
+ UINT8 ResourceType;
+ UINT32 I2cSlaveAddress;
+ UINT32 ConnectionSpeed;
+ UINT8 I2cSliceNumber;
+} I2C_RESOURCE_DATA;
+
+typedef struct {
+ CHAR8 DeviceName[4];
+ CHAR8 HardwareId[8];
+ CHAR8 CompatibilityId[8];
+ UINT32 UniqueId;
+ UINT8 Address;
+ CHAR8 DosDeviceName[32];
+ UINT8 EnableStatus;
+ UINT8 NumberOfResources;
+} SSDT_DEVICE_DATA;
+
+typedef struct {
+ EFI_GUID Guid;
+ UINT8 Revision;
+ UINT16 Count;
+ UINT8 Rsvd[5];
+} PCT_ACPI_BLOCK_HDR;
+
+#endif
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AdvancedAcpiDxe/AcpiPlatform.c b/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AdvancedAcpiDxe/AcpiPlatform.c
new file mode 100644
index 0000000000..3a70d0b1b7
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AdvancedAcpiDxe/AcpiPlatform.c
@@ -0,0 +1,1716 @@
+/** @file
+ Advanced ACPI Driver
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+#include <Base.h>
+#include <Uefi.h>
+#include <Library/HobLib.h>
+#include <Guid/HobList.h>
+#include <Protocol/FirmwareVolume2.h>
+#include <PlatformBoardId.h>
+#include <IndustryStandard/AcpiAml.h>
+#include <IndustryStandard/Pci30.h>
+#include "AcpiPlatform.h"
+#include <Library/PciSegmentLib.h>
+#include <Library/PchInfoLib.h>
+#include <Library/PchPcieRpLib.h>
+#include <Library/GpioLib.h>
+#include <Library/EspiLib.h>
+#include <Library/PchPciBdfLib.h>
+#include <PlatformBoardConfig.h>
+#include <Library/CpuPlatformLib.h>
+#include <Protocol/VariableLock.h>
+#include <Mcfg.h>
+#include <Library/GraphicsInfoLib.h>
+#include "GenSsdtLib.h"
+// Global variables
+//
+GLOBAL_REMOVE_IF_UNREFERENCED VOID *mGfxNvsAddress;
+GLOBAL_REMOVE_IF_UNREFERENCED PLATFORM_NVS_AREA_PROTOCOL mPlatformNvsAreaProtocol;
+
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_CPU_IO2_PROTOCOL *mCpuIo;
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_CPU_ID_ORDER_MAP *mCpuApicIdOrderTable;
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_CPU_APIC_ID_REORDER_MAP *mCpuApicIdReorderTable;
+GLOBAL_REMOVE_IF_UNREFERENCED UINTN mNumberOfCpus;
+GLOBAL_REMOVE_IF_UNREFERENCED UINTN mNumberOfEnabledCpus;
+GLOBAL_REMOVE_IF_UNREFERENCED BOOLEAN IsX2ApicMode;
+
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_CPU_PACKAGE_INFO mSbspPackageInfo;
+//
+// Function implementations
+//
+
+/**
+ Install Soc ACPI Table
+
+ @param[in] *SsdtTableGuid Pointer to GUID that identifies new SSDT table
+ @param[in] Signature Signature of the table
+
+**/
+VOID
+STATIC
+InstallSocAcpiTable (
+ IN EFI_GUID *SsdtTableGuid,
+ IN UINT64 Signature
+ )
+{
+ EFI_STATUS Status;
+ EFI_HANDLE *HandleBuffer;
+ UINTN NumberOfHandles;
+ UINTN Index;
+ INTN Instance;
+ UINTN Size;
+ UINT32 FvStatus;
+ UINTN TableHandle;
+ EFI_FV_FILETYPE FileType;
+ EFI_FV_FILE_ATTRIBUTES Attributes;
+ EFI_FIRMWARE_VOLUME2_PROTOCOL *FwVol;
+ EFI_ACPI_TABLE_PROTOCOL *AcpiTable;
+ EFI_ACPI_DESCRIPTION_HEADER *TableHeader;
+ EFI_ACPI_COMMON_HEADER *Table;
+
+ FwVol = NULL;
+ Table = NULL;
+
+ //
+ // Locate FV protocol.
+ //
+ Status = gBS->LocateHandleBuffer (
+ ByProtocol,
+ &gEfiFirmwareVolume2ProtocolGuid,
+ NULL,
+ &NumberOfHandles,
+ &HandleBuffer
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Look for FV with ACPI storage file
+ //
+ for (Index = 0; Index < NumberOfHandles; Index++) {
+ //
+ // Get the protocol on this handle
+ // This should not fail because of LocateHandleBuffer
+ //
+ Status = gBS->HandleProtocol (
+ HandleBuffer[Index],
+ &gEfiFirmwareVolume2ProtocolGuid,
+ (VOID **) &FwVol
+ );
+ ASSERT_EFI_ERROR (Status);
+ if (FwVol == NULL) {
+ return;
+ }
+ //
+ // See if it has the ACPI storage file
+ //
+ Size = 0;
+ FvStatus = 0;
+ Status = FwVol->ReadFile (
+ FwVol,
+ SsdtTableGuid,
+ NULL,
+ &Size,
+ &FileType,
+ &Attributes,
+ &FvStatus
+ );
+ if (!EFI_ERROR (Status)) {
+ break;
+ }
+ }
+ //
+ // Free any allocated buffers
+ //
+ FreePool (HandleBuffer);
+
+ //
+ // Sanity check that we found our data file
+ //
+ ASSERT (FwVol);
+
+ //
+ // Locate ACPI tables
+ //
+ Status = gBS->LocateProtocol (&gEfiAcpiTableProtocolGuid, NULL, (VOID **) &AcpiTable);
+
+ //
+ // Read tables from the storage file.
+ //
+ if (FwVol == NULL) {
+ ASSERT_EFI_ERROR (EFI_NOT_FOUND);
+ return;
+ }
+ Instance = 0;
+
+ while (Status == EFI_SUCCESS) {
+ //
+ // Read the ACPI tables
+ //
+ Status = FwVol->ReadSection (
+ FwVol,
+ SsdtTableGuid,
+ EFI_SECTION_RAW,
+ Instance,
+ (VOID **) &Table,
+ &Size,
+ &FvStatus
+ );
+ if (!EFI_ERROR (Status)) {
+ TableHeader = (EFI_ACPI_DESCRIPTION_HEADER *) Table;
+
+ if (((EFI_ACPI_DESCRIPTION_HEADER *) TableHeader)->OemTableId == Signature) {
+ TableHandle = 0;
+ //
+ // Add the table
+ //
+ Status = AcpiTable->InstallAcpiTable (
+ AcpiTable,
+ TableHeader,
+ TableHeader->Length,
+ &TableHandle
+ );
+ }
+
+ //
+ // Increment the instance
+ //
+ Instance++;
+ Table = NULL;
+ }
+ }
+}
+
+/**
+ Install Xhci ACPI Table
+**/
+VOID
+InstallXhciAcpiTable (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+ EFI_FIRMWARE_VOLUME2_PROTOCOL *FwVol;
+ EFI_ACPI_COMMON_HEADER *CurrentTable;
+ UINT32 FvStatus;
+ UINTN Size;
+ UINTN TableHandle;
+ INTN Instance;
+ EFI_ACPI_TABLE_PROTOCOL *AcpiTable;
+ EFI_ACPI_DESCRIPTION_HEADER *TableHeader;
+ EFI_GUID EfiAcpiMultiTableStorageGuid;
+
+ EfiAcpiMultiTableStorageGuid = gAcpiTableStorageGuid;
+ Instance = 0;
+ TableHandle = 0;
+ CurrentTable = NULL;
+ FwVol = NULL;
+
+ DEBUG ((DEBUG_INFO, "InstallXhciAcpiTable\n"));
+ //
+ // Update OEM table ID
+ //
+ if (PcdGet64 (PcdXhciAcpiTableSignature) == 0) {
+ DEBUG ((DEBUG_INFO, "InstallXhciAcpiTable: Cannot find PcdXhciAcpiTableSignature\n"));
+ return;
+ }
+
+ //
+ // Find the AcpiSupport protocol
+ //
+ Status = LocateSupportProtocol (
+ &gEfiAcpiTableProtocolGuid,
+ EfiAcpiMultiTableStorageGuid,
+ (VOID **) &AcpiTable,
+ FALSE
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Locate the firmware volume protocol
+ //
+ Status = LocateSupportProtocol (
+ &gEfiFirmwareVolume2ProtocolGuid,
+ EfiAcpiMultiTableStorageGuid,
+ (VOID **) &FwVol,
+ TRUE
+ );
+
+ //
+ // Read tables from the storage file.
+ //
+ while (Status == EFI_SUCCESS) {
+ Status = FwVol->ReadSection (
+ FwVol,
+ &EfiAcpiMultiTableStorageGuid,
+ EFI_SECTION_RAW,
+ Instance,
+ (VOID **) &CurrentTable,
+ &Size,
+ &FvStatus
+ );
+
+ if (!EFI_ERROR (Status)) {
+
+ TableHeader = (EFI_ACPI_DESCRIPTION_HEADER *) CurrentTable;
+
+ if (TableHeader->OemTableId == PcdGet64 (PcdXhciAcpiTableSignature)) {
+ DEBUG ((DEBUG_INFO, "Install xhci table: %x\n", TableHeader->OemTableId));
+ //
+ // Add the table
+ //
+ TableHandle = 0;
+
+ Status = AcpiTable->InstallAcpiTable (
+ AcpiTable,
+ CurrentTable,
+ CurrentTable->Length,
+ &TableHandle
+ );
+
+ break;
+ }
+
+ //
+ // Increment the instance
+ //
+ Instance++;
+ gBS->FreePool (CurrentTable);
+ CurrentTable = NULL;
+ }
+ }
+
+ if (CurrentTable != NULL) {
+ gBS->FreePool (CurrentTable);
+ CurrentTable = NULL;
+ }
+}
+
+/**
+ Locate the first instance of a protocol. If the protocol requested is an
+ FV protocol, then it will return the first FV that contains the ACPI table
+ storage file.
+
+ @param[in] Protocol The protocol to find.
+ @param[in] Instance Return pointer to the first instance of the protocol.
+ @param[in] Type TRUE if the desired protocol is a FV protocol.
+
+ @retval EFI_SUCCESS The function completed successfully.
+ @retval EFI_NOT_FOUND The protocol could not be located.
+ @retval EFI_OUT_OF_RESOURCES There are not enough resources to find the protocol.
+**/
+EFI_STATUS
+LocateSupportProtocol (
+ IN EFI_GUID *Protocol,
+ IN EFI_GUID gEfiAcpiMultiTableStorageGuid,
+ OUT VOID **Instance,
+ IN BOOLEAN Type
+ )
+{
+ EFI_STATUS Status;
+ EFI_HANDLE *HandleBuffer;
+ UINTN NumberOfHandles;
+ EFI_FV_FILETYPE FileType;
+ UINT32 FvStatus;
+ EFI_FV_FILE_ATTRIBUTES Attributes;
+ UINTN Size;
+ UINTN Index;
+
+ //
+ // Locate protocol.
+ //
+ Status = gBS->LocateHandleBuffer (
+ ByProtocol,
+ Protocol,
+ NULL,
+ &NumberOfHandles,
+ &HandleBuffer
+ );
+ if (EFI_ERROR (Status)) {
+ //
+ // Defined errors at this time are not found and out of resources.
+ //
+ return Status;
+ }
+
+ //
+ // Looking for FV with ACPI storage file
+ //
+ for (Index = 0; Index < NumberOfHandles; Index++) {
+
+ //
+ // Get the protocol on this handle
+ // This should not fail because of LocateHandleBuffer
+ //
+ Status = gBS->HandleProtocol (
+ HandleBuffer[Index],
+ Protocol,
+ Instance
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ if (!Type) {
+
+ //
+ // Not looking for the FV protocol, so find the first instance of the
+ // protocol. There should not be any errors because our handle buffer
+ // should always contain at least one or LocateHandleBuffer would have
+ // returned not found.
+ //
+ break;
+ }
+
+ //
+ // See if it has the ACPI storage file
+ //
+ Size = 0;
+ FvStatus = 0;
+ Status = ((EFI_FIRMWARE_VOLUME2_PROTOCOL *) (*Instance))->ReadFile (
+ *Instance,
+ &gEfiAcpiMultiTableStorageGuid,
+ NULL,
+ &Size,
+ &FileType,
+ &Attributes,
+ &FvStatus
+ );
+
+ //
+ // If we found it, then we are done
+ //
+ if (Status == EFI_SUCCESS) {
+ break;
+ }
+ }
+
+ //
+ // Our exit status is determined by the success of the previous operations
+ // If the protocol was found, Instance already points to it.
+ //
+ //
+ // Free any allocated buffers
+ //
+ FreePool (HandleBuffer);
+
+ return Status;
+}
+
+/**
+ This function will update any runtime platform specific information.
+ This currently includes:
+ Setting OEM table values, ID, table ID, creator ID and creator revision.
+ Enabling the proper processor entries in the APIC tables
+ It also indicates with which ACPI table version the table belongs.
+
+ @param[in] Table The table to update
+ @param[in] Version Where to install this table
+
+ @retval EFI_SUCCESS Updated tables commplete.
+**/
+EFI_STATUS
+PlatformUpdateTables (
+ IN OUT EFI_ACPI_COMMON_HEADER *Table,
+ IN OUT EFI_ACPI_TABLE_VERSION *Version
+ )
+{
+ EFI_ACPI_DESCRIPTION_HEADER *TableHeader;
+ UINT8 *CurrPtr;
+ UINT8 *TmpDsdtPointer;
+ UINT8 *EndPtr;
+ EFI_ACPI_1_0_PROCESSOR_LOCAL_APIC_STRUCTURE *ApicPtr;
+ EFI_STATUS Status;
+ EFI_MP_SERVICES_PROTOCOL *MpService;
+
+ UINT8 MaximumDsdtPointLength;
+
+ EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;
+ UINT32 LocalApicCounter;
+
+
+ CurrPtr = NULL;
+ EndPtr = NULL;
+ ApicPtr = NULL;
+
+ LocalApicCounter = 0;
+ MaximumDsdtPointLength = 20;
+
+ //
+ // This will be accurate except for FACS structure
+ //
+ TableHeader = (EFI_ACPI_DESCRIPTION_HEADER *) Table;
+
+ //
+ // Update the OEM and creator information for every table except FACS.
+ //
+ if (Table->Signature != EFI_ACPI_1_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE) {
+ if ((Table->Signature == EFI_ACPI_1_0_SECONDARY_SYSTEM_DESCRIPTION_TABLE_SIGNATURE) &&
+ (CompareMem (&TableHeader->OemId, "Rtd3", 4) == 0)) {
+ // For SsdtRtd3 table, "OemId" update is done later
+ } else {
+ CopyMem (TableHeader->OemId, PcdGetPtr (PcdAcpiDefaultOemId), sizeof (TableHeader->OemId));
+ }
+
+ //
+ // Skip OEM table ID and creator information for SSDT tables, since these are
+ // created by an ASL compiler and the creator information is useful.
+ //
+ if (Table->Signature != EFI_ACPI_1_0_SECONDARY_SYSTEM_DESCRIPTION_TABLE_SIGNATURE) {
+ //
+ // Set through patchable PCD value
+ //
+ TableHeader->OemTableId = PcdGet64 (PcdAcpiDefaultOemTableId);
+ TableHeader->OemRevision = PcdGet32(PcdAcpiDefaultOemRevision);
+
+ //
+ // Update creator information
+ //
+ TableHeader->CreatorId = PcdGet32 (PcdAcpiDefaultCreatorId);
+ TableHeader->CreatorRevision = PcdGet32 (PcdAcpiDefaultCreatorRevision) ;
+ }
+ }
+
+ //
+ // Locate the PCI IO protocol
+ //
+ Status = gBS->LocateProtocol (
+ &gEfiPciRootBridgeIoProtocolGuid,
+ NULL,
+ (VOID **) &PciRootBridgeIo
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Locate the MP services protocol
+ // Find the MP Protocol. This is an MP platform, so MP protocol must be there.
+ //
+ Status = gBS->LocateProtocol (
+ &gEfiMpServiceProtocolGuid,
+ NULL,
+ (VOID **) &MpService
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Get supported CPU Interrupt model (xApic or x2Apic)
+ //
+ IsX2ApicMode = (GetApicMode() == LOCAL_APIC_MODE_X2APIC) ? TRUE : FALSE;
+
+ //
+ // By default, a table belongs in all ACPI table versions published.
+ // Some tables will override this because they have different versions of the table.
+ //
+ *Version = EFI_ACPI_TABLE_VERSION_1_0B | EFI_ACPI_TABLE_VERSION_2_0 | EFI_ACPI_TABLE_VERSION_3_0;
+
+ //
+ // Update the various table types with the necessary updates
+ //
+ switch (Table->Signature) {
+
+ case EFI_ACPI_1_0_APIC_SIGNATURE:
+ //
+ // if not MP and not APIC then don't publish the APIC tables.
+ //
+ //@todo mSystemConfiguration.ApicEnabled default value is 1. So, the following logic is not executed.
+ //if (mSystemConfiguration.ApicEnabled == 0) {
+ // *Version = EFI_ACPI_TABLE_VERSION_NONE;
+ // break;
+ //}
+ CurrPtr = (UINT8 *) &((EFI_ACPI_DESCRIPTION_HEADER *) Table)[1];
+ CurrPtr = CurrPtr + 8;
+ //
+ // Size of Local APIC Address & Flag
+ //
+ EndPtr = (UINT8 *) Table;
+ EndPtr = EndPtr + Table->Length;
+
+ ApicPtr = (EFI_ACPI_1_0_PROCESSOR_LOCAL_APIC_STRUCTURE *) CurrPtr;
+ DEBUG((DEBUG_INFO, "ApicPtr Type = %x \n ", ApicPtr->Type));
+ if ((IsX2ApicMode && ApicPtr->Type == EFI_ACPI_1_0_PROCESSOR_LOCAL_APIC) ||(!IsX2ApicMode && ApicPtr->Type == EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC)) {
+ // Lets skip the MADT table in below cases:
+ // 1. MADT table with Local APIC records when X2Apic Mode is enabled.
+ // 2. MADT table with x2Apic records when xApic Mode is enabled.
+
+ *Version = EFI_ACPI_TABLE_VERSION_NONE;
+ break;
+ }
+
+ //
+ // Call for Local APIC ID Reorder
+ //
+ SortCpuLocalApicInTable(MpService);
+
+ while (CurrPtr < EndPtr) {
+ ApicPtr = (EFI_ACPI_1_0_PROCESSOR_LOCAL_APIC_STRUCTURE *) CurrPtr;
+
+ //
+ // Check table entry type
+ //
+ if ((ApicPtr->Type == EFI_ACPI_1_0_PROCESSOR_LOCAL_APIC) || (ApicPtr->Type == EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC)) {
+ AppendCpuMapTableEntry (
+ ApicPtr,
+ LocalApicCounter
+ );
+ LocalApicCounter++;
+ }
+
+ //
+ // Go to the next structure in the APIC table
+ //
+ CurrPtr = CurrPtr + ApicPtr->Length;
+ }
+ break;
+
+ case EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE:
+ //
+ // Fix up all FACP Table values if configuration requires it.
+ // This code fixes up the following Table values:
+ // (1) C2/C3/CST Enable FACP values
+ // (2) RTC S4 Flag
+ //
+ {
+ EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE *FadtPointer;
+
+ FadtPointer = (EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE *) Table;
+
+ //
+ // Check the version of the table
+ //
+ *Version = EFI_ACPI_TABLE_VERSION_NONE;
+ if (FadtPointer->Header.Revision == EFI_ACPI_1_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION) {
+ *Version = EFI_ACPI_TABLE_VERSION_NONE;
+ } else if (FadtPointer->Header.Revision == EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION) {
+ *Version = EFI_ACPI_TABLE_VERSION_1_0B | EFI_ACPI_TABLE_VERSION_2_0;
+ } else if (FadtPointer->Header.Revision == EFI_ACPI_3_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION) {
+ *Version = EFI_ACPI_TABLE_VERSION_1_0B | EFI_ACPI_TABLE_VERSION_3_0;
+ } else if (FadtPointer->Header.Revision == EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION) {
+ *Version = EFI_ACPI_TABLE_VERSION_1_0B | EFI_ACPI_TABLE_VERSION_5_0;
+ } else if (FadtPointer->Header.Revision == EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE_REVISION) {
+ *Version = EFI_ACPI_TABLE_VERSION_5_0;
+ } else if (FadtPointer->Header.Revision == EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE_REVISION) {
+ *Version = EFI_ACPI_TABLE_VERSION_5_0;
+ }
+
+
+ //
+ // Modify Preferred_PM_Profile field based on Board SKU's. Default is set to Mobile
+ //
+ FadtPointer->PreferredPmProfile = PcdGet8 (PcdPreferredPmProfile);
+
+
+ //
+ // PME WAKE supported, set PCI_EXP_WAK, BIT14 of Fixed feature flags.
+ //
+ FadtPointer->Flags |= (EFI_ACPI_6_0_PCI_EXP_WAK);
+
+ FadtPointer->Flags &= ~(EFI_ACPI_2_0_PWR_BUTTON); // clear indicates the power button is handled as a fixed feature programming model
+
+ //
+ // 1. set header revision.
+ //
+ FadtPointer->Header.Revision = EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE_REVISION;
+
+ //
+ // 2. set all GAR register AccessSize to valid value.
+ //
+ ((EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE *)FadtPointer)->ResetReg.AccessSize = EFI_ACPI_6_3_BYTE;
+ ((EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE *)FadtPointer)->XPm1aEvtBlk.AccessSize = EFI_ACPI_6_3_WORD;
+ ((EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE *)FadtPointer)->XPm1bEvtBlk.AccessSize = EFI_ACPI_6_3_WORD;
+ ((EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE *)FadtPointer)->XPm1aCntBlk.AccessSize = EFI_ACPI_6_3_WORD;
+ ((EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE *)FadtPointer)->XPm1bCntBlk.AccessSize = EFI_ACPI_6_3_WORD;
+ ((EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE *)FadtPointer)->XPm2CntBlk.AccessSize = EFI_ACPI_6_3_BYTE;
+ ((EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE *)FadtPointer)->XPmTmrBlk.AccessSize = EFI_ACPI_6_3_DWORD;
+ ((EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE *)FadtPointer)->XGpe0Blk.AccessSize = EFI_ACPI_6_3_BYTE;
+ ((EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE *)FadtPointer)->XGpe1Blk.AccessSize = EFI_ACPI_6_3_BYTE;
+
+ //
+ // SLEEP_CONTROL_REG and SLEEP_STATUS_REG are optional
+ // Only implement in HW-Reduced ACPI system
+ // In non-HW-Reduced system will remain all 0 as default
+ //
+ if ((FadtPointer->Flags & EFI_ACPI_6_3_HW_REDUCED_ACPI) != 0) {
+ //
+ // If the HW_REDUCED_ACPI flag in the table is set, OSPM will ignore fields related to the ACPI HW
+ //
+ ((EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE *)FadtPointer)->SleepControlReg.AddressSpaceId = 0x1;
+ ((EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE *)FadtPointer)->SleepControlReg.RegisterBitWidth = 0x8;
+ ((EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE *)FadtPointer)->SleepControlReg.RegisterBitOffset = 0;
+ ((EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE *)FadtPointer)->SleepControlReg.AccessSize = EFI_ACPI_6_3_DWORD;
+ ((EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE *)FadtPointer)->SleepControlReg.Address = EFI_ACPI_PM1A_EVT_BLK_ADDRESS + 4;
+
+ ((EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE *)FadtPointer)->SleepStatusReg.AddressSpaceId = 0x1;
+ ((EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE *)FadtPointer)->SleepStatusReg.RegisterBitWidth = 0x8;
+ ((EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE *)FadtPointer)->SleepStatusReg.RegisterBitOffset = 0;
+ ((EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE *)FadtPointer)->SleepStatusReg.AccessSize = EFI_ACPI_6_3_DWORD;
+ ((EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE *)FadtPointer)->SleepStatusReg.Address = EFI_ACPI_PM1A_EVT_BLK_ADDRESS;
+ }
+
+ //
+ // Set the S4BiosReq to 0 as we don't support it in the FACS for TGL.
+ //
+ FadtPointer->S4BiosReq = 0;
+
+ //@todo RtcS4WakeEnable and PmTimerEnable default value is 1. So, the following logic is not executed.
+ ////
+ //// Check if RTC S4 is enabled
+ ////
+ //if (!mSystemConfiguration.RtcS4WakeEnable) {
+
+ // //
+ // // Clear the S4 RTC flag
+ // //
+ // FadtPointer->Flags &= ~EFI_ACPI_2_0_RTC_S4;
+ //}
+
+ ////
+ //// Check if PM timer is enabled
+ ////
+ //if (!mSystemConfiguration.PmTimerEnable) {
+
+ // //
+ // // Clear the PM timer flag
+ // //
+ // FadtPointer->Flags &= ~EFI_ACPI_3_0_USE_PLATFORM_CLOCK;
+ //}
+ }
+ break;
+
+ case EFI_ACPI_1_0_PERSISTENT_SYSTEM_DESCRIPTION_TABLE_SIGNATURE:
+ //
+ // These items only belong in the 1.0 tables.
+ //
+ *Version = EFI_ACPI_TABLE_VERSION_1_0B;
+ break;
+
+ case EFI_ACPI_2_0_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE:
+ //
+ // Fix up the AML code in the DSDT affected by end user options.
+ // Fix up the following ASL Code:
+ // (1) ACPI Global NVS Memory Base and Size.
+ // (2) ACPI Graphics NVS Memory Base and Size.
+ // (3) SMBus I/O Base.
+ // (4) Thermal Management Methods.
+ //
+ {
+ UINT8 *DsdtPointer;
+ UINT32 *Signature;
+ UINT8 *Operation;
+ UINT32 *Address;
+ UINT8 *Value;
+ UINT16 *Size;
+ //
+ // Loop through the ASL looking for values that we must fix up.
+ //
+ CurrPtr = (UINT8 *) Table;
+ for (DsdtPointer = CurrPtr;
+ DsdtPointer < (CurrPtr + ((EFI_ACPI_COMMON_HEADER *) CurrPtr)->Length - sizeof (UINT32));
+ DsdtPointer++
+ ) {
+ Signature = (UINT32 *) DsdtPointer;
+ switch (*Signature) {
+ //
+ // GNVS operation region
+ //
+ case (SIGNATURE_32 ('G', 'N', 'V', 'S')):
+ //
+ // Conditional match. For Region Objects, the Operator will always be the
+ // byte immediately before the specific name. Therefore, subtract 1 to check
+ // the Operator.
+ //
+ Operation = DsdtPointer - 1;
+ if (*Operation == AML_EXT_REGION_OP) {
+ Address = (UINT32 *) (DsdtPointer + 6);
+ *Address = (UINT32) (UINTN) mPlatformNvsAreaProtocol.Area;
+ Size = (UINT16 *) (DsdtPointer + 11);
+ *Size = sizeof (PLATFORM_NVS_AREA);
+ }
+ break;
+
+ //
+ // _UPC method for Device (\_SB.PC00.XHCI.RHUB)
+ //
+ case (SIGNATURE_32('H', 'S', '1', '3')):
+ for (TmpDsdtPointer = DsdtPointer;
+ TmpDsdtPointer <= DsdtPointer + MaximumDsdtPointLength;
+ TmpDsdtPointer++){
+ Signature = (UINT32 *) TmpDsdtPointer;
+ switch (*Signature) {
+ case(SIGNATURE_32('U', 'P', 'C', 'P')):
+ Value = (UINT8 *)((UINT32 *)TmpDsdtPointer + 2);
+ break;
+ default:
+ //
+ // Do nothing.
+ //
+ break;
+ }
+ }
+ break;
+
+
+
+ default:
+ //
+ // Do nothing.
+ //
+ break;
+ }
+ }
+ }
+ break;
+
+ case EFI_ACPI_3_0_HIGH_PRECISION_EVENT_TIMER_TABLE_SIGNATURE:
+ break;
+
+ case EFI_ACPI_3_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE:
+ //
+ // Update MCFG base and end bus number
+ //
+ ((EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_DESCRIPTION_TABLE *) Table)->AllocationStructure[0].BaseAddress
+ = PcdGet64 (PcdPciExpressBaseAddress);
+
+ ((EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_DESCRIPTION_TABLE *) Table)->AllocationStructure[0].EndBusNumber
+ = (UINT8)(PcdGet32 (PcdPciExpressRegionLength) / 0x100000) - 1;
+
+
+ {
+ ((EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_DESCRIPTION_TABLE *) Table)->Header.Length -= sizeof (EFI_ACPI_MEMORY_MAPPED_ENHANCED_CONFIGURATION_SPACE_BASE_ADDRESS_ALLOCATION_STRUCTURE);
+ }
+ break;
+
+ case EFI_ACPI_5_0_EMBEDDED_CONTROLLER_BOOT_RESOURCES_TABLE_SIGNATURE:
+ //
+ // If EC is not present, don't publish the table.
+ //
+ if (mPlatformNvsAreaProtocol.Area->EcAvailable == PLATFORM_NVS_DEVICE_DISABLE) {
+ *Version = EFI_ACPI_TABLE_VERSION_NONE;
+ }
+ break;
+
+/* @todo Need to uncomment once MSFT fully implements uPEP
+ case SIGNATURE_32 ('L', 'P', 'I', 'T'):
+ //
+ // If L0s is disabled in setup, don't publish the table.
+ //
+ if (mSystemConfiguration.LowPowerS0Idle == 0) {
+ *Version = EFI_ACPI_TABLE_VERSION_NONE;
+ }
+ break;
+*/
+ case EFI_ACPI_1_0_SECONDARY_SYSTEM_DESCRIPTION_TABLE_SIGNATURE:
+ {
+ UINT8 *TablePointer;
+ UINT32 *Signature;
+
+ //
+ // Do not load the xHCI table. It is handled by separate function.
+ //
+ if (CompareMem (&TableHeader->OemTableId, "xh_", 3) == 0) {
+ DEBUG((DEBUG_INFO,"TableHeader->OemTableId = %x\n ", TableHeader->OemTableId));
+ *Version = EFI_ACPI_TABLE_VERSION_NONE;
+ }
+
+ //
+ // Load SSDT tables for the platforms based on boardID; default to RVP tables.
+ // Load Ther_Rvp for all others.
+ //
+ if (CompareMem (&TableHeader->OemTableId, "Ther_Rvp", 8) == 0) {
+ CurrPtr = (UINT8 *) Table;
+ for (TablePointer = CurrPtr;TablePointer < (CurrPtr + ((EFI_ACPI_COMMON_HEADER *) CurrPtr)->Length - sizeof (UINT32));TablePointer++)
+ {
+ Signature = (UINT32 *) TablePointer;
+ switch (*Signature) {
+ }
+ }
+ }
+
+ //
+ // Load RTD3 SSDT table for ADL RVP SKUs
+ // Note: "OemId" field is used to indentify whether SSDT table is for RTD3 usage
+ //
+ if ((CompareMem (&TableHeader->OemId, "Rtd3", 4) == 0)) {
+ //
+ // OemId should be replaced with PcdAcpiDefaultOemId
+ //
+ CopyMem (TableHeader->OemId, PcdGetPtr (PcdAcpiDefaultOemId), sizeof (TableHeader->OemId));
+ //
+ // set default = none
+ //
+ *Version = EFI_ACPI_TABLE_VERSION_NONE;
+ } // Load RTD3 SSDT table
+ }
+ break;
+
+ default:
+ break;
+ }
+ return EFI_SUCCESS;
+}
+
+/**
+ This function calculates RCR based on PCI Device ID and Vendor ID from the devices
+ available on the platform.
+ It also includes other instances of BIOS change to calculate CRC and provides as
+ HWSignature filed in FADT table.
+**/
+VOID
+IsHardwareChange (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+ UINTN Index;
+ UINTN HandleCount;
+ EFI_HANDLE *HandleBuffer;
+ EFI_PCI_IO_PROTOCOL *PciIo;
+ UINT32 CRC;
+ UINT32 *HWChange;
+ UINTN HWChangeSize;
+ UINT32 PciId;
+ UINTN Handle;
+ EFI_ACPI_2_0_FIRMWARE_ACPI_CONTROL_STRUCTURE *FacsPtr;
+ EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE *pFADT;
+
+ HandleCount = 0;
+ HandleBuffer = NULL;
+
+ Status = gBS->LocateHandleBuffer (
+ ByProtocol,
+ &gEfiPciIoProtocolGuid,
+ NULL,
+ &HandleCount,
+ &HandleBuffer
+ );
+ if (EFI_ERROR (Status)) {
+ return; // PciIO protocol not installed yet!
+ }
+
+ if (HandleCount > 0x1FFF) { // PCI config space max limit
+ return;
+ }
+
+ //
+ // Allocate memory for HWChange and add additional entrie for
+ // pFADT->XDsdt
+ //
+ HWChangeSize = HandleCount + 1;
+ HWChange = AllocateZeroPool( sizeof(UINT32) * HWChangeSize );
+ ASSERT( HWChange != NULL );
+
+ if (HWChange == NULL) return;
+
+ //
+ // add HWChange inputs: PCI devices
+ //
+ for (Index = 0; HandleCount > 0; HandleCount--) {
+ PciId = 0;
+ Status = gBS->HandleProtocol (HandleBuffer[Index], &gEfiPciIoProtocolGuid, (VOID **) &PciIo);
+ if (!EFI_ERROR (Status)) {
+ Status = PciIo->Pci.Read (PciIo, EfiPciIoWidthUint32, 0, 1, &PciId);
+ if (EFI_ERROR (Status)) {
+ continue;
+ }
+ HWChange[Index++] = PciId;
+ }
+ }
+
+ //
+ // Locate FACP Table
+ //
+ Handle = 0;
+ Status = LocateAcpiTableBySignature (
+ EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE,
+ (EFI_ACPI_DESCRIPTION_HEADER **) &pFADT,
+ &Handle
+ );
+ if (EFI_ERROR (Status) || (pFADT == NULL)) {
+ return; //Table not found or out of memory resource for pFADT table
+ }
+
+ //
+ // add HWChange inputs: others
+ //
+ HWChange[Index++] = (UINT32)pFADT->XDsdt;
+
+ //
+ // Calculate CRC value with HWChange data.
+ //
+ Status = gBS->CalculateCrc32(HWChange, sizeof(UINT32) * HWChangeSize, &CRC);
+ DEBUG((DEBUG_INFO,"CRC = %x and Status = %r\n", CRC, Status));
+
+ //
+ // Set HardwareSignature value based on CRC value.
+ //
+ FacsPtr = (EFI_ACPI_2_0_FIRMWARE_ACPI_CONTROL_STRUCTURE *)(UINTN)pFADT->FirmwareCtrl;
+ FacsPtr->HardwareSignature = CRC;
+ FreePool( HWChange );
+}
+
+EFI_STATUS
+PublishAcpiTablesFromFv (
+ IN EFI_GUID gEfiAcpiMultiTableStorageGuid
+ )
+{
+ EFI_STATUS Status;
+ EFI_FIRMWARE_VOLUME2_PROTOCOL *FwVol;
+ EFI_ACPI_COMMON_HEADER *CurrentTable;
+ UINT32 FvStatus;
+ UINTN Size;
+ EFI_ACPI_TABLE_VERSION Version;
+ UINTN TableHandle;
+ INTN Instance;
+ EFI_ACPI_TABLE_PROTOCOL *AcpiTable;
+
+ Instance = 0;
+ TableHandle = 0;
+ CurrentTable = NULL;
+ FwVol = NULL;
+
+ //
+ // Find the AcpiSupport protocol
+ //
+ Status = LocateSupportProtocol (
+ &gEfiAcpiTableProtocolGuid,
+ gEfiAcpiMultiTableStorageGuid,
+ (VOID **) &AcpiTable,
+ FALSE
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Locate the firmware volume protocol
+ //
+ Status = LocateSupportProtocol (
+ &gEfiFirmwareVolume2ProtocolGuid,
+ gEfiAcpiMultiTableStorageGuid,
+ (VOID **) &FwVol,
+ TRUE
+ );
+
+ /* TODO: Hang at native mode. Need to find the cause
+ * when the related drivers are finished for native support. */
+ //ASSERT_EFI_ERROR (Status);
+
+ //
+ // Read tables from the storage file.
+ //
+ while (Status == EFI_SUCCESS) {
+ Status = FwVol->ReadSection (
+ FwVol,
+ &gEfiAcpiMultiTableStorageGuid,
+ EFI_SECTION_RAW,
+ Instance,
+ (VOID **) &CurrentTable,
+ &Size,
+ &FvStatus
+ );
+
+ if (!EFI_ERROR (Status)) {
+
+ //
+ // Perform any table specific updates.
+ //
+ PlatformUpdateTables (CurrentTable, &Version);
+
+ //
+ // Add the table
+ //
+ TableHandle = 0;
+
+ if (Version != EFI_ACPI_TABLE_VERSION_NONE) {
+ DEBUG((DEBUG_INFO, "[Advanced ACPI] Installing table: %x : %x\n", CurrentTable->Signature, CurrentTable));
+ Status = AcpiTable->InstallAcpiTable (
+ AcpiTable,
+ CurrentTable,
+ CurrentTable->Length,
+ &TableHandle
+ );
+ }
+
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Increment the instance
+ //
+ Instance++;
+ gBS->FreePool (CurrentTable);
+ CurrentTable = NULL;
+ }
+
+ if (CurrentTable != NULL) {
+ gBS->FreePool (CurrentTable);
+ CurrentTable = NULL;
+ }
+ }
+
+ //
+ // Finished
+ //
+ return EFI_SUCCESS;
+}
+
+
+/**
+ Allocate MemoryType below 4G memory address.
+
+ @param[in] Size - Size of memory to allocate.
+ @param[in] Buffer - Allocated address for output.
+
+ @retval EFI_SUCCESS - Memory successfully allocated.
+ @retval Other - Other errors occur.
+
+**/
+EFI_STATUS
+AllocateMemoryBelow4G (
+ IN EFI_MEMORY_TYPE MemoryType,
+ IN UINTN Size,
+ OUT VOID **Buffer
+ )
+{
+ UINTN Pages;
+ EFI_PHYSICAL_ADDRESS Address;
+ EFI_STATUS Status;
+
+ Pages = EFI_SIZE_TO_PAGES (Size);
+ Address = 0xffffffff;
+
+ Status = (gBS->AllocatePages) (
+ AllocateMaxAddress,
+ MemoryType,
+ Pages,
+ &Address
+ );
+
+ *Buffer = (VOID *) (UINTN) Address;
+
+ return Status;
+}
+
+
+VOID
+EFIAPI
+AcpiEndOfDxeEvent (
+ EFI_EVENT Event,
+ VOID *ParentImageHandle
+ )
+{
+
+ if (Event != NULL) {
+ gBS->CloseEvent(Event);
+ }
+
+
+ //
+ // Install xHCI SSDT ACPI Table
+ //
+ InstallXhciAcpiTable ();
+
+ //
+ // Install Soc Gpe SSDT ACPI Table
+ //
+ InstallSocAcpiTable (&gSocGpeSsdtAcpiTableStorageGuid, SIGNATURE_64 ('S', 'o', 'c', 'G', 'p', 'e', ' ', 0));
+
+ //
+ // Install Soc Common SSDT ACPI Table
+ //
+ InstallSocAcpiTable (&gSocCmnSsdtAcpiTableStorageGuid, SIGNATURE_64 ('S', 'o', 'c', 'C', 'm', 'n', ' ', 0));
+
+ //
+ // Calculate Hardware Signature value based on current platform configurations
+ //
+ IsHardwareChange();
+
+}
+
+/**
+ Convert string containing GUID in the canonical form:
+ "aabbccdd-eeff-gghh-iijj-kkllmmnnoopp"
+ where aa - pp are unicode hexadecimal digits
+ to the buffer format to be used in ACPI, byte ordering:
+ [Byte 0] gg, hh, ee, ff, aa, bb, cc, dd [Byte 7]
+ [Byte 8] pp, oo, nn, mm, ll, kk, jj, ii [Byte 16]
+
+ @param[in] GuidString - GUID String null terminated (aligned on a 16-bit boundary)
+ @param[out] AcpiGuidPart1 - First half of buffer (bytes 0 - 7)
+ @param[out] AcpiGuidPart2 - Second half of buffer (bytes 8 - 16)
+
+ @retval EFI_SUCCESS - String converted successfully.
+ @retval EFI_UNSUPPORTED - Wrong input string format.
+
+**/
+EFI_STATUS
+GuidStringToAcpiBuffer (
+ IN CHAR16 *GuidString,
+ OUT UINT64 *AcpiGuidPart1,
+ OUT UINT64 *AcpiGuidPart2
+ )
+{
+ UINT32 GuidTempPart32 = 0;
+ UINT16 GuidTempPart16 = 0;
+ UINT8 GuidPartIndex;
+
+ DEBUG((DEBUG_INFO,"GuidStringToAcpiBuffer() - GUID = %s\n", GuidString));
+
+ for (GuidPartIndex = 0; GuidPartIndex < 4; GuidPartIndex++) {
+ switch (GuidPartIndex){
+ case 0:
+ GuidTempPart32 = SwapBytes32((UINT32)StrHexToUint64(GuidString));
+ *AcpiGuidPart1 = ((UINT64)GuidTempPart32 << 0x20);
+ break;
+ case 1:
+ GuidTempPart16 = SwapBytes16((UINT16)StrHexToUint64(GuidString));
+ *AcpiGuidPart1 += ((UINT64)GuidTempPart16 << 0x10);
+ break;
+ case 2:
+ GuidTempPart16 = SwapBytes16((UINT16)StrHexToUint64(GuidString));
+ *AcpiGuidPart1 += ((UINT64)GuidTempPart16);
+ break;
+ case 3:
+ GuidTempPart16 = (UINT16)StrHexToUint64(GuidString);
+ break;
+ default:
+ return EFI_UNSUPPORTED;
+ }
+
+ while ((*GuidString != L'-') && (*GuidString != L'\0')) {
+ GuidString++;
+ }
+
+ if (*GuidString == L'-') {
+ GuidString++;
+ } else {
+ return EFI_UNSUPPORTED;
+ }
+ }
+
+ *AcpiGuidPart2 = ((UINT64)GuidTempPart16 << 0x30) + StrHexToUint64(GuidString);
+
+ // Switch endianess because it will be swapped again in ACPI Buffer object
+ *AcpiGuidPart1 = SwapBytes64(*AcpiGuidPart1);
+ *AcpiGuidPart2 = SwapBytes64(*AcpiGuidPart2);
+
+ return EFI_SUCCESS;
+}
+
+
+/**
+ ACPI Platform driver installation function.
+
+ @param[in] ImageHandle Handle for this drivers loaded image protocol.
+ @param[in] SystemTable EFI system table.
+
+ @retval EFI_SUCCESS The driver installed without error.
+ @retval EFI_ABORTED The driver encountered an error and could not complete installation of
+ the ACPI tables.
+
+**/
+EFI_STATUS
+EFIAPI
+InstallAcpiPlatform (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUS Status;
+ EFI_HANDLE Handle;
+ CPUID_VERSION_INFO_EAX CpuidVersionInfoEax;
+ EFI_MP_SERVICES_PROTOCOL *MpService;
+ EFI_EVENT EndOfDxeEvent;
+
+
+
+ Handle = NULL;
+ mCpuApicIdOrderTable = NULL;
+ mCpuApicIdReorderTable = NULL;
+
+ AsmCpuid (
+ CPUID_VERSION_INFO,
+ &CpuidVersionInfoEax.Uint32,
+ NULL,
+ NULL,
+ NULL
+ );
+
+ //
+ // Locate the MP services protocol
+ // Find the MP Protocol. This is an MP platform, so MP protocol must be there.
+ //
+ Status = gBS->LocateProtocol (
+ &gEfiMpServiceProtocolGuid,
+ NULL,
+ (VOID **) &MpService
+ );
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ //
+ // Determine the number of processors
+ //
+ MpService->GetNumberOfProcessors (
+ MpService,
+ &mNumberOfCpus,
+ &mNumberOfEnabledCpus
+ );
+
+ DEBUG ((DEBUG_INFO, "mNumberOfCpus - %x,mNumberOfEnabledCpus - %x\n", mNumberOfCpus, mNumberOfEnabledCpus));
+ mCpuApicIdOrderTable = AllocateZeroPool (mNumberOfCpus * sizeof (EFI_CPU_ID_ORDER_MAP));
+ if (mCpuApicIdOrderTable == NULL) {
+ return EFI_UNSUPPORTED;
+ }
+ mCpuApicIdReorderTable = AllocateZeroPool (mNumberOfCpus * sizeof (EFI_CPU_APIC_ID_REORDER_MAP));
+ if (mCpuApicIdReorderTable == NULL) {
+ return EFI_UNSUPPORTED;
+ }
+
+ //
+ // Allocate and initialize the NVS area for SMM and ASL communication.
+ //
+ AcpiGnvsInit((VOID **) &mPlatformNvsAreaProtocol.Area);
+
+ //
+ // Create an End of DXE event.
+ //
+ Status = gBS->CreateEventEx (
+ EVT_NOTIFY_SIGNAL,
+ TPL_CALLBACK,
+ AcpiEndOfDxeEvent,
+ NULL,
+ &gEfiEndOfDxeEventGroupGuid,
+ &EndOfDxeEvent
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ Status = gBS->InstallMultipleProtocolInterfaces (
+ &Handle,
+ &gPlatformNvsAreaProtocolGuid,
+ &mPlatformNvsAreaProtocol,
+ NULL
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Allocate NVS area for VBIOS. This is not currently used.
+ //
+ Status = AllocateMemoryBelow4G (
+ EfiACPIMemoryNVS,
+ 0x10000,
+ &mGfxNvsAddress
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Generate ACPI tables from configuration data
+ //
+ Status = GenerateSsdtFromConfigFile();
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Platform ACPI Tables
+ //
+ PublishAcpiTablesFromFv(gAcpiTableStorageGuid);
+
+ //
+ // Reference Code ACPI Tables
+ //
+ PublishAcpiTablesFromFv(gRcAcpiTableStorageGuid);
+
+
+ //
+ // Finished
+ //
+ return EFI_SUCCESS;
+}
+
+/**
+ Sort ordering of CPUs according to the priorities of cores and threads.
+ ** ASSUMPTION: 1) single CPU package systsem wide; 2) two threads per core
+
+ @param[in] MpService The MP servicde protocol (used to retrievel MP info)
+
+ @retval EFI_SUCCESS The driver installed without error.
+
+**/
+EFI_STATUS
+SortCpuLocalApicInTable (
+ IN EFI_MP_SERVICES_PROTOCOL *MpService
+ )
+{
+ EFI_PROCESSOR_INFORMATION *MpContext;
+ UINT8 Index;
+ UINTN BspIndex;
+ UINT8 CurrProcessor;
+ EFI_STATUS Status;
+ UINT8 MaxCpuCore;
+ UINT8 MaxCpuThread;
+
+ MpContext = NULL;
+ MaxCpuCore = 0;
+ MaxCpuThread = 0;
+
+ Status = MpService->WhoAmI (
+ MpService,
+ &BspIndex
+ );
+
+ //
+ // Fill mCpuApicIdOrderTable
+ //
+ for (CurrProcessor = 0; CurrProcessor < mNumberOfCpus; CurrProcessor++) {
+
+ MpContext = AllocatePool (sizeof(EFI_PROCESSOR_INFORMATION));
+ ASSERT (MpContext != NULL);
+ Status = MpService->GetProcessorInfo (
+ MpService,
+ CurrProcessor,
+ MpContext
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ if (MpContext == NULL) {
+ return Status;
+ }
+ mCpuApicIdOrderTable[CurrProcessor].ApicId = (UINT32) MpContext->ProcessorId;
+ DEBUG((DEBUG_INFO, "The CurrProcessor 0x%x ApicId is 0x%x\n", CurrProcessor, mCpuApicIdOrderTable[CurrProcessor].ApicId));
+ mCpuApicIdOrderTable[CurrProcessor].Flags = (MpContext->StatusFlag & PROCESSOR_ENABLED_BIT)? 1: 0;
+ mCpuApicIdOrderTable[CurrProcessor].Package = (UINT8) MpContext->Location.Package;
+ mCpuApicIdOrderTable[CurrProcessor].Die = (UINT8) 0;
+ mCpuApicIdOrderTable[CurrProcessor].Core = (UINT8) MpContext->Location.Core;
+ mCpuApicIdOrderTable[CurrProcessor].Thread = (UINT8) MpContext->Location.Thread;
+
+ if (MaxCpuThread < (UINT8) MpContext->Location.Thread) {
+ MaxCpuThread = (UINT8) MpContext->Location.Thread;
+ }
+
+ if (MaxCpuCore < (UINT8) MpContext->Location.Core) {
+ MaxCpuCore = (UINT8) MpContext->Location.Core;
+ }
+ }
+
+ //
+ // Do some statistics about the SBSP package
+ //
+ for (CurrProcessor = 0; CurrProcessor < mNumberOfCpus; CurrProcessor++) {
+ if (CurrProcessor == BspIndex) {
+ mSbspPackageInfo.BspApicId = mCpuApicIdOrderTable[CurrProcessor].ApicId;
+ mSbspPackageInfo.PackageNo = mCpuApicIdOrderTable[CurrProcessor].Package;
+ mSbspPackageInfo.TotalThreads = 0;
+ mSbspPackageInfo.CoreNo = 0;
+ mSbspPackageInfo.LogicalThreadNo = 0;
+ }
+ }
+
+ for (CurrProcessor = 0; CurrProcessor < mNumberOfCpus; CurrProcessor++) {
+ if (mCpuApicIdOrderTable[CurrProcessor].Package == mSbspPackageInfo.PackageNo) {
+ mSbspPackageInfo.TotalThreads++;
+ if (mCpuApicIdOrderTable[CurrProcessor].Thread == 0) {
+ mSbspPackageInfo.CoreNo++;
+ } else {
+ mSbspPackageInfo.LogicalThreadNo++;
+ }
+ }
+ }
+
+ //
+ // Output debug info
+ //
+ for (Index = 0; Index < mNumberOfCpus; Index++) {
+ DEBUG((DEBUG_INFO, "Package = %x, Die = %x, Core = %x, Thread = %x, ApicId = %x\n", \
+ mCpuApicIdOrderTable[Index].Package, \
+ mCpuApicIdOrderTable[Index].Die, \
+ mCpuApicIdOrderTable[Index].Core, \
+ mCpuApicIdOrderTable[Index].Thread, \
+ mCpuApicIdOrderTable[Index].ApicId));
+ }
+
+ DEBUG((DEBUG_INFO, "MaxCpuCore = %x\n", MaxCpuCore));
+ DEBUG((DEBUG_INFO, "MaxCpuThread = %x\n\n", MaxCpuThread));
+ DEBUG((DEBUG_INFO, "mSbspPackageInfo.BspApicId = %x\n", mSbspPackageInfo.BspApicId));
+ DEBUG((DEBUG_INFO, "mSbspPackageInfo.TotalThreads = %x\n", mSbspPackageInfo.TotalThreads));
+ DEBUG((DEBUG_INFO, "mSbspPackageInfo.PackageNo = %x\n", mSbspPackageInfo.PackageNo));
+ DEBUG((DEBUG_INFO, "mSbspPackageInfo.CoreNo = %x\n", mSbspPackageInfo.CoreNo));
+ DEBUG((DEBUG_INFO, "mSbspPackageInfo.LogicalThreadNo = %x\n", mSbspPackageInfo.LogicalThreadNo));
+
+ //
+ // First entry is always SBSP
+ //
+ CurrProcessor = 0;
+ mCpuApicIdReorderTable[CurrProcessor].ApicId = mSbspPackageInfo.BspApicId;
+ mCpuApicIdReorderTable[CurrProcessor].Package = mSbspPackageInfo.PackageNo;
+ mCpuApicIdReorderTable[CurrProcessor].Flags = 1;
+ CurrProcessor++;
+
+ //
+ // Output debug info
+ //
+ for (Index = 0; Index < mNumberOfCpus; Index++) {
+ DEBUG((DEBUG_INFO, "Index = %x, ApicId = %x, Package = %x\n", \
+ Index, \
+ mCpuApicIdOrderTable[Index].ApicId, \
+ mCpuApicIdOrderTable[Index].Package));
+ }
+
+ FreePool (MpContext);
+
+ return EFI_SUCCESS;
+}
+
+
+EFI_STATUS
+AppendCpuMapTableEntry (
+ IN EFI_ACPI_1_0_PROCESSOR_LOCAL_APIC_STRUCTURE *AcpiLocalApic,
+ IN UINT32 LocalApicCounter
+ )
+{
+ EFI_STATUS Status = EFI_SUCCESS;
+ EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC_STRUCTURE *LocalX2ApicPtr;
+
+ if (AcpiLocalApic->Type == EFI_ACPI_1_0_PROCESSOR_LOCAL_APIC) {
+ if (LocalApicCounter < mNumberOfCpus) {
+ AcpiLocalApic->Flags = (UINT8)mCpuApicIdOrderTable[LocalApicCounter].Flags;
+ AcpiLocalApic->ApicId = (UINT8)mCpuApicIdOrderTable[LocalApicCounter].ApicId;
+ //
+ // Make AcpiProcessorIds 0-based
+ //
+ AcpiLocalApic->AcpiProcessorId = (UINT8)LocalApicCounter;
+ } else {
+ AcpiLocalApic->Flags = 0;
+ AcpiLocalApic->ApicId = 0xFF;
+ //
+ // Make AcpiProcessorIds 0-based
+ //
+ AcpiLocalApic->AcpiProcessorId = (UINT8)LocalApicCounter;
+ Status = EFI_UNSUPPORTED;
+ }
+
+ //
+ // Display the results
+ //
+ DEBUG((DEBUG_INFO, "AcpiLocalApic: AcpiProcessorId=%x, ApicId=%x, Flags=%x\n", \
+ AcpiLocalApic->AcpiProcessorId, \
+ AcpiLocalApic->ApicId, \
+ AcpiLocalApic->Flags));
+ } else if (AcpiLocalApic->Type == EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC) {
+ LocalX2ApicPtr = (EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC_STRUCTURE *)AcpiLocalApic;
+ if (LocalApicCounter < mNumberOfCpus) {
+ LocalX2ApicPtr->Flags = (UINT8)mCpuApicIdOrderTable[LocalApicCounter].Flags;
+ LocalX2ApicPtr->X2ApicId = mCpuApicIdOrderTable[LocalApicCounter].ApicId;
+ LocalX2ApicPtr->AcpiProcessorUid = LocalApicCounter;
+ } else {
+ LocalX2ApicPtr->Flags = 0;
+ LocalX2ApicPtr->X2ApicId = (UINT32)-1;
+ LocalX2ApicPtr->AcpiProcessorUid = LocalApicCounter;
+ Status = EFI_UNSUPPORTED;
+ }
+ //
+ // Display the results
+ //
+ DEBUG((DEBUG_INFO, "AcpiLocalx2Apic: AcpiProcessorId=%x, ApicId=%x, Flags=%x\n", \
+ LocalX2ApicPtr->AcpiProcessorUid, \
+ LocalX2ApicPtr->X2ApicId, \
+ LocalX2ApicPtr->Flags));
+ } else {
+ Status = EFI_UNSUPPORTED;
+ }
+ return Status;
+}
+
+/**
+ I/O work flow to wait input buffer empty in given time.
+
+ @param[in] Timeout Wating time.
+
+ @retval EFI_TIMEOUT if input is still not empty in given time.
+ @retval EFI_SUCCESS input is empty.
+**/
+EFI_STATUS
+WaitInputEmpty (
+ IN UINTN Timeout
+ )
+{
+ UINTN Delay;
+ UINT8 Data;
+
+ Delay = Timeout / 50;
+
+ do {
+ Data = IoRead8 (KBC_CMD_STS_PORT);
+
+ //
+ // Check keyboard controller status bit 0 and 1 (Output Buffer and Input Buffer status)
+ //
+ if ((Data & KBC_OUTB) != 0) {
+ IoRead8 (KBC_DATA_PORT);
+ } else if ((Data & KBC_INPB) == 0) {
+ break;
+ }
+
+ gBS->Stall (50);
+ Delay--;
+ } while (Delay != 0);
+
+ if (Delay == 0) {
+ return EFI_TIMEOUT;
+ }
+
+ return EFI_SUCCESS;
+}
+
+/**
+ I/O work flow to wait output buffer full in given time.
+
+ @param[in] Timeout given time
+
+ @retval EFI_TIMEOUT output is not full in given time
+ @retval EFI_SUCCESS output is full in given time.
+**/
+EFI_STATUS
+WaitOutputFull (
+ IN UINTN Timeout
+ )
+{
+ UINTN Delay;
+ UINT8 Data;
+
+ Delay = Timeout / 50;
+
+ do {
+ Data = IoRead8 (KBC_CMD_STS_PORT);
+
+ //
+ // Check keyboard controller status bit 0(output buffer status)
+ // & bit5(output buffer for auxiliary device)
+ //
+ if ((Data & (KBC_OUTB | KBC_AUXB)) == (KBC_OUTB | KBC_AUXB)) {
+ break;
+ }
+
+ gBS->Stall (50);
+ Delay--;
+ } while (Delay != 0);
+
+ if (Delay == 0) {
+ return EFI_TIMEOUT;
+ }
+
+ return EFI_SUCCESS;
+}
+
+/**
+ I/O work flow of in 8042 Aux data.
+
+ @param Data Buffer holding return value.
+
+ @retval EFI_SUCCESS Success to excute I/O work flow
+ @retval EFI_TIMEOUT Keyboard controller time out.
+**/
+EFI_STATUS
+In8042AuxData (
+ IN OUT UINT8 *Data
+ )
+{
+ EFI_STATUS Status;
+
+ //
+ // wait for output data
+ //
+ Status = WaitOutputFull (BAT_TIMEOUT);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ *Data = IoRead8 (KBC_DATA_PORT);
+
+ return EFI_SUCCESS;
+}
+
+/**
+ I/O work flow of outing 8042 Aux command.
+
+ @param Command Aux I/O command
+
+ @retval EFI_SUCCESS Success to excute I/O work flow
+ @retval EFI_TIMEOUT Keyboard controller time out.
+**/
+EFI_STATUS
+Out8042AuxCommand (
+ IN UINT8 Command
+ )
+{
+ EFI_STATUS Status;
+ UINT8 Data;
+
+ //
+ // Wait keyboard controller input buffer empty
+ //
+ Status = WaitInputEmpty (TIMEOUT);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+ //
+ // Send write to auxiliary device command
+ //
+ Data = WRITE_AUX_DEV;
+ IoWrite8 (KBC_CMD_STS_PORT, Data);
+
+ Status = WaitInputEmpty (TIMEOUT);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+ //
+ // Send auxiliary device command
+ //
+ IoWrite8 (KBC_DATA_PORT, Command);
+
+ //
+ // Read return code
+ //
+ Status = In8042AuxData (&Data);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ if (Data == PS2_ACK) {
+ //
+ // Receive mouse acknowledge, command send success
+ //
+ return EFI_SUCCESS;
+
+ } else if (Data == PS2_RESEND) {
+ //
+ // Resend command
+ //
+ Status = Out8042AuxCommand (Command);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ } else {
+ //
+ // Invalid return code
+ //
+ return EFI_DEVICE_ERROR;
+
+ }
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Issue command to enable Ps2 mouse.
+
+ @return Status of command issuing.
+**/
+EFI_STATUS
+PS2MouseEnable (
+ VOID
+ )
+{
+ //
+ // Send auxiliary command to enable mouse
+ //
+ return Out8042AuxCommand (ENABLE_CMD);
+}
+
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AdvancedAcpiDxe/AcpiPlatform.h b/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AdvancedAcpiDxe/AcpiPlatform.h
new file mode 100644
index 0000000000..11b21cd675
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AdvancedAcpiDxe/AcpiPlatform.h
@@ -0,0 +1,142 @@
+/** @file
+ This is an implementation of the Advanced ACPI driver.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _ACPI_PLATFORM_H_
+#define _ACPI_PLATFORM_H_
+
+//
+// Statements that include other header files
+//
+
+#include <IndustryStandard/Acpi.h>
+#include <Guid/EventGroup.h>
+#include <Guid/GlobalVariable.h>
+#include <Library/UefiLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/UefiRuntimeServicesTableLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/IoLib.h>
+#include <Library/PcdLib.h>
+#include <Library/LocalApicLib.h>
+#include <Protocol/CpuIo2.h>
+#include <Protocol/AcpiTable.h>
+#include <Protocol/PciRootBridgeIo.h>
+#include <Protocol/MpService.h>
+#include <Register/Cpuid.h>
+#include <Protocol/PciIo.h>
+#include <Library/PchCycleDecodingLib.h>
+
+#include <IndustryStandard/HighPrecisionEventTimerTable.h>
+#include <Library/DxeAcpiGnvsInitLib.h>
+
+#include <Register/PchRegs.h>
+
+//
+// Produced protocols
+//
+#include <Protocol/PlatformNvsArea.h>
+
+#include <Platform.h>
+#include <Library/AslUpdateLib.h>
+
+#include <Acpi/AcpiTables/Fadt/Fadt6.3.h>
+
+//
+// ACPI table information used to initialize tables.
+//
+
+#define NAT_CONFIG_INDEX 0x2E
+#define NAT_CONFIG_DATA 0x2F
+#define WPCN381U_CONFIG_INDEX 0x2E
+#define WPCN381U_CONFIG_DATA 0x2F
+#define WPCN381U_CHIP_ID 0xF4
+#define WDCP376_CHIP_ID 0xF1
+
+#define KBC_DATA_PORT 0x60
+#define KBC_CMD_STS_PORT 0x64
+
+#define ENABLE_CMD 0xf4
+#define WRITE_AUX_DEV 0xd4
+
+#define PS2_ACK 0xfa
+#define PS2_RESEND 0xfe
+
+#define KBC_INPB 0x02
+#define KBC_OUTB 0x01
+#define KBC_AUXB 0x20
+
+#define TIMEOUT 50000
+#define BAT_TIMEOUT 5000
+
+#define IO_EXPANDER_DISABLED 0xFF
+
+typedef struct {
+ UINT32 ApicId;
+ UINT32 Flags;
+ UINT8 Package;
+ UINT8 Die;
+ UINT8 Core;
+ UINT8 Thread;
+} EFI_CPU_ID_ORDER_MAP;
+
+typedef struct {
+ UINT8 Package;
+ UINT32 ApicId;
+ UINT32 Flags;
+} EFI_CPU_APIC_ID_REORDER_MAP;
+
+typedef struct {
+ UINT32 BspApicId;
+ UINT8 TotalThreads;
+ UINT8 PackageNo;
+ UINT8 CoreNo;
+ UINT8 LogicalThreadNo;
+} EFI_CPU_PACKAGE_INFO;
+
+//
+// Function definitions
+//
+EFI_STATUS
+LocateSupportProtocol (
+ IN EFI_GUID *Protocol,
+ IN EFI_GUID gEfiAcpiMultiTableStorageGuid,
+ OUT VOID **Instance,
+ IN BOOLEAN Type
+ );
+
+/**
+ Entry point of the ACPI platform driver.
+
+ @param[in] ImageHandle A handle for the image that is initializing this driver
+ @param[in] SystemTable A pointer to the EFI system table
+
+ @retval EFI_SUCCESS The driver installed without error.
+ @retval EFI_ABORTED The driver encountered an error and could not complete
+ installation of the ACPI tables.
+**/
+EFI_STATUS
+EFIAPI
+InstallAcpiPlatform (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ );
+
+EFI_STATUS
+SortCpuLocalApicInTable (
+ IN EFI_MP_SERVICES_PROTOCOL *MpService
+ );
+
+EFI_STATUS
+AppendCpuMapTableEntry (
+ IN EFI_ACPI_1_0_PROCESSOR_LOCAL_APIC_STRUCTURE *AcpiLocalApic,
+ IN UINT32 LocalApicCounter
+ );
+
+#endif
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AdvancedAcpiDxe/AdvancedAcpiDxe.inf b/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AdvancedAcpiDxe/AdvancedAcpiDxe.inf
new file mode 100644
index 0000000000..0e38852fbf
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AdvancedAcpiDxe/AdvancedAcpiDxe.inf
@@ -0,0 +1,154 @@
+### @file
+# Component information file for AdvancedAcpiDxe module
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+# @par Glossary:
+###
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = AdvancedAcpiDxe
+ FILE_GUID = C3E69EB2-0429-4BD6-AE4A-8CA02FBACC2E
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+ ENTRY_POINT = InstallAcpiPlatform
+
+[Sources.common]
+ AcpiPlatform.h
+ AcpiPlatform.c
+ GenSsdtLib.c
+ GenSsdtLib.h
+ AcpiByteStream.h
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ UefiCpuPkg/UefiCpuPkg.dec
+ AlderlakeSiliconPkg/SiPkg.dec
+ AlderlakeOpenBoardPkg/OpenBoardPkg.dec
+ IntelSiliconPkg/IntelSiliconPkg.dec
+
+[LibraryClasses]
+ UefiDriverEntryPoint
+ BaseLib
+ DebugLib
+ IoLib
+ PcdLib
+ AslUpdateLib
+ DxeAcpiGnvsInitLib
+ UefiBootServicesTableLib
+ UefiRuntimeServicesTableLib
+ BaseMemoryLib
+ MemoryAllocationLib
+ PchCycleDecodingLib
+ PchInfoLib
+ PchPcieRpLib
+ PciSegmentLib
+ HobLib
+ GpioLib
+ EspiLib
+ CpuPlatformLib
+ GraphicsInfoLib
+ PchPciBdfLib
+ LocalApicLib
+
+[Pcd]
+ gSiPkgTokenSpaceGuid.PcdPciExpressRegionLength ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdRealBattery1Control ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdRealBattery2Control ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdNCT6776FCOM ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdNCT6776FSIO ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdNCT6776FHWMON ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdH8S2113SIO ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdH8S2113UAR ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdSmcRuntimeSciPin ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdVirtualButtonVolumeUpSupport ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdVirtualButtonVolumeDownSupport ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdVirtualButtonHomeButtonSupport ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdVirtualButtonRotationLockSupport ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdSlateModeSwitchSupport ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdPmPowerButtonGpioPin ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdAcpiEnableAllButtonSupport ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdAcpiHidDriverButtonSupport ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdTsOnDimmTemperature ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdBatteryPresent ## CONSUMES
+ gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemTableId ## CONSUMES
+ gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemRevision
+ gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorId
+ gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorRevision
+ gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemId
+
+ # DXE PCD
+ gBoardModuleTokenSpaceGuid.PcdXhciAcpiTableSignature ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdPreferredPmProfile ## CONSUMES
+
+ gBoardModuleTokenSpaceGuid.PcdBoardRtd3TableSignature ## CONSUMES
+
+ gBoardModuleTokenSpaceGuid.PcdEnableVoltageMargining ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdPlatformGeneration ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdBoardId ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdBoardRev ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdBoardType ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdPlatformType ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdPlatformFlavor ## CONSUMES
+
+ gBoardModuleTokenSpaceGuid.PcdBoardUcmcGpio1 ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdBoardUcmcGpio2 ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdBoardUcmcGpio3 ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdBoardUcmcGpio4 ## CONSUMES
+
+ # Onboard MR 1 GPIO configuration PCDs
+ gBoardModuleTokenSpaceGuid.PcdOnBoardMr1PowerEnableGpioNo ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdOnBoardMr1PowerEnableGpioPolarity ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdOnBoardMr1WakeGpioPin ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdOnBoardMr1RootPort ## CONSUMES
+
+ # Onboard MR 2 GPIO configuration PCDs
+ gBoardModuleTokenSpaceGuid.PcdOnBoardMr2PowerEnableGpioNo ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdOnBoardMr2PowerEnableGpioPolarity ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdOnBoardMr2WakeGpioPin ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdOnBoardMr2RootPort ## CONSUMES
+
+ # PCH SATA port GPIO configuration PCDs
+ gBoardModuleTokenSpaceGuid.PcdPchSataPortPwrEnableGpioNo ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdPchSataPortPwrEnableGpioPolarity ## CONSUMES
+
+ # ACPI configuration file data
+ gBoardModuleTokenSpaceGuid.PcdBoardAcpiData ## CONSUMES
+
+[FixedPcd]
+ gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress
+ gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress
+ gSiPkgTokenSpaceGuid.PcdAdlLpSupport ## CONSUMES
+ gSiPkgTokenSpaceGuid.PcdAdlSSupport ## CONSUMES
+
+[Protocols]
+ gEfiAcpiTableProtocolGuid ## CONSUMES
+ gEfiFirmwareVolume2ProtocolGuid ## CONSUMES
+ gEfiPciRootBridgeIoProtocolGuid ## CONSUMES
+ gEfiMpServiceProtocolGuid ## CONSUMES
+ gEfiPciIoProtocolGuid ## CONSUMES
+ gIgdOpRegionProtocolGuid ## CONSUMES
+ gPchSerialIoUartDebugInfoProtocolGuid ## CONSUMES
+ gEfiCpuIo2ProtocolGuid ## CONSUMES
+ gEfiSimpleFileSystemProtocolGuid ## CONSUMES
+ gPlatformNvsAreaProtocolGuid ## PRODUCES
+
+[Guids]
+ gAcpiTableStorageGuid ## CONSUMES
+ gRcAcpiTableStorageGuid ## CONSUMES
+ gEfiHobListGuid ## CONSUMES
+ gEfiFileInfoGuid ## CONSUMES
+ gEfiEndOfDxeEventGroupGuid ## CONSUMES
+ gSocGpeSsdtAcpiTableStorageGuid ## CONSUMES
+ gSocCmnSsdtAcpiTableStorageGuid ## CONSUMES
+
+[Depex]
+ gEfiAcpiTableProtocolGuid AND
+ gEfiFirmwareVolume2ProtocolGuid AND
+ gEfiCpuIo2ProtocolGuid AND
+ gEfiMpServiceProtocolGuid AND
+ gEfiPciRootBridgeIoProtocolGuid
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AdvancedAcpiDxe/GenSsdtLib.c b/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AdvancedAcpiDxe/GenSsdtLib.c
new file mode 100644
index 0000000000..0234d06cc3
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AdvancedAcpiDxe/GenSsdtLib.c
@@ -0,0 +1,474 @@
+/** @file
+ ACPI SSDT table generation library
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "AcpiByteStream.h"
+#include <Base.h>
+#include <Uefi.h>
+#include <Library/BaseLib.h>
+#include <Library/HobLib.h>
+#include <Guid/HobList.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <IndustryStandard/Acpi.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Protocol/AcpiTable.h>
+#include <Protocol/AcpiSystemDescriptionTable.h>
+#include <Library/MemoryAllocationLib.h>
+
+GLOBAL_REMOVE_IF_UNREFERENCED UINT8 SsdtHeader [] = {
+ 0x53,0x53,0x44,0x54,0x08,0x01,0x00,0x00, /* 00000000 "SSDT...." */
+ 0x02,0x06,0x49,0x6E,0x74,0x65,0x6C,0x20, /* 00000008 "..Intel " */
+ 0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20, /* 00000010 " " */
+ 0x01,0x00,0x00,0x00,0x49,0x4E,0x54,0x4C, /* 00000018 "....INTL" */
+ 0x27,0x05,0x16,0x20, /* 00000020 "'.. " */
+ 0xA0,0x0F,0x00 /* 00000024 "..." */
+};
+
+GLOBAL_REMOVE_IF_UNREFERENCED UINT8 SsdtExternalDualName [] = {
+ 0x15,0x5C,0x2E,0x5F,0x53,0x42,0x5F,0x50, /* 00000000 ".\._SB_P" */
+ 0x43,0x49,0x58,0x06,0x00 /* 00000008 "CIX.." */
+};
+
+GLOBAL_REMOVE_IF_UNREFERENCED UINT8 SsdtScopePkgLengthEncoding [] = {
+ 0x10, 0x00, 0x00, 0x00, 0x00 /* 00000000 "....." */
+};
+
+GLOBAL_REMOVE_IF_UNREFERENCED UINT8 SsdtScopeDualName [] = {
+ 0x5C,0x2E,0x5F,0x53,0x42, /* 00000000 "\._SB" */
+ 0x5F,0x50,0x43,0x49,0x58 /* 00000008 "_PCIX" */
+};
+
+GLOBAL_REMOVE_IF_UNREFERENCED UINT8 SsdtDevicePkgLengthEncoding [] = {
+ 0x5B,0x82,0x00,0x00,0x00,0x00 /* 00000000 "......" */
+};
+
+GLOBAL_REMOVE_IF_UNREFERENCED UINT8 SsdtDeviceName [] = {
+ 0x54,0x4D,0x50,0x31 /* 00000000 "TMP1" */
+};
+
+GLOBAL_REMOVE_IF_UNREFERENCED UINT8 SsdtHardwareId [] = {
+ 0x08,0x5F,0x48,0x49,0x44,0x0D,0x49,0x4E, /* 00000000 "._HID.IN" */
+ 0x54,0x30,0x30,0x30,0x30,0x30,0x00 /* 00000008 "T0000." */
+};
+
+GLOBAL_REMOVE_IF_UNREFERENCED UINT8 SsdtCompatibleId [] = {
+ 0x08,0x5F,0x43,0x49,0x44,0x0D,0x49,0x4E, /* 00000000 "._CID.IN" */
+ 0x54,0x30,0x30,0x30,0x30,0x30,0x00 /* 00000008 "T0000." */
+};
+
+GLOBAL_REMOVE_IF_UNREFERENCED UINT8 SsdtUniqueId [] = {
+ 0x08,0x5F,0x55,0x49,0x44,0x00 /* 00000000 "._UID." */
+};
+
+GLOBAL_REMOVE_IF_UNREFERENCED UINT8 SsdtCurrentResourceSettings [] = {
+ 0x08,0x5F,0x43,0x52,0x53, /* 00000000 "._CRS" */
+};
+
+GLOBAL_REMOVE_IF_UNREFERENCED UINT8 SsdtBufferPkgLengthEncoding [] = {
+ 0x11,0x00,0x00
+};
+
+GLOBAL_REMOVE_IF_UNREFERENCED UINT8 SsdtCrsPkgLengthEncoding [] = {
+ 0x00,0x00, 0x00 /* 00000000 "....." */
+};
+
+GLOBAL_REMOVE_IF_UNREFERENCED UINT8 SsdtGpioResource [] = {
+ 0x8C,0x20,0x00,0x01,0x01,0x01,0x00,0x02, /* 00000000 ". ......" */
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x17,0x00, /* 00000008 "........" */
+ 0x00,0x19,0x00,0x23,0x00,0x00,0x00,0x03, /* 00000010 "...#...." */
+ 0x00,0x5C,0x5F,0x53,0x42,0x2E,0x47,0x50, /* 00000018 ".\_SB.GP" */
+ 0x49,0x30,0x00, /* 00000020 "I0." */
+};
+
+GLOBAL_REMOVE_IF_UNREFERENCED UINT8 SsdtI2cSerialBusResource [] = {
+ 0x8E,0x1E,0x00,0x01,0x00,0x01,0x02,0x00, /* 00000000 "........" */
+ 0x00,0x01,0x06,0x00,0x80,0x1A,0x06,0x00, /* 00000008 "........" */
+ 0x22,0x00,0x5C,0x5F,0x53,0x42,0x2E,0x50, /* 00000010 "".\_SB.P" */
+ 0x43,0x49,0x30,0x2E,0x49,0x32,0x43,0x58, /* 00000018 "CI0.I2CX" */
+ 0x00 /* 00000020 "." */
+};
+
+GLOBAL_REMOVE_IF_UNREFERENCED UINT8 SsdtStatusMethod [] = {
+ 0x14,0x09,0x5F,0x53,0x54,0x41,0x00, /* 00000000 ".._STA." */
+ 0xA4,0x0A,0x0F /* 00000008 "..." */
+};
+
+GLOBAL_REMOVE_IF_UNREFERENCED UINT8 SsdtResourceTemplateEndTag [] = {
+ 0x79, 0x00
+};
+
+EFI_STATUS
+GetTableSize(
+ IN UINT8 *AcpiDataBase,
+ OUT UINT32 *SsdtTableSize
+ )
+{
+ UINTN GpioResources;
+ UINTN I2cResources;
+ UINT32 ResourceBufferLength;
+ UINT32 DevicePackageLength;
+ UINT32 ScopePackageLength;
+ UINT32 ResourceSize;
+ UINTN i;
+ UINTN ResourceOffset;
+ UINT8 ResourceType;
+ UINTN NextResource;
+ EFI_ACPI_SDT_HEADER *SsdtTableInfo;
+ SSDT_DEVICE_DATA *SsdtDeviceInfo;
+ UINT32 Size;
+ UINT8 *PrintData;
+
+ //
+ // Get table info from HOB
+ //
+ SsdtTableInfo = (EFI_ACPI_SDT_HEADER *) AcpiDataBase;
+ SsdtDeviceInfo = (SSDT_DEVICE_DATA *) (AcpiDataBase + sizeof(EFI_ACPI_SDT_HEADER));
+ ResourceOffset = sizeof(EFI_ACPI_SDT_HEADER) + sizeof(SSDT_DEVICE_DATA) - sizeof(UINT8);
+ NextResource = 0;
+ GpioResources = 0;
+ I2cResources = 0;
+ ResourceSize = 0;
+
+ Size = SsdtTableInfo->Length;
+
+ DEBUG_CODE_BEGIN();
+ DEBUG((DEBUG_INFO, "GenSsdt AcpiData print:\n"));
+ for (PrintData = AcpiDataBase; PrintData<(AcpiDataBase + Size); PrintData++) {
+ DEBUG((DEBUG_INFO, "%x ", *PrintData));
+ }
+ DEBUG((DEBUG_INFO, "\n"));
+ DEBUG_CODE_END();
+
+ DEBUG((DEBUG_INFO, "NumberOfResources: %x \n", SsdtDeviceInfo->NumberOfResources));
+
+ for (i = 0; i < SsdtDeviceInfo->NumberOfResources; i++) {
+ ResourceType = *(AcpiDataBase + ResourceOffset + NextResource);
+ DEBUG((DEBUG_INFO, "ResourceType: %x ", ResourceType));
+ switch (ResourceType) {
+ case ACPI_GPIO_RESOURCE_TYPE :
+ {
+ ResourceSize = ResourceSize + sizeof(GPIO_RESOURCE_DATA);
+ NextResource = NextResource + sizeof(GPIO_RESOURCE_DATA) - sizeof(UINT8);
+ GpioResources++;
+ break;
+ }
+ case ACPI_I2C_RESOURCE_TYPE :
+ {
+ ResourceSize = ResourceSize + sizeof(I2C_RESOURCE_DATA);
+ NextResource = NextResource + sizeof(I2C_RESOURCE_DATA) - sizeof(UINT8);
+ I2cResources++;
+ break;
+ }
+ default :
+ DEBUG ((DEBUG_INFO, "Unsupported resource type.\n"));
+ break;
+ }
+ }
+ DEBUG((DEBUG_INFO, "GenSsdt GpioResources:%d I2cResources:%d\n", GpioResources, I2cResources));
+ //
+ // Calculate the size of table to be generated
+ //
+ ResourceBufferLength = (UINT32) ((GpioResources * sizeof(SsdtGpioResource)) +
+ (I2cResources * sizeof(SsdtI2cSerialBusResource)) +
+ sizeof(SsdtResourceTemplateEndTag));
+ DEBUG((DEBUG_INFO, "GenSsdt ResourceBufferLength: 0x%x\n", ResourceBufferLength));
+
+ DevicePackageLength = (UINT32) (sizeof(SsdtDeviceName) + sizeof(SsdtHardwareId) +
+ sizeof(SsdtCompatibleId) + sizeof(SsdtUniqueId) +
+ sizeof(SsdtCurrentResourceSettings) + ResourceBufferLength +
+ sizeof(SsdtStatusMethod));
+ DEBUG((DEBUG_INFO, "GenSsdt DevicePkgLength: 0x%x\n", DevicePackageLength));
+
+ if (ResourceBufferLength < 254) {
+ SsdtCrsPkgLengthEncoding[0] = ACPI_BYTE_PREFIX_OPCODE;
+ SsdtCrsPkgLengthEncoding[1] = (UINT8) ResourceBufferLength;
+ DevicePackageLength = DevicePackageLength + 2; //Adding Package length encoding size
+ DEBUG((DEBUG_INFO, "GenSsdt CrsPkgLengthEncoding1: 0x%x\n", SsdtCrsPkgLengthEncoding[1]));
+ } else if (ResourceBufferLength < 65533) {
+ SsdtCrsPkgLengthEncoding[0] = ACPI_WORD_PREFIX_OPCODE;
+ SsdtCrsPkgLengthEncoding[1] = (UINT8) (ResourceBufferLength & 0x00FF);
+ SsdtCrsPkgLengthEncoding[2] = (UINT8) ((ResourceBufferLength & 0xFF00) >> 8);
+ DevicePackageLength = DevicePackageLength + 3; //Adding Package length encoding size
+ DEBUG((DEBUG_INFO, "GenSsdt CrsPkgLengthEncoding1: 0x%x\n", SsdtCrsPkgLengthEncoding[1]));
+ DEBUG((DEBUG_INFO, "GenSsdt CrsPkgLengthEncoding2: 0x%x\n", SsdtCrsPkgLengthEncoding[2]));
+ }
+
+ if (ResourceBufferLength < 61) {
+ SsdtBufferPkgLengthEncoding[1] = (UINT8) ResourceBufferLength + 3; //Taking CrsPackageLength encoding into account
+ DevicePackageLength = DevicePackageLength + 2; //Adding Package length encoding size
+ DEBUG((DEBUG_INFO, "GenSsdt BufferPkgLengthEncoding1: 0x%x\n", SsdtBufferPkgLengthEncoding[1]));
+ } else if (ResourceBufferLength < 4095) {
+ SsdtBufferPkgLengthEncoding[1] = 0x40 | ((UINT8)((ResourceBufferLength + 5) & 0x00F)); //Taking CrsPackageLength encoding into account
+ SsdtBufferPkgLengthEncoding[2] = (UINT8) (((ResourceBufferLength + 5) & 0xFF0) >> 4); //Taking CrsPackageLength encoding into account
+ DevicePackageLength = DevicePackageLength + 3; //Adding Package length encoding size
+ DEBUG((DEBUG_INFO, "GenSsdt BufferPkgLengthEncoding1: 0x%x\n", SsdtBufferPkgLengthEncoding[1]));
+ DEBUG((DEBUG_INFO, "GenSsdt BufferPkgLengthEncoding2: 0x%x\n", SsdtBufferPkgLengthEncoding[2]));
+ }
+
+ ScopePackageLength = 0;
+ if (DevicePackageLength < 63) {
+ SsdtDevicePkgLengthEncoding[2] = (UINT8) DevicePackageLength;
+ ScopePackageLength = ScopePackageLength + 3;
+ DEBUG((DEBUG_INFO, "GenSsdt DevicePkgLengthEncoding2: 0x%x\n", SsdtDevicePkgLengthEncoding[2]));
+ } else if (DevicePackageLength < 4094) {
+ SsdtDevicePkgLengthEncoding[2] = 0x40 | ((UINT8)((DevicePackageLength + 2) & 0x00F));
+ SsdtDevicePkgLengthEncoding[3] = (UINT8) (((DevicePackageLength + 2) & 0xFF0) >> 4);
+ ScopePackageLength = ScopePackageLength + 4;
+ DEBUG((DEBUG_INFO, "GenSsdt DevicePkgLengthEncoding2: 0x%x\n", SsdtDevicePkgLengthEncoding[2]));
+ DEBUG((DEBUG_INFO, "GenSsdt DevicePkgLengthEncoding3: 0x%x\n", SsdtDevicePkgLengthEncoding[3]));
+ }
+
+ ScopePackageLength = ScopePackageLength + sizeof(SsdtScopeDualName) + DevicePackageLength;
+ if (ScopePackageLength < 63) {
+ SsdtScopePkgLengthEncoding[1] = (UINT8) ScopePackageLength;
+ DEBUG((DEBUG_INFO, "GenSsdt ScopePkgLengthEncoding1: 0x%x\n", SsdtScopePkgLengthEncoding[1]));
+ } else if (ScopePackageLength < 4094) {
+ ScopePackageLength = ScopePackageLength + 2;
+ SsdtScopePkgLengthEncoding[1] = 0x40 | ((UINT8)(ScopePackageLength & 0x00F));
+ SsdtScopePkgLengthEncoding[2] = (UINT8) ((ScopePackageLength & 0xFF0) >> 4);
+ DEBUG((DEBUG_INFO, "GenSsdt ScopePkgLengthEncoding1: 0x%x\n", SsdtScopePkgLengthEncoding[1]));
+ DEBUG((DEBUG_INFO, "GenSsdt ScopePkgLengthEncoding2: 0x%x\n", SsdtScopePkgLengthEncoding[2]));
+ }
+
+ *SsdtTableSize = (UINT32) (sizeof(SsdtHeader) + sizeof(SsdtExternalDualName) + ScopePackageLength + 1);
+
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+CreateAcpiTableInMemory (
+ IN UINT8 *AcpiDataBase,
+ IN UINT32 *SsdtTableSize,
+ OUT UINT8 *CurrentTable
+ )
+{
+ UINT8 *CurrentTablePointer;
+ EFI_ACPI_SDT_HEADER *AcpiTableHeader;
+ EFI_ACPI_SDT_HEADER *SsdtTableInfo;
+ SSDT_DEVICE_DATA *SsdtDeviceInfo;
+ GPIO_RESOURCE_DATA *GpioResourceInfo;
+ I2C_RESOURCE_DATA *I2cResourceInfo;
+ GPIO_RESOURCE *TempGpioResource;
+ I2C_SERIAL_BUS_RESOURCE *TempI2cResource;
+ UINTN i;
+ UINTN ResourceOffset;
+ UINT8 ResourceType;
+ UINTN NextResource;
+ UINT32 Size;
+
+ SsdtTableInfo = (EFI_ACPI_SDT_HEADER *) AcpiDataBase;
+ SsdtDeviceInfo = (SSDT_DEVICE_DATA *) (AcpiDataBase + sizeof(EFI_ACPI_SDT_HEADER));
+ ResourceOffset = sizeof(EFI_ACPI_SDT_HEADER) + sizeof(SSDT_DEVICE_DATA) - sizeof(UINT8);
+ //
+ // Copy SSDT content to allocated space
+ //
+ CurrentTablePointer = (UINT8 *) CurrentTable;
+ CopyMem(CurrentTablePointer, &SsdtHeader, sizeof(SsdtHeader));
+ AcpiTableHeader = (EFI_ACPI_SDT_HEADER *) CurrentTablePointer;
+ AcpiTableHeader->Length = *SsdtTableSize;
+ CopyMem(AcpiTableHeader->OemId, SsdtTableInfo->OemId, 6);
+ CopyMem(AcpiTableHeader->OemTableId, SsdtTableInfo->OemTableId, 8);
+
+ CurrentTablePointer = (UINT8 *) (CurrentTable + sizeof(SsdtHeader));
+ CopyMem(CurrentTablePointer, &SsdtExternalDualName, sizeof(SsdtExternalDualName));
+ *(CHAR8 *) (CurrentTablePointer + ACPI_EXTERNAL_PCI_BUS_NUMBER_OFFSET) = '0'; //PCI bus 0
+
+ CurrentTablePointer = (UINT8 *) (CurrentTablePointer + sizeof(SsdtExternalDualName));
+ Size = ((SsdtScopePkgLengthEncoding[1] & 0xC0) >> 6) + 2;
+ CopyMem(CurrentTablePointer, &SsdtScopePkgLengthEncoding, Size);
+
+ CurrentTablePointer = (UINT8 *) (CurrentTablePointer + Size);
+ CopyMem(CurrentTablePointer, &SsdtScopeDualName, sizeof(SsdtScopeDualName));
+ *(CHAR8 *) (CurrentTablePointer + ACPI_SCOPE_PCI_BUS_NUMBER_OFFSET) = '0'; //PCI bus 0
+
+ CurrentTablePointer = (UINT8 *) (CurrentTablePointer + sizeof(SsdtScopeDualName));
+ Size = ((SsdtDevicePkgLengthEncoding[2] & 0xC0) >> 6) + 3;
+ CopyMem(CurrentTablePointer, &SsdtDevicePkgLengthEncoding, Size);
+
+ CurrentTablePointer = (UINT8 *) (CurrentTablePointer + Size);
+ CopyMem(&SsdtDeviceName, SsdtDeviceInfo->DeviceName, 4);
+ CopyMem(CurrentTablePointer, &SsdtDeviceName, sizeof(SsdtDeviceName));
+
+ CurrentTablePointer = (UINT8 *) (CurrentTablePointer + sizeof(SsdtDeviceName));
+ CopyMem(CurrentTablePointer, &SsdtHardwareId, sizeof(SsdtHardwareId));
+ CopyMem(CurrentTablePointer + ACPI_NAME_OBJECT_STRING_OFFSET, SsdtDeviceInfo->HardwareId, 8);
+
+ CurrentTablePointer = (UINT8 *) (CurrentTablePointer + sizeof(SsdtHardwareId));
+ CopyMem(CurrentTablePointer, &SsdtCompatibleId, sizeof(SsdtCompatibleId));
+ CopyMem(CurrentTablePointer + ACPI_NAME_OBJECT_STRING_OFFSET, SsdtDeviceInfo->CompatibilityId, 8);
+
+ CurrentTablePointer = (UINT8 *) (CurrentTablePointer + sizeof(SsdtCompatibleId));
+ SsdtUniqueId[ACPI_UNIQUE_ID_NUMBER_OFFSET] = (UINT8) SsdtDeviceInfo->UniqueId;
+ CopyMem(CurrentTablePointer, &SsdtUniqueId, sizeof(SsdtUniqueId));
+
+ CurrentTablePointer = (UINT8 *) (CurrentTablePointer + sizeof(SsdtUniqueId));
+ CopyMem(CurrentTablePointer, &SsdtCurrentResourceSettings, sizeof(SsdtCurrentResourceSettings));
+
+ CurrentTablePointer = (UINT8 *) (CurrentTablePointer + sizeof(SsdtCurrentResourceSettings));
+ Size = ((SsdtBufferPkgLengthEncoding[1] & 0xC0) >> 6) + 2;
+ CopyMem(CurrentTablePointer, &SsdtBufferPkgLengthEncoding, Size);
+
+ CurrentTablePointer = (UINT8 *) (CurrentTablePointer + Size);
+ if (SsdtCrsPkgLengthEncoding[0] == ACPI_BYTE_PREFIX_OPCODE) {
+ Size = 2;
+ } else if (SsdtCrsPkgLengthEncoding[0] == ACPI_WORD_PREFIX_OPCODE) {
+ Size = 3;
+ }
+ CopyMem(CurrentTablePointer, &SsdtCrsPkgLengthEncoding, Size);
+
+ CurrentTablePointer = (UINT8 *) (CurrentTablePointer + Size);
+ NextResource = 0;
+ for (i = 0; i < SsdtDeviceInfo->NumberOfResources; i++) {
+ ResourceType = *(UINT8 *)(AcpiDataBase + ResourceOffset + NextResource);
+ switch (ResourceType) {
+ case ACPI_GPIO_RESOURCE_TYPE :
+ {
+ CopyMem(CurrentTablePointer, &SsdtGpioResource, sizeof(SsdtGpioResource));
+ TempGpioResource = (GPIO_RESOURCE *) CurrentTablePointer;
+ DEBUG((DEBUG_INFO, "TempGpioConnDesc: %x\n", TempGpioResource->GpioConnectionDescriptor));
+ DEBUG((DEBUG_INFO, "TempGpioResourceNumber1 before: %x\n", TempGpioResource->PinNumber1));
+ DEBUG((DEBUG_INFO, "TempGpioResourceNumber2 before: %x\n", TempGpioResource->PinNumber2));
+ GpioResourceInfo = (GPIO_RESOURCE_DATA *) (AcpiDataBase + ResourceOffset + NextResource);
+ if (GpioResourceInfo->GpioResourceType == ACPI_GPIO_RESOURCE_TYPE_INTERRUPT) {
+ TempGpioResource->GpioConnectionType = GpioInterrupt;
+ TempGpioResource->InterruptAndIoFlags1 |= 0x10;
+ TempGpioResource->PinNumber1 = GpioResourceInfo->GpioNumber & 0x00FF;
+ TempGpioResource->PinNumber2 = (GpioResourceInfo->GpioNumber & 0xFF00) >> 8;
+ } else if (GpioResourceInfo->GpioResourceType == ACPI_GPIO_RESOURCE_TYPE_IO) {
+ TempGpioResource->GpioConnectionType = GpioIo;
+ TempGpioResource->InterruptAndIoFlags1 &= 0x0F;
+ TempGpioResource->PinNumber1 = GpioResourceInfo->GpioNumber & 0x00FF;
+ TempGpioResource->PinNumber2 = (GpioResourceInfo->GpioNumber & 0xFF00) >> 8;
+ }
+ DEBUG((DEBUG_INFO, "TempGpioResourceNumber1 after: %x\n", TempGpioResource->PinNumber1));
+ DEBUG((DEBUG_INFO, "TempGpioResourceNumber2 after: %x\n", TempGpioResource->PinNumber2));
+ NextResource = NextResource + sizeof(GPIO_RESOURCE_DATA) - sizeof(UINT8);
+ CurrentTablePointer = CurrentTablePointer + sizeof(SsdtGpioResource);
+
+ break;
+ }
+ case ACPI_I2C_RESOURCE_TYPE :
+ {
+ CopyMem(CurrentTablePointer, &SsdtI2cSerialBusResource, sizeof(SsdtI2cSerialBusResource));
+ TempI2cResource = (I2C_SERIAL_BUS_RESOURCE *) CurrentTablePointer;
+ I2cResourceInfo = (I2C_RESOURCE_DATA *) (AcpiDataBase + ResourceOffset + NextResource);
+ TempI2cResource->SlaveAddress = (UINT16) I2cResourceInfo->I2cSlaveAddress;
+ TempI2cResource->ConnectionSpeed = I2cResourceInfo->ConnectionSpeed;
+ *(CurrentTablePointer + ACPI_I2C_RESOURCE_CONTROLLER_NUMBER_OFFSET) = I2cResourceInfo->I2cSliceNumber + ASCII_0_ORDINAL;
+ NextResource = NextResource + sizeof(I2C_RESOURCE_DATA) - sizeof(UINT8);
+ CurrentTablePointer = CurrentTablePointer + sizeof(SsdtI2cSerialBusResource);
+
+ break;
+ }
+ }
+ }
+ CopyMem(CurrentTablePointer, &SsdtResourceTemplateEndTag, sizeof(SsdtResourceTemplateEndTag));
+ CurrentTablePointer = CurrentTablePointer + sizeof(SsdtResourceTemplateEndTag);
+ if (SsdtDeviceInfo->EnableStatus == TRUE) {
+ SsdtStatusMethod[ACPI_STA_RETURN_VALUE_OFFSET] = ACPI_STA_RETURN_VALUE_DEVICE_ENABLED;
+ } else {
+ SsdtStatusMethod[ACPI_STA_RETURN_VALUE_OFFSET] = ACPI_STA_RETURN_VALUE_DEVICE_DISABLED;
+ }
+ CopyMem(CurrentTablePointer, &SsdtStatusMethod, sizeof(SsdtStatusMethod));
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Generate SSDTs from ACPI data available in BIOS board files
+ or ACPI data generated from PCT tool FVs
+**/
+EFI_STATUS
+GenerateSsdtFromConfigFile (
+ VOID
+)
+{
+ EFI_STATUS Status = EFI_SUCCESS;
+ UINTN Pages;
+ UINT8 *CurrentTable;
+ EFI_ACPI_TABLE_PROTOCOL *AcpiTable;
+ EFI_ACPI_SDT_HEADER *AcpiTableHeader;
+ UINT32 SsdtTableSize;
+ UINT8 *PctAcpiDataBase;
+ UINTN i,j;
+ UINT8 *PrintData;
+ UINTN TableHandle;
+ PCT_ACPI_BLOCK_HDR *PctAcpiDataHeader;
+ UINT16 TableCount;
+ UINT8 *AcpiDataPointer;
+
+ DEBUG((DEBUG_INFO, "GenSsdt start\n"));
+ Status = gBS->LocateProtocol (&gEfiAcpiTableProtocolGuid, NULL, (VOID **) &AcpiTable);
+ ASSERT_EFI_ERROR(Status);
+
+ //
+ // Look for ACPI data HOB from PCT
+ //
+ PctAcpiDataBase = (UINT8 *) PcdGetPtr(PcdBoardAcpiData);
+ if (PctAcpiDataBase == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ if (*PctAcpiDataBase != 0) {
+ PctAcpiDataHeader = (PCT_ACPI_BLOCK_HDR *) PctAcpiDataBase;
+ AcpiDataPointer = (UINT8 *) (PctAcpiDataBase + sizeof(PCT_ACPI_BLOCK_HDR));
+ // Get number of tables to be generated
+ TableCount = PctAcpiDataHeader->Count;
+ for (i=0; i<TableCount; i++) {
+ // Calculate table size to be created
+ Status = GetTableSize(AcpiDataPointer, &SsdtTableSize);
+ ASSERT_EFI_ERROR (Status);
+
+ // Allocate memory for SSDT
+ Pages = EFI_SIZE_TO_PAGES(SsdtTableSize);
+ Status = (gBS->AllocatePages) (
+ AllocateMaxAddress,
+ EfiACPIMemoryNVS,
+ Pages,
+ (EFI_PHYSICAL_ADDRESS *) &CurrentTable
+ );
+ ASSERT_EFI_ERROR (Status);
+ ZeroMem ((VOID *) CurrentTable, SsdtTableSize);
+
+ //Copy SSDT content to allocated space
+ Status = CreateAcpiTableInMemory(AcpiDataPointer, &SsdtTableSize, CurrentTable);
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Dump table content from memory
+ //
+ DEBUG_CODE_BEGIN();
+ PrintData = (UINT8 *)CurrentTable;
+ DEBUG((DEBUG_INFO, "GenSsdt TableDump:\n"));
+ for (j=0; j<SsdtTableSize; j++) {
+ DEBUG((DEBUG_INFO, "%02x ", *PrintData));
+ PrintData++;
+ }
+ DEBUG((DEBUG_INFO, "\n"));
+ DEBUG_CODE_END();
+
+ TableHandle = 0;
+ AcpiTableHeader = (EFI_ACPI_SDT_HEADER *)CurrentTable;
+
+ //
+ // Install SSDT
+ //
+ Status = AcpiTable->InstallAcpiTable (
+ AcpiTable,
+ CurrentTable,
+ AcpiTableHeader->Length,
+ &TableHandle
+ );
+
+ ASSERT_EFI_ERROR(Status);
+
+ AcpiDataPointer += ((EFI_ACPI_SDT_HEADER *) AcpiDataPointer)->Length;
+ }
+ }
+ return Status;
+}
\ No newline at end of file
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AdvancedAcpiDxe/GenSsdtLib.h b/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AdvancedAcpiDxe/GenSsdtLib.h
new file mode 100644
index 0000000000..0cb3a4aaef
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Acpi/AdvancedAcpiDxe/GenSsdtLib.h
@@ -0,0 +1,17 @@
+/** @file
+ This is an implementation of the ACPI platform driver.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _GEN_SSDT_LIB_H_
+#define _GEN_SSDT_LIB_H_
+
+EFI_STATUS
+GenerateSsdtFromConfigFile (
+ VOID
+);
+
+#endif
--
2.36.1.windows.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 5/6] AlderlakeOpenBoardPkg: Adds the Policy Module
[not found] <cover.1686770061.git.saloni.kasbekar@intel.com>
` (3 preceding siblings ...)
2023-06-14 19:17 ` [PATCH 4/6] AlderlakeOpenBoardPkg: Add ACPI module Saloni Kasbekar
@ 2023-06-14 19:17 ` Saloni Kasbekar
2023-06-14 19:17 ` [PATCH 6/6] AlderlakeOpenBoardPkg: Add Library Instances Saloni Kasbekar
5 siblings, 0 replies; 6+ messages in thread
From: Saloni Kasbekar @ 2023-06-14 19:17 UTC (permalink / raw)
To: devel
Cc: Saloni Kasbekar, Sai Chaganty, Nate DeSimone, Isaac Oram,
Rosen Chuang
Adds the following libraries within the Policy module
- DxeSiliconPolicyUpdateLib
- PeiPolicyBoardConfigLib
- PeiPolicyUpdateLib
- PeiSiliconPolicyUpdateLib
Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Isaac Oram <isaac.w.oram@intel.com>
Cc: Rosen Chuang <rosen.chuang@intel.com>
Signed-off-by: Saloni Kasbekar <saloni.kasbekar@intel.com>
---
.../DxeCpuPolicyInit.c | 147 +++++
.../DxeSaPolicyInit.c | 64 +++
.../DxeSiliconPolicyInit.c | 49 ++
.../DxeSiliconPolicyUpdateLate.c | 122 +++++
.../DxeSiliconPolicyUpdateLib.inf | 61 +++
.../PeiCpuPolicyBoardConfigPreMem.c | 59 ++
.../PeiMePolicyBoardConfig.c | 39 ++
.../PeiMePolicyBoardConfigPreMem.c | 39 ++
.../PeiPchPolicyBoardConfigPreMem.c | 42 ++
.../PeiPolicyBoardConfig.h | 29 +
.../PeiPolicyBoardConfigLib.inf | 72 +++
.../PeiPolicyBoardConfigLibFsp.inf | 67 +++
.../PeiSaPolicyBoardConfig.c | 47 ++
.../PeiSaPolicyBoardConfigPreMem.c | 48 ++
.../PeiSiPolicyBoardConfig.c | 23 +
.../PeiPolicyUpdateLib/PeiCpuPolicyUpdate.c | 344 ++++++++++++
.../PeiPolicyUpdateLib/PeiCpuPolicyUpdate.h | 31 ++
.../PeiCpuPolicyUpdatePreMem.c | 120 +++++
.../PeiPolicyUpdateLib/PeiMePolicyUpdate.c | 65 +++
.../PeiMePolicyUpdatePreMem.c | 60 +++
.../PeiPolicyUpdateLib/PeiPchPolicyUpdate.c | 267 ++++++++++
.../PeiPolicyUpdateLib/PeiPchPolicyUpdate.h | 34 ++
.../PeiPchPolicyUpdatePreMem.c | 173 ++++++
.../PeiPolicyUpdateLib/PeiPolicyUpdateLib.inf | 225 ++++++++
.../PeiPolicyUpdateLib/PeiSaPolicyUpdate.c | 293 ++++++++++
.../PeiPolicyUpdateLib/PeiSaPolicyUpdate.h | 47 ++
.../PeiSaPolicyUpdatePreMem.c | 502 ++++++++++++++++++
.../PeiPolicyUpdateLib/PeiSiPolicyUpdate.c | 114 ++++
.../PeiPolicyUpdateLib/PeiSiPolicyUpdate.h | 17 +
.../PeiSiliconPolicyUpdateLib/PeiCpuPolicy.h | 22 +
.../PeiSiliconPolicyUpdateLib/PeiMePolicy.h | 21 +
.../PeiSiliconPolicyUpdateLib/PeiPolicy.h | 21 +
.../PeiSiliconPolicyUpdateLib/PeiSaPolicy.h | 22 +
.../PeiSiliconPolicyUpdateLib/PeiSiPolicy.h | 21 +
.../PeiSiliconPolicyUpdateLate.c | 18 +
.../PeiSiliconPolicyUpdateLib.inf | 67 +++
.../PeiSiliconPolicyUpdatePostMem.c | 53 ++
.../PeiSiliconPolicyUpdatePreMem.c | 49 ++
38 files changed, 3494 insertions(+)
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdateLib/DxeCpuPolicyInit.c
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSaPolicyInit.c
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSiliconPolicyInit.c
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSiliconPolicyUpdateLate.c
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSiliconPolicyUpdateLib.inf
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyBoardConfigLib/PeiCpuPolicyBoardConfigPreMem.c
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyBoardConfigLib/PeiMePolicyBoardConfig.c
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyBoardConfigLib/PeiMePolicyBoardConfigPreMem.c
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyBoardConfigLib/PeiPchPolicyBoardConfigPreMem.c
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyBoardConfigLib/PeiPolicyBoardConfig.h
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyBoardConfigLib/PeiPolicyBoardConfigLib.inf
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyBoardConfigLib/PeiPolicyBoardConfigLibFsp.inf
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyBoardConfigLib/PeiSaPolicyBoardConfig.c
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyBoardConfigLib/PeiSaPolicyBoardConfigPreMem.c
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyBoardConfigLib/PeiSiPolicyBoardConfig.c
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiCpuPolicyUpdate.c
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiCpuPolicyUpdate.h
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiCpuPolicyUpdatePreMem.c
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiMePolicyUpdate.c
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiMePolicyUpdatePreMem.c
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiPchPolicyUpdate.c
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiPchPolicyUpdate.h
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiPchPolicyUpdatePreMem.c
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiPolicyUpdateLib.inf
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiSaPolicyUpdate.c
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiSaPolicyUpdate.h
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiSaPolicyUpdatePreMem.c
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiSiPolicyUpdate.c
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiSiPolicyUpdate.h
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiSiliconPolicyUpdateLib/PeiCpuPolicy.h
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiSiliconPolicyUpdateLib/PeiMePolicy.h
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiSiliconPolicyUpdateLib/PeiPolicy.h
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSaPolicy.h
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiPolicy.h
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLate.c
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdatePostMem.c
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdatePreMem.c
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdateLib/DxeCpuPolicyInit.c b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdateLib/DxeCpuPolicyInit.c
new file mode 100644
index 0000000000..25b401057d
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdateLib/DxeCpuPolicyInit.c
@@ -0,0 +1,147 @@
+/** @file
+ This file is SampleCode for Intel Silicon DXE Platform Policy initialzation.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+#include <PiDxe.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/UefiRuntimeServicesTableLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Protocol/CpuPolicyProtocol.h>
+#include <Library/PcdLib.h>
+
+DXE_CPU_POLICY_PROTOCOL mCpuPolicyData;
+
+/**
+ This function prints the CPU DXE phase policy.
+
+ @param[in] DxeCpuPolicy - CPU DXE Policy protocol
+**/
+VOID
+CpuDxePrintPolicyProtocol (
+ IN DXE_CPU_POLICY_PROTOCOL *DxeCpuPolicy
+ )
+{
+ DEBUG_CODE_BEGIN ();
+ DEBUG ((DEBUG_INFO, "\n------------------------ CPU Policy (DXE) print BEGIN -----------------\n"));
+ DEBUG ((DEBUG_INFO, "Revision : %x\n", DxeCpuPolicy->Revision));
+ ASSERT (DxeCpuPolicy->Revision == DXE_CPU_POLICY_PROTOCOL_REVISION);
+ DEBUG ((DEBUG_INFO, "DgrEnable : %x\n", DxeCpuPolicy->DgrEnable));
+ DEBUG ((DEBUG_INFO, "DgrStateSaveProtect : %x\n", DxeCpuPolicy->DgrStateSaveProtect));
+ DEBUG ((DEBUG_INFO, "DgrSpaEnable : %x\n", DxeCpuPolicy->DgrSpaEnable));
+ DEBUG ((DEBUG_INFO, "SmmMsrSaveStateEnable : %x\n", DxeCpuPolicy->SmmMsrSaveStateEnable));
+ DEBUG ((DEBUG_INFO, "SmmUseDelayIndication : %x\n", DxeCpuPolicy->SmmUseDelayIndication));
+ DEBUG ((DEBUG_INFO, "SmmUseBlockIndication : %x\n", DxeCpuPolicy->SmmUseBlockIndication));
+ DEBUG ((DEBUG_INFO, "SmmUseSmmEnableIndication : %x\n", DxeCpuPolicy->SmmUseSmmEnableIndication));
+ DEBUG ((DEBUG_INFO, "SmmProcTraceEnable : %x\n", DxeCpuPolicy->SmmProcTraceEnable));
+ DEBUG ((DEBUG_INFO, "\n------------------------ CPU Policy (DXE) print END -----------------\n"));
+ DEBUG_CODE_END ();
+}
+
+/**
+ Get data for CPU policy from setup options.
+
+ @param[in] DxeCpuPolicy The pointer to get CPU Policy protocol instance
+
+ @retval EFI_SUCCESS Operation success.
+
+**/
+EFI_STATUS
+EFIAPI
+UpdateDxeSiCpuPolicy (
+ IN OUT DXE_CPU_POLICY_PROTOCOL *DxeCpuPolicy
+ )
+{
+
+#if FixedPcdGetBool (PcdPpamEnable) == 1
+ DxeCpuPolicy->DgrEnable = 1;
+#endif
+#if FixedPcdGetBool (PcdSpsStateSaveEnable) == 1
+ DxeCpuPolicy->DgrStateSaveProtect = 1;
+#endif
+ DxeCpuPolicy->SmmUseDelayIndication = 1;
+ DxeCpuPolicy->SmmUseBlockIndication = 1;
+ DxeCpuPolicy->SmmUseSmmEnableIndication = 1;
+
+ return EFI_SUCCESS;
+}
+
+/**
+ CpuInstallPolicyProtocol installs CPU Policy.
+ While installed, RC assumes the Policy is ready and finalized. So please update and override
+ any setting before calling this function.
+
+ @param[in] ImageHandle Image handle of this driver.
+ @param[in] DxeCpuPolicy The pointer to CPU Policy Protocol instance
+
+ @retval EFI_SUCCESS The policy is installed.
+ @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer
+
+**/
+EFI_STATUS
+EFIAPI
+CpuInstallPolicyProtocol (
+ IN EFI_HANDLE ImageHandle,
+ IN DXE_CPU_POLICY_PROTOCOL *DxeCpuPolicy
+ )
+{
+ EFI_STATUS Status;
+
+ ///
+ /// Print CPU DXE Policy
+ ///
+ CpuDxePrintPolicyProtocol (DxeCpuPolicy);
+
+ ///
+ /// Install the DXE_CPU_POLICY_PROTOCOL interface
+ ///
+ Status = gBS->InstallMultipleProtocolInterfaces (
+ &ImageHandle,
+ &gDxeCpuPolicyProtocolGuid,
+ DxeCpuPolicy,
+ NULL
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ return Status;
+}
+
+
+/**
+ Initilize Intel CPU DXE Platform Policy
+
+ @param[in] ImageHandle Image handle of this driver.
+
+ @retval EFI_SUCCESS Initialization complete.
+ @exception EFI_UNSUPPORTED The chipset is unsupported by this driver.
+ @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize the driver.
+ @retval EFI_DEVICE_ERROR Device error, driver exits abnormally.
+**/
+EFI_STATUS
+EFIAPI
+CpuPolicyInitDxe (
+ IN EFI_HANDLE ImageHandle
+ )
+{
+ EFI_STATUS Status;
+
+ ZeroMem (&mCpuPolicyData, sizeof (DXE_CPU_POLICY_PROTOCOL));
+ mCpuPolicyData.Revision = DXE_CPU_POLICY_PROTOCOL_REVISION;
+
+ //UpdateDxeSiCpuPolicy (&mCpuPolicyData);
+
+ //
+ // Install CpuInstallPolicyProtocol.
+ // While installed, RC assumes the Policy is ready and finalized. So please
+ // update and override any setting before calling this function.
+ //
+ Status = CpuInstallPolicyProtocol (ImageHandle, &mCpuPolicyData);
+ ASSERT_EFI_ERROR (Status);
+
+ return Status;
+}
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSaPolicyInit.c b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSaPolicyInit.c
new file mode 100644
index 0000000000..da2f568e07
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSaPolicyInit.c
@@ -0,0 +1,64 @@
+/** @file
+ This file initialises and Installs GopPolicy Protocol.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Uefi.h>
+#include <Library/DebugLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/GraphicsInfoLib.h>
+#include <Protocol/SaPolicy.h>
+
+EFI_STATUS
+EFIAPI
+CreateSaDxeConfigBlocks (
+ IN OUT VOID **SaPolicy
+ );
+
+EFI_STATUS
+EFIAPI
+SaInstallPolicyProtocol (
+ IN EFI_HANDLE ImageHandle,
+ IN VOID *SaPolicy
+ );
+
+/**
+ Initialize SA DXE Policy
+
+ @param[in] ImageHandle Image handle of this driver.
+
+ @retval EFI_SUCCESS Initialization complete.
+ @retval EFI_UNSUPPORTED The chipset is unsupported by this driver.
+ @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize the driver.
+ @retval EFI_DEVICE_ERROR Device error, driver exits abnormally.
+**/
+EFI_STATUS
+EFIAPI
+SaPolicyInitDxe (
+ IN EFI_HANDLE ImageHandle
+ )
+{
+ EFI_STATUS Status;
+ SA_POLICY_PROTOCOL *SaPolicy;
+
+ //
+ // Call CreateSaDxeConfigBlocks to create & initialize platform policy structure
+ // and get all Intel default policy settings.
+ //
+ Status = CreateSaDxeConfigBlocks (&SaPolicy);
+ DEBUG ((DEBUG_INFO, "SaPolicy->TableHeader.NumberOfBlocks = 0x%x\n ", SaPolicy->TableHeader.NumberOfBlocks));
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Install SaInstallPolicyProtocol.
+ // While installed, RC assumes the Policy is ready and finalized. So please
+ // update and override any setting before calling this function.
+ //
+ Status = SaInstallPolicyProtocol (ImageHandle, SaPolicy);
+ ASSERT_EFI_ERROR (Status);
+
+ return EFI_SUCCESS;
+}
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSiliconPolicyInit.c b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSiliconPolicyInit.c
new file mode 100644
index 0000000000..00c90d438b
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSiliconPolicyInit.c
@@ -0,0 +1,49 @@
+/** @file
+ This file is SampleCode for Intel Silicon DXE Platform Policy initialzation.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+#include <Protocol/FirmwareVolume2.h>
+#include <Guid/StatusCodeDataTypeId.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/DebugLib.h>
+#include <Protocol/SiPolicyProtocol.h>
+#include <Library/BaseLib.h>
+
+DXE_SI_POLICY_PROTOCOL mSiPolicyData = { 0 };
+
+/**
+ Initilize Intel Cpu DXE Platform Policy
+
+ @param[in] ImageHandle Image handle of this driver.
+
+ @retval EFI_SUCCESS Initialization complete.
+ @exception EFI_UNSUPPORTED The chipset is unsupported by this driver.
+ @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize the driver.
+ @retval EFI_DEVICE_ERROR Device error, driver exits abnormally.
+**/
+EFI_STATUS
+EFIAPI
+SiliconPolicyInitDxe (
+ IN EFI_HANDLE ImageHandle
+ )
+{
+ EFI_STATUS Status;
+
+ mSiPolicyData.Revision = DXE_SI_POLICY_PROTOCOL_REVISION;
+ mSiPolicyData.SmbiosOemTypeFirmwareVersionInfo = (UINT8) PcdGet8 (PcdSmbiosOemTypeFirmwareVersionInfo);
+ ///
+ /// Install the DXE_SI_POLICY_PROTOCOL interface
+ ///
+ Status = gBS->InstallMultipleProtocolInterfaces (
+ &ImageHandle,
+ &gDxeSiPolicyProtocolGuid,
+ &mSiPolicyData,
+ NULL
+ );
+ ASSERT_EFI_ERROR (Status);
+ return Status;
+}
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSiliconPolicyUpdateLate.c b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSiliconPolicyUpdateLate.c
new file mode 100644
index 0000000000..67171b09b7
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSiliconPolicyUpdateLate.c
@@ -0,0 +1,122 @@
+/** @file
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <PiDxe.h>
+#include <Library/PcdLib.h>
+#include <Library/DebugLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+
+/**
+ Initialize SA DXE Policy
+
+ @param[in] ImageHandle Image handle of this driver.
+
+ @retval EFI_SUCCESS Initialization complete.
+ @retval EFI_UNSUPPORTED The chipset is unsupported by this driver.
+ @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize the driver.
+ @retval EFI_DEVICE_ERROR Device error, driver exits abnormally.
+**/
+EFI_STATUS
+EFIAPI
+SaPolicyInitDxe (
+ IN EFI_HANDLE ImageHandle
+ );
+
+/**
+ Initilize Intel Silicon DXE Platform Policy
+
+ @param[in] ImageHandle Image handle of this driver.
+
+ @retval EFI_SUCCESS Initialization complete.
+ @exception EFI_UNSUPPORTED The chipset is unsupported by this driver.
+ @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize the driver.
+ @retval EFI_DEVICE_ERROR Device error, driver exits abnormally.
+**/
+EFI_STATUS
+EFIAPI
+SiliconPolicyInitDxe (
+ IN EFI_HANDLE ImageHandle
+ );
+
+/**
+ Initialize CPU DXE Policy
+
+ @param[in] ImageHandle - Image handle of this driver.
+
+ @retval EFI_SUCCESS Initialization complete.
+ @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize the driver.
+ @retval EFI_DEVICE_ERROR Device error, driver exits abnormally.
+**/
+EFI_STATUS
+EFIAPI
+CpuPolicyInitDxe (
+ IN EFI_HANDLE ImageHandle
+ );
+
+/**
+ Initialize GOP DXE Policy
+
+ @param[in] ImageHandle - Image handle of this driver.
+
+ @retval EFI_SUCCESS Initialization complete.
+ @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize the driver.
+ @retval EFI_DEVICE_ERROR Device error, driver exits abnormally.
+**/
+EFI_STATUS
+EFIAPI
+GopPolicyInitDxe (
+ IN EFI_HANDLE ImageHandle
+ );
+
+/**
+ Performs silicon late policy update.
+
+ The meaning of Policy is defined by silicon code.
+ It could be the raw data, a handle, a Protocol, etc.
+
+ The input Policy must be returned by SiliconPolicyDoneLate().
+
+ In FSP or non-FSP path, the board may use additional way to get
+ the silicon policy data field based upon the input Policy.
+
+ @param[in, out] Policy Pointer to policy.
+
+ @return the updated policy.
+**/
+VOID *
+EFIAPI
+SiliconPolicyUpdateLate (
+ IN OUT VOID *Policy
+ )
+{
+ EFI_STATUS Status;
+
+ Status = EFI_SUCCESS;
+
+ //
+ // SystemAgent Dxe Platform Policy Initialization
+ //
+ Status = SaPolicyInitDxe (gImageHandle);
+ DEBUG ((DEBUG_INFO, "SystemAgent Dxe Platform Policy Initialization status: %r\n", Status));
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Silicon Dxe Platform Policy Initialization
+ //
+ Status = SiliconPolicyInitDxe (gImageHandle);
+ DEBUG ((DEBUG_INFO, "Silicon Dxe Platform Policy Initialization status: %r\n", Status));
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // CPU DXE Platform Policy Initialization
+ //
+ Status = CpuPolicyInitDxe (gImageHandle);
+ DEBUG ((DEBUG_INFO, "Cpu Dxe Platform Policy Initialization status: %r\n", Status));
+ ASSERT_EFI_ERROR (Status);
+
+ return EFI_SUCCESS;
+}
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSiliconPolicyUpdateLib.inf b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSiliconPolicyUpdateLib.inf
new file mode 100644
index 0000000000..6cd1923792
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSiliconPolicyUpdateLib.inf
@@ -0,0 +1,61 @@
+## @file
+# Component information file for Silicon Policy Update Library
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+###
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = DxeSiliconUpdateLib
+ FILE_GUID = C523609D-E354-416B-B24F-33468D4BD21D
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = SiliconPolicyUpdateLib
+
+[LibraryClasses]
+ BaseLib
+ BaseMemoryLib
+ PcdLib
+ DebugLib
+ UefiBootServicesTableLib
+ MemoryAllocationLib
+ DxeSaPolicyLib
+ UefiLib
+ ConfigBlockLib
+ GraphicsInfoLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ AlderlakeSiliconPkg/SiPkg.dec
+ MinPlatformPkg/MinPlatformPkg.dec
+ IntelSiliconPkg/IntelSiliconPkg.dec
+ AlderlakeOpenBoardPkg/OpenBoardPkg.dec
+
+[Sources]
+ DxeSiliconPolicyUpdateLate.c
+ DxeSaPolicyInit.c
+ DxeSiliconPolicyInit.c
+ DxeCpuPolicyInit.c
+
+[Pcd]
+ gBoardModuleTokenSpaceGuid.PcdIntelGopEnable
+ gBoardModuleTokenSpaceGuid.PcdGraphicsVbtGuid
+ gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange
+ gBoardModuleTokenSpaceGuid.PcdVbtMipiGuid
+ gIntelSiliconPkgTokenSpaceGuid.PcdIntelGraphicsVbtFileGuid
+ gPlatformModuleTokenSpaceGuid.PcdSmbiosOemTypeFirmwareVersionInfo ## CONSUMES
+ gSiPkgTokenSpaceGuid.PcdPpamEnable ## CONSUMES
+ gSiPkgTokenSpaceGuid.PcdSpsStateSaveEnable ## CONSUMES
+
+[Protocols]
+ gEfiFirmwareVolume2ProtocolGuid ## CONSUMES
+ gSaPolicyProtocolGuid ## CONSUMES
+ gDxeSiPolicyProtocolGuid ## PRODUCES
+ gGopPolicyProtocolGuid ## PRODUCES
+ gDxeCpuPolicyProtocolGuid ## PRODUCES
+
+[Depex]
+ gEfiVariableArchProtocolGuid
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyBoardConfigLib/PeiCpuPolicyBoardConfigPreMem.c b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyBoardConfigLib/PeiCpuPolicyBoardConfigPreMem.c
new file mode 100644
index 0000000000..6051baa483
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyBoardConfigLib/PeiCpuPolicyBoardConfigPreMem.c
@@ -0,0 +1,59 @@
+/** @file
+ Intel PEI CPU Pre-Memory Policy update by board configuration
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+#include "PeiPolicyBoardConfig.h"
+#include <Register/Cpuid.h>
+#include <PolicyUpdateMacro.h>
+
+#define GET_OCCUPIED_SIZE(ActualSize, Alignment) \
+ ((ActualSize) + (((Alignment) - ((ActualSize) & ((Alignment) - 1))) & ((Alignment) - 1)))
+
+/**
+ This function performs PEI CPU Pre-Memory Policy update by board configuration.
+
+ @retval EFI_SUCCESS The SI Policy is successfully updated.
+ @retval Others The SI Policy is not successfully updated.
+**/
+EFI_STATUS
+EFIAPI
+UpdatePeiCpuPolicyBoardConfigPreMem (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+ CPUID_VERSION_INFO_ECX Ecx;
+#if FixedPcdGet8(PcdFspModeSelection) == 1
+ VOID *FspmUpd;
+#else
+ SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi;
+ CPU_SECURITY_PREMEM_CONFIG *CpuSecurityPreMemConfig;
+#endif
+
+ DEBUG ((DEBUG_INFO, "Updating CPU Policy by board config in Pre-Mem\n"));
+
+#if FixedPcdGet8(PcdFspModeSelection) == 1
+ FspmUpd = NULL;
+#else
+ SiPreMemPolicyPpi = NULL;
+ CpuSecurityPreMemConfig = NULL;
+#endif
+
+#if FixedPcdGet8(PcdFspModeSelection) == 1
+ FspmUpd = (FSPM_UPD *) PcdGet32 (PcdFspmUpdDataAddress);
+ ASSERT (FspmUpd != NULL);
+#else
+ Status = PeiServicesLocatePpi (&gSiPreMemPolicyPpiGuid, 0, NULL, (VOID **) &SiPreMemPolicyPpi);
+ ASSERT_EFI_ERROR (Status);
+
+
+ Status = GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gCpuSecurityPreMemConfigGuid, (VOID *) &CpuSecurityPreMemConfig);
+ ASSERT_EFI_ERROR(Status);
+#endif
+ AsmCpuid (CPUID_VERSION_INFO, NULL, NULL, &Ecx.Uint32, NULL);
+
+ return EFI_SUCCESS;
+}
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyBoardConfigLib/PeiMePolicyBoardConfig.c b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyBoardConfigLib/PeiMePolicyBoardConfig.c
new file mode 100644
index 0000000000..7611a0d9c5
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyBoardConfigLib/PeiMePolicyBoardConfig.c
@@ -0,0 +1,39 @@
+/** @file
+ Intel PEI ME Policy update by board configuration
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+#include "PeiPolicyBoardConfig.h"
+
+/**
+ This function performs PEI ME Policy update by board configuration.
+
+ @retval EFI_SUCCESS The SI Policy is successfully updated.
+ @retval Others The SI Policy is not successfully updated.
+**/
+EFI_STATUS
+EFIAPI
+UpdatePeiMePolicyBoardConfig (
+ VOID
+ )
+{
+#if FixedPcdGet8(PcdFspModeSelection) == 0
+ EFI_STATUS Status;
+ SI_POLICY_PPI *SiPolicyPpi;
+
+ DEBUG ((DEBUG_INFO, "Updating ME Policy by board config in Post-Mem\n"));
+
+ Status = EFI_SUCCESS;
+ SiPolicyPpi = NULL;
+
+ Status = PeiServicesLocatePpi (&gSiPolicyPpiGuid, 0, NULL, (VOID **) &SiPolicyPpi);
+ ASSERT_EFI_ERROR (Status);
+
+ return Status;
+#else
+ return EFI_SUCCESS;
+#endif
+
+}
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyBoardConfigLib/PeiMePolicyBoardConfigPreMem.c b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyBoardConfigLib/PeiMePolicyBoardConfigPreMem.c
new file mode 100644
index 0000000000..c6e8dbdb2b
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyBoardConfigLib/PeiMePolicyBoardConfigPreMem.c
@@ -0,0 +1,39 @@
+/** @file
+ Intel PEI ME Pre-Memory Policy update by board configuration
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+#include "PeiPolicyBoardConfig.h"
+
+/**
+ This function performs PEI ME Pre-Memory Policy update by board configuration.
+
+ @retval EFI_SUCCESS The SI Policy is successfully updated.
+ @retval Others The SI Policy is not successfully updated.
+**/
+EFI_STATUS
+EFIAPI
+UpdatePeiMePolicyBoardConfigPreMem (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+#if FixedPcdGet8(PcdFspModeSelection) == 0
+ SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi;
+#endif
+
+ DEBUG ((DEBUG_INFO, "Updating ME Policy by board config in Pre-Mem\n"));
+
+ Status = EFI_SUCCESS;
+
+#if FixedPcdGet8(PcdFspModeSelection) == 0
+ Status = PeiServicesLocatePpi (&gSiPreMemPolicyPpiGuid, 0, NULL, (VOID **) &SiPreMemPolicyPpi);
+ ASSERT_EFI_ERROR (Status);
+
+#endif
+
+ return Status;
+}
+
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyBoardConfigLib/PeiPchPolicyBoardConfigPreMem.c b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyBoardConfigLib/PeiPchPolicyBoardConfigPreMem.c
new file mode 100644
index 0000000000..d17a75dce8
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyBoardConfigLib/PeiPchPolicyBoardConfigPreMem.c
@@ -0,0 +1,42 @@
+/** @file
+ Intel PEI PCH Pre-Memory Policy update by board configuration
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+#include "PeiPolicyBoardConfig.h"
+
+/**
+ This function performs PEI PCH Pre-Memory Policy update by board configuration.
+
+ @retval EFI_SUCCESS The SI Policy is successfully updated.
+ @retval Others The SI Policy is not successfully updated.
+**/
+EFI_STATUS
+EFIAPI
+UpdatePeiPchPolicyBoardConfigPreMem (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+#if FixedPcdGet8(PcdFspModeSelection) == 0
+ SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi;
+ PCH_GENERAL_PREMEM_CONFIG *PchGeneralPreMemConfig;
+#endif
+
+ DEBUG ((DEBUG_INFO, "Updating PCH Policy by board config in Pre-Mem\n"));
+
+ Status = EFI_SUCCESS;
+
+#if FixedPcdGet8(PcdFspModeSelection) == 0
+ Status = PeiServicesLocatePpi (&gSiPreMemPolicyPpiGuid, 0, NULL, (VOID **) &SiPreMemPolicyPpi);
+ ASSERT_EFI_ERROR (Status);
+
+ Status = GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gPchGeneralPreMemConfigGuid, (VOID *) &PchGeneralPreMemConfig);
+ ASSERT_EFI_ERROR (Status);
+#endif
+
+ return Status;
+}
+
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyBoardConfigLib/PeiPolicyBoardConfig.h b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyBoardConfigLib/PeiPolicyBoardConfig.h
new file mode 100644
index 0000000000..6771f27a6d
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyBoardConfigLib/PeiPolicyBoardConfig.h
@@ -0,0 +1,29 @@
+/** @file
+ Header file for PeiPolicyBoardConfig library instance.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+#ifndef _PEI_POLICY_BOARD_CONFIG_H_
+#define _PEI_POLICY_BOARD_CONFIG_H_
+
+#include <PiPei.h>
+#include <Library/PeiServicesLib.h>
+#include <Library/DebugLib.h>
+#include <Library/HobLib.h>
+#include <Library/ConfigBlockLib.h>
+#include <Library/PeiPolicyBoardConfigLib.h>
+#include <Library/IoLib.h>
+#include <Ppi/ReadOnlyVariable2.h>
+#include <Library/BaseCryptLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Ppi/SiPolicy.h>
+#include <Library/SiPolicyLib.h>
+#if FixedPcdGet8(PcdFspModeSelection) == 1
+#include <FspmUpd.h>
+#include <FspsUpd.h>
+#include <Library/FspCommonLib.h>
+#endif
+
+#endif
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyBoardConfigLib/PeiPolicyBoardConfigLib.inf b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyBoardConfigLib/PeiPolicyBoardConfigLib.inf
new file mode 100644
index 0000000000..d1bfd07ab6
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyBoardConfigLib/PeiPolicyBoardConfigLib.inf
@@ -0,0 +1,72 @@
+### @file
+# Module Information file for PeiPolicyBoardConfigLib Library
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+###
+
+[Defines]
+ INF_VERSION = 0x00010017
+ BASE_NAME = PeiPolicyBoardConfigLib
+ FILE_GUID = B1E959E3-9DCA-4D6F-938C-420C3BF5D820
+ VERSION_STRING = 1.0
+ MODULE_TYPE = PEIM
+ LIBRARY_CLASS = PeiPolicyBoardConfigLib|PEIM PEI_CORE SEC
+
+[Sources]
+ PeiCpuPolicyBoardConfigPreMem.c
+ PeiMePolicyBoardConfigPreMem.c
+ PeiMePolicyBoardConfig.c
+ PeiPchPolicyBoardConfigPreMem.c
+ PeiSaPolicyBoardConfigPreMem.c
+ PeiSaPolicyBoardConfig.c
+ PeiSiPolicyBoardConfig.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ AlderlakeSiliconPkg/SiPkg.dec
+ IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec
+ CryptoPkg/CryptoPkg.dec
+ SecurityPkg/SecurityPkg.dec
+ UefiCpuPkg/UefiCpuPkg.dec
+ AlderlakeOpenBoardPkg/OpenBoardPkg.dec
+ IntelSiliconPkg/IntelSiliconPkg.dec
+ MinPlatformPkg/MinPlatformPkg.dec
+
+[LibraryClasses]
+ PcdLib
+ DebugLib
+ HobLib
+ ConfigBlockLib
+ IoLib
+ BaseCryptLib
+ BaseMemoryLib
+ FirmwareBootMediaLib
+ CpuPlatformLib
+ PmcLib
+ GpioLib
+
+
+[Guids]
+ gCpuSecurityPreMemConfigGuid ## CONSUMES
+ gPchGeneralPreMemConfigGuid ## CONSUMES
+ gSaMiscPeiPreMemConfigGuid ## CONSUMES
+ gPchGeneralConfigGuid ## CONSUMES
+
+[Ppis]
+ gEfiPeiReadOnlyVariable2PpiGuid ## CONSUMES
+
+[Pcd]
+ gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection ## CONSUMES
+ gSiPkgTokenSpaceGuid.PcdSmbusBaseAddress ## CONSUMES
+ gPlatformModuleTokenSpaceGuid.PcdDmiBaseAddress ## CONSUMES
+ gPlatformModuleTokenSpaceGuid.PcdEpBaseAddress ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdBoardId ## CONSUMES
+
+ [FixedPcd]
+ gSiPkgTokenSpaceGuid.PcdBiosSize ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdFlashFvFirmwareBinariesBase ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryBase ## CONSUMES
+ gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress ## CONSUMES
+ gSiPkgTokenSpaceGuid.PcdAdlSSupport ## CONSUMES
\ No newline at end of file
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyBoardConfigLib/PeiPolicyBoardConfigLibFsp.inf b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyBoardConfigLib/PeiPolicyBoardConfigLibFsp.inf
new file mode 100644
index 0000000000..2816ca6d76
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyBoardConfigLib/PeiPolicyBoardConfigLibFsp.inf
@@ -0,0 +1,67 @@
+### @file
+# Module Information file for PeiPolicyBoardConfigLib Library
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+###
+
+[Defines]
+ INF_VERSION = 0x00010017
+ BASE_NAME = PeiPolicyBoardConfigLib
+ FILE_GUID = B1E959E3-9DCA-4D6F-938C-420C3BF5D820
+ VERSION_STRING = 1.0
+ MODULE_TYPE = PEIM
+ LIBRARY_CLASS = PeiPolicyBoardConfigLib|PEIM PEI_CORE SEC
+
+[Sources]
+ PeiCpuPolicyBoardConfigPreMem.c
+ PeiMePolicyBoardConfigPreMem.c
+ PeiMePolicyBoardConfig.c
+ PeiPchPolicyBoardConfigPreMem.c
+ PeiSaPolicyBoardConfigPreMem.c
+ PeiSaPolicyBoardConfig.c
+ PeiSiPolicyBoardConfig.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ AlderlakeSiliconPkg/SiPkg.dec
+ IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec
+ SecurityPkg/SecurityPkg.dec
+ CryptoPkg/CryptoPkg.dec
+ IntelFsp2Pkg/IntelFsp2Pkg.dec
+ AlderLakeFspBinPkg/Client/AlderLakeP/AlderLakeFspBinPkg.dec
+ UefiCpuPkg/UefiCpuPkg.dec
+ AlderlakeOpenBoardPkg/OpenBoardPkg.dec
+ MinPlatformPkg/MinPlatformPkg.dec
+
+[LibraryClasses]
+ PcdLib
+ DebugLib
+ HobLib
+ IoLib
+ BaseCryptLib
+ BaseMemoryLib
+ PmcLib
+ FspCommonLib
+ GpioLib
+ PcdLib
+
+[Ppis]
+ gEfiPeiReadOnlyVariable2PpiGuid ## CONSUMES
+
+[Pcd]
+ gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection ## CONSUMES
+ gSiPkgTokenSpaceGuid.PcdSmbusBaseAddress ## CONSUMES
+ gPlatformModuleTokenSpaceGuid.PcdDmiBaseAddress ## CONSUMES
+ gPlatformModuleTokenSpaceGuid.PcdEpBaseAddress ## CONSUMES
+ gIntelFsp2WrapperTokenSpaceGuid.PcdFspmUpdDataAddress ## CONSUMES
+ gIntelFsp2WrapperTokenSpaceGuid.PcdFspsUpdDataAddress ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdBoardId ## CONSUMES
+
+[FixedPcd]
+ gSiPkgTokenSpaceGuid.PcdBiosSize ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdFlashFvFirmwareBinariesBase ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryBase ## CONSUMES
+ gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress ## CONSUMES
+ gSiPkgTokenSpaceGuid.PcdAdlSSupport ## CONSUMES
\ No newline at end of file
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyBoardConfigLib/PeiSaPolicyBoardConfig.c b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyBoardConfigLib/PeiSaPolicyBoardConfig.c
new file mode 100644
index 0000000000..236d9afcc4
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyBoardConfigLib/PeiSaPolicyBoardConfig.c
@@ -0,0 +1,47 @@
+/** @file
+ Intel PEI SA Policy update by board configuration
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+#include "PeiPolicyBoardConfig.h"
+#include <Pins/GpioPinsVer2Lp.h>
+#include <PlatformBoardId.h>
+
+
+/**
+ This function performs PEI SA Policy update by board configuration.
+
+ @retval EFI_SUCCESS The SI Policy is successfully updated.
+ @retval Others The SI Policy is not successfully updated.
+**/
+EFI_STATUS
+EFIAPI
+UpdatePeiSaPolicyBoardConfig (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+#if FixedPcdGet8(PcdFspModeSelection) == 1
+ VOID *FspsUpd;
+#endif
+
+ DEBUG ((DEBUG_INFO, "Updating SA Policy by board config in Post-Mem\n"));
+
+ Status = EFI_SUCCESS;
+#if FixedPcdGet8(PcdFspModeSelection) == 1
+ FspsUpd = NULL;
+#endif
+
+#if FixedPcdGet8(PcdFspModeSelection) == 1
+ FspsUpd = (FSPS_UPD *) PcdGet32 (PcdFspsUpdDataAddress);
+ ASSERT (FspsUpd != NULL);
+ if (FspsUpd == NULL){
+ return EFI_OUT_OF_RESOURCES;
+ }
+#endif
+
+
+ return Status;
+}
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyBoardConfigLib/PeiSaPolicyBoardConfigPreMem.c b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyBoardConfigLib/PeiSaPolicyBoardConfigPreMem.c
new file mode 100644
index 0000000000..0610b0f5c2
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyBoardConfigLib/PeiSaPolicyBoardConfigPreMem.c
@@ -0,0 +1,48 @@
+/** @file
+ Intel PEI SA Pre-Memory Policy update by board configuration
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+#include "PeiPolicyBoardConfig.h"
+
+/**
+ This function performs PEI SA Pre-Memory Policy update by board configuration.
+
+ @retval EFI_SUCCESS The SI Policy is successfully updated.
+ @retval Others The SI Policy is not successfully updated.
+**/
+EFI_STATUS
+EFIAPI
+UpdatePeiSaPolicyBoardConfigPreMem (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+#if FixedPcdGet8(PcdFspModeSelection) == 1
+ VOID *FspmUpd;
+#else
+ SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi;
+#endif
+
+ DEBUG ((DEBUG_INFO, "Updating SA Policy by board config in Pre-Mem\n"));
+
+ Status = EFI_SUCCESS;
+#if FixedPcdGet8(PcdFspModeSelection) == 1
+ FspmUpd = NULL;
+#else
+ SiPreMemPolicyPpi = NULL;
+#endif
+
+#if FixedPcdGet8(PcdFspModeSelection) == 1
+ FspmUpd = (FSPM_UPD *) PcdGet32 (PcdFspmUpdDataAddress);
+ ASSERT (FspmUpd != NULL);
+#else
+ Status = PeiServicesLocatePpi (&gSiPreMemPolicyPpiGuid, 0, NULL, (VOID **) &SiPreMemPolicyPpi);
+ ASSERT_EFI_ERROR (Status);
+#endif
+
+ return Status;
+}
+
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyBoardConfigLib/PeiSiPolicyBoardConfig.c b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyBoardConfigLib/PeiSiPolicyBoardConfig.c
new file mode 100644
index 0000000000..ce2fe19fa2
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyBoardConfigLib/PeiSiPolicyBoardConfig.c
@@ -0,0 +1,23 @@
+/** @file
+ Intel PEI SA Policy update by board configuration
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+#include "PeiPolicyBoardConfig.h"
+
+/**
+ This function performs PEI SI Policy update by board configuration.
+
+ @retval EFI_SUCCESS The SI Policy is successfully updated.
+ @retval Others The SI Policy is not successfully updated.
+**/
+EFI_STATUS
+EFIAPI
+UpdatePeiSiPolicyBoardConfig (
+ VOID
+ )
+{
+ return EFI_SUCCESS;
+}
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiCpuPolicyUpdate.c b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiCpuPolicyUpdate.c
new file mode 100644
index 0000000000..cfaf45a679
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiCpuPolicyUpdate.c
@@ -0,0 +1,344 @@
+/** @file
+ CPU PEI Policy Update & initialization.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+
+**/
+#include "PeiCpuPolicyUpdate.h"
+#include <Library/ConfigBlockLib.h>
+#include <Library/CpuPlatformLib.h>
+#include <Library/HobLib.h>
+#include <Library/PeiSiPolicyUpdateLib.h>
+#include <Library/SiPolicyLib.h>
+#include <Library/Tpm12CommandLib.h>
+#include <Library/Tpm2CommandLib.h>
+#include <Ppi/SecPlatformInformation2.h>
+
+#include <PolicyUpdateMacro.h>
+
+#if FixedPcdGet8(PcdFspModeSelection) == 1
+#include <FspmUpd.h>
+#include <FspsUpd.h>
+#include <Library/FspCommonLib.h>
+#endif
+
+#if FixedPcdGet8(PcdFspModeSelection) == 1
+/**
+ This routine is used to get Sec Platform Information Record2 Pointer.
+
+ @param[in] PeiServices Pointer to the PEI services table
+
+ @retval GetSecPlatformInformation2 - The pointer of Sec Platform Information Record2 Pointer.
+**/
+EFI_SEC_PLATFORM_INFORMATION_RECORD2 *
+GetSecPlatformInformation2 (
+ IN EFI_PEI_SERVICES **PeiServices
+ )
+{
+ EFI_SEC_PLATFORM_INFORMATION2_PPI *SecPlatformInformation2Ppi;
+ EFI_SEC_PLATFORM_INFORMATION_RECORD2 *SecPlatformInformation2 = NULL;
+ UINT64 InformationSize;
+ EFI_STATUS Status;
+
+ //
+ // Get BIST information from Sec Platform Information2 Ppi firstly
+ //
+ Status = PeiServicesLocatePpi (
+ &gEfiSecPlatformInformation2PpiGuid, // GUID
+ 0, // Instance
+ NULL, // EFI_PEI_PPI_DESCRIPTOR
+ (VOID ** ) &SecPlatformInformation2Ppi // PPI
+ );
+ if (EFI_ERROR(Status)) {
+ DEBUG((DEBUG_ERROR, "LocatePpi SecPlatformInformationPpi2 Status - %r\n", Status));
+ return NULL;
+ }
+
+ InformationSize = 0;
+
+ Status = SecPlatformInformation2Ppi->PlatformInformation2 (
+ (CONST EFI_PEI_SERVICES **) PeiServices,
+ &InformationSize,
+ SecPlatformInformation2
+ );
+
+ ASSERT (Status == EFI_BUFFER_TOO_SMALL);
+ if (Status != EFI_BUFFER_TOO_SMALL) {
+ return NULL;
+ }
+
+ SecPlatformInformation2 = AllocatePool((UINTN)InformationSize);
+ ASSERT (SecPlatformInformation2 != NULL);
+ if (SecPlatformInformation2 == NULL) {
+ return NULL;
+ }
+
+ //
+ // Retrieve BIST data from SecPlatform2
+ //
+ Status = SecPlatformInformation2Ppi->PlatformInformation2 (
+ (CONST EFI_PEI_SERVICES **) PeiServices,
+ &InformationSize,
+ SecPlatformInformation2
+ );
+ DEBUG((DEBUG_INFO, "SecPlatformInformation2Ppi->PlatformInformation2 Status - %r\n", Status));
+ ASSERT_EFI_ERROR (Status);
+ if (EFI_ERROR (Status)) {
+ return NULL;
+ }
+
+ return SecPlatformInformation2;
+}
+
+
+/**
+ This routine is used to get Sec Platform Information Record Pointer.
+
+ @param[in] PeiServices Pointer to the PEI services table
+
+ @retval GetSecPlatformInformation2 - The pointer of Sec Platform Information Record Pointer.
+**/
+EFI_SEC_PLATFORM_INFORMATION_RECORD2 *
+GetSecPlatformInformationInfoInFormat2 (
+ IN EFI_PEI_SERVICES **PeiServices
+ )
+{
+ EFI_SEC_PLATFORM_INFORMATION_PPI *SecPlatformInformationPpi;
+ EFI_SEC_PLATFORM_INFORMATION_RECORD *SecPlatformInformation = NULL;
+ EFI_SEC_PLATFORM_INFORMATION_RECORD2 *SecPlatformInformation2;
+ UINT64 InformationSize;
+ EFI_STATUS Status;
+
+ //
+ // Get BIST information from Sec Platform Information
+ //
+ Status = PeiServicesLocatePpi (
+ &gEfiSecPlatformInformationPpiGuid, // GUID
+ 0, // Instance
+ NULL, // EFI_PEI_PPI_DESCRIPTOR
+ (VOID ** ) &SecPlatformInformationPpi // PPI
+ );
+ if (EFI_ERROR(Status)) {
+ DEBUG((DEBUG_ERROR, "LocatePpi SecPlatformInformationPpi Status - %r\n", Status));
+ return NULL;
+ }
+
+ InformationSize = 0;
+ Status = SecPlatformInformationPpi->PlatformInformation (
+ (CONST EFI_PEI_SERVICES **) PeiServices,
+ &InformationSize,
+ SecPlatformInformation
+ );
+
+ ASSERT (Status == EFI_BUFFER_TOO_SMALL);
+ if (Status != EFI_BUFFER_TOO_SMALL) {
+ return NULL;
+ }
+
+ SecPlatformInformation = AllocatePool((UINTN)InformationSize);
+ ASSERT (SecPlatformInformation != NULL);
+ if (SecPlatformInformation == NULL) {
+ return NULL;
+ }
+
+ //
+ // Retrieve BIST data from SecPlatform
+ //
+ Status = SecPlatformInformationPpi->PlatformInformation (
+ (CONST EFI_PEI_SERVICES **) PeiServices,
+ &InformationSize,
+ SecPlatformInformation
+ );
+ DEBUG((DEBUG_INFO, "FSP SecPlatformInformation2Ppi->PlatformInformation Status - %r\n", Status));
+ ASSERT_EFI_ERROR (Status);
+ if (EFI_ERROR (Status)) {
+ return NULL;
+ }
+
+ SecPlatformInformation2 = AllocatePool(sizeof (EFI_SEC_PLATFORM_INFORMATION_RECORD2));
+ ASSERT (SecPlatformInformation2 != NULL);
+ if (SecPlatformInformation2 == NULL) {
+ return NULL;
+ }
+
+ SecPlatformInformation2->NumberOfCpus = 1;
+ SecPlatformInformation2->CpuInstance[0].CpuLocation = 0;
+ SecPlatformInformation2->CpuInstance[0].InfoRecord.x64HealthFlags.Uint32 = SecPlatformInformation->x64HealthFlags.Uint32;
+
+ FreePool(SecPlatformInformation);
+
+ return SecPlatformInformation2;
+}
+#endif
+
+#if FixedPcdGet8(PcdFspModeSelection) == 0
+/*
+ Get the uCode region from PCD settings, and copy the patches to memory.
+ This function is used to replace CpuLocateMicrocodePatch due to that function can not works
+ with uCode update new design.
+ In current uCode update solution, there are some padding data between uCode patches,
+ the algorithm in CpuLocateMicrocodePatch can not handle this.
+ Besides that, in CpuLocateMicrocodePatch function, the scan algorithm just find the first
+ correct uCode patch which is not the highest version uCode.
+ This function just copy the uCode region to memory, and in later, the CpuMpInit driver
+ will load the correct patch for CPU.
+
+ @param[out] RegionAddress Pointer to the uCode array.
+ @param[out] RegionSize Size of the microcode FV.
+
+ @retval EFI_SUCCESS Find uCode patch region and success copy the data to memory.
+ @retval EFI_NOT_FOUND Something wrong with uCode region.
+ @retval EFI_OUT_OF_RESOUCES Memory allocation fail.
+ @retval EFI_INVALID_PARAMETER RegionAddres or RegionSize is NULL.
+
+*/
+EFI_STATUS
+SearchMicrocodeRegion (
+ OUT UINTN *RegionAddress,
+ OUT UINTN *RegionSize
+ )
+{
+ UINTN MicrocodeStart;
+ UINTN MicrocodeEnd;
+ UINT8 *MemoryBuffer;
+
+ if (RegionAddress == NULL || RegionSize == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ *RegionAddress = 0;
+ *RegionSize = 0;
+
+ if ((FixedPcdGet32 (PcdFlashFvMicrocodeBase) == 0) || (FixedPcdGet32 (PcdFlashFvMicrocodeSize) == 0)) {
+ return EFI_NOT_FOUND;
+ }
+
+ MicrocodeStart = (UINTN) FixedPcdGet32 (PcdFlashFvMicrocodeBase) + (UINTN) FixedPcdGet32 (PcdMicrocodeOffsetInFv);
+ MicrocodeEnd = (UINTN) FixedPcdGet32 (PcdFlashFvMicrocodeBase) + (UINTN) FixedPcdGet32 (PcdFlashFvMicrocodeSize);
+ *RegionSize = MicrocodeEnd - MicrocodeStart;
+
+ DEBUG ((DEBUG_INFO, "[SearchMicrocodeRegion]: Microcode Region Address = %x, Size = %d\n", MicrocodeStart, *RegionSize));
+
+ MemoryBuffer = AllocatePages (EFI_SIZE_TO_PAGES (*RegionSize));
+ ASSERT (MemoryBuffer != NULL);
+ if (MemoryBuffer == NULL) {
+ DEBUG ((DEBUG_ERROR, "Failed to allocate enough memory for Microcode Patch.\n"));
+ return EFI_OUT_OF_RESOURCES;
+ } else {
+ CopyMem (MemoryBuffer, (UINT8 *)MicrocodeStart, *RegionSize);
+ *RegionAddress = (UINTN)MemoryBuffer;
+ DEBUG ((DEBUG_INFO, "Copy whole uCode region to memory, address = %x, size = %d\n", RegionAddress, *RegionSize));
+ }
+
+ return EFI_SUCCESS;
+}
+#endif
+
+/**
+ This function performs CPU PEI Policy initialization.
+
+ @retval EFI_SUCCESS The PPI is installed and initialized.
+ @retval EFI ERRORS The PPI is not successfully installed.
+ @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize the driver
+**/
+EFI_STATUS
+EFIAPI
+UpdatePeiCpuPolicy (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+ EFI_PEI_READ_ONLY_VARIABLE2_PPI *VariableServices;
+#if FixedPcdGet8(PcdFspModeSelection) == 1
+ VOID *FspsUpd;
+ VOID *FspmUpd;
+ EFI_SEC_PLATFORM_INFORMATION_RECORD2 *SecPlatformInformation2;
+#else
+ SI_POLICY_PPI *SiPolicyPpi;
+ SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi;
+ CPU_CONFIG *CpuConfig;
+ CPU_SECURITY_PREMEM_CONFIG *CpuSecurityPreMemConfig;
+#endif
+
+ DEBUG ((DEBUG_INFO, "Update PeiCpuPolicyUpdate Pos-Mem Start\n"));
+
+#if FixedPcdGet8(PcdFspModeSelection) == 1
+ FspsUpd = NULL;
+ FspmUpd = NULL;
+#else
+ SiPolicyPpi = NULL;
+ CpuConfig = NULL;
+ SiPreMemPolicyPpi = NULL;
+ CpuSecurityPreMemConfig = NULL;
+#endif
+
+#if FixedPcdGet8(PcdFspModeSelection) == 1
+ FspmUpd = (FSPM_UPD *) PcdGet32 (PcdFspmUpdDataAddress);
+ ASSERT (FspmUpd != NULL);
+
+ FspsUpd = (FSPS_UPD *) PcdGet32 (PcdFspsUpdDataAddress);
+ ASSERT (FspsUpd != NULL);
+#else
+ Status = PeiServicesLocatePpi (&gSiPreMemPolicyPpiGuid, 0, NULL, (VOID **) &SiPreMemPolicyPpi);
+ ASSERT_EFI_ERROR (Status);
+
+ Status = PeiServicesLocatePpi (&gSiPolicyPpiGuid, 0, NULL, (VOID **) &SiPolicyPpi);
+ ASSERT_EFI_ERROR (Status);
+
+ Status = GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gCpuSecurityPreMemConfigGuid, (VOID *) &CpuSecurityPreMemConfig);
+ ASSERT_EFI_ERROR (Status);
+
+ Status = GetConfigBlock ((VOID *) SiPolicyPpi, &gCpuConfigGuid, (VOID *) &CpuConfig);
+ ASSERT_EFI_ERROR (Status);
+#endif
+
+ //
+ // Make sure ReadOnlyVariablePpi is available
+ //
+ Status = PeiServicesLocatePpi (
+ &gEfiPeiReadOnlyVariable2PpiGuid,
+ 0,
+ NULL,
+ (VOID **) &VariableServices
+ );
+ ASSERT_EFI_ERROR (Status);
+
+
+
+
+ // Update value is related with Setup value, Need to check Policy Default
+ COMPARE_AND_UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.PpinSupport, CpuConfig->PpinSupport, 0); ///< reference code policy is disabled
+
+ UPDATE_POLICY (((FSPS_UPD *)FspsUpd)->FspsConfig.X2ApicSupport, CpuConfig->X2ApicSupport, 0);
+
+#if FixedPcdGet8(PcdFspModeSelection) == 0
+ Status = SearchMicrocodeRegion (
+ (UINTN *)&CpuConfig->MicrocodePatchAddress,
+ (UINTN *)&CpuConfig->MicrocodePatchRegionSize
+ );
+#endif
+
+
+#if FixedPcdGet8(PcdFspModeSelection) == 1
+ //
+ // Get BIST information from Sec Platform Information
+ //
+ SecPlatformInformation2 = GetSecPlatformInformation2 ((EFI_PEI_SERVICES **) GetPeiServicesTablePointer ());
+ if (SecPlatformInformation2 == NULL) {
+ SecPlatformInformation2 = GetSecPlatformInformationInfoInFormat2 ((EFI_PEI_SERVICES **) GetPeiServicesTablePointer ());
+ }
+
+ ASSERT (SecPlatformInformation2 != NULL);
+
+ if (SecPlatformInformation2 != NULL) {
+ ((FSPS_UPD *) FspsUpd)->FspsConfig.CpuBistData = (UINT32) SecPlatformInformation2;
+ DEBUG((DEBUG_INFO, "SecPlatformInformation NumberOfCpus - %x\n", SecPlatformInformation2->NumberOfCpus));
+ DEBUG((DEBUG_INFO, "SecPlatformInformation BIST - %x\n", SecPlatformInformation2->CpuInstance[0].InfoRecord.x64HealthFlags.Uint32));
+ }
+#endif
+
+
+ return EFI_SUCCESS;
+}
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiCpuPolicyUpdate.h b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiCpuPolicyUpdate.h
new file mode 100644
index 0000000000..b003481db0
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiCpuPolicyUpdate.h
@@ -0,0 +1,31 @@
+/** @file
+ Header file for PEI CpuPolicyUpdate.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+#ifndef _PEI_CPU_POLICY_UPDATE_H_
+#define _PEI_CPU_POLICY_UPDATE_H_
+
+#include <PiPei.h>
+#include <Ppi/SiPolicy.h>
+#include <Ppi/Wdt.h>
+#include <Ppi/ReadOnlyVariable2.h>
+#include <Library/PeiServicesTablePointerLib.h>
+#include <Library/DebugLib.h>
+#include <Library/PcdLib.h>
+#include <Library/IoLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <PlatformBoardId.h>
+#include <Library/BaseCryptLib.h>
+#include <Register/Cpuid.h>
+#include <Register/Msr.h>
+#include <Ppi/MasterBootMode.h>
+#include <Library/PeiServicesLib.h>
+#include "PeiPchPolicyUpdate.h"
+#include <Library/CpuPlatformLib.h>
+
+
+#endif
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiCpuPolicyUpdatePreMem.c b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiCpuPolicyUpdatePreMem.c
new file mode 100644
index 0000000000..f00257848e
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiCpuPolicyUpdatePreMem.c
@@ -0,0 +1,120 @@
+/** @file
+ This file is SampleCode of the library for Intel CPU PEI Policy initialization.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+#include "PeiCpuPolicyUpdate.h"
+#include <Library/ConfigBlockLib.h>
+#include <Library/CpuPlatformLib.h>
+#include <Library/FirmwareBootMediaLib.h>
+#include <Library/HobLib.h>
+#include <Library/PchCycleDecodingLib.h>
+#include <Library/PciSegmentLib.h>
+#include <Library/PeiSiPolicyUpdateLib.h>
+#include <Library/PmcLib.h>
+#include <Library/SiPolicyLib.h>
+#include <Library/SpiLib.h>
+#include <Ppi/Spi.h>
+#include <Register/CommonMsr.h>
+#include <Register/PchRegs.h>
+#include <PlatformBoardConfig.h>
+#include <PolicyUpdateMacro.h>
+#if FixedPcdGet8(PcdFspModeSelection) == 1
+#include <FspmUpd.h>
+#endif
+
+#define GET_OCCUPIED_SIZE(ActualSize, Alignment) \
+ ((ActualSize) + (((Alignment) - ((ActualSize) & ((Alignment) - 1))) & ((Alignment) - 1)))
+
+
+/**
+ This function performs CPU PEI Policy initialization in Pre-memory.
+
+ @retval EFI_SUCCESS The PPI is installed and initialized.
+ @retval EFI ERRORS The PPI is not successfully installed.
+ @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize the driver
+**/
+EFI_STATUS
+EFIAPI
+UpdatePeiCpuPolicyPreMem (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+ CPU_SECURITY_PREMEM_CONFIG *CpuSecurityPreMemConfig;
+ CPU_CONFIG_LIB_PREMEM_CONFIG *CpuConfigLibPreMemConfig;
+#if FixedPcdGet8(PcdFspModeSelection) == 1
+ VOID *FspmUpd;
+#else
+ SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi;
+#endif
+ UINT32 MaxLogicProcessors;
+ UINT16 BiosSize;
+ UINT16 BiosMemSizeInMb;
+ FW_BOOT_MEDIA_TYPE FwBootMediaType;
+ MSR_CORE_THREAD_COUNT_REGISTER MsrCoreThreadCount;
+ UINT8 AllCoreCount;
+ UINT8 AllSmallCoreCount;
+ UINT32 DisablePerCoreMask;
+
+ DEBUG ((DEBUG_INFO, "Update PeiCpuPolicyUpdate Pre-Mem Start\n"));
+
+#if FixedPcdGet8(PcdFspModeSelection) == 1
+ FspmUpd = NULL;
+#else
+ SiPreMemPolicyPpi = NULL;
+#endif
+ CpuSecurityPreMemConfig = NULL;
+ CpuConfigLibPreMemConfig = NULL;
+ BiosSize = 0;
+ BiosMemSizeInMb = 0;
+ FwBootMediaType = FwBootMediaMax;
+ AllCoreCount = 0;
+ AllSmallCoreCount = 0;
+ DisablePerCoreMask = 0;
+
+#if FixedPcdGet8(PcdFspModeSelection) == 1
+ FspmUpd = (FSPM_UPD *) PcdGet32 (PcdFspmUpdDataAddress);
+ ASSERT (FspmUpd != NULL);
+#else
+ Status = PeiServicesLocatePpi (&gSiPreMemPolicyPpiGuid, 0, NULL, (VOID **) &SiPreMemPolicyPpi);
+ ASSERT_EFI_ERROR (Status);
+ Status = GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gCpuSecurityPreMemConfigGuid, (VOID *) &CpuSecurityPreMemConfig);
+ ASSERT_EFI_ERROR (Status);
+ Status = GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gCpuConfigLibPreMemConfigGuid, (VOID *) &CpuConfigLibPreMemConfig);
+ ASSERT_EFI_ERROR (Status);
+#endif
+
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.SkipStopPbet, CpuSecurityPreMemConfig->SkipStopPbet, FALSE);
+
+ SpiServiceInit ();
+ DEBUG ((DEBUG_INFO, "BIOS Guard PCD and Policy are disabled\n"));
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.BiosGuard, CpuSecurityPreMemConfig->BiosGuard, CPU_FEATURE_DISABLE);
+
+ Status = GetFirmwareBootMediaType (&FwBootMediaType);
+ if (Status != EFI_SUCCESS) {
+ ASSERT_EFI_ERROR (Status);
+ DEBUG ((DEBUG_ERROR, "FirmwareBootMediaLib Error: Cannot Get Boot Media Type\n"));
+ }
+
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.CpuRatio, CpuConfigLibPreMemConfig->CpuRatio, 0);
+
+
+ ///
+ /// Set PcdCpuMaxLogicalProcessorNumber to max number of logical processors enabled
+ /// Read MSR_CORE_THREAD_COUNT (0x35) to check the total active Threads
+ ///
+ MsrCoreThreadCount.Uint64 = AsmReadMsr64 (MSR_CORE_THREAD_COUNT);
+ MaxLogicProcessors = MsrCoreThreadCount.Bits.Threadcount;
+ DEBUG ((DEBUG_INFO, "MaxLogicProcessors = %d\n", MaxLogicProcessors));
+
+#if (FixedPcdGet8(PcdFspModeSelection) == 1)
+ PcdSet32S (PcdCpuMaxLogicalProcessorNumber, MaxLogicProcessors);
+#else
+ PcdSetEx32S (&gUefiCpuPkgTokenSpaceGuid, PcdCpuMaxLogicalProcessorNumber, MaxLogicProcessors);
+#endif
+
+ return EFI_SUCCESS;
+}
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiMePolicyUpdate.c b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiMePolicyUpdate.c
new file mode 100644
index 0000000000..9504a736dd
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiMePolicyUpdate.c
@@ -0,0 +1,65 @@
+/** @file
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Library/ConfigBlockLib.h>
+#include <Library/DebugLib.h>
+#include <Library/PeiServicesLib.h>
+#include <Library/PeiSiPolicyUpdateLib.h>
+#include <Library/PmcLib.h>
+#include <Library/SiPolicyLib.h>
+#include <Ppi/ReadOnlyVariable2.h>
+
+#include <PolicyUpdateMacro.h>
+
+#if FixedPcdGet8(PcdFspModeSelection) == 1
+#include <FspsUpd.h>
+#endif
+
+/**
+ Update the ME Policy Library
+
+ @retval EFI_SUCCESS Update complete.
+ @retval Others Update unsuccessful.
+**/
+EFI_STATUS
+EFIAPI
+UpdatePeiMePolicy (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+
+#if FixedPcdGet8(PcdFspModeSelection) == 1
+ VOID *FspsUpd;
+#else
+ SI_POLICY_PPI *SiPolicyPpi;
+#endif
+
+
+ DEBUG ((DEBUG_INFO, "%a()\n", __FUNCTION__));
+
+#if FixedPcdGet8(PcdFspModeSelection) == 1
+ FspsUpd = NULL;
+#else
+ SiPolicyPpi = NULL;
+#endif
+
+#if FixedPcdGet8(PcdFspModeSelection) == 1
+ FspsUpd = (FSPS_UPD *) PcdGet32 (PcdFspsUpdDataAddress);
+ ASSERT (FspsUpd != NULL);
+#else
+ Status = PeiServicesLocatePpi (&gSiPolicyPpiGuid, 0, NULL, (VOID **) &SiPolicyPpi);
+ ASSERT_EFI_ERROR (Status);
+
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+#endif
+
+ return Status;
+}
+
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiMePolicyUpdatePreMem.c b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiMePolicyUpdatePreMem.c
new file mode 100644
index 0000000000..f5f4479f10
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiMePolicyUpdatePreMem.c
@@ -0,0 +1,60 @@
+/** @file
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Library/ConfigBlockLib.h>
+#include <Library/DebugLib.h>
+#include <Library/PeiServicesLib.h>
+#include <Library/PeiSiPolicyUpdateLib.h>
+#include <Library/SiPolicyLib.h>
+#include <Ppi/ReadOnlyVariable2.h>
+
+#include <PolicyUpdateMacro.h>
+
+#if FixedPcdGet8(PcdFspModeSelection) == 1
+#include <FspmUpd.h>
+#endif
+
+/**
+ Update the ME Policy Library
+
+ @retval EFI_SUCCESS Update complete.
+**/
+EFI_STATUS
+EFIAPI
+UpdatePeiMePolicyPreMem (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+#if FixedPcdGet8(PcdFspModeSelection) == 1
+ VOID *FspmUpd;
+#else
+ SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi;
+#endif
+
+ DEBUG ((DEBUG_INFO, "Update PeiMePolicyUpdate Pre-Mem Start\n"));
+
+#if FixedPcdGet8(PcdFspModeSelection) == 1
+ FspmUpd = NULL;
+#else
+ SiPreMemPolicyPpi = NULL;
+#endif
+
+ Status = EFI_SUCCESS;
+if (!EFI_ERROR (Status)) {
+#if FixedPcdGet8(PcdFspModeSelection) == 1
+ FspmUpd = (FSPM_UPD *) PcdGet32 (PcdFspmUpdDataAddress);
+ ASSERT (FspmUpd != NULL);
+#else
+ Status = PeiServicesLocatePpi (&gSiPreMemPolicyPpiGuid, 0, NULL, (VOID **) &SiPreMemPolicyPpi);
+ ASSERT_EFI_ERROR (Status);
+#endif
+
+ }
+
+ return Status;
+}
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiPchPolicyUpdate.c b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiPchPolicyUpdate.c
new file mode 100644
index 0000000000..9fe5e2dffe
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiPchPolicyUpdate.c
@@ -0,0 +1,267 @@
+/** @file
+ This file is SampleCode of the library for Intel PCH PEI Policy initialization.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "PeiPchPolicyUpdate.h"
+#include <Guid/FmpCapsule.h>
+#include <Guid/GlobalVariable.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/GpioConfig.h>
+#include <Library/HobLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/PchInfoLib.h>
+#include <Library/PchPcieRpLib.h>
+#include <Library/PeiSiPolicyUpdateLib.h>
+#include <Library/SiPolicyLib.h>
+#include <ConfigBlock.h>
+#include <Ppi/Spi.h>
+
+#include <PlatformBoardConfig.h>
+#include <PolicyUpdateMacro.h>
+#include <SerialIoDevices.h>
+
+#include <Pins/GpioPinsVer2Lp.h>
+
+#if FixedPcdGet8(PcdFspModeSelection) == 1
+#include <FspmUpd.h>
+#include <FspsUpd.h>
+#endif
+
+/**
+ This is helper function for getting I2C Pads Internal Termination settings from Pcd
+
+ @param[in] Index I2C Controller Index
+**/
+UINT8
+STATIC
+GetSerialIoI2cPadsTerminationFromPcd (
+ IN UINT8 Index
+ )
+{
+ switch (Index) {
+ case 0:
+ return PcdGet8 (PcdPchSerialIoI2c0PadInternalTerm);
+ case 1:
+ return PcdGet8 (PcdPchSerialIoI2c1PadInternalTerm);
+ case 2:
+ return PcdGet8 (PcdPchSerialIoI2c2PadInternalTerm);
+ case 3:
+ return PcdGet8 (PcdPchSerialIoI2c3PadInternalTerm);
+ case 4:
+ return PcdGet8 (PcdPchSerialIoI2c4PadInternalTerm);
+ case 5:
+ return PcdGet8 (PcdPchSerialIoI2c5PadInternalTerm);
+ case 6:
+ return PcdGet8 (PcdPchSerialIoI2c6PadInternalTerm);
+ case 7:
+ return PcdGet8 (PcdPchSerialIoI2c7PadInternalTerm);
+ default:
+ ASSERT (FALSE); // Invalid I2C Controller Index
+ }
+ return 0;
+}
+
+/**
+ This function performs PCH Serial IO Platform Policy initialization
+
+ @param[in] SiPolicy Pointer to SI_POLICY_PPI
+ @param[in] FspsUpd A VOID pointer
+**/
+VOID
+UpdateSerialIoConfig (
+ IN SI_POLICY_PPI *SiPolicy,
+ IN VOID *FspsUpd
+ )
+{
+ UINT8 Index;
+#if FixedPcdGet8(PcdFspModeSelection) == 0
+ SERIAL_IO_CONFIG *SerialIoConfig;
+ EFI_STATUS Status;
+
+ Status = GetConfigBlock ((VOID *) SiPolicy, &gSerialIoConfigGuid, (VOID *) &SerialIoConfig);
+ ASSERT_EFI_ERROR (Status);
+ if (EFI_ERROR (Status)) {
+ return;
+ }
+#endif
+
+
+ //
+ // I2C
+ //
+ for (Index = 0; Index < GetPchMaxSerialIoI2cControllersNum (); Index++) {
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.PchSerialIoI2cPadsTermination[Index], SerialIoConfig->I2cDeviceConfig[Index].PadTermination, GetSerialIoI2cPadsTerminationFromPcd (Index));
+ }
+
+ if (IsPchP ()) {
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoI2cMode[0], SerialIoConfig->I2cDeviceConfig[0].Mode, 0);
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoI2cMode[1], SerialIoConfig->I2cDeviceConfig[1].Mode, 0);
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoI2cMode[2], SerialIoConfig->I2cDeviceConfig[2].Mode, 0);
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoI2cMode[3], SerialIoConfig->I2cDeviceConfig[3].Mode, 0);
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoI2cMode[4], SerialIoConfig->I2cDeviceConfig[4].Mode, 0);
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoI2cMode[5], SerialIoConfig->I2cDeviceConfig[5].Mode, 0);
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoI2cMode[6], SerialIoConfig->I2cDeviceConfig[6].Mode, 0);
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoI2cMode[7], SerialIoConfig->I2cDeviceConfig[7].Mode, 0);
+ }
+
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoUartMode[0], SerialIoConfig->UartDeviceConfig[0].Mode, 2);
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoUartMode[1], SerialIoConfig->UartDeviceConfig[1].Mode, 0);
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoUartMode[2], SerialIoConfig->UartDeviceConfig[2].Mode, 0);
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoUartMode[3], SerialIoConfig->UartDeviceConfig[3].Mode, 0);
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoUartMode[4], SerialIoConfig->UartDeviceConfig[4].Mode, 0);
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoUartMode[5], SerialIoConfig->UartDeviceConfig[5].Mode, 0);
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoUartMode[6], SerialIoConfig->UartDeviceConfig[6].Mode, 0);
+
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoUartAutoFlow[0], SerialIoConfig->UartDeviceConfig[0].Attributes.AutoFlow, 1);
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoUartAutoFlow[1], SerialIoConfig->UartDeviceConfig[1].Attributes.AutoFlow, 1);
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoUartAutoFlow[2], SerialIoConfig->UartDeviceConfig[2].Attributes.AutoFlow, 1);
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoUartAutoFlow[3], SerialIoConfig->UartDeviceConfig[3].Attributes.AutoFlow, 0);
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoUartAutoFlow[4], SerialIoConfig->UartDeviceConfig[4].Attributes.AutoFlow, 0);
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoUartAutoFlow[5], SerialIoConfig->UartDeviceConfig[5].Attributes.AutoFlow, 0);
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoUartAutoFlow[6], SerialIoConfig->UartDeviceConfig[6].Attributes.AutoFlow, 0);
+
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoUartPowerGating[0], SerialIoConfig->UartDeviceConfig[0].PowerGating, 2);
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoUartPowerGating[1], SerialIoConfig->UartDeviceConfig[1].PowerGating, 2);
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoUartPowerGating[2], SerialIoConfig->UartDeviceConfig[2].PowerGating, 2);
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoUartPowerGating[3], SerialIoConfig->UartDeviceConfig[3].PowerGating, 0);
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoUartPowerGating[4], SerialIoConfig->UartDeviceConfig[4].PowerGating, 0);
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoUartPowerGating[5], SerialIoConfig->UartDeviceConfig[5].PowerGating, 0);
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoUartPowerGating[6], SerialIoConfig->UartDeviceConfig[6].PowerGating, 0);
+
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoUartDmaEnable[0], SerialIoConfig->UartDeviceConfig[0].DmaEnable, 1);
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoUartDmaEnable[1], SerialIoConfig->UartDeviceConfig[1].DmaEnable, 1);
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoUartDmaEnable[2], SerialIoConfig->UartDeviceConfig[2].DmaEnable, 1);
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoUartDmaEnable[3], SerialIoConfig->UartDeviceConfig[3].DmaEnable, 0);
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoUartDmaEnable[4], SerialIoConfig->UartDeviceConfig[4].DmaEnable, 0);
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoUartDmaEnable[5], SerialIoConfig->UartDeviceConfig[5].DmaEnable, 0);
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoUartDmaEnable[6], SerialIoConfig->UartDeviceConfig[6].DmaEnable, 0);
+
+}
+
+
+/**
+ Update PCIe Root Port Configuration
+
+ @param[in] SiPolicy Pointer to SI_POLICY_PPI
+ @param[in] FspsUpd Pointer to FspsUpd structure
+ // @param[in] PchSetup Pointer to PCH_SETUP buffer
+ // @param[in] SetupVariables Pointer to SETUP_DATA buffer
+**/
+VOID
+UpdatePcieRpConfig (
+ IN SI_POLICY_PPI *SiPolicy,
+ IN VOID *FspsUpd
+ )
+{
+ UINT8 Index;
+#if FixedPcdGet8(PcdFspModeSelection) == 0
+ EFI_STATUS Status;
+#endif
+#if FixedPcdGet8(PcdFspModeSelection) == 0
+ PCH_PCIE_CONFIG *PchPcieConfig;
+#endif
+ UINTN MaxPciePorts;
+
+ MaxPciePorts = GetPchMaxPciePortNum ();
+#if FixedPcdGet8(PcdFspModeSelection) == 0
+ PchPcieConfig = NULL;
+ Status = GetConfigBlock ((VOID *) SiPolicy, &gPchPcieConfigGuid, (VOID *) &PchPcieConfig);
+ ASSERT_EFI_ERROR (Status);
+ if (EFI_ERROR (Status)) {
+ return;
+ }
+#endif
+
+
+ //
+ // PCI express config
+ //
+ for (Index = 0; Index < MaxPciePorts; Index++) {
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.PcieRpMaxPayload[Index], PchPcieConfig->RootPort[Index].PcieRpCommonConfig.MaxPayload, PchPcieMaxPayload256);
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.PcieRpPhysicalSlotNumber[Index], PchPcieConfig->RootPort[Index].PcieRpCommonConfig.PhysicalSlotNumber, (UINT8) Index);
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.PcieRpClkReqDetect[Index], PchPcieConfig->RootPort[Index].PcieRpCommonConfig.ClkReqDetect, TRUE);
+ }
+}
+
+
+#if FixedPcdGet8(PcdFspModeSelection) == 1
+/**
+ Update DevInt config
+
+ @param[in] FspsUpd Pointer to FspsUpd structure
+**/
+STATIC
+VOID
+UpdateDevIntConfig (
+ IN VOID *FspsUpd
+ )
+{
+ ((FSPS_UPD *) FspsUpd)->FspsConfig.DevIntConfigPtr = (UINT32) NULL;
+}
+#endif
+
+
+
+/**
+ This function performs PCH PEI Policy initialization.
+
+ @retval EFI_SUCCESS The PPI is installed and initialized.
+ @retval EFI ERRORS The PPI is not successfully installed.
+ @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize the driver
+**/
+EFI_STATUS
+EFIAPI
+UpdatePeiPchPolicy (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+ VOID *FspsUpd;
+ SI_POLICY_PPI *SiPolicy;
+ VOID *FspmUpd;
+ SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi;
+ CPU_SECURITY_PREMEM_CONFIG *CpuSecurityPreMemConfig;
+
+ DEBUG ((DEBUG_INFO, "Update PeiPchPolicyUpdate Pos-Mem Start\n"));
+
+ FspsUpd = NULL;
+ FspmUpd = NULL;
+ SiPolicy = NULL;
+ CpuSecurityPreMemConfig = NULL;
+ SiPreMemPolicyPpi = NULL;
+
+#if FixedPcdGet8(PcdFspModeSelection) == 1
+ FspmUpd = (FSPM_UPD *) PcdGet32 (PcdFspmUpdDataAddress);
+ ASSERT (FspmUpd != NULL);
+ FspsUpd = (FSPS_UPD *) PcdGet32 (PcdFspsUpdDataAddress);
+ ASSERT (FspsUpd != NULL);
+#else
+ Status = PeiServicesLocatePpi (&gSiPolicyPpiGuid, 0, NULL, (VOID **) &SiPolicy);
+ ASSERT_EFI_ERROR (Status);
+ Status = PeiServicesLocatePpi (&gSiPreMemPolicyPpiGuid, 0, NULL, (VOID **) &SiPreMemPolicyPpi);
+ ASSERT_EFI_ERROR (Status);
+ Status = GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gCpuSecurityPreMemConfigGuid, (VOID *) &CpuSecurityPreMemConfig);
+ ASSERT_EFI_ERROR (Status);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+#endif
+
+
+#if FixedPcdGet8(PcdFspModeSelection) == 1
+ //
+ // Interrupt Config
+ //
+ UpdateDevIntConfig (FspsUpd);
+#endif
+
+ UpdatePcieRpConfig (SiPolicy, FspsUpd);
+ UpdateSerialIoConfig (SiPolicy, FspsUpd);
+
+ return EFI_SUCCESS;
+}
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiPchPolicyUpdate.h b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiPchPolicyUpdate.h
new file mode 100644
index 0000000000..54dba37e1b
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiPchPolicyUpdate.h
@@ -0,0 +1,34 @@
+/** @file
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+#ifndef _PEI_PCH_POLICY_UPDATE_H_
+#define _PEI_PCH_POLICY_UPDATE_H_
+
+//
+// External include files do NOT need to be explicitly specified in real EDKII
+// environment
+//
+#include <PiPei.h>
+#include <PlatformBoardId.h>
+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+#include <Ppi/ReadOnlyVariable2.h>
+#include <Library/PeiServicesLib.h>
+#include <Ppi/SiPolicy.h>
+#include <Library/ConfigBlockLib.h>
+#include <PlatformBoardConfig.h>
+
+//
+// Valid External Vnn Rail Configurations
+//
+typedef enum {
+ VnnRailVoltageConfig0, // 0.7V@Bypass-0.75V@Internal-1.05V@Internal
+ VnnRailVoltageConfig1, // 0.75V@Bypass-0.75V@Bypass-1.05V@Internal
+ VnnRailVoltageConfig2, // 0.7V@Bypass-0.75V@Bypass-1.05V@Internal
+ VnnRailVoltageConfig3 // 1.05V@Bypass-1.05V@Bypass-1.05V@Bypass
+} VNN_RAIL_VOLTAGE_CONFIG;
+
+#endif
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiPchPolicyUpdatePreMem.c b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiPchPolicyUpdatePreMem.c
new file mode 100644
index 0000000000..290474f76d
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiPchPolicyUpdatePreMem.c
@@ -0,0 +1,173 @@
+/** @file
+ This file is SampleCode of the library for Intel PCH PEI Policy initialization.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "PeiPchPolicyUpdate.h"
+#include <Guid/GlobalVariable.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/HobLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/PchInfoLib.h>
+#include <Library/PchPcieRpLib.h>
+#include <Library/PeiSiPolicyUpdateLib.h>
+#include <Library/SiPolicyLib.h>
+
+#include <PolicyUpdateMacro.h>
+
+#if FixedPcdGet8(PcdFspModeSelection) == 1
+#include <FspmUpd.h>
+#endif
+
+#include <Pins/GpioPinsVer2Lp.h>
+#include <PchDmiConfig.h>
+
+//
+// Sawtooth Peak
+// Single SPD EEPROM at 0xA2 serves both C0D0 and C1D0 (LPDDR is 1DPC only)
+//
+#define DIMM_SMB_SPD_P0C0D0_STP 0xA2
+#define DIMM_SMB_SPD_P0C0D1_STP 0xA0
+#define DIMM_SMB_SPD_P0C1D0_STP 0xA2
+#define DIMM_SMB_SPD_P0C1D1_STP 0xA0
+
+GLOBAL_REMOVE_IF_UNREFERENCED UINT8 mSmbusSTPRsvdAddresses[] = {
+ DIMM_SMB_SPD_P0C0D0_STP,
+ DIMM_SMB_SPD_P0C0D1_STP,
+ DIMM_SMB_SPD_P0C1D0_STP,
+ DIMM_SMB_SPD_P0C1D1_STP
+};
+
+
+
+
+VOID
+UpdatePcieClockInfo (
+ PCH_PCIE_RP_PREMEM_CONFIG *PcieRpPreMemConfig,
+ IN VOID *FspmUpd,
+ UINTN Index,
+ UINT64 Data
+ )
+{
+ PCD64_BLOB Pcd64;
+
+ Pcd64.Blob = Data;
+ DEBUG ((DEBUG_INFO, "UpdatePcieClockInfo ClkIndex %x ClkUsage %x, Supported %x\n", Index, Pcd64.PcieClock.ClockUsage, Pcd64.PcieClock.ClkReqSupported));
+
+ UPDATE_POLICY (((FSPM_UPD *)FspmUpd)->FspmConfig.PcieClkSrcUsage[Index], PcieRpPreMemConfig->PcieClock[Index].Usage, (UINT8)Pcd64.PcieClock.ClockUsage);
+ UPDATE_POLICY (((FSPM_UPD *)FspmUpd)->FspmConfig.PcieClkSrcClkReq[Index], PcieRpPreMemConfig->PcieClock[Index].ClkReq, Pcd64.PcieClock.ClkReqSupported ? (UINT8)Index : 0xFF);
+}
+
+/**
+ Update PcieRp pre mem policies.
+
+ @param[in] SiPreMemPolicy Pointer to SI_PREMEM_POLICY_PPI
+ @param[in] FspsUpm Pointer to FSPM_UPD
+ @param[in] PchSetup Pointer to PCH_SETUP
+**/
+STATIC
+VOID
+UpdatePcieRpPreMemPolicy (
+ IN SI_PREMEM_POLICY_PPI *SiPreMemPolicy,
+ IN VOID *FspmUpd
+ )
+{
+ UINT32 RpIndex;
+ UINT32 RpEnabledMask;
+ PCH_PCIE_RP_PREMEM_CONFIG *PcieRpPreMemConfig;
+#if FixedPcdGet8(PcdFspModeSelection) == 0
+ EFI_STATUS Status;
+ Status = GetConfigBlock ((VOID *) SiPreMemPolicy, &gPcieRpPreMemConfigGuid, (VOID *) &PcieRpPreMemConfig);
+ ASSERT_EFI_ERROR (Status);
+ if (EFI_ERROR (Status)) {
+ return;
+ }
+#else
+ PcieRpPreMemConfig = NULL;
+#endif
+
+ GET_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.PcieRpEnableMask, PcieRpPreMemConfig->RpEnabledMask, RpEnabledMask);
+
+ for (RpIndex = 0; RpIndex < GetPchMaxPciePortNum (); RpIndex ++) {
+ RpEnabledMask |= (UINT32) (1 << RpIndex);
+ }
+ // RpEnabledMask value is related with Setup value, Need to check Policy Default
+ COMPARE_AND_UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.PcieRpEnableMask, PcieRpPreMemConfig->RpEnabledMask, RpEnabledMask);
+
+ UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 0, PcdGet64(PcdPcieClock0));
+ UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 1, PcdGet64(PcdPcieClock1));
+ UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 2, PcdGet64(PcdPcieClock2));
+ UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 3, PcdGet64(PcdPcieClock3));
+ UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 4, PcdGet64(PcdPcieClock4));
+ UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 5, PcdGet64(PcdPcieClock5));
+ UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 6, PcdGet64(PcdPcieClock6));
+ UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 7, PcdGet64(PcdPcieClock7));
+ UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 8, PcdGet64(PcdPcieClock8));
+ UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 9, PcdGet64(PcdPcieClock9));
+ UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 10, PcdGet64(PcdPcieClock10));
+ UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 11, PcdGet64(PcdPcieClock11));
+ UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 12, PcdGet64(PcdPcieClock12));
+ UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 13, PcdGet64(PcdPcieClock13));
+ UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 14, PcdGet64(PcdPcieClock14));
+ UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 15, PcdGet64(PcdPcieClock15));
+ UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 16, PcdGet64(PcdPcieClock16));
+ UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 17, PcdGet64(PcdPcieClock17));
+
+}
+
+/**
+ Update Dmi Pre Mem policies.
+
+ @param[in] SiPreMemPolicy Pointer to SI_PREMEM_POLICY_PPI
+ @param[in] FspmUpd Pointer to FSPM_UPD
+**/
+STATIC
+VOID
+UpdateDmiPreMemPolicy (
+ IN SI_PREMEM_POLICY_PPI *SiPreMemPolicy,
+ IN VOID *FspmUpd
+ )
+{
+ return;
+}
+
+/**
+ This function performs PCH PEI Policy initialization.
+
+ @retval EFI_SUCCESS The PPI is installed and initialized.
+ @retval EFI ERRORS The PPI is not successfully installed.
+ @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize the driver
+**/
+EFI_STATUS
+EFIAPI
+UpdatePeiPchPolicyPreMem (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+ VOID *FspmUpd;
+ SI_PREMEM_POLICY_PPI *SiPreMemPolicy;
+
+ DEBUG ((DEBUG_INFO, "Update PeiPchPolicyUpdate Pre-Mem Start\n"));
+
+ FspmUpd = NULL;
+ SiPreMemPolicy = NULL;
+
+#if FixedPcdGet8(PcdFspModeSelection) == 1
+ FspmUpd = (FSPM_UPD *) PcdGet32 (PcdFspmUpdDataAddress);
+ ASSERT (FspmUpd != NULL);
+#else
+ Status = PeiServicesLocatePpi (&gSiPreMemPolicyPpiGuid, 0, NULL, (VOID **) &SiPreMemPolicy);
+ ASSERT_EFI_ERROR (Status);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+#endif
+
+ UpdatePcieRpPreMemPolicy (SiPreMemPolicy, FspmUpd);
+ return EFI_SUCCESS;
+}
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiPolicyUpdateLib.inf b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiPolicyUpdateLib.inf
new file mode 100644
index 0000000000..a02093054d
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiPolicyUpdateLib.inf
@@ -0,0 +1,225 @@
+### @file
+# Module Information file for PEI PolicyUpdateLib Library
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+###
+
+[Defines]
+ INF_VERSION = 0x00010017
+ BASE_NAME = PeiPolicyUpdateLib
+ FILE_GUID = D42F5BB8-E0CE-47BD-8C52-476C79055FC6
+ VERSION_STRING = 1.0
+ MODULE_TYPE = PEIM
+ LIBRARY_CLASS = PeiPolicyUpdateLib|PEIM PEI_CORE SEC
+
+[LibraryClasses]
+ HobLib
+ BaseCryptLib
+ CpuPlatformLib
+ IoLib
+ ConfigBlockLib
+ MemoryAllocationLib
+ PeiServicesTablePointerLib
+ PcdLib
+ Tpm2CommandLib
+ Tpm12CommandLib
+ Tpm2DeviceLib
+ Tpm12DeviceLib
+ BoardConfigLib
+ PciSegmentLib
+ SiPolicyLib
+ PeiServicesLib
+ FirmwareBootMediaLib
+ SpiLib
+ BmpSupportLib
+ PeiGetFvInfoLib
+ TimerLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ UefiCpuPkg/UefiCpuPkg.dec
+ IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec
+ AlderlakeSiliconPkg/SiPkg.dec
+ SecurityPkg/SecurityPkg.dec
+ CryptoPkg/CryptoPkg.dec
+ IntelSiliconPkg/IntelSiliconPkg.dec
+ AlderlakeOpenBoardPkg/OpenBoardPkg.dec
+ MinPlatformPkg/MinPlatformPkg.dec
+ BoardModulePkg/BoardModulePkg.dec
+
+[FixedPcd]
+ gBoardModuleTokenSpaceGuid.PcdDefaultBoardId ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdFlashFvFirmwareBinariesBase ## CONSUMES
+ gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageSize ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdMicrocodeOffsetInFv ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiAcpiNvsMemorySize ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiAcpiReclaimMemorySize ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiReservedMemorySize ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtCodeMemorySize ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtDataMemorySize ## CONSUMES
+ gSiPkgTokenSpaceGuid.PcdAdlLpSupport ## CONSUMES
+ gSiPkgTokenSpaceGuid.PcdBiosSize ## CONSUMES
+ gSiPkgTokenSpaceGuid.PcdTsegSize ## CONSUMES
+
+[Pcd]
+ gSiPkgTokenSpaceGuid.PcdMchBaseAddress ## CONSUMES
+ gSiPkgTokenSpaceGuid.PcdSmbusBaseAddress ## CONSUMES
+ gPlatformModuleTokenSpaceGuid.PcdDmiBaseAddress ## CONSUMES
+ gPlatformModuleTokenSpaceGuid.PcdEpBaseAddress ## CONSUMES
+ gPlatformModuleTokenSpaceGuid.PcdGttMmAddress ## CONSUMES
+ gPlatformModuleTokenSpaceGuid.PcdGmAdrAddress ## CONSUMES
+ gPlatformModuleTokenSpaceGuid.PcdEdramBaseAddress ## CONSUMES
+
+ gBoardModuleTokenSpaceGuid.PcdSaDdrFreqLimit ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdBoardPmcPdEnable ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdBoardId ## CONSUMES
+
+ # SA Misc Config
+ gBoardModuleTokenSpaceGuid.PcdSaMiscUserBd ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdSaMiscMmioSizeAdjustment ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdMrcRcompResistor ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdMrcRcompTarget ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdMrcDqByteMap ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdMrcDqByteMapSize ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdMrcDqsMapCpu2Dram ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdMrcDqsMapCpu2DramSize ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdMrcDqMapCpu2Dram ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdMrcDqMapCpu2DramSize ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdMrcDqPinsInterleavedControl ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdMrcDqPinsInterleaved ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdData ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdDataSize ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdMrcLp5CccConfig ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdMrcCmdMirror ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdSaMiscFirstDimmBitMask ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdSaMiscFirstDimmBitMaskEcc ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdSaMiscDisableMrcRetrainingOnRtcPowerLoss ## CONSUMES
+
+ # Display DDI
+ gBoardModuleTokenSpaceGuid.PcdSaDisplayConfigTable ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdSaDisplayConfigTableSize ## CONSUMES
+
+ # PCIE RTD3 GPIO
+ gBoardModuleTokenSpaceGuid.PcdRootPortIndex ## CONSUMES
+
+ gBoardModuleTokenSpaceGuid.PcdPcieSlot1GpioSupport ## CONSUMES
+
+ # SPD Address Table
+ gBoardModuleTokenSpaceGuid.PcdSpdPresent ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable0 ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable1 ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable2 ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable3 ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable4 ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable5 ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable6 ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable7 ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable8 ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable9 ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable10 ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable11 ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable12 ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable13 ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable14 ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable15 ## CONSUMES
+
+
+ # PCIe Clock Info
+ gBoardModuleTokenSpaceGuid.PcdPcieClock0 ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdPcieClock1 ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdPcieClock2 ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdPcieClock3 ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdPcieClock4 ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdPcieClock5 ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdPcieClock6 ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdPcieClock7 ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdPcieClock8 ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdPcieClock9 ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdPcieClock10 ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdPcieClock11 ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdPcieClock12 ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdPcieClock13 ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdPcieClock14 ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdPcieClock15 ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdPcieClock16 ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdPcieClock17 ## CONSUMES
+
+
+ # Pch SerialIo I2c Pads Termination
+ gBoardModuleTokenSpaceGuid.PcdPchSerialIoI2c0PadInternalTerm ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdPchSerialIoI2c1PadInternalTerm ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdPchSerialIoI2c2PadInternalTerm ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdPchSerialIoI2c3PadInternalTerm ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdPchSerialIoI2c4PadInternalTerm ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdPchSerialIoI2c5PadInternalTerm ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdPchSerialIoI2c6PadInternalTerm ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdPchSerialIoI2c7PadInternalTerm ## CONSUMES
+
+ gIntelSiliconPkgTokenSpaceGuid.PcdIntelGraphicsVbtFileGuid ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdSmbusAlertEnable ## CONSUMES
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber ## CONSUMES
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress ## CONSUMES
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdPolicyCheckIsFirstBoot ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdPolicyCheckIsRvpSupport ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdPolicyCheckPcdInitDone ## CONSUMES
+ gPlatformModuleTokenSpaceGuid.PcdExtendedBiosRegionSupport ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdFlashExtendRegionSizeInUse ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdBoardGpioTablePreMem ## CONSUMES
+
+[Sources]
+ PeiPchPolicyUpdatePreMem.c
+ PeiPchPolicyUpdate.c
+ PeiCpuPolicyUpdatePreMem.c
+ PeiCpuPolicyUpdate.c
+ PeiMePolicyUpdatePreMem.c
+ PeiMePolicyUpdate.c
+ PeiSaPolicyUpdate.c
+ PeiSaPolicyUpdatePreMem.c
+ PeiSiPolicyUpdate.c
+
+[Ppis]
+ gEfiPeiReadOnlyVariable2PpiGuid ## CONSUMES
+ gWdtPpiGuid ## CONSUMES
+ gPchSpiPpiGuid ## CONSUMES
+ gSiPolicyPpiGuid ## CONSUMES
+ gSiPreMemPolicyPpiGuid ## CONSUMES
+ gFspmArchConfigPpiGuid ## PRODUCES
+ gReadyForGopConfigPpiGuid ## PRODUCES
+ gPeiGraphicsPlatformPpiGuid ## CONSUMES
+ gPeiGraphicsFramebufferReadyPpiGuid ## CONSUMES
+
+[Guids]
+ gEfiGlobalVariableGuid ## CONSUMES
+ gMemoryConfigVariableGuid ## CONSUMES
+ gS3MemoryVariableGuid ## CONSUMES
+ gEfiCapsuleVendorGuid ## CONSUMES
+ gEfiMemoryTypeInformationGuid ## CONSUMES
+ gEfiMemoryOverwriteControlDataGuid ## CONSUMES
+ gDebugConfigVariableGuid ## CONSUMES
+ gSiPreMemConfigGuid ## CONSUMES
+ gSiConfigGuid ## CONSUMES
+ gCpuSecurityPreMemConfigGuid ## CONSUMES
+ gCpuConfigLibPreMemConfigGuid ## CONSUMES
+ gCpuConfigGuid ## CONSUMES
+ gVmdPeiConfigGuid ## CONSUMES
+ gCpuPcieRpPrememConfigGuid ## CONSUMES
+ gVmdInfoHobGuid ## CONSUMES
+ gPciePreMemConfigGuid ## CONSUMES
+ gPlatformInitFvLocationGuid ## CONSUMES
+ gHostBridgePeiPreMemConfigGuid ## CONSUMES
+ gEfiVmdFeatureVariableGuid ## CONSUMES
+ gEfiGraphicsInfoHobGuid ## CONSUMES
+ gPchDmiPreMemConfigGuid ## CONSUMES
+ gGraphicsPeiConfigGuid ## CONSUMES
+ gMemoryConfigGuid ## CONSUMES
+ gMemoryConfigNoCrcGuid ## CONSUMES
+ gPchPcieConfigGuid ## CONSUMES
+ gSerialIoConfigGuid ## CONSUMES
+ gPcieRpPreMemConfigGuid ## CONSUMES
\ No newline at end of file
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiSaPolicyUpdate.c b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiSaPolicyUpdate.c
new file mode 100644
index 0000000000..659da2f296
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiSaPolicyUpdate.c
@@ -0,0 +1,293 @@
+/** @file
+Do Platform Stage System Agent initialization.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "PeiSaPolicyUpdate.h"
+#include <Library/BaseMemoryLib.h>
+#include <Library/BmpSupportLib.h>
+#include <Library/CpuPcieInfoFruLib.h>
+#include <Library/HobLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/PeiGetFvInfoLib.h>
+#include <Library/PeiSiPolicyUpdateLib.h>
+#include <Library/SiPolicyLib.h>
+#include <Pi/PiFirmwareFile.h>
+#include <Protocol/GraphicsOutput.h>
+
+#include <CpuPcieConfig.h>
+#include <CpuPcieHob.h>
+#include <IndustryStandard/Bmp.h>
+#include <Platform.h>
+#include <PolicyUpdateMacro.h>
+#include <Guid/GraphicsInfoHob.h>
+
+#include <VmdPeiConfig.h>
+#if FixedPcdGet8(PcdFspModeSelection) == 1
+#include <FspsUpd.h>
+#endif
+
+#include <Ppi/GraphicsPlatformPolicyPpi.h>
+
+
+#if FixedPcdGet8(PcdFspModeSelection) == 0
+EFI_STATUS
+EFIAPI
+PeiGraphicsPolicyUpdateCallback (
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
+ IN VOID *Ppi
+ )
+{
+ EFI_STATUS Status;
+ EFI_PEI_GRAPHICS_INFO_HOB *PlatformGraphicsOutput;
+ EFI_PEI_HOB_POINTERS Hob;
+ UINT8 *HobStart;
+#if FixedPcdGet8(PcdFspModeSelection) == 1
+ VOID *FspsUpd;
+#else
+ GRAPHICS_PEI_CONFIG *GtConfig;
+ SI_POLICY_PPI *SiPolicyPpi;
+#endif
+
+ DEBUG ((DEBUG_INFO, "%a: Entry\n",__FUNCTION__));
+
+ PlatformGraphicsOutput = NULL;
+ HobStart = NULL;
+
+#if FixedPcdGet8(PcdFspModeSelection) == 1
+ FspsUpd = NULL;
+ FspsUpd = (FSPS_UPD *) PcdGet32 (PcdFspsUpdDataAddress);
+ ASSERT (FspsUpd != NULL);
+#else
+ GtConfig = NULL;
+ SiPolicyPpi = NULL;
+ Status = PeiServicesLocatePpi (&gSiPolicyPpiGuid, 0, NULL, (VOID **) &SiPolicyPpi);
+ ASSERT_EFI_ERROR(Status);
+
+ Status = GetConfigBlock ((VOID *) SiPolicyPpi, &gGraphicsPeiConfigGuid, (VOID *) &GtConfig);
+ ASSERT_EFI_ERROR(Status);
+#endif
+
+ Status = PeiServicesGetHobList ((VOID **) &Hob.Raw);
+ HobStart = Hob.Raw;
+
+ if (!EFI_ERROR (Status)) {
+ if (HobStart != NULL) {
+ if ((Hob.Raw = GetNextGuidHob (&gEfiGraphicsInfoHobGuid, HobStart)) != NULL) {
+ DEBUG ((DEBUG_INFO, "Found EFI_PEI_GRAPHICS_INFO_HOB\n"));
+ PlatformGraphicsOutput = GET_GUID_HOB_DATA (Hob.Guid);
+ }
+ }
+ }
+
+ if (PlatformGraphicsOutput != NULL) {
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.HorizontalResolution, GtConfig->HorizontalResolution, PlatformGraphicsOutput->GraphicsMode.HorizontalResolution);
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.VerticalResolution, GtConfig->VerticalResolution, PlatformGraphicsOutput->GraphicsMode.VerticalResolution);
+ } else {
+ DEBUG ((DEBUG_INFO, "Not able to find EFI_PEI_GRAPHICS_INFO_HOB\n"));
+ }
+
+ DEBUG((DEBUG_INFO, "%a: Exit\n", __FUNCTION__));
+ return Status;
+}
+
+STATIC
+EFI_PEI_NOTIFY_DESCRIPTOR mPeiGfxPolicyUpdateNotifyList = {
+ (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
+ &gPeiGraphicsFramebufferReadyPpiGuid,
+ PeiGraphicsPolicyUpdateCallback
+};
+#endif
+
+#if FixedPcdGet8(PcdFspModeSelection) == 1
+#if FixedPcdGetBool(PcdAdlLpSupport) == 1
+EFI_STATUS
+EFIAPI
+PeiGraphicsPlatformPolicyNotifyCallback (
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
+ IN VOID *Ppi
+ )
+{
+ EFI_STATUS Status;
+ VOID *FspsUpd;
+ PEI_GRAPHICS_PLATFORM_POLICY_PPI *GfxPlatformPolicyPpi;
+ LID_STATUS CurrentLidStatus;
+
+ DEBUG ((DEBUG_INFO, "PeiGraphicsPlatformPolicyNotifyCallback Entry\n"));
+
+ FspsUpd = (FSPS_UPD *) PcdGet32 (PcdFspsUpdDataAddress);
+ ASSERT (FspsUpd != NULL);
+ ///
+ /// Locate GfxPlatformPolicyPpi
+ ///
+ Status = PeiServicesLocatePpi (&gPeiGraphicsPlatformPpiGuid, 0, NULL, (VOID *) &GfxPlatformPolicyPpi);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_WARN, "Failed to locate GfxPlatformPolicyPpi.\n"));
+ ASSERT_EFI_ERROR(Status);
+ }
+
+ Status = GfxPlatformPolicyPpi->GetPlatformLidStatus (&CurrentLidStatus);
+ ASSERT_EFI_ERROR (Status);
+ ((FSPS_UPD *) FspsUpd)->FspsConfig.LidStatus = (UINT8) CurrentLidStatus;
+ DEBUG ((DEBUG_INFO, "LidStatus from GetPlatformLidStatus is 0x%x\n", ((FSPS_UPD *) FspsUpd)->FspsConfig.LidStatus));
+ DEBUG ((DEBUG_INFO, "PeiGraphicsPlatformPolicyNotifyCallback Exit\n"));
+
+ return Status;
+}
+
+STATIC
+EFI_PEI_NOTIFY_DESCRIPTOR mPeiGfxPlatformPolicyNotifyList = {
+ (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
+ &gPeiGraphicsPlatformPpiGuid,
+ PeiGraphicsPlatformPolicyNotifyCallback
+};
+#endif
+#endif
+
+
+/**
+ UpdatePeiSaPolicy performs SA PEI Policy initialization
+
+ @retval EFI_SUCCESS The policy is installed and initialized.
+**/
+EFI_STATUS
+EFIAPI
+UpdatePeiSaPolicy (
+ VOID
+ )
+{
+ EFI_GUID BmpImageGuid;
+ EFI_STATUS Status;
+ EFI_GUID FileGuid;
+ VOID *Buffer;
+ UINT32 Size;
+ EFI_BOOT_MODE BootMode;
+ VOID *VmdVariablePtr;
+ GRAPHICS_PEI_CONFIG *GtConfig;
+ SI_POLICY_PPI *SiPolicyPpi;
+ CPU_PCIE_CONFIG *CpuPcieRpConfig;
+ VMD_PEI_CONFIG *VmdPeiConfig;
+ EFI_PEI_PPI_DESCRIPTOR *ReadyForGopConfigPpiDesc;
+ VOID *VbtPtr;
+ EFI_GRAPHICS_OUTPUT_BLT_PIXEL *Blt;
+ UINTN BltSize;
+ UINTN Height;
+ UINTN Width;
+
+ DEBUG ((DEBUG_INFO, "Update PeiSaPolicyUpdate Pos-Mem Start\n"));
+
+ Size = 0;
+ Blt = NULL;
+ BltSize = 0;
+
+ GtConfig = NULL;
+ SiPolicyPpi = NULL;
+ CpuPcieRpConfig = NULL;
+ VmdVariablePtr = NULL;
+ Buffer = NULL;
+
+ Status = PeiServicesLocatePpi (&gSiPolicyPpiGuid, 0, NULL, (VOID **) &SiPolicyPpi);
+ ASSERT_EFI_ERROR (Status);
+
+ Status = GetConfigBlock ((VOID *) SiPolicyPpi, &gGraphicsPeiConfigGuid, (VOID *) &GtConfig);
+ ASSERT_EFI_ERROR(Status);
+
+
+
+ VmdPeiConfig = NULL;
+ Status = GetConfigBlock ((VOID *) SiPolicyPpi, &gVmdPeiConfigGuid, (VOID *) &VmdPeiConfig);
+ ASSERT_EFI_ERROR(Status);
+
+ Status = PeiServicesGetBootMode (&BootMode);
+ ASSERT_EFI_ERROR (Status);
+
+ CopyMem(&BmpImageGuid, PcdGetPtr(PcdIntelGraphicsVbtFileGuid), sizeof(BmpImageGuid));
+
+
+ if (!EFI_ERROR (Status)) {
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SkipFspGop, GtConfig->SkipFspGop, 0x0);
+
+
+ Buffer = NULL;
+
+ CopyMem(&FileGuid, &BmpImageGuid, sizeof(FileGuid));
+ PeiGetSectionFromFv(FileGuid, &Buffer, &Size);
+ if (Buffer == NULL) {
+ DEBUG((DEBUG_ERROR, "Could not locate VBT\n"));
+ }
+
+ if (BootMode == BOOT_ON_S3_RESUME) {
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.GraphicsConfigPtr, GtConfig->GraphicsConfigPtr, NULL);
+ } else {
+ GtConfig->GraphicsConfigPtr = Buffer;
+ DEBUG ((DEBUG_INFO, "Vbt Pointer from PeiGetSectionFromFv is 0x%x\n", GtConfig->GraphicsConfigPtr));
+ }
+ DEBUG ((DEBUG_INFO, "Vbt Size from PeiGetSectionFromFv is 0x%x\n", Size));
+ GET_POLICY ((VOID *) ((FSPS_UPD *) FspsUpd)->FspsConfig.GraphicsConfigPtr, GtConfig->GraphicsConfigPtr, VbtPtr);
+
+ //
+ // Install ReadyForGopConfig PPI to trigger PEI phase GopConfig callback.
+ //
+ ReadyForGopConfigPpiDesc = (EFI_PEI_PPI_DESCRIPTOR *) AllocateZeroPool (sizeof (EFI_PEI_PPI_DESCRIPTOR));
+ if (ReadyForGopConfigPpiDesc == NULL) {
+ ASSERT (FALSE);
+ return EFI_OUT_OF_RESOURCES;
+ }
+ ReadyForGopConfigPpiDesc->Flags = EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST;
+ ReadyForGopConfigPpiDesc->Guid = &gReadyForGopConfigPpiGuid;
+ ReadyForGopConfigPpiDesc->Ppi = VbtPtr;
+ Status = PeiServicesInstallPpi (ReadyForGopConfigPpiDesc);
+
+
+ Status = TranslateBmpToGopBlt (
+ Buffer,
+ Size,
+ &Blt,
+ &BltSize,
+ &Height,
+ &Width
+ );
+
+ if (Status == EFI_BUFFER_TOO_SMALL) {
+ Blt = NULL;
+ Status = TranslateBmpToGopBlt (
+ Buffer,
+ Size,
+ &Blt,
+ &BltSize,
+ &Height,
+ &Width
+ );
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "TranslateBmpToGopBlt, Status = %r\n", Status));
+ ASSERT_EFI_ERROR (Status);
+ return Status;
+ }
+ }
+
+ //
+ // Initialize Blt, BltSize
+ //
+ GtConfig->BltBufferAddress = Blt;
+
+ UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.BltBufferSize, GtConfig->BltBufferSize, BltSize);
+
+ DEBUG ((DEBUG_INFO, "Calling mPeiGfxPolicyUpdateNotifyList\n"));
+ Status = PeiServicesNotifyPpi (&mPeiGfxPolicyUpdateNotifyList);
+
+ }
+
+ //
+ // VMD related settings from setup variable
+ //
+ COMPARE_AND_UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.VmdEnable, VmdPeiConfig->VmdEnable, 0);
+ VmdPeiConfig->VmdVariablePtr = VmdVariablePtr;
+ DEBUG ((DEBUG_INFO, "VmdVariablePtr from PeiGetSectionFromFv is 0x%x\n", VmdVariablePtr));
+
+ return EFI_SUCCESS;
+}
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiSaPolicyUpdate.h b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiSaPolicyUpdate.h
new file mode 100644
index 0000000000..c2b24ad5e8
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiSaPolicyUpdate.h
@@ -0,0 +1,47 @@
+/** @file
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+#ifndef _PEI_SA_POLICY_UPDATE_H_
+#define _PEI_SA_POLICY_UPDATE_H_
+
+//
+// External include files do NOT need to be explicitly specified in real EDKII
+// environment
+//
+#include <Ppi/SiPolicy.h>
+#include <Library/DebugPrintErrorLevelLib.h>
+#include <Ppi/Wdt.h>
+#include <CpuRegs.h>
+#include <Library/CpuPlatformLib.h>
+#include "PeiPchPolicyUpdate.h"
+#include <Library/PcdLib.h>
+#include <Library/PciSegmentLib.h>
+#include <Library/SiPolicyLib.h>
+#if FixedPcdGet8(PcdFspModeSelection) == 1
+#include <FspmUpd.h>
+#include <FspsUpd.h>
+#endif
+
+///
+/// DIMM SMBus addresses for Haddock Creek
+///
+
+//
+// Sawtooth Peak
+// Single SPD EEPROM at 0xA2 serves both C0D0 and C1D0 (LPDDR is 1DPC only)
+//
+#define DIMM_SMB_SPD_P0C0D0_STP 0xA2
+#define DIMM_SMB_SPD_P0C0D1_STP 0xA0
+#define DIMM_SMB_SPD_P0C1D0_STP 0xA2
+#define DIMM_SMB_SPD_P0C1D1_STP 0xA0
+
+
+#define WDT_TIMEOUT 60
+
+// BClk Frequency Limitations (in Hz)
+
+#endif
+
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiSaPolicyUpdatePreMem.c b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiSaPolicyUpdatePreMem.c
new file mode 100644
index 0000000000..2c98cbccd4
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiSaPolicyUpdatePreMem.c
@@ -0,0 +1,502 @@
+/** @file
+Do Platform Stage System Agent initialization.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "PeiSaPolicyUpdate.h"
+#include "MemoryConfig.h"
+#include <Guid/MemoryOverwriteControl.h>
+#include <Guid/MemoryTypeInformation.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/CpuPcieInfoFruLib.h>
+#include <Library/CpuPlatformLib.h>
+#include <Library/GpioLib.h>
+#include <Library/HobLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/PeiSiPolicyUpdateLib.h>
+#include <Library/SiPolicyLib.h>
+#include <Register/CommonMsr.h>
+#include <Register/Cpuid.h>
+#include <Register/Msr.h>
+#include <CpuRegs.h>
+#include <HostBridgeConfig.h>
+#include <Platform.h>
+#include <PlatformBoardConfig.h>
+#include <PolicyUpdateMacro.h>
+#include <SaDataHob.h>
+
+#if FixedPcdGet8(PcdFspModeSelection) == 1
+#include <FspmUpd.h>
+#else
+#include <Ppi/FspmArchConfigPpi.h>
+#endif
+
+
+///
+///
+
+///
+/// Memory Reserved should be between 125% to 150% of the Current required memory
+/// otherwise BdsMisc.c would do a reset to make it 125% to avoid s4 resume issues.
+///
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_MEMORY_TYPE_INFORMATION mDefaultMemoryTypeInformation[] = {
+ { EfiACPIReclaimMemory, FixedPcdGet32 (PcdPlatformEfiAcpiReclaimMemorySize) }, // ASL
+ { EfiACPIMemoryNVS, FixedPcdGet32 (PcdPlatformEfiAcpiNvsMemorySize) }, // ACPI NVS (including S3 related)
+ { EfiReservedMemoryType, FixedPcdGet32 (PcdPlatformEfiReservedMemorySize) }, // BIOS Reserved (including S3 related)
+ { EfiRuntimeServicesData, FixedPcdGet32 (PcdPlatformEfiRtDataMemorySize) }, // Runtime Service Data
+ { EfiRuntimeServicesCode, FixedPcdGet32 (PcdPlatformEfiRtCodeMemorySize) }, // Runtime Service Code
+ { EfiMaxMemoryType, 0 }
+};
+
+
+/**
+ UpdatePeiSaPolicyPreMem performs SA PEI Policy initialization
+
+ @retval EFI_SUCCESS The policy is installed and initialized.
+**/
+EFI_STATUS
+EFIAPI
+UpdatePeiSaPolicyPreMem (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+
+ EFI_PEI_READ_ONLY_VARIABLE2_PPI *VariableServices;
+
+ UINTN VariableSize;
+#if FixedPcdGet8(PcdFspModeSelection) == 0
+ SA_MEMORY_RCOMP *RcompData;
+#endif
+ WDT_PPI *gWdtPei;
+ UINT8 WdtTimeout;
+
+ UINT8 Index;
+ UINTN DataSize;
+ EFI_MEMORY_TYPE_INFORMATION MemoryData[EfiMaxMemoryType + 1];
+ EFI_BOOT_MODE BootMode;
+ UINT8 MorControl;
+ UINT64 PlatformMemorySize;
+ VOID *MemorySavedData;
+ VOID *NullSpdPtr;
+ UINT32 RpEnabledMask;
+
+#if FixedPcdGet8(PcdFspModeSelection) == 1
+ VOID *FspmUpd;
+ VOID *MemorySpdPtr000;
+ VOID *MemorySpdPtr010;
+ VOID *MemorySpdPtr020;
+ VOID *MemorySpdPtr030;
+ VOID *MemorySpdPtr100;
+ VOID *MemorySpdPtr110;
+ VOID *MemorySpdPtr120;
+ VOID *MemorySpdPtr130;
+#else
+ SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi;
+ MEMORY_CONFIGURATION *MemConfig;
+ SA_MISC_PEI_PREMEM_CONFIG *MiscPeiPreMemConfig;
+ MEMORY_CONFIG_NO_CRC *MemConfigNoCrc;
+ EFI_PEI_PPI_DESCRIPTOR *FspmArchConfigPpiDesc;
+ FSPM_ARCH_CONFIG_PPI *FspmArchConfigPpi;
+ HOST_BRIDGE_PREMEM_CONFIG *HostBridgePreMemConfig;
+#endif
+ UINT16 AdjustedMmioSize;
+ UINT8 SaDisplayConfigTable[16];
+ EFI_BOOT_MODE SysBootMode;
+ UINT32 ProcessorTraceTotalMemSize;
+ CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX Ebx;
+ UINT32 CapsuleSupportMemSize;
+
+ DEBUG ((DEBUG_INFO, "Update PeiSaPolicyUpdate Pre-Mem Start\n"));
+ ZeroMem ((VOID*) SaDisplayConfigTable, sizeof (SaDisplayConfigTable));
+ WdtTimeout = 0;
+ SysBootMode = 0;
+#if FixedPcdGet8(PcdFspModeSelection) == 0
+ RcompData = NULL;
+#endif
+ PlatformMemorySize = 0;
+ RpEnabledMask = 0;
+#if FixedPcdGet8(PcdFspModeSelection) == 1
+ FspmUpd = NULL;
+ MemorySpdPtr000 = NULL;
+ MemorySpdPtr010 = NULL;
+ MemorySpdPtr020 = NULL;
+ MemorySpdPtr030 = NULL;
+ MemorySpdPtr100 = NULL;
+ MemorySpdPtr110 = NULL;
+ MemorySpdPtr120 = NULL;
+ MemorySpdPtr130 = NULL;
+#else
+ SiPreMemPolicyPpi = NULL;
+ MemConfig = NULL;
+ MemConfigNoCrc = NULL;
+
+
+ MiscPeiPreMemConfig = NULL;
+ HostBridgePreMemConfig = NULL;
+ FspmArchConfigPpi = NULL;
+#endif
+
+ ProcessorTraceTotalMemSize = 0;
+ CapsuleSupportMemSize = 0;
+
+ AdjustedMmioSize = PcdGet16 (PcdSaMiscMmioSizeAdjustment);
+
+#if FixedPcdGet8(PcdFspModeSelection) == 1
+ FspmUpd = (FSPM_UPD *) PcdGet32 (PcdFspmUpdDataAddress);
+ ASSERT (FspmUpd != NULL);
+#else
+ Status = PeiServicesLocatePpi (&gSiPreMemPolicyPpiGuid, 0, NULL, (VOID **) &SiPreMemPolicyPpi);
+ ASSERT_EFI_ERROR (Status);
+
+ Status = GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gHostBridgePeiPreMemConfigGuid, (VOID *) &HostBridgePreMemConfig);
+ ASSERT_EFI_ERROR (Status);
+
+ Status = GetConfigBlock((VOID *) SiPreMemPolicyPpi, &gSaMiscPeiPreMemConfigGuid, (VOID *) &MiscPeiPreMemConfig);
+ ASSERT_EFI_ERROR(Status);
+
+ Status = GetConfigBlock((VOID *) SiPreMemPolicyPpi, &gMemoryConfigGuid, (VOID *) &MemConfig);
+ ASSERT_EFI_ERROR(Status);
+
+ Status = GetConfigBlock((VOID *) SiPreMemPolicyPpi, &gMemoryConfigNoCrcGuid, (VOID *) &MemConfigNoCrc);
+ ASSERT_EFI_ERROR(Status);
+
+#endif
+
+#if FixedPcdGet8(PcdFspModeSelection) == 0
+ RcompData = MemConfigNoCrc->RcompData;
+#endif
+
+ //
+ // Locate system configuration variable
+ //
+ Status = PeiServicesLocatePpi(
+ &gEfiPeiReadOnlyVariable2PpiGuid, // GUID
+ 0, // INSTANCE
+ NULL, // EFI_PEI_PPI_DESCRIPTOR
+ (VOID **) &VariableServices // PPI
+ );
+ ASSERT_EFI_ERROR(Status);
+
+ Status = PeiServicesGetBootMode (&BootMode);
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Initialize S3 Data variable (S3DataPtr)
+ //
+ VariableSize = 0;
+ MemorySavedData = NULL;
+ Status = VariableServices->GetVariable (
+ VariableServices,
+ L"MemoryConfig",
+ &gMemoryConfigVariableGuid,
+ NULL,
+ &VariableSize,
+ MemorySavedData
+ );
+ if (Status == EFI_BUFFER_TOO_SMALL) {
+ MemorySavedData = AllocateZeroPool (VariableSize);
+ ASSERT (MemorySavedData != NULL);
+
+ Status = VariableServices->GetVariable (
+ VariableServices,
+ L"MemoryConfig",
+ &gMemoryConfigVariableGuid,
+ NULL,
+ &VariableSize,
+ MemorySavedData
+ );
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "Fail to retrieve Variable: MemoryConfig, Status = %r\n", Status));
+ ASSERT_EFI_ERROR (Status);
+ }
+ }
+#if FixedPcdGet8(PcdFspModeSelection) == 0
+ FspmArchConfigPpi = (FSPM_ARCH_CONFIG_PPI *) AllocateZeroPool (sizeof (FSPM_ARCH_CONFIG_PPI));
+ if (FspmArchConfigPpi == NULL) {
+ ASSERT (FALSE);
+ return EFI_OUT_OF_RESOURCES;
+ }
+ FspmArchConfigPpi->Revision = 1;
+ FspmArchConfigPpi->NvsBufferPtr = MemorySavedData;
+ MiscPeiPreMemConfig->S3DataPtr = MemorySavedData;
+
+ FspmArchConfigPpiDesc = (EFI_PEI_PPI_DESCRIPTOR *) AllocateZeroPool (sizeof (EFI_PEI_PPI_DESCRIPTOR));
+ if (FspmArchConfigPpiDesc == NULL) {
+ ASSERT (FALSE);
+ return EFI_OUT_OF_RESOURCES;
+ }
+ FspmArchConfigPpiDesc->Flags = EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST;
+ FspmArchConfigPpiDesc->Guid = &gFspmArchConfigPpiGuid;
+ FspmArchConfigPpiDesc->Ppi = FspmArchConfigPpi;
+
+ //
+ // Install FSP-M Arch Config PPI
+ //
+ Status = PeiServicesInstallPpi (FspmArchConfigPpiDesc);
+ ASSERT_EFI_ERROR (Status);
+
+#else
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmArchUpd.NvsBufferPtr, MiscPeiPreMemConfig->S3DataPtr, MemorySavedData);
+#endif
+
+ VariableSize = sizeof (MorControl);
+ Status = VariableServices->GetVariable(
+ VariableServices,
+ MEMORY_OVERWRITE_REQUEST_VARIABLE_NAME,
+ &gEfiMemoryOverwriteControlDataGuid,
+ NULL,
+ &VariableSize,
+ &MorControl
+ );
+ if (EFI_ERROR (Status)) {
+ MorControl = 0;
+ }
+
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.UserBd, MiscPeiPreMemConfig->UserBd, 0); // It's a CRB mobile board by default (btCRBMB)
+
+#if (FixedPcdGet8(PcdFspModeSelection) == 0)
+ MiscPeiPreMemConfig->TxtImplemented = 0;
+#endif
+
+
+ if (PcdGet32 (PcdMrcRcompTarget)) {
+ COPY_POLICY ((VOID *)((FSPM_UPD *) FspmUpd)->FspmConfig.RcompTarget, (VOID *)RcompData->RcompTarget, (VOID *)(UINTN)PcdGet32 (PcdMrcRcompTarget), sizeof (UINT16) * MRC_MAX_RCOMP_TARGETS);
+ }
+
+ if (PcdGetBool (PcdMrcDqPinsInterleavedControl)) {
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.DqPinsInterleaved, MemConfig->DqPinsInterleaved, PcdGetBool (PcdMrcDqPinsInterleaved));
+ }
+
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.SpdAddressTable[0], MiscPeiPreMemConfig->SpdAddressTable[0], PcdGet8 (PcdMrcSpdAddressTable0));
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.SpdAddressTable[1], MiscPeiPreMemConfig->SpdAddressTable[1], PcdGet8 (PcdMrcSpdAddressTable1));
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.SpdAddressTable[2], MiscPeiPreMemConfig->SpdAddressTable[2], PcdGet8 (PcdMrcSpdAddressTable2));
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.SpdAddressTable[3], MiscPeiPreMemConfig->SpdAddressTable[3], PcdGet8 (PcdMrcSpdAddressTable3));
+ if (PcdGet8 (PcdMrcLp5CccConfig)) {
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.Lp5CccConfig, MemConfig->Lp5CccConfig, PcdGet8 (PcdMrcLp5CccConfig));
+ }
+
+
+ NullSpdPtr = AllocateZeroPool (SPD_DATA_SIZE);
+ ASSERT (NullSpdPtr != NULL);
+
+#if FixedPcdGet8(PcdFspModeSelection) == 1
+ MemorySpdPtr000 = AllocateZeroPool (SPD_DATA_SIZE);
+ ASSERT (MemorySpdPtr000 != NULL);
+ MemorySpdPtr010 = AllocateZeroPool (SPD_DATA_SIZE);
+ ASSERT (MemorySpdPtr010 != NULL);
+ MemorySpdPtr020 = AllocateZeroPool (SPD_DATA_SIZE);
+ ASSERT (MemorySpdPtr020 != NULL);
+ MemorySpdPtr030 = AllocateZeroPool (SPD_DATA_SIZE);
+ ASSERT (MemorySpdPtr030 != NULL);
+ MemorySpdPtr100 = AllocateZeroPool (SPD_DATA_SIZE);
+ ASSERT (MemorySpdPtr100 != NULL);
+ MemorySpdPtr110 = AllocateZeroPool (SPD_DATA_SIZE);
+ ASSERT (MemorySpdPtr110 != NULL);
+ MemorySpdPtr120 = AllocateZeroPool (SPD_DATA_SIZE);
+ ASSERT (MemorySpdPtr120 != NULL);
+ MemorySpdPtr130 = AllocateZeroPool (SPD_DATA_SIZE);
+ ASSERT (MemorySpdPtr130 != NULL);
+ ((FSPM_UPD *) FspmUpd)->FspmConfig.MemorySpdPtr000 = (UINT32) MemorySpdPtr000;
+ ((FSPM_UPD *) FspmUpd)->FspmConfig.MemorySpdPtr010 = (UINT32) MemorySpdPtr010;
+ ((FSPM_UPD *) FspmUpd)->FspmConfig.MemorySpdPtr020 = (UINT32) MemorySpdPtr020;
+ ((FSPM_UPD *) FspmUpd)->FspmConfig.MemorySpdPtr030 = (UINT32) MemorySpdPtr030;
+ ((FSPM_UPD *) FspmUpd)->FspmConfig.MemorySpdPtr100 = (UINT32) MemorySpdPtr100;
+ ((FSPM_UPD *) FspmUpd)->FspmConfig.MemorySpdPtr110 = (UINT32) MemorySpdPtr110;
+ ((FSPM_UPD *) FspmUpd)->FspmConfig.MemorySpdPtr120 = (UINT32) MemorySpdPtr120;
+ ((FSPM_UPD *) FspmUpd)->FspmConfig.MemorySpdPtr130 = (UINT32) MemorySpdPtr130;
+#endif
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.SpdAddressTable[4], MiscPeiPreMemConfig->SpdAddressTable[4], PcdGet8 (PcdMrcSpdAddressTable4));
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.SpdAddressTable[5], MiscPeiPreMemConfig->SpdAddressTable[5], PcdGet8 (PcdMrcSpdAddressTable5));
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.SpdAddressTable[6], MiscPeiPreMemConfig->SpdAddressTable[6], PcdGet8 (PcdMrcSpdAddressTable6));
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.SpdAddressTable[7], MiscPeiPreMemConfig->SpdAddressTable[7], PcdGet8 (PcdMrcSpdAddressTable7));
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.SpdAddressTable[8], MiscPeiPreMemConfig->SpdAddressTable[8], PcdGet8 (PcdMrcSpdAddressTable8));
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.SpdAddressTable[9], MiscPeiPreMemConfig->SpdAddressTable[9], PcdGet8 (PcdMrcSpdAddressTable9));
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.SpdAddressTable[10], MiscPeiPreMemConfig->SpdAddressTable[10], PcdGet8 (PcdMrcSpdAddressTable10));
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.SpdAddressTable[11], MiscPeiPreMemConfig->SpdAddressTable[11], PcdGet8 (PcdMrcSpdAddressTable11));
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.SpdAddressTable[12], MiscPeiPreMemConfig->SpdAddressTable[12], PcdGet8 (PcdMrcSpdAddressTable12));
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.SpdAddressTable[13], MiscPeiPreMemConfig->SpdAddressTable[13], PcdGet8 (PcdMrcSpdAddressTable13));
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.SpdAddressTable[14], MiscPeiPreMemConfig->SpdAddressTable[14], PcdGet8 (PcdMrcSpdAddressTable14));
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.SpdAddressTable[15], MiscPeiPreMemConfig->SpdAddressTable[15], PcdGet8 (PcdMrcSpdAddressTable15));
+ if (PcdGet32 (PcdMrcRcompResistor)) {
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.RcompResistor, RcompData->RcompResistor, (UINT8) PcdGet32 (PcdMrcRcompResistor));
+ }
+ if (PcdGet32 (PcdMrcDqsMapCpu2Dram)) {
+ COPY_POLICY ((VOID *)((FSPM_UPD *) FspmUpd)->FspmConfig.DqsMapCpu2DramMc0Ch0, (VOID *)MemConfigNoCrc->DqDqsMap->DqsMapCpu2Dram, (VOID *)(UINTN)PcdGet32 (PcdMrcDqsMapCpu2Dram), sizeof (UINT8) * MEM_CFG_MAX_CONTROLLERS * MEM_CFG_MAX_CHANNELS * MEM_CFG_NUM_BYTES_MAPPED);
+ }
+ if (PcdGet32 (PcdMrcDqMapCpu2Dram)) {
+ COPY_POLICY ((VOID *)((FSPM_UPD *) FspmUpd)->FspmConfig.DqMapCpu2DramMc0Ch0, (VOID *)MemConfigNoCrc->DqDqsMap->DqMapCpu2Dram, (VOID *)(UINTN)PcdGet32 (PcdMrcDqMapCpu2Dram), sizeof (UINT8) * MEM_CFG_MAX_CONTROLLERS * MEM_CFG_MAX_CHANNELS * MEM_CFG_NUM_BYTES_MAPPED * 8);
+ }
+ if (PcdGetBool (PcdSpdPresent)) {
+ // Clear SPD data so it can be filled in by the MRC init code
+ COPY_POLICY ((VOID *)((FSPM_UPD *) FspmUpd)->FspmConfig.MemorySpdPtr000, (VOID *) MemConfigNoCrc->SpdData->SpdData[0][0][0], (VOID *)(UINT32) NullSpdPtr, SPD_DATA_SIZE);
+ COPY_POLICY ((VOID *)((FSPM_UPD *) FspmUpd)->FspmConfig.MemorySpdPtr010, (VOID *) MemConfigNoCrc->SpdData->SpdData[0][1][0], (VOID *)(UINT32) NullSpdPtr, SPD_DATA_SIZE);
+ COPY_POLICY ((VOID *)((FSPM_UPD *) FspmUpd)->FspmConfig.MemorySpdPtr020, (VOID *) MemConfigNoCrc->SpdData->SpdData[0][2][0], (VOID *)(UINT32) NullSpdPtr, SPD_DATA_SIZE);
+ COPY_POLICY ((VOID *)((FSPM_UPD *) FspmUpd)->FspmConfig.MemorySpdPtr030, (VOID *) MemConfigNoCrc->SpdData->SpdData[0][3][0], (VOID *)(UINT32) NullSpdPtr, SPD_DATA_SIZE);
+ COPY_POLICY ((VOID *)((FSPM_UPD *) FspmUpd)->FspmConfig.MemorySpdPtr100, (VOID *) MemConfigNoCrc->SpdData->SpdData[1][0][0], (VOID *)(UINT32) NullSpdPtr, SPD_DATA_SIZE);
+ COPY_POLICY ((VOID *)((FSPM_UPD *) FspmUpd)->FspmConfig.MemorySpdPtr110, (VOID *) MemConfigNoCrc->SpdData->SpdData[1][1][0], (VOID *)(UINT32) NullSpdPtr, SPD_DATA_SIZE);
+ COPY_POLICY ((VOID *)((FSPM_UPD *) FspmUpd)->FspmConfig.MemorySpdPtr120, (VOID *) MemConfigNoCrc->SpdData->SpdData[1][2][0], (VOID *)(UINT32) NullSpdPtr, SPD_DATA_SIZE);
+ COPY_POLICY ((VOID *)((FSPM_UPD *) FspmUpd)->FspmConfig.MemorySpdPtr130, (VOID *) MemConfigNoCrc->SpdData->SpdData[1][3][0], (VOID *)(UINT32) NullSpdPtr, SPD_DATA_SIZE);
+ } else {
+ if (PcdGet32 (PcdMrcSpdData)) {
+ COPY_POLICY ((VOID *)((FSPM_UPD *) FspmUpd)->FspmConfig.MemorySpdPtr000, (VOID *)MemConfigNoCrc->SpdData->SpdData[0][0][0], (VOID *)(UINTN)PcdGet32 (PcdMrcSpdData), SPD_DATA_SIZE);
+ COPY_POLICY ((VOID *)((FSPM_UPD *) FspmUpd)->FspmConfig.MemorySpdPtr010, (VOID *)MemConfigNoCrc->SpdData->SpdData[0][1][0], (VOID *)(UINTN)PcdGet32 (PcdMrcSpdData), SPD_DATA_SIZE);
+ COPY_POLICY ((VOID *)((FSPM_UPD *) FspmUpd)->FspmConfig.MemorySpdPtr020, (VOID *)MemConfigNoCrc->SpdData->SpdData[0][2][0], (VOID *)(UINTN)PcdGet32 (PcdMrcSpdData), SPD_DATA_SIZE);
+ COPY_POLICY ((VOID *)((FSPM_UPD *) FspmUpd)->FspmConfig.MemorySpdPtr030, (VOID *)MemConfigNoCrc->SpdData->SpdData[0][3][0], (VOID *)(UINTN)PcdGet32 (PcdMrcSpdData), SPD_DATA_SIZE);
+ COPY_POLICY ((VOID *)((FSPM_UPD *) FspmUpd)->FspmConfig.MemorySpdPtr100, (VOID *)MemConfigNoCrc->SpdData->SpdData[1][0][0], (VOID *)(UINTN)PcdGet32 (PcdMrcSpdData), SPD_DATA_SIZE);
+ COPY_POLICY ((VOID *)((FSPM_UPD *) FspmUpd)->FspmConfig.MemorySpdPtr110, (VOID *)MemConfigNoCrc->SpdData->SpdData[1][1][0], (VOID *)(UINTN)PcdGet32 (PcdMrcSpdData), SPD_DATA_SIZE);
+ COPY_POLICY ((VOID *)((FSPM_UPD *) FspmUpd)->FspmConfig.MemorySpdPtr120, (VOID *)MemConfigNoCrc->SpdData->SpdData[1][2][0], (VOID *)(UINTN)PcdGet32 (PcdMrcSpdData), SPD_DATA_SIZE);
+ COPY_POLICY ((VOID *)((FSPM_UPD *) FspmUpd)->FspmConfig.MemorySpdPtr130, (VOID *)MemConfigNoCrc->SpdData->SpdData[1][3][0], (VOID *)(UINTN)PcdGet32 (PcdMrcSpdData), SPD_DATA_SIZE);
+ }
+ }
+
+
+ //
+ // Get the Platform Configuration from SetupData
+ //
+#if FixedPcdGet8(PcdFspModeSelection) == 0
+ HostBridgePreMemConfig->MchBar = (UINTN) PcdGet64 (PcdMchBaseAddress);
+ HostBridgePreMemConfig->DmiBar = (UINTN) PcdGet64 (PcdDmiBaseAddress);
+ HostBridgePreMemConfig->EpBar = (UINTN) PcdGet64 (PcdEpBaseAddress);
+ HostBridgePreMemConfig->EdramBar = (UINTN) PcdGet64 (PcdEdramBaseAddress);
+ MiscPeiPreMemConfig->SmbusBar = (UINTN) PcdGet16 (PcdSmbusBaseAddress);
+#endif
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.TsegSize, MiscPeiPreMemConfig->TsegSize, PcdGet32 (PcdTsegSize));
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.UserBd, MiscPeiPreMemConfig->UserBd, PcdGet8 (PcdSaMiscUserBd));
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.DisableMrcRetrainingOnRtcPowerLoss,MiscPeiPreMemConfig->DisableMrcRetrainingOnRtcPowerLoss, PcdGet8(PcdSaMiscDisableMrcRetrainingOnRtcPowerLoss));
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.MmioSizeAdjustment, HostBridgePreMemConfig->MmioSizeAdjustment, PcdGet16 (PcdSaMiscMmioSizeAdjustment));
+
+ //
+ // Display DDI Initialization ( default Native GPIO as per board during AUTO case)
+ //
+ CopyMem (SaDisplayConfigTable, (VOID *) (UINTN) PcdGet32 (PcdSaDisplayConfigTable), (UINTN)PcdGet16 (PcdSaDisplayConfigTableSize));
+
+ //
+ // If user custom profile is selected, we will send the setup values to the MRC.
+ // The setup values will be the current memory settings plus user override values.
+ // If any other profile is selected or a WDT timeout has occured, we zero out
+ // the settings just to be safe.
+ //
+ gWdtPei = NULL;
+ Status = PeiServicesLocatePpi(
+ &gWdtPpiGuid,
+ 0,
+ NULL,
+ (VOID **) &gWdtPei
+ );
+ if (gWdtPei != NULL) {
+ WdtTimeout = gWdtPei->CheckStatus();
+ } else {
+ WdtTimeout = FALSE;
+ }
+
+ if ((WdtTimeout == FALSE)) {
+ //
+ // If USER custom profile is selected, we will start the WDT.
+ //
+ if (gWdtPei != NULL) {
+ Status = gWdtPei->ReloadAndStart(WDT_TIMEOUT);
+ }
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.VddVoltage, MemConfig->VddVoltage, 0); // Use platform default as the safe value.
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.VddqVoltage, MemConfig->VddqVoltage, 0); // Use platform default as the safe value.
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.VppVoltage, MemConfig->VppVoltage, 0); // Use platform default as the safe value.
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.Ratio, MemConfig->Ratio, 0);
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.tCL, MemConfig->tCL, 0);
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.tCWL, MemConfig->tCWL, 0);
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.tFAW, MemConfig->tFAW, 0);
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.tRAS, MemConfig->tRAS, 0);
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.tRCDtRP, MemConfig->tRCDtRP, 0);
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.tREFI, MemConfig->tREFI, 0);
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.tRFC, MemConfig->tRFC, 0);
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.tRRD, MemConfig->tRRD, 0);
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.tRTP, MemConfig->tRTP, 0);
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.tWR, MemConfig->tWR, 0);
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.tWTR, MemConfig->tWTR, 0);
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.NModeSupport, MemConfig->NModeSupport, 0);
+ }
+
+
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.CmdMirror, MemConfig->CmdMirror, PcdGet8 (PcdMrcCmdMirror)); // BitMask where bits [3:0] are controller 0 Channel [3:0] and [7:4] are Controller 1 Channel [3:0]. 0 = No Command Mirror and 1 = Command Mirror.
+
+
+ // FirstDimmBitMask defines which DIMM should be populated first on a 2DPC board
+
+ COMPARE_AND_UPDATE_POLICY(((FSPM_UPD *)FspmUpd)->FspmConfig.FirstDimmBitMask, MemConfig->FirstDimmBitMask, PcdGet8(PcdSaMiscFirstDimmBitMask));
+ COMPARE_AND_UPDATE_POLICY(((FSPM_UPD *)FspmUpd)->FspmConfig.FirstDimmBitMaskEcc, MemConfig->FirstDimmBitMaskEcc, PcdGet8(PcdSaMiscFirstDimmBitMaskEcc));
+
+
+ //
+ // Update CleanMemory variable from Memory overwrite request value. Ignore if we are performing capsule update.
+ //
+ if ((BootMode != BOOT_ON_FLASH_UPDATE) && (BootMode != BOOT_ON_S3_RESUME)) {
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.CleanMemory, MemConfigNoCrc->CleanMemory, (BOOLEAN)(MorControl & MOR_CLEAR_MEMORY_BIT_MASK));
+ }
+
+
+
+#if FixedPcdGet8(PcdFspModeSelection) == 0
+ if (BootMode == BOOT_ON_FLASH_UPDATE) {
+ CapsuleSupportMemSize = SIZE_32MB; // Reserve 32M for Capsule update/Recovery usage in PEI
+ }
+#endif
+
+ DataSize = sizeof (MemoryData);
+ Status = VariableServices->GetVariable (
+ VariableServices,
+ EFI_MEMORY_TYPE_INFORMATION_VARIABLE_NAME,
+ &gEfiMemoryTypeInformationGuid,
+ NULL,
+ &DataSize,
+ &MemoryData
+ );
+ ///
+ /// Accumulate maximum amount of memory needed
+ ///
+#if FixedPcdGet8(PcdFspModeSelection) == 1
+ PlatformMemorySize = ((FSPM_UPD *) FspmUpd)->FspmConfig.PlatformMemorySize;
+#else
+ PlatformMemorySize = MemConfigNoCrc->PlatformMemorySize;
+#endif
+ AsmCpuidEx (CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS, 0, NULL, &Ebx.Uint32, NULL, NULL);
+
+ if (EFI_ERROR (Status)) {
+ if (BootMode == BOOT_IN_RECOVERY_MODE) {
+ PlatformMemorySize = PEI_RECOVERY_MIN_MEMORY_SIZE;
+ } else {
+ ///
+ /// Use default value to avoid memory fragment.
+ /// OS boot/installation fails if there is not enough continuous memory available
+ ///
+ PlatformMemorySize = PEI_MIN_MEMORY_SIZE + ProcessorTraceTotalMemSize + CapsuleSupportMemSize;
+ DataSize = sizeof (mDefaultMemoryTypeInformation);
+ CopyMem (MemoryData, mDefaultMemoryTypeInformation, DataSize);
+ }
+ } else {
+ ///
+ /// Start with at least PEI_MIN_MEMORY_SIZE of memory for the DXE Core and the DXE Stack
+ ///
+ PlatformMemorySize = PEI_MIN_MEMORY_SIZE + ProcessorTraceTotalMemSize + CapsuleSupportMemSize;
+ }
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.PlatformMemorySize, MemConfigNoCrc->PlatformMemorySize, PlatformMemorySize);
+
+ if (BootMode != BOOT_IN_RECOVERY_MODE) {
+ for (Index = 0; Index < DataSize / sizeof (EFI_MEMORY_TYPE_INFORMATION); Index++) {
+ PlatformMemorySize += MemoryData[Index].NumberOfPages * EFI_PAGE_SIZE;
+ }
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.PlatformMemorySize, MemConfigNoCrc->PlatformMemorySize, PlatformMemorySize);
+
+ ///
+ /// Build the GUID'd HOB for DXE
+ ///
+ BuildGuidDataHob (
+ &gEfiMemoryTypeInformationGuid,
+ MemoryData,
+ DataSize
+ );
+ }
+
+ return EFI_SUCCESS;
+}
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiSiPolicyUpdate.c b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiSiPolicyUpdate.c
new file mode 100644
index 0000000000..2fd41e9189
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiSiPolicyUpdate.c
@@ -0,0 +1,114 @@
+/** @file
+ This file is SampleCode of the library for Intel Silicon PEI
+ Platform Policy initialization.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "PeiSiPolicyUpdate.h"
+#include <Library/DebugLib.h>
+#include <Library/HobLib.h>
+#include <Library/PcdLib.h>
+#include <Library/PeiServicesLib.h>
+#include <Library/PeiSiPolicyUpdateLib.h>
+#include <Library/SiPolicyLib.h>
+#include <Ppi/ReadOnlyVariable2.h>
+
+#include <PciePreMemConfig.h>
+#include <PolicyUpdateMacro.h>
+
+#if FixedPcdGet8(PcdFspModeSelection) == 1
+#include <FspmUpd.h>
+#include <FspsUpd.h>
+#include <Ppi/DebugEventHandler.h>
+#endif
+
+/**
+ This function performs Silicon PEI Policy initialization.
+
+ @retval EFI_SUCCESS The PPI is installed and initialized.
+ @retval EFI_NOT_FOUND The FspmUpd is not found.
+ @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize the driver
+**/
+EFI_STATUS
+EFIAPI
+UpdatePeiSiPolicyPreMem (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+ SI_PREMEM_POLICY_PPI *SiPreMemPolicy;
+ SI_PREMEM_CONFIG *SiPreMemConfig;
+
+ SiPreMemPolicy = NULL;
+ SiPreMemConfig = NULL;
+
+ DEBUG ((DEBUG_INFO, "Update PeiSiPolicyUpdate Pre-Mem Start\n"));
+
+ Status = PeiServicesLocatePpi (&gSiPreMemPolicyPpiGuid, 0, NULL, (VOID **) &SiPreMemPolicy);
+ ASSERT_EFI_ERROR (Status);
+ Status = GetConfigBlock ((VOID *) SiPreMemPolicy, &gSiPreMemConfigGuid, (VOID *) &SiPreMemConfig);
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Policy to prevent MRC modify the boot mode while in flash update
+ //
+ UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.SiSkipOverrideBootModeWhenFwUpdate, SiPreMemConfig->SkipOverrideBootModeWhenFwUpdate, (UINT8) FALSE);
+
+ return EFI_SUCCESS;
+}
+
+/**
+ This function performs Silicon PEI Policy initialization.
+
+ @retval EFI_SUCCESS The function completed successfully
+**/
+EFI_STATUS
+EFIAPI
+UpdatePeiSiPolicy (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+#if FixedPcdGet8(PcdFspModeSelection) == 1
+ VOID *FspsUpd;
+ DEBUG_EVENT_HABDLER_PPI *DebugEventHandlerPpi;
+#else
+ SI_POLICY_PPI *SiPolicyPpi;
+#endif
+
+ DEBUG ((DEBUG_INFO, "Update PeiSiPolicyUpdate Pos-Mem Start\n"));
+
+ Status = EFI_SUCCESS;
+#if FixedPcdGet8(PcdFspModeSelection) == 1
+ FspsUpd = NULL;
+#else
+ SiPolicyPpi = NULL;
+#endif
+
+#if FixedPcdGet8(PcdFspModeSelection) == 1
+ FspsUpd = (FSPS_UPD *) PcdGet32 (PcdFspsUpdDataAddress);
+ ASSERT (FspsUpd != NULL);
+#else
+ Status = PeiServicesLocatePpi (&gSiPolicyPpiGuid, 0, NULL, (VOID **) &SiPolicyPpi);
+ ASSERT_EFI_ERROR (Status);
+#endif
+
+#if FixedPcdGet8(PcdFspModeSelection) == 1
+ Status = PeiServicesLocatePpi (
+ &gDebugEventHandlerPpiGuid, // GUID
+ 0, // INSTANCE
+ NULL, // EFI_PEI_PPI_DESCRIPTOR
+ (VOID **) &DebugEventHandlerPpi // PPI
+ );
+ if (!EFI_ERROR(Status)) {
+ ((FSPS_UPD *) FspsUpd)->FspsConfig.FspEventHandler = (UINT32) DebugEventHandlerPpi->DebugEventHandler;
+ }
+#endif
+
+
+ return EFI_SUCCESS;
+}
+
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiSiPolicyUpdate.h b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiSiPolicyUpdate.h
new file mode 100644
index 0000000000..e7c008a6fa
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiSiPolicyUpdate.h
@@ -0,0 +1,17 @@
+/** @file
+ Header file for PEI SiPolicyUpdate.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _PEI_SI_POLICY_UPDATE_H_
+#define _PEI_SI_POLICY_UPDATE_H_
+
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/ConfigBlockLib.h>
+#include <Ppi/SiPolicy.h>
+
+#endif
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiSiliconPolicyUpdateLib/PeiCpuPolicy.h b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiSiliconPolicyUpdateLib/PeiCpuPolicy.h
new file mode 100644
index 0000000000..2f5bb13590
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiSiliconPolicyUpdateLib/PeiCpuPolicy.h
@@ -0,0 +1,22 @@
+/** @file
+ Header file for the PeiCpuPolicyInit.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _PEI_CPU_POLICY_H_
+#define _PEI_CPU_POLICY_H_
+
+#include <PiPei.h>
+#include <Library/DebugLib.h>
+#include <Library/PeiServicesLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/MemoryAllocationLib.h>
+
+#include <Ppi/SiPolicy.h>
+#include <Library/PeiPolicyBoardConfigLib.h>
+#include <Library/PeiSiPolicyUpdateLib.h>
+
+#endif
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiSiliconPolicyUpdateLib/PeiMePolicy.h b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiSiliconPolicyUpdateLib/PeiMePolicy.h
new file mode 100644
index 0000000000..bc61df96fb
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiSiliconPolicyUpdateLib/PeiMePolicy.h
@@ -0,0 +1,21 @@
+/** @file
+ Header file for the PeiMePolicyInit
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+#ifndef _PEI_ME_POLICY_H_
+#define _PEI_ME_POLICY_H_
+
+#include <PiPei.h>
+#include <Library/DebugLib.h>
+#include <Library/PeiServicesLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/MemoryAllocationLib.h>
+
+#include <Ppi/SiPolicy.h>
+#include <Library/PeiPolicyBoardConfigLib.h>
+#include <Library/PeiSiPolicyUpdateLib.h>
+
+#endif // _PEI_ME_POLICY_H_
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiSiliconPolicyUpdateLib/PeiPolicy.h b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiSiliconPolicyUpdateLib/PeiPolicy.h
new file mode 100644
index 0000000000..cceb829dc1
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiSiliconPolicyUpdateLib/PeiPolicy.h
@@ -0,0 +1,21 @@
+/** @file
+ Header file for PeiSiliconPolicyUpdateLib
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+#ifndef _PEI_POLICY_H_
+#define _PEI_POLICY_H_
+
+#include <PiPei.h>
+#include <Library/DebugLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/PcdLib.h>
+
+#include "PeiCpuPolicy.h"
+#include "PeiMePolicy.h"
+#include "PeiSaPolicy.h"
+#include "PeiSiPolicy.h"
+
+#endif
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSaPolicy.h b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSaPolicy.h
new file mode 100644
index 0000000000..19c99de0b9
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSaPolicy.h
@@ -0,0 +1,22 @@
+/** @file
+ Header file for the SaPolicyInitPei PEIM.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+#ifndef _SA_POLICY_PEI_H_
+#define _SA_POLICY_PEI_H_
+
+#include <PiPei.h>
+#include <Library/DebugLib.h>
+#include <Library/PeiServicesLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/PcdLib.h>
+
+#include <Ppi/SiPolicy.h>
+#include <Library/PeiPolicyBoardConfigLib.h>
+#include <Library/PeiSiPolicyUpdateLib.h>
+
+#endif
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiPolicy.h b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiPolicy.h
new file mode 100644
index 0000000000..31efbf17bf
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiPolicy.h
@@ -0,0 +1,21 @@
+/** @file
+ Header file for the PeiSiPolicyInit
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+#ifndef _SI_POLICY_PEI_H_
+#define _SI_POLICY_PEI_H_
+
+#include <PiPei.h>
+#include <Library/DebugLib.h>
+#include <Library/PeiServicesLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/MemoryAllocationLib.h>
+
+#include <Ppi/SiPolicy.h>
+#include <Library/PeiPolicyBoardConfigLib.h>
+#include <Library/PeiSiPolicyUpdateLib.h>
+
+#endif // _SI_POLICY_PEI_H_
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLate.c b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLate.c
new file mode 100644
index 0000000000..d912222eb9
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLate.c
@@ -0,0 +1,18 @@
+/** @file
+ This file is SampleCode for Intel PEI Platform Policy initialization.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Base.h>
+
+VOID *
+EFIAPI
+SiliconPolicyUpdateLate (
+ IN OUT VOID *Policy
+ )
+{
+ return NULL;
+}
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf
new file mode 100644
index 0000000000..67b0b324c7
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf
@@ -0,0 +1,67 @@
+## @file
+# Provide Silicon policy update functionality.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+###
+
+################################################################################
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+################################################################################
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = SiliconPolicyUpdateLib
+ FILE_GUID = 34435831-33D7-4742-992F-3A3C7B860BC5
+ MODULE_TYPE = PEIM
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = SiliconPolicyUpdateLib
+
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = IA32 X64
+#
+
+################################################################################
+#
+# Sources Section - list of files that are required for the build to succeed.
+#
+################################################################################
+
+[Sources]
+ PeiSiliconPolicyUpdatePreMem.c
+ PeiSiliconPolicyUpdatePostMem.c
+ PeiSiliconPolicyUpdateLate.c
+
+################################################################################
+#
+# Package Dependency Section - list of Package files that are required for
+# this module.
+#
+################################################################################
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ AlderlakeSiliconPkg/SiPkg.dec
+ AlderlakeOpenBoardPkg/OpenBoardPkg.dec
+
+[LibraryClasses.IA32]
+ BaseMemoryLib
+ BaseLib
+ DebugLib
+ PeiServicesTablePointerLib
+ PeiServicesLib
+ PcdLib
+ PeiPolicyBoardConfigLib
+ PeiPolicyUpdateLib
+
+[FixedPcd]
+
+[Ppis]
+
+[Guids]
\ No newline at end of file
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdatePostMem.c b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdatePostMem.c
new file mode 100644
index 0000000000..9a91ea7fe1
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdatePostMem.c
@@ -0,0 +1,53 @@
+/** @file
+ This file is SampleCode for Intel PEI Platform Policy initialization in post-memory.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "PeiPolicy.h"
+#include <Library/PeiSiPolicyUpdateLib.h>
+
+#include <Ppi/ReadOnlyVariable2.h>
+
+#include <Library/PeiServicesLib.h>
+#include <Library/PeiServicesTablePointerLib.h>
+VOID
+EFIAPI
+SiliconPolicyUpdatePostMemFirmwareConfig (
+ VOID
+ )
+{
+ //
+ // Update and override all platform related and customized settings below.
+ //
+ UpdatePeiSiPolicy ();
+ UpdatePeiPchPolicy ();
+ UpdatePeiSaPolicy ();
+ UpdatePeiCpuPolicy ();
+ UpdatePeiMePolicy ();
+
+
+
+}
+
+VOID *
+EFIAPI
+SiliconPolicyUpdatePostMem (
+ IN OUT VOID *Policy
+ )
+{
+ Policy = NULL;
+ //
+ // Update policy by board configuration
+ //
+ UpdatePeiSiPolicyBoardConfig ();
+ UpdatePeiSaPolicyBoardConfig ();
+ UpdatePeiMePolicyBoardConfig ();
+
+ // @todo separate out the advanced policy update process from this module.
+ SiliconPolicyUpdatePostMemFirmwareConfig ();
+
+ return Policy;
+}
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdatePreMem.c b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdatePreMem.c
new file mode 100644
index 0000000000..a56118ffa6
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdatePreMem.c
@@ -0,0 +1,49 @@
+/** @file
+ This file is SampleCode for Intel PEI Platform Policy initialization in pre-memory.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "PeiPolicy.h"
+#include <Library/PeiSiPolicyUpdateLib.h>
+#include <Ppi/ReadOnlyVariable2.h>
+#include <Library/PeiServicesLib.h>
+#include <Library/PeiServicesTablePointerLib.h>
+
+VOID
+EFIAPI
+SiliconPolicyUpdatePreMemFirmwareConfig (
+ VOID
+ )
+{
+ UpdatePeiSiPolicyPreMem ();
+ UpdatePeiPchPolicyPreMem ();
+ UpdatePeiMePolicyPreMem ();
+ UpdatePeiSaPolicyPreMem ();
+ UpdatePeiCpuPolicyPreMem ();
+
+}
+
+
+VOID *
+EFIAPI
+SiliconPolicyUpdatePreMem (
+ IN OUT VOID *Policy
+ )
+{
+ Policy = NULL;
+ //
+ // Update policy by board configuration
+ //
+ UpdatePeiPchPolicyBoardConfigPreMem ();
+ UpdatePeiMePolicyBoardConfigPreMem ();
+ UpdatePeiSaPolicyBoardConfigPreMem ();
+ UpdatePeiCpuPolicyBoardConfigPreMem ();
+
+ // @todo separate out the advanced policy update process from this module.
+ SiliconPolicyUpdatePreMemFirmwareConfig ();
+
+ return Policy;
+}
--
2.36.1.windows.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 6/6] AlderlakeOpenBoardPkg: Add Library Instances
[not found] <cover.1686770061.git.saloni.kasbekar@intel.com>
` (4 preceding siblings ...)
2023-06-14 19:17 ` [PATCH 5/6] AlderlakeOpenBoardPkg: Adds the Policy Module Saloni Kasbekar
@ 2023-06-14 19:17 ` Saloni Kasbekar
5 siblings, 0 replies; 6+ messages in thread
From: Saloni Kasbekar @ 2023-06-14 19:17 UTC (permalink / raw)
To: devel
Cc: Saloni Kasbekar, Sai Chaganty, Nate DeSimone, Isaac Oram,
Rosen Chuang
Adds the following libraries
- BasePlatformHookLib
- DxeAcpiGnvsInitLib
- PeiBoardConfigLib
- PeiGetFvInfoLib
- PeiReportFvLib
- SmmSpiFlashCommonLib
Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Isaac Oram <isaac.w.oram@intel.com>
Cc: Rosen Chuang <rosen.chuang@intel.com>
Signed-off-by: Saloni Kasbekar <saloni.kasbekar@intel.com>
---
.../BasePlatformHookLib/BasePlatformHookLib.c | 38 +
.../BasePlatformHookLib.inf | 48 +
.../DxeAcpiGnvsInitLib/DxeAcpiGnvsInitLib.c | 62 +
.../DxeAcpiGnvsInitLib/DxeAcpiGnvsInitLib.inf | 34 +
.../PeiBoardConfigLib/PeiBoardConfigLib.c | 252 ++++
.../PeiBoardConfigLib/PeiBoardConfigLib.inf | 73 ++
.../Library/PeiBoardConfigLib/PeiSpdTables.c | 1041 +++++++++++++++++
.../Library/PeiGetFvInfoLib/PeiGetFvInfoLib.c | 89 ++
.../PeiGetFvInfoLib/PeiGetFvInfoLib.inf | 34 +
.../Library/PeiReportFvLib/PeiReportFvLib.c | 372 ++++++
.../Library/PeiReportFvLib/PeiReportFvLib.inf | 78 ++
.../SmmSpiFlashCommonLib.inf | 52 +
.../SmmSpiFlashCommonLib/SpiFlashCommon.c | 215 ++++
.../SpiFlashCommonSmmLib.c | 64 +
14 files changed, 2452 insertions(+)
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Library/BasePlatformHookLib/BasePlatformHookLib.c
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Library/BasePlatformHookLib/BasePlatformHookLib.inf
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Library/DxeAcpiGnvsInitLib/DxeAcpiGnvsInitLib.c
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Library/DxeAcpiGnvsInitLib/DxeAcpiGnvsInitLib.inf
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Library/PeiBoardConfigLib/PeiBoardConfigLib.c
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Library/PeiBoardConfigLib/PeiBoardConfigLib.inf
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Library/PeiBoardConfigLib/PeiSpdTables.c
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Library/PeiGetFvInfoLib/PeiGetFvInfoLib.c
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Library/PeiGetFvInfoLib/PeiGetFvInfoLib.inf
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Library/PeiReportFvLib/PeiReportFvLib.c
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Library/PeiReportFvLib/PeiReportFvLib.inf
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Library/SmmSpiFlashCommonLib/SmmSpiFlashCommonLib.inf
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Library/SmmSpiFlashCommonLib/SpiFlashCommon.c
create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Library/SmmSpiFlashCommonLib/SpiFlashCommonSmmLib.c
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Library/BasePlatformHookLib/BasePlatformHookLib.c b/Platform/Intel/AlderlakeOpenBoardPkg/Library/BasePlatformHookLib/BasePlatformHookLib.c
new file mode 100644
index 0000000000..cccb1e18cc
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Library/BasePlatformHookLib/BasePlatformHookLib.c
@@ -0,0 +1,38 @@
+/** @file
+ Platform Hook Library instances
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Uefi/UefiBaseType.h>
+#include <Library/PchCycleDecodingLib.h>
+
+
+/**
+ Performs platform specific initialization required for the CPU to access
+ the hardware associated with a SerialPortLib instance. This function does
+ not initialize the serial port hardware itself. Instead, it initializes
+ hardware devices that are required for the CPU to access the serial port
+ hardware. This function may be called more than once.
+
+ @retval RETURN_SUCCESS The platform specific initialization succeeded.
+ @retval RETURN_DEVICE_ERROR The platform specific initialization could not be completed.
+
+**/
+RETURN_STATUS
+EFIAPI
+PlatformHookSerialPortInitialize (
+ VOID
+ )
+{
+
+ //
+ // Enable I/O decoding for COM1(3F8h-3FFh), COM2(2F8h-2FFh), I/O port 2Eh/2Fh, 4Eh/4Fh, 60h/64Fh and 62h/66h.
+ //
+ PchLpcIoDecodeRangesSet (PcdGet16 (PcdLpcIoDecodeRange));
+ PchLpcIoEnableDecodingSet (PcdGet16 (PchLpcIoEnableDecoding));
+
+ return RETURN_SUCCESS;
+}
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Library/BasePlatformHookLib/BasePlatformHookLib.inf b/Platform/Intel/AlderlakeOpenBoardPkg/Library/BasePlatformHookLib/BasePlatformHookLib.inf
new file mode 100644
index 0000000000..19458e7724
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Library/BasePlatformHookLib/BasePlatformHookLib.inf
@@ -0,0 +1,48 @@
+### @file
+# Platform Hook Library instance for Alderlake Mobile/Desktop CRB.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+###
+
+[Defines]
+ INF_VERSION = 0x00010017
+ BASE_NAME = BasePlatformHookLib
+ FILE_GUID = E22ADCC6-ED90-4A90-9837-C8E7FF9E963D
+ VERSION_STRING = 1.0
+ MODULE_TYPE = BASE
+ LIBRARY_CLASS = PlatformHookLib
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = IA32 X64 IPF EBC
+#
+
+[LibraryClasses]
+ BaseLib
+ IoLib
+ PciSegmentLib
+ PciLib
+ PchCycleDecodingLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ MinPlatformPkg/MinPlatformPkg.dec
+ AlderlakeOpenBoardPkg/OpenBoardPkg.dec
+ AlderlakeSiliconPkg/SiPkg.dec
+
+[Pcd]
+ gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdLpcSioIndexPort ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdLpcSioDataPort ## CONSUMES
+
+[FixedPcd]
+ gBoardModuleTokenSpaceGuid.PcdLpcSioConfigDefaultPort ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdSioBaseAddress ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdLpcIoDecodeRange ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PchLpcIoEnableDecoding ## CONSUMES
+
+[Sources]
+ BasePlatformHookLib.c
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Library/DxeAcpiGnvsInitLib/DxeAcpiGnvsInitLib.c b/Platform/Intel/AlderlakeOpenBoardPkg/Library/DxeAcpiGnvsInitLib/DxeAcpiGnvsInitLib.c
new file mode 100644
index 0000000000..3aef72ea52
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Library/DxeAcpiGnvsInitLib/DxeAcpiGnvsInitLib.c
@@ -0,0 +1,62 @@
+/** @file
+ Acpi Gnvs Init Library.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Uefi.h>
+#include <Library/IoLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+
+#include <Protocol/PlatformNvsArea.h>
+#include <Library/DxeAcpiGnvsInitLib.h>
+
+/**
+@brief
+ Global NVS initialize.
+
+ @param[in] PlatformNvsAreaPtr - Pointer of global NVS area
+
+ @retval EFI_SUCCESS - Allocate Global NVS completed.
+ @retval EFI_OUT_OF_RESOURCES - Failed to allocate required page for PlatformNvsAreaProtocol.
+**/
+EFI_STATUS
+EFIAPI
+AcpiGnvsInit (
+ IN OUT VOID **PlatformNvsAreaPtr
+ )
+{
+ UINTN Pages;
+ EFI_PHYSICAL_ADDRESS Address;
+ EFI_STATUS Status;
+ PLATFORM_NVS_AREA_PROTOCOL *PlatformNvsAreaProtocol;
+
+ Pages = EFI_SIZE_TO_PAGES (sizeof (PLATFORM_NVS_AREA));
+ Address = 0xffffffff; // allocate address below 4G.
+
+ Status = gBS->AllocatePages (
+ AllocateMaxAddress,
+ EfiACPIMemoryNVS,
+ Pages,
+ &Address
+ );
+ ASSERT_EFI_ERROR (Status);
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+
+ *PlatformNvsAreaPtr = (VOID *) (UINTN) Address;
+ SetMem (*PlatformNvsAreaPtr, sizeof (PLATFORM_NVS_AREA), 0);
+
+ //
+ // PlatformNvsAreaProtocol default value init here...
+ //
+ PlatformNvsAreaProtocol = (PLATFORM_NVS_AREA_PROTOCOL *) &Address;
+
+ return EFI_SUCCESS;
+}
+
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Library/DxeAcpiGnvsInitLib/DxeAcpiGnvsInitLib.inf b/Platform/Intel/AlderlakeOpenBoardPkg/Library/DxeAcpiGnvsInitLib/DxeAcpiGnvsInitLib.inf
new file mode 100644
index 0000000000..f9ec542f50
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Library/DxeAcpiGnvsInitLib/DxeAcpiGnvsInitLib.inf
@@ -0,0 +1,34 @@
+### @file
+# Component description file for the DxeAcpiGnvsInitLib
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+###
+
+[Defines]
+ INF_VERSION = 0x00010017
+ BASE_NAME = DxeAcpiGnvsInitLib
+ FILE_GUID = 9972077E-00AA-4F66-8CDA-E53CBD74A2F9
+ VERSION_STRING = 1.0
+ MODULE_TYPE = BASE
+ LIBRARY_CLASS = DxeAcpiGnvsInitLib
+
+[LibraryClasses]
+ BaseLib
+ DebugLib
+ IoLib
+ BaseMemoryLib
+ UefiBootServicesTableLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ AlderlakeOpenBoardPkg/OpenBoardPkg.dec
+ AlderlakeSiliconPkg/SiPkg.dec
+
+[Sources]
+ DxeAcpiGnvsInitLib.c
+
+[Pcd]
+ # gSiPkgTokenSpaceGuid.PcdAdlLpSupport ## CONSUMES
+ # gSiPkgTokenSpaceGuid.PcdAdlSSupport ## CONSUMES
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Library/PeiBoardConfigLib/PeiBoardConfigLib.c b/Platform/Intel/AlderlakeOpenBoardPkg/Library/PeiBoardConfigLib/PeiBoardConfigLib.c
new file mode 100644
index 0000000000..7b041e9315
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Library/PeiBoardConfigLib/PeiBoardConfigLib.c
@@ -0,0 +1,252 @@
+/** @file
+ Implementation of PeiBoardConfigLib.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <PiPei.h>
+#include <Library/DebugLib.h>
+#include <Library/PcdLib.h>
+#include <Library/PostCodeLib.h>
+#include <Library/TimerLib.h>
+
+#include <Library/GpioLib.h>
+
+#include <PlatformBoardType.h>
+#include <PlatformBoardId.h>
+#include <PlatformBoardConfig.h>
+#include <Ppi/ReadOnlyVariable2.h>
+#include <Library/PeiServicesLib.h>
+#include <Library/PmcLib.h>
+#include <Library/BoardConfigLib.h>
+
+
+
+VOID
+EFIAPI
+InternalUpdateRvpBoardConfig (
+ IN OUT UINT16 BoardId
+ )
+{
+ UINT8 BoardType;
+ UINT8 PlatformType;
+ UINT8 PlatformFlavor;
+
+ //
+ // Update Board Type/Platform Type/Platform Flavor
+ //
+ switch (BoardId) {
+ case BoardIdAdlPDdr5Rvp:
+ BoardType = BoardTypeRvp;
+ PlatformType = TypeUltUlx;
+ PlatformFlavor = FlavorMobile;
+ if(PcdSet64S (PcdAcpiDefaultOemTableId, ACPI_OEM_TABLE_ID_ADL_P_M) != EFI_SUCCESS)
+ {
+ DEBUG ((DEBUG_INFO, "Set PcdAcpiDefaultOemTableId error!!!\n"));
+ }
+ break;
+
+ default:
+ BoardType = BoardTypeRvp;
+ PlatformType = TypeUnknown;
+ PlatformFlavor = FlavorUnknown;
+ break;
+ }
+
+ PcdSet8S (PcdBoardType, BoardType);
+ PcdSet8S (PcdPlatformType, PlatformType);
+ PcdSet8S (PcdPlatformFlavor, PlatformFlavor);
+
+ DEBUG ((DEBUG_INFO, "PcdAcpiDefaultOemTableId is 0x%llX\n", PcdGet64 (PcdAcpiDefaultOemTableId)));
+}
+
+/**
+ Procedure to detect current board HW configuration.
+
+**/
+VOID
+GetBoardConfig (
+ VOID
+ )
+{
+ UINT16 BoardId;
+
+ //
+ // Get Platform Info and fill the PCD
+ //
+ BoardId = BoardIdAdlPDdr5Rvp;
+ PcdSet8S (PcdBoardType, BoardTypeMax);
+ PcdSet16S (PcdBoardId, BoardId);
+ //
+ // update RVP board config
+ //
+ InternalUpdateRvpBoardConfig (BoardId);
+
+ DEBUG ((DEBUG_INFO, "Platform Information:\n"));
+ DEBUG ((DEBUG_INFO, "PlatformType: %x\n", PcdGet8 (PcdPlatformType)));
+ DEBUG ((DEBUG_INFO, "PlatformFlavor: %x\n", PcdGet8 (PcdPlatformFlavor)));
+ DEBUG ((DEBUG_INFO, "BoardID: 0x%x\n", BoardId));
+ DEBUG ((DEBUG_INFO, "BoardType: %x\n", PcdGet8 (PcdBoardType)));
+
+}
+
+/**
+ Count the number of GPIO settings in the Table.
+
+ @param[in] GpioTable The pointer of GPIO config table
+ @param[out] GpioCount The number of GPIO config entries
+**/
+VOID
+GetGpioTableSize (
+ GPIO_INIT_CONFIG *GpioTable,
+ OUT UINT16 *GpioCount
+ )
+{
+ *GpioCount = 0;
+ if(GpioTable != NULL) {
+ while (GpioTable[*GpioCount].GpioPad != 0 && *GpioCount < MAX_GPIO_PINS) {
+ DEBUG ((DEBUG_INFO, "GpioTable[%d]->GpioPad = %x \n", *GpioCount, GpioTable[*GpioCount].GpioPad));
+ (*GpioCount) ++;
+ }
+ } else {
+ DEBUG ((DEBUG_INFO, "GpioTable is NULL\n"));
+ }
+ DEBUG ((DEBUG_INFO, "GetGpioTableSize() GpioCount = %d\n", *GpioCount));
+}
+
+/**
+Configure GPIO Table setting to PcdBoardGpioTablePreMem && PcdBoardGpioTable
+
+@param[in] GpioTable The pointer of GPIO config table
+@param[in] IsPostMem Is call from PostMem/PreMem
+ True - PostMem, False - PreMem
+**/
+VOID
+ConfigureGpioTabletoPCD(
+ IN GPIO_INIT_CONFIG *GpioTable,
+ IN UINT16 IsPostMem
+ )
+{
+ UINT16 GpioCount = 0;
+ UINTN Size = 0;
+ EFI_STATUS Status = EFI_SUCCESS;
+ BOOLEAN DisableVpdGpioTable = FALSE;
+
+ DEBUG ((DEBUG_INFO, "ConfigureGpioTabletoPCD() Start\n"));
+
+ DisableVpdGpioTable = (BOOLEAN) PcdGetBool (PcdDisableVpdGpioTable);
+ DEBUG((DEBUG_INFO, "PcdDisableVpdGpioTable = %d\n", DisableVpdGpioTable));
+ if (!DisableVpdGpioTable) {
+ if (GpioTable != NULL) {
+ GetGpioTableSize (GpioTable, &GpioCount);
+ if (GpioCount) {
+ if (IsPostMem == POST_MEM) { // Post Mem GPIO Configuration
+ if (GpioCount >= MAX_GPIO_PINS) {
+ DEBUG ((DEBUG_ERROR, "GpioTable entries exceeds limit, Configure only MAX_GPIO_PINS Pins.\n"));
+ GpioCount = MAX_GPIO_PINS;
+ }
+ DEBUG ((DEBUG_INFO, "GpioTable Count = %d\n", GpioCount));
+ Size = (UINTN) (GpioCount * sizeof (GPIO_INIT_CONFIG));
+ Status = PcdSetPtrS (PcdBoardGpioTable, &Size, GpioTable);
+ } else if (IsPostMem == PRE_MEM) { // Pre Mem GPIO Configuration
+ if (GpioCount >= MAX_PRE_MEM_GPIO_PINS) {
+ DEBUG ((DEBUG_ERROR, "PreMem GpioTable entries exceeds limit, Configure only MAX_PRE_MEM_GPIO_PINS Pins.\n"));
+ GpioCount = MAX_PRE_MEM_GPIO_PINS;
+ }
+ DEBUG ((DEBUG_INFO, "GpioTable Count = %d\n", GpioCount));
+ Size = (UINTN) (GpioCount * sizeof (GPIO_INIT_CONFIG));
+ Status = PcdSetPtrS (PcdBoardGpioTablePreMem, &Size, GpioTable);
+ } else if (IsPostMem == EARLY_PRE_MEM) { // Pre Mem GPIO Configuration
+ if (GpioCount >= MAX_PRE_MEM_GPIO_PINS) {
+ DEBUG((DEBUG_ERROR, "EarlyPreMem GpioTable entries exceeds limit, Configure only MAX_PRE_MEM_GPIO_PINS Pins.\n"));
+ GpioCount = MAX_PRE_MEM_GPIO_PINS;
+ }
+ DEBUG((DEBUG_INFO, "EarlyPreMem GpioTable Count = %d\n", GpioCount));
+ Size = (UINTN)(GpioCount * sizeof(GPIO_INIT_CONFIG));
+ Status = PcdSetPtrS(PcdBoardGpioTableEarlyPreMem, &Size, GpioTable);
+ }
+ ASSERT_EFI_ERROR (Status);
+ } else {
+ DEBUG ((DEBUG_INFO, "GpioTable is Empty\n"));
+ }
+ } else {
+ DEBUG ((DEBUG_INFO, "GpioTable is NULL\n"));
+ }
+ } else {
+ DEBUG ((DEBUG_INFO, "PcdDisableVpdGpioTable is TRUE, GPIO Tables will be updated by PCT PEIM \n"));
+ }
+
+ DEBUG ((DEBUG_INFO, "ConfigureGpioTabletoPCD() End\n"));
+}
+
+/**
+ Configures GPIO
+
+ @param[in] GpioTable Point to Platform Gpio table
+ @param[in] GpioTableCount Number of Gpio table entries
+**/
+STATIC
+VOID
+ConfigureGpio (
+ IN GPIO_INIT_CONFIG *GpioTable,
+ IN UINT16 GpioTableCount
+ )
+{
+ EFI_STATUS Status;
+
+ DEBUG ((DEBUG_INFO, "ConfigureGpio() Start\n"));
+
+ Status = GpioConfigurePads (GpioTableCount, GpioTable);
+ ASSERT_EFI_ERROR (Status);
+
+ DEBUG ((DEBUG_INFO, "ConfigureGpio() End\n"));
+}
+
+/**
+ Configure GPIO Before Memory is initialized.
+
+ @param[in] GpioTable Pointer to Gpio table
+**/
+VOID
+GpioInit (
+ IN GPIO_INIT_CONFIG *GpioTable
+ )
+{
+ UINT16 GpioCount;
+
+ if (GpioTable != 0) {
+ GpioCount = 0;
+ GetGpioTableSize (GpioTable, &GpioCount);
+ if (GpioCount != 0) {
+ ConfigureGpio ((VOID *) GpioTable, (UINTN) GpioCount);
+ }
+ }
+}
+
+/**
+ Update Cpu Xhci Port Enable Map PCD from SaSetup data.
+
+**/
+VOID
+EFIAPI
+TcssUpdateCpuXhciPortEnableMapPcd (
+ VOID
+ )
+{
+ UINT8 PortEnableMask;
+ UINT8 PortEnableMap;
+
+ DEBUG ((DEBUG_INFO, "[TCSS] TcssUpdateCpuXhciPortEnableMapPcd: Start\n"));
+ PortEnableMask = 0x0F; // Enable Mask for All 4 CPU USB Port.
+ PortEnableMap = PcdGet8 (PcdCpuXhciPortSupportMap); // Get Board Capability Map set Cpu Xhci Port.
+
+
+ DEBUG ((DEBUG_INFO, "[TCSS] Cpu Usb Port Enable Mask is = 0x%x\n", PortEnableMask));
+ PortEnableMap &= PortEnableMask; // Apply the Mask calculated from SaSetup Data.
+ DEBUG ((DEBUG_INFO, "[TCSS] Cpu Usb Port Enable Map in Post-Mem is = 0x%x\n", PortEnableMap));
+ PcdSet8S (PcdCpuUsb30PortEnable, PortEnableMap);
+ DEBUG ((DEBUG_INFO, "[TCSS] TcssUpdateCpuXhciPortEnableMapPcd: End\n"));
+}
+
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Library/PeiBoardConfigLib/PeiBoardConfigLib.inf b/Platform/Intel/AlderlakeOpenBoardPkg/Library/PeiBoardConfigLib/PeiBoardConfigLib.inf
new file mode 100644
index 0000000000..4e3f3d375b
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Library/PeiBoardConfigLib/PeiBoardConfigLib.inf
@@ -0,0 +1,73 @@
+### @file
+# Component information file for BaseBoardConfigLib.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+###
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = PeiBoardConfigLib
+ FILE_GUID = AA9812A8-1BA6-40AD-A846-50D0BC29C38C
+ MODULE_TYPE = PEIM
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = BoardConfigLib|PEIM
+
+[LibraryClasses]
+ DebugLib
+ PcdLib
+ PostCodeLib
+ TimerLib
+ PeiServicesLib
+ PmcLib
+ GpioLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ AlderlakeSiliconPkg/SiPkg.dec
+ AlderlakeOpenBoardPkg/OpenBoardPkg.dec
+
+[Sources]
+ PeiBoardConfigLib.c
+ PeiSpdTables.c
+
+[Ppis]
+ gEfiPeiReadOnlyVariable2PpiGuid ## CONSUMES
+
+[Pcd]
+ gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemTableId ## PRODUCES ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdBoardId ## PRODUCES ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdBoardBomId ## PRODUCES ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdBoardRev ## PRODUCES ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdSpdPresent ## PRODUCES ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdBoardType ## PRODUCES ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdPlatformType ## PRODUCES ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdPlatformFlavor ## PRODUCES ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdPlatformGeneration ## CONSUMES
+
+ # GPIO Group Tier
+ gBoardModuleTokenSpaceGuid.PcdGpioGroupToGpeDw0
+ gBoardModuleTokenSpaceGuid.PcdGpioGroupToGpeDw1
+ gBoardModuleTokenSpaceGuid.PcdGpioGroupToGpeDw2
+
+ gBoardModuleTokenSpaceGuid.PcdDisableVpdGpioTable
+ gBoardModuleTokenSpaceGuid.PcdBoardGpioTable
+ gBoardModuleTokenSpaceGuid.PcdBoardGpioTablePreMem
+ gBoardModuleTokenSpaceGuid.PcdBoardGpioTableEarlyPreMem
+ gBoardModuleTokenSpaceGuid.PcdDisplayId ## PRODUCES ## CONSUMES
+
+ # Cpu USB XHCI Port Enable Mapping
+ gBoardModuleTokenSpaceGuid.PcdCpuXhciPortSupportMap
+ gBoardModuleTokenSpaceGuid.PcdCpuUsb30PortEnable
+
+[FixedPcd]
+ gSiPkgTokenSpaceGuid.PcdAdlLpSupport ## CONSUMES
+ gSiPkgTokenSpaceGuid.PcdAdlSSupport ## CONSUMES
+
+[Guids]
+ gBoardInfoVariableGuid
+
+[Depex]
+ gEfiPeiReadOnlyVariable2PpiGuid
\ No newline at end of file
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Library/PeiBoardConfigLib/PeiSpdTables.c b/Platform/Intel/AlderlakeOpenBoardPkg/Library/PeiBoardConfigLib/PeiSpdTables.c
new file mode 100644
index 0000000000..37cd660014
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Library/PeiBoardConfigLib/PeiSpdTables.c
@@ -0,0 +1,1041 @@
+/** @file
+ SPD tables for ADL boards.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+// LPDDR4 200b
+// Samsung K4F6E304Hx-MGCJ
+// or Hynix H9HCNNNBUUxLHR-NMx
+// or Micron MT53B512M32D2NP-053
+// 3733, 32-34-34-79
+GLOBAL_REMOVE_IF_UNREFERENCED const UINT8 mLpddr4Ddp8Gb200bSpd[] = {
+ 0x23, ///< 0 384 SPD bytes used, 512 total
+ 0x11, ///< 1 SPD Revision 1.1
+ 0x10, ///< 2 DRAM Type: LPDDR4 SDRAM
+ 0x0E, ///< 3 Module Type: Not Hybrid (DRAM only) / Non-DIMM Solution (on-board DRAM)
+ 0x15, ///< 4 8 Banks, no bank groups, 8 Gb SDRAM density
+ 0x19, ///< 5 15 Rows, 10 Columns
+ 0x91, ///< 6 Non-Monolithic DRAM Device, 2 die, 1 Channels per package, Signal Loading Matrix 1
+ 0x08, ///< 7 SDRAM Optional Features: tMAW = 8192 * tREFI, Unlimited MAC
+ 0x00, ///< 8 SDRAM Thermal / Refresh options: Reserved
+ 0x40, ///< 9 Other SDRAM Optional Features: Post package repair supported, one row per bank group, Soft PPR not supported
+ 0x00, ///< 10 Reserved
+ 0x00, ///< 11 Module Nominal Voltage: Reserved
+ 0x0A, ///< 12 Module Organization: 2 Ranks, x16 Device Width per Channel
+ 0x01, ///< 13 Module Memory Bus width: 1 Channels, 16 bits channel width, no ECC
+ 0x00, ///< 14 Module Thermal Sensor: none
+ 0x00, ///< 15 Extended Module Type: Reserved
+ 0x00, ///< 16 Signal Loading: not specified
+ 0x00, ///< 17 MTB = 0.125ns, FTB = 1 ps
+ 0x05, ///< 18 tCKAVGmin = 0.536 ns (LPDDR4-3733)
+ 0x0F, ///< 19 tCKAVGmax = 1.875 ns
+ 0x92, ///< 20 CAS Latencies supported (First Byte) : 14, 10, 6
+ 0x54, ///< 21 CAS Latencies supported (Second Byte): 28, 24, 20
+ 0x01, ///< 22 CAS Latencies supported (Third Byte) : 32
+ 0x00, ///< 23 CAS Latencies supported (Fourth Byte):
+ 0x8A, ///< 24 Minimum CAS Latency (tAAmin) = 17.14 ns
+ 0x00, ///< 25 Read and Write Latency Set options: Write Latency Set A and DBI-Read Disabled
+ 0x90, ///< 26 Minimum RAS-to-CAS delay (tRCDmin) = 18 ns
+ 0xA8, ///< 27 Row precharge time for all banks (tRPab) = 21 ns
+ 0x90, ///< 28 Minimum row precharge time (tRPmin) = 18 ns
+ 0xA0, ///< 29 tRFCab = 180 ns (8 Gb dual-channel die)
+ 0x05, ///< 30 tRFCab MSB
+ 0xD0, ///< 31 tRFCpb = 90 ns (8 Gb dual-channel die)
+ 0x02, ///< 32 tRFCpb MSB
+ 0, 0, 0, 0, 0, 0, 0, ///< 33 - 39
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 40 - 49
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 50 - 59
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 60 - 69
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 70 - 79
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 80 - 89
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 90 - 99
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 100 - 109
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 110 - 119
+ 0x00, ///< 120 FTB for Row precharge time per bank (tRPpb) = 18 ns
+ 0x00, ///< 121 FTB for Row precharge time for all banks (tRPab) = 21 ns
+ 0x00, ///< 122 FTB for Minimum RAS-to-CAS delay (tRCDmin) = 18 ns
+ 0x92, ///< 123 FTB for tAAmin = 17.14 ns
+ 0x00, ///< 124 FTB for tCKAVGmax = 1.875 ns
+ 0xA7, ///< 125 FTB for tCKAVGmin = 0.536 ns (LPDDR4-3733)
+ 0x00, ///< 126 CRC A
+ 0x00, ///< 127 CRC B
+ 0, 0, ///< 128 - 129
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 130 - 139
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 140 - 149
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 150 - 159
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 160 - 169
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 170 - 179
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 180 - 189
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 190 - 199
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 200 - 209
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 210 - 219
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 220 - 229
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 230 - 239
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 240 - 249
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 250 - 259
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 260 - 269
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 270 - 279
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 280 - 289
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 290 - 299
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 300 - 309
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 310 - 319
+ 0x00, ///< 320 Module Manufacturer ID Code, Least Significant Byte
+ 0x00, ///< 321 Module Manufacturer ID Code, Most Significant Byte
+ 0x00, ///< 322 Module Manufacturing Location
+ 0x00, ///< 323 Module Manufacturing Date Year
+ 0x00, ///< 324 Module Manufacturing Date Week
+ 0x20, ///< 325 Module Serial Number A
+ 0x00, ///< 326 Module Serial Number B
+ 0x00, ///< 327 Module Serial Number C
+ 0x00, ///< 328 Module Serial Number D
+ 0x20, 0x20, 0x20, 0x20, 0x20, ///< 329 - 333 Module Part Number: Unused bytes coded as ASCII Blanks (0x20)
+ 0x20, 0x20, 0x20, 0x20, 0x20, ///< 334 - 338 Module Part Number
+ 0x20, 0x20, 0x20, 0x20, 0x20, ///< 339 - 343 Module Part Number
+ 0x20, 0x20, 0x20, 0x20, 0x20, ///< 344 - 348 Module Part Number
+ 0x00, ///< 349 Module Revision Code
+ 0x00, ///< 350 DRAM Manufacturer ID Code, Least Significant Byte
+ 0x00, ///< 351 DRAM Manufacturer ID Code, Most Significant Byte
+ 0x00 ///< 352 DRAM Stepping
+ ///< 353 - 511 are zeroes, no need to keep them, reduce BIOS image size
+};
+
+// LPDDR4X 556b
+// Micron MT53D512M64D4RQ-046 WT:E
+// 4266
+GLOBAL_REMOVE_IF_UNREFERENCED const UINT8 mLpddr4xQdp4Gb556bSpd[] = {
+ 0x23, ///< 0 384 SPD bytes used, 512 total
+ 0x11, ///< 1 SPD Revision 1.1
+ 0x11, ///< 2 DRAM Type: LPDDR4x SDRAM
+ 0x0E, ///< 3 Module Type: Not Hybrid (DRAM only) / Non-DIMM Solution (on-board DRAM)
+ 0x15, ///< 4 8 Banks, no bank groups, 8 Gb SDRAM density
+ 0x21, ///< 5 16 Row bits, 10 Column bits
+ 0xB9, ///< 6 Non-Monolithic DRAM Device, 4 dies, 2 Channels per die, Signal Loading not specified
+ 0x08, ///< 7 SDRAM Optional Features: tMAW = 8192 * tREFI, Unlimited MAC
+ 0x00, ///< 8 SDRAM Thermal / Refresh options: Reserved
+ 0x40, ///< 9 Other SDRAM Optional Features: Post package repair supported, one row per bank group, Soft PPR not supported
+ 0x00, ///< 10 Reserved
+ 0x00, ///< 11 Module Nominal Voltage: Reserved
+ 0x02, ///< 12 Module Organization: 1 Ranks, x16 Device Width per Channel
+ 0x01, ///< 13 Module Memory Bus width: 1 Channels, 16 bits channel width, no ECC
+ 0x00, ///< 14 Module Thermal Sensor: none
+ 0x00, ///< 15 Extended Module Type: Reserved
+ 0x00, ///< 16 Signal Loading: Not Specific
+ 0x00, ///< 17 MTB = 0.125ns, FTB = 1 ps
+ 0x04, ///< 18 tCKAVGmin = 0.536 ns (LPDDR4-3733)
+ 0x0F, ///< 19 tCKAVGmax = 1.875 ns
+ 0x92, ///< 20 CAS Latencies supported (First Byte) : 14, 10, 6
+ 0x54, ///< 21 CAS Latencies supported (Second Byte): 28, 24, 20
+ 0x05, ///< 22 CAS Latencies supported (Third Byte) : 32
+ 0x00, ///< 23 CAS Latencies supported (Fourth Byte):
+ 0x87, ///< 24 Minimum CAS Latency (tAAmin) = 17.14 ns
+ 0x00, ///< 25 Read and Write Latency Set options: Write Latency Set A and DBI-Read Disabled
+ 0x90, ///< 26 Minimum RAS-to-CAS delay (tRCDmin) = 18 ns
+ 0xA8, ///< 27 Row precharge time for all banks (tRPab) = 21 ns
+ 0x90, ///< 28 Minimum row precharge time (tRPmin) = 18 ns
+ 0xC0, ///< 29 tRFCab = 280 ns (8 Gb single-channel die)
+ 0x08, ///< 30 tRFCab MSB
+ 0x60, ///< 31 tRFCpb = 140 ns (8 Gb single-channel die)
+ 0x04, ///< 32 tRFCpb MSB
+ 0, 0, 0, 0, 0, 0, 0, ///< 33 - 39
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 40 - 49
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 50 - 59
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 60 - 69
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 70 - 79
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 80 - 89
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 90 - 99
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 100 - 109
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 110 - 119
+ 0x00, ///< 120 FTB for Row precharge time per bank (tRPpb) = 18 ns
+ 0x00, ///< 121 FTB for Row precharge time for all banks (tRPab) = 21 ns
+ 0x00, ///< 122 FTB for Minimum RAS-to-CAS delay (tRCDmin) = 18 ns
+ 0xE5, ///< 123 FTB for tAAmin = 17.14 ns (FTB = -0.11 ns)
+ 0x00, ///< 124 FTB for tCKAVGmax = 1.875 ns (FTB = 0 ns)
+ 0xE1, ///< 125 FTB for tCKAVGmin = 0.536 ns (FTB = -.089 ns) (LPDDR4-3733)
+ 0x85, ///< 126 CRC A
+ 0x85, ///< 127 CRC B
+ 0, 0, ///< 128 - 129
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 130 - 139
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 140 - 149
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 150 - 159
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 160 - 169
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 170 - 179
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 180 - 189
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 190 - 199
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 200 - 209
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 210 - 219
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 220 - 229
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 230 - 239
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 240 - 249
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 250 - 259
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 260 - 269
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 270 - 279
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 280 - 289
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 290 - 299
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 300 - 309
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 310 - 319
+ 0x00, ///< 320 Module Manufacturer ID Code, Least Significant Byte
+ 0x00, ///< 321 Module Manufacturer ID Code, Most Significant Byte
+ 0x00, ///< 322 Module Manufacturing Location
+ 0x00, ///< 323 Module Manufacturing Date Year
+ 0x00, ///< 324 Module Manufacturing Date Week
+ 0x56, ///< 325 Module Serial Number A
+ 0x00, ///< 326 Module Serial Number B
+ 0x00, ///< 327 Module Serial Number C
+ 0x00, ///< 328 Module Serial Number D
+ 0x20, 0x20, 0x20, 0x20, 0x20, ///< 329 - 333 Module Part Number: Unused bytes coded as ASCII Blanks (0x20)
+ 0x20, 0x20, 0x20, 0x20, 0x20, ///< 334 - 338 Module Part Number
+ 0x20, 0x20, 0x20, 0x20, 0x20, ///< 339 - 343 Module Part Number
+ 0x20, 0x20, 0x20, 0x20, 0x20, ///< 344 - 348 Module Part Number
+ 0x00, ///< 349 Module Revision Code
+ 0x00, ///< 350 DRAM Manufacturer ID Code, Least Significant Byte
+ 0x00, ///< 351 DRAM Manufacturer ID Code, Most Significant Byte
+ 0x00 ///< 352 DRAM Stepping
+ ///< 353 - 511 are zeroes, no need to keep them, reduce BIOS image size
+};
+
+// LPDDR4X 432b
+// Samsung K3UH7H70MM-JGCJ
+// 3733, 32-34-34-79
+GLOBAL_REMOVE_IF_UNREFERENCED const UINT8 mLpddr4xQdp16Gb432bSpd[] = {
+ 0x23, ///< 0 384 SPD bytes used, 512 total
+ 0x11, ///< 1 SPD Revision 1.1
+ 0x11, ///< 2 DRAM Type: LPDDR4x SDRAM
+ 0x0E, ///< 3 Module Type: Not Hybrid (DRAM only) / Non-DIMM Solution (on-board DRAM)
+ 0x16, ///< 4 8 Banks, no bank groups, 16 Gb SDRAM density
+ 0x21, ///< 5 16 Row bits, 10 Column bits
+ 0xB4, ///< 6 Non-Monolithic DRAM Device, 4 dies, 2 Channels per die, Signal Loading not specified
+ 0x08, ///< 7 SDRAM Optional Features: tMAW = 8192 * tREFI, Unlimited MAC
+ 0x00, ///< 8 SDRAM Thermal / Refresh options: Reserved
+ 0x40, ///< 9 Other SDRAM Optional Features: Post package repair supported, one row per bank group, Soft PPR not supported
+ 0x00, ///< 10 Reserved
+ 0x00, ///< 11 Module Nominal Voltage: Reserved
+ 0x0A, ///< 12 Module Organization: 2 Ranks, x16 Device Width per Channel
+ 0x01, ///< 13 Module Memory Bus width: 1 Channels, 16 bits channel width, no ECC
+ 0x00, ///< 14 Module Thermal Sensor: none
+ 0x00, ///< 15 Extended Module Type: Reserved
+ 0x48, ///< 16 Signal Loading: Data/Strobe/Mask: 2 loads, CAC: 2 loads, CS: 1 load
+ 0x00, ///< 17 MTB = 0.125ns, FTB = 1 ps
+ 0x05, ///< 18 tCKAVGmin = 0.536 ns (LPDDR4-3733)
+ 0x0F, ///< 19 tCKAVGmax = 1.875 ns
+ 0x92, ///< 20 CAS Latencies supported (First Byte) : 14, 10, 6
+ 0x54, ///< 21 CAS Latencies supported (Second Byte): 28, 24, 20
+ 0x01, ///< 22 CAS Latencies supported (Third Byte) : 32
+ 0x00, ///< 23 CAS Latencies supported (Fourth Byte):
+ 0x8A, ///< 24 Minimum CAS Latency (tAAmin) = 17.14 ns
+ 0x00, ///< 25 Read and Write Latency Set options: Write Latency Set A and DBI-Read Disabled
+ 0x90, ///< 26 Minimum RAS-to-CAS delay (tRCDmin) = 18 ns
+ 0xA8, ///< 27 Row precharge time for all banks (tRPab) = 21 ns
+ 0x90, ///< 28 Minimum row precharge time (tRPmin) = 18 ns
+ 0xC0, ///< 29 tRFCab = 280 ns (16 Gb dual-channel die)
+ 0x08, ///< 30 tRFCab MSB
+ 0x60, ///< 31 tRFCpb = 140 ns (16 Gb dual-channel die)
+ 0x04, ///< 32 tRFCpb MSB
+ 0, 0, 0, 0, 0, 0, 0, ///< 33 - 39
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 40 - 49
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 50 - 59
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 60 - 69
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 70 - 79
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 80 - 89
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 90 - 99
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 100 - 109
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 110 - 119
+ 0x00, ///< 120 FTB for Row precharge time per bank (tRPpb) = 18 ns
+ 0x00, ///< 121 FTB for Row precharge time for all banks (tRPab) = 21 ns
+ 0x00, ///< 122 FTB for Minimum RAS-to-CAS delay (tRCDmin) = 18 ns
+ 0x92, ///< 123 FTB for tAAmin = 17.14 ns (FTB = -0.11 ns)
+ 0x00, ///< 124 FTB for tCKAVGmax = 1.875 ns (FTB = 0 ns)
+ 0xA7, ///< 125 FTB for tCKAVGmin = 0.536 ns (FTB = -.089 ns) (LPDDR4-3733)
+ 0x00, ///< 126 CRC A
+ 0x00, ///< 127 CRC B
+ 0, 0, ///< 128 - 129
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 130 - 139
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 140 - 149
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 150 - 159
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 160 - 169
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 170 - 179
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 180 - 189
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 190 - 199
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 200 - 209
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 210 - 219
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 220 - 229
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 230 - 239
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 240 - 249
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 250 - 259
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 260 - 269
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 270 - 279
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 280 - 289
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 290 - 299
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 300 - 309
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 310 - 319
+ 0x00, ///< 320 Module Manufacturer ID Code, Least Significant Byte
+ 0x00, ///< 321 Module Manufacturer ID Code, Most Significant Byte
+ 0x00, ///< 322 Module Manufacturing Location
+ 0x00, ///< 323 Module Manufacturing Date Year
+ 0x00, ///< 324 Module Manufacturing Date Week
+ 0x43, ///< 325 Module Serial Number A
+ 0x00, ///< 326 Module Serial Number B
+ 0x00, ///< 327 Module Serial Number C
+ 0x00, ///< 328 Module Serial Number D
+ 0x20, 0x20, 0x20, 0x20, 0x20, ///< 329 - 333 Module Part Number: Unused bytes coded as ASCII Blanks (0x20)
+ 0x20, 0x20, 0x20, 0x20, 0x20, ///< 334 - 338 Module Part Number
+ 0x20, 0x20, 0x20, 0x20, 0x20, ///< 339 - 343 Module Part Number
+ 0x20, 0x20, 0x20, 0x20, 0x20, ///< 344 - 348 Module Part Number
+ 0x00, ///< 349 Module Revision Code
+ 0x80, ///< 350 DRAM Manufacturer ID Code, Least Significant Byte
+ 0xCE, ///< 351 DRAM Manufacturer ID Code, Most Significant Byte
+ 0x00 ///< 352 DRAM Stepping
+ ///< 353 - 511 are zeroes, no need to keep them, reduce BIOS image size
+};
+
+// LPDDR4X 556b
+// Micron MT53D1G64D8SQ-046
+// 4266
+GLOBAL_REMOVE_IF_UNREFERENCED const UINT8 mLpddr4xOdp8Gb556bSpd[] = {
+ 0x23, ///< 0 384 SPD bytes used, 512 total
+ 0x11, ///< 1 SPD Revision 1.1
+ 0x11, ///< 2 DRAM Type: LPDDR4x SDRAM
+ 0x0E, ///< 3 Module Type: Not Hybrid (DRAM only) / Non-DIMM Solution (on-board DRAM)
+ 0x1B, ///< 4 8 Banks, no bank groups, 6 Gb SDRAM density
+ 0x21, ///< 5 15 Rows, 10 Columns
+ 0xF8, ///< 6 Non-Monolithic DRAM Device, 8 die, 4 Channels per package, Signal Loading Matrix 1
+ 0x08, ///< 7 SDRAM Optional Features: tMAW = 8192 * tREFI, Unlimited MAC
+ 0x00, ///< 8 SDRAM Thermal / Refresh options: Reserved
+ 0x40, ///< 9 Other SDRAM Optional Features: Post package repair supported, one row per bank group, Soft PPR not supported
+ 0x00, ///< 10 Reserved
+ 0x00, ///< 11 Module Nominal Voltage: Reserved
+ 0x0A, ///< 12 Module Organization: 2 Ranks, x16 Device Width per Channel
+ 0x01, ///< 13 Module Memory Bus width: 1 Channels, 16 bits channel width, no ECC
+ 0x00, ///< 14 Module Thermal Sensor: none
+ 0x00, ///< 15 Extended Module Type: Reserved
+ 0x00, ///< 16 Signal Loading: Not Specific
+ 0x00, ///< 17 MTB = 0.125ns, FTB = 1 ps
+ 0x05, ///< 18 tCKAVGmin = 0.536 ns (LPDDR4-3733)
+ 0x0F, ///< 19 tCKAVGmax = 1.875 ns
+ 0x92, ///< 20 CAS Latencies supported (First Byte) : 14, 10, 6
+ 0x54, ///< 21 CAS Latencies supported (Second Byte): 28, 24, 20
+ 0x01, ///< 22 CAS Latencies supported (Third Byte) : 32
+ 0x00, ///< 23 CAS Latencies supported (Fourth Byte):
+ 0x8A, ///< 24 Minimum CAS Latency (tAAmin) = 17.14 ns
+ 0x00, ///< 25 Read and Write Latency Set options: Write Latency Set A and DBI-Read Disabled
+ 0x90, ///< 26 Minimum RAS-to-CAS delay (tRCDmin) = 18 ns
+ 0xA8, ///< 27 Row precharge time for all banks (tRPab) = 21 ns
+ 0x90, ///< 28 Minimum row precharge time (tRPmin) = 18 ns
+ 0xC0, ///< 29 tRFCab = 280 ns (8 Gb single-channel die)
+ 0x08, ///< 30 tRFCab MSB
+ 0x60, ///< 31 tRFCpb = 140 ns (8 Gb single-channel die)
+ 0x04, ///< 32 tRFCpb MSB
+ 0, 0, 0, 0, 0, 0, 0, ///< 33 - 39
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 40 - 49
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 50 - 59
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 60 - 69
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 70 - 79
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 80 - 89
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 90 - 99
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 100 - 109
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 110 - 119
+ 0x00, ///< 120 FTB for Row precharge time per bank (tRPpb) = 18 ns
+ 0x00, ///< 121 FTB for Row precharge time for all banks (tRPab) = 21 ns
+ 0x00, ///< 122 FTB for Minimum RAS-to-CAS delay (tRCDmin) = 18 ns
+ 0x92, ///< 123 FTB for tAAmin = 17.14 ns (FTB = -0.11 ns)
+ 0x00, ///< 124 FTB for tCKAVGmax = 1.875 ns (FTB = 0 ns)
+ 0xA7, ///< 125 FTB for tCKAVGmin = 0.536 ns (FTB = -.089 ns) (LPDDR4-3733)
+ 0x00, ///< 126 CRC A
+ 0x00, ///< 127 CRC B
+ 0, 0, ///< 128 - 129
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 130 - 139
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 140 - 149
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 150 - 159
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 160 - 169
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 170 - 179
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 180 - 189
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 190 - 199
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 200 - 209
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 210 - 219
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 220 - 229
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 230 - 239
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 240 - 249
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 250 - 259
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 260 - 269
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 270 - 279
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 280 - 289
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 290 - 299
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 300 - 309
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 310 - 319
+ 0x00, ///< 320 Module Manufacturer ID Code, Least Significant Byte
+ 0x00, ///< 321 Module Manufacturer ID Code, Most Significant Byte
+ 0x00, ///< 322 Module Manufacturing Location
+ 0x00, ///< 323 Module Manufacturing Date Year
+ 0x00, ///< 324 Module Manufacturing Date Week
+ 0x56, ///< 325 Module Serial Number A
+ 0x00, ///< 326 Module Serial Number B
+ 0x00, ///< 327 Module Serial Number C
+ 0x00, ///< 328 Module Serial Number D
+ 0x20, 0x20, 0x20, 0x20, 0x20, ///< 329 - 333 Module Part Number: Unused bytes coded as ASCII Blanks (0x20)
+ 0x20, 0x20, 0x20, 0x20, 0x20, ///< 334 - 338 Module Part Number
+ 0x20, 0x20, 0x20, 0x20, 0x20, ///< 339 - 343 Module Part Number
+ 0x20, 0x20, 0x20, 0x20, 0x20, ///< 344 - 348 Module Part Number
+ 0x00, ///< 349 Module Revision Code
+ 0x00, ///< 350 DRAM Manufacturer ID Code, Least Significant Byte
+ 0x00, ///< 351 DRAM Manufacturer ID Code, Most Significant Byte
+ 0x00 ///< 352 DRAM Stepping
+ ///< 353 - 511 are zeroes, no need to keep them, reduce BIOS image size
+};
+
+GLOBAL_REMOVE_IF_UNREFERENCED const UINT8 mLpddr4Ddp16Gb200b1rSpd[] = {
+ 0x23, ///< 0 384 SPD bytes used, 512 total
+ 0x10, ///< 1 SPD Revision 1.0
+ 0x11, ///< 2 DRAM Type: LPDDR4X SDRAM
+ 0x0E, ///< 3 Module Type: Not Hybrid (DRAM only) / Non-DIMM Solution (on-board DRAM)
+ 0x15, ///< 4 8 Banks, no bank groups, 8 Gb SDRAM density
+ 0x19, ///< 5 15 Rows, 10 Columns
+ 0x95, ///< 6 Non-Monolithic DRAM Device, 2 die, 2 Channels per package, Signal Loading Matrix 1
+ 0x08, ///< 7 SDRAM Optional Features: tMAW = 8192 * tREFI, Unlimited MAC
+ 0x00, ///< 8 SDRAM Thermal / Refresh options: Reserved
+ 0x40, ///< 9 Other SDRAM Optional Features: Post package repair supported, one row per bank group, Soft PPR not supported
+ 0x00, ///< 10 Reserved
+ 0x00, ///< 11 Module Nominal Voltage: Reserved
+ 0x02, ///< 12 Module Organization: 1 Ranks, x16 Device Width per Channel
+ 0x01, ///< 13 Module Memory Bus width: 1 Channels, 16 bits channel width, no ECC
+ 0x00, ///< 14 Module Thermal Sensor: none
+ 0x00, ///< 15 Extended Module Type: Reserved
+ 0x48, ///< 16 Signal Loading: Data/Strobe/Mask: 2 loads, CAC: 2 loads, CS: 1 load
+ 0x00, ///< 17 MTB = 0.125ns, FTB = 1 ps
+ 0x04, ///< 18 tCKAVGmin = 0.469 ns (LPDDR4-4267)
+ 0xFF, ///< 19 tCKAVGmax = 32.002 ns
+ 0x92, ///< 20 CAS Latencies supported (First Byte) : 14, 10, 6
+ 0x55, ///< 21 CAS Latencies supported (Second Byte): 28, 24, 20, 16
+ 0x00, ///< 22 CAS Latencies supported (Third Byte) :
+ 0x00, ///< 23 CAS Latencies supported (Fourth Byte):
+ 0x8C, ///< 24 Minimum CAS Latency (tAAmin) = 17.5 ns
+ 0x00, ///< 25 Read and Write Latency Set options: Write Latency Set A and DBI-Read Disabled
+ 0x90, ///< 26 Minimum RAS-to-CAS delay (tRCDmin) = 18 ns
+ 0xA8, ///< 27 Row precharge time for all banks (tRPab) = 21 ns
+ 0x90, ///< 28 Minimum row precharge time (tRPmin) = 18 ns
+ 0x90, ///< 29 tRFCab = 210 ns (16 Gb dual-channel die)
+ 0x06, ///< 30 tRFCab MSB
+ 0xD0, ///< 31 tRFCpb = 90 ns (16 Gb dual-channel die)
+ 0x02, ///< 32 tRFCpb MSB
+ 0, 0, 0, 0, 0, 0, 0, ///< 33 - 39
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 40 - 49
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 50 - 59
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 60 - 69
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 70 - 79
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 80 - 89
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 90 - 99
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 100 - 109
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 110 - 119
+ 0x00, ///< 120 FTB for Row precharge time per bank (tRPpb) = 18 ns
+ 0x00, ///< 121 FTB for Row precharge time for all banks (tRPab) = 21 ns
+ 0x00, ///< 122 FTB for Minimum RAS-to-CAS delay (tRCDmin) = 18 ns
+ 0x00, ///< 123 FTB for tAAmin = 17.5 ns
+ 0x7F, ///< 124 FTB for tCKAVGmax = 32.002 ns
+ 0xE1, ///< 125 FTB for tCKAVGmin = 0.469 ns (LPDDR4-4267)
+ 0x00, ///< 126 CRC A
+ 0x00, ///< 127 CRC B
+ 0, 0, ///< 128 - 129
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 130 - 139
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 140 - 149
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 150 - 159
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 160 - 169
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 170 - 179
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 180 - 189
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 190 - 199
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 200 - 209
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 210 - 219
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 220 - 229
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 230 - 239
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 240 - 249
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 250 - 259
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 260 - 269
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 270 - 279
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 280 - 289
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 290 - 299
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 300 - 309
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 310 - 319
+ 0x00, ///< 320 Module Manufacturer ID Code, Least Significant Byte
+ 0x00, ///< 321 Module Manufacturer ID Code, Most Significant Byte
+ 0x00, ///< 322 Module Manufacturing Location
+ 0x00, ///< 323 Module Manufacturing Date Year
+ 0x00, ///< 324 Module Manufacturing Date Week
+ 0x55, ///< 325 Module Serial Number A
+ 0x00, ///< 326 Module Serial Number B
+ 0x00, ///< 327 Module Serial Number C
+ 0x00, ///< 328 Module Serial Number D
+ 0x20, 0x20, 0x20, 0x20, 0x20, ///< 329 - 333 Module Part Number: Unused bytes coded as ASCII Blanks (0x20)
+ 0x20, 0x20, 0x20, 0x20, 0x20, ///< 334 - 338 Module Part Number
+ 0x20, 0x20, 0x20, 0x20, 0x20, ///< 339 - 343 Module Part Number
+ 0x20, 0x20, 0x20, 0x20, 0x20, ///< 344 - 348 Module Part Number
+ 0x00, ///< 349 Module Revision Code
+ 0x00, ///< 350 DRAM Manufacturer ID Code, Least Significant Byte
+ 0x00, ///< 351 DRAM Manufacturer ID Code, Most Significant Byte
+ 0x00 ///< 352 DRAM Stepping
+ ///< 353 - 511 are zeroes, no need to keep them, reduce BIOS image size
+};
+
+// LPDDR5 496b 12Gb die, QDP 1x16
+// Samsung K3LK2K20BM-BGCN
+// 5500, ??-??-??-??
+// 16 Banks, 4 bank groups, 12Gb SDRAM density
+// 16 Row bits, 10 Column bits
+// Non-Monolithic DRAM Device, 4 dies, 4 Channels per die,
+GLOBAL_REMOVE_IF_UNREFERENCED const UINT8 mLpddr5xQdp12Gb496bSpd[] = {
+ // ************************************
+ // Placeholder need correct SPD for LP5
+ // ************************************
+ 0x23, ///< 0 384 SPD bytes used, 512 total
+ 0x10, ///< 1 SPD Revision 1.0
+ 0x13, ///< 2 DRAM Type: LPDDR5 SDRAM
+ 0x0E, ///< 3 Module Type: Not Hybrid (DRAM only) / Non-DIMM Solution (on-board DRAM)
+ 0x88, ///< 4 8 Banks, no bank groups, 12 Gb SDRAM density
+ 0x29, ///< 5 17 Rows, 10 Columns
+ 0xB8, ///< 6 Non-Monolithic DRAM Device, 4 die, 4 Channels per package, Signal Loading Matrix 1
+ 0x08, ///< 7 SDRAM Optional Features: tMAW = 8192 * tREFI, Unlimited MAC
+ 0x00, ///< 8 SDRAM Thermal / Refresh options: Reserved
+ 0x40, ///< 9 Other SDRAM Optional Features: Post package repair supported, one row per bank group, Soft PPR not supported
+ 0x00, ///< 10 Reserved
+ 0x00, ///< 11 Module Nominal Voltage: Reserved
+ 0x02, ///< 12 Module Organization: 1 Ranks, x16 Device Width per Channel
+ 0x01, ///< 13 Module Memory Bus width: 1 Channels, 16 bits channel width, no ECC
+ 0x00, ///< 14 Module Thermal Sensor: none
+ 0x00, ///< 15 Extended Module Type: Reserved
+ 0x48, ///< 16 Signal Loading: Data/Strobe/Mask: 2 loads, CAC: 2 loads, CS: 1 load
+ 0x00, ///< 17 MTB = 0.125ns, FTB = 1 ps
+ 0x05, ///< 18 tCKAVGmin = 0.625 ns (LPDDR4-3200)
+ 0xFF, ///< 19 tCKAVGmax = 32.002 ns
+ 0x92, ///< 20 CAS Latencies supported (First Byte) : 14, 10, 6
+ 0x55, ///< 21 CAS Latencies supported (Second Byte): 28, 24, 20, 16
+ 0x00, ///< 22 CAS Latencies supported (Third Byte) :
+ 0x00, ///< 23 CAS Latencies supported (Fourth Byte):
+ 0x8C, ///< 24 Minimum CAS Latency (tAAmin) = 17.5 ns
+ 0x00, ///< 25 Read and Write Latency Set options: Write Latency Set A and DBI-Read Disabled
+ 0x90, ///< 26 Minimum RAS-to-CAS delay (tRCDmin) = 18 ns
+ 0xA8, ///< 27 Row precharge time for all banks (tRPab) = 21 ns
+ 0x90, ///< 28 Minimum row precharge time (tRPmin) = 18 ns
+ 0x90, ///< 29 tRFCab = 210 ns (16 Gb dual-channel die)
+ 0x06, ///< 30 tRFCab MSB
+ 0xD0, ///< 31 tRFCpb = 90 ns (16 Gb dual-channel die)
+ 0x02, ///< 32 tRFCpb MSB
+ 0, 0, 0, 0, 0, 0, 0, ///< 33 - 39
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 40 - 49
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 50 - 59
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 60 - 69
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 70 - 79
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 80 - 89
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 90 - 99
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 100 - 109
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 110 - 119
+ 0x00, ///< 120 FTB for Row precharge time per bank (tRPpb) = 18 ns
+ 0x00, ///< 121 FTB for Row precharge time for all banks (tRPab) = 21 ns
+ 0x00, ///< 122 FTB for Minimum RAS-to-CAS delay (tRCDmin) = 18 ns
+ 0x00, ///< 123 FTB for tAAmin = 17.5 ns
+ 0x7F, ///< 124 FTB for tCKAVGmax = 32.002 ns
+ 0x00, ///< 125 FTB for tCKAVGmin = 0.469 ns (LPDDR4-4267)
+ 0x00, ///< 126 CRC A
+ 0x00, ///< 127 CRC B
+ 0, 0, ///< 128 - 129
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 130 - 139
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 140 - 149
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 150 - 159
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 160 - 169
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 170 - 179
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 180 - 189
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 190 - 199
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 200 - 209
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 210 - 219
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 220 - 229
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 230 - 239
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 240 - 249
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 250 - 259
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 260 - 269
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 270 - 279
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 280 - 289
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 290 - 299
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 300 - 309
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 310 - 319
+ 0x00, ///< 320 Module Manufacturer ID Code, Least Significant Byte
+ 0x00, ///< 321 Module Manufacturer ID Code, Most Significant Byte
+ 0x00, ///< 322 Module Manufacturing Location
+ 0x00, ///< 323 Module Manufacturing Date Year
+ 0x00, ///< 324 Module Manufacturing Date Week
+ 0x20, ///< 325 Module ID: Module Serial Number
+ 0x00, ///< 326 Module Serial Number B
+ 0x00, ///< 327 Module Serial Number C
+ 0x00, ///< 328 Module Serial Number D
+ 0x20, 0x20, 0x20, 0x20, 0x20, ///< 329 - 333 Module Part Number: Unused bytes coded as ASCII Blanks (0x20)
+ 0x20, 0x20, 0x20, 0x20, 0x20, ///< 334 - 338 Module Part Number
+ 0x20, 0x20, 0x20, 0x20, 0x20, ///< 339 - 343 Module Part Number
+ 0x20, 0x20, 0x20, 0x20, 0x20, ///< 344 - 348 Module Part Number
+ 0x00, ///< 349 Module Revision Code
+ 0x00, ///< 350 DRAM Manufacturer ID Code, Least Significant Byte
+ 0x00, ///< 351 DRAM Manufacturer ID Code, Most Significant Byte
+ 0x00 ///< 352 DRAM Stepping
+ ///< 353 - 511 are zeroes, no need to keep them, reduce BIOS image size
+};
+
+// LPDDR4X 200b 16Gb die, DDP, 2 channel per die, 2x8
+// Samsung K4U6E3S4AA-MGCL
+// 4267, 36-39-39-90
+// 1 rank per channel, 2 SDRAMs per channel, 2x8GB = 16GB total per channel
+GLOBAL_REMOVE_IF_UNREFERENCED const UINT8 mLpddr4xDdp16Gb200bSpd[] = {
+ 0x23, ///< 0 384 SPD bytes used, 512 total
+ 0x10, ///< 1 SPD Revision 1.0
+ 0x11, ///< 2 DRAM Type: LPDDR4x SDRAM
+ 0x0E, ///< 3 Module Type: Not Hybrid (DRAM only) / Non-DIMM Solution (on-board DRAM)
+ 0x15, ///< 4 8 Banks, no bank groups, 16 Gb SDRAM density
+ 0x19, ///< 5 5 15 Rows, 10 Columns
+ 0x94, ///< 6 Non-Monolithic DRAM Device, 2 die, 1 Channels per package, Signal Loading Matrix 1
+ 0x08, ///< 7 SDRAM Optional Features: tMAW = 8192 * tREFI, Unlimited MAC
+ 0x00, ///< 8 SDRAM Thermal / Refresh options: Reserved
+ 0x40, ///< 9 Other SDRAM Optional Features: Post package repair supported, one row per bank group, Soft PPR not supported
+ 0x00, ///< 10 Reserved
+ 0x00, ///< 11 Module Nominal Voltage: Reserved
+ 0x02, ///< 12 Module Organization: 1 Ranks, x16 Device Width per Channel
+ 0x01, ///< 13 Module Memory Bus width: 1 Channels, 16 bits channel width, no ECC
+ 0x00, ///< 14 Module Thermal Sensor: none
+ 0x00, ///< 15 Extended Module Type: Reserved
+ 0x48, ///< 16 Signal Loading: Data/Strobe/Mask: 2 loads, CAC: 2 loads, CS: 1 load
+ 0x00, ///< 17 MTB = 0.125ns, FTB = 1 ps
+ 0x05, ///< 18 tCKAVGmin = 0.625 ns (LPDDR4-3200)
+ 0xFF, ///< 19 tCKAVGmax = 32.002 ns
+ 0x92, ///< 20 CAS Latencies supported (First Byte) : 14, 10, 6
+ 0x55, ///< 21 CAS Latencies supported (Second Byte): 28, 24, 20, 16
+ 0x00, ///< 22 CAS Latencies supported (Third Byte) :
+ 0x00, ///< 23 CAS Latencies supported (Fourth Byte):
+ 0x8C, ///< 24 Minimum CAS Latency (tAAmin) = 17.5 ns
+ 0x00, ///< 25 Read and Write Latency Set options: Write Latency Set A and DBI-Read Disabled
+ 0x90, ///< 26 Minimum RAS-to-CAS delay (tRCDmin) = 18 ns
+ 0xA8, ///< 27 Row precharge time for all banks (tRPab) = 21 ns
+ 0x90, ///< 28 Minimum row precharge time (tRPmin) = 18 ns
+ 0x90, ///< 29 tRFCab = 210 ns (16 Gb dual-channel die)
+ 0x06, ///< 30 tRFCab MSB
+ 0xD0, ///< 31 tRFCpb = 90 ns (16 Gb dual-channel die)
+ 0x02, ///< 32 tRFCpb MSB
+ 0, 0, 0, 0, 0, 0, 0, ///< 33 - 39
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 40 - 49
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 50 - 59
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 60 - 69
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 70 - 79
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 80 - 89
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 90 - 99
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 100 - 109
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 110 - 119
+ 0x00, ///< 120 FTB for Row precharge time per bank (tRPpb) = 18 ns
+ 0x00, ///< 121 FTB for Row precharge time for all banks (tRPab) = 21 ns
+ 0x00, ///< 122 FTB for Minimum RAS-to-CAS delay (tRCDmin) = 18 ns
+ 0x00, ///< 123 FTB for tAAmin = 17.5 ns
+ 0x7F, ///< 124 FTB for tCKAVGmax = 32.002 ns
+ 0x00, ///< 125 FTB for tCKAVGmin = 0.469 ns (LPDDR4-4267)
+ 0x00, ///< 126 CRC A
+ 0x00, ///< 127 CRC B
+ 0, 0, ///< 128 - 129
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 130 - 139
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 140 - 149
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 150 - 159
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 160 - 169
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 170 - 179
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 180 - 189
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 190 - 199
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 200 - 209
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 210 - 219
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 220 - 229
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 230 - 239
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 240 - 249
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 250 - 259
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 260 - 269
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 270 - 279
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 280 - 289
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 290 - 299
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 300 - 309
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 310 - 319
+ 0x00, ///< 320 Module Manufacturer ID Code, Least Significant Byte
+ 0x00, ///< 321 Module Manufacturer ID Code, Most Significant Byte
+ 0x00, ///< 322 Module Manufacturing Location
+ 0x00, ///< 323 Module Manufacturing Date Year
+ 0x00, ///< 324 Module Manufacturing Date Week
+ 0x20, ///< 325 Module ID: Module Serial Number
+ 0x00, ///< 326 Module Serial Number B
+ 0x00, ///< 327 Module Serial Number C
+ 0x00, ///< 328 Module Serial Number D
+ 0x20, 0x20, 0x20, 0x20, 0x20, ///< 329 - 333 Module Part Number: Unused bytes coded as ASCII Blanks (0x20)
+ 0x20, 0x20, 0x20, 0x20, 0x20, ///< 334 - 338 Module Part Number
+ 0x20, 0x20, 0x20, 0x20, 0x20, ///< 339 - 343 Module Part Number
+ 0x20, 0x20, 0x20, 0x20, 0x20, ///< 344 - 348 Module Part Number
+ 0x00, ///< 349 Module Revision Code
+ 0x00, ///< 350 DRAM Manufacturer ID Code, Least Significant Byte
+ 0x00, ///< 351 DRAM Manufacturer ID Code, Most Significant Byte
+ 0x00 ///< 352 DRAM Stepping
+ ///< 353 - 511 are zeroes, no need to keep them, reduce BIOS image size
+};
+
+// LPDDR4X 200b 16Gb die, 2 channel per die, 2x8
+// Micron MT53E1G32D4NQ-046
+// 3200
+GLOBAL_REMOVE_IF_UNREFERENCED const UINT8 mLpddr4xQdp16Gb200bSpd[] = {
+ 0x23, ///< 0 384 SPD bytes used, 512 total
+ 0x12, ///< 1 SPD Revision 1.0
+ 0x11, ///< 2 DRAM Type: LPDDR4x SDRAM
+ 0x0E, ///< 3 Module Type: Not Hybrid (DRAM only) / Non-DIMM Solution (on-board DRAM)
+ 0x15, ///< 4 8 Banks, no bank groups, 16 Gb SDRAM density
+ 0x21, ///< 5 5 15 Rows, 10 Columns
+ 0xB1, ///< 6 Non-Monolithic DRAM Device, 2 die, 1 Channels per package, Signal Loading Matrix 1
+ 0x08, ///< 7 SDRAM Optional Features: tMAW = 8192 * tREFI, Unlimited MAC
+ 0x00, ///< 8 SDRAM Thermal / Refresh options: Reserved
+ 0x40, ///< 9 Other SDRAM Optional Features: Post package repair supported, one row per bank group, Soft PPR not supported
+ 0x00, ///< 10 Reserved
+ 0x00, ///< 11 Module Nominal Voltage: Reserved
+ 0x0A, ///< 12 Module Organization: 1 Ranks, x16 Device Width per Channel
+ 0x01, ///< 13 Module Memory Bus width: 1 Channels, 16 bits channel width, no ECC
+ 0x00, ///< 14 Module Thermal Sensor: none
+ 0x00, ///< 15 Extended Module Type: Reserved
+ 0x48, ///< 16 Signal Loading: Data/Strobe/Mask: 2 loads, CAC: 2 loads, CS: 1 load
+ 0x00, ///< 17 MTB = 0.125ns, FTB = 1 ps
+ 0x04, ///< 18 tCKAVGmin = 0.625 ns (LPDDR4-3200)
+ 0x00, ///< 19 tCKAVGmax = 32.002 ns
+ 0xD2, ///< 20 CAS Latencies supported (First Byte) : 14, 10, 6
+ 0x54, ///< 21 CAS Latencies supported (Second Byte): 28, 24, 20, 16
+ 0x01, ///< 22 CAS Latencies supported (Third Byte) :
+ 0x00, ///< 23 CAS Latencies supported (Fourth Byte):
+ 0x87, ///< 24 Minimum CAS Latency (tAAmin) = 17.5 ns
+ 0x40, ///< 25 Read and Write Latency Set options: Write Latency Set A and DBI-Read Disabled
+ 0x90, ///< 26 Minimum RAS-to-CAS delay (tRCDmin) = 18 ns
+ 0xA8, ///< 27 Row precharge time for all banks (tRPab) = 21 ns
+ 0x90, ///< 28 Minimum row precharge time (tRPmin) = 18 ns
+ 0xC0, ///< 29 tRFCab = 210 ns (16 Gb dual-channel die)
+ 0x08, ///< 30 tRFCab MSB
+ 0x60, ///< 31 tRFCpb = 90 ns (16 Gb dual-channel die)
+ 0x04, ///< 32 tRFCpb MSB
+ 0, 0, 0, 0, 0, 0, 0, ///< 33 - 39
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 40 - 49
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 50 - 59
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 60 - 69
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 70 - 79
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 80 - 89
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 90 - 99
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 100 - 109
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 110 - 119
+ 0x00, ///< 120 FTB for Row precharge time per bank (tRPpb) = 18 ns
+ 0x00, ///< 121 FTB for Row precharge time for all banks (tRPab) = 21 ns
+ 0x00, ///< 122 FTB for Minimum RAS-to-CAS delay (tRCDmin) = 18 ns
+ 0xE4, ///< 123 FTB for tAAmin = 17.5 ns
+ 0x00, ///< 124 FTB for tCKAVGmax = 32.002 ns
+ 0x60, ///< 125 FTB for tCKAVGmin = 0.469 ns (LPDDR4-4267)
+ 0xA1, ///< 126 CRC A
+ 0xAC, ///< 127 CRC B
+ 0, 0, ///< 128 - 129
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 130 - 139
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 140 - 149
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 150 - 159
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 160 - 169
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 170 - 179
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 180 - 189
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 190 - 199
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 200 - 209
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 210 - 219
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 220 - 229
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 230 - 239
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 240 - 249
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 250 - 259
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 260 - 269
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 270 - 279
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 280 - 289
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 290 - 299
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 300 - 309
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 310 - 319
+ 0x00, ///< 320 Module Manufacturer ID Code, Least Significant Byte
+ 0x00, ///< 321 Module Manufacturer ID Code, Most Significant Byte
+ 0x00, ///< 322 Module Manufacturing Location
+ 0x00, ///< 323 Module Manufacturing Date Year
+ 0x00, ///< 324 Module Manufacturing Date Week
+ 0x20, ///< 325 Module ID: Module Serial Number
+ 0x00, ///< 326 Module Serial Number B
+ 0x00, ///< 327 Module Serial Number C
+ 0x00, ///< 328 Module Serial Number D
+ 0x20, 0x20, 0x20, 0x20, 0x20, ///< 329 - 333 Module Part Number: Unused bytes coded as ASCII Blanks (0x20)
+ 0x20, 0x20, 0x20, 0x20, 0x20, ///< 334 - 338 Module Part Number
+ 0x20, 0x20, 0x20, 0x20, 0x20, ///< 339 - 343 Module Part Number
+ 0x20, 0x20, 0x20, 0x20, 0x20, ///< 344 - 348 Module Part Number
+ 0x00, ///< 349 Module Revision Code
+ 0x00, ///< 350 DRAM Manufacturer ID Code, Least Significant Byte
+ 0x00, ///< 351 DRAM Manufacturer ID Code, Most Significant Byte
+ 0x00 ///< 352 DRAM Stepping
+ ///< 353 - 511 are zeroes, no need to keep them, reduce BIOS image size
+};
+
+GLOBAL_REMOVE_IF_UNREFERENCED const UINT8 mDdr5Spd_1Rx8[] = {
+ 0x30,///< 0 1024 SPD bytes total
+ 0x08,///< 1 SPD Revision 0.8
+ 0x12,///< 2 DRAM Type: DDR5 SDRAM
+ 0x03,///< 3 Module Type: Not Hybrid (DRAM only) / SO-DIMM Solution
+ 0x04,///< 4 Monolithic SDRAM, 16 Gb SDRAM density
+ 0x00,///< 5 16 Rows, 10 Columns
+ 0x20,///< 6 x8 SDRAM I/O Width
+ 0x62,///< 7 8 Bank Groups, 4 Banks per Bank Group
+ 0x00,///< 8 Secondary SDRAM Density and Package
+ 0x00,///< 9 Secondary SDRAM Addressing
+ 0x00,///< 10 Secondary SDRAM I/O Width
+ 0x00,///< 11 Secondary BankGroups and Banks per Bank Group
+ 0x60,///< 12 PPR Supported, One row per bank group, Soft PPR Supported
+ 0x00,///< 13 Commercial Temperature Grade, 0 to 85 C
+ 0x00,///< 14 Reserved
+ 0x00,///< 15 Reserved
+ 0x00,///< 16 SDRAM Nominal Voltage VDD: 1.1V
+ 0x00,///< 17 SDRAM Nominal Voltage VDDQ: 1.1V
+ 0x00,///< 18 SDRAM Nominal Voltage VPP: 1.8V
+ 0x00,///< 19 Reserved
+ 0xA1,///< 20 tCKAVGmin LSB
+ 0x01,///< 21 tCKAVGmin MSB
+ 0xE8,///< 22 tCKAVGmax LSB
+ 0x03,///< 23 tCKAVGmax MSB
+ 0x72,///< 24 CAS Latencies supported (First Byte) : 32, 30, 28, 22
+ 0x15,///< 25 CAS Latencies supported (Second Byte): 44, 40, 36
+ 0x00,///< 26 CAS Latencies supported (Third Byte) :
+ 0x00,///< 27 CAS Latencies supported (Fourth Byte):
+ 0x00,///< 28 CAS Latencies supported (Fifth Byte) :
+ 0x00,///< 29 Reserved
+ 0x1E,///< 30 Minimum CAS Latency (tAAmin) LSB
+ 0x41,///< 31 Minimum CAS Latency (tAAmin) MSB
+ 0x1E,///< 32 Minimum RAS-to-CAS delay (tRCDmin) LSB
+ 0x41,///< 33 Minimum RAS-to-CAS delay (tRCDmin) MSB
+ 0x1E,///< 34 Minimum Row Precharge delay (tRPmin) LSB
+ 0x41,///< 35 Minimum Row Precharge delay (tRPmin) MSB
+ 0x00,///< 36 Minimum Active to Precharge delay (tRASmin) LSB
+ 0x7D,///< 37 Minimum Active to Precharge delay (tRASmin) MSB
+ 0x1E,///< 38 Minimum Active to Active/Refresh delay (tRCmin) LSB
+ 0xBE,///< 39 Minimum Active to Active/Refresh delay (tRCmin) MSB
+ 0x30,///< 40 Minimum Write Recovery time (tWRmin) LSB
+ 0x75,///< 41 Minimum Write Recovery time (tWRmin) MSB
+ 0x27,///< 42 Refresh Recovery Delay (tRFC1min) LSB
+ 0x01,///< 43 Refresh Recovery Delay (tRFC1min) MSB
+ 0xA0,///< 44 Refresh Recovery Delay (tRFC2min) MSB
+ 0x00,///< 45 Refresh Recovery Delay (tRFC2min) MSB
+ 0x82,///< 46 Refresh Recovery Delay (tRFCsbmin) MSB
+ 0x00,///< 47 Refresh Recovery Delay (tRFCsbmin) MSB
+ 0, 0, ///< 48 - 49
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 50 - 59
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 60 - 69
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 70 - 79
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 80 - 89
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 90 - 99
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 100 - 109
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 110 - 119
+ 0, 0, 0, 0, 0, 0, ///< 120 - 125
+ 0x47, ///< 126 CRC Bytes 0 - 127 LSB
+ 0xAE, ///< 127 CRC Bytes 0 - 127 MSB
+ 0, 0, ///< 128 - 129
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 130 - 139
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 140 - 149
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 150 - 159
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 160 - 169
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 170 - 179
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 180 - 189
+ 0, 0, ///< 190 - 191
+ 0x08, ///< 192 SPD Revision for Module Information: 0.8
+ 0x00, ///< 193 Reserved
+ 0xC2, ///< 194 SPD Manufacturer ID First Byte
+ 0xC4, ///< 195 SPD Manufacturer ID Second Byte
+ 0x80, ///< 196 SPD Device Type
+ 0x00, ///< 197 SPD Device Revision
+ 0x80, ///< 198 PMIC0 Manufacturer ID First Byte
+ 0xB3, ///< 199 PMIC0 Manufacturer ID Second Byte
+ 0x80, ///< 200 PMIC0 Device Type
+ 0x11, ///< 201 PMIC0 Device Revision
+ 0, 0, 0, 0, ///< 202 - 205 PMIC1
+ 0, 0, 0, 0, ///< 206 - 209 PMIC2
+ 0x80, ///< 210 Thermal Sensors Manufacturer ID First Byte
+ 0xB3, ///< 211 Thermal Sensors Manufacturer ID First Byte
+ 0x80, ///< 212 Thermal Sensors Device Type
+ 0x11, ///< 213 Thermal Sensors Device Revision
+ 0, 0, 0, 0, 0, 0, ///< 214 - 219
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 220 - 229
+ 0x0F, ///< 230 Module Nominal Height
+ 0x10, ///< 231 Module Nominal Thickness
+ 0x00, ///< 232 Reference Raw Card Used
+ 0x01, ///< 233 1 Row of DRAM on Module
+ 0x01, ///< 234 1 Rank, 8 bits SDRAM data width per channel
+ 0x22, ///< 235 2 Channels per DIMM, 32 bits per Channel
+ 0, 0, 0, 0, ///< 236 - 239
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 240 - 249
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 250 - 259
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 260 - 269
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 270 - 279
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 280 - 289
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 290 - 299
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 300 - 309
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 310 - 319
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 320 - 329
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 330 - 339
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 340 - 349
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 350 - 359
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 360 - 369
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 370 - 379
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 380 - 389
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 390 - 399
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 400 - 409
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 410 - 419
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 420 - 429
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 430 - 439
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ///< 440 - 445
+ 0x9C, ///< 446 CRC for Bytes 128 - 253 LSB
+ 0xAD, ///< 447 CRC for Bytes 128 - 253 MSB
+ 0, 0, ///< 448 - 449
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 450 - 459
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 460 - 469
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 470 - 479
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 480 - 489
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 490 - 499
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 500 - 509
+ 0, 0, ///< 510 - 511
+ 0x80, ///< 512 Module Manufacturer ID First Byte
+ 0xAD, ///< 513 Module Manufacturer ID Second Byte
+ 0x00, ///< 514 Module Manufacturing Location
+ 0, 0, ///< 515 - 516 Module Manufacturing Date
+ 0, 0, 0, 0, ///< 517 - 520 Module Serial Number
+ 0x54, 0x4D, 0x43, 0x41, 0x32, 0x47, 0x53, 0x36, 0x41, 0x4A, ///< 521 - 530
+ 0x52, 0x38, 0x43, 0x2D, 0x45, 0x42, 0x20, 0x20, 0x20, 0x20, ///< 531 - 540
+ 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, ///< 541 - 550
+ 0x00, ///< 551 Module Revision Code
+ 0x80, ///< 552 DRAM Manufacturer ID First Byte
+ 0xAD ///< 553 DRAM Manufacturer ID Second Byte
+ ///< 554 - 1023 are zeroes, no need to keep them, save PEI FV size
+};
+
+GLOBAL_REMOVE_IF_UNREFERENCED const UINT8 mDdr5Spd_2Rx8[] = {
+ 0x30,///< 0 1024 SPD bytes total
+ 0x08,///< 1 SPD Revision 0.8
+ 0x12,///< 2 DRAM Type: DDR5 SDRAM
+ 0x03,///< 3 Module Type: Not Hybrid (DRAM only) / SO-DIMM Solution
+ 0x04,///< 4 Monolithic SDRAM, 16 Gb SDRAM density
+ 0x00,///< 5 16 Rows, 10 Columns
+ 0x20,///< 6 x8 SDRAM I/O Width
+ 0x62,///< 7 8 Bank Groups, 4 Banks per Bank Group
+ 0x00,///< 8 Secondary SDRAM Density and Package
+ 0x00,///< 9 Secondary SDRAM Addressing
+ 0x00,///< 10 Secondary SDRAM I/O Width
+ 0x00,///< 11 Secondary BankGroups and Banks per Bank Group
+ 0x60,///< 12 PPR Supported, One row per bank group, Soft PPR Supported
+ 0x00,///< 13 Commercial Temperature Grade, 0 to 85 C
+ 0x00,///< 14 Reserved
+ 0x00,///< 15 Reserved
+ 0x00,///< 16 SDRAM Nominal Voltage VDD: 1.1V
+ 0x00,///< 17 SDRAM Nominal Voltage VDDQ: 1.1V
+ 0x00,///< 18 SDRAM Nominal Voltage VPP: 1.8V
+ 0x00,///< 19 Reserved
+ 0xA1,///< 20 tCKAVGmin LSB
+ 0x01,///< 21 tCKAVGmin MSB
+ 0xE8,///< 22 tCKAVGmax LSB
+ 0x03,///< 23 tCKAVGmax MSB
+ 0x72,///< 24 CAS Latencies supported (First Byte) : 32, 30, 28, 22
+ 0x15,///< 25 CAS Latencies supported (Second Byte): 44, 40, 36
+ 0x00,///< 26 CAS Latencies supported (Third Byte) :
+ 0x00,///< 27 CAS Latencies supported (Fourth Byte):
+ 0x00,///< 28 CAS Latencies supported (Fifth Byte) :
+ 0x00,///< 29 Reserved
+ 0x1E,///< 30 Minimum CAS Latency (tAAmin) LSB
+ 0x41,///< 31 Minimum CAS Latency (tAAmin) MSB
+ 0x1E,///< 32 Minimum RAS-to-CAS delay (tRCDmin) LSB
+ 0x41,///< 33 Minimum RAS-to-CAS delay (tRCDmin) MSB
+ 0x1E,///< 34 Minimum Row Precharge delay (tRPmin) LSB
+ 0x41,///< 35 Minimum Row Precharge delay (tRPmin) MSB
+ 0x00,///< 36 Minimum Active to Precharge delay (tRASmin) LSB
+ 0x7D,///< 37 Minimum Active to Precharge delay (tRASmin) MSB
+ 0x1E,///< 38 Minimum Active to Active/Refresh delay (tRCmin) LSB
+ 0xBE,///< 39 Minimum Active to Active/Refresh delay (tRCmin) MSB
+ 0x30,///< 40 Minimum Write Recovery time (tWRmin) LSB
+ 0x75,///< 41 Minimum Write Recovery time (tWRmin) MSB
+ 0x27,///< 42 Refresh Recovery Delay (tRFC1min) LSB
+ 0x01,///< 43 Refresh Recovery Delay (tRFC1min) MSB
+ 0xA0,///< 44 Refresh Recovery Delay (tRFC2min) MSB
+ 0x00,///< 45 Refresh Recovery Delay (tRFC2min) MSB
+ 0x82,///< 46 Refresh Recovery Delay (tRFCsbmin) MSB
+ 0x00,///< 47 Refresh Recovery Delay (tRFCsbmin) MSB
+ 0, 0, ///< 48 - 49
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 50 - 59
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 60 - 69
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 70 - 79
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 80 - 89
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 90 - 99
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 100 - 109
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 110 - 119
+ 0, 0, 0, 0, 0, 0, ///< 120 - 125
+ 0x47, ///< 126 CRC Bytes 0 - 127 LSB
+ 0xAE, ///< 127 CRC Bytes 0 - 127 MSB
+ 0, 0, ///< 128 - 129
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 130 - 139
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 140 - 149
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 150 - 159
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 160 - 169
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 170 - 179
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 180 - 189
+ 0, 0, ///< 190 - 191
+ 0x08, ///< 192 SPD Revision for Module Information: 0.8
+ 0x00, ///< 193 Reserved
+ 0xC2, ///< 194 SPD Manufacturer ID First Byte
+ 0xC4, ///< 195 SPD Manufacturer ID Second Byte
+ 0x80, ///< 196 SPD Device Type
+ 0x00, ///< 197 SPD Device Revision
+ 0x80, ///< 198 PMIC0 Manufacturer ID First Byte
+ 0xB3, ///< 199 PMIC0 Manufacturer ID Second Byte
+ 0x80, ///< 200 PMIC0 Device Type
+ 0x11, ///< 201 PMIC0 Device Revision
+ 0, 0, 0, 0, ///< 202 - 205 PMIC1
+ 0, 0, 0, 0, ///< 206 - 209 PMIC2
+ 0x80, ///< 210 Thermal Sensors Manufacturer ID First Byte
+ 0xB3, ///< 211 Thermal Sensors Manufacturer ID First Byte
+ 0x80, ///< 212 Thermal Sensors Device Type
+ 0x11, ///< 213 Thermal Sensors Device Revision
+ 0, 0, 0, 0, 0, 0, ///< 214 - 219
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 220 - 229
+ 0x0F, ///< 230 Module Nominal Height
+ 0x10, ///< 231 Module Nominal Thickness
+ 0x00, ///< 232 Reference Raw Card Used
+ 0x01, ///< 233 1 Row of DRAM on Module
+ 0x08, ///< 234 Module Organization: 2 Package Ranks; symmetrical rank mix
+ 0x22, ///< 235 2 Channels per DIMM, 32 bits per Channel
+ 0, 0, 0, 0, ///< 236 - 239
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 240 - 249
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 250 - 259
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 260 - 269
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 270 - 279
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 280 - 289
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 290 - 299
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 300 - 309
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 310 - 319
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 320 - 329
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 330 - 339
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 340 - 349
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 350 - 359
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 360 - 369
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 370 - 379
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 380 - 389
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 390 - 399
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 400 - 409
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 410 - 419
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 420 - 429
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 430 - 439
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ///< 440 - 445
+ 0x9C, ///< 446 CRC for Bytes 128 - 253 LSB
+ 0xAD, ///< 447 CRC for Bytes 128 - 253 MSB
+ 0, 0, ///< 448 - 449
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 450 - 459
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 460 - 469
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 470 - 479
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 480 - 489
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 490 - 499
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 500 - 509
+ 0, 0, ///< 510 - 511
+ 0x80, ///< 512 Module Manufacturer ID First Byte
+ 0xAD, ///< 513 Module Manufacturer ID Second Byte
+ 0x00, ///< 514 Module Manufacturing Location
+ 0, 0, ///< 515 - 516 Module Manufacturing Date
+ 0, 0, 0, 0, ///< 517 - 520 Module Serial Number
+ 0x54, 0x4D, 0x43, 0x41, 0x32, 0x47, 0x53, 0x36, 0x41, 0x4A, ///< 521 - 530
+ 0x52, 0x38, 0x43, 0x2D, 0x45, 0x42, 0x20, 0x20, 0x20, 0x20, ///< 531 - 540
+ 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, ///< 541 - 550
+ 0x00, ///< 551 Module Revision Code
+ 0x80, ///< 552 DRAM Manufacturer ID First Byte
+ 0xAD ///< 553 DRAM Manufacturer ID Second Byte
+ ///< 554 - 1023 are zeroes, no need to keep them, save PEI FV size
+};
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Library/PeiGetFvInfoLib/PeiGetFvInfoLib.c b/Platform/Intel/AlderlakeOpenBoardPkg/Library/PeiGetFvInfoLib/PeiGetFvInfoLib.c
new file mode 100644
index 0000000000..eb6e0a0f4b
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Library/PeiGetFvInfoLib/PeiGetFvInfoLib.c
@@ -0,0 +1,89 @@
+/** @file
+ Helper Library for PEI Graphics PEIM
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Library/PeiGetFvInfoLib.h>
+#include <Ppi/FirmwareVolume.h>
+#include <Pi/PiPeiCis.h>
+#include <Core/Pei/PeiMain.h>
+#include <Library/PeiServicesLib.h>
+#include <Library/HobLib.h>
+
+/**
+ PeiGetSectionFromFv finds the file in FV and gets file Address and Size
+
+ @param[in] NameGuid - File GUID
+ @param[out] Address - Pointer to the File Address
+ @param[out] Size - Pointer to File Size
+
+ @retval EFI_SUCCESS Successfull in reading the section from FV
+ @retval EFI_NOT_FOUND File not found
+**/
+EFI_STATUS
+EFIAPI
+PeiGetSectionFromFv (
+ IN CONST EFI_GUID NameGuid,
+ OUT VOID **Address,
+ OUT UINT32 *Size
+ )
+{
+ EFI_STATUS Status;
+ EFI_PEI_FIRMWARE_VOLUME_PPI *FvPpi;
+ EFI_FV_FILE_INFO FvFileInfo;
+ PEI_CORE_FV_HANDLE *CoreFvHandle;
+ EFI_PEI_FILE_HANDLE FileHandle;
+ EFI_GUID *FileGuid;
+ EFI_COMMON_SECTION_HEADER *Section;
+ EFI_HOB_GUID_TYPE *GuidHob;
+ VOID *HobData;
+
+ Status = PeiServicesLocatePpi(
+ &gEfiFirmwareFileSystem2Guid,
+ 0,
+ NULL,
+ (VOID **)&FvPpi
+ );
+ ASSERT_EFI_ERROR(Status);
+
+ GuidHob = GetFirstGuidHob (&gPlatformInitFvLocationGuid);
+ if (GuidHob != NULL) {
+ HobData = *(VOID **)GET_GUID_HOB_DATA(GuidHob);
+ CoreFvHandle = (PEI_CORE_FV_HANDLE *) HobData;
+
+ //
+ // File typically resides in current FV or previous FV, so searching both of them.
+ //
+ Status = FvPpi->FindFileByName (FvPpi, &NameGuid, &CoreFvHandle->FvHandle, &FileHandle);
+
+ if (!EFI_ERROR(Status) && FileHandle != NULL) {
+
+ DEBUG((DEBUG_INFO, "Find SectionByType \n"));
+
+ Status = FvPpi->FindSectionByType(FvPpi, EFI_SECTION_RAW, FileHandle, (VOID **)&FileGuid);
+ if (!EFI_ERROR(Status)) {
+
+ DEBUG((DEBUG_INFO, "GetFileInfo \n"));
+
+ Status = FvPpi->GetFileInfo(FvPpi, FileHandle, &FvFileInfo);
+ Section = (EFI_COMMON_SECTION_HEADER *)FvFileInfo.Buffer;
+
+ if (IS_SECTION2(Section)) {
+ ASSERT(SECTION2_SIZE(Section) > 0x00FFFFFF);
+ *Size = SECTION2_SIZE(Section) - sizeof (EFI_COMMON_SECTION_HEADER2);
+ *Address = ((UINT8 *)Section + sizeof (EFI_COMMON_SECTION_HEADER2));
+ } else {
+ *Size = SECTION_SIZE(Section) - sizeof (EFI_COMMON_SECTION_HEADER);
+ *Address = ((UINT8 *)Section + sizeof (EFI_COMMON_SECTION_HEADER));
+ }
+ return EFI_SUCCESS;
+ }
+ }
+ } else {
+ DEBUG ((DEBUG_INFO, "Hob not found\n"));
+ }
+ return EFI_NOT_FOUND;
+}
\ No newline at end of file
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Library/PeiGetFvInfoLib/PeiGetFvInfoLib.inf b/Platform/Intel/AlderlakeOpenBoardPkg/Library/PeiGetFvInfoLib/PeiGetFvInfoLib.inf
new file mode 100644
index 0000000000..1701fb15fe
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Library/PeiGetFvInfoLib/PeiGetFvInfoLib.inf
@@ -0,0 +1,34 @@
+### @file
+# Component description file for PeiGetFvInfo library.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+###
+
+[Defines]
+ INF_VERSION = 0x00010017
+ BASE_NAME = PeiGetFvInfoLib
+ FILE_GUID = C2584BE4-2CCD-418C-9205-A2031CE75861
+ VERSION_STRING = 1.0
+ MODULE_TYPE = PEIM
+ LIBRARY_CLASS = PeiGetFvInfoLib
+
+[LibraryClasses]
+ BaseMemoryLib
+ BaseLib
+ DebugLib
+ DebugPrintErrorLevelLib
+ HobLib
+ PeiServicesLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ AlderlakeOpenBoardPkg/OpenBoardPkg.dec
+
+[Sources]
+ PeiGetFvInfoLib.c
+
+[Guids]
+ gPlatformInitFvLocationGuid ## CONSUMES
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Library/PeiReportFvLib/PeiReportFvLib.c b/Platform/Intel/AlderlakeOpenBoardPkg/Library/PeiReportFvLib/PeiReportFvLib.c
new file mode 100644
index 0000000000..fa6dc70e6b
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Library/PeiReportFvLib/PeiReportFvLib.c
@@ -0,0 +1,372 @@
+/** @file
+
+ Source code file for the Report Firmware Volume (FV) library
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Base.h>
+#include <PiPei.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/HobLib.h>
+#include <Library/PcdLib.h>
+#include <Library/PeiServicesLib.h>
+#include <Library/ReportFvLib.h>
+#include <Guid/FirmwareFileSystem2.h>
+#include <Ppi/FirmwareVolumeInfo.h>
+#include <Ppi/ReadOnlyVariable2.h>
+#include <Library/PcdLib.h>
+#include <Pi/PiStatusCode.h>
+#include <Library/MtrrLib.h>
+#include <Library/ReportStatusCodeLib.h>
+
+EFI_STATUS
+EFIAPI
+InstallFvExtendedPostMemoryCallback (
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
+ IN VOID *Ppi
+ );
+
+EFI_STATUS
+EFIAPI
+InstallFvExtendedAdvancedCallback (
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
+ IN VOID *Ppi
+ );
+
+/**
+ Notify list for FV installation to the memory for Extended BIOS Region.
+ Each entry of the notify list may need to be registered based on a boot path.
+ Make sure what FV is installed by each callback and notify them per needs.
+**/
+static EFI_PEI_NOTIFY_DESCRIPTOR mExtendedBiosDecodeReadyNotifyList [] = {
+ {
+ (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
+ &gExtendedBiosDecodeReadyPpiGuid,
+ InstallFvExtendedPostMemoryCallback
+ },
+ {
+ (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
+ &gExtendedBiosDecodeReadyPpiGuid,
+ InstallFvExtendedAdvancedCallback
+ },
+};
+
+VOID
+PrintFvHeaderInfo (
+ EFI_FIRMWARE_VOLUME_HEADER *FvHeader
+ );
+
+VOID
+ReportPreMemFv (
+ VOID
+ )
+{
+ /*
+ Note : FSP FVs except FSP-T FV are installed in IntelFsp2Wrapper Pkg or FspPkg in Dispatch mode.
+ */
+ if (FixedPcdGetBool (PcdFspWrapperBootMode)) {
+ DEBUG ((DEBUG_INFO, "Install FlashFvFspT - 0x%x, 0x%x\n", PcdGet32 (PcdFlashFvFspTBase), PcdGet32 (PcdFlashFvFspTSize)));
+ PeiServicesInstallFvInfo2Ppi (
+ &(((EFI_FIRMWARE_VOLUME_HEADER *) (UINTN) PcdGet32 (PcdFlashFvFspTBase))->FileSystemGuid),
+ (VOID *) (UINTN) PcdGet32 (PcdFlashFvFspTBase),
+ PcdGet32 (PcdFlashFvFspTSize),
+ NULL,
+ NULL,
+ 0
+ );
+ }
+
+
+ DEBUG ((DEBUG_INFO, "Install FlashFvFirmwareBinaries - 0x%x, 0x%x\n", PcdGet32 (PcdFlashFvFirmwareBinariesBase), PcdGet32 (PcdFlashFvFirmwareBinariesSize)));
+ PeiServicesInstallFvInfo2Ppi (
+ &(((EFI_FIRMWARE_VOLUME_HEADER *) (UINTN) PcdGet32 (PcdFlashFvFirmwareBinariesBase))->FileSystemGuid),
+ (VOID *) (UINTN) PcdGet32 (PcdFlashFvFirmwareBinariesBase),
+ PcdGet32 (PcdFlashFvFirmwareBinariesSize),
+ NULL,
+ NULL,
+ 0
+ );
+}
+
+/**
+ FvCnvUncompact section dependency PPI
+**/
+static EFI_PEI_PPI_DESCRIPTOR mFvCnvDispatchFlagPpi = {
+ (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
+ &gPeiFvCnvDispatchFlagPpiGuid,
+ NULL
+};
+
+/**
+ This function call checks if this is after capsule update by BootStateAfterCapsule variable.
+ The variable is set to TRUE at the end of capsule update process.
+ The boot paths always require all FVs to be installed
+ so UEFI global boot option variables are initialized.
+
+ @retval TRUE This is the first boot after capsule update.
+ @retval FALSE This is NOT the first boot after capsule update.
+**/
+BOOLEAN
+IsAfterCapsule (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+ EFI_PEI_READ_ONLY_VARIABLE2_PPI *VariablePpi;
+ BOOLEAN BootStateAfterCapsule;
+ BOOLEAN IsAfterCapsule;
+ BootStateAfterCapsule = FALSE;
+ IsAfterCapsule = FALSE;
+
+ Status = PeiServicesLocatePpi (
+ &gEfiPeiReadOnlyVariable2PpiGuid,
+ 0,
+ NULL,
+ (VOID **)&VariablePpi
+ );
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "IsAfterCapsule : Read Only Variable PPI is not found.\n"));
+ ASSERT_EFI_ERROR (Status);
+ return FALSE;
+ }
+
+
+ return IsAfterCapsule;
+}
+
+/**
+ This function call installs section dependency PPIs for the child FVs in Optional FV.
+
+ @param[out] *Installed Return TRUE if section dependencies in Optional FV are installed.
+ Return FALSE when none of section dependencies in Optional FV are installed.
+
+ @retval EFI_SUCCESS Section dependency installation completes successfully.
+ @retval Others Section dependency installation fails to complete.
+**/
+EFI_STATUS
+InstallOptionalFvDependency (
+ OUT BOOLEAN *Installed
+ )
+{
+ EFI_STATUS Status;
+
+ Status = EFI_SUCCESS;
+ *Installed = FALSE;
+
+#if FixedPcdGet8(PcdFspModeSelection) == 0 // #if Dispatch Mode
+ if (IsAfterCapsule ()) {
+#endif
+ DEBUG ((DEBUG_INFO, "InstallOptionalFvDependency : Installing FvCnvUncompact dependency.\n"));
+ Status = PeiServicesInstallPpi (&mFvCnvDispatchFlagPpi);
+ *Installed = TRUE;
+ ASSERT_EFI_ERROR (Status);
+#if FixedPcdGet8(PcdFspModeSelection) == 0 // #if Dispatch Mode
+ }
+#endif
+ return Status;
+}
+VOID
+ReportPostMemFv (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+ EFI_BOOT_MODE BootMode;
+ EFI_HOB_GUID_TYPE *GuidHob;
+ BOOLEAN IsOptFvDependencyInstalled;
+ IsOptFvDependencyInstalled = FALSE;
+
+ Status = PeiServicesGetBootMode (&BootMode);
+ ASSERT_EFI_ERROR (Status);
+
+ /*
+ Note : FSP FVs except FSP-T FV are installed in IntelFsp2WrapperPkg or FspPkg.
+ */
+
+ ///
+ /// Build HOB for DXE
+ ///
+ if (BootMode == BOOT_IN_RECOVERY_MODE) {
+ ///
+ /// Prepare the recovery service
+ ///
+ } else {
+ GuidHob = GetFirstGuidHob (&gBiosInfoRecoveryGuid);
+ if (GuidHob == NULL) {
+ DEBUG ((DEBUG_INFO, "Install FlashFvSecurity - 0x%x, 0x%x\n", PcdGet32 (PcdFlashFvSecurityBase), PcdGet32 (PcdFlashFvSecuritySize)));
+ PeiServicesInstallFvInfo2Ppi (
+ &(((EFI_FIRMWARE_VOLUME_HEADER *) (UINTN) PcdGet32 (PcdFlashFvSecurityBase))->FileSystemGuid),
+ (VOID *) (UINTN) PcdGet32 (PcdFlashFvSecurityBase),
+ PcdGet32 (PcdFlashFvSecuritySize),
+ NULL,
+ NULL,
+ 0
+ );
+ if (BootMode != BOOT_ON_S3_RESUME) {
+ DEBUG ((DEBUG_INFO, "Install FlashFvAdvanced - 0x%x, 0x%x\n", PcdGet32 (PcdFlashFvAdvancedBase), PcdGet32 (PcdFlashFvAdvancedSize)));
+ PeiServicesInstallFvInfo2Ppi (
+ &(((EFI_FIRMWARE_VOLUME_HEADER *) (UINTN) PcdGet32 (PcdFlashFvAdvancedBase))->FileSystemGuid),
+ (VOID *) (UINTN) PcdGet32 (PcdFlashFvAdvancedBase),
+ PcdGet32 (PcdFlashFvAdvancedSize),
+ NULL,
+ NULL,
+ 0
+ );
+ DEBUG ((DEBUG_INFO, "Install FlashFvUefiBoot - 0x%x, 0x%x\n", PcdGet32 (PcdFlashFvUefiBootBase), PcdGet32 (PcdFlashFvUefiBootSize)));
+ PeiServicesInstallFvInfo2Ppi (
+ &(((EFI_FIRMWARE_VOLUME_HEADER *) (UINTN) PcdGet32 (PcdFlashFvUefiBootBase))->FileSystemGuid),
+ (VOID *) (UINTN) PcdGet32 (PcdFlashFvUefiBootBase),
+ PcdGet32 (PcdFlashFvUefiBootSize),
+ NULL,
+ NULL,
+ 0
+ );
+ DEBUG ((DEBUG_INFO, "Install FlashFvOsBoot - 0x%x, 0x%x\n", PcdGet32 (PcdFlashFvOsBootBase), PcdGet32 (PcdFlashFvOsBootSize)));
+ PeiServicesInstallFvInfo2Ppi (
+ &(((EFI_FIRMWARE_VOLUME_HEADER *) (UINTN) PcdGet32 (PcdFlashFvOsBootBase))->FileSystemGuid),
+ (VOID *) (UINTN) PcdGet32 (PcdFlashFvOsBootBase),
+ PcdGet32 (PcdFlashFvOsBootSize),
+ NULL,
+ NULL,
+ 0
+ );
+ Status = InstallOptionalFvDependency (&IsOptFvDependencyInstalled);
+ if (!EFI_ERROR (Status) && IsOptFvDependencyInstalled) {
+ DEBUG ((DEBUG_INFO, "Install FlashFvOptional - 0x%x, 0x%x\n", PcdGet32 (PcdFlashFvOptionalBase), PcdGet32 (PcdFlashFvOptionalSize)));
+ PeiServicesInstallFvInfo2Ppi (
+ &(((EFI_FIRMWARE_VOLUME_HEADER *) (UINTN) PcdGet32 (PcdFlashFvOptionalBase))->FileSystemGuid),
+ (VOID *) (UINTN) PcdGet32 (PcdFlashFvOptionalBase),
+ PcdGet32 (PcdFlashFvOptionalSize),
+ NULL,
+ NULL,
+ 0
+ );
+ }
+ }
+ Status = PeiServicesNotifyPpi (&mExtendedBiosDecodeReadyNotifyList [1]);
+ ASSERT_EFI_ERROR (Status);
+ }
+ DEBUG ((DEBUG_INFO, "Install FlashFvPostMemory - 0x%x, 0x%x\n", PcdGet32 (PcdFlashFvPostMemoryBase), PcdGet32 (PcdFlashFvPostMemorySize)));
+ PeiServicesInstallFvInfo2Ppi (
+ &(((EFI_FIRMWARE_VOLUME_HEADER *) (UINTN) PcdGet32 (PcdFlashFvPostMemoryBase))->FileSystemGuid),
+ (VOID *) (UINTN) PcdGet32 (PcdFlashFvPostMemoryBase),
+ PcdGet32 (PcdFlashFvPostMemorySize),
+ NULL,
+ NULL,
+ 0
+ );
+
+ Status = PeiServicesNotifyPpi (&mExtendedBiosDecodeReadyNotifyList [0]);
+ ASSERT_EFI_ERROR (Status);
+
+ if (BootMode != BOOT_ON_S3_RESUME) {
+ BuildFvHob (
+ (UINTN) FixedPcdGet32 (PcdFlashFvMicrocodeBase),
+ (UINTN) FixedPcdGet32 (PcdFlashFvMicrocodeSize)
+ );
+ DEBUG ((DEBUG_INFO, "Build FlashFvMicrocode Hob - 0x%x, 0x%x\n", PcdGet32 (PcdFlashFvMicrocodeBase), PcdGet32 (PcdFlashFvMicrocodeSize)));
+
+ }
+ }
+
+ //
+ // Report resource HOB for flash FV
+ //
+ BuildResourceDescriptorHob (
+ EFI_RESOURCE_MEMORY_MAPPED_IO,
+ (EFI_RESOURCE_ATTRIBUTE_PRESENT |
+ EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
+ EFI_RESOURCE_ATTRIBUTE_WRITE_PROTECTABLE),
+ (UINTN) PcdGet32 (PcdFlashAreaBaseAddress),
+ (UINTN) PcdGet32 (PcdFlashAreaSize)
+ );
+ BuildMemoryAllocationHob (
+ (UINTN) PcdGet32 (PcdFlashAreaBaseAddress),
+ (UINTN) PcdGet32 (PcdFlashAreaSize),
+ EfiMemoryMappedIO
+ );
+}
+
+
+/**
+ Callback on Extended BIOS Decode Ready Ppi so Extended PostMemory FV is installed to the memory
+ for Extended BIOS Region. The callback is called regardless of Extended BIOS Region support
+ in platform code.
+
+ @param[in] PeiServices General purpose services available to every PEIM.
+ @param[in] NotifyDescriptor The notification structure this PEIM registered on install.
+ @param[in] Ppi The gExtendedBiosDecodeReady PPI. Not used.
+
+ @retval EFI_SUCCESS Always returns EFI_SUCCESS
+**/
+EFI_STATUS
+EFIAPI
+InstallFvExtendedPostMemoryCallback (
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
+ IN VOID *Ppi
+ )
+{
+ DEBUG ((DEBUG_INFO, "Extended BIOS Region is not supported by the image. No FV installed here\n"));
+ return EFI_SUCCESS;
+}
+
+
+/**
+ Callback on Extended BIOS Decode Ready Ppi so Extended Advanced FV is installed to the memory
+ for Extended BIOS Region. The callback is called regardless of Extended BIOS Region support in
+ platform code. Extended Advanced FV contains DXE phase drivers only and may want to be skipped
+ on S3 path for responsiveness.
+
+ @param[in] PeiServices General purpose services available to every PEIM.
+ @param[in] NotifyDescriptor The notification structure this PEIM registered on install.
+ @param[in] Ppi The gExtendedBiosDecodeReady PPI. Not used.
+
+ @retval EFI_SUCCESS Always returns EFI_SUCCESS
+**/
+EFI_STATUS
+EFIAPI
+InstallFvExtendedAdvancedCallback (
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
+ IN VOID *Ppi
+ )
+{
+ DEBUG ((DEBUG_INFO, "Extended BIOS Region is not supported by the image. No FV installed here\n"));
+ return EFI_SUCCESS;
+}
+
+
+/**
+ Debug support function to output detailed information on a firmware volume being installed.
+ Setting DEBUG_PROPERTY_DEBUG_CODE_ENABLED bit of PcdDebugProperyMask lets the function to be
+ included in a module. Refer to DEBUG_CODE macro.
+
+ @param[in] FvHeader Pointer to firmware volume header
+**/
+VOID
+PrintFvHeaderInfo (
+ EFI_FIRMWARE_VOLUME_HEADER *FvHeader
+ )
+{
+ DEBUG_CODE (
+ EFI_FIRMWARE_VOLUME_EXT_HEADER *FvExtHeader;
+ EFI_FFS_FILE_HEADER *FfsHeader;
+
+ DEBUG ((DEBUG_INFO, "[ FV @ 0x%x ] \n", FvHeader));
+ DEBUG ((DEBUG_INFO, " FV File System : %g \n", &FvHeader->FileSystemGuid));
+ if (FvHeader->ExtHeaderOffset != 0) {
+ FvExtHeader = (EFI_FIRMWARE_VOLUME_EXT_HEADER *) ((UINT8 *) FvHeader + FvHeader->ExtHeaderOffset);
+ FfsHeader = (EFI_FFS_FILE_HEADER *) ((UINT8 *) FvExtHeader + FvExtHeader->ExtHeaderSize);
+ FfsHeader = (EFI_FFS_FILE_HEADER *) ALIGN_POINTER (FfsHeader, 8);
+ DEBUG ((DEBUG_INFO, " FV GUID : %g \n", &FvExtHeader->FvName));
+ DEBUG ((DEBUG_INFO, " File GUID : %g \n", &FfsHeader->Name));
+ }
+ );
+}
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Library/PeiReportFvLib/PeiReportFvLib.inf b/Platform/Intel/AlderlakeOpenBoardPkg/Library/PeiReportFvLib/PeiReportFvLib.inf
new file mode 100644
index 0000000000..9e0035d445
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Library/PeiReportFvLib/PeiReportFvLib.inf
@@ -0,0 +1,78 @@
+## @file
+# Component information file for the PEI Report Firmware Volume (FV) library.
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010017
+ BASE_NAME = PeiReportFvLib
+ FILE_GUID = 44328FA5-E4DD-4A15-ABDF-C6584AC363D9
+ VERSION_STRING = 1.0
+ MODULE_TYPE = PEIM
+ LIBRARY_CLASS = ReportFvLib
+
+[LibraryClasses]
+ BaseMemoryLib
+ DebugLib
+ HobLib
+ PeiServicesLib
+ PcdLib
+ MtrrLib
+ ReportStatusCodeLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ MinPlatformPkg/MinPlatformPkg.dec
+ AlderlakeSiliconPkg/SiPkg.dec
+ AlderlakeOpenBoardPkg/OpenBoardPkg.dec
+ IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec
+ UefiCpuPkg/UefiCpuPkg.dec
+
+
+[Sources]
+ PeiReportFvLib.c
+
+[Ppis]
+ gEfiPeiReadOnlyVariable2PpiGuid ## CONSUMES
+ gPeiFvCnvDispatchFlagPpiGuid ## PRODUCES
+ gExtendedBiosDecodeReadyPpiGuid ## CONSUMES
+
+[Guids]
+ gBiosInfoRecoveryGuid
+
+[Pcd]
+ gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTBase ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSize ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryBase ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootBase ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootBase ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityBase ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedBase ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdFlashFvFirmwareBinariesBase ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdFlashFvFirmwareBinariesSize ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdFlashFvOptionalBase ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdFlashFvOptionalSize ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryBase ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemorySize ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdFlashFvExtendedPostMemoryBase ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdFlashFvExtendedPostMemorySize ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdFlashFvExtendedAdvancedBase ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdFlashFvExtendedAdvancedSize ## CONSUMES
+
+ [FixedPcd]
+ gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection ## CONSUMES
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Library/SmmSpiFlashCommonLib/SmmSpiFlashCommonLib.inf b/Platform/Intel/AlderlakeOpenBoardPkg/Library/SmmSpiFlashCommonLib/SmmSpiFlashCommonLib.inf
new file mode 100644
index 0000000000..ea2f464b99
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Library/SmmSpiFlashCommonLib/SmmSpiFlashCommonLib.inf
@@ -0,0 +1,52 @@
+### @file
+# SMM Library instance of Spi Flash Common Library Class
+#
+# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+###
+
+[Defines]
+ INF_VERSION = 0x00010017
+ BASE_NAME = SmmSpiFlashCommonLib
+ FILE_GUID = 9632D96E-E849-4217-9217-DC500B8AAE47
+ VERSION_STRING = 1.0
+ MODULE_TYPE = DXE_SMM_DRIVER
+ LIBRARY_CLASS = SpiFlashCommonLib|DXE_SMM_DRIVER
+ CONSTRUCTOR = SmmSpiFlashCommonLibConstructor
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = IA32 X64
+#
+
+[LibraryClasses]
+ IoLib
+ MemoryAllocationLib
+ BaseLib
+ UefiLib
+ SmmServicesTableLib
+ BaseMemoryLib
+ DebugLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ AlderlakeSiliconPkg/SiPkg.dec
+ AlderlakeOpenBoardPkg/OpenBoardPkg.dec
+
+[Pcd]
+ gSiPkgTokenSpaceGuid.PcdBiosAreaBaseAddress ## CONSUMES
+ gSiPkgTokenSpaceGuid.PcdBiosSize ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdFlashExtendRegionSizeInUse ## CONSUMES
+ gBoardModuleTokenSpaceGuid.PcdFlashExtendRegionOffset ## CONSUMES
+ gPlatformModuleTokenSpaceGuid.PcdExtendedBiosRegionSupport ## CONSUMES
+
+[Sources]
+ SpiFlashCommonSmmLib.c
+ SpiFlashCommon.c
+
+[Protocols]
+ gPchSmmSpiProtocolGuid ## CONSUMES
+
+[Depex.X64.DXE_SMM_DRIVER]
+ gPchSmmSpiProtocolGuid
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Library/SmmSpiFlashCommonLib/SpiFlashCommon.c b/Platform/Intel/AlderlakeOpenBoardPkg/Library/SmmSpiFlashCommonLib/SpiFlashCommon.c
new file mode 100644
index 0000000000..3f7c52ac73
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Library/SmmSpiFlashCommonLib/SpiFlashCommon.c
@@ -0,0 +1,215 @@
+/** @file
+ Wrap EFI_SPI_PROTOCOL to provide some library level interfaces
+ for module use.
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+
+**/
+
+#include <Library/SpiFlashCommon.h>
+#include <Library/IoLib.h>
+
+PCH_SPI_PROTOCOL *mSpiProtocol;
+
+//
+// Variables for boottime and runtime usage.
+//
+UINTN mBiosAreaBaseAddress = 0;
+UINTN mBiosSize = 0;
+UINTN mBiosOffset = 0;
+
+/**
+ Enable block protection on the Serial Flash device.
+
+ @retval EFI_SUCCESS Operation is successful.
+ @retval EFI_DEVICE_ERROR If there is any device errors.
+
+**/
+EFI_STATUS
+EFIAPI
+SpiFlashLock (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+
+ Status = EFI_SUCCESS;
+
+ return Status;
+}
+
+/**
+ Read NumBytes bytes of data from the address specified by
+ PAddress into Buffer.
+
+ @param[in] Address The starting physical address of the read.
+ @param[in,out] NumBytes On input, the number of bytes to read. On output, the number
+ of bytes actually read.
+ @param[out] Buffer The destination data buffer for the read.
+
+ @retval EFI_SUCCESS Operation is successful.
+ @retval EFI_DEVICE_ERROR If there is any device errors.
+
+**/
+EFI_STATUS
+EFIAPI
+SpiFlashRead (
+ IN UINTN Address,
+ IN OUT UINT32 *NumBytes,
+ OUT UINT8 *Buffer
+ )
+{
+ ASSERT ((NumBytes != NULL) && (Buffer != NULL));
+ if ((NumBytes == NULL) || (Buffer == NULL)) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ //
+ // This function is implemented specifically for those platforms
+ // at which the SPI device is memory mapped for read. So this
+ // function just do a memory copy for Spi Flash Read.
+ //
+ CopyMem (Buffer, (VOID *) Address, *NumBytes);
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Write NumBytes bytes of data from Buffer to the address specified by
+ PAddresss.
+
+ @param[in] Address The starting physical address of the write.
+ @param[in,out] NumBytes On input, the number of bytes to write. On output,
+ the actual number of bytes written.
+ @param[in] Buffer The source data buffer for the write.
+
+ @retval EFI_SUCCESS Operation is successful.
+ @retval EFI_DEVICE_ERROR If there is any device errors.
+ @retval EFI_INVALID_PARAMETER Invalid parameter.
+ @retval EFI_BAD_BUFFER_SIZE DataSectionSize in BGUP header exceeds the
+ size ofBIOS Guard script buffer
+
+**/
+EFI_STATUS
+EFIAPI
+SpiFlashWrite (
+ IN UINTN Address,
+ IN OUT UINT32 *NumBytes,
+ IN UINT8 *Buffer
+ )
+{
+ EFI_STATUS Status;
+ UINTN Offset;
+ UINT32 Length;
+ UINT32 RemainingBytes;
+
+ ASSERT ((NumBytes != NULL) && (Buffer != NULL));
+ if ((NumBytes == NULL) || (Buffer == NULL)) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ ASSERT (Address >= mBiosAreaBaseAddress);
+ if (Address < mBiosAreaBaseAddress) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ Offset = Address - mBiosAreaBaseAddress;
+
+ ASSERT ((*NumBytes + Offset) <= mBiosSize);
+ if ((*NumBytes + Offset) > mBiosSize) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ Status = EFI_SUCCESS;
+ RemainingBytes = *NumBytes;
+
+ while (RemainingBytes > 0) {
+ if (RemainingBytes > SECTOR_SIZE_4KB) {
+ Length = SECTOR_SIZE_4KB;
+ } else {
+ Length = RemainingBytes;
+ }
+ Status = mSpiProtocol->FlashWrite (
+ mSpiProtocol,
+ FlashRegionBios,
+ (UINT32) Offset,
+ Length,
+ Buffer
+ );
+ if (EFI_ERROR (Status)) {
+ break;
+ }
+ RemainingBytes -= Length;
+ Offset += Length;
+ Buffer += Length;
+ }
+
+ //
+ // Actual number of bytes written
+ //
+ *NumBytes -= RemainingBytes;
+
+ return Status;
+}
+
+/**
+ Erase the block starting at Address.
+
+ @param[in] Address The starting physical address of the block to be erased.
+ This library assume that caller garantee that the PAddress
+ is at the starting address of this block.
+ @param[in] NumBytes On input, the number of bytes of the logical block to be erased.
+ On output, the actual number of bytes erased.
+
+ @retval EFI_SUCCESS. Operation is successful.
+ @retval EFI_DEVICE_ERROR If there is any device errors.
+ @retval EFI_INVALID_PARAMETER Invalid parameter.
+
+**/
+EFI_STATUS
+EFIAPI
+SpiFlashBlockErase (
+ IN UINTN Address,
+ IN UINTN *NumBytes
+ )
+{
+ EFI_STATUS Status;
+ UINTN Offset;
+ UINTN RemainingBytes;
+
+ ASSERT (NumBytes != NULL);
+ if (NumBytes == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ ASSERT (Address >= mBiosAreaBaseAddress);
+ if (Address < mBiosAreaBaseAddress) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ Offset = Address - mBiosAreaBaseAddress;
+
+ ASSERT ((*NumBytes % SECTOR_SIZE_4KB) == 0);
+ if ((*NumBytes % SECTOR_SIZE_4KB) != 0) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ ASSERT ((*NumBytes + Offset) <= mBiosSize);
+ if ((*NumBytes + Offset) > mBiosSize) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ Status = EFI_SUCCESS;
+ RemainingBytes = *NumBytes;
+
+ Status = mSpiProtocol->FlashErase (
+ mSpiProtocol,
+ FlashRegionBios,
+ (UINT32) Offset,
+ (UINT32) RemainingBytes
+ );
+ return Status;
+}
+
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Library/SmmSpiFlashCommonLib/SpiFlashCommonSmmLib.c b/Platform/Intel/AlderlakeOpenBoardPkg/Library/SmmSpiFlashCommonLib/SpiFlashCommonSmmLib.c
new file mode 100644
index 0000000000..7d74162d43
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Library/SmmSpiFlashCommonLib/SpiFlashCommonSmmLib.c
@@ -0,0 +1,64 @@
+/** @file
+ SMM Library instance of SPI Flash Common Library Class
+
+ Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+
+**/
+
+#include <Library/SpiFlashCommon.h>
+#include <Library/SmmServicesTableLib.h>
+
+extern PCH_SPI_PROTOCOL *mSpiProtocol;
+
+extern UINTN mBiosAreaBaseAddress;
+extern UINTN mBiosSize;
+extern UINTN mBiosOffset;
+
+/**
+ The library constructuor.
+
+ The function does the necessary initialization work for this library
+ instance.
+
+ @param[in] ImageHandle The firmware allocated handle for the UEFI image.
+ @param[in] SystemTable A pointer to the EFI system table.
+
+ @retval EFI_SUCCESS The function always return EFI_SUCCESS for now.
+ It will ASSERT on error for debug version.
+ @retval EFI_ERROR Please reference LocateProtocol for error code details.
+**/
+EFI_STATUS
+EFIAPI
+SmmSpiFlashCommonLibConstructor (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUS Status;
+ UINT32 BaseAddr;
+ UINT32 RegionSize;
+
+#if FixedPcdGetBool(PcdExtendedBiosRegionSupport) == 0
+ mBiosAreaBaseAddress = (UINTN)PcdGet32 (PcdBiosAreaBaseAddress);
+ mBiosSize = (UINTN)PcdGet32 (PcdBiosSize);
+#else
+ mBiosAreaBaseAddress = (UINTN) PcdGet32 (PcdBiosAreaBaseAddress) + (UINTN) PcdGet32 (PcdFlashExtendRegionOffset);
+ mBiosSize = 0x1000000 + (UINTN) PcdGet32 (PcdFlashExtendRegionSizeInUse);
+#endif
+ //
+ // Locate the SMM SPI protocol.
+ //
+ Status = gSmst->SmmLocateProtocol (
+ &gPchSmmSpiProtocolGuid,
+ NULL,
+ (VOID **) &mSpiProtocol
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ mSpiProtocol->GetRegionAddress (mSpiProtocol, FlashRegionBios, &BaseAddr, &RegionSize);
+ mBiosOffset = BaseAddr;
+
+ return Status;
+}
--
2.36.1.windows.1
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2023-06-14 19:17 ` [PATCH 1/6] AlderlakeOpenBoardPkg: Add package and headers Saloni Kasbekar
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2023-06-14 19:17 ` [PATCH 4/6] AlderlakeOpenBoardPkg: Add ACPI module Saloni Kasbekar
2023-06-14 19:17 ` [PATCH 5/6] AlderlakeOpenBoardPkg: Adds the Policy Module Saloni Kasbekar
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