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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB03.amd.com; pr=C Received: from SATLEXMB03.amd.com (165.204.84.17) by BN8NAM11FT024.mail.protection.outlook.com (10.13.177.38) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6156.19 via Frontend Transport; Wed, 15 Mar 2023 07:11:39 +0000 Received: from SATLEXMB03.amd.com (10.181.40.144) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.34; Wed, 15 Mar 2023 02:11:38 -0500 Received: from BLR-LAB-SFW01.amd.com (10.180.168.240) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server id 15.1.2375.34 via Frontend Transport; Wed, 15 Mar 2023 02:11:36 -0500 From: "Abdul Lateef Attar" To: CC: Abdul Lateef Attar , Ard Biesheuvel , Leif Lindholm Subject: [PATCH v1 2/4] Platform/AMD/PlatformPkg: Adds PciHotPlug init protocol implementation Date: Wed, 15 Mar 2023 12:41:13 +0530 Message-ID: X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 Return-Path: AbdulLateef.Attar@amd.com X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT024:EE_|DS0PR12MB7703:EE_ X-MS-Office365-Filtering-Correlation-Id: 3f4621d2-c385-43cd-2e47-08db252485b9 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Mar 2023 07:11:39.5144 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3f4621d2-c385-43cd-2e47-08db252485b9 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT024.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB7703 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain Adds PCI hotplug init protocol implementation. Cc: Ard Biesheuvel Cc: Leif Lindholm Cc: Abner Chang --- Platform/AMD/PlatformPkg/PlatformPkg.dec | 16 + Platform/AMD/PlatformPkg/PlatformPkg.dsc | 23 ++ .../PlatformPkg/PciHotPlug/PciHotPlugInit.inf | 41 +++ .../PlatformPkg/PciHotPlug/PciHotPlugInit.c | 340 ++++++++++++++++++ 4 files changed, 420 insertions(+) create mode 100644 Platform/AMD/PlatformPkg/PciHotPlug/PciHotPlugInit.inf create mode 100644 Platform/AMD/PlatformPkg/PciHotPlug/PciHotPlugInit.c diff --git a/Platform/AMD/PlatformPkg/PlatformPkg.dec b/Platform/AMD/Platfo= rmPkg/PlatformPkg.dec index 6155860979cb..1bc38d6025c3 100644 --- a/Platform/AMD/PlatformPkg/PlatformPkg.dec +++ b/Platform/AMD/PlatformPkg/PlatformPkg.dec @@ -13,3 +13,19 @@ [Defines] PACKAGE_NAME =3D PlatformPkg PACKAGE_GUID =3D 38FBA311-E2AA-4620-9A90-9A23753D1878 PACKAGE_VERSION =3D 0.1 + +[Guids] + gPlatformPkgTokenSpaceGuid =3D { 0x95ECA58D, 0x09B6, 0x4420, { 0xB4,= 0xE7, 0x01, 0x7F, 0x6A, 0x5B, 0x26, 0x0F }} + +[PcdsDynamic, PcdsDynamicEx] + # + # PCI HotPlug Resource Padding + # + # IO Resource padding in bytes, default 4KB + gPlatformPkgTokenSpaceGuid.PcdPciHotPlugResourcePadIO|0x00001000|UINT64|= 0x10000000 + # PreFetch Memory padding in bytes, default 2MB + gPlatformPkgTokenSpaceGuid.PcdPciHotPlugResourcePadPMem|0x00200000|UINT6= 4|0x10000001 + # Non-PreFetch Memory padding in bytes, default 1MB + gPlatformPkgTokenSpaceGuid.PcdPciHotPlugResourcePadMem|0x00100000|UINT64= |0x10000002 + # PCI bus padding, number of bus to reserve, default 2 bus + gPlatformPkgTokenSpaceGuid.PcdPciHotPlugResourcePadBus|2|UINT8|0x1000000= 3 diff --git a/Platform/AMD/PlatformPkg/PlatformPkg.dsc b/Platform/AMD/Platfo= rmPkg/PlatformPkg.dsc index 704566b9ea73..9a693070ab3f 100644 --- a/Platform/AMD/PlatformPkg/PlatformPkg.dsc +++ b/Platform/AMD/PlatformPkg/PlatformPkg.dsc @@ -16,5 +16,28 @@ [Defines] BUILD_TARGETS =3D DEBUG | RELEASE | NOOPT SUPPORTED_ARCHITECTURES =3D IA32 | X64 =20 + [Packages] PlatformPkg/PlatformPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + +[LibraryClasses.Common] + UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntry= Point.inf + UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBoo= tServicesTableLib.inf + DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.in= f + MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAll= ocationLib.inf + BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf + BaseLib|MdePkg/Library/BaseLib/BaseLib.inf + PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf + RegisterFilterLib|MdePkg/Library/RegisterFilterLibNull/RegisterFilterLib= Null.inf + SerialPortLib|MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPort= Lib16550.inf + PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf + DebugPrintErrorLevelLib|MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseD= ebugPrintErrorLevelLib.inf + IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf + PlatformHookLib|MdeModulePkg/Library/BasePlatformHookLibNull/BasePlatfor= mHookLibNull.inf + PciLib|MdePkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf + PciExpressLib|MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf + +[Components.X64] + PlatformPkg/PciHotPlug/PciHotPlugInit.inf diff --git a/Platform/AMD/PlatformPkg/PciHotPlug/PciHotPlugInit.inf b/Platf= orm/AMD/PlatformPkg/PciHotPlug/PciHotPlugInit.inf new file mode 100644 index 000000000000..0079c4acf14e --- /dev/null +++ b/Platform/AMD/PlatformPkg/PciHotPlug/PciHotPlugInit.inf @@ -0,0 +1,41 @@ +## @file +# This driver implements EFI_PCI_HOT_PLUG_INIT_PROTOCOL. +# Adds resource padding information, for PCIe hotplug purposes. +# +# Copyright (C) 2023 Advanced Micro Devices, Inc. All rights reserved +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +[Defines] + INF_VERSION =3D 1.29 + BASE_NAME =3D PciHotPlugInit + FILE_GUID =3D 8B67D95F-78B7-484F-8F16-5F22AB388B0C + MODULE_TYPE =3D DXE_DRIVER + VERSION_STRING =3D 0.1 + ENTRY_POINT =3D PciHotPlugInitialize + +[Sources] + PciHotPlugInit.c + +[Packages] + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + PlatformPkg/PlatformPkg.dec + +[LibraryClasses] + UefiDriverEntryPoint + UefiBootServicesTableLib + DebugLib + MemoryAllocationLib + +[Protocols] + gEfiPciHotPlugInitProtocolGuid + +[Pcd] + gPlatformPkgTokenSpaceGuid.PcdPciHotPlugResourcePadIO + gPlatformPkgTokenSpaceGuid.PcdPciHotPlugResourcePadPMem + gPlatformPkgTokenSpaceGuid.PcdPciHotPlugResourcePadMem + gPlatformPkgTokenSpaceGuid.PcdPciHotPlugResourcePadBus + +[Depex] + TRUE diff --git a/Platform/AMD/PlatformPkg/PciHotPlug/PciHotPlugInit.c b/Platfor= m/AMD/PlatformPkg/PciHotPlug/PciHotPlugInit.c new file mode 100644 index 000000000000..7a3c8e024e4d --- /dev/null +++ b/Platform/AMD/PlatformPkg/PciHotPlug/PciHotPlugInit.c @@ -0,0 +1,340 @@ +/** @file + This file declares EFI PCI Hot Plug Init Protocol. + + This protocol provides the necessary functionality to initialize the Hot= Plug + Controllers (HPCs) and the buses that they control. This protocol also p= rovides + information regarding resource padding. + + @par Note: + This source has the reference of OVMF PciHotPluginit.c and Intel platf= orm PciHotPlug.c. + + This protocol is required only on platforms that support one or more P= CI Hot + Plug* slots or CardBus sockets. + + The EFI_PCI_HOT_PLUG_INIT_PROTOCOL provides a mechanism for the PCI bus = enumerator + to properly initialize the HPCs and CardBus sockets that require initial= ization. + The HPC initialization takes place before the PCI enumeration process is= complete. + There cannot be more than one instance of this protocol in a system. Thi= s protocol + is installed on its own separate handle. + + Because the system may include multiple HPCs, one instance of this proto= col + should represent all of them. The protocol functions use the device path= of + the HPC to identify the HPC. When the PCI bus enumerator finds a root HP= C, it + will call EFI_PCI_HOT_PLUG_INIT_PROTOCOL.InitializeRootHpc(). If Initial= izeRootHpc() + is unable to initialize a root HPC, the PCI enumerator will ignore that = root HPC + and continue the enumeration process. If the HPC is not initialized, the= devices + that it controls may not be initialized, and no resource padding will be= provided. + + From the standpoint of the PCI bus enumerator, HPCs are divided into the= following + two classes: + + - Root HPC: + These HPCs must be initialized by calling InitializeRootHpc() duri= ng the + enumeration process. These HPCs will also require resource padding= . The + platform code must have a priori knowledge of these devices and mu= st know + how to initialize them. There may not be any way to access their P= CI + configuration space before the PCI enumerator programs all the ups= tream + bridges and thus enables the path to these devices. The PCI bus en= umerator + is responsible for determining the PCI bus address of the HPC befo= re it + calls InitializeRootHpc(). + - Nonroot HPC: + These HPCs will not need explicit initialization during enumeratio= n process. + These HPCs will require resource padding. The platform code does n= ot have + to have a priori knowledge of these devices. + + Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.
+ Copyright (C) 2016, Red Hat, Inc.
+ Copyright (C) 2023 Advanced Micro Devices, Inc. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + This Protocol is defined in UEFI Platform Initialization Specification 1= .2 + Volume 5: Standards + +**/ + +#include +#include +#include +#include +#include +#include + +// +// The protocol interface this driver produces. +// +STATIC EFI_PCI_HOT_PLUG_INIT_PROTOCOL mPciHotPlugInit; + +/** + Returns a list of root Hot Plug Controllers (HPCs) that require initiali= zation + during the boot process. + + This procedure returns a list of root HPCs. The PCI bus driver must init= ialize + these controllers during the boot process. The PCI bus driver may or may= not be + able to detect these HPCs. If the platform includes a PCI-to-CardBus bri= dge, it + can be included in this list if it requires initialization. The HpcList= must be + self consistent. An HPC cannot control any of its parent buses. Only one= HPC can + control a PCI bus. Because this list includes only root HPCs, no HPC in = the list + can be a child of another HPC. This policy must be enforced by the + EFI_PCI_HOT_PLUG_INIT_PROTOCOL. The PCI bus driver may not check for s= uch + invalid conditions. The callee allocates the buffer HpcList + + @param[in] This Pointer to the EFI_PCI_HOT_PLUG_INIT_PROTOCOL ins= tance. + @param[out] HpcCount The number of root HPCs that were returned. + @param[out] HpcList The list of root HPCs. HpcCount defines the numbe= r of + elements in this list. + + @retval EFI_SUCCESS HpcList was returned. + @retval EFI_OUT_OF_RESOURCES HpcList was not returned due to insuffic= ient + resources. + @retval EFI_INVALID_PARAMETER HpcCount is NULL or HpcList is NULL. + +**/ +EFI_STATUS +EFIAPI +GetRootHpcList ( + IN EFI_PCI_HOT_PLUG_INIT_PROTOCOL *This, + OUT UINTN *HpcCount, + OUT EFI_HPC_LOCATION **HpcList + ) +{ + if ((HpcCount =3D=3D NULL) || (HpcList =3D=3D NULL)) { + return EFI_INVALID_PARAMETER; + } + + // + // Platform BIOS not doing any extra/special HPC initialization + // Hence returning the HpcCount as zero and HpcList as NULL + // + *HpcCount =3D 0; + *HpcList =3D NULL; + + return EFI_SUCCESS; +} + +/** + Initializes one root Hot Plug Controller (HPC). This process may causes + initialization of its subordinate buses. + + This function initializes the specified HPC. At the end of initializatio= n, + the hot-plug slots or sockets (controlled by this HPC) are powered and a= re + connected to the bus. All the necessary registers in the HPC are set up.= For + a Standard (PCI) Hot Plug Controller (SHPC), the registers that must be = set + up are defined in the PCI Standard Hot Plug Controller and Subsystem + Specification. + + @param[in] This Pointer to the EFI_PCI_HOT_PLUG_INIT_PROTOCO= L instance. + @param[in] HpcDevicePath The device path to the HPC that is being ini= tialized. + @param[in] HpcPciAddress The address of the HPC function on the PCI b= us. + @param[in] Event The event that should be signaled when the H= PC + initialization is complete. Set to NULL if = the + caller wants to wait until the entire initia= lization + process is complete. + @param[out] HpcState The state of the HPC hardware. The state is + EFI_HPC_STATE_INITIALIZED or EFI_HPC_STATE_E= NABLED. + + @retval EFI_SUCCESS If Event is NULL, the specific HPC was s= uccessfully + initialized. If Event is not NULL, Event= will be + signaled at a later time when initializa= tion is complete. + @retval EFI_UNSUPPORTED This instance of EFI_PCI_HOT_PLUG_INIT_P= ROTOCOL + does not support the specified HPC. + @retval EFI_OUT_OF_RESOURCES Initialization failed due to insufficien= t + resources. + @retval EFI_INVALID_PARAMETER HpcState is NULL. + +**/ +EFI_STATUS +EFIAPI +InitializeRootHpc ( + IN EFI_PCI_HOT_PLUG_INIT_PROTOCOL *This, + IN EFI_DEVICE_PATH_PROTOCOL *HpcDevicePath, + IN UINT64 HpcPciAddress, + IN EFI_EVENT Event, OPTIONAL + OUT EFI_HPC_STATE *HpcState + ) +{ + if (HpcState =3D=3D NULL) { + return EFI_INVALID_PARAMETER; + } + + // + // This Platform doesnt have any non-enumerated HPC. + // Hence no extra initialization required from Platform BIOS. + // + return EFI_UNSUPPORTED; +} + +/** + Returns the resource padding that is required by the PCI bus that is con= trolled + by the specified Hot Plug Controller (HPC). + + This function returns the resource padding that is required by the PCI b= us that + is controlled by the specified HPC. This member function is called for a= ll the + root HPCs and nonroot HPCs that are detected by the PCI bus enumerator. = This + function will be called before PCI resource allocation is completed. Thi= s function + must be called after all the root HPCs, with the possible exception of a + PCI-to-CardBus bridge, have completed initialization. + + @param[in] This Pointer to the EFI_PCI_HOT_PLUG_INIT_PROTOCO= L instance. + @param[in] HpcDevicePath The device path to the HPC. + @param[in] HpcPciAddress The address of the HPC function on the PCI b= us. + @param[in] HpcState The state of the HPC hardware. + @param[out] Padding The amount of resource padding that is requi= red by the + PCI bus under the control of the specified H= PC. + @param[out] Attributes Describes how padding is accounted for. The = padding + is returned in the form of ACPI 2.0 resource= descriptors. + + @retval EFI_SUCCESS The resource padding was successfully re= turned. + @retval EFI_UNSUPPORTED This instance of the EFI_PCI_HOT_PLUG_IN= IT_PROTOCOL + does not support the specified HPC. + @retval EFI_NOT_READY This function was called before HPC init= ialization + is complete. + @retval EFI_INVALID_PARAMETER HpcState or Padding or Attributes is NUL= L. + @retval EFI_OUT_OF_RESOURCES ACPI 2.0 resource descriptors for Paddin= g + cannot be allocated due to insufficient = resources. + +**/ +EFI_STATUS +EFIAPI +GetResourcePadding ( + IN EFI_PCI_HOT_PLUG_INIT_PROTOCOL *This, + IN EFI_DEVICE_PATH_PROTOCOL *HpcDevicePath, + IN UINT64 HpcPciAddress, + OUT EFI_HPC_STATE *HpcState, + OUT VOID **Padding, + OUT EFI_HPC_PADDING_ATTRIBUTES *Attributes + ) +{ + EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *PaddingResource; + + // + // Need total 5 resources + // 1 - IO resource + // 2 - Mem resource + // 3 - PMem resource + // 4 - Bus resource + // 5 - end tag resource + PaddingResource =3D AllocateZeroPool (4 * sizeof (EFI_ACPI_ADDRESS_SPACE= _DESCRIPTOR) + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR)); + if (PaddingResource =3D=3D NULL) { + return EFI_OUT_OF_RESOURCES; + } + + *Padding =3D (VOID *)PaddingResource; + + // + // Padding for bus + // + *Attributes =3D EfiPaddingPciBus; + + PaddingResource->Desc =3D ACPI_ADDRESS_SPACE_DESCRIPTOR; + PaddingResource->Len =3D (UINT16)( + sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPT= OR) - + OFFSET_OF ( + EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR, + ResType + ) + ); + PaddingResource->ResType =3D ACPI_ADDRESS_SPACE_TYPE_BUS; + PaddingResource->GenFlag =3D 0x0; + PaddingResource->SpecificFlag =3D 0; + PaddingResource->AddrRangeMin =3D 0; + PaddingResource->AddrRangeMax =3D 0; + PaddingResource->AddrLen =3D PcdGet8 (PcdPciHotPlugResourcePadBus); + + // + // Padding for non-prefetchable memory + // + PaddingResource++; + PaddingResource->Desc =3D ACPI_ADDRESS_SPACE_DESCRIPTOR; + PaddingResource->Len =3D (UINT16)( + sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPT= OR) - + OFFSET_OF ( + EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR, + ResType + ) + ); + PaddingResource->ResType =3D ACPI_ADDRESS_SPACE_TYPE_MEM; + PaddingResource->GenFlag =3D 0x0; + PaddingResource->AddrSpaceGranularity =3D 32; + PaddingResource->SpecificFlag =3D EFI_ACPI_MEMORY_RESOURCE_SPECI= FIC_FLAG_NON_CACHEABLE; + PaddingResource->AddrRangeMin =3D 0; + PaddingResource->AddrLen =3D PcdGet64 (PcdPciHotPlugResourc= ePadMem); + PaddingResource->AddrRangeMax =3D PaddingResource->AddrLen - 1; + + // + // Padding for prefetchable memory + // + PaddingResource++; + PaddingResource->Desc =3D ACPI_ADDRESS_SPACE_DESCRIPTOR; + PaddingResource->Len =3D (UINT16)( + sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPT= OR) - + OFFSET_OF ( + EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR, + ResType + ) + ); + PaddingResource->ResType =3D ACPI_ADDRESS_SPACE_TYPE_MEM; + PaddingResource->GenFlag =3D 0x0; + PaddingResource->AddrSpaceGranularity =3D 32; + PaddingResource->SpecificFlag =3D EFI_ACPI_MEMORY_RESOURCE_SPECI= FIC_FLAG_CACHEABLE_PREFETCHABLE; + PaddingResource->AddrLen =3D PcdGet64 (PcdPciHotPlugResourc= ePadPMem); + PaddingResource->AddrRangeMax =3D PaddingResource->AddrLen - 1; + + // + // Padding for I/O + // + PaddingResource++; + PaddingResource->Desc =3D ACPI_ADDRESS_SPACE_DESCRIPTOR; + PaddingResource->Len =3D (UINT16)( + sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPT= OR) - + OFFSET_OF ( + EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR, + ResType + ) + ); + PaddingResource->ResType =3D ACPI_ADDRESS_SPACE_TYPE_IO; + PaddingResource->GenFlag =3D 0x0; + PaddingResource->SpecificFlag =3D 0; + PaddingResource->AddrRangeMin =3D 0; + PaddingResource->AddrLen =3D PcdGet64 (PcdPciHotPlugResourcePadIO); + PaddingResource->AddrRangeMax =3D PaddingResource->AddrLen - 1; + + // + // Terminate the entries. + // + PaddingResource++; + ((EFI_ACPI_END_TAG_DESCRIPTOR *)PaddingResource)->Desc =3D ACPI_END_= TAG_DESCRIPTOR; + ((EFI_ACPI_END_TAG_DESCRIPTOR *)PaddingResource)->Checksum =3D 0x0; + + *HpcState =3D EFI_HPC_STATE_INITIALIZED | EFI_HPC_STATE_ENABLED; + + return EFI_SUCCESS; +} + +/** + Entry point for this driver. + + @param[in] ImageHandle Image handle of this driver. + @param[in] SystemTable Pointer to SystemTable. + + @retval EFI_SUCESS Driver has loaded successfully. + @return Error codes from lower level functions. + +**/ +EFI_STATUS +EFIAPI +PciHotPlugInitialize ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + mPciHotPlugInit.GetRootHpcList =3D GetRootHpcList; + mPciHotPlugInit.InitializeRootHpc =3D InitializeRootHpc; + mPciHotPlugInit.GetResourcePadding =3D GetResourcePadding; + return gBS->InstallMultipleProtocolInterfaces ( + &ImageHandle, + &gEfiPciHotPlugInitProtocolGuid, + &mPciHotPlugInit, + NULL + ); +} --=20 2.25.1