From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=216.228.121.65; helo=hqemgate16.nvidia.com; envelope-from=jbrasen@nvidia.com; receiver=edk2-devel@lists.01.org Received: from hqemgate16.nvidia.com (hqemgate16.nvidia.com [216.228.121.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 08D03211648B7 for ; Tue, 9 Oct 2018 10:51:05 -0700 (PDT) Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 09 Oct 2018 10:51:07 -0700 Received: from HQMAIL101.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Tue, 09 Oct 2018 10:51:04 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Tue, 09 Oct 2018 10:51:04 -0700 Received: from HQMAIL102.nvidia.com (172.18.146.10) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Tue, 9 Oct 2018 17:51:04 +0000 Received: from HQMAIL105.nvidia.com (172.20.187.12) by HQMAIL102.nvidia.com (172.18.146.10) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Tue, 9 Oct 2018 17:51:04 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1395.4 via Frontend Transport; Tue, 9 Oct 2018 17:51:04 +0000 Received: from jbrasen-ux.nvidia.com (Not Verified[10.28.48.113]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Tue, 09 Oct 2018 10:51:04 -0700 From: Jeff Brasen To: CC: Jeff Brasen Date: Tue, 9 Oct 2018 11:50:36 -0600 Message-ID: X-Mailer: git-send-email 2.7.4 In-Reply-To: References: X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1539107467; bh=FWcgjBev7sYKQlEHuP48GRphfCJ9HsswCacceJD7+8U=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=bIGIWMWyGu449NutTzj1/Qs9JtDb/pyxAk91WPSxjC8KxKdidMsmERap1z+rBPT5L dJJno2I1/59HHKW3QEX1JB2T6AbGDabHn2DnQMsAHzSJNpJfeAmJvtgDy+MYCLEbZ8 GCZCAxycsucgYDkdhFOfBtN3y1PlxfQkr7/eHuE9h/BXJPy/nuSu0Yu7CqMJBz9FUj 69+dytXI3X3P3V/GPuA04kVVBtlHp0dBQFPfxdCconoEf6qUglKAfgjoyHucnaRgTX 9UKpgExYAM2cE8zRmtPi6hPLErvDRgjNGb58Mz/ng10dUB+4fsYrPYIPNXlBQvs8wz mQHyEr+62cVWQ== Subject: [PATCH v2 1/2] MdeModulePkg/SdMmcPciHcDxe: Add controller version defines X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 09 Oct 2018 17:51:05 -0000 Content-Type: text/plain Add SDHCI controller defines, this is useful as the version in the register does not explictly map to a specification version. For example vesion 4.10 of the specification is version 0x04. https://bugzilla.tianocore.org/show_bug.cgi?id=1233 Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jeff Brasen --- MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c | 4 ++-- MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c | 2 +- MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h | 10 ++++++++++ 3 files changed, 13 insertions(+), 3 deletions(-) diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c index 8c93933..d3f77ed 100644 --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c @@ -978,9 +978,9 @@ SdCardIdentification ( return Status; } - if ((ControllerVer & 0xFF) == 2) { + if ((ControllerVer & 0xFF) == SD_MMC_HC_CTRL_VER_300) { S18r = TRUE; - } else if (((ControllerVer & 0xFF) == 0) || ((ControllerVer & 0xFF) == 1)) { + } else if (((ControllerVer & 0xFF) == SD_MMC_HC_CTRL_VER_100) || ((ControllerVer & 0xFF) == SD_MMC_HC_CTRL_VER_200)) { S18r = FALSE; } else { ASSERT (FALSE); diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c index 25771dc..3b9a184 100644 --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c @@ -782,7 +782,7 @@ SdMmcHcClockSupply ( // // Set SDCLK Frequency Select and Internal Clock Enable fields in Clock Control register. // - if ((ControllerVer & 0xFF) == 2) { + if ((ControllerVer & 0xFF) == SD_MMC_HC_CTRL_VER_300) { ASSERT (Divisor <= 0x3FF); ClockCtrl = ((Divisor & 0xFF) << 8) | ((Divisor & 0x300) >> 2); } else if (((ControllerVer & 0xFF) == 0) || ((ControllerVer & 0xFF) == 1)) { diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h index e389d52..7e3f588 100644 --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h @@ -135,6 +135,16 @@ typedef struct { UINT32 Hs400:1; // bit 63 } SD_MMC_HC_SLOT_CAP; +// +// SD Host controller version +// +#define SD_MMC_HC_CTRL_VER_100 0x00 +#define SD_MMC_HC_CTRL_VER_200 0x01 +#define SD_MMC_HC_CTRL_VER_300 0x02 +#define SD_MMC_HC_CTRL_VER_400 0x03 +#define SD_MMC_HC_CTRL_VER_410 0x04 +#define SD_MMC_HC_CTRL_VER_420 0x05 + /** Dump the content of SD/MMC host controller's Capability Register. -- 2.7.4