From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: redhat.com, ip: 209.132.183.28, mailfrom: lersek@redhat.com) Received: from mx1.redhat.com (mx1.redhat.com [209.132.183.28]) by groups.io with SMTP; Tue, 30 Apr 2019 03:31:11 -0700 Received: from smtp.corp.redhat.com (int-mx02.intmail.prod.int.phx2.redhat.com [10.5.11.12]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 4034C307D97F; Tue, 30 Apr 2019 10:31:11 +0000 (UTC) Received: from lacos-laptop-7.usersys.redhat.com (ovpn-121-42.rdu2.redhat.com [10.10.121.42]) by smtp.corp.redhat.com (Postfix) with ESMTP id 3381970582; Tue, 30 Apr 2019 10:31:10 +0000 (UTC) Subject: Re: [Patch V2 4/6] UefiCpuPkg/MpInitLib: Avoid MSR_IA32_APIC_BASE for single core To: Michael D Kinney , devel@edk2.groups.io Cc: Eric Dong , Ray Ni References: <20190430013012.24008-1-michael.d.kinney@intel.com> <20190430013012.24008-5-michael.d.kinney@intel.com> From: "Laszlo Ersek" Message-ID: Date: Tue, 30 Apr 2019 12:31:09 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.9.1 MIME-Version: 1.0 In-Reply-To: <20190430013012.24008-5-michael.d.kinney@intel.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.12 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.48]); Tue, 30 Apr 2019 10:31:11 +0000 (UTC) Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Hi Mike, On 04/30/19 03:30, Michael D Kinney wrote: > Avoid access to MSR_IA32_APIC_BASE that may not be supported > on single core CPUs. If PcdCpuMaxLogicalProcessorNumber is 1, > then there is only one CPU that must be the BSP. > > Cc: Eric Dong > Cc: Ray Ni > Cc: Laszlo Ersek > Signed-off-by: Michael D Kinney > --- > UefiCpuPkg/Library/MpInitLib/PeiMpLib.c | 15 ++++++++++++++- > 1 file changed, 14 insertions(+), 1 deletion(-) > > diff --git a/UefiCpuPkg/Library/MpInitLib/PeiMpLib.c b/UefiCpuPkg/Library/MpInitLib/PeiMpLib.c > index 35dff91fd2..5488049c08 100644 > --- a/UefiCpuPkg/Library/MpInitLib/PeiMpLib.c > +++ b/UefiCpuPkg/Library/MpInitLib/PeiMpLib.c > @@ -1,7 +1,7 @@ > /** @file > MP initialize support functions for PEI phase. > > - Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.
> + Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.
> SPDX-License-Identifier: BSD-2-Clause-Patent > > **/ > @@ -101,6 +101,19 @@ GetCpuMpData ( > MSR_IA32_APIC_BASE_REGISTER ApicBaseMsr; > IA32_DESCRIPTOR Idtr; > > + // > + // If there is only 1 CPU, then it must be the BSP. This avoids an access to > + // MSR_IA32_APIC_BASE that may not be supported on single core CPUs. > + // > + if (PcdGet32 (PcdCpuMaxLogicalProcessorNumber) == 1) { this PcdGet32() call has the same issue as in v1. It is unsafe because: - if the platform makes PcdCpuMaxLogicalProcessorNumber a dynamic or dynamic-ex PCD, then the above call will result in a PPI member function invocation, - and said invocation may be executed on an AP, not necessarily on the BSP. But, APs must not call PPI member functions, to my knowledge. We can certainly use a PCD here, but both UefiCpuPkg.dec, and the code added here, must prevent platforms from making that PCD dynamic or dynamic-ex. Thanks Laszlo > + CpuMpData = GetCpuMpDataFromGuidedHob (); > + ASSERT (CpuMpData != NULL); > + return CpuMpData; > + } > + > + // > + // Otherwise use MSR_IA32_APIC_BASE to determine if the CPU is BSP or AP. > + // > ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE); > if (ApicBaseMsr.Bits.BSP == 1) { > CpuMpData = GetCpuMpDataFromGuidedHob (); >