From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=134.134.136.126; helo=mga18.intel.com; envelope-from=ruiyu.ni@intel.com; receiver=edk2-devel@lists.01.org Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 05BA1211518E1 for ; Fri, 21 Sep 2018 01:43:54 -0700 (PDT) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga106.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 21 Sep 2018 01:43:53 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.54,284,1534834800"; d="scan'208";a="93665044" Received: from ray-dev.ccr.corp.intel.com (HELO [10.239.9.8]) ([10.239.9.8]) by orsmga002.jf.intel.com with ESMTP; 21 Sep 2018 01:43:52 -0700 To: Eric Dong , edk2-devel@lists.01.org Cc: Michael D Kinney , Laszlo Ersek References: <20180921074133.9140-1-eric.dong@intel.com> <20180921074133.9140-9-eric.dong@intel.com> From: "Ni, Ruiyu" Message-ID: Date: Fri, 21 Sep 2018 16:44:47 +0800 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:52.0) Gecko/20100101 Thunderbird/52.9.1 MIME-Version: 1.0 In-Reply-To: <20180921074133.9140-9-eric.dong@intel.com> Subject: Re: [Patch v2 08/14] UefiCpuPkg/Include/Register/ArchitecturalMsr.h: Change structure definition. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 21 Sep 2018 08:43:54 -0000 Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit On 9/21/2018 3:41 PM, Eric Dong wrote: > UINT32 User:1; > - UINT32 Reserved1:2; > + /// > + /// [Bit 4] PwrEvtEn. > + /// > + UINT32 PwrEvtEn:1; > + /// > + /// [Bit 5] FUPonPTW. > + /// > + UINT32 FUPonPTW:1; > /// > /// [Bit 6] FabricEn. If (CPUID.(EAX=07H, ECX=0):ECX[3] = 1). > /// > @@ -4672,7 +4679,10 @@ typedef union { > /// [Bit 11] DisRETC. > /// > UINT32 DisRETC:1; > - UINT32 Reserved2:1; > + /// > + /// [Bit 12] PTWEn. > + /// > + UINT32 PTWEn:1; > /// > /// [Bit 13] BranchEn. > /// > @@ -4681,17 +4691,17 @@ typedef union { > /// [Bits 17:14] MTCFreq. If (CPUID.(EAX=07H, ECX=0):EBX[3] = 1). > /// > UINT32 MTCFreq:4; > - UINT32 Reserved3:1; > + UINT32 Reserved7:1; I prefer to not change this field name since the bit range for this Reserved6 is not changed. > /// > /// [Bits 22:19] CYCThresh. If (CPUID.(EAX=07H, ECX=0):EBX[1] = 1). > /// > UINT32 CYCThresh:4; > - UINT32 Reserved4:1; > + UINT32 Reserved8:1; I prefer to not change this field name since the bit range for this Reserved6 is not changed. > /// > /// [Bits 27:24] PSBFreq. If (CPUID.(EAX=07H, ECX=0):EBX[1] = 1). > /// > UINT32 PSBFreq:4; > - UINT32 Reserved5:4; > + UINT32 Reserved9:4; I prefer to not change this field name since the bit range for this Reserved6 is not changed. > /// > /// [Bits 35:32] ADDR0_CFG. If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > 0). > /// > @@ -4708,7 +4718,7 @@ typedef union { > /// [Bits 47:44] ADDR3_CFG. If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > 3). > /// > UINT32 ADDR3_CFG:4; > - UINT32 Reserved6:16; > + UINT32 Reserved10:16; I prefer to not change this field name since the bit range for this Reserved6 is not changed. > } Bits; Eric, As comments above, I suggest we keep the original Reserved## name if the bit range for that field doesn't change. We can only update the Reserved## name if the bit range changes. In this way, we can maximally avoid build failure and also avoid silent failure. In general, the Reserved## name is updated when the bit range changes. The ## is updated to 1 + MAX (all numbers used by Reserved## in this structure). Laszlo, What's your opinion? -- Thanks, Ray