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Received: from DM6PR12MB3163.namprd12.prod.outlook.com (2603:10b6:5:15e::26) by DM6PR12MB4201.namprd12.prod.outlook.com (2603:10b6:5:216::9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2772.18; Mon, 2 Mar 2020 23:08:29 +0000 Received: from DM6PR12MB3163.namprd12.prod.outlook.com ([fe80::f0f9:a88f:f840:2733]) by DM6PR12MB3163.namprd12.prod.outlook.com ([fe80::f0f9:a88f:f840:2733%7]) with mapi id 15.20.2772.019; Mon, 2 Mar 2020 23:08:29 +0000 From: "Lendacky, Thomas" To: devel@edk2.groups.io Cc: Jordan Justen , Laszlo Ersek , Ard Biesheuvel , Michael D Kinney , Liming Gao , Eric Dong , Ray Ni , Brijesh Singh Subject: [PATCH v5 37/42] UefiCpuPkg: Add a 16-bit protected mode code segment descriptor Date: Mon, 2 Mar 2020 17:07:08 -0600 Message-Id: X-Mailer: git-send-email 2.17.1 In-Reply-To: References: X-ClientProxiedBy: DM5PR2001CA0013.namprd20.prod.outlook.com (2603:10b6:4:16::23) To DM6PR12MB3163.namprd12.prod.outlook.com (2603:10b6:5:15e::26) Return-Path: thomas.lendacky@amd.com MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from tlendack-t1.amd.com (165.204.77.1) by DM5PR2001CA0013.namprd20.prod.outlook.com (2603:10b6:4:16::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2772.16 via Frontend Transport; Mon, 2 Mar 2020 23:08:02 +0000 X-Mailer: git-send-email 2.17.1 X-Originating-IP: [165.204.77.1] X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: 7644d018-85bd-48b0-e578-08d7befe8ee3 X-MS-TrafficTypeDiagnostic: DM6PR12MB4201:|DM6PR12MB4201: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:5797; X-Forefront-PRVS: 033054F29A X-Forefront-Antispam-Report: SFV:NSPM;SFS:(10009020)(4636009)(376002)(366004)(136003)(346002)(396003)(39860400002)(199004)(189003)(66946007)(8936002)(54906003)(316002)(81156014)(81166006)(6486002)(6916009)(66556008)(8676002)(4326008)(66476007)(52116002)(7696005)(2616005)(5660300002)(2906002)(36756003)(186003)(966005)(86362001)(478600001)(16526019)(26005)(956004);DIR:OUT;SFP:1101;SCL:1;SRVR:DM6PR12MB4201;H:DM6PR12MB3163.namprd12.prod.outlook.com;FPR:;SPF:None;LANG:en;PTR:InfoNoRecords;A:1;MX:1; Received-SPF: None (protection.outlook.com: amd.com does not designate permitted sender hosts) X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: mkk+BUV1E3JE72d/2QKCHRoIIoKi1281129yPwE1hA9D2nyTx5AU/TjJ4VVVOuYp8YI9304QRFM31KghDdk3LQR/6MtDWWfX+8cYn0b2yb5jHlXM7vkr3ps/iFh6+591RWOMZfhz18+BQ6BMajYwGAhbd7sgxTgki3f7zCMUVtFgMXyXZ9Cecu6ZpGrzj0BDX/DuAl7Vs+IS3XhKYCULbBMHIB7VB141feoedJaTpbWNlYiN2vHy+dlyj0IjqxJpj+jkYJR66M4aJS/SeLibtiVu4q5HWFFHpxvjfysfcbgJIhi/YfT11VpW9GS7FrF5mAYv8VOJ1qrSTlDoVyiahltUeI56gJvyHzfJ7xZe5/0nkjQ6CTEX3ASBfSTpAAclXjKf6ycHyyYIz06CN2z1iKid4FYwdfCLJbIVI4kNCcX+jqXV8IppkwJ1fFHfvOjrQAMuaFQrqOWPokOn8jFt9tfmmb00dpO+tsYkK8R/1GK9a7mlSpTwmSt2RmnlFHz6YRPLR8P65IsC4POuybw4uA== X-MS-Exchange-AntiSpam-MessageData: KCE9Qm4ppZSV6/iGJmGUMBBAD5PLfu072OnVKRYGB/CdmZRw0rd3tUhbM4AO5pBupoueALtyrct3GHaWVi8ryIINN8ZaSDAJtMPkm8RitzfCgYul+DJDQHrrRqKCHACwTqWzNDEFVUbuaN+mAk5pgg== X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: 7644d018-85bd-48b0-e578-08d7befe8ee3 X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Mar 2020 23:08:02.6923 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: OSTxWN0bexlGml/MPSz6j3pFEjRtbm7ZIEMFxakQ36dyA1jNGExexo3VDnerUDcH48+I7gd4uMPdW1/u55Fxxg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4201 Content-Type: text/plain BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2198 A hypervisor is not allowed to update an SEV-ES guests register state, so when booting an SEV-ES guest AP, the hypervisor is not allowed to set the RIP to the guest requested value. Instead, an SEV-ES AP must be transition from 64-bit long mode to 16-bit real mode in response to an INIT-SIPI-SIPI sequence. This requires a 16-bit code segment descriptor. For PEI, create this descriptor in the reset vector GDT table. For DXE, create this descriptor from the newly reserved entry at location 0x28. Cc: Eric Dong Cc: Ray Ni Cc: Laszlo Ersek Signed-off-by: Tom Lendacky --- UefiCpuPkg/CpuDxe/CpuGdt.h | 4 ++-- UefiCpuPkg/CpuDxe/CpuGdt.c | 8 ++++---- UefiCpuPkg/ResetVector/Vtf0/Ia16/Real16ToFlat32.asm | 9 +++++++++ 3 files changed, 15 insertions(+), 6 deletions(-) diff --git a/UefiCpuPkg/CpuDxe/CpuGdt.h b/UefiCpuPkg/CpuDxe/CpuGdt.h index 3a0210b2f172..1c94487cbee8 100644 --- a/UefiCpuPkg/CpuDxe/CpuGdt.h +++ b/UefiCpuPkg/CpuDxe/CpuGdt.h @@ -36,7 +36,7 @@ struct _GDT_ENTRIES { GDT_ENTRY LinearCode; GDT_ENTRY SysData; GDT_ENTRY SysCode; - GDT_ENTRY Spare4; + GDT_ENTRY SysCode16; GDT_ENTRY LinearData64; GDT_ENTRY LinearCode64; GDT_ENTRY Spare5; @@ -49,7 +49,7 @@ struct _GDT_ENTRIES { #define LINEAR_CODE_SEL OFFSET_OF (GDT_ENTRIES, LinearCode) #define SYS_DATA_SEL OFFSET_OF (GDT_ENTRIES, SysData) #define SYS_CODE_SEL OFFSET_OF (GDT_ENTRIES, SysCode) -#define SPARE4_SEL OFFSET_OF (GDT_ENTRIES, Spare4) +#define SYS_CODE16_SEL OFFSET_OF (GDT_ENTRIES, SysCode16) #define LINEAR_DATA64_SEL OFFSET_OF (GDT_ENTRIES, LinearData64) #define LINEAR_CODE64_SEL OFFSET_OF (GDT_ENTRIES, LinearCode64) #define SPARE5_SEL OFFSET_OF (GDT_ENTRIES, Spare5) diff --git a/UefiCpuPkg/CpuDxe/CpuGdt.c b/UefiCpuPkg/CpuDxe/CpuGdt.c index 64efadeba601..a1ab543f2da5 100644 --- a/UefiCpuPkg/CpuDxe/CpuGdt.c +++ b/UefiCpuPkg/CpuDxe/CpuGdt.c @@ -70,14 +70,14 @@ STATIC GDT_ENTRIES GdtTemplate = { 0x0, }, // - // SPARE4_SEL + // SYS_CODE16_SEL // { - 0x0, // limit 15:0 + 0x0FFFF, // limit 15:0 0x0, // base 15:0 0x0, // base 23:16 - 0x0, // type - 0x0, // limit 19:16, flags + 0x09A, // present, ring 0, code, execute/read + 0x08F, // page-granular, 16-bit 0x0, // base 31:24 }, // diff --git a/UefiCpuPkg/ResetVector/Vtf0/Ia16/Real16ToFlat32.asm b/UefiCpuPkg/ResetVector/Vtf0/Ia16/Real16ToFlat32.asm index ce4ebfffb688..0e79a3984b16 100644 --- a/UefiCpuPkg/ResetVector/Vtf0/Ia16/Real16ToFlat32.asm +++ b/UefiCpuPkg/ResetVector/Vtf0/Ia16/Real16ToFlat32.asm @@ -129,5 +129,14 @@ LINEAR_CODE64_SEL equ $-GDT_BASE DB 0 ; base 31:24 %endif +; linear code segment descriptor +LINEAR_CODE16_SEL equ $-GDT_BASE + DW 0xffff ; limit 15:0 + DW 0 ; base 15:0 + DB 0 ; base 23:16 + DB PRESENT_FLAG(1)|DPL(0)|SYSTEM_FLAG(1)|DESC_TYPE(CODE32_TYPE) + DB GRANULARITY_FLAG(1)|DEFAULT_SIZE32(0)|CODE64_FLAG(0)|UPPER_LIMIT(0xf) + DB 0 ; base 31:24 + GDT_END: -- 2.17.1