[PATCH 0/4] OvmfPkg: CloudHv: Reduce PIO and MMIO accesses

[PATCH 0/4] OvmfPkg: CloudHv: Reduce PIO and MMIO accesses

[Boeuf, Sebastien]

From: Sebastien Boeuf <sebastien.boeuf@intel.com>

The goal of this series is to reduce the amount of inappropriate PIO
and MMIO accesses generated by the firmware when running on Cloud
Hypervisor.

For MMIO accesses, it is about providing the right base address where
the firmware will be loaded by the VMM in order to avoid unexpected
accesses to some address ranges.

For PIO accesses, it is about preventing some read/write to be performed
in the first place, as we know the underlying device is not emulated by
Cloud Hypervisor.

Signed-off-by: Sebastien Boeuf <sebastien.boeuf@intel.com>

Sebastien Boeuf (4):
  OvmfPkg: CloudHv: Fix FW_BASE_ADDRESS
  OvmfPkg: Check for QemuFwCfg availability before accessing it
  OvmfPkg: CloudHv: Rely on QemuFwCfgLibNull implementation
  OvmfPkg: Don't access A20 gate register on Cloud Hypervisor

 OvmfPkg/CloudHv/CloudHvDefines.fdf.inc        | 65 +++++++++++++++++++
 OvmfPkg/CloudHv/CloudHvX64.dsc                |  4 +-
 OvmfPkg/CloudHv/CloudHvX64.fdf                |  2 +-
 OvmfPkg/Library/PlatformInitLib/Platform.c    | 13 ++--
 .../QemuBootOrderLib/QemuBootOrderLib.c       |  8 ++-
 5 files changed, 82 insertions(+), 10 deletions(-)
 create mode 100644 OvmfPkg/CloudHv/CloudHvDefines.fdf.inc

-- 
2.32.0

---------------------------------------------------------------------
Intel Corporation SAS (French simplified joint stock company)
Registered headquarters: "Les Montalets"- 2, rue de Paris, 
92196 Meudon Cedex, France
Registration Number:  302 456 199 R.C.S. NANTERRE
Capital: 5 208 026.16 Euros

This e-mail and any attachments may contain confidential material for
the sole use of the intended recipient(s). Any review or distribution
by others is strictly prohibited. If you are not the intended
recipient, please contact the sender and delete all copies.

[PATCH 1/4] OvmfPkg: CloudHv: Fix FW_BASE_ADDRESS

[Boeuf, Sebastien]

From: Sebastien Boeuf <sebastien.boeuf@intel.com>

The FW_BASE_ADDRESS value provided by OvmfPkgDefines.fdf.inc is
incorrect for the CloudHv target. We know the generated firmware
contains a PVH ELF header, meaning it will be loaded according to the
address provided through this header. And since we know this address
isn't going to change as it's part of CloudHvElfHeader.fdf.inc, we can
hardcode it through a new include file CloudHvDefines.fdf.inc, which
replaces the generic one OvmfPkgDefines.fdf.inc.

With this change, we prevent the firmware from accessing MMIO addresses
from the address range 0xffc00000-0xffffffff since we know the firmware
hasn't been loaded on this address range.

Signed-off-by: Sebastien Boeuf <sebastien.boeuf@intel.com>
---
 OvmfPkg/CloudHv/CloudHvDefines.fdf.inc | 65 ++++++++++++++++++++++++++
 OvmfPkg/CloudHv/CloudHvX64.fdf         |  2 +-
 2 files changed, 66 insertions(+), 1 deletion(-)
 create mode 100644 OvmfPkg/CloudHv/CloudHvDefines.fdf.inc

diff --git a/OvmfPkg/CloudHv/CloudHvDefines.fdf.inc b/OvmfPkg/CloudHv/CloudHvDefines.fdf.inc
new file mode 100644
index 0000000000..2198cbcd87
--- /dev/null
+++ b/OvmfPkg/CloudHv/CloudHvDefines.fdf.inc
@@ -0,0 +1,65 @@
+## @file
+#  FDF include file that defines the main macros and sets the dependent PCDs.
+#
+#  Copyright (C) 2014, Red Hat, Inc.
+#  Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR>
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+DEFINE BLOCK_SIZE        = 0x1000
+DEFINE VARS_OFFSET       = 0
+
+DEFINE VARS_SIZE         = 0x84000
+DEFINE VARS_BLOCKS       = 0x84
+DEFINE VARS_LIVE_SIZE    = 0x40000
+DEFINE VARS_SPARE_SIZE   = 0x42000
+
+DEFINE FW_BASE_ADDRESS   = 0x004FFFD0
+DEFINE FW_SIZE           = 0x00400000
+DEFINE FW_BLOCKS         = 0x400
+DEFINE CODE_BASE_ADDRESS = 0x00583FD0
+DEFINE CODE_SIZE         = 0x0037C000
+DEFINE CODE_BLOCKS       = 0x37C
+DEFINE FVMAIN_SIZE       = 0x00348000
+DEFINE SECFV_OFFSET      = 0x003CC000
+DEFINE SECFV_SIZE        = 0x34000
+
+SET gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFdBaseAddress     = $(FW_BASE_ADDRESS)
+SET gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFirmwareFdSize    = $(FW_SIZE)
+SET gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFirmwareBlockSize = $(BLOCK_SIZE)
+
+SET gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFlashNvStorageVariableBase = $(FW_BASE_ADDRESS)
+SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize = $(VARS_LIVE_SIZE)
+
+SET gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFlashNvStorageEventLogBase = gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFlashNvStorageVariableBase + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
+SET gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFlashNvStorageEventLogSize = $(BLOCK_SIZE)
+
+SET gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFlashNvStorageFtwWorkingBase = gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFlashNvStorageEventLogBase + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFlashNvStorageEventLogSize
+SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize = $(BLOCK_SIZE)
+
+SET gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFlashNvStorageFtwSpareBase = gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFlashNvStorageFtwWorkingBase + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
+SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize = $(VARS_SPARE_SIZE)
+
+# The OVMF WorkArea contains a fixed size header followed by the actual data.
+# The size of header is accessed through a fixed PCD in the reset vector code.
+# The value need to be kept in sync with the any changes to the Confidential
+# Computing Work Area header defined in the Include/WorkArea.h
+SET gUefiOvmfPkgTokenSpaceGuid.PcdOvmfConfidentialComputingWorkAreaHeader  = 4
+
+SET gUefiOvmfPkgTokenSpaceGuid.PcdCfvBase           = $(FW_BASE_ADDRESS)
+SET gUefiOvmfPkgTokenSpaceGuid.PcdCfvRawDataOffset  = $(VARS_OFFSET)
+SET gUefiOvmfPkgTokenSpaceGuid.PcdCfvRawDataSize    = $(VARS_SIZE)
+
+SET gUefiOvmfPkgTokenSpaceGuid.PcdBfvBase           = $(CODE_BASE_ADDRESS)
+SET gUefiOvmfPkgTokenSpaceGuid.PcdBfvRawDataOffset  = $(VARS_SIZE)
+SET gUefiOvmfPkgTokenSpaceGuid.PcdBfvRawDataSize    = $(CODE_SIZE)
+
+!if $(SMM_REQUIRE) == TRUE
+SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64 = gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFlashNvStorageVariableBase
+SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase = gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFlashNvStorageFtwWorkingBase
+SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase   = gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFlashNvStorageFtwSpareBase
+!endif
+
+DEFINE MEMFD_BASE_ADDRESS = 0x800000
diff --git a/OvmfPkg/CloudHv/CloudHvX64.fdf b/OvmfPkg/CloudHv/CloudHvX64.fdf
index de64a3a709..a41a553693 100644
--- a/OvmfPkg/CloudHv/CloudHvX64.fdf
+++ b/OvmfPkg/CloudHv/CloudHvX64.fdf
@@ -11,7 +11,7 @@
 ################################################################################
 
 [Defines]
-!include OvmfPkg/OvmfPkgDefines.fdf.inc
+!include CloudHvDefines.fdf.inc
 
 #
 # This will allow the flash device image to be recognize as an ELF, with first
-- 
2.32.0

---------------------------------------------------------------------
Intel Corporation SAS (French simplified joint stock company)
Registered headquarters: "Les Montalets"- 2, rue de Paris, 
92196 Meudon Cedex, France
Registration Number:  302 456 199 R.C.S. NANTERRE
Capital: 5 208 026.16 Euros

This e-mail and any attachments may contain confidential material for
the sole use of the intended recipient(s). Any review or distribution
by others is strictly prohibited. If you are not the intended
recipient, please contact the sender and delete all copies.

[PATCH 2/4] OvmfPkg: Check for QemuFwCfg availability before accessing it

[Boeuf, Sebastien]

From: Sebastien Boeuf <sebastien.boeuf@intel.com>

There are few places in the codebase assuming QemuFwCfg will be present
and supported, which can cause some issues when trying to rely on the
QemuFwCfgLibNull implementation of QemuFwCfgLib.

Signed-off-by: Sebastien Boeuf <sebastien.boeuf@intel.com>
---
 OvmfPkg/Library/PlatformInitLib/Platform.c          | 9 ++++++---
 OvmfPkg/Library/QemuBootOrderLib/QemuBootOrderLib.c | 8 +++++---
 2 files changed, 11 insertions(+), 6 deletions(-)

diff --git a/OvmfPkg/Library/PlatformInitLib/Platform.c b/OvmfPkg/Library/PlatformInitLib/Platform.c
index 101074f610..cb1a893aef 100644
--- a/OvmfPkg/Library/PlatformInitLib/Platform.c
+++ b/OvmfPkg/Library/PlatformInitLib/Platform.c
@@ -410,14 +410,17 @@ PlatformMaxCpuCountInitialization (
   IN OUT EFI_HOB_PLATFORM_INFO  *PlatformInfoHob
   )
 {
-  UINT16  BootCpuCount;
+  UINT16  BootCpuCount = 0;
   UINT32  MaxCpuCount;
 
   //
   // Try to fetch the boot CPU count.
   //
-  QemuFwCfgSelectItem (QemuFwCfgItemSmpCpuCount);
-  BootCpuCount = QemuFwCfgRead16 ();
+  if (QemuFwCfgIsAvailable ()) {
+    QemuFwCfgSelectItem (QemuFwCfgItemSmpCpuCount);
+    BootCpuCount = QemuFwCfgRead16 ();
+  }
+
   if (BootCpuCount == 0) {
     //
     // QEMU doesn't report the boot CPU count. (BootCpuCount == 0) will let
diff --git a/OvmfPkg/Library/QemuBootOrderLib/QemuBootOrderLib.c b/OvmfPkg/Library/QemuBootOrderLib/QemuBootOrderLib.c
index b5768285d8..67d29ac642 100644
--- a/OvmfPkg/Library/QemuBootOrderLib/QemuBootOrderLib.c
+++ b/OvmfPkg/Library/QemuBootOrderLib/QemuBootOrderLib.c
@@ -2233,6 +2233,11 @@ GetFrontPageTimeoutFromQemu (
 {
   FIRMWARE_CONFIG_ITEM  BootMenuWaitItem;
   UINTN                 BootMenuWaitSize;
+  UINT16                Timeout = PcdGet16 (PcdPlatformBootTimeOut);
+
+  if (!QemuFwCfgIsAvailable ()) {
+    return Timeout;
+  }
 
   QemuFwCfgSelectItem (QemuFwCfgItemBootMenu);
   if (QemuFwCfgRead16 () == 0) {
@@ -2257,9 +2262,6 @@ GetFrontPageTimeoutFromQemu (
     // return three seconds if the platform default would cause us to skip the
     // front page, and return the platform default otherwise.
     //
-    UINT16  Timeout;
-
-    Timeout = PcdGet16 (PcdPlatformBootTimeOut);
     if (Timeout == 0) {
       Timeout = 3;
     }
-- 
2.32.0

---------------------------------------------------------------------
Intel Corporation SAS (French simplified joint stock company)
Registered headquarters: "Les Montalets"- 2, rue de Paris, 
92196 Meudon Cedex, France
Registration Number:  302 456 199 R.C.S. NANTERRE
Capital: 5 208 026.16 Euros

This e-mail and any attachments may contain confidential material for
the sole use of the intended recipient(s). Any review or distribution
by others is strictly prohibited. If you are not the intended
recipient, please contact the sender and delete all copies.

[PATCH 3/4] OvmfPkg: CloudHv: Rely on QemuFwCfgLibNull implementation

[Boeuf, Sebastien]

From: Sebastien Boeuf <sebastien.boeuf@intel.com>

Since Cloud Hypervisor doesn't support the fw_cfg mechanism, it's more
appropriate to rely on QemuFwCfgLibNull implementation of QemuFwCfgLib
since it provides a null implementation that will not issue any PIO
accesses to ports 0x510 and 0x511.

Signed-off-by: Sebastien Boeuf <sebastien.boeuf@intel.com>
---
 OvmfPkg/CloudHv/CloudHvX64.dsc | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/OvmfPkg/CloudHv/CloudHvX64.dsc b/OvmfPkg/CloudHv/CloudHvX64.dsc
index d1c85f60c7..4d6bc2a84d 100644
--- a/OvmfPkg/CloudHv/CloudHvX64.dsc
+++ b/OvmfPkg/CloudHv/CloudHvX64.dsc
@@ -175,7 +175,7 @@
   UefiCpuLib|UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.inf
   SecurityManagementLib|MdeModulePkg/Library/DxeSecurityManagementLib/DxeSecurityManagementLib.inf
   SerializeVariablesLib|OvmfPkg/Library/SerializeVariablesLib/SerializeVariablesLib.inf
-  QemuFwCfgLib|OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgDxeLib.inf
+  QemuFwCfgLib|OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgLibNull.inf
   QemuFwCfgSimpleParserLib|OvmfPkg/Library/QemuFwCfgSimpleParserLib/QemuFwCfgSimpleParserLib.inf
   VirtioLib|OvmfPkg/Library/VirtioLib/VirtioLib.inf
   LoadLinuxLib|OvmfPkg/Library/LoadLinuxLib/LoadLinuxLib.inf
@@ -305,7 +305,7 @@
   MpInitLib|UefiCpuPkg/Library/MpInitLib/PeiMpInitLib.inf
   QemuFwCfgS3Lib|OvmfPkg/Library/QemuFwCfgS3Lib/PeiQemuFwCfgS3LibFwCfg.inf
   PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf
-  QemuFwCfgLib|OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgPeiLib.inf
+  QemuFwCfgLib|OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgLibNull.inf
 
 !include OvmfPkg/OvmfTpmLibsPeim.dsc.inc
 
-- 
2.32.0

---------------------------------------------------------------------
Intel Corporation SAS (French simplified joint stock company)
Registered headquarters: "Les Montalets"- 2, rue de Paris, 
92196 Meudon Cedex, France
Registration Number:  302 456 199 R.C.S. NANTERRE
Capital: 5 208 026.16 Euros

This e-mail and any attachments may contain confidential material for
the sole use of the intended recipient(s). Any review or distribution
by others is strictly prohibited. If you are not the intended
recipient, please contact the sender and delete all copies.

[PATCH 4/4] OvmfPkg: Don't access A20 gate register on Cloud Hypervisor

[Boeuf, Sebastien]

From: Sebastien Boeuf <sebastien.boeuf@intel.com>

Since Cloud Hypervisor doesn't emulate an A20 gate register on I/O port
0x92, it's better to avoid accessing it when the platform is identified
as Cloud Hypervisor.

Signed-off-by: Sebastien Boeuf <sebastien.boeuf@intel.com>
---
 OvmfPkg/Library/PlatformInitLib/Platform.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/OvmfPkg/Library/PlatformInitLib/Platform.c b/OvmfPkg/Library/PlatformInitLib/Platform.c
index cb1a893aef..f2b07dc937 100644
--- a/OvmfPkg/Library/PlatformInitLib/Platform.c
+++ b/OvmfPkg/Library/PlatformInitLib/Platform.c
@@ -314,7 +314,9 @@ PlatformMiscInitialization (
   //
   // Disable A20 Mask
   //
-  IoOr8 (0x92, BIT1);
+  if (PlatformInfoHob->HostBridgeDevId != CLOUDHV_DEVICE_ID) {
+    IoOr8 (0x92, BIT1);
+  }
 
   //
   // Build the CPU HOB with guest RAM size dependent address width and 16-bits
-- 
2.32.0

---------------------------------------------------------------------
Intel Corporation SAS (French simplified joint stock company)
Registered headquarters: "Les Montalets"- 2, rue de Paris, 
92196 Meudon Cedex, France
Registration Number:  302 456 199 R.C.S. NANTERRE
Capital: 5 208 026.16 Euros

This e-mail and any attachments may contain confidential material for
the sole use of the intended recipient(s). Any review or distribution
by others is strictly prohibited. If you are not the intended
recipient, please contact the sender and delete all copies.

Re: [PATCH 0/4] OvmfPkg: CloudHv: Reduce PIO and MMIO accesses

[Boeuf, Sebastien]

[-- Attachment #1: Type: text/plain, Size: 2414 bytes --]


Hi,

Sorry to bother you folks, but I was wondering if you had this patchset on your radar :)

Thanks for your time,
Sebastien
________________________________
From: Boeuf, Sebastien <sebastien.boeuf@intel.com>
Sent: Tuesday, May 10, 2022 2:50 PM
To: devel@edk2.groups.io <devel@edk2.groups.io>
Cc: Yao, Jiewen <jiewen.yao@intel.com>; Justen, Jordan L <jordan.l.justen@intel.com>; kraxel@redhat.com <kraxel@redhat.com>; Boeuf, Sebastien <sebastien.boeuf@intel.com>
Subject: [PATCH 0/4] OvmfPkg: CloudHv: Reduce PIO and MMIO accesses

From: Sebastien Boeuf <sebastien.boeuf@intel.com>

The goal of this series is to reduce the amount of inappropriate PIO
and MMIO accesses generated by the firmware when running on Cloud
Hypervisor.

For MMIO accesses, it is about providing the right base address where
the firmware will be loaded by the VMM in order to avoid unexpected
accesses to some address ranges.

For PIO accesses, it is about preventing some read/write to be performed
in the first place, as we know the underlying device is not emulated by
Cloud Hypervisor.

Signed-off-by: Sebastien Boeuf <sebastien.boeuf@intel.com>

Sebastien Boeuf (4):
  OvmfPkg: CloudHv: Fix FW_BASE_ADDRESS
  OvmfPkg: Check for QemuFwCfg availability before accessing it
  OvmfPkg: CloudHv: Rely on QemuFwCfgLibNull implementation
  OvmfPkg: Don't access A20 gate register on Cloud Hypervisor

 OvmfPkg/CloudHv/CloudHvDefines.fdf.inc        | 65 +++++++++++++++++++
 OvmfPkg/CloudHv/CloudHvX64.dsc                |  4 +-
 OvmfPkg/CloudHv/CloudHvX64.fdf                |  2 +-
 OvmfPkg/Library/PlatformInitLib/Platform.c    | 13 ++--
 .../QemuBootOrderLib/QemuBootOrderLib.c       |  8 ++-
 5 files changed, 82 insertions(+), 10 deletions(-)
 create mode 100644 OvmfPkg/CloudHv/CloudHvDefines.fdf.inc

--
2.32.0

---------------------------------------------------------------------
Intel Corporation SAS (French simplified joint stock company)
Registered headquarters: "Les Montalets"- 2, rue de Paris, 
92196 Meudon Cedex, France
Registration Number:  302 456 199 R.C.S. NANTERRE
Capital: 5 208 026.16 Euros

This e-mail and any attachments may contain confidential material for
the sole use of the intended recipient(s). Any review or distribution
by others is strictly prohibited. If you are not the intended
recipient, please contact the sender and delete all copies.

[-- Attachment #2: Type: text/html, Size: 4370 bytes --]

Re: [PATCH 0/4] OvmfPkg: CloudHv: Reduce PIO and MMIO accesses

[Yao, Jiewen]

Acked-by: Jiewen Yao <Jiewen.yao@intel.com>

I notice the PR failed - https://github.com/tianocore/edk2/pull/2875

I just want to double confirm, do you have a success PR for this patch set?

Thank you
Yao Jiewen

> -----Original Message-----
> From: Boeuf, Sebastien <sebastien.boeuf@intel.com>
> Sent: Tuesday, May 10, 2022 8:51 PM
> To: devel@edk2.groups.io
> Cc: Yao, Jiewen <jiewen.yao@intel.com>; Justen, Jordan L
> <jordan.l.justen@intel.com>; kraxel@redhat.com; Boeuf, Sebastien
> <sebastien.boeuf@intel.com>
> Subject: [PATCH 0/4] OvmfPkg: CloudHv: Reduce PIO and MMIO accesses
> 
> From: Sebastien Boeuf <sebastien.boeuf@intel.com>
> 
> The goal of this series is to reduce the amount of inappropriate PIO
> and MMIO accesses generated by the firmware when running on Cloud
> Hypervisor.
> 
> For MMIO accesses, it is about providing the right base address where
> the firmware will be loaded by the VMM in order to avoid unexpected
> accesses to some address ranges.
> 
> For PIO accesses, it is about preventing some read/write to be performed
> in the first place, as we know the underlying device is not emulated by
> Cloud Hypervisor.
> 
> Signed-off-by: Sebastien Boeuf <sebastien.boeuf@intel.com>
> 
> Sebastien Boeuf (4):
>   OvmfPkg: CloudHv: Fix FW_BASE_ADDRESS
>   OvmfPkg: Check for QemuFwCfg availability before accessing it
>   OvmfPkg: CloudHv: Rely on QemuFwCfgLibNull implementation
>   OvmfPkg: Don't access A20 gate register on Cloud Hypervisor
> 
>  OvmfPkg/CloudHv/CloudHvDefines.fdf.inc        | 65 +++++++++++++++++++
>  OvmfPkg/CloudHv/CloudHvX64.dsc                |  4 +-
>  OvmfPkg/CloudHv/CloudHvX64.fdf                |  2 +-
>  OvmfPkg/Library/PlatformInitLib/Platform.c    | 13 ++--
>  .../QemuBootOrderLib/QemuBootOrderLib.c       |  8 ++-
>  5 files changed, 82 insertions(+), 10 deletions(-)
>  create mode 100644 OvmfPkg/CloudHv/CloudHvDefines.fdf.inc
> 
> --
> 2.32.0

Re: [PATCH 0/4] OvmfPkg: CloudHv: Reduce PIO and MMIO accesses

[Boeuf, Sebastien]

On Thu, 2022-06-02 at 08:57 +0000, Yao, Jiewen wrote:
> Acked-by: Jiewen Yao <Jiewen.yao@intel.com>
> 
> I notice the PR failed - https://github.com/tianocore/edk2/pull/2875
> 
> I just want to double confirm, do you have a success PR for this
> patch set?

Let me repush the PR once rebased on latest master. I think the
failures were only related to the Windows CI issues.

Thanks,
Sebastien

> 
> Thank you
> Yao Jiewen
> 
> > -----Original Message-----
> > From: Boeuf, Sebastien <sebastien.boeuf@intel.com>
> > Sent: Tuesday, May 10, 2022 8:51 PM
> > To: devel@edk2.groups.io
> > Cc: Yao, Jiewen <jiewen.yao@intel.com>; Justen, Jordan L
> > <jordan.l.justen@intel.com>; kraxel@redhat.com; Boeuf, Sebastien
> > <sebastien.boeuf@intel.com>
> > Subject: [PATCH 0/4] OvmfPkg: CloudHv: Reduce PIO and MMIO accesses
> > 
> > From: Sebastien Boeuf <sebastien.boeuf@intel.com>
> > 
> > The goal of this series is to reduce the amount of inappropriate
> > PIO
> > and MMIO accesses generated by the firmware when running on Cloud
> > Hypervisor.
> > 
> > For MMIO accesses, it is about providing the right base address
> > where
> > the firmware will be loaded by the VMM in order to avoid unexpected
> > accesses to some address ranges.
> > 
> > For PIO accesses, it is about preventing some read/write to be
> > performed
> > in the first place, as we know the underlying device is not
> > emulated by
> > Cloud Hypervisor.
> > 
> > Signed-off-by: Sebastien Boeuf <sebastien.boeuf@intel.com>
> > 
> > Sebastien Boeuf (4):
> >   OvmfPkg: CloudHv: Fix FW_BASE_ADDRESS
> >   OvmfPkg: Check for QemuFwCfg availability before accessing it
> >   OvmfPkg: CloudHv: Rely on QemuFwCfgLibNull implementation
> >   OvmfPkg: Don't access A20 gate register on Cloud Hypervisor
> > 
> >  OvmfPkg/CloudHv/CloudHvDefines.fdf.inc        | 65
> > +++++++++++++++++++
> >  OvmfPkg/CloudHv/CloudHvX64.dsc                |  4 +-
> >  OvmfPkg/CloudHv/CloudHvX64.fdf                |  2 +-
> >  OvmfPkg/Library/PlatformInitLib/Platform.c    | 13 ++--
> >  .../QemuBootOrderLib/QemuBootOrderLib.c       |  8 ++-
> >  5 files changed, 82 insertions(+), 10 deletions(-)
> >  create mode 100644 OvmfPkg/CloudHv/CloudHvDefines.fdf.inc
> > 
> > --
> > 2.32.0
> 

---------------------------------------------------------------------
Intel Corporation SAS (French simplified joint stock company)
Registered headquarters: "Les Montalets"- 2, rue de Paris, 
92196 Meudon Cedex, France
Registration Number:  302 456 199 R.C.S. NANTERRE
Capital: 5 208 026.16 Euros

This e-mail and any attachments may contain confidential material for
the sole use of the intended recipient(s). Any review or distribution
by others is strictly prohibited. If you are not the intended
recipient, please contact the sender and delete all copies.

Re: [PATCH 0/4] OvmfPkg: CloudHv: Reduce PIO and MMIO accesses

[Boeuf, Sebastien]

On Thu, 2022-06-02 at 11:04 +0200, Sebastien Boeuf wrote:
> On Thu, 2022-06-02 at 08:57 +0000, Yao, Jiewen wrote:
> > Acked-by: Jiewen Yao <Jiewen.yao@intel.com>
> > 
> > I notice the PR failed -
> > https://github.com/tianocore/edk2/pull/2875
> > 
> > I just want to double confirm, do you have a success PR for this
> > patch set?
> 
> Let me repush the PR once rebased on latest master. I think the
> failures were only related to the Windows CI issues.

Ok the CI is passing fine after I rebased on latest master. See
https://github.com/tianocore/edk2/pull/2875

Thanks,
Sebastien

> 
> Thanks,
> Sebastien
> 
> > 
> > Thank you
> > Yao Jiewen
> > 
> > > -----Original Message-----
> > > From: Boeuf, Sebastien <sebastien.boeuf@intel.com>
> > > Sent: Tuesday, May 10, 2022 8:51 PM
> > > To: devel@edk2.groups.io
> > > Cc: Yao, Jiewen <jiewen.yao@intel.com>; Justen, Jordan L
> > > <jordan.l.justen@intel.com>; kraxel@redhat.com; Boeuf, Sebastien
> > > <sebastien.boeuf@intel.com>
> > > Subject: [PATCH 0/4] OvmfPkg: CloudHv: Reduce PIO and MMIO
> > > accesses
> > > 
> > > From: Sebastien Boeuf <sebastien.boeuf@intel.com>
> > > 
> > > The goal of this series is to reduce the amount of inappropriate
> > > PIO
> > > and MMIO accesses generated by the firmware when running on Cloud
> > > Hypervisor.
> > > 
> > > For MMIO accesses, it is about providing the right base address
> > > where
> > > the firmware will be loaded by the VMM in order to avoid
> > > unexpected
> > > accesses to some address ranges.
> > > 
> > > For PIO accesses, it is about preventing some read/write to be
> > > performed
> > > in the first place, as we know the underlying device is not
> > > emulated by
> > > Cloud Hypervisor.
> > > 
> > > Signed-off-by: Sebastien Boeuf <sebastien.boeuf@intel.com>
> > > 
> > > Sebastien Boeuf (4):
> > >   OvmfPkg: CloudHv: Fix FW_BASE_ADDRESS
> > >   OvmfPkg: Check for QemuFwCfg availability before accessing it
> > >   OvmfPkg: CloudHv: Rely on QemuFwCfgLibNull implementation
> > >   OvmfPkg: Don't access A20 gate register on Cloud Hypervisor
> > > 
> > >  OvmfPkg/CloudHv/CloudHvDefines.fdf.inc        | 65
> > > +++++++++++++++++++
> > >  OvmfPkg/CloudHv/CloudHvX64.dsc                |  4 +-
> > >  OvmfPkg/CloudHv/CloudHvX64.fdf                |  2 +-
> > >  OvmfPkg/Library/PlatformInitLib/Platform.c    | 13 ++--
> > >  .../QemuBootOrderLib/QemuBootOrderLib.c       |  8 ++-
> > >  5 files changed, 82 insertions(+), 10 deletions(-)
> > >  create mode 100644 OvmfPkg/CloudHv/CloudHvDefines.fdf.inc
> > > 
> > > --
> > > 2.32.0
> > 
> 

---------------------------------------------------------------------
Intel Corporation SAS (French simplified joint stock company)
Registered headquarters: "Les Montalets"- 2, rue de Paris, 
92196 Meudon Cedex, France
Registration Number:  302 456 199 R.C.S. NANTERRE
Capital: 5 208 026.16 Euros

This e-mail and any attachments may contain confidential material for
the sole use of the intended recipient(s). Any review or distribution
by others is strictly prohibited. If you are not the intended
recipient, please contact the sender and delete all copies.

Re: [PATCH 0/4] OvmfPkg: CloudHv: Reduce PIO and MMIO accesses

[Yao, Jiewen]

Sounds good, thanks!

> -----Original Message-----
> From: Boeuf, Sebastien <sebastien.boeuf@intel.com>
> Sent: Thursday, June 2, 2022 5:29 PM
> To: Yao, Jiewen <jiewen.yao@intel.com>; devel@edk2.groups.io
> Cc: kraxel@redhat.com; Justen, Jordan L <jordan.l.justen@intel.com>
> Subject: Re: [PATCH 0/4] OvmfPkg: CloudHv: Reduce PIO and MMIO accesses
> 
> On Thu, 2022-06-02 at 11:04 +0200, Sebastien Boeuf wrote:
> > On Thu, 2022-06-02 at 08:57 +0000, Yao, Jiewen wrote:
> > > Acked-by: Jiewen Yao <Jiewen.yao@intel.com>
> > >
> > > I notice the PR failed -
> > > https://github.com/tianocore/edk2/pull/2875
> > >
> > > I just want to double confirm, do you have a success PR for this
> > > patch set?
> >
> > Let me repush the PR once rebased on latest master. I think the
> > failures were only related to the Windows CI issues.
> 
> Ok the CI is passing fine after I rebased on latest master. See
> https://github.com/tianocore/edk2/pull/2875
> 
> Thanks,
> Sebastien
> 
> >
> > Thanks,
> > Sebastien
> >
> > >
> > > Thank you
> > > Yao Jiewen
> > >
> > > > -----Original Message-----
> > > > From: Boeuf, Sebastien <sebastien.boeuf@intel.com>
> > > > Sent: Tuesday, May 10, 2022 8:51 PM
> > > > To: devel@edk2.groups.io
> > > > Cc: Yao, Jiewen <jiewen.yao@intel.com>; Justen, Jordan L
> > > > <jordan.l.justen@intel.com>; kraxel@redhat.com; Boeuf, Sebastien
> > > > <sebastien.boeuf@intel.com>
> > > > Subject: [PATCH 0/4] OvmfPkg: CloudHv: Reduce PIO and MMIO
> > > > accesses
> > > >
> > > > From: Sebastien Boeuf <sebastien.boeuf@intel.com>
> > > >
> > > > The goal of this series is to reduce the amount of inappropriate
> > > > PIO
> > > > and MMIO accesses generated by the firmware when running on Cloud
> > > > Hypervisor.
> > > >
> > > > For MMIO accesses, it is about providing the right base address
> > > > where
> > > > the firmware will be loaded by the VMM in order to avoid
> > > > unexpected
> > > > accesses to some address ranges.
> > > >
> > > > For PIO accesses, it is about preventing some read/write to be
> > > > performed
> > > > in the first place, as we know the underlying device is not
> > > > emulated by
> > > > Cloud Hypervisor.
> > > >
> > > > Signed-off-by: Sebastien Boeuf <sebastien.boeuf@intel.com>
> > > >
> > > > Sebastien Boeuf (4):
> > > >   OvmfPkg: CloudHv: Fix FW_BASE_ADDRESS
> > > >   OvmfPkg: Check for QemuFwCfg availability before accessing it
> > > >   OvmfPkg: CloudHv: Rely on QemuFwCfgLibNull implementation
> > > >   OvmfPkg: Don't access A20 gate register on Cloud Hypervisor
> > > >
> > > >  OvmfPkg/CloudHv/CloudHvDefines.fdf.inc        | 65
> > > > +++++++++++++++++++
> > > >  OvmfPkg/CloudHv/CloudHvX64.dsc                |  4 +-
> > > >  OvmfPkg/CloudHv/CloudHvX64.fdf                |  2 +-
> > > >  OvmfPkg/Library/PlatformInitLib/Platform.c    | 13 ++--
> > > >  .../QemuBootOrderLib/QemuBootOrderLib.c       |  8 ++-
> > > >  5 files changed, 82 insertions(+), 10 deletions(-)
> > > >  create mode 100644 OvmfPkg/CloudHv/CloudHvDefines.fdf.inc
> > > >
> > > > --
> > > > 2.32.0
> > >
> >

Re: [PATCH 0/4] OvmfPkg: CloudHv: Reduce PIO and MMIO accesses

[Yao, Jiewen]

Merged https://github.com/tianocore/edk2/pull/2942

> -----Original Message-----
> From: Boeuf, Sebastien <sebastien.boeuf@intel.com>
> Sent: Thursday, June 2, 2022 5:29 PM
> To: Yao, Jiewen <jiewen.yao@intel.com>; devel@edk2.groups.io
> Cc: kraxel@redhat.com; Justen, Jordan L <jordan.l.justen@intel.com>
> Subject: Re: [PATCH 0/4] OvmfPkg: CloudHv: Reduce PIO and MMIO accesses
> 
> On Thu, 2022-06-02 at 11:04 +0200, Sebastien Boeuf wrote:
> > On Thu, 2022-06-02 at 08:57 +0000, Yao, Jiewen wrote:
> > > Acked-by: Jiewen Yao <Jiewen.yao@intel.com>
> > >
> > > I notice the PR failed -
> > > https://github.com/tianocore/edk2/pull/2875
> > >
> > > I just want to double confirm, do you have a success PR for this
> > > patch set?
> >
> > Let me repush the PR once rebased on latest master. I think the
> > failures were only related to the Windows CI issues.
> 
> Ok the CI is passing fine after I rebased on latest master. See
> https://github.com/tianocore/edk2/pull/2875
> 
> Thanks,
> Sebastien
> 
> >
> > Thanks,
> > Sebastien
> >
> > >
> > > Thank you
> > > Yao Jiewen
> > >
> > > > -----Original Message-----
> > > > From: Boeuf, Sebastien <sebastien.boeuf@intel.com>
> > > > Sent: Tuesday, May 10, 2022 8:51 PM
> > > > To: devel@edk2.groups.io
> > > > Cc: Yao, Jiewen <jiewen.yao@intel.com>; Justen, Jordan L
> > > > <jordan.l.justen@intel.com>; kraxel@redhat.com; Boeuf, Sebastien
> > > > <sebastien.boeuf@intel.com>
> > > > Subject: [PATCH 0/4] OvmfPkg: CloudHv: Reduce PIO and MMIO
> > > > accesses
> > > >
> > > > From: Sebastien Boeuf <sebastien.boeuf@intel.com>
> > > >
> > > > The goal of this series is to reduce the amount of inappropriate
> > > > PIO
> > > > and MMIO accesses generated by the firmware when running on Cloud
> > > > Hypervisor.
> > > >
> > > > For MMIO accesses, it is about providing the right base address
> > > > where
> > > > the firmware will be loaded by the VMM in order to avoid
> > > > unexpected
> > > > accesses to some address ranges.
> > > >
> > > > For PIO accesses, it is about preventing some read/write to be
> > > > performed
> > > > in the first place, as we know the underlying device is not
> > > > emulated by
> > > > Cloud Hypervisor.
> > > >
> > > > Signed-off-by: Sebastien Boeuf <sebastien.boeuf@intel.com>
> > > >
> > > > Sebastien Boeuf (4):
> > > >   OvmfPkg: CloudHv: Fix FW_BASE_ADDRESS
> > > >   OvmfPkg: Check for QemuFwCfg availability before accessing it
> > > >   OvmfPkg: CloudHv: Rely on QemuFwCfgLibNull implementation
> > > >   OvmfPkg: Don't access A20 gate register on Cloud Hypervisor
> > > >
> > > >  OvmfPkg/CloudHv/CloudHvDefines.fdf.inc        | 65
> > > > +++++++++++++++++++
> > > >  OvmfPkg/CloudHv/CloudHvX64.dsc                |  4 +-
> > > >  OvmfPkg/CloudHv/CloudHvX64.fdf                |  2 +-
> > > >  OvmfPkg/Library/PlatformInitLib/Platform.c    | 13 ++--
> > > >  .../QemuBootOrderLib/QemuBootOrderLib.c       |  8 ++-
> > > >  5 files changed, 82 insertions(+), 10 deletions(-)
> > > >  create mode 100644 OvmfPkg/CloudHv/CloudHvDefines.fdf.inc
> > > >
> > > > --
> > > > 2.32.0
> > >
> >

Re: [PATCH 0/4] OvmfPkg: CloudHv: Reduce PIO and MMIO accesses

[Boeuf, Sebastien]

[-- Attachment #1: Type: text/plain, Size: 4126 bytes --]

Thank you!
________________________________
From: Yao, Jiewen <jiewen.yao@intel.com>
Sent: Friday, June 3, 2022 12:52 PM
To: Boeuf, Sebastien <sebastien.boeuf@intel.com>; devel@edk2.groups.io <devel@edk2.groups.io>
Cc: kraxel@redhat.com <kraxel@redhat.com>; Justen, Jordan L <jordan.l.justen@intel.com>
Subject: RE: [PATCH 0/4] OvmfPkg: CloudHv: Reduce PIO and MMIO accesses

Merged https://github.com/tianocore/edk2/pull/2942

> -----Original Message-----
> From: Boeuf, Sebastien <sebastien.boeuf@intel.com>
> Sent: Thursday, June 2, 2022 5:29 PM
> To: Yao, Jiewen <jiewen.yao@intel.com>; devel@edk2.groups.io
> Cc: kraxel@redhat.com; Justen, Jordan L <jordan.l.justen@intel.com>
> Subject: Re: [PATCH 0/4] OvmfPkg: CloudHv: Reduce PIO and MMIO accesses
>
> On Thu, 2022-06-02 at 11:04 +0200, Sebastien Boeuf wrote:
> > On Thu, 2022-06-02 at 08:57 +0000, Yao, Jiewen wrote:
> > > Acked-by: Jiewen Yao <Jiewen.yao@intel.com>
> > >
> > > I notice the PR failed -
> > > https://github.com/tianocore/edk2/pull/2875
> > >
> > > I just want to double confirm, do you have a success PR for this
> > > patch set?
> >
> > Let me repush the PR once rebased on latest master. I think the
> > failures were only related to the Windows CI issues.
>
> Ok the CI is passing fine after I rebased on latest master. See
> https://github.com/tianocore/edk2/pull/2875
>
> Thanks,
> Sebastien
>
> >
> > Thanks,
> > Sebastien
> >
> > >
> > > Thank you
> > > Yao Jiewen
> > >
> > > > -----Original Message-----
> > > > From: Boeuf, Sebastien <sebastien.boeuf@intel.com>
> > > > Sent: Tuesday, May 10, 2022 8:51 PM
> > > > To: devel@edk2.groups.io
> > > > Cc: Yao, Jiewen <jiewen.yao@intel.com>; Justen, Jordan L
> > > > <jordan.l.justen@intel.com>; kraxel@redhat.com; Boeuf, Sebastien
> > > > <sebastien.boeuf@intel.com>
> > > > Subject: [PATCH 0/4] OvmfPkg: CloudHv: Reduce PIO and MMIO
> > > > accesses
> > > >
> > > > From: Sebastien Boeuf <sebastien.boeuf@intel.com>
> > > >
> > > > The goal of this series is to reduce the amount of inappropriate
> > > > PIO
> > > > and MMIO accesses generated by the firmware when running on Cloud
> > > > Hypervisor.
> > > >
> > > > For MMIO accesses, it is about providing the right base address
> > > > where
> > > > the firmware will be loaded by the VMM in order to avoid
> > > > unexpected
> > > > accesses to some address ranges.
> > > >
> > > > For PIO accesses, it is about preventing some read/write to be
> > > > performed
> > > > in the first place, as we know the underlying device is not
> > > > emulated by
> > > > Cloud Hypervisor.
> > > >
> > > > Signed-off-by: Sebastien Boeuf <sebastien.boeuf@intel.com>
> > > >
> > > > Sebastien Boeuf (4):
> > > >   OvmfPkg: CloudHv: Fix FW_BASE_ADDRESS
> > > >   OvmfPkg: Check for QemuFwCfg availability before accessing it
> > > >   OvmfPkg: CloudHv: Rely on QemuFwCfgLibNull implementation
> > > >   OvmfPkg: Don't access A20 gate register on Cloud Hypervisor
> > > >
> > > >  OvmfPkg/CloudHv/CloudHvDefines.fdf.inc        | 65
> > > > +++++++++++++++++++
> > > >  OvmfPkg/CloudHv/CloudHvX64.dsc                |  4 +-
> > > >  OvmfPkg/CloudHv/CloudHvX64.fdf                |  2 +-
> > > >  OvmfPkg/Library/PlatformInitLib/Platform.c    | 13 ++--
> > > >  .../QemuBootOrderLib/QemuBootOrderLib.c       |  8 ++-
> > > >  5 files changed, 82 insertions(+), 10 deletions(-)
> > > >  create mode 100644 OvmfPkg/CloudHv/CloudHvDefines.fdf.inc
> > > >
> > > > --
> > > > 2.32.0
> > >
> >

---------------------------------------------------------------------
Intel Corporation SAS (French simplified joint stock company)
Registered headquarters: "Les Montalets"- 2, rue de Paris, 
92196 Meudon Cedex, France
Registration Number:  302 456 199 R.C.S. NANTERRE
Capital: 5 208 026.16 Euros

This e-mail and any attachments may contain confidential material for
the sole use of the intended recipient(s). Any review or distribution
by others is strictly prohibited. If you are not the intended
recipient, please contact the sender and delete all copies.

[-- Attachment #2: Type: text/html, Size: 6587 bytes --]