From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by mx.groups.io with SMTP id smtpd.web08.9091.1645271832752102625 for ; Sat, 19 Feb 2022 03:58:10 -0800 Authentication-Results: mx.groups.io; dkim=fail reason="unable to parse pub key" header.i=@intel.com header.s=intel header.b=m2sVDCbV; spf=pass (domain: intel.com, ip: 192.55.52.151, mailfrom: min.m.xu@intel.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1645271889; x=1676807889; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=a67q141YtsUvL10BgvgmnR1f0sAGgJDscE/AIPWqKJg=; b=m2sVDCbVRDqqkHUAYp9ATuCmg6T9UpmIDavXsJY+M+dpk9LJWKeAEox0 4dQnFdvVs7Z0yqM8een+J0qU6AkTf9yobZR+jweUORJU7vYhJtLuiWMSe M2+7pV9U+QdAJuvEdiU+DK25eBp2rCLyQnk6ca3fBorSvM3D3bQYk0fPK DRxQ/NxpYa5+Bu7/jxAaDE0GTYi4Vb4zoQY1NoGKjijrKkatOZTIv/0hS CXsJ+rktR9EU36Ojln4lkixXUheEfHh9I/RAGDKbipWH/bTFtFXX8TGQR IYB8P1c2zK/CKDmm9F2jp0ws8kFnP9kOxivAt2KNQ9lhhN3f9n0b8PueY w==; X-IronPort-AV: E=McAfee;i="6200,9189,10262"; a="231915426" X-IronPort-AV: E=Sophos;i="5.88,381,1635231600"; d="scan'208";a="231915426" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Feb 2022 03:58:09 -0800 X-IronPort-AV: E=Sophos;i="5.88,381,1635231600"; d="scan'208";a="546691244" Received: from mxu9-mobl1.ccr.corp.intel.com ([10.249.175.253]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Feb 2022 03:58:06 -0800 From: "Min Xu" To: devel@edk2.groups.io Cc: Min Xu , Ard Biesheuvel , Jordan Justen , Brijesh Singh , Erdem Aktas , James Bottomley , Jiewen Yao , Tom Lendacky , Gerd Hoffmann Subject: [PATCH V6 20/42] OvmfPkg/PlatformPei: Update hob functions PlatformInitLib Date: Sat, 19 Feb 2022 19:56:33 +0800 Message-Id: X-Mailer: git-send-email 2.29.2.windows.2 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit RFC: https://bugzilla.tianocore.org/show_bug.cgi?id=3429 Hob functions in OvmfPkg/PlatformPei are updated with the ones in PlatformInitLib. Cc: Ard Biesheuvel Cc: Jordan Justen Cc: Brijesh Singh Cc: Erdem Aktas Cc: James Bottomley Cc: Jiewen Yao Cc: Tom Lendacky Cc: Gerd Hoffmann Signed-off-by: Min Xu --- OvmfPkg/PlatformPei/MemDetect.c | 20 +++---- OvmfPkg/PlatformPei/Platform.c | 101 ++++---------------------------- OvmfPkg/PlatformPei/Platform.h | 31 ---------- 3 files changed, 21 insertions(+), 131 deletions(-) diff --git a/OvmfPkg/PlatformPei/MemDetect.c b/OvmfPkg/PlatformPei/MemDetect.c index d118dba2f214..d19a344d18b8 100644 --- a/OvmfPkg/PlatformPei/MemDetect.c +++ b/OvmfPkg/PlatformPei/MemDetect.c @@ -274,10 +274,10 @@ ScanOrAdd64BitE820Ram ( End = (E820Entry.BaseAddr + E820Entry.Length) & ~(UINT64)EFI_PAGE_MASK; if (Base < End) { - AddMemoryRangeHob (Base, End); + PlatformAddMemoryRangeHob (Base, End); DEBUG (( DEBUG_VERBOSE, - "%a: AddMemoryRangeHob [0x%Lx, 0x%Lx)\n", + "%a: PlatformAddMemoryRangeHob [0x%Lx, 0x%Lx)\n", __FUNCTION__, Base, End @@ -743,8 +743,8 @@ QemuInitializeRamBelow1gb ( ) { if (FeaturePcdGet (PcdSmmSmramRequire) && mQ35SmramAtDefaultSmbase) { - AddMemoryRangeHob (0, SMM_DEFAULT_SMBASE); - AddReservedMemoryBaseSizeHob ( + PlatformAddMemoryRangeHob (0, SMM_DEFAULT_SMBASE); + PlatformAddReservedMemoryBaseSizeHob ( SMM_DEFAULT_SMBASE, MCH_DEFAULT_SMBASE_SIZE, TRUE /* Cacheable */ @@ -753,12 +753,12 @@ QemuInitializeRamBelow1gb ( SMM_DEFAULT_SMBASE + MCH_DEFAULT_SMBASE_SIZE < BASE_512KB + BASE_128KB, "end of SMRAM at default SMBASE ends at, or exceeds, 640KB" ); - AddMemoryRangeHob ( + PlatformAddMemoryRangeHob ( SMM_DEFAULT_SMBASE + MCH_DEFAULT_SMBASE_SIZE, BASE_512KB + BASE_128KB ); } else { - AddMemoryRangeHob (0, BASE_512KB + BASE_128KB); + PlatformAddMemoryRangeHob (0, BASE_512KB + BASE_128KB); } } @@ -816,14 +816,14 @@ QemuInitializeRam ( UINT32 TsegSize; TsegSize = mQ35TsegMbytes * SIZE_1MB; - AddMemoryRangeHob (BASE_1MB, LowerMemorySize - TsegSize); - AddReservedMemoryBaseSizeHob ( + PlatformAddMemoryRangeHob (BASE_1MB, LowerMemorySize - TsegSize); + PlatformAddReservedMemoryBaseSizeHob ( LowerMemorySize - TsegSize, TsegSize, TRUE ); } else { - AddMemoryRangeHob (BASE_1MB, LowerMemorySize); + PlatformAddMemoryRangeHob (BASE_1MB, LowerMemorySize); } // @@ -835,7 +835,7 @@ QemuInitializeRam ( if (EFI_ERROR (Status)) { UpperMemorySize = GetSystemMemorySizeAbove4gb (); if (UpperMemorySize != 0) { - AddMemoryBaseSizeHob (BASE_4GB, UpperMemorySize); + PlatformAddMemoryBaseSizeHob (BASE_4GB, UpperMemorySize); } } } diff --git a/OvmfPkg/PlatformPei/Platform.c b/OvmfPkg/PlatformPei/Platform.c index 594891786440..62480c3c40e5 100644 --- a/OvmfPkg/PlatformPei/Platform.c +++ b/OvmfPkg/PlatformPei/Platform.c @@ -57,85 +57,6 @@ BOOLEAN mS3Supported = FALSE; UINT32 mMaxCpuCount; -VOID -AddIoMemoryBaseSizeHob ( - EFI_PHYSICAL_ADDRESS MemoryBase, - UINT64 MemorySize - ) -{ - BuildResourceDescriptorHob ( - EFI_RESOURCE_MEMORY_MAPPED_IO, - EFI_RESOURCE_ATTRIBUTE_PRESENT | - EFI_RESOURCE_ATTRIBUTE_INITIALIZED | - EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE | - EFI_RESOURCE_ATTRIBUTE_TESTED, - MemoryBase, - MemorySize - ); -} - -VOID -AddReservedMemoryBaseSizeHob ( - EFI_PHYSICAL_ADDRESS MemoryBase, - UINT64 MemorySize, - BOOLEAN Cacheable - ) -{ - BuildResourceDescriptorHob ( - EFI_RESOURCE_MEMORY_RESERVED, - EFI_RESOURCE_ATTRIBUTE_PRESENT | - EFI_RESOURCE_ATTRIBUTE_INITIALIZED | - EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE | - (Cacheable ? - EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE | - EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE | - EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE : - 0 - ) | - EFI_RESOURCE_ATTRIBUTE_TESTED, - MemoryBase, - MemorySize - ); -} - -VOID -AddIoMemoryRangeHob ( - EFI_PHYSICAL_ADDRESS MemoryBase, - EFI_PHYSICAL_ADDRESS MemoryLimit - ) -{ - AddIoMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase)); -} - -VOID -AddMemoryBaseSizeHob ( - EFI_PHYSICAL_ADDRESS MemoryBase, - UINT64 MemorySize - ) -{ - BuildResourceDescriptorHob ( - EFI_RESOURCE_SYSTEM_MEMORY, - EFI_RESOURCE_ATTRIBUTE_PRESENT | - EFI_RESOURCE_ATTRIBUTE_INITIALIZED | - EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE | - EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE | - EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE | - EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE | - EFI_RESOURCE_ATTRIBUTE_TESTED, - MemoryBase, - MemorySize - ); -} - -VOID -AddMemoryRangeHob ( - EFI_PHYSICAL_ADDRESS MemoryBase, - EFI_PHYSICAL_ADDRESS MemoryLimit - ) -{ - AddMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase)); -} - VOID MemMapInitialization ( VOID @@ -155,12 +76,12 @@ MemMapInitialization ( // // Video memory + Legacy BIOS region // - AddIoMemoryRangeHob (0x0A0000, BASE_1MB); + PlatformAddIoMemoryRangeHob (0x0A0000, BASE_1MB); if (mHostBridgeDevId == 0xffff /* microvm */) { - AddIoMemoryBaseSizeHob (MICROVM_GED_MMIO_BASE, SIZE_4KB); - AddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB); /* ioapic #1 */ - AddIoMemoryBaseSizeHob (0xFEC10000, SIZE_4KB); /* ioapic #2 */ + PlatformAddIoMemoryBaseSizeHob (MICROVM_GED_MMIO_BASE, SIZE_4KB); + PlatformAddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB); /* ioapic #1 */ + PlatformAddIoMemoryBaseSizeHob (0xFEC10000, SIZE_4KB); /* ioapic #2 */ return; } @@ -194,20 +115,20 @@ MemMapInitialization ( // 0xFEE00000 LAPIC 1 MB // PciSize = 0xFC000000 - PciBase; - AddIoMemoryBaseSizeHob (PciBase, PciSize); + PlatformAddIoMemoryBaseSizeHob (PciBase, PciSize); PcdStatus = PcdSet64S (PcdPciMmio32Base, PciBase); ASSERT_RETURN_ERROR (PcdStatus); PcdStatus = PcdSet64S (PcdPciMmio32Size, PciSize); ASSERT_RETURN_ERROR (PcdStatus); - AddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB); - AddIoMemoryBaseSizeHob (0xFED00000, SIZE_1KB); + PlatformAddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB); + PlatformAddIoMemoryBaseSizeHob (0xFED00000, SIZE_1KB); if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) { - AddIoMemoryBaseSizeHob (ICH9_ROOT_COMPLEX_BASE, SIZE_16KB); + PlatformAddIoMemoryBaseSizeHob (ICH9_ROOT_COMPLEX_BASE, SIZE_16KB); // // Note: there should be an // - // AddIoMemoryBaseSizeHob (PciExBarBase, SIZE_256MB); + // PlatformAddIoMemoryBaseSizeHob (PciExBarBase, SIZE_256MB); // // call below, just like the one above for RCBA. However, Linux insists // that the MMCONFIG area be marked in the E820 or UEFI memory map as @@ -225,7 +146,7 @@ MemMapInitialization ( // is most definitely not RAM; so, as an exception, cover it with // uncacheable reserved memory right here. // - AddReservedMemoryBaseSizeHob (PciExBarBase, SIZE_256MB, FALSE); + PlatformAddReservedMemoryBaseSizeHob (PciExBarBase, SIZE_256MB, FALSE); BuildMemoryAllocationHob ( PciExBarBase, SIZE_256MB, @@ -233,7 +154,7 @@ MemMapInitialization ( ); } - AddIoMemoryBaseSizeHob (PcdGet32 (PcdCpuLocalApicBaseAddress), SIZE_1MB); + PlatformAddIoMemoryBaseSizeHob (PcdGet32 (PcdCpuLocalApicBaseAddress), SIZE_1MB); // // On Q35, the IO Port space is available for PCI resource allocations from diff --git a/OvmfPkg/PlatformPei/Platform.h b/OvmfPkg/PlatformPei/Platform.h index 24e4da4e1d93..f193ff736549 100644 --- a/OvmfPkg/PlatformPei/Platform.h +++ b/OvmfPkg/PlatformPei/Platform.h @@ -11,37 +11,6 @@ #include -VOID -AddIoMemoryBaseSizeHob ( - EFI_PHYSICAL_ADDRESS MemoryBase, - UINT64 MemorySize - ); - -VOID -AddIoMemoryRangeHob ( - EFI_PHYSICAL_ADDRESS MemoryBase, - EFI_PHYSICAL_ADDRESS MemoryLimit - ); - -VOID -AddMemoryBaseSizeHob ( - EFI_PHYSICAL_ADDRESS MemoryBase, - UINT64 MemorySize - ); - -VOID -AddMemoryRangeHob ( - EFI_PHYSICAL_ADDRESS MemoryBase, - EFI_PHYSICAL_ADDRESS MemoryLimit - ); - -VOID -AddReservedMemoryBaseSizeHob ( - EFI_PHYSICAL_ADDRESS MemoryBase, - UINT64 MemorySize, - BOOLEAN Cacheable - ); - VOID AddressWidthInitialization ( VOID -- 2.29.2.windows.2