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charset="us-ascii" Content-ID: <8BB5DCCC3441D04F946E36136BF1459D@namprd12.prod.outlook.com> Content-Transfer-Encoding: quoted-printable From: Tom Lendacky BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2198 Under SEV-ES, a CPUID intercept generates a #VC exception. VMGEXIT must be used to allow the hypervisor to handle this intercept. Add support to construct the required GHCB values to support a CPUID NAE event. Additionally, CPUID 0x0000_000d requires XCR0 to be supplied in the GHCB, so add support to issue the XGETBV instruction. Cc: Eric Dong Cc: Ray Ni Cc: Laszlo Ersek Signed-off-by: Tom Lendacky --- .../X64/AMDSevVcCommon.c | 45 +++++++++++++++++++ 1 file changed, 45 insertions(+) diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/AMDSevVcCommon.c= b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/AMDSevVcCommon.c index ce5514fd0fb6..29119ba863d3 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/AMDSevVcCommon.c +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/AMDSevVcCommon.c @@ -4,6 +4,8 @@ #include #include "AMDSevVcCommon.h" =20 +#define CR4_OSXSAVE (1 << 18) + typedef enum { LongMode64Bit =3D 0, LongModeCompat32Bit, @@ -481,6 +483,45 @@ IoioExit ( return 0; } =20 +STATIC +UINTN +CpuidExit ( + GHCB *Ghcb, + EFI_SYSTEM_CONTEXT_X64 *Regs, + SEV_ES_INSTRUCTION_DATA *InstructionData + ) +{ + UINTN Status; + + Ghcb->SaveArea.Rax =3D Regs->Rax; + GhcbSetRegValid (Ghcb, GhcbRax); + Ghcb->SaveArea.Rcx =3D Regs->Rcx; + GhcbSetRegValid (Ghcb, GhcbRcx); + if (Regs->Rax =3D=3D 0x0000000d) { + Ghcb->SaveArea.XCr0 =3D (AsmReadCr4 () & CR4_OSXSAVE) ? AsmXGetBv (0) = : 1; + GhcbSetRegValid (Ghcb, GhcbXCr0); + } + + Status =3D VmgExit (Ghcb, SvmExitCpuid, 0, 0); + if (Status) { + return Status; + } + + if (!GhcbIsRegValid (Ghcb, GhcbRax) || + !GhcbIsRegValid (Ghcb, GhcbRbx) || + !GhcbIsRegValid (Ghcb, GhcbRcx) || + !GhcbIsRegValid (Ghcb, GhcbRdx)) { + VmgExit (Ghcb, SvmExitUnsupported, SvmExitCpuid, 0); + ASSERT (0); + } + Regs->Rax =3D Ghcb->SaveArea.Rax; + Regs->Rbx =3D Ghcb->SaveArea.Rbx; + Regs->Rcx =3D Ghcb->SaveArea.Rcx; + Regs->Rdx =3D Ghcb->SaveArea.Rdx; + + return 0; +} + UINTN DoVcCommon ( GHCB *Ghcb, @@ -497,6 +538,10 @@ DoVcCommon ( =20 ExitCode =3D Regs->ExceptionData; switch (ExitCode) { + case SvmExitCpuid: + NaeExit =3D CpuidExit; + break; + case SvmExitIoioProt: NaeExit =3D IoioExit; break; --=20 2.17.1