From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=216.228.121.64; helo=hqemgate15.nvidia.com; envelope-from=jbrasen@nvidia.com; receiver=edk2-devel@lists.01.org Received: from hqemgate15.nvidia.com (hqemgate15.nvidia.com [216.228.121.64]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 3DC30211648B7 for ; Tue, 9 Oct 2018 10:51:06 -0700 (PDT) Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 09 Oct 2018 10:50:08 -0700 Received: from HQMAIL106.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Tue, 09 Oct 2018 10:51:05 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Tue, 09 Oct 2018 10:51:05 -0700 Received: from HQMAIL106.nvidia.com (172.18.146.12) by HQMAIL106.nvidia.com (172.18.146.12) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Tue, 9 Oct 2018 17:51:05 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL106.nvidia.com (172.18.146.12) with Microsoft SMTP Server (TLS) id 15.0.1395.4 via Frontend Transport; Tue, 9 Oct 2018 17:51:05 +0000 Received: from jbrasen-ux.nvidia.com (Not Verified[10.28.48.113]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Tue, 09 Oct 2018 10:51:05 -0700 From: Jeff Brasen To: CC: Jeff Brasen Date: Tue, 9 Oct 2018 11:50:37 -0600 Message-ID: X-Mailer: git-send-email 2.7.4 In-Reply-To: References: X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1539107408; bh=m4CNpar09k7vc6JDn3LCp4Byh6bmX8dZJh5L2UaIyTo=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=clJmeXvqoPxCJLgPwUahnzrTUWtFBLxV5TIjnjGpo2qDYxd5iQFCs0TQOBV2uNEvq w8IRiCwok1QYsfKx8DivSuCgc07DWmoKYg/n3XYAHa7lqmQfu+L6CO0JKMy9Mi4zpe ZXBixNEEWChZIfPi2U0uZgHU6KIcPAzXU5UFOltXD2i7KcsNfavygQU7hamfSrj3CP hP8eVgGHNsSyCPU+GW0NAjY7QFtg13GbnjemWO0+ZwKGtPHLEzhUG4NOnwj5IEvxrd kNnRmEx6elETTg0QzKzkCy/CWzHTBTssDTOoooXE85+KOhRnRONdZDQ4b8gruFlSK2 SHiSc4+AUDqyw== Subject: [PATCH v2 2/2] MdeModulePkg/SdMmcPciHcDxe: Allow additional SDHCI versions X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 09 Oct 2018 17:51:06 -0000 Content-Type: text/plain Clock control is similar in SDHCI versions greater then version 2. Add support for more recent versions of the controller specification. SD card support for 1.8V is also present in controller versions 3 and greater. https://bugzilla.tianocore.org/show_bug.cgi?id=1233 Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jeff Brasen --- MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c | 3 ++- MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c index d3f77ed..6ee9ed7 100644 --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c @@ -978,7 +978,8 @@ SdCardIdentification ( return Status; } - if ((ControllerVer & 0xFF) == SD_MMC_HC_CTRL_VER_300) { + if (((ControllerVer & 0xFF) >= SD_MMC_HC_CTRL_VER_300) && + ((ControllerVer & 0xFF) <= SD_MMC_HC_CTRL_VER_420)) { S18r = TRUE; } else if (((ControllerVer & 0xFF) == SD_MMC_HC_CTRL_VER_100) || ((ControllerVer & 0xFF) == SD_MMC_HC_CTRL_VER_200)) { S18r = FALSE; diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c index 3b9a184..bedc968 100644 --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c @@ -782,7 +782,8 @@ SdMmcHcClockSupply ( // // Set SDCLK Frequency Select and Internal Clock Enable fields in Clock Control register. // - if ((ControllerVer & 0xFF) == SD_MMC_HC_CTRL_VER_300) { + if (((ControllerVer & 0xFF) >= SD_MMC_HC_CTRL_VER_300) && + ((ControllerVer & 0xFF) <= SD_MMC_HC_CTRL_VER_420)) { ASSERT (Divisor <= 0x3FF); ClockCtrl = ((Divisor & 0xFF) << 8) | ((Divisor & 0x300) >> 2); } else if (((ControllerVer & 0xFF) == 0) || ((ControllerVer & 0xFF) == 1)) { -- 2.7.4