From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by mx.groups.io with SMTP id smtpd.web10.52.1584422799131442965 for ; Mon, 16 Mar 2020 22:26:39 -0700 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 192.55.52.120, mailfrom: liming.gao@intel.com) IronPort-SDR: JtK9SOcKVM2ticoVZ4gSjIaSrdqjbrZfCx6VvgwXYcT3NbuaMmdY4NCfFPprb4KCJWAof9TO16 kklY/wt5mazA== X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Mar 2020 22:26:38 -0700 IronPort-SDR: rdCORD4xYkm9twBTsiI6BAYDoLpf/9ArjHiBnjtCnXjGUfovNBNCtDBXen45VumnmjhT1as+9W P3QQLrR+8jGQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.70,563,1574150400"; d="scan'208";a="262919070" Received: from fmsmsx105.amr.corp.intel.com ([10.18.124.203]) by orsmga002.jf.intel.com with ESMTP; 16 Mar 2020 22:26:38 -0700 Received: from shsmsx605.ccr.corp.intel.com (10.109.6.215) by FMSMSX105.amr.corp.intel.com (10.18.124.203) with Microsoft SMTP Server (TLS) id 14.3.439.0; Mon, 16 Mar 2020 22:26:38 -0700 Received: from shsmsx606.ccr.corp.intel.com (10.109.6.216) by SHSMSX605.ccr.corp.intel.com (10.109.6.215) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1713.5; Tue, 17 Mar 2020 13:26:35 +0800 Received: from shsmsx606.ccr.corp.intel.com ([10.109.6.216]) by SHSMSX606.ccr.corp.intel.com ([10.109.6.216]) with mapi id 15.01.1713.004; Tue, 17 Mar 2020 13:26:35 +0800 From: "Liming Gao" To: "Feng, Bob C" , "Fu, Siyuan" , "devel@edk2.groups.io" Subject: Re: [Patch] Silicon/Intel/Tools: Add parameter for microcode alignment in FitGen. Thread-Topic: [Patch] Silicon/Intel/Tools: Add parameter for microcode alignment in FitGen. Thread-Index: AQHV94hG4UeqvPR+w0K7elgD1hXkFqhDr0YAgAiaLRA= Date: Tue, 17 Mar 2020 05:26:35 +0000 Message-ID: References: <38bdd61c2ceb4bd5873b497e150d9cb8@intel.com> In-Reply-To: <38bdd61c2ceb4bd5873b497e150d9cb8@intel.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-version: 11.2.0.6 dlp-product: dlpe-windows dlp-reaction: no-action x-originating-ip: [10.239.127.36] MIME-Version: 1.0 Return-Path: liming.gao@intel.com Content-Language: en-US Content-Type: text/plain; charset="iso-2022-jp" Content-Transfer-Encoding: quoted-printable Siyuan: Sorry for the late response. Please also update tool minor version to mat= ch this change. #define UTILITY_MINOR_VERSION 60 =3D=3D> #define UTILITY_MINOR_VERSION 61 It is defined edk2-platforms\Silicon\Intel\Tools\FitGen\FitGen.h Thanks Liming -----Original Message----- From: Feng, Bob C =20 Sent: 2020=1B$BG/=1B(B3=1B$B7n=1B(B12=1B$BF|=1B(B 10:02 To: Fu, Siyuan ; devel@edk2.groups.io Cc: Gao, Liming Subject: RE: [Patch] Silicon/Intel/Tools: Add parameter for microcode align= ment in FitGen. Reviewed-by: Bob Feng -----Original Message----- From: Fu, Siyuan Sent: Wednesday, March 11, 2020 5:34 PM To: devel@edk2.groups.io Cc: Feng, Bob C ; Gao, Liming Subject: [Patch] Silicon/Intel/Tools: Add parameter for microcode alignment= in FitGen. The current FitGen has "-NA" parameter to indicate whether microcode is pla= ced with an alignment, but it could only support 0x800 alignment: - With"-NA" means microcode is not aligned. - No "-NA" means Microcode is 0x800 aligned. There is no method to specify other alignment value. This patch add "-A" option to FitGen for to configure the alignment to a us= er specified value. The change is backward compatible as: - Only "-NA" means microcode is not aligned (same as before). - No "-NA" and No "-A" means Microcode is 0x800 aligned (same as before). - Only "-A" means microcode is aligned with specified value (new). Cc: Bob Feng Cc: Liming Gao Signed-off-by: Siyuan Fu --- Silicon/Intel/Tools/FitGen/FitGen.c | 35 +++++++++++++++++++---------- 1 file changed, 23 insertions(+), 12 deletions(-) diff --git a/Silicon/Intel/Tools/FitGen/FitGen.c b/Silicon/Intel/Tools/FitG= en/FitGen.c index 49ec33a7fd..75d8932d90 100644 --- a/Silicon/Intel/Tools/FitGen/FitGen.c +++ b/Silicon/Intel/Tools/FitGen/FitGen.c @@ -260,7 +260,8 @@ typedef struct { FIT_TABLE_CONTEXT_ENTRY BiosModule[MAX_BIOS_MODULE_ENTRY]; UINT32 BiosModuleVersion; FIT_TABLE_CONTEXT_ENTRY Microcode[MAX_MICROCODE_ENTRY]; - BOOLEAN MicrocodeAlignment; + BOOLEAN MicrocodeIsAligned; + UINT32 MicrocodeAlignValue; UINT32 MicrocodeVersion; FIT_TABLE_CONTEXT_ENTRY OptionalModule[MAX_OPTIONAL_ENTRY]; FIT_TABLE_CONTEXT_ENTRY PortModule[MAX_PORT_ENTRY]; @@ -325,6 +326,7 @@ Returns: "\t[-V ]\n" "\t[-F ] [-F ] [-V= ]\n" "\t[-NA]\n" + "\t[-A ]\n" "\t[-CLEAR]\n" "\t[-L ]\n" "\t[-I ]\n" @@ -357,7 +359,8 @@ Returns: printf ("\tMicrocodeGuid - Guid of Microcode Module.\n"); printf ("\tMicrocodeSlotSize - Occupied region size of each Microco= de binary.\n"); printf ("\tMicrocodeFfsGuid - Guid of FFS which is used to save Mi= crocode binary"); - printf ("\t-NA - No 0x800 aligned Microcode requireme= nt. No -NA means Microcode is 0x800 aligned.\n"); + printf ("\t-NA - No 0x800 aligned Microcode requireme= nt. No -NA means Microcode is aligned with option MicrocodeAlignment value.= \n"); + printf ("\tMicrocodeAlignment - HEX value of Microcode alignment. Ig= nored if \"-NA\" is specified. Default value is 0x800.\n"); printf ("\tRecordType - FIT entry record type. User should e= nsure it is ordered.\n"); printf ("\tRecordDataAddress - FIT entry record data address.\n"); printf ("\tRecordDataSize - FIT entry record data size.\n"); @@ -957,17 +960,25 @@ Returns: // if ((Index >=3D argc) || ((strcmp (argv[Index], "-NA") !=3D 0) && - (strcmp (argv[Index], "-na") !=3D 0)) ) { + (strcmp (argv[Index], "-na") !=3D 0) && + (strcmp (argv[Index], "-A") !=3D 0) && + (strcmp (argv[Index], "-a") !=3D 0))) { // // by pass // - gFitTableContext.MicrocodeAlignment =3D TRUE; - } else { + gFitTableContext.MicrocodeIsAligned =3D TRUE; + gFitTableContext.MicrocodeAlignValue =3D 0x800; } else if ((strcmp=20 + (argv[Index], "-NA") =3D=3D 0) || (strcmp (argv[Index], "-na") =3D=3D 0))= { + gFitTableContext.MicrocodeIsAligned =3D FALSE; + gFitTableContext.MicrocodeAlignValue =3D 1; + Index +=3D 1; + } else if ((strcmp (argv[Index], "-A") =3D=3D 0) || (strcmp (argv[Index]= , "-a") =3D=3D 0)) { + gFitTableContext.MicrocodeIsAligned =3D TRUE; // - // no alignment + // Get alignment from parameter // - gFitTableContext.MicrocodeAlignment =3D FALSE; - Index +=3D 1; + gFitTableContext.MicrocodeAlignValue =3D xtoi (argv[Index + 1]);; + Index +=3D 2; } =20 // @@ -1159,8 +1170,8 @@ Returns: // // MCU might be put at 2KB alignment, if so, we need to ad= just the size as 2KB alignment. // - if (gFitTableContext.MicrocodeAlignment) { - MicrocodeSize =3D (*(UINT32 *)(MicrocodeBuffer + 32) + M= ICROCODE_ALIGNMENT) & ~MICROCODE_ALIGNMENT; + if (gFitTableContext.MicrocodeIsAligned) { + MicrocodeSize =3D (*(UINT32 *)(MicrocodeBuffer + 32) +=20 + (gFitTableContext.MicrocodeAlignValue - 1)) &=20 + ~(gFitTableContext.MicrocodeAlignValue - 1); } else { MicrocodeSize =3D (*(UINT32 *)(MicrocodeBuffer + 32)); } @@ -1537,8 +1548,8 @@ Returns: // // MCU might be put at 2KB alignment, if so, we need to adjust the= size as 2KB alignment. // - if (gFitTableContext.MicrocodeAlignment) { - MicrocodeSize =3D (*(UINT32 *)(MicrocodeBuffer + 32) + MICROCODE= _ALIGNMENT) & ~MICROCODE_ALIGNMENT; + if (gFitTableContext.MicrocodeIsAligned) { + MicrocodeSize =3D (*(UINT32 *)(MicrocodeBuffer + 32) +=20 + (gFitTableContext.MicrocodeAlignValue - 1)) &=20 + ~(gFitTableContext.MicrocodeAlignValue - 1); } else { MicrocodeSize =3D (*(UINT32 *)(MicrocodeBuffer + 32)); } -- 2.19.1.windows.1