From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=192.55.52.120; helo=mga04.intel.com; envelope-from=ruiyu.ni@intel.com; receiver=edk2-devel@lists.01.org Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id A88E421163DF9 for ; Tue, 9 Oct 2018 00:47:04 -0700 (PDT) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga104.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 09 Oct 2018 00:47:04 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.54,359,1534834800"; d="scan'208";a="97737970" Received: from ray-dev.ccr.corp.intel.com (HELO [10.239.9.11]) ([10.239.9.11]) by orsmga001.jf.intel.com with ESMTP; 09 Oct 2018 00:47:02 -0700 To: Eric Dong , edk2-devel@lists.01.org Cc: Laszlo Ersek , Jian J Wang References: <20181009060100.6984-1-eric.dong@intel.com> From: "Ni, Ruiyu" Message-ID: Date: Tue, 9 Oct 2018 15:48:10 +0800 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:52.0) Gecko/20100101 Thunderbird/52.9.1 MIME-Version: 1.0 In-Reply-To: <20181009060100.6984-1-eric.dong@intel.com> Subject: Re: [Patch v3] UefiCpuPkg/S3Resume2Pei: disable paging before creating new page table. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 09 Oct 2018 07:47:04 -0000 Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit On 10/9/2018 2:01 PM, Eric Dong wrote: > V3 changes: > No need to change inf file. Also update commit message to include regression info. > > V2 changes: > Only disable paging in 32 bit mode, no matter it is enable or not. > > V1 changes: > PEI Stack Guard needs to enable paging. This might cause #GP if code > trying to write CR3 register with PML4 page table while the processor > is enabled with PAE paging. > > Simply disabling paging before updating CR3 can solve this conflict. > > It's an regression caused by change: 0a0d5296e448fc350de1594c49b9c0deff7fad60 > > BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=1232 > > Cc: Ruiyu Ni > Cc: Laszlo Ersek > Cc: Jian J Wang > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by:Eric Dong > --- > UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume.c | 8 ++++++++ > 1 file changed, 8 insertions(+) > > diff --git a/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume.c b/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume.c > index f164c1713b..53ed76c6e6 100644 > --- a/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume.c > +++ b/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume.c > @@ -1105,6 +1105,14 @@ S3RestoreConfig2 ( > // > SetInterruptState (InterruptStatus); > > + if (sizeof(UINTN) == sizeof(UINT32)) { > + // > + // Paging maybe enabled. If current mode is 32 bit mode and code try to > + // enable 64 bit mode page table, it will cause GP fault. > + // To avoid conflict configuration, disable paging first anyway. > + // > + AsmWriteCr0 (AsmReadCr0 () & (~BIT31)); > + } > AsmWriteCr3 ((UINTN)SmmS3ResumeState->SmmS3Cr3); > > // > Reviewed-by: Ruiyu Ni -- Thanks, Ray