From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from hqnvemgate26.nvidia.com (hqnvemgate26.nvidia.com [216.228.121.65]) by mx.groups.io with SMTP id smtpd.web11.4638.1591725395898279585 for ; Tue, 09 Jun 2020 10:56:36 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@nvidia.com header.s=n1 header.b=OIFQeTMY; spf=pass (domain: nvidia.com, ip: 216.228.121.65, mailfrom: ipark@nvidia.com) Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate26.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 09 Jun 2020 10:56:22 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Tue, 09 Jun 2020 10:56:35 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Tue, 09 Jun 2020 10:56:35 -0700 Received: from HQMAIL105.nvidia.com (172.20.187.12) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Tue, 9 Jun 2020 17:56:35 +0000 Received: from rnnvemgw01.nvidia.com (10.128.109.123) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Tue, 9 Jun 2020 17:56:35 +0000 Received: from ipark-ubuntu.nvidia.com (Not Verified[10.28.100.106]) by rnnvemgw01.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Tue, 09 Jun 2020 10:56:34 -0700 From: "Irene Park" To: CC: Irene Park Subject: [PATCH] ArmPlatformPkg/PL011UartLib: Check PID2 if FiFoDepth is zero Date: Tue, 9 Jun 2020 13:56:31 -0400 Message-ID: X-Mailer: git-send-email 2.7.4 X-NVConfidentiality: public Return-Path: ipark@nvidia.com MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1591725382; bh=qD/a6OCblPcpWwdDUl2sC4bSiH/mTAbGc06Wy7v1n0c=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: X-NVConfidentiality:MIME-Version:Content-Type; b=OIFQeTMYRP2DDlQb+xbAwi9L4gF4WXW+HP4M8ttA3SPPR9PaBcfJz9010MDZMBNa5 QC5f6Y9aexhr065XqoICbBt/9MQNEMsjL8kwcbz14ts9Gro0Ns52ZPKM6ebu5s/EI1 UxeNA8NSk4XL93lwtZUXCHHDUAF8IwAaex39s17BYd5nBNJ+o07p609MiO6eSFdp8L CxvQ1NKIo629WAKlRJO/+vGePVzuqRnYTuOMZzO7GhWWlbQy85xse6t7+kct67mCuQ umJnUGZzqhRhvJfOY2JP5vYllhjun1xiZj2kp75aMsftp1fWUOfBW5ufC9fcWwjY9Q s2gaEx/1RpbgQ== Content-Type: text/plain From: Irene Park PL011UartLib determines its FIFO depth based on the PID2 value but the register PID2 is not mandatory as per the SBSA spec. This change won't check PID2 if PcdUartDefaultReceiveFifoDepth is set to a value > 0. Change-Id: I2dd7b3412f9306888078e0cb0488b902d4a8ace9 Signed-off-by: Irene Park --- ArmPlatformPkg/Library/PL011UartLib/PL011UartLib.c | 4 ++++ ArmPlatformPkg/Library/PL011UartLib/PL011UartLib.inf | 1 + 2 files changed, 5 insertions(+) diff --git a/ArmPlatformPkg/Library/PL011UartLib/PL011UartLib.c b/ArmPlatformPkg/Library/PL011UartLib/PL011UartLib.c index 801990d..05ad1ad 100644 --- a/ArmPlatformPkg/Library/PL011UartLib/PL011UartLib.c +++ b/ArmPlatformPkg/Library/PL011UartLib/PL011UartLib.c @@ -79,9 +79,13 @@ PL011UartInitializePort ( UINT32 Fractional; UINT32 HardwareFifoDepth; + HardwareFifoDepth = FixedPcdGet16 (PcdUartDefaultReceiveFifoDepth); +#if FixedPcdGet16 (PcdUartDefaultReceiveFifoDepth) == 0 HardwareFifoDepth = (PL011_UARTPID2_VER (MmioRead32 (UartBase + UARTPID2)) \ > PL011_VER_R1P4) \ ? 32 : 16 ; +#endif + // The PL011 supports a buffer of 1, 16 or 32 chars. Therefore we can accept // 1 char buffer as the minimum FIFO size. Because everything can be rounded // down, there is no maximum FIFO size. diff --git a/ArmPlatformPkg/Library/PL011UartLib/PL011UartLib.inf b/ArmPlatformPkg/Library/PL011UartLib/PL011UartLib.inf index d99e89f..e3da507 100644 --- a/ArmPlatformPkg/Library/PL011UartLib/PL011UartLib.inf +++ b/ArmPlatformPkg/Library/PL011UartLib/PL011UartLib.inf @@ -30,6 +30,7 @@ ArmPlatformPkg/ArmPlatformPkg.dec [FixedPcd] + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultReceiveFifoDepth gEfiMdeModulePkgTokenSpaceGuid.PcdSerialBaudRate gArmPlatformTokenSpaceGuid.PL011UartInteger -- 2.7.4