From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by mx.groups.io with SMTP id smtpd.web10.25470.1686851593481588403 for ; Thu, 15 Jun 2023 10:53:16 -0700 Authentication-Results: mx.groups.io; dkim=fail reason="unable to parse pub key" header.i=@intel.com header.s=intel header.b=PyakrsKT; spf=pass (domain: intel.com, ip: 134.134.136.126, mailfrom: saloni.kasbekar@intel.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1686851596; x=1718387596; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=V6wKNte3w4gZlpfmhlLy0N648V7TpXoae4DZz9+Znpk=; b=PyakrsKTOie0nTOxZnq+6kX61waZu/mgLY3icP3G5zQHR8WnMT8bH7d0 mxHtdvkSbnnjoxVRpp9pJj3qDPjfE/Lu3ZjmZcuGRr7GGD97e2NaUpdgC XDuJb+2nf0Okf6k8ySEEhBfMFpu+I0OItbZmiUoPF073KqhvtqEPnX8Uo lN50APndsYMpcs+H5MV8X8HTUm9AlFa9EpdAwPzzKr89OoPh3+MNQ+2Rd IMOvMbrZxWipjDKmQ45y8NsOhQTRXdmOLqYQlc4FQyaIAPHFYrVKD2dMV CWyiclx24TkRocTyUGCNfE1piYTqwYIRYdbkalS6I5Pwlk3hzybWWRpfj w==; X-IronPort-AV: E=McAfee;i="6600,9927,10742"; a="343732750" X-IronPort-AV: E=Sophos;i="6.00,245,1681196400"; d="scan'208";a="343732750" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Jun 2023 10:53:15 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10742"; a="857053650" X-IronPort-AV: E=Sophos;i="6.00,245,1681196400"; d="scan'208";a="857053650" Received: from fmbiosdev02.amr.corp.intel.com ([10.105.221.44]) by fmsmga001-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Jun 2023 10:53:15 -0700 From: "Saloni Kasbekar" To: devel@edk2.groups.io Cc: Saloni Kasbekar , Sai Chaganty , Nate DeSimone , Isaac Oram , Rosen Chuang Subject: [PATCH 4/8] AlderlakeSiliconPkg/Pch: Add libraries Date: Thu, 15 Jun 2023 10:53:02 -0700 Message-Id: X-Mailer: git-send-email 2.36.1.windows.1 In-Reply-To: <6b58dd187980204b74c6ec718dad122674c213e1.1686851565.git.saloni.kasbekar@intel.com> References: <6b58dd187980204b74c6ec718dad122674c213e1.1686851565.git.saloni.kasbekar@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Adds the following libraries: - BasePchPciBdfLib - BaseResetSystemLib - PeiDxeSmmPchCycleDecodingLib Cc: Sai Chaganty Cc: Nate DeSimone Cc: Isaac Oram Cc: Rosen Chuang Signed-off-by: Saloni Kasbekar --- .../BasePchPciBdfLib/BasePchPciBdfLib.inf | 32 ++ .../Library/BasePchPciBdfLib/PchPciBdfLib.c | 308 ++++++++++++++++++ .../BaseResetSystemLib/BaseResetSystemLib.c | 114 +++++++ .../BaseResetSystemLib/BaseResetSystemLib.inf | 37 +++ .../PchCycleDecodingLib.c | 194 +++++++++++ .../PeiDxeSmmPchCycleDecodingLib.inf | 41 +++ 6 files changed, 726 insertions(+) create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Pch/Library/BasePchPciBdfLib/BasePchPciBdfLib.inf create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Pch/Library/BasePchPciBdfLib/PchPciBdfLib.c create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Pch/Library/BaseResetSystemLib/BaseResetSystemLib.c create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Pch/Library/BaseResetSystemLib/BaseResetSystemLib.inf create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Pch/Library/PeiDxeSmmPchCycleDecodingLib/PchCycleDecodingLib.c create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Pch/Library/PeiDxeSmmPchCycleDecodingLib/PeiDxeSmmPchCycleDecodingLib.inf diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Pch/Library/BasePchPciBdfLib/BasePchPciBdfLib.inf b/Silicon/Intel/AlderlakeSiliconPkg/Pch/Library/BasePchPciBdfLib/BasePchPciBdfLib.inf new file mode 100644 index 0000000000..e65f564c1b --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/Pch/Library/BasePchPciBdfLib/BasePchPciBdfLib.inf @@ -0,0 +1,32 @@ +## @file +# PCH PCIe Bus Device Function Library. +# +# All functions from this library are available in PEI, DXE, and SMM, +# But do not support UEFI RUNTIME environment call. +# +# Copyright (c) 2022, Intel Corporation. All rights reserved.
+# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +[Defines] +INF_VERSION = 0x00010017 +BASE_NAME = PeiDxeSmmPchPciBdfLib +FILE_GUID = A36363FC-2951-4DCF-AC81-16F4ED3FDA47 +VERSION_STRING = 1.0 +MODULE_TYPE = BASE +LIBRARY_CLASS = PchPciBdfLib + +[LibraryClasses] +BaseLib +IoLib +DebugLib +PciSegmentLib +PchInfoLib +PchPcieRpLib + +[Packages] +MdePkg/MdePkg.dec +AlderlakeSiliconPkg/SiPkg.dec + +[Sources] +PchPciBdfLib.c diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Pch/Library/BasePchPciBdfLib/PchPciBdfLib.c b/Silicon/Intel/AlderlakeSiliconPkg/Pch/Library/BasePchPciBdfLib/PchPciBdfLib.c new file mode 100644 index 0000000000..c26625e2eb --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/Pch/Library/BasePchPciBdfLib/PchPciBdfLib.c @@ -0,0 +1,308 @@ +/** @file + PCH PCIe Bus Device Function Library. + All functions from this library are available in PEI, DXE, and SMM, + But do not support UEFI RUNTIME environment call. + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include +#include + +/** + Check if a Device is present for PCH FRU + If the data is defined for PCH RFU return it + If the data is not defined (Device is NOT present) assert. + + @param[in] DataToCheck Device or Function number to check + + @retval Device or Function number value if defined for PCH FRU + 0xFF if not present in PCH FRU +**/ +UINT8 +CheckAndReturn ( + UINT8 DataToCheck + ) +{ + if (DataToCheck == NOT_PRESENT) { + ASSERT (FALSE); + } + return DataToCheck; +} + +/** + Get P2SB PCI device number + + @retval PCI dev number +**/ +UINT8 +P2sbDevNumber ( + VOID + ) +{ + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_P2SB); +} + +/** + Get P2SB PCI function number + + @retval PCI fun number +**/ +UINT8 +P2sbFuncNumber ( + VOID + ) +{ + return CheckAndReturn (PCI_FUNCTION_NUMBER_PCH_P2SB); +} + +/** + Get P2SB controller address that can be passed to the PCI Segment Library functions. + + @retval P2SB controller address in PCI Segment Library representation +**/ +UINT64 +P2sbPciCfgBase ( + VOID + ) +{ + return PCI_SEGMENT_LIB_ADDRESS ( + DEFAULT_PCI_SEGMENT_NUMBER_PCH, + DEFAULT_PCI_BUS_NUMBER_PCH, + P2sbDevNumber (), + P2sbFuncNumber (), + 0 + ); +} + + + +/** + Returns PCH SPI Device number + + @retval UINT8 PCH SPI Device number +**/ +UINT8 +SpiDevNumber ( + VOID + ) +{ + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_SPI); +} + +/** + Returns PCH SPI Function number + + @retval UINT8 PCH SPI Function number +**/ +UINT8 +SpiFuncNumber ( + VOID + ) +{ + return CheckAndReturn (PCI_FUNCTION_NUMBER_PCH_SPI); +} + +/** + Returns PCH SPI PCI Config Space base address + + @retval UINT64 PCH SPI Config Space base address +**/ +UINT64 +SpiPciCfgBase ( + VOID + ) +{ + return PCI_SEGMENT_LIB_ADDRESS ( + DEFAULT_PCI_SEGMENT_NUMBER_PCH, + DEFAULT_PCI_BUS_NUMBER_PCH, + SpiDevNumber (), + SpiFuncNumber (), + 0 + ); +} + +/** + Get XHCI controller PCIe Device Number + + @retval XHCI controller PCIe Device Number +**/ +UINT8 +PchXhciDevNumber ( + VOID + ) +{ + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_XHCI); +} + +/** + Get XHCI controller PCIe Function Number + + @retval XHCI controller PCIe Function Number +**/ +UINT8 +PchXhciFuncNumber ( + VOID + ) +{ + return CheckAndReturn (PCI_FUNCTION_NUMBER_PCH_XHCI); +} + +/** + Get LPC controller PCIe Device Number + + @retval LPC controller PCIe Device Number +**/ +UINT8 +LpcDevNumber ( + VOID + ) +{ + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_LPC); +} + +/** + Get LPC controller PCIe Function Number + + @retval LPC controller PCIe Function Number +**/ +UINT8 +LpcFuncNumber ( + VOID + ) +{ + return CheckAndReturn (PCI_FUNCTION_NUMBER_PCH_LPC); +} + +/** + Returns PCH LPC device PCI base address. + + @retval PCH LPC PCI base address. +**/ +UINT64 +LpcPciCfgBase ( + VOID + ) +{ + return PCI_SEGMENT_LIB_ADDRESS ( + DEFAULT_PCI_SEGMENT_NUMBER_PCH, + DEFAULT_PCI_BUS_NUMBER_PCH, + LpcDevNumber (), + LpcFuncNumber (), + 0 + ); +} + + + +/** + Get PCH PCIe controller PCIe Device Number + + @param[in] RpIndex Root port physical number. (0-based) + + @retval PCH PCIe controller PCIe Device Number +**/ +UINT8 +PchPcieRpDevNumber ( + IN UINTN RpIndex + ) +{ + switch (RpIndex) { + case 0: + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_1); + case 1: + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_2); + case 2: + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_3); + case 3: + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_4); + case 4: + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_5); + case 5: + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_6); + case 6: + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_7); + case 7: + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_8); + case 8: + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_9); + case 9: + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_10); + case 10: + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_11); + case 11: + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_12); + case 12: + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_13); + case 13: + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_14); + case 14: + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_15); + case 15: + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_16); + case 16: + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_17); + case 17: + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_18); + case 18: + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_19); + case 19: + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_20); + case 20: + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_21); + case 21: + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_22); + case 22: + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_23); + case 23: + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_24); + case 24: + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_25); + case 25: + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_26); + case 26: + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_27); + case 27: + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_28); + + default: + ASSERT (FALSE); + return 0xFF; + } +} + +/** + Get PCH PCIe controller PCIe Function Number + Note: + For Client PCH generations Function Number can be various + depending on "Root Port Function Swapping". For such cases + Function Number MUST be obtain from proper register. + For Server PCHs we have no "Root Port Function Swapping" + and we can return fixed Function Number. + To address this difference in this, PCH generation independent, + library we should call specific function in PchPcieRpLib. + + @param[in] RpIndex Root port physical number. (0-based) + + @retval PCH PCIe controller PCIe Function Number +**/ +UINT8 +PchPcieRpFuncNumber ( + IN UINTN RpIndex + ) +{ + UINTN Device; + UINTN Function; + + GetPchPcieRpDevFun (RpIndex, &Device, &Function); + + return (UINT8)Function; +} + diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Pch/Library/BaseResetSystemLib/BaseResetSystemLib.c b/Silicon/Intel/AlderlakeSiliconPkg/Pch/Library/BaseResetSystemLib/BaseResetSystemLib.c new file mode 100644 index 0000000000..86eeff9407 --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/Pch/Library/BaseResetSystemLib/BaseResetSystemLib.c @@ -0,0 +1,114 @@ +/** @file + System reset library services. + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#include +#include +#include +#include +#include +#include +#include +#include + +/** + Calling this function causes a system-wide reset. This sets + all circuitry within the system to its initial state. This type of reset + is asynchronous to system operation and operates without regard to + cycle boundaries. + + System reset should not return, if it returns, it means the system does + not support cold reset. +**/ +VOID +EFIAPI +ResetCold ( + VOID + ) +{ + IoWrite8 (R_PCH_IO_RST_CNT, V_PCH_IO_RST_CNT_FULLRESET); +} + +/** + Calling this function causes a system-wide initialization. The processors + are set to their initial state, and pending cycles are not corrupted. + + System reset should not return, if it returns, it means the system does + not support warm reset. +**/ +VOID +EFIAPI +ResetWarm ( + VOID + ) +{ + IoWrite8 (R_PCH_IO_RST_CNT, V_PCH_IO_RST_CNT_HARDRESET); +} + +/** + Calling this function causes the system to enter a power state equivalent + to the ACPI G2/S5 or G3 states. + + System shutdown should not return, if it returns, it means the system does + not support shut down reset. +**/ +VOID +EFIAPI +ResetShutdown ( + VOID + ) +{ + UINT16 ABase; + UINT32 Data32; + + ABase = PmcGetAcpiBase (); + + /// + /// Firstly, GPE0_EN should be disabled to avoid any GPI waking up the system from S5 + /// + IoWrite32 (ABase + R_ACPI_IO_GPE0_EN_127_96, 0); + + /// + /// Secondly, PwrSts register must be cleared + /// + /// Write a "1" to bit[8] of power button status register at + /// (PM_BASE + PM1_STS_OFFSET) to clear this bit + /// + IoWrite16 (ABase + R_ACPI_IO_PM1_STS, B_ACPI_IO_PM1_STS_PWRBTN); + + /// + /// Finally, transform system into S5 sleep state + /// + Data32 = IoRead32 (ABase + R_ACPI_IO_PM1_CNT); + + Data32 = (UINT32) ((Data32 &~(B_ACPI_IO_PM1_CNT_SLP_TYP + B_ACPI_IO_PM1_CNT_SLP_EN)) | V_ACPI_IO_PM1_CNT_S5); + + IoWrite32 (ABase + R_ACPI_IO_PM1_CNT, Data32); + + Data32 = Data32 | B_ACPI_IO_PM1_CNT_SLP_EN; + + IoWrite32 (ABase + R_ACPI_IO_PM1_CNT, Data32); + + return; +} + +/** + Calling this function causes the system to enter a power state for platform specific. + + @param[in] DataSize The size of ResetData in bytes. + @param[in] ResetData Optional element used to introduce a platform specific reset. + The exact type of the reset is defined by the EFI_GUID that follows + the Null-terminated Unicode string. + +**/ +VOID +EFIAPI +ResetPlatformSpecific ( + IN UINTN DataSize, + IN VOID *ResetData OPTIONAL + ) +{ + IoWrite8 (R_PCH_IO_RST_CNT, V_PCH_IO_RST_CNT_FULLRESET); +} diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Pch/Library/BaseResetSystemLib/BaseResetSystemLib.inf b/Silicon/Intel/AlderlakeSiliconPkg/Pch/Library/BaseResetSystemLib/BaseResetSystemLib.inf new file mode 100644 index 0000000000..f0a987d671 --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/Pch/Library/BaseResetSystemLib/BaseResetSystemLib.inf @@ -0,0 +1,37 @@ +## @file +# Component description file for Intel Ich7 Reset System Library. +# +# Copyright (c) 2022, Intel Corporation. All rights reserved.
+# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +[Defines] +INF_VERSION = 0x00010017 +BASE_NAME = BaseResetSystemLib +FILE_GUID = D4FF05AA-3C7D-4B8A-A1EE-AA5EFA0B1732 +VERSION_STRING = 1.0 +MODULE_TYPE = BASE +UEFI_SPECIFICATION_VERSION = 2.00 +LIBRARY_CLASS = ResetSystemLib + +# +# The following information is for reference only and not required by the build tools. +# +# VALID_ARCHITECTURES = IA32 X64 IPF +# + +[LibraryClasses] +IoLib +BaseLib +DebugLib +PmcLib + + +[Packages] +MdePkg/MdePkg.dec +AlderlakeSiliconPkg/SiPkg.dec + + +[Sources] +BaseResetSystemLib.c + diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Pch/Library/PeiDxeSmmPchCycleDecodingLib/PchCycleDecodingLib.c b/Silicon/Intel/AlderlakeSiliconPkg/Pch/Library/PeiDxeSmmPchCycleDecodingLib/PchCycleDecodingLib.c new file mode 100644 index 0000000000..ccdac7c5ab --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/Pch/Library/PeiDxeSmmPchCycleDecodingLib/PchCycleDecodingLib.c @@ -0,0 +1,194 @@ +/** @file + PCH cycle decoding configuration and query library. + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +typedef enum { + SlaveLpcEspiCS0, + SlaveEspiCS1, + SlaveId_Max +} SLAVE_ID_INDEX; + +/** + Get PCH TCO base address. + + @param[out] Address Address of TCO base address. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid pointer passed. +**/ +EFI_STATUS +PchTcoBaseGet ( + OUT UINT16 *Address + ) +{ + if (Address == NULL) { + DEBUG ((DEBUG_ERROR, "PchTcoBaseGet Error. Invalid pointer.\n")); + ASSERT (FALSE); + return EFI_INVALID_PARAMETER; + } + // + // Read "TCO Base Address" from DMI + // Don't read TCO base address from SMBUS PCI register since SMBUS might be disabled. + // + *Address = PchDmiGetTcoBase (); + + return EFI_SUCCESS; +} + +/** + Set PCH LPC/eSPI IO decode ranges. + Program LPC/eSPI I/O Decode Ranges in DMI to the same value programmed in LPC/eSPI PCI offset 80h. + Please check EDS for detail of LPC/eSPI IO decode ranges bit definition. + Bit 12: FDD range + Bit 9:8: LPT range + Bit 6:4: ComB range + Bit 2:0: ComA range + + @param[in] LpcIoDecodeRanges LPC/eSPI IO decode ranges bit settings. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_UNSUPPORTED DMIC.SRL is set. +**/ +EFI_STATUS +PchLpcIoDecodeRangesSet ( + IN UINT16 LpcIoDecodeRanges + ) +{ + UINT64 LpcBaseAddr; + EFI_STATUS Status; + + // + // Note: Inside this function, don't use debug print since it's could used before debug print ready. + // + + LpcBaseAddr = LpcPciCfgBase (); + + // + // check if setting is identical + // + if (LpcIoDecodeRanges == PciSegmentRead16 (LpcBaseAddr + R_LPC_CFG_IOD)) { + return EFI_SUCCESS; + } + + Status = PchDmiSetLpcIoDecodeRanges (LpcIoDecodeRanges); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return Status; + } + + // + // program LPC/eSPI PCI offset 80h. + // + PciSegmentWrite16 (LpcBaseAddr + R_LPC_CFG_IOD, LpcIoDecodeRanges); + + return Status; +} + +/** + Set PCH LPC/eSPI and eSPI CS1# IO enable decoding. + Setup I/O Enables in DMI to the same value program in LPC/eSPI PCI offset 82h (LPC, eSPI CS0#) or A0h (eSPI CS1#). + Note: Bit[15:10] of the source decode register is Read-Only. The IO range indicated by the Enables field + in LPC/eSPI PCI offset 82h[13:10] or A0h[13:10] is always forwarded by DMI to subtractive agent for handling. + Please check EDS for detail of Lpc/eSPI IO decode ranges bit definition. + + @param[in] IoEnableDecoding LPC/eSPI IO enable decoding bit settings. + @param[in] SlaveId Target ID (refer to SLAVE_ID_INDEX) + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_UNSUPPORTED DMI configuration is locked +**/ +EFI_STATUS +LpcEspiIoEnableDecodingSetHelper ( + IN UINT16 IoEnableDecoding, + IN SLAVE_ID_INDEX SlaveId + ) +{ + UINT64 LpcBaseAddr; + EFI_STATUS Status; + UINT16 Cs1IoEnableDecodingOrg; + UINT16 Cs0IoEnableDecodingOrg; + UINT16 IoEnableDecodingMerged; + + LpcBaseAddr = LpcPciCfgBase (); + + Cs0IoEnableDecodingOrg = PciSegmentRead16 (LpcBaseAddr + R_LPC_CFG_IOE); + + if (IsEspiSecondSlaveSupported ()) { + Cs1IoEnableDecodingOrg = PciSegmentRead16 (LpcBaseAddr + R_ESPI_CFG_CS1IORE); + } else { + Cs1IoEnableDecodingOrg = 0; + } + + if (SlaveId == SlaveEspiCS1) { + if (IoEnableDecoding == Cs1IoEnableDecodingOrg) { + return EFI_SUCCESS; + } else { + IoEnableDecodingMerged = (Cs0IoEnableDecodingOrg | IoEnableDecoding); + } + } else { + if ((IoEnableDecoding | Cs1IoEnableDecodingOrg) == Cs0IoEnableDecodingOrg) { + return EFI_SUCCESS; + } else { + IoEnableDecodingMerged = (Cs1IoEnableDecodingOrg | IoEnableDecoding); + } + } + + Status = PchDmiSetLpcIoEnable (IoEnableDecodingMerged); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return Status; + } + + // + // program PCI offset 82h for LPC/eSPI. + // + PciSegmentWrite16 (LpcBaseAddr + R_LPC_CFG_IOE, IoEnableDecodingMerged); + + if (SlaveId == SlaveEspiCS1) { + // + // For eSPI CS1# device program eSPI PCI offset A0h. + // + PciSegmentWrite16 (LpcBaseAddr + R_ESPI_CFG_CS1IORE, IoEnableDecoding); + } + + return Status; +} + +/** + Set PCH LPC and eSPI CS0# IO enable decoding. + Setup I/O Enables in DMI to the same value program in LPC/eSPI PCI offset 82h. + Note: Bit[15:10] of the source decode register is Read-Only. The IO range indicated by the Enables field + in LPC/eSPI PCI offset 82h[13:10] is always forwarded by DMI to subtractive agent for handling. + Please check EDS for detail of LPC/eSPI IO decode ranges bit definition. + + @param[in] LpcIoEnableDecoding LPC IO enable decoding bit settings. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_UNSUPPORTED DMIC.SRL is set. +**/ +EFI_STATUS +PchLpcIoEnableDecodingSet ( + IN UINT16 LpcIoEnableDecoding + ) +{ + return LpcEspiIoEnableDecodingSetHelper (LpcIoEnableDecoding, SlaveLpcEspiCS0); +} diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Pch/Library/PeiDxeSmmPchCycleDecodingLib/PeiDxeSmmPchCycleDecodingLib.inf b/Silicon/Intel/AlderlakeSiliconPkg/Pch/Library/PeiDxeSmmPchCycleDecodingLib/PeiDxeSmmPchCycleDecodingLib.inf new file mode 100644 index 0000000000..a381c0f0f7 --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/Pch/Library/PeiDxeSmmPchCycleDecodingLib/PeiDxeSmmPchCycleDecodingLib.inf @@ -0,0 +1,41 @@ +## @file +# PCH cycle decoding Lib. +# +# All function in this library is available for PEI, DXE, and SMM, +# But do not support UEFI RUNTIME environment call. +# +# Copyright (c) 2022, Intel Corporation. All rights reserved.
+# SPDX-License-Identifier: BSD-2-Clause-Patent +## + + +[Defines] +INF_VERSION = 0x00010017 +BASE_NAME = PeiDxeSmmPchCycleDecodingLib +FILE_GUID = 676C749F-9CD1-46B7-BAFD-4B1BC36B4C8E +VERSION_STRING = 1.0 +MODULE_TYPE = BASE +LIBRARY_CLASS = PchCycleDecodingLib + + +[LibraryClasses] +BaseLib +IoLib +DebugLib +PciSegmentLib +PchInfoLib +PchPcrLib +PchDmiLib +EspiLib +PchPciBdfLib + +[Packages] +MdePkg/MdePkg.dec +AlderlakeSiliconPkg/SiPkg.dec + +[Sources] +PchCycleDecodingLib.c + +[Pcd] +gSiPkgTokenSpaceGuid.PcdSiHpetBaseAddress ## CONSUMES +gSiPkgTokenSpaceGuid.PcdSiIoApicBaseAddress ## CONSUMES -- 2.36.1.windows.1