public inbox for devel@edk2.groups.io
 help / color / mirror / Atom feed
From: "Saloni Kasbekar" <saloni.kasbekar@intel.com>
To: devel@edk2.groups.io
Cc: Saloni Kasbekar <saloni.kasbekar@intel.com>,
	Sai Chaganty <rangasai.v.chaganty@intel.com>,
	Nate DeSimone <nathaniel.l.desimone@intel.com>,
	Isaac Oram <isaac.w.oram@intel.com>,
	Rosen Chuang <rosen.chuang@intel.com>
Subject: [PATCH 5/6] AlderlakeOpenBoardPkg: Adds the Policy Module
Date: Wed, 14 Jun 2023 12:17:27 -0700	[thread overview]
Message-ID: <f4096ae9848aced854fc8b206976e9f8f7506ee4.1686770061.git.saloni.kasbekar@intel.com> (raw)
In-Reply-To: <cover.1686770061.git.saloni.kasbekar@intel.com>

Adds the following libraries within the Policy module
- DxeSiliconPolicyUpdateLib
- PeiPolicyBoardConfigLib
- PeiPolicyUpdateLib
- PeiSiliconPolicyUpdateLib

Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Isaac Oram <isaac.w.oram@intel.com>
Cc: Rosen Chuang <rosen.chuang@intel.com>
Signed-off-by: Saloni Kasbekar <saloni.kasbekar@intel.com>
---
 .../DxeCpuPolicyInit.c                        | 147 +++++
 .../DxeSaPolicyInit.c                         |  64 +++
 .../DxeSiliconPolicyInit.c                    |  49 ++
 .../DxeSiliconPolicyUpdateLate.c              | 122 +++++
 .../DxeSiliconPolicyUpdateLib.inf             |  61 +++
 .../PeiCpuPolicyBoardConfigPreMem.c           |  59 ++
 .../PeiMePolicyBoardConfig.c                  |  39 ++
 .../PeiMePolicyBoardConfigPreMem.c            |  39 ++
 .../PeiPchPolicyBoardConfigPreMem.c           |  42 ++
 .../PeiPolicyBoardConfig.h                    |  29 +
 .../PeiPolicyBoardConfigLib.inf               |  72 +++
 .../PeiPolicyBoardConfigLibFsp.inf            |  67 +++
 .../PeiSaPolicyBoardConfig.c                  |  47 ++
 .../PeiSaPolicyBoardConfigPreMem.c            |  48 ++
 .../PeiSiPolicyBoardConfig.c                  |  23 +
 .../PeiPolicyUpdateLib/PeiCpuPolicyUpdate.c   | 344 ++++++++++++
 .../PeiPolicyUpdateLib/PeiCpuPolicyUpdate.h   |  31 ++
 .../PeiCpuPolicyUpdatePreMem.c                | 120 +++++
 .../PeiPolicyUpdateLib/PeiMePolicyUpdate.c    |  65 +++
 .../PeiMePolicyUpdatePreMem.c                 |  60 +++
 .../PeiPolicyUpdateLib/PeiPchPolicyUpdate.c   | 267 ++++++++++
 .../PeiPolicyUpdateLib/PeiPchPolicyUpdate.h   |  34 ++
 .../PeiPchPolicyUpdatePreMem.c                | 173 ++++++
 .../PeiPolicyUpdateLib/PeiPolicyUpdateLib.inf | 225 ++++++++
 .../PeiPolicyUpdateLib/PeiSaPolicyUpdate.c    | 293 ++++++++++
 .../PeiPolicyUpdateLib/PeiSaPolicyUpdate.h    |  47 ++
 .../PeiSaPolicyUpdatePreMem.c                 | 502 ++++++++++++++++++
 .../PeiPolicyUpdateLib/PeiSiPolicyUpdate.c    | 114 ++++
 .../PeiPolicyUpdateLib/PeiSiPolicyUpdate.h    |  17 +
 .../PeiSiliconPolicyUpdateLib/PeiCpuPolicy.h  |  22 +
 .../PeiSiliconPolicyUpdateLib/PeiMePolicy.h   |  21 +
 .../PeiSiliconPolicyUpdateLib/PeiPolicy.h     |  21 +
 .../PeiSiliconPolicyUpdateLib/PeiSaPolicy.h   |  22 +
 .../PeiSiliconPolicyUpdateLib/PeiSiPolicy.h   |  21 +
 .../PeiSiliconPolicyUpdateLate.c              |  18 +
 .../PeiSiliconPolicyUpdateLib.inf             |  67 +++
 .../PeiSiliconPolicyUpdatePostMem.c           |  53 ++
 .../PeiSiliconPolicyUpdatePreMem.c            |  49 ++
 38 files changed, 3494 insertions(+)
 create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdateLib/DxeCpuPolicyInit.c
 create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSaPolicyInit.c
 create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSiliconPolicyInit.c
 create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSiliconPolicyUpdateLate.c
 create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSiliconPolicyUpdateLib.inf
 create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyBoardConfigLib/PeiCpuPolicyBoardConfigPreMem.c
 create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyBoardConfigLib/PeiMePolicyBoardConfig.c
 create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyBoardConfigLib/PeiMePolicyBoardConfigPreMem.c
 create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyBoardConfigLib/PeiPchPolicyBoardConfigPreMem.c
 create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyBoardConfigLib/PeiPolicyBoardConfig.h
 create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyBoardConfigLib/PeiPolicyBoardConfigLib.inf
 create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyBoardConfigLib/PeiPolicyBoardConfigLibFsp.inf
 create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyBoardConfigLib/PeiSaPolicyBoardConfig.c
 create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyBoardConfigLib/PeiSaPolicyBoardConfigPreMem.c
 create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyBoardConfigLib/PeiSiPolicyBoardConfig.c
 create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiCpuPolicyUpdate.c
 create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiCpuPolicyUpdate.h
 create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiCpuPolicyUpdatePreMem.c
 create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiMePolicyUpdate.c
 create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiMePolicyUpdatePreMem.c
 create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiPchPolicyUpdate.c
 create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiPchPolicyUpdate.h
 create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiPchPolicyUpdatePreMem.c
 create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiPolicyUpdateLib.inf
 create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiSaPolicyUpdate.c
 create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiSaPolicyUpdate.h
 create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiSaPolicyUpdatePreMem.c
 create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiSiPolicyUpdate.c
 create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiSiPolicyUpdate.h
 create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiSiliconPolicyUpdateLib/PeiCpuPolicy.h
 create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiSiliconPolicyUpdateLib/PeiMePolicy.h
 create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiSiliconPolicyUpdateLib/PeiPolicy.h
 create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSaPolicy.h
 create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiPolicy.h
 create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLate.c
 create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf
 create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdatePostMem.c
 create mode 100644 Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdatePreMem.c

diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdateLib/DxeCpuPolicyInit.c b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdateLib/DxeCpuPolicyInit.c
new file mode 100644
index 0000000000..25b401057d
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdateLib/DxeCpuPolicyInit.c
@@ -0,0 +1,147 @@
+/** @file
+  This file is SampleCode for Intel Silicon DXE Platform Policy initialzation.
+
+   Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+   SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+#include <PiDxe.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/UefiRuntimeServicesTableLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Protocol/CpuPolicyProtocol.h>
+#include <Library/PcdLib.h>
+
+DXE_CPU_POLICY_PROTOCOL mCpuPolicyData;
+
+/**
+  This function prints the CPU DXE phase policy.
+
+  @param[in] DxeCpuPolicy - CPU DXE Policy protocol
+**/
+VOID
+CpuDxePrintPolicyProtocol (
+  IN  DXE_CPU_POLICY_PROTOCOL  *DxeCpuPolicy
+  )
+{
+  DEBUG_CODE_BEGIN ();
+  DEBUG ((DEBUG_INFO, "\n------------------------ CPU Policy (DXE) print BEGIN -----------------\n"));
+  DEBUG ((DEBUG_INFO, "Revision : %x\n", DxeCpuPolicy->Revision));
+  ASSERT (DxeCpuPolicy->Revision == DXE_CPU_POLICY_PROTOCOL_REVISION);
+  DEBUG ((DEBUG_INFO, "DgrEnable : %x\n", DxeCpuPolicy->DgrEnable));
+  DEBUG ((DEBUG_INFO, "DgrStateSaveProtect : %x\n", DxeCpuPolicy->DgrStateSaveProtect));
+  DEBUG ((DEBUG_INFO, "DgrSpaEnable : %x\n", DxeCpuPolicy->DgrSpaEnable));
+  DEBUG ((DEBUG_INFO, "SmmMsrSaveStateEnable : %x\n", DxeCpuPolicy->SmmMsrSaveStateEnable));
+  DEBUG ((DEBUG_INFO, "SmmUseDelayIndication : %x\n", DxeCpuPolicy->SmmUseDelayIndication));
+  DEBUG ((DEBUG_INFO, "SmmUseBlockIndication : %x\n", DxeCpuPolicy->SmmUseBlockIndication));
+  DEBUG ((DEBUG_INFO, "SmmUseSmmEnableIndication : %x\n", DxeCpuPolicy->SmmUseSmmEnableIndication));
+  DEBUG ((DEBUG_INFO, "SmmProcTraceEnable : %x\n", DxeCpuPolicy->SmmProcTraceEnable));
+  DEBUG ((DEBUG_INFO, "\n------------------------ CPU Policy (DXE) print END -----------------\n"));
+  DEBUG_CODE_END ();
+}
+
+/**
+  Get data for CPU policy from setup options.
+
+  @param[in] DxeCpuPolicy              The pointer to get CPU Policy protocol instance
+
+  @retval EFI_SUCCESS                  Operation success.
+
+**/
+EFI_STATUS
+EFIAPI
+UpdateDxeSiCpuPolicy (
+  IN OUT  DXE_CPU_POLICY_PROTOCOL  *DxeCpuPolicy
+  )
+{
+
+#if FixedPcdGetBool (PcdPpamEnable) == 1
+  DxeCpuPolicy->DgrEnable = 1;
+#endif
+#if FixedPcdGetBool (PcdSpsStateSaveEnable) == 1
+  DxeCpuPolicy->DgrStateSaveProtect = 1;
+#endif
+  DxeCpuPolicy->SmmUseDelayIndication = 1;
+  DxeCpuPolicy->SmmUseBlockIndication = 1;
+  DxeCpuPolicy->SmmUseSmmEnableIndication = 1;
+
+  return EFI_SUCCESS;
+}
+
+/**
+  CpuInstallPolicyProtocol installs CPU Policy.
+  While installed, RC assumes the Policy is ready and finalized. So please update and override
+  any setting before calling this function.
+
+  @param[in] ImageHandle                Image handle of this driver.
+  @param[in] DxeCpuPolicy               The pointer to CPU Policy Protocol instance
+
+  @retval EFI_SUCCESS                   The policy is installed.
+  @retval EFI_OUT_OF_RESOURCES          Insufficient resources to create buffer
+
+**/
+EFI_STATUS
+EFIAPI
+CpuInstallPolicyProtocol (
+  IN  EFI_HANDLE                  ImageHandle,
+  IN  DXE_CPU_POLICY_PROTOCOL     *DxeCpuPolicy
+  )
+{
+  EFI_STATUS            Status;
+
+  ///
+  /// Print CPU DXE Policy
+  ///
+  CpuDxePrintPolicyProtocol (DxeCpuPolicy);
+
+  ///
+  /// Install the DXE_CPU_POLICY_PROTOCOL interface
+  ///
+  Status = gBS->InstallMultipleProtocolInterfaces (
+                  &ImageHandle,
+                  &gDxeCpuPolicyProtocolGuid,
+                  DxeCpuPolicy,
+                  NULL
+                  );
+  ASSERT_EFI_ERROR (Status);
+
+  return Status;
+}
+
+
+/**
+  Initilize Intel CPU DXE Platform Policy
+
+  @param[in] ImageHandle        Image handle of this driver.
+
+  @retval EFI_SUCCESS           Initialization complete.
+  @exception EFI_UNSUPPORTED    The chipset is unsupported by this driver.
+  @retval EFI_OUT_OF_RESOURCES  Do not have enough resources to initialize the driver.
+  @retval EFI_DEVICE_ERROR      Device error, driver exits abnormally.
+**/
+EFI_STATUS
+EFIAPI
+CpuPolicyInitDxe (
+  IN EFI_HANDLE       ImageHandle
+  )
+{
+  EFI_STATUS                Status;
+
+  ZeroMem (&mCpuPolicyData, sizeof (DXE_CPU_POLICY_PROTOCOL));
+  mCpuPolicyData.Revision = DXE_CPU_POLICY_PROTOCOL_REVISION;
+
+  //UpdateDxeSiCpuPolicy (&mCpuPolicyData);
+
+  //
+  // Install CpuInstallPolicyProtocol.
+  // While installed, RC assumes the Policy is ready and finalized. So please
+  // update and override any setting before calling this function.
+  //
+  Status = CpuInstallPolicyProtocol (ImageHandle, &mCpuPolicyData);
+  ASSERT_EFI_ERROR (Status);
+
+  return Status;
+}
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSaPolicyInit.c b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSaPolicyInit.c
new file mode 100644
index 0000000000..da2f568e07
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSaPolicyInit.c
@@ -0,0 +1,64 @@
+/** @file
+  This file initialises and Installs GopPolicy Protocol.
+
+   Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+   SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Uefi.h>
+#include <Library/DebugLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/GraphicsInfoLib.h>
+#include <Protocol/SaPolicy.h>
+
+EFI_STATUS
+EFIAPI
+CreateSaDxeConfigBlocks (
+  IN OUT  VOID      **SaPolicy
+  );
+
+EFI_STATUS
+EFIAPI
+SaInstallPolicyProtocol (
+  IN  EFI_HANDLE                  ImageHandle,
+  IN  VOID                        *SaPolicy
+  );
+
+/**
+  Initialize SA DXE Policy
+
+  @param[in] ImageHandle          Image handle of this driver.
+
+  @retval EFI_SUCCESS             Initialization complete.
+  @retval EFI_UNSUPPORTED         The chipset is unsupported by this driver.
+  @retval EFI_OUT_OF_RESOURCES    Do not have enough resources to initialize the driver.
+  @retval EFI_DEVICE_ERROR        Device error, driver exits abnormally.
+**/
+EFI_STATUS
+EFIAPI
+SaPolicyInitDxe (
+  IN EFI_HANDLE           ImageHandle
+  )
+{
+  EFI_STATUS               Status;
+  SA_POLICY_PROTOCOL       *SaPolicy;
+
+  //
+  // Call CreateSaDxeConfigBlocks to create & initialize platform policy structure
+  // and get all Intel default policy settings.
+  //
+  Status = CreateSaDxeConfigBlocks (&SaPolicy);
+  DEBUG ((DEBUG_INFO, "SaPolicy->TableHeader.NumberOfBlocks = 0x%x\n ", SaPolicy->TableHeader.NumberOfBlocks));
+  ASSERT_EFI_ERROR (Status);
+
+  //
+  // Install SaInstallPolicyProtocol.
+  // While installed, RC assumes the Policy is ready and finalized. So please
+  // update and override any setting before calling this function.
+  //
+  Status = SaInstallPolicyProtocol (ImageHandle, SaPolicy);
+  ASSERT_EFI_ERROR (Status);
+
+  return EFI_SUCCESS;
+}
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSiliconPolicyInit.c b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSiliconPolicyInit.c
new file mode 100644
index 0000000000..00c90d438b
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSiliconPolicyInit.c
@@ -0,0 +1,49 @@
+/** @file
+  This file is SampleCode for Intel Silicon DXE Platform Policy initialzation.
+
+   Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+   SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+#include <Protocol/FirmwareVolume2.h>
+#include <Guid/StatusCodeDataTypeId.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/DebugLib.h>
+#include <Protocol/SiPolicyProtocol.h>
+#include <Library/BaseLib.h>
+
+DXE_SI_POLICY_PROTOCOL mSiPolicyData  = { 0 };
+
+/**
+  Initilize Intel Cpu DXE Platform Policy
+
+  @param[in] ImageHandle        Image handle of this driver.
+
+  @retval EFI_SUCCESS           Initialization complete.
+  @exception EFI_UNSUPPORTED    The chipset is unsupported by this driver.
+  @retval EFI_OUT_OF_RESOURCES  Do not have enough resources to initialize the driver.
+  @retval EFI_DEVICE_ERROR      Device error, driver exits abnormally.
+**/
+EFI_STATUS
+EFIAPI
+SiliconPolicyInitDxe (
+  IN EFI_HANDLE       ImageHandle
+  )
+{
+  EFI_STATUS Status;
+
+  mSiPolicyData.Revision                         = DXE_SI_POLICY_PROTOCOL_REVISION;
+  mSiPolicyData.SmbiosOemTypeFirmwareVersionInfo = (UINT8) PcdGet8 (PcdSmbiosOemTypeFirmwareVersionInfo);
+  ///
+  /// Install the DXE_SI_POLICY_PROTOCOL interface
+  ///
+  Status = gBS->InstallMultipleProtocolInterfaces (
+                  &ImageHandle,
+                  &gDxeSiPolicyProtocolGuid,
+                  &mSiPolicyData,
+                  NULL
+                  );
+  ASSERT_EFI_ERROR (Status);
+  return Status;
+}
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSiliconPolicyUpdateLate.c b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSiliconPolicyUpdateLate.c
new file mode 100644
index 0000000000..67171b09b7
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSiliconPolicyUpdateLate.c
@@ -0,0 +1,122 @@
+/** @file
+
+   Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+   SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <PiDxe.h>
+#include <Library/PcdLib.h>
+#include <Library/DebugLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+
+/**
+  Initialize SA DXE Policy
+
+  @param[in] ImageHandle          Image handle of this driver.
+
+  @retval EFI_SUCCESS             Initialization complete.
+  @retval EFI_UNSUPPORTED         The chipset is unsupported by this driver.
+  @retval EFI_OUT_OF_RESOURCES    Do not have enough resources to initialize the driver.
+  @retval EFI_DEVICE_ERROR        Device error, driver exits abnormally.
+**/
+EFI_STATUS
+EFIAPI
+SaPolicyInitDxe (
+  IN EFI_HANDLE           ImageHandle
+  );
+
+/**
+  Initilize Intel Silicon DXE Platform Policy
+
+  @param[in] ImageHandle        Image handle of this driver.
+
+  @retval EFI_SUCCESS           Initialization complete.
+  @exception EFI_UNSUPPORTED    The chipset is unsupported by this driver.
+  @retval EFI_OUT_OF_RESOURCES  Do not have enough resources to initialize the driver.
+  @retval EFI_DEVICE_ERROR      Device error, driver exits abnormally.
+**/
+EFI_STATUS
+EFIAPI
+SiliconPolicyInitDxe (
+  IN EFI_HANDLE       ImageHandle
+  );
+
+/**
+  Initialize CPU DXE Policy
+
+  @param[in] ImageHandle - Image handle of this driver.
+
+  @retval EFI_SUCCESS           Initialization complete.
+  @retval EFI_OUT_OF_RESOURCES  Do not have enough resources to initialize the driver.
+  @retval EFI_DEVICE_ERROR      Device error, driver exits abnormally.
+**/
+EFI_STATUS
+EFIAPI
+CpuPolicyInitDxe (
+  IN EFI_HANDLE           ImageHandle
+  );
+
+/**
+  Initialize GOP DXE Policy
+
+  @param[in] ImageHandle - Image handle of this driver.
+
+  @retval EFI_SUCCESS           Initialization complete.
+  @retval EFI_OUT_OF_RESOURCES  Do not have enough resources to initialize the driver.
+  @retval EFI_DEVICE_ERROR      Device error, driver exits abnormally.
+**/
+EFI_STATUS
+EFIAPI
+GopPolicyInitDxe (
+  IN EFI_HANDLE           ImageHandle
+  );
+
+/**
+  Performs silicon late policy update.
+
+  The meaning of Policy is defined by silicon code.
+  It could be the raw data, a handle, a Protocol, etc.
+
+  The input Policy must be returned by SiliconPolicyDoneLate().
+
+  In FSP or non-FSP path, the board may use additional way to get
+  the silicon policy data field based upon the input Policy.
+
+  @param[in, out] Policy       Pointer to policy.
+
+  @return the updated policy.
+**/
+VOID *
+EFIAPI
+SiliconPolicyUpdateLate (
+  IN OUT VOID *Policy
+  )
+{
+  EFI_STATUS           Status;
+
+  Status = EFI_SUCCESS;
+
+  //
+  // SystemAgent Dxe Platform Policy Initialization
+  //
+  Status = SaPolicyInitDxe (gImageHandle);
+  DEBUG ((DEBUG_INFO, "SystemAgent Dxe Platform Policy Initialization status: %r\n", Status));
+  ASSERT_EFI_ERROR (Status);
+
+  //
+  // Silicon Dxe Platform Policy Initialization
+  //
+  Status = SiliconPolicyInitDxe (gImageHandle);
+  DEBUG ((DEBUG_INFO, "Silicon Dxe Platform Policy Initialization status: %r\n", Status));
+  ASSERT_EFI_ERROR (Status);
+
+  //
+  // CPU DXE Platform Policy Initialization
+  //
+  Status = CpuPolicyInitDxe (gImageHandle);
+  DEBUG ((DEBUG_INFO, "Cpu Dxe Platform Policy Initialization status: %r\n", Status));
+  ASSERT_EFI_ERROR (Status);
+
+  return EFI_SUCCESS;
+}
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSiliconPolicyUpdateLib.inf b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSiliconPolicyUpdateLib.inf
new file mode 100644
index 0000000000..6cd1923792
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSiliconPolicyUpdateLib.inf
@@ -0,0 +1,61 @@
+## @file
+# Component information file for Silicon Policy Update Library
+#
+#   Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+#   SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+###
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = DxeSiliconUpdateLib
+  FILE_GUID                      = C523609D-E354-416B-B24F-33468D4BD21D
+  MODULE_TYPE                    = DXE_DRIVER
+  VERSION_STRING                 = 1.0
+  LIBRARY_CLASS                  = SiliconPolicyUpdateLib
+
+[LibraryClasses]
+  BaseLib
+  BaseMemoryLib
+  PcdLib
+  DebugLib
+  UefiBootServicesTableLib
+  MemoryAllocationLib
+  DxeSaPolicyLib
+  UefiLib
+  ConfigBlockLib
+  GraphicsInfoLib
+
+[Packages]
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  AlderlakeSiliconPkg/SiPkg.dec
+  MinPlatformPkg/MinPlatformPkg.dec
+  IntelSiliconPkg/IntelSiliconPkg.dec
+  AlderlakeOpenBoardPkg/OpenBoardPkg.dec
+
+[Sources]
+  DxeSiliconPolicyUpdateLate.c
+  DxeSaPolicyInit.c
+  DxeSiliconPolicyInit.c
+  DxeCpuPolicyInit.c
+  
+[Pcd]
+  gBoardModuleTokenSpaceGuid.PcdIntelGopEnable
+  gBoardModuleTokenSpaceGuid.PcdGraphicsVbtGuid
+  gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange
+  gBoardModuleTokenSpaceGuid.PcdVbtMipiGuid
+  gIntelSiliconPkgTokenSpaceGuid.PcdIntelGraphicsVbtFileGuid
+  gPlatformModuleTokenSpaceGuid.PcdSmbiosOemTypeFirmwareVersionInfo     ## CONSUMES
+  gSiPkgTokenSpaceGuid.PcdPpamEnable                 ## CONSUMES
+  gSiPkgTokenSpaceGuid.PcdSpsStateSaveEnable         ## CONSUMES
+  
+[Protocols]
+  gEfiFirmwareVolume2ProtocolGuid               ## CONSUMES
+  gSaPolicyProtocolGuid                         ## CONSUMES
+  gDxeSiPolicyProtocolGuid                      ## PRODUCES
+  gGopPolicyProtocolGuid                        ## PRODUCES
+  gDxeCpuPolicyProtocolGuid                     ## PRODUCES
+
+[Depex]
+  gEfiVariableArchProtocolGuid
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyBoardConfigLib/PeiCpuPolicyBoardConfigPreMem.c b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyBoardConfigLib/PeiCpuPolicyBoardConfigPreMem.c
new file mode 100644
index 0000000000..6051baa483
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyBoardConfigLib/PeiCpuPolicyBoardConfigPreMem.c
@@ -0,0 +1,59 @@
+/** @file
+ Intel PEI CPU Pre-Memory Policy update by board configuration
+
+   Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+   SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+#include "PeiPolicyBoardConfig.h"
+#include <Register/Cpuid.h>
+#include <PolicyUpdateMacro.h>
+
+#define GET_OCCUPIED_SIZE(ActualSize, Alignment) \
+  ((ActualSize) + (((Alignment) - ((ActualSize) & ((Alignment) - 1))) & ((Alignment) - 1)))
+
+/**
+  This function performs PEI CPU Pre-Memory Policy update by board configuration.
+
+  @retval EFI_SUCCESS             The SI Policy is successfully updated.
+  @retval Others                  The SI Policy is not successfully updated.
+**/
+EFI_STATUS
+EFIAPI
+UpdatePeiCpuPolicyBoardConfigPreMem (
+  VOID
+  )
+{
+  EFI_STATUS                      Status;
+  CPUID_VERSION_INFO_ECX          Ecx;
+#if FixedPcdGet8(PcdFspModeSelection) == 1
+  VOID                            *FspmUpd;
+#else
+  SI_PREMEM_POLICY_PPI            *SiPreMemPolicyPpi;
+  CPU_SECURITY_PREMEM_CONFIG      *CpuSecurityPreMemConfig;
+#endif
+
+  DEBUG ((DEBUG_INFO, "Updating CPU Policy by board config in Pre-Mem\n"));
+
+#if FixedPcdGet8(PcdFspModeSelection) == 1
+  FspmUpd = NULL;
+#else
+  SiPreMemPolicyPpi       = NULL;
+  CpuSecurityPreMemConfig = NULL;
+#endif
+
+#if FixedPcdGet8(PcdFspModeSelection) == 1
+  FspmUpd = (FSPM_UPD *) PcdGet32 (PcdFspmUpdDataAddress);
+  ASSERT (FspmUpd != NULL);
+#else
+  Status = PeiServicesLocatePpi (&gSiPreMemPolicyPpiGuid, 0, NULL, (VOID **) &SiPreMemPolicyPpi);
+  ASSERT_EFI_ERROR (Status);
+
+
+  Status = GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gCpuSecurityPreMemConfigGuid, (VOID *) &CpuSecurityPreMemConfig);
+  ASSERT_EFI_ERROR(Status);
+#endif
+  AsmCpuid (CPUID_VERSION_INFO, NULL, NULL, &Ecx.Uint32, NULL);
+
+  return EFI_SUCCESS;
+}
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyBoardConfigLib/PeiMePolicyBoardConfig.c b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyBoardConfigLib/PeiMePolicyBoardConfig.c
new file mode 100644
index 0000000000..7611a0d9c5
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyBoardConfigLib/PeiMePolicyBoardConfig.c
@@ -0,0 +1,39 @@
+/** @file
+ Intel PEI ME Policy update by board configuration
+
+   Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+   SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+#include "PeiPolicyBoardConfig.h"
+
+/**
+  This function performs PEI ME Policy update by board configuration.
+
+  @retval EFI_SUCCESS             The SI Policy is successfully updated.
+  @retval Others                  The SI Policy is not successfully updated.
+**/
+EFI_STATUS
+EFIAPI
+UpdatePeiMePolicyBoardConfig (
+  VOID
+  )
+{
+#if FixedPcdGet8(PcdFspModeSelection) == 0
+  EFI_STATUS                         Status;
+  SI_POLICY_PPI                      *SiPolicyPpi;
+
+  DEBUG ((DEBUG_INFO, "Updating ME Policy by board config in Post-Mem\n"));
+
+  Status = EFI_SUCCESS;
+  SiPolicyPpi = NULL;
+
+  Status = PeiServicesLocatePpi (&gSiPolicyPpiGuid, 0, NULL, (VOID **) &SiPolicyPpi);
+  ASSERT_EFI_ERROR (Status);
+
+  return Status;
+#else
+  return EFI_SUCCESS;
+#endif
+
+}
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyBoardConfigLib/PeiMePolicyBoardConfigPreMem.c b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyBoardConfigLib/PeiMePolicyBoardConfigPreMem.c
new file mode 100644
index 0000000000..c6e8dbdb2b
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyBoardConfigLib/PeiMePolicyBoardConfigPreMem.c
@@ -0,0 +1,39 @@
+/** @file
+ Intel PEI ME Pre-Memory Policy update by board configuration
+
+   Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+   SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+#include "PeiPolicyBoardConfig.h"
+
+/**
+  This function performs PEI ME Pre-Memory Policy update by board configuration.
+
+  @retval EFI_SUCCESS             The SI Policy is successfully updated.
+  @retval Others                  The SI Policy is not successfully updated.
+**/
+EFI_STATUS
+EFIAPI
+UpdatePeiMePolicyBoardConfigPreMem (
+  VOID
+  )
+{
+  EFI_STATUS                         Status;
+#if FixedPcdGet8(PcdFspModeSelection) == 0
+  SI_PREMEM_POLICY_PPI               *SiPreMemPolicyPpi;
+#endif
+
+  DEBUG ((DEBUG_INFO, "Updating ME Policy by board config in Pre-Mem\n"));
+
+  Status = EFI_SUCCESS;
+
+#if FixedPcdGet8(PcdFspModeSelection) == 0
+  Status = PeiServicesLocatePpi (&gSiPreMemPolicyPpiGuid, 0, NULL, (VOID **) &SiPreMemPolicyPpi);
+  ASSERT_EFI_ERROR (Status);
+
+#endif
+
+  return Status;
+}
+
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyBoardConfigLib/PeiPchPolicyBoardConfigPreMem.c b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyBoardConfigLib/PeiPchPolicyBoardConfigPreMem.c
new file mode 100644
index 0000000000..d17a75dce8
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyBoardConfigLib/PeiPchPolicyBoardConfigPreMem.c
@@ -0,0 +1,42 @@
+/** @file
+ Intel PEI PCH Pre-Memory Policy update by board configuration
+
+   Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+   SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+#include "PeiPolicyBoardConfig.h"
+
+/**
+  This function performs PEI PCH Pre-Memory Policy update by board configuration.
+
+  @retval EFI_SUCCESS             The SI Policy is successfully updated.
+  @retval Others                  The SI Policy is not successfully updated.
+**/
+EFI_STATUS
+EFIAPI
+UpdatePeiPchPolicyBoardConfigPreMem (
+  VOID
+  )
+{
+  EFI_STATUS                         Status;
+#if FixedPcdGet8(PcdFspModeSelection) == 0
+  SI_PREMEM_POLICY_PPI               *SiPreMemPolicyPpi;
+  PCH_GENERAL_PREMEM_CONFIG          *PchGeneralPreMemConfig;
+#endif
+
+  DEBUG ((DEBUG_INFO, "Updating PCH Policy by board config in Pre-Mem\n"));
+
+  Status = EFI_SUCCESS;
+
+#if FixedPcdGet8(PcdFspModeSelection) == 0
+  Status = PeiServicesLocatePpi (&gSiPreMemPolicyPpiGuid, 0, NULL, (VOID **) &SiPreMemPolicyPpi);
+  ASSERT_EFI_ERROR (Status);
+
+  Status = GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gPchGeneralPreMemConfigGuid, (VOID *) &PchGeneralPreMemConfig);
+  ASSERT_EFI_ERROR (Status);
+#endif
+
+  return Status;
+}
+
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyBoardConfigLib/PeiPolicyBoardConfig.h b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyBoardConfigLib/PeiPolicyBoardConfig.h
new file mode 100644
index 0000000000..6771f27a6d
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyBoardConfigLib/PeiPolicyBoardConfig.h
@@ -0,0 +1,29 @@
+/** @file
+ Header file for PeiPolicyBoardConfig library instance.
+
+   Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+   SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+#ifndef _PEI_POLICY_BOARD_CONFIG_H_
+#define _PEI_POLICY_BOARD_CONFIG_H_
+
+#include <PiPei.h>
+#include <Library/PeiServicesLib.h>
+#include <Library/DebugLib.h>
+#include <Library/HobLib.h>
+#include <Library/ConfigBlockLib.h>
+#include <Library/PeiPolicyBoardConfigLib.h>
+#include <Library/IoLib.h>
+#include <Ppi/ReadOnlyVariable2.h>
+#include <Library/BaseCryptLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Ppi/SiPolicy.h>
+#include <Library/SiPolicyLib.h>
+#if FixedPcdGet8(PcdFspModeSelection) == 1
+#include <FspmUpd.h>
+#include <FspsUpd.h>
+#include <Library/FspCommonLib.h>
+#endif
+
+#endif
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyBoardConfigLib/PeiPolicyBoardConfigLib.inf b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyBoardConfigLib/PeiPolicyBoardConfigLib.inf
new file mode 100644
index 0000000000..d1bfd07ab6
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyBoardConfigLib/PeiPolicyBoardConfigLib.inf
@@ -0,0 +1,72 @@
+### @file
+# Module Information file for PeiPolicyBoardConfigLib Library
+#
+#   Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+#   SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+###
+
+[Defines]
+  INF_VERSION                    = 0x00010017
+  BASE_NAME                      = PeiPolicyBoardConfigLib
+  FILE_GUID                      = B1E959E3-9DCA-4D6F-938C-420C3BF5D820
+  VERSION_STRING                 = 1.0
+  MODULE_TYPE                    = PEIM
+  LIBRARY_CLASS                  = PeiPolicyBoardConfigLib|PEIM PEI_CORE SEC
+
+[Sources]
+  PeiCpuPolicyBoardConfigPreMem.c
+  PeiMePolicyBoardConfigPreMem.c
+  PeiMePolicyBoardConfig.c
+  PeiPchPolicyBoardConfigPreMem.c
+  PeiSaPolicyBoardConfigPreMem.c
+  PeiSaPolicyBoardConfig.c
+  PeiSiPolicyBoardConfig.c
+
+[Packages]
+  MdePkg/MdePkg.dec
+  AlderlakeSiliconPkg/SiPkg.dec
+  IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec
+  CryptoPkg/CryptoPkg.dec
+  SecurityPkg/SecurityPkg.dec
+  UefiCpuPkg/UefiCpuPkg.dec
+  AlderlakeOpenBoardPkg/OpenBoardPkg.dec
+  IntelSiliconPkg/IntelSiliconPkg.dec
+  MinPlatformPkg/MinPlatformPkg.dec
+
+[LibraryClasses]
+  PcdLib
+  DebugLib
+  HobLib
+  ConfigBlockLib
+  IoLib
+  BaseCryptLib
+  BaseMemoryLib
+  FirmwareBootMediaLib
+  CpuPlatformLib
+  PmcLib
+  GpioLib
+
+
+[Guids]
+  gCpuSecurityPreMemConfigGuid                  ## CONSUMES
+  gPchGeneralPreMemConfigGuid                   ## CONSUMES
+  gSaMiscPeiPreMemConfigGuid                    ## CONSUMES
+  gPchGeneralConfigGuid                         ## CONSUMES
+
+[Ppis]
+  gEfiPeiReadOnlyVariable2PpiGuid               ## CONSUMES
+
+[Pcd]
+  gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection ## CONSUMES
+  gSiPkgTokenSpaceGuid.PcdSmbusBaseAddress            ## CONSUMES
+  gPlatformModuleTokenSpaceGuid.PcdDmiBaseAddress     ## CONSUMES
+  gPlatformModuleTokenSpaceGuid.PcdEpBaseAddress      ## CONSUMES
+  gBoardModuleTokenSpaceGuid.PcdBoardId               ## CONSUMES
+
+  [FixedPcd]
+  gSiPkgTokenSpaceGuid.PcdBiosSize                             ## CONSUMES
+  gBoardModuleTokenSpaceGuid.PcdFlashFvFirmwareBinariesBase    ## CONSUMES
+  gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryBase        ## CONSUMES
+  gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress                      ## CONSUMES
+  gSiPkgTokenSpaceGuid.PcdAdlSSupport                          ## CONSUMES
\ No newline at end of file
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyBoardConfigLib/PeiPolicyBoardConfigLibFsp.inf b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyBoardConfigLib/PeiPolicyBoardConfigLibFsp.inf
new file mode 100644
index 0000000000..2816ca6d76
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyBoardConfigLib/PeiPolicyBoardConfigLibFsp.inf
@@ -0,0 +1,67 @@
+### @file
+# Module Information file for PeiPolicyBoardConfigLib Library
+#
+#   Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+#   SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+###
+
+[Defines]
+  INF_VERSION                    = 0x00010017
+  BASE_NAME                      = PeiPolicyBoardConfigLib
+  FILE_GUID                      = B1E959E3-9DCA-4D6F-938C-420C3BF5D820
+  VERSION_STRING                 = 1.0
+  MODULE_TYPE                    = PEIM
+  LIBRARY_CLASS                  = PeiPolicyBoardConfigLib|PEIM PEI_CORE SEC
+
+[Sources]
+  PeiCpuPolicyBoardConfigPreMem.c
+  PeiMePolicyBoardConfigPreMem.c
+  PeiMePolicyBoardConfig.c
+  PeiPchPolicyBoardConfigPreMem.c
+  PeiSaPolicyBoardConfigPreMem.c
+  PeiSaPolicyBoardConfig.c
+  PeiSiPolicyBoardConfig.c
+
+[Packages]
+  MdePkg/MdePkg.dec
+  AlderlakeSiliconPkg/SiPkg.dec
+  IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec
+  SecurityPkg/SecurityPkg.dec
+  CryptoPkg/CryptoPkg.dec
+  IntelFsp2Pkg/IntelFsp2Pkg.dec
+  AlderLakeFspBinPkg/Client/AlderLakeP/AlderLakeFspBinPkg.dec
+  UefiCpuPkg/UefiCpuPkg.dec
+  AlderlakeOpenBoardPkg/OpenBoardPkg.dec
+  MinPlatformPkg/MinPlatformPkg.dec
+
+[LibraryClasses]
+  PcdLib
+  DebugLib
+  HobLib
+  IoLib
+  BaseCryptLib
+  BaseMemoryLib
+  PmcLib
+  FspCommonLib
+  GpioLib
+  PcdLib
+
+[Ppis]
+  gEfiPeiReadOnlyVariable2PpiGuid               ## CONSUMES
+
+[Pcd]
+  gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection   ## CONSUMES
+  gSiPkgTokenSpaceGuid.PcdSmbusBaseAddress              ## CONSUMES
+  gPlatformModuleTokenSpaceGuid.PcdDmiBaseAddress       ## CONSUMES
+  gPlatformModuleTokenSpaceGuid.PcdEpBaseAddress        ## CONSUMES
+  gIntelFsp2WrapperTokenSpaceGuid.PcdFspmUpdDataAddress ## CONSUMES
+  gIntelFsp2WrapperTokenSpaceGuid.PcdFspsUpdDataAddress ## CONSUMES
+  gBoardModuleTokenSpaceGuid.PcdBoardId                 ## CONSUMES
+
+[FixedPcd]
+  gSiPkgTokenSpaceGuid.PcdBiosSize                             ## CONSUMES
+  gBoardModuleTokenSpaceGuid.PcdFlashFvFirmwareBinariesBase    ## CONSUMES
+  gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryBase        ## CONSUMES
+  gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress                      ## CONSUMES
+  gSiPkgTokenSpaceGuid.PcdAdlSSupport                          ## CONSUMES
\ No newline at end of file
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyBoardConfigLib/PeiSaPolicyBoardConfig.c b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyBoardConfigLib/PeiSaPolicyBoardConfig.c
new file mode 100644
index 0000000000..236d9afcc4
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyBoardConfigLib/PeiSaPolicyBoardConfig.c
@@ -0,0 +1,47 @@
+/** @file
+ Intel PEI SA Policy update by board configuration
+
+   Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+   SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+#include "PeiPolicyBoardConfig.h"
+#include <Pins/GpioPinsVer2Lp.h>
+#include <PlatformBoardId.h>
+
+
+/**
+  This function performs PEI SA Policy update by board configuration.
+
+  @retval EFI_SUCCESS             The SI Policy is successfully updated.
+  @retval Others                  The SI Policy is not successfully updated.
+**/
+EFI_STATUS
+EFIAPI
+UpdatePeiSaPolicyBoardConfig (
+  VOID
+  )
+{
+  EFI_STATUS                         Status;
+#if FixedPcdGet8(PcdFspModeSelection) == 1
+  VOID                               *FspsUpd;
+#endif
+
+  DEBUG ((DEBUG_INFO, "Updating SA Policy by board config in Post-Mem\n"));
+
+  Status = EFI_SUCCESS;
+#if FixedPcdGet8(PcdFspModeSelection) == 1
+  FspsUpd = NULL;
+#endif
+
+#if FixedPcdGet8(PcdFspModeSelection) == 1
+  FspsUpd = (FSPS_UPD *) PcdGet32 (PcdFspsUpdDataAddress);
+  ASSERT (FspsUpd != NULL);
+  if (FspsUpd == NULL){
+    return EFI_OUT_OF_RESOURCES;
+  }
+#endif
+
+
+  return Status;
+}
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyBoardConfigLib/PeiSaPolicyBoardConfigPreMem.c b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyBoardConfigLib/PeiSaPolicyBoardConfigPreMem.c
new file mode 100644
index 0000000000..0610b0f5c2
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyBoardConfigLib/PeiSaPolicyBoardConfigPreMem.c
@@ -0,0 +1,48 @@
+/** @file
+ Intel PEI SA Pre-Memory Policy update by board configuration
+
+   Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+   SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+#include "PeiPolicyBoardConfig.h"
+
+/**
+  This function performs PEI SA Pre-Memory Policy update by board configuration.
+
+  @retval EFI_SUCCESS             The SI Policy is successfully updated.
+  @retval Others                  The SI Policy is not successfully updated.
+**/
+EFI_STATUS
+EFIAPI
+UpdatePeiSaPolicyBoardConfigPreMem (
+  VOID
+  )
+{
+  EFI_STATUS                         Status;
+#if FixedPcdGet8(PcdFspModeSelection) == 1
+  VOID                               *FspmUpd;
+#else
+  SI_PREMEM_POLICY_PPI               *SiPreMemPolicyPpi;
+#endif
+
+  DEBUG ((DEBUG_INFO, "Updating SA Policy by board config in Pre-Mem\n"));
+
+  Status = EFI_SUCCESS;
+#if FixedPcdGet8(PcdFspModeSelection) == 1
+  FspmUpd = NULL;
+#else
+  SiPreMemPolicyPpi   = NULL;
+#endif
+
+#if FixedPcdGet8(PcdFspModeSelection) == 1
+  FspmUpd = (FSPM_UPD *) PcdGet32 (PcdFspmUpdDataAddress);
+  ASSERT (FspmUpd != NULL);
+#else
+  Status = PeiServicesLocatePpi (&gSiPreMemPolicyPpiGuid, 0, NULL, (VOID **) &SiPreMemPolicyPpi);
+  ASSERT_EFI_ERROR (Status);
+#endif
+
+  return Status;
+}
+
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyBoardConfigLib/PeiSiPolicyBoardConfig.c b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyBoardConfigLib/PeiSiPolicyBoardConfig.c
new file mode 100644
index 0000000000..ce2fe19fa2
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyBoardConfigLib/PeiSiPolicyBoardConfig.c
@@ -0,0 +1,23 @@
+/** @file
+ Intel PEI SA Policy update by board configuration
+
+   Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+   SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+#include "PeiPolicyBoardConfig.h"
+
+/**
+  This function performs PEI SI Policy update by board configuration.
+
+  @retval EFI_SUCCESS             The SI Policy is successfully updated.
+  @retval Others                  The SI Policy is not successfully updated.
+**/
+EFI_STATUS
+EFIAPI
+UpdatePeiSiPolicyBoardConfig (
+  VOID
+  )
+{
+  return EFI_SUCCESS;
+}
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiCpuPolicyUpdate.c b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiCpuPolicyUpdate.c
new file mode 100644
index 0000000000..cfaf45a679
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiCpuPolicyUpdate.c
@@ -0,0 +1,344 @@
+/** @file
+  CPU PEI Policy Update & initialization.
+
+   Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+   SPDX-License-Identifier: BSD-2-Clause-Patent
+
+
+**/
+#include "PeiCpuPolicyUpdate.h"
+#include <Library/ConfigBlockLib.h>
+#include <Library/CpuPlatformLib.h>
+#include <Library/HobLib.h>
+#include <Library/PeiSiPolicyUpdateLib.h>
+#include <Library/SiPolicyLib.h>
+#include <Library/Tpm12CommandLib.h>
+#include <Library/Tpm2CommandLib.h>
+#include <Ppi/SecPlatformInformation2.h>
+
+#include <PolicyUpdateMacro.h>
+
+#if FixedPcdGet8(PcdFspModeSelection) == 1
+#include <FspmUpd.h>
+#include <FspsUpd.h>
+#include <Library/FspCommonLib.h>
+#endif
+
+#if FixedPcdGet8(PcdFspModeSelection) == 1
+/**
+  This routine is used to get Sec Platform Information Record2 Pointer.
+
+  @param[in] PeiServices    Pointer to the PEI services table
+
+  @retval GetSecPlatformInformation2 - The pointer of Sec Platform Information Record2 Pointer.
+**/
+EFI_SEC_PLATFORM_INFORMATION_RECORD2 *
+GetSecPlatformInformation2 (
+  IN EFI_PEI_SERVICES **PeiServices
+  )
+{
+  EFI_SEC_PLATFORM_INFORMATION2_PPI    *SecPlatformInformation2Ppi;
+  EFI_SEC_PLATFORM_INFORMATION_RECORD2 *SecPlatformInformation2 = NULL;
+  UINT64                               InformationSize;
+  EFI_STATUS Status;
+
+  //
+  // Get BIST information from Sec Platform Information2 Ppi firstly
+  //
+  Status = PeiServicesLocatePpi (
+             &gEfiSecPlatformInformation2PpiGuid,   // GUID
+             0,                                     // Instance
+             NULL,                                  // EFI_PEI_PPI_DESCRIPTOR
+             (VOID ** ) &SecPlatformInformation2Ppi // PPI
+             );
+  if (EFI_ERROR(Status)) {
+    DEBUG((DEBUG_ERROR, "LocatePpi SecPlatformInformationPpi2 Status - %r\n", Status));
+    return NULL;
+  }
+
+  InformationSize = 0;
+
+  Status = SecPlatformInformation2Ppi->PlatformInformation2 (
+                                         (CONST EFI_PEI_SERVICES **) PeiServices,
+                                         &InformationSize,
+                                         SecPlatformInformation2
+                                         );
+
+  ASSERT (Status == EFI_BUFFER_TOO_SMALL);
+  if (Status != EFI_BUFFER_TOO_SMALL) {
+    return NULL;
+  }
+
+  SecPlatformInformation2 = AllocatePool((UINTN)InformationSize);
+  ASSERT (SecPlatformInformation2 != NULL);
+  if (SecPlatformInformation2 == NULL) {
+    return NULL;
+  }
+
+  //
+  // Retrieve BIST data from SecPlatform2
+  //
+  Status = SecPlatformInformation2Ppi->PlatformInformation2 (
+                                         (CONST EFI_PEI_SERVICES **) PeiServices,
+                                         &InformationSize,
+                                         SecPlatformInformation2
+                                         );
+  DEBUG((DEBUG_INFO, "SecPlatformInformation2Ppi->PlatformInformation2 Status - %r\n", Status));
+  ASSERT_EFI_ERROR (Status);
+  if (EFI_ERROR (Status)) {
+    return NULL;
+  }
+
+  return SecPlatformInformation2;
+}
+
+
+/**
+  This routine is used to get Sec Platform Information Record Pointer.
+
+  @param[in] PeiServices    Pointer to the PEI services table
+
+  @retval GetSecPlatformInformation2 - The pointer of Sec Platform Information Record Pointer.
+**/
+EFI_SEC_PLATFORM_INFORMATION_RECORD2 *
+GetSecPlatformInformationInfoInFormat2 (
+  IN EFI_PEI_SERVICES **PeiServices
+  )
+{
+  EFI_SEC_PLATFORM_INFORMATION_PPI     *SecPlatformInformationPpi;
+  EFI_SEC_PLATFORM_INFORMATION_RECORD  *SecPlatformInformation = NULL;
+  EFI_SEC_PLATFORM_INFORMATION_RECORD2 *SecPlatformInformation2;
+  UINT64                               InformationSize;
+  EFI_STATUS                           Status;
+
+  //
+  // Get BIST information from Sec Platform Information
+  //
+  Status = PeiServicesLocatePpi (
+             &gEfiSecPlatformInformationPpiGuid,    // GUID
+             0,                                     // Instance
+             NULL,                                  // EFI_PEI_PPI_DESCRIPTOR
+             (VOID ** ) &SecPlatformInformationPpi  // PPI
+             );
+  if (EFI_ERROR(Status)) {
+    DEBUG((DEBUG_ERROR, "LocatePpi SecPlatformInformationPpi Status - %r\n", Status));
+    return NULL;
+  }
+
+  InformationSize = 0;
+  Status = SecPlatformInformationPpi->PlatformInformation (
+                                        (CONST EFI_PEI_SERVICES  **) PeiServices,
+                                        &InformationSize,
+                                        SecPlatformInformation
+                                        );
+
+  ASSERT (Status == EFI_BUFFER_TOO_SMALL);
+  if (Status != EFI_BUFFER_TOO_SMALL) {
+    return NULL;
+  }
+
+  SecPlatformInformation = AllocatePool((UINTN)InformationSize);
+  ASSERT (SecPlatformInformation != NULL);
+  if (SecPlatformInformation == NULL) {
+    return NULL;
+  }
+
+  //
+  // Retrieve BIST data from SecPlatform
+  //
+  Status = SecPlatformInformationPpi->PlatformInformation (
+                                        (CONST EFI_PEI_SERVICES **) PeiServices,
+                                        &InformationSize,
+                                        SecPlatformInformation
+                                        );
+  DEBUG((DEBUG_INFO, "FSP  SecPlatformInformation2Ppi->PlatformInformation Status - %r\n", Status));
+  ASSERT_EFI_ERROR (Status);
+  if (EFI_ERROR (Status)) {
+    return NULL;
+  }
+
+  SecPlatformInformation2 = AllocatePool(sizeof (EFI_SEC_PLATFORM_INFORMATION_RECORD2));
+  ASSERT (SecPlatformInformation2 != NULL);
+  if (SecPlatformInformation2 == NULL) {
+    return NULL;
+  }
+
+  SecPlatformInformation2->NumberOfCpus = 1;
+  SecPlatformInformation2->CpuInstance[0].CpuLocation = 0;
+  SecPlatformInformation2->CpuInstance[0].InfoRecord.x64HealthFlags.Uint32 = SecPlatformInformation->x64HealthFlags.Uint32;
+
+  FreePool(SecPlatformInformation);
+
+  return SecPlatformInformation2;
+}
+#endif
+
+#if FixedPcdGet8(PcdFspModeSelection) == 0
+/*
+  Get the uCode region from PCD settings, and copy the patches to memory.
+  This function is used to replace CpuLocateMicrocodePatch due to that function can not works
+  with uCode update new design.
+  In current uCode update solution, there are some padding data between uCode patches,
+  the algorithm in CpuLocateMicrocodePatch can not handle this.
+  Besides that, in CpuLocateMicrocodePatch function, the scan algorithm just find the first
+  correct uCode patch which is not the highest version uCode.
+  This function just copy the uCode region to memory, and in later, the CpuMpInit driver
+  will load the correct patch for CPU.
+
+  @param[out] RegionAddress     Pointer to the uCode array.
+  @param[out] RegionSize        Size of the microcode FV.
+
+  @retval EFI_SUCCESS           Find uCode patch region and success copy the data to memory.
+  @retval EFI_NOT_FOUND         Something wrong with uCode region.
+  @retval EFI_OUT_OF_RESOUCES   Memory allocation fail.
+  @retval EFI_INVALID_PARAMETER RegionAddres or RegionSize is NULL.
+
+*/
+EFI_STATUS
+SearchMicrocodeRegion (
+  OUT UINTN                *RegionAddress,
+  OUT UINTN                *RegionSize
+  )
+{
+  UINTN                MicrocodeStart;
+  UINTN                MicrocodeEnd;
+  UINT8                *MemoryBuffer;
+
+  if (RegionAddress == NULL || RegionSize == NULL) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  *RegionAddress = 0;
+  *RegionSize = 0;
+
+  if ((FixedPcdGet32 (PcdFlashFvMicrocodeBase) == 0) || (FixedPcdGet32 (PcdFlashFvMicrocodeSize) == 0)) {
+    return EFI_NOT_FOUND;
+  }
+
+  MicrocodeStart = (UINTN) FixedPcdGet32 (PcdFlashFvMicrocodeBase) + (UINTN) FixedPcdGet32 (PcdMicrocodeOffsetInFv);
+  MicrocodeEnd = (UINTN) FixedPcdGet32 (PcdFlashFvMicrocodeBase) + (UINTN) FixedPcdGet32 (PcdFlashFvMicrocodeSize);
+  *RegionSize = MicrocodeEnd - MicrocodeStart;
+
+  DEBUG ((DEBUG_INFO, "[SearchMicrocodeRegion]: Microcode Region Address = %x, Size = %d\n", MicrocodeStart, *RegionSize));
+
+  MemoryBuffer = AllocatePages (EFI_SIZE_TO_PAGES (*RegionSize));
+  ASSERT (MemoryBuffer != NULL);
+  if (MemoryBuffer == NULL) {
+    DEBUG ((DEBUG_ERROR, "Failed to allocate enough memory for Microcode Patch.\n"));
+    return EFI_OUT_OF_RESOURCES;
+  } else {
+    CopyMem (MemoryBuffer, (UINT8 *)MicrocodeStart, *RegionSize);
+    *RegionAddress = (UINTN)MemoryBuffer;
+    DEBUG ((DEBUG_INFO, "Copy whole uCode region to memory, address = %x, size = %d\n", RegionAddress, *RegionSize));
+  }
+
+  return EFI_SUCCESS;
+}
+#endif
+
+/**
+  This function performs CPU PEI Policy initialization.
+
+  @retval EFI_SUCCESS              The PPI is installed and initialized.
+  @retval EFI ERRORS               The PPI is not successfully installed.
+  @retval EFI_OUT_OF_RESOURCES     Do not have enough resources to initialize the driver
+**/
+EFI_STATUS
+EFIAPI
+UpdatePeiCpuPolicy (
+  VOID
+  )
+{
+  EFI_STATUS                       Status;
+  EFI_PEI_READ_ONLY_VARIABLE2_PPI  *VariableServices;
+#if FixedPcdGet8(PcdFspModeSelection) == 1
+  VOID                                 *FspsUpd;
+  VOID                                 *FspmUpd;
+  EFI_SEC_PLATFORM_INFORMATION_RECORD2 *SecPlatformInformation2;
+#else
+  SI_POLICY_PPI                    *SiPolicyPpi;
+  SI_PREMEM_POLICY_PPI             *SiPreMemPolicyPpi;
+  CPU_CONFIG                       *CpuConfig;
+  CPU_SECURITY_PREMEM_CONFIG       *CpuSecurityPreMemConfig;
+#endif
+
+  DEBUG ((DEBUG_INFO, "Update PeiCpuPolicyUpdate Pos-Mem Start\n"));
+
+#if FixedPcdGet8(PcdFspModeSelection) == 1
+  FspsUpd = NULL;
+  FspmUpd = NULL;
+#else
+  SiPolicyPpi             = NULL;
+  CpuConfig               = NULL;
+  SiPreMemPolicyPpi       = NULL;
+  CpuSecurityPreMemConfig = NULL;
+#endif
+
+#if FixedPcdGet8(PcdFspModeSelection) == 1
+  FspmUpd = (FSPM_UPD *) PcdGet32 (PcdFspmUpdDataAddress);
+  ASSERT (FspmUpd != NULL);
+
+  FspsUpd = (FSPS_UPD *) PcdGet32 (PcdFspsUpdDataAddress);
+  ASSERT (FspsUpd != NULL);
+#else
+  Status = PeiServicesLocatePpi (&gSiPreMemPolicyPpiGuid, 0, NULL, (VOID **) &SiPreMemPolicyPpi);
+  ASSERT_EFI_ERROR (Status);
+
+  Status = PeiServicesLocatePpi (&gSiPolicyPpiGuid, 0, NULL, (VOID **) &SiPolicyPpi);
+  ASSERT_EFI_ERROR (Status);
+
+  Status = GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gCpuSecurityPreMemConfigGuid, (VOID *) &CpuSecurityPreMemConfig);
+  ASSERT_EFI_ERROR (Status);
+
+  Status = GetConfigBlock ((VOID *) SiPolicyPpi, &gCpuConfigGuid, (VOID *) &CpuConfig);
+  ASSERT_EFI_ERROR (Status);
+#endif
+
+  //
+  // Make sure ReadOnlyVariablePpi is available
+  //
+  Status = PeiServicesLocatePpi (
+             &gEfiPeiReadOnlyVariable2PpiGuid,
+             0,
+             NULL,
+             (VOID **) &VariableServices
+             );
+  ASSERT_EFI_ERROR (Status);
+
+
+
+
+    // Update value is related with Setup value, Need to check Policy Default
+    COMPARE_AND_UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.PpinSupport, CpuConfig->PpinSupport, 0); ///< reference code policy is disabled
+
+  UPDATE_POLICY (((FSPS_UPD *)FspsUpd)->FspsConfig.X2ApicSupport, CpuConfig->X2ApicSupport, 0);
+
+#if FixedPcdGet8(PcdFspModeSelection) == 0
+  Status = SearchMicrocodeRegion (
+             (UINTN *)&CpuConfig->MicrocodePatchAddress,
+             (UINTN *)&CpuConfig->MicrocodePatchRegionSize
+             );
+#endif
+
+
+#if FixedPcdGet8(PcdFspModeSelection) == 1
+  //
+  // Get BIST information from Sec Platform Information
+  //
+  SecPlatformInformation2 = GetSecPlatformInformation2 ((EFI_PEI_SERVICES **) GetPeiServicesTablePointer ());
+  if (SecPlatformInformation2 == NULL) {
+    SecPlatformInformation2 = GetSecPlatformInformationInfoInFormat2 ((EFI_PEI_SERVICES **) GetPeiServicesTablePointer ());
+  }
+
+  ASSERT (SecPlatformInformation2 != NULL);
+
+  if (SecPlatformInformation2 != NULL) {
+    ((FSPS_UPD *) FspsUpd)->FspsConfig.CpuBistData = (UINT32) SecPlatformInformation2;
+    DEBUG((DEBUG_INFO, "SecPlatformInformation NumberOfCpus - %x\n", SecPlatformInformation2->NumberOfCpus));
+    DEBUG((DEBUG_INFO, "SecPlatformInformation BIST - %x\n", SecPlatformInformation2->CpuInstance[0].InfoRecord.x64HealthFlags.Uint32));
+  }
+#endif
+
+
+  return EFI_SUCCESS;
+}
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiCpuPolicyUpdate.h b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiCpuPolicyUpdate.h
new file mode 100644
index 0000000000..b003481db0
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiCpuPolicyUpdate.h
@@ -0,0 +1,31 @@
+/** @file
+  Header file for PEI CpuPolicyUpdate.
+
+   Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+   SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+#ifndef _PEI_CPU_POLICY_UPDATE_H_
+#define _PEI_CPU_POLICY_UPDATE_H_
+
+#include <PiPei.h>
+#include <Ppi/SiPolicy.h>
+#include <Ppi/Wdt.h>
+#include <Ppi/ReadOnlyVariable2.h>
+#include <Library/PeiServicesTablePointerLib.h>
+#include <Library/DebugLib.h>
+#include <Library/PcdLib.h>
+#include <Library/IoLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <PlatformBoardId.h>
+#include <Library/BaseCryptLib.h>
+#include <Register/Cpuid.h>
+#include <Register/Msr.h>
+#include <Ppi/MasterBootMode.h>
+#include <Library/PeiServicesLib.h>
+#include "PeiPchPolicyUpdate.h"
+#include <Library/CpuPlatformLib.h>
+
+
+#endif
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiCpuPolicyUpdatePreMem.c b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiCpuPolicyUpdatePreMem.c
new file mode 100644
index 0000000000..f00257848e
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiCpuPolicyUpdatePreMem.c
@@ -0,0 +1,120 @@
+/** @file
+  This file is SampleCode of the library for Intel CPU PEI Policy initialization.
+
+   Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+   SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+#include "PeiCpuPolicyUpdate.h"
+#include <Library/ConfigBlockLib.h>
+#include <Library/CpuPlatformLib.h>
+#include <Library/FirmwareBootMediaLib.h>
+#include <Library/HobLib.h>
+#include <Library/PchCycleDecodingLib.h>
+#include <Library/PciSegmentLib.h>
+#include <Library/PeiSiPolicyUpdateLib.h>
+#include <Library/PmcLib.h>
+#include <Library/SiPolicyLib.h>
+#include <Library/SpiLib.h>
+#include <Ppi/Spi.h>
+#include <Register/CommonMsr.h>
+#include <Register/PchRegs.h>
+#include <PlatformBoardConfig.h>
+#include <PolicyUpdateMacro.h>
+#if FixedPcdGet8(PcdFspModeSelection) == 1
+#include <FspmUpd.h>
+#endif
+
+#define GET_OCCUPIED_SIZE(ActualSize, Alignment) \
+  ((ActualSize) + (((Alignment) - ((ActualSize) & ((Alignment) - 1))) & ((Alignment) - 1)))
+
+
+/**
+  This function performs CPU PEI Policy initialization in Pre-memory.
+
+  @retval EFI_SUCCESS              The PPI is installed and initialized.
+  @retval EFI ERRORS               The PPI is not successfully installed.
+  @retval EFI_OUT_OF_RESOURCES     Do not have enough resources to initialize the driver
+**/
+EFI_STATUS
+EFIAPI
+UpdatePeiCpuPolicyPreMem (
+  VOID
+  )
+{
+  EFI_STATUS                      Status;
+  CPU_SECURITY_PREMEM_CONFIG      *CpuSecurityPreMemConfig;
+  CPU_CONFIG_LIB_PREMEM_CONFIG    *CpuConfigLibPreMemConfig;
+#if FixedPcdGet8(PcdFspModeSelection) == 1
+  VOID                            *FspmUpd;
+#else
+  SI_PREMEM_POLICY_PPI            *SiPreMemPolicyPpi;
+#endif
+  UINT32                          MaxLogicProcessors;
+  UINT16                          BiosSize;
+  UINT16                          BiosMemSizeInMb;
+  FW_BOOT_MEDIA_TYPE              FwBootMediaType;
+  MSR_CORE_THREAD_COUNT_REGISTER  MsrCoreThreadCount;
+  UINT8                           AllCoreCount;
+  UINT8                           AllSmallCoreCount;
+  UINT32                          DisablePerCoreMask;
+
+  DEBUG ((DEBUG_INFO, "Update PeiCpuPolicyUpdate Pre-Mem Start\n"));
+
+#if FixedPcdGet8(PcdFspModeSelection) == 1
+  FspmUpd                     = NULL;
+#else
+  SiPreMemPolicyPpi           = NULL;
+#endif
+  CpuSecurityPreMemConfig     = NULL;
+  CpuConfigLibPreMemConfig    = NULL;
+  BiosSize                    = 0;
+  BiosMemSizeInMb             = 0;
+  FwBootMediaType             = FwBootMediaMax;
+  AllCoreCount                = 0;
+  AllSmallCoreCount           = 0;
+  DisablePerCoreMask          = 0;
+
+#if FixedPcdGet8(PcdFspModeSelection) == 1
+  FspmUpd = (FSPM_UPD *) PcdGet32 (PcdFspmUpdDataAddress);
+  ASSERT (FspmUpd != NULL);
+#else
+  Status = PeiServicesLocatePpi (&gSiPreMemPolicyPpiGuid, 0, NULL, (VOID **) &SiPreMemPolicyPpi);
+  ASSERT_EFI_ERROR (Status);
+  Status = GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gCpuSecurityPreMemConfigGuid, (VOID *) &CpuSecurityPreMemConfig);
+  ASSERT_EFI_ERROR (Status);
+  Status = GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gCpuConfigLibPreMemConfigGuid, (VOID *) &CpuConfigLibPreMemConfig);
+  ASSERT_EFI_ERROR (Status);
+#endif
+
+  UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.SkipStopPbet, CpuSecurityPreMemConfig->SkipStopPbet, FALSE);
+
+  SpiServiceInit ();
+  DEBUG ((DEBUG_INFO, "BIOS Guard PCD and Policy are disabled\n"));
+  UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.BiosGuard, CpuSecurityPreMemConfig->BiosGuard, CPU_FEATURE_DISABLE);
+
+  Status = GetFirmwareBootMediaType (&FwBootMediaType);
+  if (Status != EFI_SUCCESS) {
+    ASSERT_EFI_ERROR (Status);
+    DEBUG ((DEBUG_ERROR, "FirmwareBootMediaLib Error: Cannot Get Boot Media Type\n"));
+  } 
+
+  UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.CpuRatio, CpuConfigLibPreMemConfig->CpuRatio, 0);
+
+
+  ///
+  /// Set PcdCpuMaxLogicalProcessorNumber to max number of logical processors enabled
+  /// Read MSR_CORE_THREAD_COUNT (0x35) to check the total active Threads
+  ///
+  MsrCoreThreadCount.Uint64 = AsmReadMsr64 (MSR_CORE_THREAD_COUNT);
+  MaxLogicProcessors = MsrCoreThreadCount.Bits.Threadcount;
+  DEBUG ((DEBUG_INFO, "MaxLogicProcessors = %d\n", MaxLogicProcessors));
+
+#if (FixedPcdGet8(PcdFspModeSelection) == 1)
+  PcdSet32S (PcdCpuMaxLogicalProcessorNumber, MaxLogicProcessors);
+#else
+  PcdSetEx32S (&gUefiCpuPkgTokenSpaceGuid, PcdCpuMaxLogicalProcessorNumber, MaxLogicProcessors);
+#endif
+
+  return EFI_SUCCESS;
+}
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiMePolicyUpdate.c b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiMePolicyUpdate.c
new file mode 100644
index 0000000000..9504a736dd
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiMePolicyUpdate.c
@@ -0,0 +1,65 @@
+/** @file
+
+   Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+   SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Library/ConfigBlockLib.h>
+#include <Library/DebugLib.h>
+#include <Library/PeiServicesLib.h>
+#include <Library/PeiSiPolicyUpdateLib.h>
+#include <Library/PmcLib.h>
+#include <Library/SiPolicyLib.h>
+#include <Ppi/ReadOnlyVariable2.h>
+
+#include <PolicyUpdateMacro.h>
+
+#if FixedPcdGet8(PcdFspModeSelection) == 1
+#include <FspsUpd.h>
+#endif
+
+/**
+  Update the ME Policy Library
+
+  @retval EFI_SUCCESS             Update complete.
+  @retval Others                  Update unsuccessful.
+**/
+EFI_STATUS
+EFIAPI
+UpdatePeiMePolicy (
+  VOID
+  )
+{
+  EFI_STATUS                      Status;
+
+#if FixedPcdGet8(PcdFspModeSelection) == 1
+  VOID                            *FspsUpd;
+#else
+  SI_POLICY_PPI                   *SiPolicyPpi;
+#endif
+
+
+  DEBUG ((DEBUG_INFO, "%a()\n", __FUNCTION__));
+
+#if FixedPcdGet8(PcdFspModeSelection) == 1
+  FspsUpd = NULL;
+#else
+  SiPolicyPpi = NULL;
+#endif
+
+#if FixedPcdGet8(PcdFspModeSelection) == 1
+  FspsUpd = (FSPS_UPD *) PcdGet32 (PcdFspsUpdDataAddress);
+  ASSERT (FspsUpd != NULL);
+#else
+  Status = PeiServicesLocatePpi (&gSiPolicyPpiGuid, 0, NULL, (VOID **) &SiPolicyPpi);
+  ASSERT_EFI_ERROR (Status);
+
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+#endif
+
+  return Status;
+}
+
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiMePolicyUpdatePreMem.c b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiMePolicyUpdatePreMem.c
new file mode 100644
index 0000000000..f5f4479f10
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiMePolicyUpdatePreMem.c
@@ -0,0 +1,60 @@
+/** @file
+
+   Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+   SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Library/ConfigBlockLib.h>
+#include <Library/DebugLib.h>
+#include <Library/PeiServicesLib.h>
+#include <Library/PeiSiPolicyUpdateLib.h>
+#include <Library/SiPolicyLib.h>
+#include <Ppi/ReadOnlyVariable2.h>
+
+#include <PolicyUpdateMacro.h>
+
+#if FixedPcdGet8(PcdFspModeSelection) == 1
+#include <FspmUpd.h>
+#endif
+
+/**
+  Update the ME Policy Library
+
+  @retval EFI_SUCCESS           Update complete.
+**/
+EFI_STATUS
+EFIAPI
+UpdatePeiMePolicyPreMem (
+  VOID
+  )
+{
+  EFI_STATUS                      Status;
+#if FixedPcdGet8(PcdFspModeSelection) == 1
+  VOID                            *FspmUpd;
+#else
+  SI_PREMEM_POLICY_PPI            *SiPreMemPolicyPpi;
+#endif
+
+  DEBUG ((DEBUG_INFO, "Update PeiMePolicyUpdate Pre-Mem Start\n"));
+
+#if FixedPcdGet8(PcdFspModeSelection) == 1
+  FspmUpd = NULL;
+#else
+  SiPreMemPolicyPpi = NULL;
+#endif
+
+  Status = EFI_SUCCESS;
+if (!EFI_ERROR (Status)) {
+#if FixedPcdGet8(PcdFspModeSelection) == 1
+      FspmUpd = (FSPM_UPD *) PcdGet32 (PcdFspmUpdDataAddress);
+      ASSERT (FspmUpd != NULL);
+#else
+      Status = PeiServicesLocatePpi (&gSiPreMemPolicyPpiGuid, 0, NULL, (VOID **) &SiPreMemPolicyPpi);
+      ASSERT_EFI_ERROR (Status);
+#endif
+
+  }
+
+  return Status;
+}
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiPchPolicyUpdate.c b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiPchPolicyUpdate.c
new file mode 100644
index 0000000000..9fe5e2dffe
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiPchPolicyUpdate.c
@@ -0,0 +1,267 @@
+/** @file
+  This file is SampleCode of the library for Intel PCH PEI Policy initialization.
+
+   Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+   SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "PeiPchPolicyUpdate.h"
+#include <Guid/FmpCapsule.h>
+#include <Guid/GlobalVariable.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/GpioConfig.h>
+#include <Library/HobLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/PchInfoLib.h>
+#include <Library/PchPcieRpLib.h>
+#include <Library/PeiSiPolicyUpdateLib.h>
+#include <Library/SiPolicyLib.h>
+#include <ConfigBlock.h>
+#include <Ppi/Spi.h>
+
+#include <PlatformBoardConfig.h>
+#include <PolicyUpdateMacro.h>
+#include <SerialIoDevices.h>
+
+#include <Pins/GpioPinsVer2Lp.h>
+
+#if FixedPcdGet8(PcdFspModeSelection) == 1
+#include <FspmUpd.h>
+#include <FspsUpd.h>
+#endif
+
+/**
+  This is helper function for getting I2C Pads Internal Termination settings from Pcd
+
+  @param[in]  Index            I2C Controller Index
+**/
+UINT8
+STATIC
+GetSerialIoI2cPadsTerminationFromPcd (
+  IN UINT8 Index
+  )
+{
+  switch (Index) {
+    case 0:
+      return PcdGet8 (PcdPchSerialIoI2c0PadInternalTerm);
+    case 1:
+      return PcdGet8 (PcdPchSerialIoI2c1PadInternalTerm);
+    case 2:
+      return PcdGet8 (PcdPchSerialIoI2c2PadInternalTerm);
+    case 3:
+      return PcdGet8 (PcdPchSerialIoI2c3PadInternalTerm);
+    case 4:
+      return PcdGet8 (PcdPchSerialIoI2c4PadInternalTerm);
+    case 5:
+      return PcdGet8 (PcdPchSerialIoI2c5PadInternalTerm);
+    case 6:
+      return PcdGet8 (PcdPchSerialIoI2c6PadInternalTerm);
+    case 7:
+      return PcdGet8 (PcdPchSerialIoI2c7PadInternalTerm);
+    default:
+      ASSERT (FALSE); // Invalid I2C Controller Index
+  }
+  return 0;
+}
+
+/**
+  This function performs PCH Serial IO Platform Policy initialization
+
+  @param[in] SiPolicy             Pointer to SI_POLICY_PPI
+  @param[in] FspsUpd              A VOID pointer
+**/
+VOID
+UpdateSerialIoConfig (
+  IN SI_POLICY_PPI             *SiPolicy,
+  IN VOID                      *FspsUpd
+  )
+{
+  UINT8              Index;
+#if FixedPcdGet8(PcdFspModeSelection) == 0
+  SERIAL_IO_CONFIG   *SerialIoConfig;
+  EFI_STATUS         Status;
+
+  Status = GetConfigBlock ((VOID *) SiPolicy, &gSerialIoConfigGuid, (VOID *) &SerialIoConfig);
+  ASSERT_EFI_ERROR (Status);
+  if (EFI_ERROR (Status)) {
+    return;
+  }
+#endif
+
+
+  //
+  // I2C
+  //
+  for (Index = 0; Index < GetPchMaxSerialIoI2cControllersNum (); Index++) {
+    UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.PchSerialIoI2cPadsTermination[Index], SerialIoConfig->I2cDeviceConfig[Index].PadTermination, GetSerialIoI2cPadsTerminationFromPcd (Index));
+  }
+
+  if (IsPchP ()) {
+    UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoI2cMode[0],        SerialIoConfig->I2cDeviceConfig[0].Mode,                0);
+    UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoI2cMode[1],        SerialIoConfig->I2cDeviceConfig[1].Mode,                0);
+    UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoI2cMode[2],        SerialIoConfig->I2cDeviceConfig[2].Mode,                0);
+    UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoI2cMode[3],        SerialIoConfig->I2cDeviceConfig[3].Mode,                0);
+    UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoI2cMode[4],        SerialIoConfig->I2cDeviceConfig[4].Mode,                0);
+    UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoI2cMode[5],        SerialIoConfig->I2cDeviceConfig[5].Mode,                0);
+    UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoI2cMode[6],        SerialIoConfig->I2cDeviceConfig[6].Mode,                0);
+    UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoI2cMode[7],        SerialIoConfig->I2cDeviceConfig[7].Mode,                0);
+  }
+
+    UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoUartMode[0],        SerialIoConfig->UartDeviceConfig[0].Mode,                2);
+    UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoUartMode[1],        SerialIoConfig->UartDeviceConfig[1].Mode,                0);
+    UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoUartMode[2],        SerialIoConfig->UartDeviceConfig[2].Mode,                0);
+    UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoUartMode[3],        SerialIoConfig->UartDeviceConfig[3].Mode,                0);
+    UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoUartMode[4],        SerialIoConfig->UartDeviceConfig[4].Mode,                0);
+    UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoUartMode[5],        SerialIoConfig->UartDeviceConfig[5].Mode,                0);
+    UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoUartMode[6],        SerialIoConfig->UartDeviceConfig[6].Mode,                0);
+
+    UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoUartAutoFlow[0],    SerialIoConfig->UartDeviceConfig[0].Attributes.AutoFlow, 1);
+    UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoUartAutoFlow[1],    SerialIoConfig->UartDeviceConfig[1].Attributes.AutoFlow, 1);
+    UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoUartAutoFlow[2],    SerialIoConfig->UartDeviceConfig[2].Attributes.AutoFlow, 1);
+    UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoUartAutoFlow[3],    SerialIoConfig->UartDeviceConfig[3].Attributes.AutoFlow, 0);
+    UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoUartAutoFlow[4],    SerialIoConfig->UartDeviceConfig[4].Attributes.AutoFlow, 0);
+    UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoUartAutoFlow[5],    SerialIoConfig->UartDeviceConfig[5].Attributes.AutoFlow, 0);
+    UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoUartAutoFlow[6],    SerialIoConfig->UartDeviceConfig[6].Attributes.AutoFlow, 0);
+
+    UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoUartPowerGating[0], SerialIoConfig->UartDeviceConfig[0].PowerGating,         2);
+    UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoUartPowerGating[1], SerialIoConfig->UartDeviceConfig[1].PowerGating,         2);
+    UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoUartPowerGating[2], SerialIoConfig->UartDeviceConfig[2].PowerGating,         2);
+    UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoUartPowerGating[3], SerialIoConfig->UartDeviceConfig[3].PowerGating,         0);
+    UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoUartPowerGating[4], SerialIoConfig->UartDeviceConfig[4].PowerGating,         0);
+    UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoUartPowerGating[5], SerialIoConfig->UartDeviceConfig[5].PowerGating,         0);
+    UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoUartPowerGating[6], SerialIoConfig->UartDeviceConfig[6].PowerGating,         0);
+    
+    UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoUartDmaEnable[0],   SerialIoConfig->UartDeviceConfig[0].DmaEnable,           1);
+    UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoUartDmaEnable[1],   SerialIoConfig->UartDeviceConfig[1].DmaEnable,           1);
+    UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoUartDmaEnable[2],   SerialIoConfig->UartDeviceConfig[2].DmaEnable,           1);
+    UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoUartDmaEnable[3],   SerialIoConfig->UartDeviceConfig[3].DmaEnable,           0);
+    UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoUartDmaEnable[4],   SerialIoConfig->UartDeviceConfig[4].DmaEnable,           0);
+    UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoUartDmaEnable[5],   SerialIoConfig->UartDeviceConfig[5].DmaEnable,           0);
+    UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SerialIoUartDmaEnable[6],   SerialIoConfig->UartDeviceConfig[6].DmaEnable,           0);
+
+}
+
+
+/**
+  Update PCIe Root Port Configuration
+
+  @param[in] SiPolicy             Pointer to SI_POLICY_PPI
+  @param[in] FspsUpd              Pointer to FspsUpd structure
+  // @param[in] PchSetup             Pointer to PCH_SETUP buffer
+  // @param[in] SetupVariables       Pointer to SETUP_DATA buffer
+**/
+VOID
+UpdatePcieRpConfig (
+  IN SI_POLICY_PPI             *SiPolicy,
+  IN VOID                      *FspsUpd
+  )
+{
+  UINT8                           Index;
+#if FixedPcdGet8(PcdFspModeSelection) == 0
+  EFI_STATUS                      Status;
+#endif
+#if FixedPcdGet8(PcdFspModeSelection) == 0
+  PCH_PCIE_CONFIG                 *PchPcieConfig;
+#endif
+  UINTN                           MaxPciePorts;
+
+  MaxPciePorts = GetPchMaxPciePortNum ();
+#if FixedPcdGet8(PcdFspModeSelection) == 0
+  PchPcieConfig = NULL;
+  Status = GetConfigBlock ((VOID *) SiPolicy, &gPchPcieConfigGuid, (VOID *) &PchPcieConfig);
+  ASSERT_EFI_ERROR (Status);
+  if (EFI_ERROR (Status)) {
+    return;
+  }
+#endif
+
+
+  //
+  // PCI express config
+  //
+  for (Index = 0; Index < MaxPciePorts; Index++) {
+    UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.PcieRpMaxPayload[Index],                    PchPcieConfig->RootPort[Index].PcieRpCommonConfig.MaxPayload,         PchPcieMaxPayload256);
+    UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.PcieRpPhysicalSlotNumber[Index],            PchPcieConfig->RootPort[Index].PcieRpCommonConfig.PhysicalSlotNumber, (UINT8) Index);
+    UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.PcieRpClkReqDetect[Index],                  PchPcieConfig->RootPort[Index].PcieRpCommonConfig.ClkReqDetect,       TRUE);
+  }
+}
+
+
+#if FixedPcdGet8(PcdFspModeSelection) == 1
+/**
+  Update DevInt config
+
+  @param[in] FspsUpd              Pointer to FspsUpd structure
+**/
+STATIC
+VOID
+UpdateDevIntConfig (
+  IN VOID                      *FspsUpd
+  )
+{
+  ((FSPS_UPD *) FspsUpd)->FspsConfig.DevIntConfigPtr = (UINT32) NULL;
+}
+#endif
+
+
+
+/**
+  This function performs PCH PEI Policy initialization.
+
+  @retval EFI_SUCCESS             The PPI is installed and initialized.
+  @retval EFI ERRORS              The PPI is not successfully installed.
+  @retval EFI_OUT_OF_RESOURCES    Do not have enough resources to initialize the driver
+**/
+EFI_STATUS
+EFIAPI
+UpdatePeiPchPolicy (
+  VOID
+  )
+{
+  EFI_STATUS                      Status;
+  VOID                            *FspsUpd;
+  SI_POLICY_PPI                   *SiPolicy;
+  VOID                            *FspmUpd;
+  SI_PREMEM_POLICY_PPI            *SiPreMemPolicyPpi;
+  CPU_SECURITY_PREMEM_CONFIG      *CpuSecurityPreMemConfig;
+
+  DEBUG ((DEBUG_INFO, "Update PeiPchPolicyUpdate Pos-Mem Start\n"));
+
+  FspsUpd                 = NULL;
+  FspmUpd                 = NULL;
+  SiPolicy                = NULL;
+  CpuSecurityPreMemConfig = NULL;
+  SiPreMemPolicyPpi       = NULL;
+
+#if FixedPcdGet8(PcdFspModeSelection) == 1
+  FspmUpd = (FSPM_UPD *) PcdGet32 (PcdFspmUpdDataAddress);
+  ASSERT (FspmUpd != NULL);
+  FspsUpd = (FSPS_UPD *) PcdGet32 (PcdFspsUpdDataAddress);
+  ASSERT (FspsUpd != NULL);
+#else
+  Status = PeiServicesLocatePpi (&gSiPolicyPpiGuid, 0, NULL, (VOID **) &SiPolicy);
+  ASSERT_EFI_ERROR (Status);
+  Status = PeiServicesLocatePpi (&gSiPreMemPolicyPpiGuid, 0, NULL, (VOID **) &SiPreMemPolicyPpi);
+  ASSERT_EFI_ERROR (Status);
+  Status = GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gCpuSecurityPreMemConfigGuid, (VOID *) &CpuSecurityPreMemConfig);
+  ASSERT_EFI_ERROR (Status);
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+#endif
+
+
+#if FixedPcdGet8(PcdFspModeSelection) == 1
+  //
+  // Interrupt Config
+  //
+  UpdateDevIntConfig (FspsUpd);
+#endif
+
+  UpdatePcieRpConfig (SiPolicy, FspsUpd);
+  UpdateSerialIoConfig (SiPolicy, FspsUpd);
+
+  return EFI_SUCCESS;
+}
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiPchPolicyUpdate.h b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiPchPolicyUpdate.h
new file mode 100644
index 0000000000..54dba37e1b
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiPchPolicyUpdate.h
@@ -0,0 +1,34 @@
+/** @file
+
+   Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+   SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+#ifndef _PEI_PCH_POLICY_UPDATE_H_
+#define _PEI_PCH_POLICY_UPDATE_H_
+
+//
+// External include files do NOT need to be explicitly specified in real EDKII
+// environment
+//
+#include <PiPei.h>
+#include <PlatformBoardId.h>
+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+#include <Ppi/ReadOnlyVariable2.h>
+#include <Library/PeiServicesLib.h>
+#include <Ppi/SiPolicy.h>
+#include <Library/ConfigBlockLib.h>
+#include <PlatformBoardConfig.h>
+
+//
+// Valid External Vnn Rail Configurations
+//
+typedef enum {
+  VnnRailVoltageConfig0,         // 0.7V@Bypass-0.75V@Internal-1.05V@Internal
+  VnnRailVoltageConfig1,         // 0.75V@Bypass-0.75V@Bypass-1.05V@Internal
+  VnnRailVoltageConfig2,         // 0.7V@Bypass-0.75V@Bypass-1.05V@Internal
+  VnnRailVoltageConfig3          // 1.05V@Bypass-1.05V@Bypass-1.05V@Bypass
+} VNN_RAIL_VOLTAGE_CONFIG;
+
+#endif
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiPchPolicyUpdatePreMem.c b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiPchPolicyUpdatePreMem.c
new file mode 100644
index 0000000000..290474f76d
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiPchPolicyUpdatePreMem.c
@@ -0,0 +1,173 @@
+/** @file
+  This file is SampleCode of the library for Intel PCH PEI Policy initialization.
+
+   Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+   SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "PeiPchPolicyUpdate.h"
+#include <Guid/GlobalVariable.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/HobLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/PchInfoLib.h>
+#include <Library/PchPcieRpLib.h>
+#include <Library/PeiSiPolicyUpdateLib.h>
+#include <Library/SiPolicyLib.h>
+
+#include <PolicyUpdateMacro.h>
+
+#if FixedPcdGet8(PcdFspModeSelection) == 1
+#include <FspmUpd.h>
+#endif
+
+#include <Pins/GpioPinsVer2Lp.h>
+#include <PchDmiConfig.h>
+
+//
+// Sawtooth Peak
+// Single SPD EEPROM at 0xA2 serves both C0D0 and C1D0 (LPDDR is 1DPC only)
+//
+#define DIMM_SMB_SPD_P0C0D0_STP 0xA2
+#define DIMM_SMB_SPD_P0C0D1_STP 0xA0
+#define DIMM_SMB_SPD_P0C1D0_STP 0xA2
+#define DIMM_SMB_SPD_P0C1D1_STP 0xA0
+
+GLOBAL_REMOVE_IF_UNREFERENCED UINT8 mSmbusSTPRsvdAddresses[] = {
+  DIMM_SMB_SPD_P0C0D0_STP,
+  DIMM_SMB_SPD_P0C0D1_STP,
+  DIMM_SMB_SPD_P0C1D0_STP,
+  DIMM_SMB_SPD_P0C1D1_STP
+};
+
+
+
+
+VOID
+UpdatePcieClockInfo (
+  PCH_PCIE_RP_PREMEM_CONFIG  *PcieRpPreMemConfig,
+  IN VOID                    *FspmUpd,
+  UINTN                      Index,
+  UINT64                     Data
+  )
+{
+  PCD64_BLOB Pcd64;
+
+  Pcd64.Blob = Data;
+  DEBUG ((DEBUG_INFO, "UpdatePcieClockInfo ClkIndex %x ClkUsage %x, Supported %x\n", Index, Pcd64.PcieClock.ClockUsage, Pcd64.PcieClock.ClkReqSupported));
+
+  UPDATE_POLICY (((FSPM_UPD *)FspmUpd)->FspmConfig.PcieClkSrcUsage[Index], PcieRpPreMemConfig->PcieClock[Index].Usage, (UINT8)Pcd64.PcieClock.ClockUsage);
+  UPDATE_POLICY (((FSPM_UPD *)FspmUpd)->FspmConfig.PcieClkSrcClkReq[Index], PcieRpPreMemConfig->PcieClock[Index].ClkReq, Pcd64.PcieClock.ClkReqSupported ? (UINT8)Index : 0xFF);
+}
+
+/**
+  Update PcieRp pre mem policies.
+
+  @param[in] SiPreMemPolicy Pointer to SI_PREMEM_POLICY_PPI
+  @param[in] FspsUpm        Pointer to FSPM_UPD
+  @param[in] PchSetup       Pointer to PCH_SETUP
+**/
+STATIC
+VOID
+UpdatePcieRpPreMemPolicy (
+  IN  SI_PREMEM_POLICY_PPI     *SiPreMemPolicy,
+  IN  VOID                     *FspmUpd
+  )
+{
+  UINT32                          RpIndex;
+  UINT32                          RpEnabledMask;
+  PCH_PCIE_RP_PREMEM_CONFIG       *PcieRpPreMemConfig;
+#if FixedPcdGet8(PcdFspModeSelection) == 0
+  EFI_STATUS                      Status;
+  Status = GetConfigBlock ((VOID *) SiPreMemPolicy, &gPcieRpPreMemConfigGuid, (VOID *) &PcieRpPreMemConfig);
+  ASSERT_EFI_ERROR (Status);
+  if (EFI_ERROR (Status)) {
+    return;
+  }
+#else
+  PcieRpPreMemConfig = NULL;
+#endif
+
+  GET_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.PcieRpEnableMask, PcieRpPreMemConfig->RpEnabledMask, RpEnabledMask);
+
+  for (RpIndex = 0; RpIndex < GetPchMaxPciePortNum (); RpIndex ++) {
+      RpEnabledMask |=  (UINT32) (1 << RpIndex);
+  }
+  // RpEnabledMask value is related with Setup value, Need to check Policy Default
+  COMPARE_AND_UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.PcieRpEnableMask, PcieRpPreMemConfig->RpEnabledMask, RpEnabledMask);
+
+  UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 0, PcdGet64(PcdPcieClock0));
+  UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 1, PcdGet64(PcdPcieClock1));
+  UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 2, PcdGet64(PcdPcieClock2));
+  UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 3, PcdGet64(PcdPcieClock3));
+  UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 4, PcdGet64(PcdPcieClock4));
+  UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 5, PcdGet64(PcdPcieClock5));
+  UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 6, PcdGet64(PcdPcieClock6));
+  UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 7, PcdGet64(PcdPcieClock7));
+  UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 8, PcdGet64(PcdPcieClock8));
+  UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 9, PcdGet64(PcdPcieClock9));
+  UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 10, PcdGet64(PcdPcieClock10));
+  UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 11, PcdGet64(PcdPcieClock11));
+  UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 12, PcdGet64(PcdPcieClock12));
+  UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 13, PcdGet64(PcdPcieClock13));
+  UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 14, PcdGet64(PcdPcieClock14));
+  UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 15, PcdGet64(PcdPcieClock15));
+  UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 16, PcdGet64(PcdPcieClock16));
+  UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 17, PcdGet64(PcdPcieClock17));
+
+}
+
+/**
+  Update Dmi Pre Mem policies.
+
+  @param[in] SiPreMemPolicy Pointer to SI_PREMEM_POLICY_PPI
+  @param[in] FspmUpd        Pointer to FSPM_UPD
+**/
+STATIC
+VOID
+UpdateDmiPreMemPolicy (
+  IN SI_PREMEM_POLICY_PPI *SiPreMemPolicy,
+  IN VOID                 *FspmUpd
+  )
+{
+  return;
+}
+
+/**
+  This function performs PCH PEI Policy initialization.
+
+  @retval EFI_SUCCESS             The PPI is installed and initialized.
+  @retval EFI ERRORS              The PPI is not successfully installed.
+  @retval EFI_OUT_OF_RESOURCES    Do not have enough resources to initialize the driver
+**/
+EFI_STATUS
+EFIAPI
+UpdatePeiPchPolicyPreMem (
+  VOID
+  )
+{
+  EFI_STATUS                      Status;
+  VOID                            *FspmUpd;
+  SI_PREMEM_POLICY_PPI            *SiPreMemPolicy;
+
+  DEBUG ((DEBUG_INFO, "Update PeiPchPolicyUpdate Pre-Mem Start\n"));
+
+  FspmUpd        = NULL;
+  SiPreMemPolicy = NULL;
+
+#if FixedPcdGet8(PcdFspModeSelection) == 1
+  FspmUpd = (FSPM_UPD *) PcdGet32 (PcdFspmUpdDataAddress);
+  ASSERT (FspmUpd != NULL);
+#else
+  Status = PeiServicesLocatePpi (&gSiPreMemPolicyPpiGuid, 0, NULL, (VOID **) &SiPreMemPolicy);
+  ASSERT_EFI_ERROR (Status);
+  if (EFI_ERROR (Status)) {
+    return Status;
+  }
+#endif
+
+  UpdatePcieRpPreMemPolicy (SiPreMemPolicy, FspmUpd);
+  return EFI_SUCCESS;
+}
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiPolicyUpdateLib.inf b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiPolicyUpdateLib.inf
new file mode 100644
index 0000000000..a02093054d
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiPolicyUpdateLib.inf
@@ -0,0 +1,225 @@
+### @file
+# Module Information file for PEI PolicyUpdateLib Library
+#
+#   Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+#   SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+###
+
+[Defines]
+  INF_VERSION                    = 0x00010017
+  BASE_NAME                      = PeiPolicyUpdateLib
+  FILE_GUID                      = D42F5BB8-E0CE-47BD-8C52-476C79055FC6
+  VERSION_STRING                 = 1.0
+  MODULE_TYPE                    = PEIM
+  LIBRARY_CLASS                  = PeiPolicyUpdateLib|PEIM PEI_CORE SEC
+
+[LibraryClasses]
+  HobLib
+  BaseCryptLib
+  CpuPlatformLib
+  IoLib
+  ConfigBlockLib
+  MemoryAllocationLib
+  PeiServicesTablePointerLib
+  PcdLib
+  Tpm2CommandLib
+  Tpm12CommandLib
+  Tpm2DeviceLib
+  Tpm12DeviceLib
+  BoardConfigLib
+  PciSegmentLib
+  SiPolicyLib
+  PeiServicesLib
+  FirmwareBootMediaLib
+  SpiLib
+  BmpSupportLib
+  PeiGetFvInfoLib
+  TimerLib
+
+[Packages]
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  UefiCpuPkg/UefiCpuPkg.dec
+  IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec
+  AlderlakeSiliconPkg/SiPkg.dec
+  SecurityPkg/SecurityPkg.dec
+  CryptoPkg/CryptoPkg.dec
+  IntelSiliconPkg/IntelSiliconPkg.dec
+  AlderlakeOpenBoardPkg/OpenBoardPkg.dec
+  MinPlatformPkg/MinPlatformPkg.dec
+  BoardModulePkg/BoardModulePkg.dec
+
+[FixedPcd]
+  gBoardModuleTokenSpaceGuid.PcdDefaultBoardId                            ## CONSUMES
+  gBoardModuleTokenSpaceGuid.PcdFlashFvFirmwareBinariesBase               ## CONSUMES
+  gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection                     ## CONSUMES
+  gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase                   ## CONSUMES
+  gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize                   ## CONSUMES
+  gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageSize                     ## CONSUMES
+  gMinPlatformPkgTokenSpaceGuid.PcdMicrocodeOffsetInFv                    ## CONSUMES
+  gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiAcpiNvsMemorySize           ## CONSUMES
+  gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiAcpiReclaimMemorySize       ## CONSUMES
+  gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiReservedMemorySize          ## CONSUMES
+  gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtCodeMemorySize            ## CONSUMES
+  gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtDataMemorySize            ## CONSUMES
+  gSiPkgTokenSpaceGuid.PcdAdlLpSupport                                    ## CONSUMES
+  gSiPkgTokenSpaceGuid.PcdBiosSize                                        ## CONSUMES
+  gSiPkgTokenSpaceGuid.PcdTsegSize                                        ## CONSUMES
+
+[Pcd]
+  gSiPkgTokenSpaceGuid.PcdMchBaseAddress             ## CONSUMES
+  gSiPkgTokenSpaceGuid.PcdSmbusBaseAddress           ## CONSUMES
+  gPlatformModuleTokenSpaceGuid.PcdDmiBaseAddress    ## CONSUMES
+  gPlatformModuleTokenSpaceGuid.PcdEpBaseAddress     ## CONSUMES
+  gPlatformModuleTokenSpaceGuid.PcdGttMmAddress      ## CONSUMES
+  gPlatformModuleTokenSpaceGuid.PcdGmAdrAddress      ## CONSUMES
+  gPlatformModuleTokenSpaceGuid.PcdEdramBaseAddress  ## CONSUMES
+
+  gBoardModuleTokenSpaceGuid.PcdSaDdrFreqLimit       ## CONSUMES
+  gBoardModuleTokenSpaceGuid.PcdBoardPmcPdEnable     ## CONSUMES
+  gBoardModuleTokenSpaceGuid.PcdBoardId              ## CONSUMES
+
+  # SA Misc Config
+  gBoardModuleTokenSpaceGuid.PcdSaMiscUserBd                   ## CONSUMES
+  gBoardModuleTokenSpaceGuid.PcdSaMiscMmioSizeAdjustment       ## CONSUMES
+  gBoardModuleTokenSpaceGuid.PcdMrcRcompResistor               ## CONSUMES
+  gBoardModuleTokenSpaceGuid.PcdMrcRcompTarget                 ## CONSUMES
+  gBoardModuleTokenSpaceGuid.PcdMrcDqByteMap                   ## CONSUMES
+  gBoardModuleTokenSpaceGuid.PcdMrcDqByteMapSize               ## CONSUMES
+  gBoardModuleTokenSpaceGuid.PcdMrcDqsMapCpu2Dram              ## CONSUMES
+  gBoardModuleTokenSpaceGuid.PcdMrcDqsMapCpu2DramSize          ## CONSUMES
+  gBoardModuleTokenSpaceGuid.PcdMrcDqMapCpu2Dram               ## CONSUMES
+  gBoardModuleTokenSpaceGuid.PcdMrcDqMapCpu2DramSize           ## CONSUMES
+  gBoardModuleTokenSpaceGuid.PcdMrcDqPinsInterleavedControl    ## CONSUMES
+  gBoardModuleTokenSpaceGuid.PcdMrcDqPinsInterleaved           ## CONSUMES
+  gBoardModuleTokenSpaceGuid.PcdMrcSpdData                     ## CONSUMES
+  gBoardModuleTokenSpaceGuid.PcdMrcSpdDataSize                 ## CONSUMES
+  gBoardModuleTokenSpaceGuid.PcdMrcLp5CccConfig                ## CONSUMES
+  gBoardModuleTokenSpaceGuid.PcdMrcCmdMirror                   ## CONSUMES
+  gBoardModuleTokenSpaceGuid.PcdSaMiscFirstDimmBitMask         ## CONSUMES
+  gBoardModuleTokenSpaceGuid.PcdSaMiscFirstDimmBitMaskEcc      ## CONSUMES
+  gBoardModuleTokenSpaceGuid.PcdSaMiscDisableMrcRetrainingOnRtcPowerLoss ## CONSUMES
+
+  # Display DDI
+  gBoardModuleTokenSpaceGuid.PcdSaDisplayConfigTable           ## CONSUMES
+  gBoardModuleTokenSpaceGuid.PcdSaDisplayConfigTableSize       ## CONSUMES
+
+  # PCIE RTD3 GPIO
+  gBoardModuleTokenSpaceGuid.PcdRootPortIndex                  ## CONSUMES
+
+  gBoardModuleTokenSpaceGuid.PcdPcieSlot1GpioSupport               ## CONSUMES
+
+  # SPD Address Table
+  gBoardModuleTokenSpaceGuid.PcdSpdPresent                     ## CONSUMES
+  gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable0            ## CONSUMES
+  gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable1            ## CONSUMES
+  gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable2            ## CONSUMES
+  gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable3            ## CONSUMES
+  gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable4            ## CONSUMES
+  gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable5            ## CONSUMES
+  gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable6            ## CONSUMES
+  gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable7            ## CONSUMES
+  gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable8            ## CONSUMES
+  gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable9            ## CONSUMES
+  gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable10           ## CONSUMES
+  gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable11           ## CONSUMES
+  gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable12           ## CONSUMES
+  gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable13           ## CONSUMES
+  gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable14           ## CONSUMES
+  gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable15           ## CONSUMES
+
+
+  # PCIe Clock Info
+  gBoardModuleTokenSpaceGuid.PcdPcieClock0                     ## CONSUMES
+  gBoardModuleTokenSpaceGuid.PcdPcieClock1                     ## CONSUMES
+  gBoardModuleTokenSpaceGuid.PcdPcieClock2                     ## CONSUMES
+  gBoardModuleTokenSpaceGuid.PcdPcieClock3                     ## CONSUMES
+  gBoardModuleTokenSpaceGuid.PcdPcieClock4                     ## CONSUMES
+  gBoardModuleTokenSpaceGuid.PcdPcieClock5                     ## CONSUMES
+  gBoardModuleTokenSpaceGuid.PcdPcieClock6                     ## CONSUMES
+  gBoardModuleTokenSpaceGuid.PcdPcieClock7                     ## CONSUMES
+  gBoardModuleTokenSpaceGuid.PcdPcieClock8                     ## CONSUMES
+  gBoardModuleTokenSpaceGuid.PcdPcieClock9                     ## CONSUMES
+  gBoardModuleTokenSpaceGuid.PcdPcieClock10                    ## CONSUMES
+  gBoardModuleTokenSpaceGuid.PcdPcieClock11                    ## CONSUMES
+  gBoardModuleTokenSpaceGuid.PcdPcieClock12                    ## CONSUMES
+  gBoardModuleTokenSpaceGuid.PcdPcieClock13                    ## CONSUMES
+  gBoardModuleTokenSpaceGuid.PcdPcieClock14                    ## CONSUMES
+  gBoardModuleTokenSpaceGuid.PcdPcieClock15                    ## CONSUMES
+  gBoardModuleTokenSpaceGuid.PcdPcieClock16                    ## CONSUMES
+  gBoardModuleTokenSpaceGuid.PcdPcieClock17                    ## CONSUMES
+
+
+  # Pch SerialIo I2c Pads Termination
+  gBoardModuleTokenSpaceGuid.PcdPchSerialIoI2c0PadInternalTerm ## CONSUMES
+  gBoardModuleTokenSpaceGuid.PcdPchSerialIoI2c1PadInternalTerm ## CONSUMES
+  gBoardModuleTokenSpaceGuid.PcdPchSerialIoI2c2PadInternalTerm ## CONSUMES
+  gBoardModuleTokenSpaceGuid.PcdPchSerialIoI2c3PadInternalTerm ## CONSUMES
+  gBoardModuleTokenSpaceGuid.PcdPchSerialIoI2c4PadInternalTerm ## CONSUMES
+  gBoardModuleTokenSpaceGuid.PcdPchSerialIoI2c5PadInternalTerm ## CONSUMES
+  gBoardModuleTokenSpaceGuid.PcdPchSerialIoI2c6PadInternalTerm ## CONSUMES
+  gBoardModuleTokenSpaceGuid.PcdPchSerialIoI2c7PadInternalTerm ## CONSUMES
+
+  gIntelSiliconPkgTokenSpaceGuid.PcdIntelGraphicsVbtFileGuid   ## CONSUMES
+  gBoardModuleTokenSpaceGuid.PcdSmbusAlertEnable               ## CONSUMES
+  gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber    ## CONSUMES
+  gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress        ## CONSUMES
+  gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize     ## CONSUMES
+  gBoardModuleTokenSpaceGuid.PcdPolicyCheckIsFirstBoot         ## CONSUMES
+  gBoardModuleTokenSpaceGuid.PcdPolicyCheckIsRvpSupport        ## CONSUMES
+  gBoardModuleTokenSpaceGuid.PcdPolicyCheckPcdInitDone         ## CONSUMES
+  gPlatformModuleTokenSpaceGuid.PcdExtendedBiosRegionSupport   ## CONSUMES
+  gBoardModuleTokenSpaceGuid.PcdFlashExtendRegionSizeInUse     ## CONSUMES
+  gBoardModuleTokenSpaceGuid.PcdBoardGpioTablePreMem           ## CONSUMES
+
+[Sources]
+  PeiPchPolicyUpdatePreMem.c
+  PeiPchPolicyUpdate.c
+  PeiCpuPolicyUpdatePreMem.c
+  PeiCpuPolicyUpdate.c
+  PeiMePolicyUpdatePreMem.c
+  PeiMePolicyUpdate.c
+  PeiSaPolicyUpdate.c
+  PeiSaPolicyUpdatePreMem.c
+  PeiSiPolicyUpdate.c
+
+[Ppis]
+  gEfiPeiReadOnlyVariable2PpiGuid               ## CONSUMES
+  gWdtPpiGuid                                   ## CONSUMES
+  gPchSpiPpiGuid                                ## CONSUMES
+  gSiPolicyPpiGuid                              ## CONSUMES
+  gSiPreMemPolicyPpiGuid                        ## CONSUMES
+  gFspmArchConfigPpiGuid                        ## PRODUCES
+  gReadyForGopConfigPpiGuid                     ## PRODUCES
+  gPeiGraphicsPlatformPpiGuid                   ## CONSUMES
+  gPeiGraphicsFramebufferReadyPpiGuid           ## CONSUMES
+
+[Guids]
+  gEfiGlobalVariableGuid                        ## CONSUMES
+  gMemoryConfigVariableGuid                     ## CONSUMES
+  gS3MemoryVariableGuid                         ## CONSUMES
+  gEfiCapsuleVendorGuid                         ## CONSUMES
+  gEfiMemoryTypeInformationGuid                 ## CONSUMES
+  gEfiMemoryOverwriteControlDataGuid            ## CONSUMES
+  gDebugConfigVariableGuid                      ## CONSUMES
+  gSiPreMemConfigGuid                           ## CONSUMES
+  gSiConfigGuid                                 ## CONSUMES
+  gCpuSecurityPreMemConfigGuid                  ## CONSUMES
+  gCpuConfigLibPreMemConfigGuid                 ## CONSUMES
+  gCpuConfigGuid                                ## CONSUMES
+  gVmdPeiConfigGuid                             ## CONSUMES
+  gCpuPcieRpPrememConfigGuid                    ## CONSUMES
+  gVmdInfoHobGuid                               ## CONSUMES
+  gPciePreMemConfigGuid                         ## CONSUMES
+  gPlatformInitFvLocationGuid                   ## CONSUMES
+  gHostBridgePeiPreMemConfigGuid                ## CONSUMES
+  gEfiVmdFeatureVariableGuid                    ## CONSUMES
+  gEfiGraphicsInfoHobGuid                       ## CONSUMES
+  gPchDmiPreMemConfigGuid                       ## CONSUMES
+  gGraphicsPeiConfigGuid                        ## CONSUMES
+  gMemoryConfigGuid                             ## CONSUMES
+  gMemoryConfigNoCrcGuid                        ## CONSUMES
+  gPchPcieConfigGuid                            ## CONSUMES
+  gSerialIoConfigGuid                           ## CONSUMES
+  gPcieRpPreMemConfigGuid                       ## CONSUMES
\ No newline at end of file
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiSaPolicyUpdate.c b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiSaPolicyUpdate.c
new file mode 100644
index 0000000000..659da2f296
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiSaPolicyUpdate.c
@@ -0,0 +1,293 @@
+/** @file
+Do Platform Stage System Agent initialization.
+
+   Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+   SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "PeiSaPolicyUpdate.h"
+#include <Library/BaseMemoryLib.h>
+#include <Library/BmpSupportLib.h>
+#include <Library/CpuPcieInfoFruLib.h>
+#include <Library/HobLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/PeiGetFvInfoLib.h>
+#include <Library/PeiSiPolicyUpdateLib.h>
+#include <Library/SiPolicyLib.h>
+#include <Pi/PiFirmwareFile.h>
+#include <Protocol/GraphicsOutput.h>
+
+#include <CpuPcieConfig.h>
+#include <CpuPcieHob.h>
+#include <IndustryStandard/Bmp.h>
+#include <Platform.h>
+#include <PolicyUpdateMacro.h>
+#include <Guid/GraphicsInfoHob.h>
+
+#include <VmdPeiConfig.h>
+#if FixedPcdGet8(PcdFspModeSelection) == 1
+#include <FspsUpd.h>
+#endif
+
+#include <Ppi/GraphicsPlatformPolicyPpi.h>
+
+
+#if FixedPcdGet8(PcdFspModeSelection) == 0
+EFI_STATUS
+EFIAPI
+PeiGraphicsPolicyUpdateCallback (
+  IN EFI_PEI_SERVICES           **PeiServices,
+  IN EFI_PEI_NOTIFY_DESCRIPTOR  *NotifyDescriptor,
+  IN VOID                       *Ppi
+  )
+{
+  EFI_STATUS                          Status;
+  EFI_PEI_GRAPHICS_INFO_HOB           *PlatformGraphicsOutput;
+  EFI_PEI_HOB_POINTERS                 Hob;
+  UINT8                               *HobStart;
+#if FixedPcdGet8(PcdFspModeSelection) == 1
+  VOID                                *FspsUpd;
+#else
+  GRAPHICS_PEI_CONFIG                 *GtConfig;
+  SI_POLICY_PPI                       *SiPolicyPpi;
+#endif
+
+  DEBUG ((DEBUG_INFO, "%a: Entry\n",__FUNCTION__));
+
+  PlatformGraphicsOutput = NULL;
+  HobStart = NULL;
+
+#if FixedPcdGet8(PcdFspModeSelection) == 1
+  FspsUpd = NULL;
+  FspsUpd = (FSPS_UPD *) PcdGet32 (PcdFspsUpdDataAddress);
+  ASSERT (FspsUpd != NULL);
+#else
+  GtConfig = NULL;
+  SiPolicyPpi = NULL;
+  Status = PeiServicesLocatePpi (&gSiPolicyPpiGuid, 0, NULL, (VOID **) &SiPolicyPpi);
+  ASSERT_EFI_ERROR(Status);
+
+  Status = GetConfigBlock ((VOID *) SiPolicyPpi, &gGraphicsPeiConfigGuid, (VOID *) &GtConfig);
+  ASSERT_EFI_ERROR(Status);
+#endif
+
+  Status = PeiServicesGetHobList ((VOID **) &Hob.Raw);
+  HobStart = Hob.Raw;
+
+  if (!EFI_ERROR (Status)) {
+    if (HobStart != NULL) {
+      if ((Hob.Raw = GetNextGuidHob (&gEfiGraphicsInfoHobGuid, HobStart)) != NULL) {
+        DEBUG ((DEBUG_INFO, "Found EFI_PEI_GRAPHICS_INFO_HOB\n"));
+        PlatformGraphicsOutput = GET_GUID_HOB_DATA (Hob.Guid);
+      }
+    }
+  }
+
+  if (PlatformGraphicsOutput != NULL) {
+    UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.HorizontalResolution,   GtConfig->HorizontalResolution, PlatformGraphicsOutput->GraphicsMode.HorizontalResolution);
+    UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.VerticalResolution,     GtConfig->VerticalResolution,   PlatformGraphicsOutput->GraphicsMode.VerticalResolution);
+  } else {
+    DEBUG ((DEBUG_INFO, "Not able to find EFI_PEI_GRAPHICS_INFO_HOB\n"));
+  }
+
+  DEBUG((DEBUG_INFO, "%a: Exit\n", __FUNCTION__));
+  return Status;
+}
+
+STATIC
+EFI_PEI_NOTIFY_DESCRIPTOR  mPeiGfxPolicyUpdateNotifyList = {
+  (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
+  &gPeiGraphicsFramebufferReadyPpiGuid,
+  PeiGraphicsPolicyUpdateCallback
+};
+#endif
+
+#if FixedPcdGet8(PcdFspModeSelection) == 1
+#if FixedPcdGetBool(PcdAdlLpSupport) == 1
+EFI_STATUS
+EFIAPI
+PeiGraphicsPlatformPolicyNotifyCallback (
+  IN EFI_PEI_SERVICES           **PeiServices,
+  IN EFI_PEI_NOTIFY_DESCRIPTOR  *NotifyDescriptor,
+  IN VOID                       *Ppi
+  )
+{
+  EFI_STATUS                        Status;
+  VOID                             *FspsUpd;
+  PEI_GRAPHICS_PLATFORM_POLICY_PPI *GfxPlatformPolicyPpi;
+  LID_STATUS                       CurrentLidStatus;
+
+  DEBUG ((DEBUG_INFO, "PeiGraphicsPlatformPolicyNotifyCallback Entry\n"));
+
+  FspsUpd = (FSPS_UPD *) PcdGet32 (PcdFspsUpdDataAddress);
+  ASSERT (FspsUpd != NULL);
+  ///
+  /// Locate GfxPlatformPolicyPpi
+  ///
+  Status = PeiServicesLocatePpi (&gPeiGraphicsPlatformPpiGuid, 0, NULL, (VOID *) &GfxPlatformPolicyPpi);
+  if (EFI_ERROR (Status)) {
+    DEBUG ((DEBUG_WARN, "Failed to locate GfxPlatformPolicyPpi.\n"));
+    ASSERT_EFI_ERROR(Status);
+  }
+
+  Status = GfxPlatformPolicyPpi->GetPlatformLidStatus (&CurrentLidStatus);
+  ASSERT_EFI_ERROR (Status);
+  ((FSPS_UPD *) FspsUpd)->FspsConfig.LidStatus = (UINT8) CurrentLidStatus;
+  DEBUG ((DEBUG_INFO, "LidStatus from GetPlatformLidStatus is 0x%x\n", ((FSPS_UPD *) FspsUpd)->FspsConfig.LidStatus));
+  DEBUG ((DEBUG_INFO, "PeiGraphicsPlatformPolicyNotifyCallback Exit\n"));
+
+  return Status;
+}
+
+STATIC
+EFI_PEI_NOTIFY_DESCRIPTOR  mPeiGfxPlatformPolicyNotifyList = {
+  (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
+  &gPeiGraphicsPlatformPpiGuid,
+  PeiGraphicsPlatformPolicyNotifyCallback
+};
+#endif
+#endif
+
+
+/**
+  UpdatePeiSaPolicy performs SA PEI Policy initialization
+
+  @retval EFI_SUCCESS              The policy is installed and initialized.
+**/
+EFI_STATUS
+EFIAPI
+UpdatePeiSaPolicy (
+  VOID
+  )
+{
+  EFI_GUID                        BmpImageGuid;
+  EFI_STATUS                      Status;
+  EFI_GUID                        FileGuid;
+  VOID                            *Buffer;
+  UINT32                          Size;
+  EFI_BOOT_MODE                   BootMode;
+  VOID                            *VmdVariablePtr;
+  GRAPHICS_PEI_CONFIG             *GtConfig;
+  SI_POLICY_PPI                   *SiPolicyPpi;
+  CPU_PCIE_CONFIG                 *CpuPcieRpConfig;
+  VMD_PEI_CONFIG                  *VmdPeiConfig;
+  EFI_PEI_PPI_DESCRIPTOR          *ReadyForGopConfigPpiDesc;
+  VOID                            *VbtPtr;
+  EFI_GRAPHICS_OUTPUT_BLT_PIXEL    *Blt;
+  UINTN                            BltSize;
+  UINTN                            Height;
+  UINTN                            Width;
+
+  DEBUG ((DEBUG_INFO, "Update PeiSaPolicyUpdate Pos-Mem Start\n"));
+
+  Size  = 0;
+  Blt   = NULL;
+  BltSize = 0;
+
+  GtConfig              = NULL;
+  SiPolicyPpi           = NULL;
+  CpuPcieRpConfig       = NULL;
+  VmdVariablePtr        = NULL;
+  Buffer     = NULL;
+
+  Status = PeiServicesLocatePpi (&gSiPolicyPpiGuid, 0, NULL, (VOID **) &SiPolicyPpi);
+  ASSERT_EFI_ERROR (Status);
+
+  Status = GetConfigBlock ((VOID *) SiPolicyPpi, &gGraphicsPeiConfigGuid, (VOID *) &GtConfig);
+  ASSERT_EFI_ERROR(Status);
+
+
+
+  VmdPeiConfig          = NULL;
+  Status = GetConfigBlock ((VOID *) SiPolicyPpi, &gVmdPeiConfigGuid, (VOID *) &VmdPeiConfig);
+  ASSERT_EFI_ERROR(Status);
+
+  Status = PeiServicesGetBootMode (&BootMode);
+  ASSERT_EFI_ERROR (Status);
+
+  CopyMem(&BmpImageGuid, PcdGetPtr(PcdIntelGraphicsVbtFileGuid), sizeof(BmpImageGuid));
+
+
+  if (!EFI_ERROR (Status)) {
+    UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.SkipFspGop,                      GtConfig->SkipFspGop,          0x0);
+
+
+      Buffer = NULL;
+
+      CopyMem(&FileGuid, &BmpImageGuid, sizeof(FileGuid));
+      PeiGetSectionFromFv(FileGuid, &Buffer, &Size);
+      if (Buffer == NULL) {
+        DEBUG((DEBUG_ERROR, "Could not locate VBT\n"));
+      }
+
+      if (BootMode == BOOT_ON_S3_RESUME) {
+        UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.GraphicsConfigPtr, GtConfig->GraphicsConfigPtr, NULL);
+      } else {
+        GtConfig->GraphicsConfigPtr = Buffer;
+        DEBUG ((DEBUG_INFO, "Vbt Pointer from PeiGetSectionFromFv is 0x%x\n", GtConfig->GraphicsConfigPtr));
+      }
+      DEBUG ((DEBUG_INFO, "Vbt Size from PeiGetSectionFromFv is 0x%x\n", Size));
+      GET_POLICY ((VOID *) ((FSPS_UPD *) FspsUpd)->FspsConfig.GraphicsConfigPtr, GtConfig->GraphicsConfigPtr, VbtPtr);
+
+      //
+      // Install ReadyForGopConfig PPI to trigger PEI phase GopConfig callback.
+      //
+      ReadyForGopConfigPpiDesc = (EFI_PEI_PPI_DESCRIPTOR *) AllocateZeroPool (sizeof (EFI_PEI_PPI_DESCRIPTOR));
+      if (ReadyForGopConfigPpiDesc == NULL) {
+        ASSERT (FALSE);
+        return EFI_OUT_OF_RESOURCES;
+      }
+      ReadyForGopConfigPpiDesc->Flags = EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST;
+      ReadyForGopConfigPpiDesc->Guid  = &gReadyForGopConfigPpiGuid;
+      ReadyForGopConfigPpiDesc->Ppi   = VbtPtr;
+      Status = PeiServicesInstallPpi (ReadyForGopConfigPpiDesc);
+
+
+    Status = TranslateBmpToGopBlt (
+              Buffer,
+              Size,
+              &Blt,
+              &BltSize,
+              &Height,
+              &Width
+              );
+
+    if (Status == EFI_BUFFER_TOO_SMALL) {
+      Blt = NULL;
+      Status = TranslateBmpToGopBlt (
+                Buffer,
+                Size,
+                &Blt,
+                &BltSize,
+                &Height,
+                &Width
+                );
+      if (EFI_ERROR (Status)) {
+        DEBUG ((DEBUG_ERROR, "TranslateBmpToGopBlt, Status = %r\n", Status));
+        ASSERT_EFI_ERROR (Status);
+        return Status;
+      }
+    }
+
+    //
+    // Initialize Blt, BltSize
+    //
+    GtConfig->BltBufferAddress = Blt;
+
+    UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.BltBufferSize,   GtConfig->BltBufferSize,  BltSize);
+
+    DEBUG ((DEBUG_INFO, "Calling mPeiGfxPolicyUpdateNotifyList\n"));
+    Status = PeiServicesNotifyPpi (&mPeiGfxPolicyUpdateNotifyList);
+
+  }
+
+  //
+  // VMD related settings from setup variable
+  //
+  COMPARE_AND_UPDATE_POLICY (((FSPS_UPD *) FspsUpd)->FspsConfig.VmdEnable,            VmdPeiConfig->VmdEnable,                       0);
+  VmdPeiConfig->VmdVariablePtr = VmdVariablePtr;
+  DEBUG ((DEBUG_INFO, "VmdVariablePtr from PeiGetSectionFromFv is 0x%x\n", VmdVariablePtr));
+
+  return EFI_SUCCESS;
+}
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiSaPolicyUpdate.h b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiSaPolicyUpdate.h
new file mode 100644
index 0000000000..c2b24ad5e8
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiSaPolicyUpdate.h
@@ -0,0 +1,47 @@
+/** @file
+
+   Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+   SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+#ifndef _PEI_SA_POLICY_UPDATE_H_
+#define _PEI_SA_POLICY_UPDATE_H_
+
+//
+// External include files do NOT need to be explicitly specified in real EDKII
+// environment
+//
+#include <Ppi/SiPolicy.h>
+#include <Library/DebugPrintErrorLevelLib.h>
+#include <Ppi/Wdt.h>
+#include <CpuRegs.h>
+#include <Library/CpuPlatformLib.h>
+#include "PeiPchPolicyUpdate.h"
+#include <Library/PcdLib.h>
+#include <Library/PciSegmentLib.h>
+#include <Library/SiPolicyLib.h>
+#if FixedPcdGet8(PcdFspModeSelection) == 1
+#include <FspmUpd.h>
+#include <FspsUpd.h>
+#endif
+
+///
+/// DIMM SMBus addresses for Haddock Creek
+///
+
+//
+// Sawtooth Peak
+// Single SPD EEPROM at 0xA2 serves both C0D0 and C1D0 (LPDDR is 1DPC only)
+//
+#define DIMM_SMB_SPD_P0C0D0_STP 0xA2
+#define DIMM_SMB_SPD_P0C0D1_STP 0xA0
+#define DIMM_SMB_SPD_P0C1D0_STP 0xA2
+#define DIMM_SMB_SPD_P0C1D1_STP 0xA0
+
+
+#define WDT_TIMEOUT 60
+
+// BClk Frequency Limitations (in Hz)
+
+#endif
+
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiSaPolicyUpdatePreMem.c b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiSaPolicyUpdatePreMem.c
new file mode 100644
index 0000000000..2c98cbccd4
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiSaPolicyUpdatePreMem.c
@@ -0,0 +1,502 @@
+/** @file
+Do Platform Stage System Agent initialization.
+
+   Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+   SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "PeiSaPolicyUpdate.h"
+#include "MemoryConfig.h"
+#include <Guid/MemoryOverwriteControl.h>
+#include <Guid/MemoryTypeInformation.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/CpuPcieInfoFruLib.h>
+#include <Library/CpuPlatformLib.h>
+#include <Library/GpioLib.h>
+#include <Library/HobLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/PeiSiPolicyUpdateLib.h>
+#include <Library/SiPolicyLib.h>
+#include <Register/CommonMsr.h>
+#include <Register/Cpuid.h>
+#include <Register/Msr.h>
+#include <CpuRegs.h>
+#include <HostBridgeConfig.h>
+#include <Platform.h>
+#include <PlatformBoardConfig.h>
+#include <PolicyUpdateMacro.h>
+#include <SaDataHob.h>
+
+#if FixedPcdGet8(PcdFspModeSelection) == 1
+#include <FspmUpd.h>
+#else
+#include <Ppi/FspmArchConfigPpi.h>
+#endif
+
+
+///
+///
+
+///
+/// Memory Reserved should be between 125% to 150% of the Current required memory
+/// otherwise BdsMisc.c would do a reset to make it 125% to avoid s4 resume issues.
+///
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_MEMORY_TYPE_INFORMATION mDefaultMemoryTypeInformation[] = {
+  { EfiACPIReclaimMemory,   FixedPcdGet32 (PcdPlatformEfiAcpiReclaimMemorySize) },  // ASL
+  { EfiACPIMemoryNVS,       FixedPcdGet32 (PcdPlatformEfiAcpiNvsMemorySize) },      // ACPI NVS (including S3 related)
+  { EfiReservedMemoryType,  FixedPcdGet32 (PcdPlatformEfiReservedMemorySize) },     // BIOS Reserved (including S3 related)
+  { EfiRuntimeServicesData, FixedPcdGet32 (PcdPlatformEfiRtDataMemorySize) },       // Runtime Service Data
+  { EfiRuntimeServicesCode, FixedPcdGet32 (PcdPlatformEfiRtCodeMemorySize) },       // Runtime Service Code
+  { EfiMaxMemoryType, 0 }
+};
+
+
+/**
+  UpdatePeiSaPolicyPreMem performs SA PEI Policy initialization
+
+  @retval EFI_SUCCESS              The policy is installed and initialized.
+**/
+EFI_STATUS
+EFIAPI
+UpdatePeiSaPolicyPreMem (
+  VOID
+  )
+{
+  EFI_STATUS                                      Status;
+
+  EFI_PEI_READ_ONLY_VARIABLE2_PPI                 *VariableServices;
+
+  UINTN                                           VariableSize;
+#if FixedPcdGet8(PcdFspModeSelection) == 0
+  SA_MEMORY_RCOMP                                 *RcompData;
+#endif
+  WDT_PPI                                         *gWdtPei;
+  UINT8                                           WdtTimeout;
+
+  UINT8                                           Index;
+  UINTN                                           DataSize;
+  EFI_MEMORY_TYPE_INFORMATION                     MemoryData[EfiMaxMemoryType + 1];
+  EFI_BOOT_MODE                                   BootMode;
+  UINT8                                           MorControl;
+  UINT64                                          PlatformMemorySize;
+  VOID                                            *MemorySavedData;
+  VOID                                            *NullSpdPtr;
+  UINT32                          RpEnabledMask;
+
+#if FixedPcdGet8(PcdFspModeSelection) == 1
+  VOID                                            *FspmUpd;
+  VOID                                            *MemorySpdPtr000;
+  VOID                                            *MemorySpdPtr010;
+  VOID                                            *MemorySpdPtr020;
+  VOID                                            *MemorySpdPtr030;
+  VOID                                            *MemorySpdPtr100;
+  VOID                                            *MemorySpdPtr110;
+  VOID                                            *MemorySpdPtr120;
+  VOID                                            *MemorySpdPtr130;
+#else
+  SI_PREMEM_POLICY_PPI                            *SiPreMemPolicyPpi;
+  MEMORY_CONFIGURATION                            *MemConfig;
+  SA_MISC_PEI_PREMEM_CONFIG                       *MiscPeiPreMemConfig;
+  MEMORY_CONFIG_NO_CRC                            *MemConfigNoCrc;
+  EFI_PEI_PPI_DESCRIPTOR                          *FspmArchConfigPpiDesc;
+  FSPM_ARCH_CONFIG_PPI                            *FspmArchConfigPpi;
+  HOST_BRIDGE_PREMEM_CONFIG                       *HostBridgePreMemConfig;
+#endif
+  UINT16                                          AdjustedMmioSize;
+  UINT8                                           SaDisplayConfigTable[16];
+  EFI_BOOT_MODE                                   SysBootMode;
+  UINT32                                          ProcessorTraceTotalMemSize;
+  CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX     Ebx;
+  UINT32                                          CapsuleSupportMemSize;
+
+  DEBUG ((DEBUG_INFO, "Update PeiSaPolicyUpdate Pre-Mem Start\n"));
+  ZeroMem ((VOID*) SaDisplayConfigTable, sizeof (SaDisplayConfigTable));
+  WdtTimeout           = 0;
+  SysBootMode          = 0;
+#if FixedPcdGet8(PcdFspModeSelection) == 0
+  RcompData            = NULL;
+#endif
+  PlatformMemorySize   = 0;
+  RpEnabledMask        = 0;
+#if FixedPcdGet8(PcdFspModeSelection) == 1
+  FspmUpd              = NULL;
+  MemorySpdPtr000      = NULL;
+  MemorySpdPtr010      = NULL;
+  MemorySpdPtr020      = NULL;
+  MemorySpdPtr030      = NULL;
+  MemorySpdPtr100      = NULL;
+  MemorySpdPtr110      = NULL;
+  MemorySpdPtr120      = NULL;
+  MemorySpdPtr130      = NULL;
+#else
+  SiPreMemPolicyPpi    = NULL;
+  MemConfig            = NULL;
+  MemConfigNoCrc       = NULL;
+
+
+  MiscPeiPreMemConfig  = NULL;
+  HostBridgePreMemConfig = NULL;
+  FspmArchConfigPpi    = NULL;
+#endif
+
+  ProcessorTraceTotalMemSize = 0;
+  CapsuleSupportMemSize = 0;
+
+  AdjustedMmioSize = PcdGet16 (PcdSaMiscMmioSizeAdjustment);
+
+#if FixedPcdGet8(PcdFspModeSelection) == 1
+  FspmUpd = (FSPM_UPD *) PcdGet32 (PcdFspmUpdDataAddress);
+  ASSERT (FspmUpd != NULL);
+#else
+  Status = PeiServicesLocatePpi (&gSiPreMemPolicyPpiGuid, 0, NULL, (VOID **) &SiPreMemPolicyPpi);
+  ASSERT_EFI_ERROR (Status);
+
+  Status = GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gHostBridgePeiPreMemConfigGuid, (VOID *) &HostBridgePreMemConfig);
+  ASSERT_EFI_ERROR (Status);
+
+  Status = GetConfigBlock((VOID *) SiPreMemPolicyPpi, &gSaMiscPeiPreMemConfigGuid, (VOID *) &MiscPeiPreMemConfig);
+  ASSERT_EFI_ERROR(Status);
+
+  Status = GetConfigBlock((VOID *) SiPreMemPolicyPpi, &gMemoryConfigGuid, (VOID *) &MemConfig);
+  ASSERT_EFI_ERROR(Status);
+
+  Status = GetConfigBlock((VOID *) SiPreMemPolicyPpi, &gMemoryConfigNoCrcGuid, (VOID *) &MemConfigNoCrc);
+  ASSERT_EFI_ERROR(Status);
+
+#endif
+
+#if FixedPcdGet8(PcdFspModeSelection) == 0
+  RcompData = MemConfigNoCrc->RcompData;
+#endif
+
+  //
+  // Locate system configuration variable
+  //
+  Status = PeiServicesLocatePpi(
+             &gEfiPeiReadOnlyVariable2PpiGuid, // GUID
+             0,                                // INSTANCE
+             NULL,                             // EFI_PEI_PPI_DESCRIPTOR
+             (VOID **) &VariableServices       // PPI
+             );
+  ASSERT_EFI_ERROR(Status);
+
+  Status = PeiServicesGetBootMode (&BootMode);
+  ASSERT_EFI_ERROR (Status);
+
+  //
+  // Initialize S3 Data variable (S3DataPtr)
+  //
+  VariableSize = 0;
+  MemorySavedData = NULL;
+  Status = VariableServices->GetVariable (
+                               VariableServices,
+                               L"MemoryConfig",
+                               &gMemoryConfigVariableGuid,
+                               NULL,
+                               &VariableSize,
+                               MemorySavedData
+                               );
+  if (Status == EFI_BUFFER_TOO_SMALL) {
+    MemorySavedData = AllocateZeroPool (VariableSize);
+    ASSERT (MemorySavedData != NULL);
+
+    Status = VariableServices->GetVariable (
+                                 VariableServices,
+                                 L"MemoryConfig",
+                                 &gMemoryConfigVariableGuid,
+                                 NULL,
+                                 &VariableSize,
+                                 MemorySavedData
+                                 );
+    if (EFI_ERROR (Status)) {
+      DEBUG ((DEBUG_ERROR, "Fail to retrieve Variable: MemoryConfig, Status = %r\n", Status));
+      ASSERT_EFI_ERROR (Status);
+    }
+  }
+#if FixedPcdGet8(PcdFspModeSelection) == 0
+  FspmArchConfigPpi = (FSPM_ARCH_CONFIG_PPI *) AllocateZeroPool (sizeof (FSPM_ARCH_CONFIG_PPI));
+  if (FspmArchConfigPpi == NULL) {
+    ASSERT (FALSE);
+    return EFI_OUT_OF_RESOURCES;
+  }
+  FspmArchConfigPpi->Revision     = 1;
+  FspmArchConfigPpi->NvsBufferPtr = MemorySavedData;
+  MiscPeiPreMemConfig->S3DataPtr  = MemorySavedData;
+
+  FspmArchConfigPpiDesc = (EFI_PEI_PPI_DESCRIPTOR *) AllocateZeroPool (sizeof (EFI_PEI_PPI_DESCRIPTOR));
+  if (FspmArchConfigPpiDesc == NULL) {
+    ASSERT (FALSE);
+    return EFI_OUT_OF_RESOURCES;
+  }
+  FspmArchConfigPpiDesc->Flags = EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST;
+  FspmArchConfigPpiDesc->Guid  = &gFspmArchConfigPpiGuid;
+  FspmArchConfigPpiDesc->Ppi   = FspmArchConfigPpi;
+
+  //
+  // Install FSP-M Arch Config PPI
+  //
+  Status = PeiServicesInstallPpi (FspmArchConfigPpiDesc);
+  ASSERT_EFI_ERROR (Status);
+
+#else
+  UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmArchUpd.NvsBufferPtr, MiscPeiPreMemConfig->S3DataPtr, MemorySavedData);
+#endif
+
+  VariableSize = sizeof (MorControl);
+  Status = VariableServices->GetVariable(
+                               VariableServices,
+                               MEMORY_OVERWRITE_REQUEST_VARIABLE_NAME,
+                               &gEfiMemoryOverwriteControlDataGuid,
+                               NULL,
+                               &VariableSize,
+                               &MorControl
+                               );
+  if (EFI_ERROR (Status)) {
+    MorControl = 0;
+  }
+
+  UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.UserBd,     MiscPeiPreMemConfig->UserBd,      0); // It's a CRB mobile board by default (btCRBMB)
+
+#if (FixedPcdGet8(PcdFspModeSelection) == 0)
+  MiscPeiPreMemConfig->TxtImplemented = 0;
+#endif
+
+
+  if (PcdGet32 (PcdMrcRcompTarget)) {
+    COPY_POLICY ((VOID *)((FSPM_UPD *) FspmUpd)->FspmConfig.RcompTarget, (VOID *)RcompData->RcompTarget, (VOID *)(UINTN)PcdGet32 (PcdMrcRcompTarget), sizeof (UINT16) * MRC_MAX_RCOMP_TARGETS);
+  }
+
+  if (PcdGetBool (PcdMrcDqPinsInterleavedControl)) {
+    UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.DqPinsInterleaved, MemConfig->DqPinsInterleaved, PcdGetBool (PcdMrcDqPinsInterleaved));
+  }
+
+  UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.SpdAddressTable[0], MiscPeiPreMemConfig->SpdAddressTable[0], PcdGet8 (PcdMrcSpdAddressTable0));
+  UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.SpdAddressTable[1], MiscPeiPreMemConfig->SpdAddressTable[1], PcdGet8 (PcdMrcSpdAddressTable1));
+  UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.SpdAddressTable[2], MiscPeiPreMemConfig->SpdAddressTable[2], PcdGet8 (PcdMrcSpdAddressTable2));
+  UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.SpdAddressTable[3], MiscPeiPreMemConfig->SpdAddressTable[3], PcdGet8 (PcdMrcSpdAddressTable3));
+  if (PcdGet8 (PcdMrcLp5CccConfig)) {
+    UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.Lp5CccConfig, MemConfig->Lp5CccConfig, PcdGet8 (PcdMrcLp5CccConfig));
+  }
+
+
+  NullSpdPtr = AllocateZeroPool (SPD_DATA_SIZE);
+  ASSERT (NullSpdPtr != NULL);
+
+#if FixedPcdGet8(PcdFspModeSelection) == 1
+  MemorySpdPtr000 = AllocateZeroPool (SPD_DATA_SIZE);
+  ASSERT (MemorySpdPtr000 != NULL);
+  MemorySpdPtr010 = AllocateZeroPool (SPD_DATA_SIZE);
+  ASSERT (MemorySpdPtr010 != NULL);
+  MemorySpdPtr020 = AllocateZeroPool (SPD_DATA_SIZE);
+  ASSERT (MemorySpdPtr020 != NULL);
+  MemorySpdPtr030 = AllocateZeroPool (SPD_DATA_SIZE);
+  ASSERT (MemorySpdPtr030 != NULL);
+  MemorySpdPtr100 = AllocateZeroPool (SPD_DATA_SIZE);
+  ASSERT (MemorySpdPtr100 != NULL);
+  MemorySpdPtr110 = AllocateZeroPool (SPD_DATA_SIZE);
+  ASSERT (MemorySpdPtr110 != NULL);
+  MemorySpdPtr120 = AllocateZeroPool (SPD_DATA_SIZE);
+  ASSERT (MemorySpdPtr120 != NULL);
+  MemorySpdPtr130 = AllocateZeroPool (SPD_DATA_SIZE);
+  ASSERT (MemorySpdPtr130 != NULL);
+  ((FSPM_UPD *) FspmUpd)->FspmConfig.MemorySpdPtr000 = (UINT32) MemorySpdPtr000;
+  ((FSPM_UPD *) FspmUpd)->FspmConfig.MemorySpdPtr010 = (UINT32) MemorySpdPtr010;
+  ((FSPM_UPD *) FspmUpd)->FspmConfig.MemorySpdPtr020 = (UINT32) MemorySpdPtr020;
+  ((FSPM_UPD *) FspmUpd)->FspmConfig.MemorySpdPtr030 = (UINT32) MemorySpdPtr030;
+  ((FSPM_UPD *) FspmUpd)->FspmConfig.MemorySpdPtr100 = (UINT32) MemorySpdPtr100;
+  ((FSPM_UPD *) FspmUpd)->FspmConfig.MemorySpdPtr110 = (UINT32) MemorySpdPtr110;
+  ((FSPM_UPD *) FspmUpd)->FspmConfig.MemorySpdPtr120 = (UINT32) MemorySpdPtr120;
+  ((FSPM_UPD *) FspmUpd)->FspmConfig.MemorySpdPtr130 = (UINT32) MemorySpdPtr130;
+#endif
+  UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.SpdAddressTable[4], MiscPeiPreMemConfig->SpdAddressTable[4], PcdGet8 (PcdMrcSpdAddressTable4));
+  UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.SpdAddressTable[5], MiscPeiPreMemConfig->SpdAddressTable[5], PcdGet8 (PcdMrcSpdAddressTable5));
+  UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.SpdAddressTable[6], MiscPeiPreMemConfig->SpdAddressTable[6], PcdGet8 (PcdMrcSpdAddressTable6));
+  UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.SpdAddressTable[7], MiscPeiPreMemConfig->SpdAddressTable[7], PcdGet8 (PcdMrcSpdAddressTable7));
+  UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.SpdAddressTable[8], MiscPeiPreMemConfig->SpdAddressTable[8], PcdGet8 (PcdMrcSpdAddressTable8));
+  UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.SpdAddressTable[9], MiscPeiPreMemConfig->SpdAddressTable[9], PcdGet8 (PcdMrcSpdAddressTable9));
+  UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.SpdAddressTable[10], MiscPeiPreMemConfig->SpdAddressTable[10], PcdGet8 (PcdMrcSpdAddressTable10));
+  UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.SpdAddressTable[11], MiscPeiPreMemConfig->SpdAddressTable[11], PcdGet8 (PcdMrcSpdAddressTable11));
+  UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.SpdAddressTable[12], MiscPeiPreMemConfig->SpdAddressTable[12], PcdGet8 (PcdMrcSpdAddressTable12));
+  UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.SpdAddressTable[13], MiscPeiPreMemConfig->SpdAddressTable[13], PcdGet8 (PcdMrcSpdAddressTable13));
+  UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.SpdAddressTable[14], MiscPeiPreMemConfig->SpdAddressTable[14], PcdGet8 (PcdMrcSpdAddressTable14));
+  UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.SpdAddressTable[15], MiscPeiPreMemConfig->SpdAddressTable[15], PcdGet8 (PcdMrcSpdAddressTable15));
+  if (PcdGet32 (PcdMrcRcompResistor)) {
+    UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.RcompResistor, RcompData->RcompResistor, (UINT8) PcdGet32 (PcdMrcRcompResistor));
+  }
+  if (PcdGet32 (PcdMrcDqsMapCpu2Dram)) {
+    COPY_POLICY ((VOID *)((FSPM_UPD *) FspmUpd)->FspmConfig.DqsMapCpu2DramMc0Ch0, (VOID *)MemConfigNoCrc->DqDqsMap->DqsMapCpu2Dram, (VOID *)(UINTN)PcdGet32 (PcdMrcDqsMapCpu2Dram), sizeof (UINT8) * MEM_CFG_MAX_CONTROLLERS * MEM_CFG_MAX_CHANNELS * MEM_CFG_NUM_BYTES_MAPPED);
+  }
+  if (PcdGet32 (PcdMrcDqMapCpu2Dram)) {
+    COPY_POLICY ((VOID *)((FSPM_UPD *) FspmUpd)->FspmConfig.DqMapCpu2DramMc0Ch0, (VOID *)MemConfigNoCrc->DqDqsMap->DqMapCpu2Dram, (VOID *)(UINTN)PcdGet32 (PcdMrcDqMapCpu2Dram), sizeof (UINT8) * MEM_CFG_MAX_CONTROLLERS * MEM_CFG_MAX_CHANNELS * MEM_CFG_NUM_BYTES_MAPPED * 8);
+  }
+  if (PcdGetBool (PcdSpdPresent)) {
+    // Clear SPD data so it can be filled in by the MRC init code
+    COPY_POLICY ((VOID *)((FSPM_UPD *) FspmUpd)->FspmConfig.MemorySpdPtr000, (VOID *) MemConfigNoCrc->SpdData->SpdData[0][0][0], (VOID *)(UINT32) NullSpdPtr, SPD_DATA_SIZE);
+    COPY_POLICY ((VOID *)((FSPM_UPD *) FspmUpd)->FspmConfig.MemorySpdPtr010, (VOID *) MemConfigNoCrc->SpdData->SpdData[0][1][0], (VOID *)(UINT32) NullSpdPtr, SPD_DATA_SIZE);
+    COPY_POLICY ((VOID *)((FSPM_UPD *) FspmUpd)->FspmConfig.MemorySpdPtr020, (VOID *) MemConfigNoCrc->SpdData->SpdData[0][2][0], (VOID *)(UINT32) NullSpdPtr, SPD_DATA_SIZE);
+    COPY_POLICY ((VOID *)((FSPM_UPD *) FspmUpd)->FspmConfig.MemorySpdPtr030, (VOID *) MemConfigNoCrc->SpdData->SpdData[0][3][0], (VOID *)(UINT32) NullSpdPtr, SPD_DATA_SIZE);
+    COPY_POLICY ((VOID *)((FSPM_UPD *) FspmUpd)->FspmConfig.MemorySpdPtr100, (VOID *) MemConfigNoCrc->SpdData->SpdData[1][0][0], (VOID *)(UINT32) NullSpdPtr, SPD_DATA_SIZE);
+    COPY_POLICY ((VOID *)((FSPM_UPD *) FspmUpd)->FspmConfig.MemorySpdPtr110, (VOID *) MemConfigNoCrc->SpdData->SpdData[1][1][0], (VOID *)(UINT32) NullSpdPtr, SPD_DATA_SIZE);
+    COPY_POLICY ((VOID *)((FSPM_UPD *) FspmUpd)->FspmConfig.MemorySpdPtr120, (VOID *) MemConfigNoCrc->SpdData->SpdData[1][2][0], (VOID *)(UINT32) NullSpdPtr, SPD_DATA_SIZE);
+    COPY_POLICY ((VOID *)((FSPM_UPD *) FspmUpd)->FspmConfig.MemorySpdPtr130, (VOID *) MemConfigNoCrc->SpdData->SpdData[1][3][0], (VOID *)(UINT32) NullSpdPtr, SPD_DATA_SIZE);
+  } else {
+    if (PcdGet32 (PcdMrcSpdData)) {
+      COPY_POLICY ((VOID *)((FSPM_UPD *) FspmUpd)->FspmConfig.MemorySpdPtr000, (VOID *)MemConfigNoCrc->SpdData->SpdData[0][0][0], (VOID *)(UINTN)PcdGet32 (PcdMrcSpdData), SPD_DATA_SIZE);
+      COPY_POLICY ((VOID *)((FSPM_UPD *) FspmUpd)->FspmConfig.MemorySpdPtr010, (VOID *)MemConfigNoCrc->SpdData->SpdData[0][1][0], (VOID *)(UINTN)PcdGet32 (PcdMrcSpdData), SPD_DATA_SIZE);
+      COPY_POLICY ((VOID *)((FSPM_UPD *) FspmUpd)->FspmConfig.MemorySpdPtr020, (VOID *)MemConfigNoCrc->SpdData->SpdData[0][2][0], (VOID *)(UINTN)PcdGet32 (PcdMrcSpdData), SPD_DATA_SIZE);
+      COPY_POLICY ((VOID *)((FSPM_UPD *) FspmUpd)->FspmConfig.MemorySpdPtr030, (VOID *)MemConfigNoCrc->SpdData->SpdData[0][3][0], (VOID *)(UINTN)PcdGet32 (PcdMrcSpdData), SPD_DATA_SIZE);
+      COPY_POLICY ((VOID *)((FSPM_UPD *) FspmUpd)->FspmConfig.MemorySpdPtr100, (VOID *)MemConfigNoCrc->SpdData->SpdData[1][0][0], (VOID *)(UINTN)PcdGet32 (PcdMrcSpdData), SPD_DATA_SIZE);
+      COPY_POLICY ((VOID *)((FSPM_UPD *) FspmUpd)->FspmConfig.MemorySpdPtr110, (VOID *)MemConfigNoCrc->SpdData->SpdData[1][1][0], (VOID *)(UINTN)PcdGet32 (PcdMrcSpdData), SPD_DATA_SIZE);
+      COPY_POLICY ((VOID *)((FSPM_UPD *) FspmUpd)->FspmConfig.MemorySpdPtr120, (VOID *)MemConfigNoCrc->SpdData->SpdData[1][2][0], (VOID *)(UINTN)PcdGet32 (PcdMrcSpdData), SPD_DATA_SIZE);
+      COPY_POLICY ((VOID *)((FSPM_UPD *) FspmUpd)->FspmConfig.MemorySpdPtr130, (VOID *)MemConfigNoCrc->SpdData->SpdData[1][3][0], (VOID *)(UINTN)PcdGet32 (PcdMrcSpdData), SPD_DATA_SIZE);
+    }
+  }
+
+
+    //
+    // Get the Platform Configuration from SetupData
+    //
+#if FixedPcdGet8(PcdFspModeSelection) == 0
+    HostBridgePreMemConfig->MchBar   = (UINTN) PcdGet64 (PcdMchBaseAddress);
+    HostBridgePreMemConfig->DmiBar   = (UINTN) PcdGet64 (PcdDmiBaseAddress);
+    HostBridgePreMemConfig->EpBar    = (UINTN) PcdGet64 (PcdEpBaseAddress);
+    HostBridgePreMemConfig->EdramBar = (UINTN) PcdGet64 (PcdEdramBaseAddress);
+    MiscPeiPreMemConfig->SmbusBar = (UINTN) PcdGet16 (PcdSmbusBaseAddress);
+#endif
+    UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.TsegSize,           MiscPeiPreMemConfig->TsegSize,           PcdGet32 (PcdTsegSize));
+    UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.UserBd,             MiscPeiPreMemConfig->UserBd,             PcdGet8 (PcdSaMiscUserBd));
+    UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.DisableMrcRetrainingOnRtcPowerLoss,MiscPeiPreMemConfig->DisableMrcRetrainingOnRtcPowerLoss,   PcdGet8(PcdSaMiscDisableMrcRetrainingOnRtcPowerLoss));
+    UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.MmioSizeAdjustment, HostBridgePreMemConfig->MmioSizeAdjustment, PcdGet16 (PcdSaMiscMmioSizeAdjustment));
+
+    //
+    // Display DDI Initialization ( default Native GPIO as per board during AUTO case)
+    //
+    CopyMem (SaDisplayConfigTable, (VOID *) (UINTN) PcdGet32 (PcdSaDisplayConfigTable), (UINTN)PcdGet16 (PcdSaDisplayConfigTableSize));
+
+    //
+    // If user custom profile is selected, we will send the setup values to the MRC.
+    // The setup values will be the current memory settings plus user override values.
+    // If any other profile is selected or a WDT timeout has occured, we zero out
+    // the settings just to be safe.
+    //
+    gWdtPei = NULL;
+    Status = PeiServicesLocatePpi(
+               &gWdtPpiGuid,
+               0,
+               NULL,
+               (VOID **) &gWdtPei
+               );
+    if (gWdtPei != NULL) {
+      WdtTimeout = gWdtPei->CheckStatus();
+    } else {
+      WdtTimeout = FALSE;
+    }
+
+    if ((WdtTimeout == FALSE)) {
+      //
+      // If USER custom profile is selected, we will start the WDT.
+      //
+      if (gWdtPei != NULL) {
+        Status = gWdtPei->ReloadAndStart(WDT_TIMEOUT);
+      }
+      UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.VddVoltage,   MemConfig->VddVoltage,          0); // Use platform default as the safe value.
+      UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.VddqVoltage,  MemConfig->VddqVoltage,         0); // Use platform default as the safe value.
+      UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.VppVoltage,   MemConfig->VppVoltage,          0); // Use platform default as the safe value.
+      UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.Ratio,        MemConfig->Ratio,               0);
+      UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.tCL,          MemConfig->tCL,                 0);
+      UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.tCWL,         MemConfig->tCWL,                0);
+      UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.tFAW,         MemConfig->tFAW,                0);
+      UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.tRAS,         MemConfig->tRAS,                0);
+      UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.tRCDtRP,      MemConfig->tRCDtRP,             0);
+      UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.tREFI,        MemConfig->tREFI,               0);
+      UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.tRFC,         MemConfig->tRFC,                0);
+      UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.tRRD,         MemConfig->tRRD,                0);
+      UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.tRTP,         MemConfig->tRTP,                0);
+      UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.tWR,          MemConfig->tWR,                 0);
+      UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.tWTR,         MemConfig->tWTR,                0);
+      UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.NModeSupport, MemConfig->NModeSupport,        0);
+    }
+
+
+    UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.CmdMirror,                            MemConfig->CmdMirror,             PcdGet8 (PcdMrcCmdMirror)); // BitMask where bits [3:0] are controller 0 Channel [3:0] and [7:4] are Controller 1 Channel [3:0].  0 = No Command Mirror and 1 = Command Mirror.
+
+
+    // FirstDimmBitMask defines which DIMM should be populated first on a 2DPC board
+
+    COMPARE_AND_UPDATE_POLICY(((FSPM_UPD *)FspmUpd)->FspmConfig.FirstDimmBitMask, MemConfig->FirstDimmBitMask, PcdGet8(PcdSaMiscFirstDimmBitMask));
+    COMPARE_AND_UPDATE_POLICY(((FSPM_UPD *)FspmUpd)->FspmConfig.FirstDimmBitMaskEcc, MemConfig->FirstDimmBitMaskEcc, PcdGet8(PcdSaMiscFirstDimmBitMaskEcc));
+
+
+    //
+    // Update CleanMemory variable from Memory overwrite request value. Ignore if we are performing capsule update.
+    //
+    if ((BootMode != BOOT_ON_FLASH_UPDATE) && (BootMode != BOOT_ON_S3_RESUME)) {
+      UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.CleanMemory, MemConfigNoCrc->CleanMemory, (BOOLEAN)(MorControl & MOR_CLEAR_MEMORY_BIT_MASK));
+    }
+  
+  
+
+#if FixedPcdGet8(PcdFspModeSelection) == 0
+  if (BootMode == BOOT_ON_FLASH_UPDATE) {
+    CapsuleSupportMemSize = SIZE_32MB; // Reserve 32M for Capsule update/Recovery usage in PEI
+  }
+#endif
+
+  DataSize = sizeof (MemoryData);
+  Status = VariableServices->GetVariable (
+                               VariableServices,
+                               EFI_MEMORY_TYPE_INFORMATION_VARIABLE_NAME,
+                               &gEfiMemoryTypeInformationGuid,
+                               NULL,
+                               &DataSize,
+                               &MemoryData
+                               );
+  ///
+  /// Accumulate maximum amount of memory needed
+  ///
+#if FixedPcdGet8(PcdFspModeSelection) == 1
+  PlatformMemorySize = ((FSPM_UPD *) FspmUpd)->FspmConfig.PlatformMemorySize;
+#else
+  PlatformMemorySize = MemConfigNoCrc->PlatformMemorySize;
+#endif
+  AsmCpuidEx (CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS, 0, NULL, &Ebx.Uint32, NULL, NULL);
+
+  if (EFI_ERROR (Status)) {
+    if (BootMode == BOOT_IN_RECOVERY_MODE) {
+      PlatformMemorySize = PEI_RECOVERY_MIN_MEMORY_SIZE;
+    } else {
+      ///
+      /// Use default value to avoid memory fragment.
+      /// OS boot/installation fails if there is not enough continuous memory available
+      ///
+      PlatformMemorySize = PEI_MIN_MEMORY_SIZE + ProcessorTraceTotalMemSize + CapsuleSupportMemSize;
+      DataSize = sizeof (mDefaultMemoryTypeInformation);
+      CopyMem (MemoryData, mDefaultMemoryTypeInformation, DataSize);
+    }
+  } else {
+    ///
+    /// Start with at least PEI_MIN_MEMORY_SIZE of memory for the DXE Core and the DXE Stack
+    ///
+    PlatformMemorySize = PEI_MIN_MEMORY_SIZE + ProcessorTraceTotalMemSize + CapsuleSupportMemSize;
+  }
+  UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.PlatformMemorySize, MemConfigNoCrc->PlatformMemorySize, PlatformMemorySize);
+
+  if (BootMode != BOOT_IN_RECOVERY_MODE) {
+    for (Index = 0; Index < DataSize / sizeof (EFI_MEMORY_TYPE_INFORMATION); Index++) {
+      PlatformMemorySize += MemoryData[Index].NumberOfPages * EFI_PAGE_SIZE;
+    }
+    UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.PlatformMemorySize, MemConfigNoCrc->PlatformMemorySize, PlatformMemorySize);
+
+    ///
+    /// Build the GUID'd HOB for DXE
+    ///
+    BuildGuidDataHob (
+      &gEfiMemoryTypeInformationGuid,
+      MemoryData,
+      DataSize
+      );
+  }
+
+  return EFI_SUCCESS;
+}
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiSiPolicyUpdate.c b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiSiPolicyUpdate.c
new file mode 100644
index 0000000000..2fd41e9189
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiSiPolicyUpdate.c
@@ -0,0 +1,114 @@
+/** @file
+  This file is SampleCode of the library for Intel Silicon PEI
+  Platform Policy initialization.
+
+   Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+   SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "PeiSiPolicyUpdate.h"
+#include <Library/DebugLib.h>
+#include <Library/HobLib.h>
+#include <Library/PcdLib.h>
+#include <Library/PeiServicesLib.h>
+#include <Library/PeiSiPolicyUpdateLib.h>
+#include <Library/SiPolicyLib.h>
+#include <Ppi/ReadOnlyVariable2.h>
+
+#include <PciePreMemConfig.h>
+#include <PolicyUpdateMacro.h>
+
+#if FixedPcdGet8(PcdFspModeSelection) == 1
+#include <FspmUpd.h>
+#include <FspsUpd.h>
+#include <Ppi/DebugEventHandler.h>
+#endif
+
+/**
+  This function performs Silicon PEI Policy initialization.
+
+  @retval EFI_SUCCESS             The PPI is installed and initialized.
+  @retval EFI_NOT_FOUND           The FspmUpd is not found.
+  @retval EFI_OUT_OF_RESOURCES    Do not have enough resources to initialize the driver
+**/
+EFI_STATUS
+EFIAPI
+UpdatePeiSiPolicyPreMem (
+  VOID
+  )
+{
+  EFI_STATUS                        Status;
+  SI_PREMEM_POLICY_PPI              *SiPreMemPolicy;
+  SI_PREMEM_CONFIG                  *SiPreMemConfig;
+
+  SiPreMemPolicy = NULL;
+  SiPreMemConfig = NULL;
+
+  DEBUG ((DEBUG_INFO, "Update PeiSiPolicyUpdate Pre-Mem Start\n"));
+
+  Status = PeiServicesLocatePpi (&gSiPreMemPolicyPpiGuid, 0, NULL, (VOID **) &SiPreMemPolicy);
+  ASSERT_EFI_ERROR (Status);
+  Status = GetConfigBlock ((VOID *) SiPreMemPolicy, &gSiPreMemConfigGuid, (VOID *) &SiPreMemConfig);
+  ASSERT_EFI_ERROR (Status);
+
+  //
+  // Policy to prevent MRC modify the boot mode while in flash update
+  //
+  UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.SiSkipOverrideBootModeWhenFwUpdate,  SiPreMemConfig->SkipOverrideBootModeWhenFwUpdate, (UINT8) FALSE);
+
+  return EFI_SUCCESS;
+}
+
+/**
+  This function performs Silicon PEI Policy initialization.
+
+  @retval EFI_SUCCESS  The function completed successfully
+**/
+EFI_STATUS
+EFIAPI
+UpdatePeiSiPolicy (
+  VOID
+  )
+{
+  EFI_STATUS                         Status;
+#if FixedPcdGet8(PcdFspModeSelection) == 1
+  VOID                               *FspsUpd;
+  DEBUG_EVENT_HABDLER_PPI            *DebugEventHandlerPpi;
+#else
+  SI_POLICY_PPI                      *SiPolicyPpi;
+#endif
+
+  DEBUG ((DEBUG_INFO, "Update PeiSiPolicyUpdate Pos-Mem Start\n"));
+
+  Status = EFI_SUCCESS;
+#if FixedPcdGet8(PcdFspModeSelection) == 1
+  FspsUpd = NULL;
+#else
+  SiPolicyPpi     = NULL;
+#endif
+
+#if FixedPcdGet8(PcdFspModeSelection) == 1
+  FspsUpd = (FSPS_UPD *) PcdGet32 (PcdFspsUpdDataAddress);
+  ASSERT (FspsUpd != NULL);
+#else
+  Status = PeiServicesLocatePpi (&gSiPolicyPpiGuid, 0, NULL, (VOID **) &SiPolicyPpi);
+  ASSERT_EFI_ERROR (Status);
+#endif
+
+#if FixedPcdGet8(PcdFspModeSelection) == 1
+  Status = PeiServicesLocatePpi (
+           &gDebugEventHandlerPpiGuid,       // GUID
+           0,                                // INSTANCE
+           NULL,                             // EFI_PEI_PPI_DESCRIPTOR
+           (VOID **) &DebugEventHandlerPpi   // PPI
+           );
+  if (!EFI_ERROR(Status)) {
+    ((FSPS_UPD *) FspsUpd)->FspsConfig.FspEventHandler = (UINT32) DebugEventHandlerPpi->DebugEventHandler;
+  }
+#endif
+
+
+  return EFI_SUCCESS;
+}
+
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiSiPolicyUpdate.h b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiSiPolicyUpdate.h
new file mode 100644
index 0000000000..e7c008a6fa
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiSiPolicyUpdate.h
@@ -0,0 +1,17 @@
+/** @file
+   Header file for PEI SiPolicyUpdate.
+
+   Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+   SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _PEI_SI_POLICY_UPDATE_H_
+#define _PEI_SI_POLICY_UPDATE_H_
+
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/ConfigBlockLib.h>
+#include <Ppi/SiPolicy.h>
+
+#endif
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiSiliconPolicyUpdateLib/PeiCpuPolicy.h b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiSiliconPolicyUpdateLib/PeiCpuPolicy.h
new file mode 100644
index 0000000000..2f5bb13590
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiSiliconPolicyUpdateLib/PeiCpuPolicy.h
@@ -0,0 +1,22 @@
+/** @file
+  Header file for the PeiCpuPolicyInit.
+
+   Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+   SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _PEI_CPU_POLICY_H_
+#define _PEI_CPU_POLICY_H_
+
+#include <PiPei.h>
+#include <Library/DebugLib.h>
+#include <Library/PeiServicesLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/MemoryAllocationLib.h>
+
+#include <Ppi/SiPolicy.h>
+#include <Library/PeiPolicyBoardConfigLib.h>
+#include <Library/PeiSiPolicyUpdateLib.h>
+
+#endif
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiSiliconPolicyUpdateLib/PeiMePolicy.h b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiSiliconPolicyUpdateLib/PeiMePolicy.h
new file mode 100644
index 0000000000..bc61df96fb
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiSiliconPolicyUpdateLib/PeiMePolicy.h
@@ -0,0 +1,21 @@
+/** @file
+  Header file for the PeiMePolicyInit
+
+   Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+   SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+#ifndef _PEI_ME_POLICY_H_
+#define _PEI_ME_POLICY_H_
+
+#include <PiPei.h>
+#include <Library/DebugLib.h>
+#include <Library/PeiServicesLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/MemoryAllocationLib.h>
+
+#include <Ppi/SiPolicy.h>
+#include <Library/PeiPolicyBoardConfigLib.h>
+#include <Library/PeiSiPolicyUpdateLib.h>
+
+#endif // _PEI_ME_POLICY_H_
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiSiliconPolicyUpdateLib/PeiPolicy.h b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiSiliconPolicyUpdateLib/PeiPolicy.h
new file mode 100644
index 0000000000..cceb829dc1
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiSiliconPolicyUpdateLib/PeiPolicy.h
@@ -0,0 +1,21 @@
+/** @file
+  Header file for PeiSiliconPolicyUpdateLib
+
+   Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+   SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+#ifndef _PEI_POLICY_H_
+#define _PEI_POLICY_H_
+
+#include <PiPei.h>
+#include <Library/DebugLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/PcdLib.h>
+
+#include "PeiCpuPolicy.h"
+#include "PeiMePolicy.h"
+#include "PeiSaPolicy.h"
+#include "PeiSiPolicy.h"
+
+#endif
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSaPolicy.h b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSaPolicy.h
new file mode 100644
index 0000000000..19c99de0b9
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSaPolicy.h
@@ -0,0 +1,22 @@
+/** @file
+  Header file for the SaPolicyInitPei PEIM.
+
+   Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+   SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+#ifndef _SA_POLICY_PEI_H_
+#define _SA_POLICY_PEI_H_
+
+#include <PiPei.h>
+#include <Library/DebugLib.h>
+#include <Library/PeiServicesLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/PcdLib.h>
+
+#include <Ppi/SiPolicy.h>
+#include <Library/PeiPolicyBoardConfigLib.h>
+#include <Library/PeiSiPolicyUpdateLib.h>
+
+#endif
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiPolicy.h b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiPolicy.h
new file mode 100644
index 0000000000..31efbf17bf
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiPolicy.h
@@ -0,0 +1,21 @@
+/** @file
+  Header file for the PeiSiPolicyInit
+
+   Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+   SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+#ifndef _SI_POLICY_PEI_H_
+#define _SI_POLICY_PEI_H_
+
+#include <PiPei.h>
+#include <Library/DebugLib.h>
+#include <Library/PeiServicesLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/MemoryAllocationLib.h>
+
+#include <Ppi/SiPolicy.h>
+#include <Library/PeiPolicyBoardConfigLib.h>
+#include <Library/PeiSiPolicyUpdateLib.h>
+
+#endif // _SI_POLICY_PEI_H_
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLate.c b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLate.c
new file mode 100644
index 0000000000..d912222eb9
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLate.c
@@ -0,0 +1,18 @@
+/** @file
+  This file is SampleCode for Intel PEI Platform Policy initialization.
+
+   Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+   SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Base.h>
+
+VOID *
+EFIAPI
+SiliconPolicyUpdateLate (
+  IN OUT VOID *Policy
+  )
+{
+  return NULL;
+}
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf
new file mode 100644
index 0000000000..67b0b324c7
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf
@@ -0,0 +1,67 @@
+## @file
+#  Provide Silicon policy update functionality.
+#
+#   Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+#   SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+###
+
+################################################################################
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+################################################################################
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = SiliconPolicyUpdateLib
+  FILE_GUID                      = 34435831-33D7-4742-992F-3A3C7B860BC5
+  MODULE_TYPE                    = PEIM
+  VERSION_STRING                 = 1.0
+  LIBRARY_CLASS                  = SiliconPolicyUpdateLib
+
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+#  VALID_ARCHITECTURES           = IA32 X64
+#
+
+################################################################################
+#
+# Sources Section - list of files that are required for the build to succeed.
+#
+################################################################################
+
+[Sources]
+  PeiSiliconPolicyUpdatePreMem.c
+  PeiSiliconPolicyUpdatePostMem.c
+  PeiSiliconPolicyUpdateLate.c
+
+################################################################################
+#
+# Package Dependency Section - list of Package files that are required for
+#                              this module.
+#
+################################################################################
+
+[Packages]
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  AlderlakeSiliconPkg/SiPkg.dec
+  AlderlakeOpenBoardPkg/OpenBoardPkg.dec
+
+[LibraryClasses.IA32]
+  BaseMemoryLib
+  BaseLib
+  DebugLib
+  PeiServicesTablePointerLib
+  PeiServicesLib
+  PcdLib
+  PeiPolicyBoardConfigLib
+  PeiPolicyUpdateLib
+
+[FixedPcd]
+
+[Ppis]
+
+[Guids]
\ No newline at end of file
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdatePostMem.c b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdatePostMem.c
new file mode 100644
index 0000000000..9a91ea7fe1
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdatePostMem.c
@@ -0,0 +1,53 @@
+/** @file
+  This file is SampleCode for Intel PEI Platform Policy initialization in post-memory.
+
+   Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+   SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "PeiPolicy.h"
+#include <Library/PeiSiPolicyUpdateLib.h>
+
+#include <Ppi/ReadOnlyVariable2.h>
+
+#include <Library/PeiServicesLib.h>
+#include <Library/PeiServicesTablePointerLib.h>
+VOID
+EFIAPI
+SiliconPolicyUpdatePostMemFirmwareConfig (
+  VOID
+  )
+{
+    //
+    // Update and override all platform related and customized settings below.
+    //
+    UpdatePeiSiPolicy ();
+    UpdatePeiPchPolicy ();
+    UpdatePeiSaPolicy ();
+    UpdatePeiCpuPolicy ();
+    UpdatePeiMePolicy ();
+
+
+
+}
+
+VOID *
+EFIAPI
+SiliconPolicyUpdatePostMem (
+  IN OUT VOID *Policy
+  )
+{
+  Policy = NULL;
+  //
+  // Update policy by board configuration
+  //
+  UpdatePeiSiPolicyBoardConfig ();
+  UpdatePeiSaPolicyBoardConfig ();
+  UpdatePeiMePolicyBoardConfig ();
+
+  // @todo separate out the advanced policy update process from this module.
+  SiliconPolicyUpdatePostMemFirmwareConfig ();
+
+  return Policy;
+}
diff --git a/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdatePreMem.c b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdatePreMem.c
new file mode 100644
index 0000000000..a56118ffa6
--- /dev/null
+++ b/Platform/Intel/AlderlakeOpenBoardPkg/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdatePreMem.c
@@ -0,0 +1,49 @@
+/** @file
+  This file is SampleCode for Intel PEI Platform Policy initialization in pre-memory.
+
+   Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+   SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "PeiPolicy.h"
+#include <Library/PeiSiPolicyUpdateLib.h>
+#include <Ppi/ReadOnlyVariable2.h>
+#include <Library/PeiServicesLib.h>
+#include <Library/PeiServicesTablePointerLib.h>
+
+VOID
+EFIAPI
+SiliconPolicyUpdatePreMemFirmwareConfig (
+  VOID
+  )
+{
+    UpdatePeiSiPolicyPreMem ();
+    UpdatePeiPchPolicyPreMem ();
+    UpdatePeiMePolicyPreMem ();
+    UpdatePeiSaPolicyPreMem ();
+    UpdatePeiCpuPolicyPreMem ();
+
+}
+
+
+VOID *
+EFIAPI
+SiliconPolicyUpdatePreMem (
+  IN OUT VOID *Policy
+  )
+{
+  Policy = NULL;
+  //
+  // Update policy by board configuration
+  //
+  UpdatePeiPchPolicyBoardConfigPreMem ();
+  UpdatePeiMePolicyBoardConfigPreMem ();
+  UpdatePeiSaPolicyBoardConfigPreMem ();
+  UpdatePeiCpuPolicyBoardConfigPreMem ();
+
+  // @todo separate out the advanced policy update process from this module.
+  SiliconPolicyUpdatePreMemFirmwareConfig ();
+
+  return Policy;
+}
-- 
2.36.1.windows.1


  parent reply	other threads:[~2023-06-14 19:17 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
     [not found] <cover.1686770061.git.saloni.kasbekar@intel.com>
2023-06-14 19:17 ` [PATCH 1/6] AlderlakeOpenBoardPkg: Add package and headers Saloni Kasbekar
2023-06-14 19:17 ` [PATCH 2/6] AlderlakeOpenBoardPkg: Add modules Saloni Kasbekar
2023-06-14 19:17 ` [PATCH 3/6] AlderlakeOpenBoardPkg/AlderlakePRvp: Add library instances Saloni Kasbekar
2023-06-14 19:17 ` [PATCH 4/6] AlderlakeOpenBoardPkg: Add ACPI module Saloni Kasbekar
2023-06-14 19:17 ` Saloni Kasbekar [this message]
2023-06-14 19:17 ` [PATCH 6/6] AlderlakeOpenBoardPkg: Add Library Instances Saloni Kasbekar

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-list from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=f4096ae9848aced854fc8b206976e9f8f7506ee4.1686770061.git.saloni.kasbekar@intel.com \
    --to=devel@edk2.groups.io \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox