From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=216.228.121.64; helo=hqemgate15.nvidia.com; envelope-from=jbrasen@nvidia.com; receiver=edk2-devel@lists.01.org Received: from hqemgate15.nvidia.com (hqemgate15.nvidia.com [216.228.121.64]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id E4F4E2008319E for ; Tue, 19 Feb 2019 09:07:14 -0800 (PST) Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 19 Feb 2019 09:07:13 -0800 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Tue, 19 Feb 2019 09:07:14 -0800 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Tue, 19 Feb 2019 09:07:14 -0800 Received: from HQMAIL103.nvidia.com (172.20.187.11) by HQMAIL108.nvidia.com (172.18.146.13) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Tue, 19 Feb 2019 17:07:13 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL103.nvidia.com (172.20.187.11) with Microsoft SMTP Server (TLS) id 15.0.1395.4 via Frontend Transport; Tue, 19 Feb 2019 17:07:13 +0000 Received: from jbrasen-ux.nvidia.com (Not Verified[10.28.48.113]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Tue, 19 Feb 2019 09:07:13 -0800 From: Jeff Brasen To: CC: Edgar Handal , Jeff Brasen , Hao A Wu Date: Tue, 19 Feb 2019 10:06:56 -0700 Message-ID: X-Mailer: git-send-email 2.7.4 X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1550596033; bh=0d1YhZBIPjlqTBNLpSZwkjKSP5Qy+vpX+GDPXG+DLgk=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: X-NVConfidentiality:MIME-Version:Content-Type; b=cy9Aj18W9dCNgbLxYPHCL7p+wbNTBg0Q8IN03EaPvTiJAD2vRweZwwJOVdAoymoTx 2ECxsgaHAKJ3mLgoLTUA+JbjtVACG1sZzhKGTd4en1v/5w+5XX238oYce3QIHKUtzb bLkcLSTKs9aREM3DU/3jmjb42+iDKke/qRvqdKF43gKtNcXpCjP6qlkMtZOjZI2Ppb 5Yjh8B2DuRC+dLjOyMIzhfOLV3sgcrJT4zxoxNIOP41rtvKJKVeflaIEdnmaXIp9vm /xog0dhDKz3KS0jwr2mj1aQW5utbjDYl9W2lUAVkU/zl+kgCXLMBOCHoDvDNi306f+ dp4dUWLEkHuLw== Subject: [PATCH v2] MdeModulePkg/SdMmcPciHcDxe: Use 16/32-bit IO widths X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 19 Feb 2019 17:07:15 -0000 Content-Type: text/plain From: Edgar Handal REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1537 Use 16-bit and 32-bit IO widths for SDMMC MMIO to prevent all register accesses from being split up into 8-bit accesses. The SDHCI specification states that the registers shall be accessible in byte, word, and double word accesses. (SD Host Controller Simplified Specification 4.20 Section 1.2) Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jeff Brasen Cc: Hao A Wu --- MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c | 25 ++++++++++++++++++++---- 1 file changed, 21 insertions(+), 4 deletions(-) diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c index 4c64da3..d73fa10 100644 --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c @@ -154,19 +154,36 @@ SdMmcHcRwMmio ( ) { EFI_STATUS Status; + EFI_PCI_IO_PROTOCOL_WIDTH Width; if ((PciIo == NULL) || (Data == NULL)) { return EFI_INVALID_PARAMETER; } - if ((Count != 1) && (Count != 2) && (Count != 4) && (Count != 8)) { - return EFI_INVALID_PARAMETER; + switch (Count) { + case 1: + Width = EfiPciIoWidthUint8; + break; + case 2: + Width = EfiPciIoWidthUint16; + Count = 1; + break; + case 4: + Width = EfiPciIoWidthUint32; + Count = 1; + break; + case 8: + Width = EfiPciIoWidthUint32; + Count = 2; + break; + default: + return EFI_INVALID_PARAMETER; } if (Read) { Status = PciIo->Mem.Read ( PciIo, - EfiPciIoWidthUint8, + Width, BarIndex, (UINT64) Offset, Count, @@ -175,7 +192,7 @@ SdMmcHcRwMmio ( } else { Status = PciIo->Mem.Write ( PciIo, - EfiPciIoWidthUint8, + Width, BarIndex, (UINT64) Offset, Count, -- 2.7.4