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contact devel+owner@edk2.groups.io Resent-Date: Wed, 01 May 2024 12:32:02 -0700 Resent-From: hong-chih.hsueh@amd.com Reply-To: devel@edk2.groups.io,hong-chih.hsueh@amd.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: iIRbvseH2OmQZLBgdi8iR6Rpx7686176AA= Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20240206 header.b="IPbSe/h+"; dmarc=pass (policy=none) header.from=groups.io; spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 45.79.224.7 as permitted sender) smtp.mailfrom=bounce@groups.io Cc: Jiangang He Signed-off-by: Neo Hsueh --- MdePkg/Include/Register/Amd/Cpuid.h | 4 ++-- MdePkg/Include/Register/Intel/ArchitecturalMsr.h | 8 ++++---- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/MdePkg/Include/Register/Amd/Cpuid.h b/MdePkg/Include/Register/= Amd/Cpuid.h index add43c40aa..51fa9f235c 100644 --- a/MdePkg/Include/Register/Amd/Cpuid.h +++ b/MdePkg/Include/Register/Amd/Cpuid.h @@ -46,9 +46,9 @@ CPUID Signature Information CPUID Extended Topology Enumeration =20 @note - Reference: AMD64 Architecture Programmer=E2=80=99s Manual Volume 3: Gene= ral-Purpose and System Instructions, + Reference: AMD64 Architecture Programmer's Manual Volume 3: General-Purp= ose and System Instructions, Revision 3.35 Appendix E, - E.4.24 Function 8000_0026=E2=80=94Extended CPU Topology: + E.4.24 Function 8000_0026-Extended CPU Topology: CPUID Fn8000_0026 reports extended topology information for logical pr= ocessors, including asymmetric and heterogenous topology descriptions. Individual logical = processors may report different values in systems with asynchronous and heterogeneous topolo= gies. diff --git a/MdePkg/Include/Register/Intel/ArchitecturalMsr.h b/MdePkg/Incl= ude/Register/Intel/ArchitecturalMsr.h index 756e7c86ec..4715c59dc4 100644 --- a/MdePkg/Include/Register/Intel/ArchitecturalMsr.h +++ b/MdePkg/Include/Register/Intel/ArchitecturalMsr.h @@ -5733,9 +5733,9 @@ typedef union { /// [Bit 7:4] TME Policy/Encryption Algorithm: Only algorithms enumera= ted in /// IA32_TME_CAPABILITY are allowed. /// For example: - /// 0000 =E2=80=93 AES-XTS-128. - /// 0001 =E2=80=93 AES-XTS-128 with integrity. - /// 0010 =E2=80=93 AES-XTS-256. + /// 0000 - AES-XTS-128. + /// 0001 - AES-XTS-128 with integrity. + /// 0010 - AES-XTS-256. /// Other values are invalid. /// UINT32 TmePolicy : 4; @@ -5756,7 +5756,7 @@ typedef union { /// Similar to enumeration, this is an encoded value. /// Writing a value greater than MK_TME_MAX_KEYID_BITS will result in = #GP. /// Writing a non-zero value to this field will #GP if bit 1 of EAX (H= ardware - /// Encryption Enable) is not also set to =E2=80=981, as encryption ha= rdware must be + /// Encryption Enable) is not also set to 1, as encryption hardware mu= st be /// enabled to use MKTME. /// Example: To support 255 keys, this field would be set to a value o= f 8. /// --=20 2.40.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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