From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mx.groups.io with SMTP id smtpd.web11.9858.1590139910633820535 for ; Fri, 22 May 2020 02:31:50 -0700 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: arm.com, ip: 217.140.110.172, mailfrom: ard.biesheuvel@arm.com) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 21A8731B; Fri, 22 May 2020 02:31:50 -0700 (PDT) Received: from [192.168.1.81] (unknown [10.37.8.250]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 3BD0A3F305; Fri, 22 May 2020 02:31:47 -0700 (PDT) Subject: Re: [PATCH edk2-platforms 08/16] Silicon/NXP: PciHostBridgeLib: Dump Layerscale iATU windows To: Wasim Khan , devel@edk2.groups.io, meenakshi.aggarwal@nxp.com, vabhav.sharma@nxp.com, V.Sethi@nxp.com, leif@nuviainc.com, jon@solid-run.com Cc: Wasim Khan References: <1590102139-16588-1-git-send-email-wasim.khan@oss.nxp.com> <1590102139-16588-9-git-send-email-wasim.khan@oss.nxp.com> From: "Ard Biesheuvel" Message-ID: Date: Fri, 22 May 2020 11:31:42 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.7.0 MIME-Version: 1.0 In-Reply-To: <1590102139-16588-9-git-send-email-wasim.khan@oss.nxp.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit On 5/22/20 1:02 AM, Wasim Khan wrote: > From: Wasim Khan > > Dump ATU windows for PCIe Layerscape controller if PcdPciDebug > is enabled. > > Signed-off-by: Wasim Khan > --- > .../Library/PciHostBridgeLib/PciHostBridgeLib.c | 42 ++++++++++++++++++++++ > 1 file changed, 42 insertions(+) > > diff --git a/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c b/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c > index 1de20c621dc0..3ad526218bcf 100644 > --- a/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c > +++ b/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c > @@ -297,6 +297,44 @@ PcieOutboundSet ( > } > > /** > + Dump PCIe Layerscape ATU > + > + @param Pcie Address of PCIe host controller. > +**/ > +VOID LsDumpAtu ( > + IN EFI_PHYSICAL_ADDRESS Pcie > + ) > +{ > + UINT32 Cnt; > + for (Cnt = 0; Cnt <= IATU_REGION_INDEX7; Cnt++) { > + MmioWrite32 ((UINTN)Pcie + IATU_VIEWPORT_OFF, > + (UINT32)(IATU_VIEWPORT_OUTBOUND | Cnt)); > + > + DEBUG ((DEBUG_INFO, "iATU%d:\n",Cnt)); > + DEBUG ((DEBUG_INFO, "\tLOWER PHYS 0x%08x\n", > + MmioRead32 ((UINTN)Pcie + IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0))); > + > + DEBUG ((DEBUG_INFO, "\tUPPER PHYS 0x%08x\n", > + MmioRead32 ((UINTN)Pcie + IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0))); > + > + DEBUG ((DEBUG_INFO, "\tLOWER BUS 0x%08x\n", > + MmioRead32 ((UINTN)Pcie + IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0))); > + > + DEBUG ((DEBUG_INFO, "\tUPPER BUS 0x%08x\n", > + MmioRead32 ((UINTN)Pcie + IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0))); > + > + DEBUG ((DEBUG_INFO, "\tLIMIT 0x%08x\n", > + MmioRead32 ((UINTN)Pcie + IATU_LIMIT_ADDR_OFF_OUTBOUND_0))); > + > + DEBUG ((DEBUG_INFO, "\tCR1 0x%08x\n", > + MmioRead32 ((UINTN)Pcie + IATU_REGION_CTRL_1_OFF_OUTBOUND_0))); > + > + DEBUG ((DEBUG_INFO, "\tCR2 0x%08x\n", > + MmioRead32 ((UINTN)Pcie + IATU_REGION_CTRL_2_OFF_OUTBOUND_0))); > + } > +} > + > +/** > Function to set-up iATU windows for Layerscape PCIe controller > > @param Pcie Address of PCIe host controller > @@ -410,6 +448,10 @@ PcieLsSetupAtu ( > SEG_IO_BUS, > SEG_IO_SIZE > ); > + > + if (FixedPcdGetBool (PcdPciDebug) == TRUE) { > + LsDumpAtu (Pcie); > + } > } > > /* We already have DEBUG vs RELEASE builds, and various debug levels. Please don't add your own DEBUG PCDs on top of that. Instead, if you need code to only be executed in DEBUG builds (like the MmioWrite() above), use DEBUG_CODE_BEGIN/END