From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mx1.redhat.com (mx1.redhat.com [209.132.183.28]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id A588381CCC for ; Fri, 4 Nov 2016 15:40:02 -0700 (PDT) Received: from int-mx14.intmail.prod.int.phx2.redhat.com (int-mx14.intmail.prod.int.phx2.redhat.com [10.5.11.27]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 7F0663D94B; Fri, 4 Nov 2016 22:40:04 +0000 (UTC) Received: from lacos-laptop-7.usersys.redhat.com (ovpn-116-156.phx2.redhat.com [10.3.116.156]) by int-mx14.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with ESMTP id uA4Me2Qo011441; Fri, 4 Nov 2016 18:40:02 -0400 To: Jiewen Yao , edk2-devel@ml01.01.org References: <1478251854-14660-1-git-send-email-jiewen.yao@intel.com> Cc: Michael D Kinney , Feng Tian , Jeff Fan , Star Zeng From: Laszlo Ersek Message-ID: Date: Fri, 4 Nov 2016 23:40:01 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.4.0 MIME-Version: 1.0 In-Reply-To: <1478251854-14660-1-git-send-email-jiewen.yao@intel.com> X-Scanned-By: MIMEDefang 2.68 on 10.5.11.27 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.30]); Fri, 04 Nov 2016 22:40:04 +0000 (UTC) Subject: Re: [PATCH V2 0/6] Enable SMM page level protection. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 04 Nov 2016 22:40:02 -0000 Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit On 11/04/16 10:30, Jiewen Yao wrote: > ==== below is V2 description ==== > 1) PiSmmCpu: resolve OVMF multiple processors boot hang issue. > 2) PiSmmCpu: Add debug info on StartupAp() fails. > 3) PiSmmCpu: Add ASSERT for AllocatePages(). > 4) PiSmmCpu: Add protection detail in commit message. > 5) UefiCpuPkg.dsc: Add page table footprint info in commit message. Jiewen, can you please push this series to a new branch in your repo? I see a branch called "SmmProtection_V2", but it seems to end with an incomplete patch (26f482d8b611d0fcb07d3ffbf3f4468fd249767b, subject "pismmcpu"), so I figured I'd ask explicitly. Thanks Laszlo > ==== below is V1 description ==== > This series patch enables SMM page level protection. > Features are: > 1) PiSmmCore reports SMM PE image code/data information > in EdkiiPiSmmMemoryAttributeTable, if the SMM image is page aligned. > 2) PiSmmCpu consumes EdkiiPiSmmMemoryAttributeTable > and set XD for data page and RO for code page. > 3) PiSmmCpu enables Static Paging for X64 according to > PcdCpuSmmStaticPageTable. If it is true, 1G paging for above 4G > is used as long as it is supported. > 4) PiSmmCpu sets importance data structure to be read only, > such as Gdt, Idt, SmmEntrypoint, and PageTable itself. > > tested platform: > 1) Intel internal platform (X64). > 2) EDKII Quark IA32 > 3) EDKII Vlv2 X64 > 4) EDKII OVMF IA32 and IA32X64. (with -smp 8) > > Cc: Jeff Fan > Cc: Feng Tian > Cc: Star Zeng > Cc: Michael D Kinney > Cc: Laszlo Ersek > Contributed-under: TianoCore Contribution Agreement 1.0 > Signed-off-by: Jiewen Yao > > Jiewen Yao (6): > MdeModulePkg/Include: Add PiSmmMemoryAttributesTable.h > MdeModulePkg/dec: Add gEdkiiPiSmmMemoryAttributesTableGuid. > MdeModulePkg/PiSmmCore: Add MemoryAttributes support. > UefiCpuPkg/dec: Add PcdCpuSmmStaticPageTable. > UefiCpuPkg/PiSmmCpuDxeSmm: Add paging protection. > QuarkPlatformPkg/dsc: enable Smm paging protection. > > MdeModulePkg/Core/PiSmmCore/Dispatcher.c | 66 + > MdeModulePkg/Core/PiSmmCore/MemoryAttributesTable.c | 1509 ++++++++++++++++++++ > MdeModulePkg/Core/PiSmmCore/Page.c | 775 +++++++++- > MdeModulePkg/Core/PiSmmCore/PiSmmCore.c | 40 + > MdeModulePkg/Core/PiSmmCore/PiSmmCore.h | 91 ++ > MdeModulePkg/Core/PiSmmCore/PiSmmCore.inf | 2 + > MdeModulePkg/Core/PiSmmCore/Pool.c | 16 + > MdeModulePkg/Include/Guid/PiSmmMemoryAttributesTable.h | 51 + > MdeModulePkg/MdeModulePkg.dec | 3 + > QuarkPlatformPkg/Quark.dsc | 6 + > UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/PageTbl.c | 71 +- > UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.S | 67 +- > UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.asm | 68 +- > UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm | 70 +- > UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiException.S | 226 +-- > UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiException.asm | 36 +- > UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiException.nasm | 36 +- > UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmFuncsArch.c | 37 +- > UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmProfileArch.c | 4 +- > UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c | 127 +- > UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c | 142 +- > UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h | 156 +- > UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf | 5 +- > UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c | 871 +++++++++++ > UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c | 39 +- > UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.h | 15 +- > UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c | 274 +++- > UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.S | 51 +- > UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.asm | 54 +- > UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm | 61 +- > UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiException.S | 250 +--- > UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiException.asm | 35 +- > UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiException.nasm | 31 +- > UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmFuncsArch.c | 30 +- > UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmProfileArch.c | 7 +- > UefiCpuPkg/UefiCpuPkg.dec | 8 + > 36 files changed, 4529 insertions(+), 801 deletions(-) > create mode 100644 MdeModulePkg/Core/PiSmmCore/MemoryAttributesTable.c > create mode 100644 MdeModulePkg/Include/Guid/PiSmmMemoryAttributesTable.h > create mode 100644 UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c >