From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by mx.groups.io with SMTP id smtpd.web10.25470.1686851593481588403 for ; Thu, 15 Jun 2023 10:53:15 -0700 Authentication-Results: mx.groups.io; dkim=fail reason="unable to parse pub key" header.i=@intel.com header.s=intel header.b=IpNVb0tD; spf=pass (domain: intel.com, ip: 134.134.136.126, mailfrom: saloni.kasbekar@intel.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1686851595; x=1718387595; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=RVvT1StQFwIR7V90Y8sa534mZ+eUB4XVTEsG5LzXhec=; b=IpNVb0tDeMzycWKm4vBuLvYC2bDt2mG/Xm4y7tqxZsLp0nKZN0KV128m ekE+p1Y3s3PL/eXymyL0VA8s9MGAd5Zqu8uX8jSGPUQiMSsbMpQO8oW+O ATYFJbvcJkTs+iiVxZynnClxbRASSL9vwOET1iXGhMIRK587ObkrEzabo 27vEO/3WvUko4H2jpPE5E0UlnfqMrv3bPhQ8js9UVE86bn/tfAOYLziol eu/Ybizgv4OdPXG3aLmE9O9epQfKXTpXmY7KaKkTFi8DBcGYA5Bv+1LCY 4kXKrT0ftqIvZk15fK9u8l9C+WCUrwwQjNS1MLyrG0Bi4akuyfoj14m3H g==; X-IronPort-AV: E=McAfee;i="6600,9927,10742"; a="343732732" X-IronPort-AV: E=Sophos;i="6.00,245,1681196400"; d="scan'208";a="343732732" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Jun 2023 10:53:14 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10742"; a="857053643" X-IronPort-AV: E=Sophos;i="6.00,245,1681196400"; d="scan'208";a="857053643" Received: from fmbiosdev02.amr.corp.intel.com ([10.105.221.44]) by fmsmga001-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Jun 2023 10:53:14 -0700 From: "Saloni Kasbekar" To: devel@edk2.groups.io Cc: Saloni Kasbekar , Sai Chaganty , Nate DeSimone , Isaac Oram , Rosen Chuang Subject: [PATCH 3/8] AlderlakeSiliconPkg/Pch: Add include headers Date: Thu, 15 Jun 2023 10:53:01 -0700 Message-Id: X-Mailer: git-send-email 2.36.1.windows.1 In-Reply-To: <6b58dd187980204b74c6ec718dad122674c213e1.1686851565.git.saloni.kasbekar@intel.com> References: <6b58dd187980204b74c6ec718dad122674c213e1.1686851565.git.saloni.kasbekar@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Adds the following header files: * Pch/Include Cc: Sai Chaganty Cc: Nate DeSimone Cc: Isaac Oram Cc: Rosen Chuang Signed-off-by: Saloni Kasbekar --- .../Include/ConfigBlock/PchGeneralConfig.h | 86 ++++++++ .../Pch/Include/Library/PchCycleDecodingLib.h | 59 ++++++ .../Pch/Include/Library/PchInfoDefs.h | 19 ++ .../Pch/Include/Library/PchInfoLib.h | 108 ++++++++++ .../Pch/Include/Library/PchPciBdfLib.h | 187 ++++++++++++++++++ .../Pch/Include/PchPolicyCommon.h | 30 +++ .../Pch/Include/PchPreMemPolicyCommon.h | 53 +++++ .../Pch/Include/PchResetPlatformSpecific.h | 21 ++ .../Pch/Include/Protocol/PchAcpiSmiDispatch.h | 134 +++++++++++++ .../Pch/Include/Protocol/PchPcieSmiDispatch.h | 166 ++++++++++++++++ .../Pch/Include/Protocol/PchSmiDispatch.h | 132 +++++++++++++ .../Include/Protocol/PchSmmIoTrapControl.h | 65 ++++++ .../Protocol/PchSmmPeriodicTimerControl.h | 65 ++++++ .../Pch/Include/Protocol/PchTcoSmiDispatch.h | 150 ++++++++++++++ .../Pch/Include/Protocol/SmmSmbus.h | 13 ++ .../Pch/Include/Register/PchRegs.h | 45 +++++ 16 files changed, 1333 insertions(+) create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Pch/Include/ConfigBlock/PchGeneralConfig.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Pch/Include/Library/PchCycleDecodingLib.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Pch/Include/Library/PchInfoDefs.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Pch/Include/Library/PchInfoLib.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Pch/Include/Library/PchPciBdfLib.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Pch/Include/PchPolicyCommon.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Pch/Include/PchPreMemPolicyCommon.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Pch/Include/PchResetPlatformSpecific.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Pch/Include/Protocol/PchAcpiSmiDispatch.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Pch/Include/Protocol/PchPcieSmiDispatch.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Pch/Include/Protocol/PchSmiDispatch.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Pch/Include/Protocol/PchSmmIoTrapControl.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Pch/Include/Protocol/PchSmmPeriodicTimerControl.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Pch/Include/Protocol/PchTcoSmiDispatch.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Pch/Include/Protocol/SmmSmbus.h create mode 100644 Silicon/Intel/AlderlakeSiliconPkg/Pch/Include/Register/PchRegs.h diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Pch/Include/ConfigBlock/PchGeneralConfig.h b/Silicon/Intel/AlderlakeSiliconPkg/Pch/Include/ConfigBlock/PchGeneralConfig.h new file mode 100644 index 0000000000..4501537fe2 --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/Pch/Include/ConfigBlock/PchGeneralConfig.h @@ -0,0 +1,86 @@ +/** @file + PCH General policy + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _PCH_GENERAL_CONFIG_H_ +#define _PCH_GENERAL_CONFIG_H_ + + +extern EFI_GUID gPchGeneralConfigGuid; +extern EFI_GUID gPchGeneralPreMemConfigGuid; + +#pragma pack (push,1) + +enum PCH_RESERVED_PAGE_ROUTE { + PchReservedPageToLpc, ///< Port 80h cycles are sent to LPC. + PchReservedPageToPcie ///< Port 80h cycles are sent to PCIe. +}; + +/** + PCH General Configuration + Revision 1: - Initial version. + Revision 2: - Added AcpiL6dPmeHandling +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Config Block Header + /** + This member describes whether or not the Compatibility Revision ID (CRID) feature + of PCH should be enabled. 0: Disable; 1: Enable + **/ + UINT32 Crid : 1; + /** + Set to enable low latency of legacy IO. + Some systems require lower IO latency irrespective of power. + This is a tradeoff between power and IO latency. + @note: Once this is enabled, DmiAspm, Pcie DmiAspm in SystemAgent + and ITSS Clock Gating are forced to disabled. + 0: Disable, 1: Enable + **/ + UINT32 LegacyIoLowLatency : 1; + /** + Enables _L6D ACPI handler. + PME GPE is shared by multiple devices So BIOS must verify the same in the ASL handler by reading offset for PMEENABLE and PMESTATUS bit + 0: Disable, 1: Enable + **/ + UINT32 AcpiL6dPmeHandling : 1; + UINT32 RsvdBits0 : 29; ///< Reserved bits +} PCH_GENERAL_CONFIG; + +/** + PCH General Pre-Memory Configuration + Revision 1: - Initial version. + Revision 2: - Added GpioOverride. + Revision 3: - Added IoeDebugEn, PmodeClkEn +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Config Block Header + /** + Control where the Port 80h cycles are sent, 0: LPC; 1: PCI. + **/ + UINT32 Port80Route : 1; + UINT32 IotgPllSscEn : 1; ///< Need to disable CPU Side SSC for A0 PO + /** + Gpio override Level + -- 0: Disable; + - 1: Override Level 1 - Skips GPIO configuration in PEI/FSPM/FSPT phase + - 2: Override Level 2 - Reserved for future use + **/ + UINT32 GpioOverride : 3; + /** + Enable/Disable IOE Debug. When enabled, IOE D2D Dfx link and clock will keep up for debug + 0: Disable; 1: Enable + **/ + UINT32 IoeDebugEn : 1; + /** + Enable/Disable PMODE clock. When enabled, Pmode clock will toggle for XDP use + 0: Disable; 1: Enable + **/ + UINT32 PmodeClkEn : 1; + UINT32 RsvdBits0 : 25; ///< Reserved bits +} PCH_GENERAL_PREMEM_CONFIG; + +#pragma pack (pop) + +#endif // _PCH_GENERAL_CONFIG_H_ diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Pch/Include/Library/PchCycleDecodingLib.h b/Silicon/Intel/AlderlakeSiliconPkg/Pch/Include/Library/PchCycleDecodingLib.h new file mode 100644 index 0000000000..65ecd58de1 --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/Pch/Include/Library/PchCycleDecodingLib.h @@ -0,0 +1,59 @@ +/** @file + Header file for PchCycleDecodingLib. + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _PCH_CYCLE_DECODING_LIB_H_ +#define _PCH_CYCLE_DECODING_LIB_H_ + +/** + Get PCH TCO base address. + + @param[out] Address Address of TCO base address. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid pointer passed. +**/ +EFI_STATUS +PchTcoBaseGet ( + OUT UINT16 *Address + ); + +/** + Set PCH LPC IO decode ranges. + Program LPC I/O Decode Ranges, PCR[DMI] + 2770h[15:0] to the same value programmed in LPC offset 80h. + Please check EDS for detail of Lpc IO decode ranges bit definition. + Bit 12: FDD range + Bit 9:8: LPT range + Bit 6:4: ComB range + Bit 2:0: ComA range + + @param[in] LpcIoDecodeRanges Lpc IO decode ranges bit settings. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_UNSUPPORTED DMIC.SRL is set. +**/ +EFI_STATUS +PchLpcIoDecodeRangesSet ( + IN UINT16 LpcIoDecodeRanges + ); + +/** + Set PCH LPC and eSPI CS0# IO enable decoding. + Setup I/O Enables in DMI to the same value program in LPC/eSPI PCI offset 82h. + Note: Bit[15:10] of the source decode register is Read-Only. The IO range indicated by the Enables field + in LPC/eSPI PCI offset 82h[13:10] is always forwarded by DMI to subtractive agent for handling. + Please check EDS for detail of LPC/eSPI IO decode ranges bit definition. + + @param[in] LpcIoEnableDecoding LPC IO enable decoding bit settings. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_UNSUPPORTED DMIC.SRL is set. +**/ +EFI_STATUS +PchLpcIoEnableDecodingSet ( + IN UINT16 LpcIoEnableDecoding + ); + +#endif // _PCH_CYCLE_DECODING_LIB_H_ diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Pch/Include/Library/PchInfoDefs.h b/Silicon/Intel/AlderlakeSiliconPkg/Pch/Include/Library/PchInfoDefs.h new file mode 100644 index 0000000000..9328e1899c --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/Pch/Include/Library/PchInfoDefs.h @@ -0,0 +1,19 @@ +/** @file + Header file for PchInfoDefs. + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _PCH_INFO_DEFS_H_ +#define _PCH_INFO_DEFS_H_ + +#define PCH_STEPPING_MAX 0xFF + +#define PCH_LP 2 +#define PCH_N 3 +#define PCH_S 4 +#define PCH_P 5 +#define PCH_M 6 +#define PCH_UNKNOWN_SERIES 0xFF + +#endif diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Pch/Include/Library/PchInfoLib.h b/Silicon/Intel/AlderlakeSiliconPkg/Pch/Include/Library/PchInfoLib.h new file mode 100644 index 0000000000..d5d412c9f2 --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/Pch/Include/Library/PchInfoLib.h @@ -0,0 +1,108 @@ +/** @file + Header file for PchInfoLib. + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _PCH_INFO_LIB_H_ +#define _PCH_INFO_LIB_H_ + +#include +#include "PchInfoDefs.h" + +typedef UINT8 PCH_STEPPING; +typedef UINT8 PCH_SERIES; +typedef UINT8 PCH_GENERATION; + +typedef enum { + RstUnsupported = 0, + RstPremium, + RstOptane, + RstMaxMode +} RST_MODE; + +/** + Return LPC Device Id + + @retval PCH_LPC_DEVICE_ID PCH Lpc Device ID +**/ +UINT16 +PchGetLpcDid ( + VOID + ); + +/** + Return Pch stepping type + + @retval PCH_STEPPING Pch stepping type +**/ +PCH_STEPPING +PchStepping ( + VOID + ); + +/** + Return Pch Series + + @retval PCH_SERIES Pch Series +**/ +PCH_SERIES +PchSeries ( + VOID + ); + +/** + Check if this is PCH LP series + + @retval TRUE It's PCH LP series + @retval FALSE It's not PCH LP series +**/ +BOOLEAN +IsPchLp ( + VOID + ); + + +/** + Check if this is PCH P series + + @retval TRUE It's PCH P series + @retval FALSE It's not PCH P series +**/ +BOOLEAN +IsPchP ( + VOID + ); + +/** + Get Pch Maximum Pcie Root Port Number + + @retval PcieMaxRootPort Pch Maximum Pcie Root Port Number +**/ +UINT8 +GetPchMaxPciePortNum ( + VOID + ); + +/** + Get Pch Maximum Serial IO I2C controllers number + + @retval Pch Maximum Serial IO I2C controllers number +**/ +UINT8 +GetPchMaxSerialIoI2cControllersNum ( + VOID + ); + +/** + return support status for P2SB PCR 20-bit addressing + + @retval TRUE + @retval FALSE +**/ +BOOLEAN +IsP2sb20bPcrSupported ( + VOID + ); + +#endif // _PCH_INFO_LIB_H_ diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Pch/Include/Library/PchPciBdfLib.h b/Silicon/Intel/AlderlakeSiliconPkg/Pch/Include/Library/PchPciBdfLib.h new file mode 100644 index 0000000000..0c8e4d21a1 --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/Pch/Include/Library/PchPciBdfLib.h @@ -0,0 +1,187 @@ +/** @file + Header file for PchPciBdfLib. + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _PCH_PCI_BDF_LIB_H_ +#define _PCH_PCI_BDF_LIB_H_ + +/** + Get P2SB controller address that can be passed to the PCI Segment Library functions. + + @retval P2SB controller address in PCI Segment Library representation +**/ +UINT64 +P2sbPciCfgBase ( + VOID + ); + +/** + Get P2SB PCI device number + + @retval PCI dev number +**/ +UINT8 +P2sbDevNumber ( + VOID + ); + +/** + Get P2SB PCI function number + + @retval PCI fun number +**/ +UINT8 +P2sbFuncNumber ( + VOID + ); + +/** + Returns SPI PCI Config Space base address + + @retval UINT64 SPI Config Space base address +**/ +UINT64 +SpiPciCfgBase ( + VOID + ); + +/** + Returns SPI Device number + + @retval UINT8 PCH SPI Device number +**/ +UINT8 +SpiDevNumber ( + VOID + ); + +/** + Returns SPI Function number + + @retval UINT8 PCH SPI Function number +**/ +UINT8 +SpiFuncNumber ( + VOID + ); + +/** + Get XHCI controller address that can be passed to the PCI Segment Library functions. + + @retval XHCI controller address in PCI Segment Library representation +**/ +UINT64 +PchXhciPciCfgBase ( + VOID + ); + +/** + Get XHCI controller PCIe Device Number + + @retval XHCI controller PCIe Device Number +**/ +UINT8 +PchXhciDevNumber ( + VOID + ); + +/** + Get XHCI controller PCIe Function Number + + @retval XHCI controller PCIe Function Number +**/ +UINT8 +PchXhciFuncNumber ( + VOID + ); + +/** + Returns PCH LPC device PCI base address. + + @retval PCH LPC PCI base address. +**/ +UINT64 +LpcPciCfgBase ( + VOID + ); + +/** + Get LPC controller PCIe Device Number + + @retval LPC controller PCIe Device Number +**/ +UINT8 +LpcDevNumber ( + VOID + ); + + +/** + Get LPC controller PCIe Function Number + + @retval LPC controller PCIe Function Number +**/ +UINT8 +LpcFuncNumber ( + VOID + ); + + +/** + Get PCH PCIe controller PCIe Device Number + + @param[in] RpIndex Root port physical number. (0-based) + + @retval PCH PCIe controller PCIe Device Number +**/ +UINT8 +PchPcieRpDevNumber ( + IN UINTN RpIndex + ); + +/** + Get PCH PCIe controller PCIe Function Number + + @param[in] RpIndex Root port physical number. (0-based) + + @retval PCH PCIe controller PCIe Function Number +**/ +UINT8 +PchPcieRpFuncNumber ( + IN UINTN RpIndex + ); + +/** + Get HECI1 controller address that can be passed to the PCI Segment Library functions. + + @retval HECI1 controller address in PCI Segment Library representation +**/ +UINT64 +PchHeci1PciCfgBase ( + VOID + ); + +/** + Get HECI3 PCI device number + + @retval PCI dev number +**/ +UINT8 +PchHeci3DevNumber ( + VOID + ); + +/** + Get HECI3 PCI function number + + @retval PCI fun number +**/ +UINT8 +PchHeci3FuncNumber ( + VOID + ); + + +#endif //_PCH_PCI_BDF_LIB_H_ diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Pch/Include/PchPolicyCommon.h b/Silicon/Intel/AlderlakeSiliconPkg/Pch/Include/PchPolicyCommon.h new file mode 100644 index 0000000000..f8a07098f0 --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/Pch/Include/PchPolicyCommon.h @@ -0,0 +1,30 @@ +/** @file + PCH configuration based on PCH policy + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _PCH_POLICY_COMMON_H_ +#define _PCH_POLICY_COMMON_H_ + +#include + +#include "PchLimits.h" +#include "ConfigBlock/PchGeneralConfig.h" +#include +#include +#include +#include + +#ifndef FORCE_ENABLE +#define FORCE_ENABLE 1 +#endif +#ifndef FORCE_DISABLE +#define FORCE_DISABLE 2 +#endif +#ifndef PLATFORM_POR +#define PLATFORM_POR 0 +#endif + + +#endif // _PCH_POLICY_COMMON_H_ diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Pch/Include/PchPreMemPolicyCommon.h b/Silicon/Intel/AlderlakeSiliconPkg/Pch/Include/PchPreMemPolicyCommon.h new file mode 100644 index 0000000000..2100a01071 --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/Pch/Include/PchPreMemPolicyCommon.h @@ -0,0 +1,53 @@ +/** @file + PCH configuration based on PCH policy + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _PCH_PREMEM_POLICY_COMMON_H_ +#define _PCH_PREMEM_POLICY_COMMON_H_ + +#include + +#include "PchLimits.h" +#include "ConfigBlock/PchGeneralConfig.h" +#include +#include +#include +#include + +#pragma pack (push,1) + +#ifndef FORCE_ENABLE +#define FORCE_ENABLE 1 +#endif +#ifndef FORCE_DISABLE +#define FORCE_DISABLE 2 +#endif +#ifndef PLATFORM_POR +#define PLATFORM_POR 0 +#endif + +/** + PCH Policy revision number + Any backwards compatible changes to this structure will result in an update in the revision number +**/ +#define PCH_PREMEM_POLICY_REVISION 1 + +/** + PCH Policy PPI\n + All PCH config block change history will be listed here\n\n + + - Revision 1: + - Initial version.\n +**/ +typedef struct _PCH_PREMEM_POLICY { + CONFIG_BLOCK_TABLE_HEADER TableHeader; +/* + Individual Config Block Structures are added here in memory as part of AddConfigBlock() +*/ +} PCH_PREMEM_POLICY; + +#pragma pack (pop) + +#endif // _PCH_PREMEM_POLICY_COMMON_H_ diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Pch/Include/PchResetPlatformSpecific.h b/Silicon/Intel/AlderlakeSiliconPkg/Pch/Include/PchResetPlatformSpecific.h new file mode 100644 index 0000000000..88884cac25 --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/Pch/Include/PchResetPlatformSpecific.h @@ -0,0 +1,21 @@ +/** @file + PCH Reset Platform Specific definitions. + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _PCH_RESET_PLATFORM_SPECIFIC_H_ +#define _PCH_RESET_PLATFORM_SPECIFIC_H_ + +#define PCH_PLATFORM_SPECIFIC_RESET_STRING L"PCH_RESET" +#define PCH_RESET_DATA_STRING_MAX_LENGTH (sizeof (PCH_PLATFORM_SPECIFIC_RESET_STRING) / sizeof (UINT16)) + +extern EFI_GUID gPchGlobalResetGuid; + +typedef struct _RESET_DATA { + CHAR16 Description[PCH_RESET_DATA_STRING_MAX_LENGTH]; + EFI_GUID Guid; +} PCH_RESET_DATA; + +#endif // _PCH_RESET_PLATFORM_SPECIFIC_H_ + diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Pch/Include/Protocol/PchAcpiSmiDispatch.h b/Silicon/Intel/AlderlakeSiliconPkg/Pch/Include/Protocol/PchAcpiSmiDispatch.h new file mode 100644 index 0000000000..f22da50262 --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/Pch/Include/Protocol/PchAcpiSmiDispatch.h @@ -0,0 +1,134 @@ +/** @file + APIs of PCH ACPI SMI Dispatch Protocol. + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _PCH_ACPI_SMI_DISPATCH_PROTOCOL_H_ +#define _PCH_ACPI_SMI_DISPATCH_PROTOCOL_H_ + +// +// Extern the GUID for protocol users. +// +extern EFI_GUID gPchAcpiSmiDispatchProtocolGuid; + +// +// Forward reference for ANSI C compatibility +// +typedef struct _PCH_ACPI_SMI_DISPATCH_PROTOCOL PCH_ACPI_SMI_DISPATCH_PROTOCOL; + +// +// Member functions +// + +/** + Callback function for an PCH ACPI SMI handler dispatch. + + @param[in] DispatchHandle The unique handle assigned to this handler by register function. + +**/ +typedef +VOID +(EFIAPI *PCH_ACPI_SMI_DISPATCH_CALLBACK) ( + IN EFI_HANDLE DispatchHandle + ); + +/** + Register a child SMI source dispatch function for PCH ACPI SMI events. + + @param[in] This Protocol instance pointer. + @param[in] DispatchFunction Pointer to dispatch function to be invoked for + this SMI source + @param[out] DispatchHandle Handle of dispatch function, for when interfacing + with the parent SMM driver. + + @retval EFI_SUCCESS The dispatch function has been successfully + registered and the SMI source has been enabled. + @retval EFI_DEVICE_ERROR The driver was unable to enable the SMI source. + @retval EFI_OUT_OF_RESOURCES Not enough memory (system or SMM) to manage this child. + @retval EFI_ACCESS_DENIED Return access denied if the EndOfDxe event has been triggered +**/ +typedef +EFI_STATUS +(EFIAPI *PCH_ACPI_SMI_DISPATCH_REGISTER) ( + IN PCH_ACPI_SMI_DISPATCH_PROTOCOL *This, + IN PCH_ACPI_SMI_DISPATCH_CALLBACK DispatchFunction, + OUT EFI_HANDLE *DispatchHandle + ); + +/** + Unregister a child SMI source dispatch function with a parent ACPI SMM driver + + @param[in] This Protocol instance pointer. + @param[in] DispatchHandle Handle of dispatch function to deregister. + + @retval EFI_SUCCESS The dispatch function has been successfully + unregistered and the SMI source has been disabled + if there are no other registered child dispatch + functions for this SMI source. + @retval EFI_INVALID_PARAMETER Handle is invalid. + @retval EFI_ACCESS_DENIED Return access denied if the EndOfDxe event has been triggered +**/ +typedef +EFI_STATUS +(EFIAPI *PCH_ACPI_SMI_DISPATCH_UNREGISTER) ( + IN PCH_ACPI_SMI_DISPATCH_PROTOCOL *This, + IN EFI_HANDLE DispatchHandle + ); + +/** + Interface structure for PCH ACPI SMIs Dispatch Protocol + The PCH ACPI SMI DISPATCH PROTOCOL provides the ability to dispatch function for PCH ACPI related SMIs. + It contains SMI types of Pme, RtcAlarm, PmeB0, and Time overflow. +**/ +struct _PCH_ACPI_SMI_DISPATCH_PROTOCOL { + /** + This member specifies the revision of this structure. This field is used to + indicate backwards compatible changes to the protocol. + **/ + UINT8 Revision; + /** + Smi unregister function for PCH ACPI SMI DISPATCH PROTOCOL. + **/ + PCH_ACPI_SMI_DISPATCH_UNREGISTER UnRegister; + /** + Pme + The event is triggered by hardware when the PME# signal goes active. + Additionally, the event is only triggered when SCI_EN is not set. + **/ + PCH_ACPI_SMI_DISPATCH_REGISTER PmeRegister; + /** + PmeB0 + The event is triggered PCH when any internal device with PCI Power Management + capabilities on bus 0 asserts the equivalent of the PME# signal. + Additionally, the event is only triggered when SCI_EN is not set. + The following are internal devices which can set this bit: + Intel HD Audio, Intel Management Engine "maskable" wake events, Integrated LAN, + SATA, xHCI, Intel SST + **/ + PCH_ACPI_SMI_DISPATCH_REGISTER PmeB0Register; + /** + RtcAlarm + The event is triggered by hardware when the RTC generates an alarm + (assertion of the IRQ8# signal). + **/ + PCH_ACPI_SMI_DISPATCH_REGISTER RtcAlarmRegister; + /** + TmrOverflow + The event is triggered any time bit 22 of the 24-bit timer goes high + (bits are numbered from 0 to 23). + This will occur every 2.3435 seconds. When the TMROF_EN bit (ABASE + 02h, bit 0) is set, + then the setting of the TMROF_STS bit will additionally generate an SMI# + Additionally, the event is only triggered when SCI_EN is not set. + **/ + PCH_ACPI_SMI_DISPATCH_REGISTER TmrOverflowRegister; +}; + +/** + PCH ACPI SMI dispatch revision number + + Revision 1: Initial version +**/ +#define PCH_ACPI_SMI_DISPATCH_REVISION 1 + +#endif diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Pch/Include/Protocol/PchPcieSmiDispatch.h b/Silicon/Intel/AlderlakeSiliconPkg/Pch/Include/Protocol/PchPcieSmiDispatch.h new file mode 100644 index 0000000000..0c0f1ab962 --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/Pch/Include/Protocol/PchPcieSmiDispatch.h @@ -0,0 +1,166 @@ +/** @file + APIs of PCH PCIE SMI Dispatch Protocol. + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _PCH_PCIE_SMI_DISPATCH_PROTOCOL_H_ +#define _PCH_PCIE_SMI_DISPATCH_PROTOCOL_H_ + +// +// Extern the GUID for protocol users. +// +extern EFI_GUID gPchPcieSmiDispatchProtocolGuid; + +// +// Forward reference for ANSI C compatibility +// +typedef struct _PCH_PCIE_SMI_DISPATCH_PROTOCOL PCH_PCIE_SMI_DISPATCH_PROTOCOL; + +typedef enum { + PchRpIndex0 = 0, + PchRpIndex1 = 1, + PchRpIndex2 = 2, + PchRpIndex3 = 3, + PchRpIndex4 = 4, + PchRpIndex5 = 5, + PchRpIndex6 = 6, + PchRpIndex7 = 7, + PchRpIndex8 = 8, + PchRpIndex9 = 9, + PchRpIndex10 = 10, + PchRpIndex11 = 11, + PchRpIndex12 = 12, + PchRpIndex13 = 13, + PchRpIndex14 = 14, + PchRpIndex15 = 15, + PchRpIndex16 = 16, + PchRpIndex17 = 17, + PchRpIndex18 = 18, + PchRpIndex19 = 19, + PchRpIndex20 = 20, + PchRpIndex21 = 21, + PchRpIndex22 = 22, + PchRpIndex23 = 23, + /** + Quantity of PCH and CPU PCIe ports, as well as their encoding in this enum, may change between + silicon generations and series. Do not assume that PCH port 0 will be always encoded by 0. + Instead, it is recommended to use (PchRpIndex0 + PchPortIndex) style to be forward-compatible + **/ + CpuRpIndex0 = 0x40, + CpuRpIndex1 = 0x41, + CpuRpIndex2 = 0x42, + CpuRpIndex3 = 0x43 +} PCIE_COMBINED_RPINDEX; + +// +// Member functions +// + +typedef struct { + UINT8 RpIndex; ///< Root port index (0-based), 0: RP1, 1: RP2, n: RP(N+1) + UINT8 BusNum; ///< Root port pci bus number + UINT8 DevNum; ///< Root port pci device number + UINT8 FuncNum; ///< Root port pci function number +} PCH_PCIE_SMI_RP_CONTEXT; + +/** + Callback function for an PCH PCIE RP SMI handler dispatch. + + @param[in] DispatchHandle The unique handle assigned to this handler by register function. + @param[in] RpContext Pointer of PCH PCIE Root Port context. + +**/ +typedef +VOID +(EFIAPI *PCH_PCIE_SMI_RP_DISPATCH_CALLBACK) ( + IN EFI_HANDLE DispatchHandle, + IN PCH_PCIE_SMI_RP_CONTEXT *RpContext + ); + +/** + Register a child SMI source dispatch function for PCH PCIERP SMI events. + + @param[in] This Protocol instance pointer. + @param[in] DispatchFunction Pointer to dispatch function to be invoked for + this SMI source + @param[in] RpIndex Refer PCIE_COMBINED_RPINDEX for PCH RP index and CPU RP index. + 0: RP1, 1: RP2, n: RP(N+1) + @param[out] DispatchHandle Handle of dispatch function, for when interfacing + with the parent SMM driver. + + @retval EFI_SUCCESS The dispatch function has been successfully + registered and the SMI source has been enabled. + @retval EFI_DEVICE_ERROR The driver was unable to enable the SMI source. + @retval EFI_OUT_OF_RESOURCES Not enough memory (system or SMM) to manage this child. + @retval EFI_ACCESS_DENIED Return access denied if the EndOfDxe event has been triggered +**/ +typedef +EFI_STATUS +(EFIAPI *PCH_PCIE_SMI_RP_DISPATCH_REGISTER) ( + IN PCH_PCIE_SMI_DISPATCH_PROTOCOL *This, + IN PCH_PCIE_SMI_RP_DISPATCH_CALLBACK DispatchFunction, + IN UINTN RpIndex, + OUT EFI_HANDLE *DispatchHandle + ); + +/** + Unregister a child SMI source dispatch function with a parent PCIE SMM driver + + @param[in] This Protocol instance pointer. + @param[in] DispatchHandle Handle of dispatch function to deregister. + + @retval EFI_SUCCESS The dispatch function has been successfully + unregistered and the SMI source has been disabled + if there are no other registered child dispatch + functions for this SMI source. + @retval EFI_INVALID_PARAMETER Handle is invalid. + @retval EFI_ACCESS_DENIED Return access denied if the EndOfDxe event has been triggered +**/ +typedef +EFI_STATUS +(EFIAPI *PCH_PCIE_SMI_DISPATCH_UNREGISTER) ( + IN PCH_PCIE_SMI_DISPATCH_PROTOCOL *This, + IN EFI_HANDLE DispatchHandle + ); + +/** + Interface structure for PCH PCIE SMIs Dispatch Protocol + The PCH PCIE SMI DISPATCH PROTOCOL provides the ability to dispatch function for PCH PCIE related SMIs. + It contains SMI types of HotPlug, LinkActive, and Link EQ. +**/ +struct _PCH_PCIE_SMI_DISPATCH_PROTOCOL { + /** + This member specifies the revision of this structure. This field is used to + indicate backwards compatible changes to the protocol. + **/ + UINT8 Revision; + /** + Smi unregister function for PCH PCIE SMI DISPATCH PROTOCOL. + **/ + PCH_PCIE_SMI_DISPATCH_UNREGISTER UnRegister; + /** + PcieRpXHotPlug + The event is triggered when PCIE root port Hot-Plug Presence Detect. + **/ + PCH_PCIE_SMI_RP_DISPATCH_REGISTER HotPlugRegister; + /** + PcieRpXLinkActive + The event is triggered when Hot-Plug Link Active State Changed. + **/ + PCH_PCIE_SMI_RP_DISPATCH_REGISTER LinkActiveRegister; + /** + PcieRpXLinkEq + The event is triggered when Device Requests Software Link Equalization. + **/ + PCH_PCIE_SMI_RP_DISPATCH_REGISTER LinkEqRegister; +}; + +/** + PCH PCIE SMI dispatch revision number + + Revision 1: Initial version +**/ +#define PCH_PCIE_SMI_DISPATCH_REVISION 1 + +#endif diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Pch/Include/Protocol/PchSmiDispatch.h b/Silicon/Intel/AlderlakeSiliconPkg/Pch/Include/Protocol/PchSmiDispatch.h new file mode 100644 index 0000000000..fd270fe72a --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/Pch/Include/Protocol/PchSmiDispatch.h @@ -0,0 +1,132 @@ +/** @file + APIs of PCH SMI Dispatch Protocol. + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _PCH_SMI_DISPATCH_PROTOCOL_H_ +#define _PCH_SMI_DISPATCH_PROTOCOL_H_ + +// +// Extern the GUID for protocol users. +// +extern EFI_GUID gPchSmiDispatchProtocolGuid; + +// +// Forward reference for ANSI C compatibility +// +typedef struct _PCH_SMI_DISPATCH_PROTOCOL PCH_SMI_DISPATCH_PROTOCOL; + +// +// Member functions +// + +/** + Callback function for an PCH SMI handler dispatch. + + @param[in] DispatchHandle The unique handle assigned to this handler by register function. + +**/ +typedef +VOID +(EFIAPI *PCH_SMI_DISPATCH_CALLBACK) ( + IN EFI_HANDLE DispatchHandle + ); + +/** + Register a child SMI source dispatch function for specific PCH SMI dispatch event. + + @param[in] This Protocol instance pointer. + @param[in] DispatchFunction Pointer to dispatch function to be invoked for + this SMI source + @param[out] DispatchHandle Handle of dispatch function, for when interfacing + with the parent SMM driver. + + @retval EFI_SUCCESS The dispatch function has been successfully + registered and the SMI source has been enabled. + @retval EFI_DEVICE_ERROR The driver was unable to enable the SMI source. + @retval EFI_OUT_OF_RESOURCES Not enough memory (system or SMM) to manage this child. + @retval EFI_ACCESS_DENIED Return access denied if the EndOfDxe event has been triggered +**/ +typedef +EFI_STATUS +(EFIAPI *PCH_SMI_DISPATCH_REGISTER) ( + IN PCH_SMI_DISPATCH_PROTOCOL *This, + IN PCH_SMI_DISPATCH_CALLBACK DispatchFunction, + OUT EFI_HANDLE *DispatchHandle + ); + +/** + Unregister a child SMI source dispatch function with a parent SMM driver + + @param[in] This Protocol instance pointer. + @param[in] DispatchHandle Handle of dispatch function to deregister. + + @retval EFI_SUCCESS The dispatch function has been successfully + unregistered and the SMI source has been disabled + if there are no other registered child dispatch + functions for this SMI source. + @retval EFI_INVALID_PARAMETER Handle is invalid. + @retval EFI_ACCESS_DENIED Return access denied if the EndOfDxe event has been triggered +**/ +typedef +EFI_STATUS +(EFIAPI *PCH_SMI_DISPATCH_UNREGISTER) ( + IN PCH_SMI_DISPATCH_PROTOCOL *This, + IN EFI_HANDLE DispatchHandle + ); + +/** + Interface structure for PCH specific SMIs Dispatch Protocol + The PCH SMI DISPATCH PROTOCOL provides the ability to dispatch function for PCH misc SMIs. + It contains legacy SMIs and new PCH SMI types like: + SerialIrq, McSmi, Smbus, ... +**/ +struct _PCH_SMI_DISPATCH_PROTOCOL { + /** + This member specifies the revision of this structure. This field is used to + indicate backwards compatible changes to the protocol. + **/ + UINT8 Revision; + /** + Smi unregister function for PCH SMI DISPATCH PROTOCOL. + **/ + PCH_SMI_DISPATCH_UNREGISTER UnRegister; + /** + SerialIrq + The event is triggered while the SMI# was caused by the SERIRQ decoder. + **/ + PCH_SMI_DISPATCH_REGISTER SerialIrqRegister; + /** + McSmi + The event is triggered if there has been an access to the power management + microcontroller range (62h or 66h) and the Microcontroller Decode Enable #1 bit + in the LPC Bridge I/O Enables configuration register is 1 . + **/ + PCH_SMI_DISPATCH_REGISTER McSmiRegister; + /** + SmBus + The event is triggered while the SMI# was caused by: + 1. The SMBus target receiving a message that an SMI# should be caused, or + 2. The SMBALERT# signal goes active and the SMB_SMI_EN bit is set and the + SMBALERT_DIS bit is cleared, or + 3. The SMBus target receiving a Host Notify message and the HOST_NOTIFY_INTREN and + the SMB_SMI_EN bits are set, or + 4. The PCH detecting the SMLINK_SLAVE_SMI command while in the S0 state. + **/ + PCH_SMI_DISPATCH_REGISTER SmbusRegister; + /** + SPI Asynchronous + When registered, the flash controller will generate an SMI when it blocks a BIOS write or erase. + **/ + PCH_SMI_DISPATCH_REGISTER SpiAsyncRegister; +}; + +/** + PCH SMI dispatch revision number + + Revision 1: Initial version +**/ +#define PCH_SMI_DISPATCH_REVISION 1 + +#endif diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Pch/Include/Protocol/PchSmmIoTrapControl.h b/Silicon/Intel/AlderlakeSiliconPkg/Pch/Include/Protocol/PchSmmIoTrapControl.h new file mode 100644 index 0000000000..87c301901e --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/Pch/Include/Protocol/PchSmmIoTrapControl.h @@ -0,0 +1,65 @@ +/** @file + PCH SMM IO Trap Control Protocol + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _PCH_SMM_IO_TRAP_CONTROL_H_ +#define _PCH_SMM_IO_TRAP_CONTROL_H_ + + +// +// Extern the GUID for protocol users. +// +extern EFI_GUID gPchSmmIoTrapControlGuid; + +// +// Forward reference for ANSI C compatibility +// +typedef struct _PCH_SMM_IO_TRAP_CONTROL_PROTOCOL PCH_SMM_IO_TRAP_CONTROL_PROTOCOL; + +// +// Related Definitions +// + +// +// Member functions +// + +/** + The Prototype of Pause and Resume IoTrap callback function. + + @param[in] This Pointer to the PCH_SMM_IO_TRAP_CONTROL_PROTOCOL instance. + @param[in] DispatchHandle Handle of the child service to change state. + + @retval EFI_SUCCESS This operation is complete. + @retval EFI_INVALID_PARAMETER The DispatchHandle is invalid. + @retval EFI_ACCESS_DENIED The SMI status is alrady PAUSED/RESUMED. +**/ +typedef +EFI_STATUS +(EFIAPI *PCH_SMM_IO_TRAP_CONTROL_FUNCTION) ( + IN PCH_SMM_IO_TRAP_CONTROL_PROTOCOL * This, + IN EFI_HANDLE DispatchHandle + ); + +/** + Interface structure for the SMM IO trap pause and resume protocol + This protocol provides the functions to runtime control the IoTrap SMI enabled/disable. + This applys the capability to the DispatchHandle which returned by IoTrap callback + registration, and the DispatchHandle which must be MergeDisable = TRUE and Address != 0. + Besides, when S3 resuem, it only restores the state of IoTrap callback registration. + The Paused/Resume state won't be restored after S3 resume. +**/ +struct _PCH_SMM_IO_TRAP_CONTROL_PROTOCOL { + /** + This runtime pauses a registered IoTrap handler. + **/ + PCH_SMM_IO_TRAP_CONTROL_FUNCTION Pause; + /** + This runtime resumes a registered IoTrap handler. + **/ + PCH_SMM_IO_TRAP_CONTROL_FUNCTION Resume; +}; + +#endif diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Pch/Include/Protocol/PchSmmPeriodicTimerControl.h b/Silicon/Intel/AlderlakeSiliconPkg/Pch/Include/Protocol/PchSmmPeriodicTimerControl.h new file mode 100644 index 0000000000..f4773c3dd3 --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/Pch/Include/Protocol/PchSmmPeriodicTimerControl.h @@ -0,0 +1,65 @@ +/** @file + PCH SMM Periodic Timer Control Protocol + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _PCH_SMM_PERIODIC_TIMER_CONTROL_H_ +#define _PCH_SMM_PERIODIC_TIMER_CONTROL_H_ + + +// +// Extern the GUID for protocol users. +// +extern EFI_GUID gPchSmmPeriodicTimerControlGuid; + +// +// Forward reference for ANSI C compatibility +// +typedef struct _PCH_SMM_PERIODIC_TIMER_CONTROL_PROTOCOL PCH_SMM_PERIODIC_TIMER_CONTROL_PROTOCOL; + +// +// Related Definitions +// + +// +// Member functions +// + +/** + The Prototype of Pause and Resume SMM PERIODIC TIMER function. + + @param[in] This Pointer to the PCH_SMM_PERIODIC_TIMER_CONTROL_PROTOCOL instance. + @param[in] DispatchHandle Handle of the child service to change state. + + @retval EFI_SUCCESS This operation is complete. + @retval EFI_INVALID_PARAMETER The DispatchHandle is invalid. + @retval EFI_ACCESS_DENIED The SMI status is alrady PAUSED/RESUMED. +**/ +typedef +EFI_STATUS +(EFIAPI *PCH_SMM_PERIODIC_TIMER_CONTROL_FUNCTION) ( + IN PCH_SMM_PERIODIC_TIMER_CONTROL_PROTOCOL *This, + IN EFI_HANDLE DispatchHandle + ); + +/** + Interface structure for the SMM PERIODIC TIMER pause and resume protocol + This protocol provides the functions to runtime control the SM periodic timer enabled/disable. + This applies the capability to the DispatchHandle which returned by SMM periodic timer callback + registration. + Besides, when S3 resume, it only restores the state of callback registration. + The Paused/Resume state won't be restored after S3 resume. +**/ +struct _PCH_SMM_PERIODIC_TIMER_CONTROL_PROTOCOL { + /** + This runtime pauses the registered periodic timer handler. + **/ + PCH_SMM_PERIODIC_TIMER_CONTROL_FUNCTION Pause; + /** + This runtime resumes the registered periodic timer handler. + **/ + PCH_SMM_PERIODIC_TIMER_CONTROL_FUNCTION Resume; +}; + +#endif // _PCH_SMM_PERIODIC_TIMER_CONTROL_H_ diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Pch/Include/Protocol/PchTcoSmiDispatch.h b/Silicon/Intel/AlderlakeSiliconPkg/Pch/Include/Protocol/PchTcoSmiDispatch.h new file mode 100644 index 0000000000..f39773e420 --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/Pch/Include/Protocol/PchTcoSmiDispatch.h @@ -0,0 +1,150 @@ +/** @file + APIs of PCH TCO SMI Dispatch Protocol. + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _PCH_TCO_SMI_DISPATCH_PROTOCOL_H_ +#define _PCH_TCO_SMI_DISPATCH_PROTOCOL_H_ + +// +// Extern the GUID for protocol users. +// +extern EFI_GUID gPchTcoSmiDispatchProtocolGuid; + +// +// Forward reference for ANSI C compatibility +// +typedef struct _PCH_TCO_SMI_DISPATCH_PROTOCOL PCH_TCO_SMI_DISPATCH_PROTOCOL; + +// +// Member functions +// + +/** + Callback function for an PCH TCO SMI handler dispatch. + + @param[in] DispatchHandle The unique handle assigned to this handler by register function. + +**/ +typedef +VOID +(EFIAPI *PCH_TCO_SMI_DISPATCH_CALLBACK) ( + IN EFI_HANDLE DispatchHandle + ); + +/** + Register a child SMI source dispatch function for PCH TCO SMI events. + + @param[in] This Protocol instance pointer. + @param[in] DispatchFunction Pointer to dispatch function to be invoked for + this SMI source + @param[out] DispatchHandle Handle of dispatch function, for when interfacing + with the parent SMM driver. + + @retval EFI_SUCCESS The dispatch function has been successfully + registered and the SMI source has been enabled. + @retval EFI_DEVICE_ERROR The driver was unable to enable the SMI source. + @retval EFI_OUT_OF_RESOURCES Not enough memory (system or SMM) to manage this child. + @retval EFI_ACCESS_DENIED Return access denied if the EndOfDxe event has been triggered +**/ +typedef +EFI_STATUS +(EFIAPI *PCH_TCO_SMI_DISPATCH_REGISTER) ( + IN PCH_TCO_SMI_DISPATCH_PROTOCOL *This, + IN PCH_TCO_SMI_DISPATCH_CALLBACK DispatchFunction, + OUT EFI_HANDLE *DispatchHandle + ); + +/** + Unregister a child SMI source dispatch function with a parent TCO SMM driver + + @param[in] This Protocol instance pointer. + @param[in] DispatchHandle Handle of dispatch function to deregister. + + @retval EFI_SUCCESS The dispatch function has been successfully + unregistered and the SMI source has been disabled + if there are no other registered child dispatch + functions for this SMI source. + @retval EFI_INVALID_PARAMETER Handle is invalid. + @retval EFI_ACCESS_DENIED Return access denied if the EndOfDxe event has been triggered +**/ +typedef +EFI_STATUS +(EFIAPI *PCH_TCO_SMI_DISPATCH_UNREGISTER) ( + IN PCH_TCO_SMI_DISPATCH_PROTOCOL *This, + IN EFI_HANDLE DispatchHandle + ); + +/** + Interface structure for PCH TCO SMIs Dispatch Protocol + The PCH TCO SMI DISPATCH PROTOCOL provides the ability to dispatch function for PCH TCO related SMIs. + It contains SMI types of Mch, TcoTimeout, OsTco, Nmi, IntruderDectect, and BiowWp. +**/ +struct _PCH_TCO_SMI_DISPATCH_PROTOCOL { + /** + This member specifies the revision of this structure. This field is used to + indicate backwards compatible changes to the protocol. + **/ + UINT8 Revision; + /** + Smi unregister function for PCH TCO SMI DISPATCH PROTOCOL. + **/ + PCH_TCO_SMI_DISPATCH_UNREGISTER UnRegister; + /** + Mch + The event is triggered when PCH received a DMI special cycle message using DMI indicating that + it wants to cause an SMI. + The software must read the processor to determine the reason for the SMI. + **/ + PCH_TCO_SMI_DISPATCH_REGISTER MchRegister; + /** + TcoTimeout + The event is triggered by PCH to indicate that the SMI was caused by the TCO timer reaching 0. + **/ + PCH_TCO_SMI_DISPATCH_REGISTER TcoTimeoutRegister; + /** + OsTco + The event is triggered when software caused an SMI# by writing to the TCO_DAT_IN register (TCOBASE + 02h). + **/ + PCH_TCO_SMI_DISPATCH_REGISTER OsTcoRegister; + /** + Nmi + The event is triggered by the PCH when an SMI# occurs because an event occurred that would otherwise have + caused an NMI (because NMI2SMI_EN is set) + **/ + PCH_TCO_SMI_DISPATCH_REGISTER NmiRegister; + /** + IntruderDectect + The event is triggered by PCH to indicate that an intrusion was detected. + **/ + PCH_TCO_SMI_DISPATCH_REGISTER IntruderDetRegister; + /** + SpiBiosWp + This event is triggered when SMI# was caused by the TCO logic and + SPI flash controller asserted Synchronous SMI by BIOS lock enable set. + **/ + PCH_TCO_SMI_DISPATCH_REGISTER SpiBiosWpRegister; + /** + LpcBiosWp + This event is triggered when SMI# was caused by the TCO logic and + LPC/eSPI BIOS lock enable set. + **/ + PCH_TCO_SMI_DISPATCH_REGISTER LpcBiosWpRegister; + /** + NewCentury + This event is triggered when SMI# was caused by the TCO logic and + year of RTC date rolls over a century (99 to 00). + **/ + PCH_TCO_SMI_DISPATCH_REGISTER NewCenturyRegister; +}; + +/** + PCH TCO SMI dispatch revision number + + Revision 1: Initial version + Revision 2: Add NEWCENTURY support +**/ +#define PCH_TCO_SMI_DISPATCH_REVISION 2 + +#endif diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Pch/Include/Protocol/SmmSmbus.h b/Silicon/Intel/AlderlakeSiliconPkg/Pch/Include/Protocol/SmmSmbus.h new file mode 100644 index 0000000000..fa1a79ca84 --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/Pch/Include/Protocol/SmmSmbus.h @@ -0,0 +1,13 @@ +/** @file + SmmSmbus Protocol + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef __EFI_SMM_SMBUS_PROTOCOL_H__ +#define __EFI_SMM_SMBUS_PROTOCOL_H__ + +extern EFI_GUID gEfiSmmSmbusProtocolGuid; + +#endif + diff --git a/Silicon/Intel/AlderlakeSiliconPkg/Pch/Include/Register/PchRegs.h b/Silicon/Intel/AlderlakeSiliconPkg/Pch/Include/Register/PchRegs.h new file mode 100644 index 0000000000..33b75e82fd --- /dev/null +++ b/Silicon/Intel/AlderlakeSiliconPkg/Pch/Include/Register/PchRegs.h @@ -0,0 +1,45 @@ +/** @file + Generic register definitions for PCH. + +Conventions: + + - Register definition format: + Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_RegisterName + - Prefix: + Definitions beginning with "R_" are registers + Definitions beginning with "B_" are bits within registers + Definitions beginning with "V_" are meaningful values within the bits + Definitions beginning with "S_" are register size + Definitions beginning with "N_" are the bit position + - [GenerationName]: + Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc.). + Register name without GenerationName applies to all generations. + - [ComponentName]: + This field indicates the component name that the register belongs to (e.g. PCH, SA etc.) + Register name without ComponentName applies to all components. + Register that is specific to -H denoted by "_PCH_H_" in component name. + Register that is specific to -LP denoted by "_PCH_LP_" in component name. + - SubsystemName: + This field indicates the subsystem name of the component that the register belongs to + (e.g. PCIE, USB, SATA, GPIO, PMC etc.). + - RegisterSpace: + MEM - MMIO space register of subsystem. + IO - IO space register of subsystem. + PCR - Private configuration register of subsystem. + CFG - PCI configuration space register of subsystem. + - RegisterName: + Full register name. + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _PCH_REGS_H_ +#define _PCH_REGS_H_ + +/// +/// The default PCH PCI segment and bus number +/// +#define DEFAULT_PCI_SEGMENT_NUMBER_PCH 0 +#define DEFAULT_PCI_BUS_NUMBER_PCH 0 + +#endif //_PCH_REGS_H_ -- 2.36.1.windows.1