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[83.11.22.169]) by smtp.gmail.com with ESMTPSA id g20-20020aa78754000000b006e672b48b49sm3215827pfo.157.2024.03.15.04.49.34 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 15 Mar 2024 04:49:35 -0700 (PDT) Message-ID: Date: Fri, 15 Mar 2024 12:49:31 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [edk2-devel] [PATCH edk2-platforms v6 2/7] Platform/SbsaQemu: read amount of cpus during init To: Ard Biesheuvel Cc: devel@edk2.groups.io, Leif Lindholm , Ard Biesheuvel , Graeme Gregory , Xiong Yining , Chen Baozi References: <20240306-no-dt-for-cpu-v6-0-acd8727a1b59@linaro.org> <20240306-no-dt-for-cpu-v6-2-acd8727a1b59@linaro.org> From: "Marcin Juszkiewicz" Organization: Linaro In-Reply-To: Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Resent-Date: Fri, 15 Mar 2024 04:49:36 -0700 Reply-To: devel@edk2.groups.io,marcin.juszkiewicz@linaro.org List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: Content-Language: pl-PL, en-GB, en-HK Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20240206 header.b=UPKZ95yo; dmarc=fail reason="SPF not aligned (relaxed), DKIM not aligned (relaxed)" header.from=linaro.org (policy=none); spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce@groups.io W dniu 14.03.2024 o 16:13, Ard Biesheuvel pisze: >> +++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuPlatformDxe/SbsaQemuPlatformDxe.inf >> @@ -1,7 +1,7 @@ >> ## @file >> # This driver effectuates SbsaQemu platform configuration settings >> # >> -# Copyright (c) 2019, Linaro Ltd. All rights reserved. >> +# Copyright (c) Linaro Ltd. All rights reserved. >> # >> # SPDX-License-Identifier: BSD-2-Clause-Patent >> # >> @@ -32,6 +32,7 @@ [LibraryClasses] >> PcdLib >> DebugLib >> NonDiscoverableDeviceRegistrationLib >> + SbsaQemuHardwareInfoLib >> UefiDriverEntryPoint >> >> [Pcd] >> @@ -46,6 +47,7 @@ [Pcd] >> gArmTokenSpaceGuid.PcdGicDistributorBase >> gArmTokenSpaceGuid.PcdGicRedistributorsBase >> gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdGicItsBase >> + gArmVirtSbsaQemuPlatformTokenSpaceGuid.PcdCoreCount >> >> >> [Depex] > How is it guaranteed that other components will only see the correct > core count? DXE dispatch is ordered using a dependency graph, so all > users of this PCD should never execute before this driver. SbsaQemuPlatformDxe is a DXE, right? So it is called on platform init. At the end of initialization it calls SbsaQemuGetCpuCount() from SbsaQemuHardwareInfoLib to SET this PCD. It does not use it during platform init cause it does not require this information. But calls function to make sure that amount of cpus is known to whatever will be called later. Sure, maybe SbsaQemuHardwareInfoLib should be something else (DXE, Protocol or other EDK2 magic thing) but it is set of functions to be called from other places of EDK2. > This is why PCDs suck for dynamic information, to be honest. Much > better to use a protocol (DEPEXes declare dependencies on protocols, > so a driver will never run before the protocols it depends on have > been made available) I am still learning. Will look at other platforms. > Given that this is intended as reference code, I think it is very > important to get this right. Fully agree. -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. 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