* [PATCH v5 0/2] Enhanced SMM support for AMD-based x86 systems.
@ 2017-10-11 19:45 Leo Duran
2017-10-11 19:45 ` [PATCH v5 1/2] UefiCpuPkg/SmmCpuFeaturesLib: Use global variables to replace macros Leo Duran
` (2 more replies)
0 siblings, 3 replies; 30+ messages in thread
From: Leo Duran @ 2017-10-11 19:45 UTC (permalink / raw)
To: edk2-devel
This patch-set replaces Intel-specific macros with global variables
to provide support for AMD-based x86 systems.
The replaced macros are:
1) SRAM_SAVE_STATE_MAP_OFFSET
2) TXT_SMM_PSD_OFFSET
3) SMM_PSD_OFFSET
Changes since v4:
Make runtime CPUID checks and use global variables instead of PCD's.
Changes since v3:
Correction on cover letter.
Changes since v2:
The intent of this revision is to maintain compatibility with existing
packages. To that end, changes to OvmgfPkg and QuarkSocPkg are reverted.
Moreover, pertinent macros are replaced in the C code, rather than on
header files that are shared globally.
Changes since v1:
Revision to Cc list for UefiCpuPkg.
Leo Duran (2):
UefiCpuPkg/SmmCpuFeaturesLib: Use global variables to replace macros
UefiCpuPkg/PiSmmCpuDxeSmm: Use global variables to replace macros
.../Library/SmmCpuFeaturesLib/Ia32/SmiEntry.S | 28 ++++++---
.../Library/SmmCpuFeaturesLib/Ia32/SmiEntry.asm | 29 ++++++---
.../Library/SmmCpuFeaturesLib/Ia32/SmiEntry.nasm | 43 +++++++++----
UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCommon.h | 48 +++++++++++++++
.../Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c | 59 +++++++++++++++---
.../SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf | 3 +
.../SmmCpuFeaturesLib/SmmCpuFeaturesLibStm.inf | 3 +
UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c | 39 ++++++++++--
.../Library/SmmCpuFeaturesLib/X64/SmiEntry.S | 28 ++++++---
.../Library/SmmCpuFeaturesLib/X64/SmiEntry.asm | 30 ++++++---
.../Library/SmmCpuFeaturesLib/X64/SmiEntry.nasm | 47 ++++++++++----
UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/Semaphore.c | 22 ++++---
UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.S | 28 ++++++---
UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.asm | 21 +++++--
UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm | 43 +++++++++----
UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c | 72 ++++++++++++++++++++--
UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h | 17 ++++-
UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c | 18 +++---
UefiCpuPkg/PiSmmCpuDxeSmm/SmramSaveState.c | 20 +++---
UefiCpuPkg/PiSmmCpuDxeSmm/X64/Semaphore.c | 22 ++++---
UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.S | 34 ++++++----
UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.asm | 22 +++++--
UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm | 45 ++++++++++----
23 files changed, 547 insertions(+), 174 deletions(-)
create mode 100644 UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCommon.h
--
2.7.4
^ permalink raw reply [flat|nested] 30+ messages in thread
* [PATCH v5 1/2] UefiCpuPkg/SmmCpuFeaturesLib: Use global variables to replace macros
2017-10-11 19:45 [PATCH v5 0/2] Enhanced SMM support for AMD-based x86 systems Leo Duran
@ 2017-10-11 19:45 ` Leo Duran
2017-10-12 21:40 ` Paolo Bonzini
2017-10-17 14:19 ` Duran, Leo
2017-10-11 19:45 ` [PATCH v5 2/2] UefiCpuPkg/PiSmmCpuDxeSmm: " Leo Duran
2017-10-13 1:52 ` [PATCH v5 0/2] Enhanced SMM support for AMD-based x86 systems Yao, Jiewen
2 siblings, 2 replies; 30+ messages in thread
From: Leo Duran @ 2017-10-11 19:45 UTC (permalink / raw)
To: edk2-devel
Cc: Leo Duran, Jiewen Yao, Ruiyu Ni, Michael D Kinney, Jordan Justen,
Liming Gao
Set global variables on Constructor function based on CPUID checks.
The variables replace Intel macros to allow support on AMD x86 systems.
Specifically, the replaced macros are:
1) SRAM_SAVE_STATE_MAP_OFFSET
2) TXT_SMM_PSD_OFFSET
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Ruiyu Ni <ruiyu.ni@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Leo Duran <leo.duran@amd.com>
---
.../Library/SmmCpuFeaturesLib/Ia32/SmiEntry.S | 28 ++++++----
.../Library/SmmCpuFeaturesLib/Ia32/SmiEntry.asm | 29 +++++++----
.../Library/SmmCpuFeaturesLib/Ia32/SmiEntry.nasm | 43 ++++++++++++----
UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCommon.h | 48 ++++++++++++++++++
.../Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c | 59 ++++++++++++++++++----
.../SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf | 3 ++
.../SmmCpuFeaturesLib/SmmCpuFeaturesLibStm.inf | 3 ++
UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c | 39 ++++++++++++--
.../Library/SmmCpuFeaturesLib/X64/SmiEntry.S | 28 ++++++----
.../Library/SmmCpuFeaturesLib/X64/SmiEntry.asm | 30 +++++++----
.../Library/SmmCpuFeaturesLib/X64/SmiEntry.nasm | 47 ++++++++++++-----
11 files changed, 282 insertions(+), 75 deletions(-)
create mode 100644 UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCommon.h
diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.S b/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.S
index 4c0f8c8..c7b49d7 100644
--- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.S
+++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.S
@@ -1,6 +1,8 @@
#------------------------------------------------------------------------------
#
# Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>
+#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
@@ -28,6 +30,9 @@ ASM_GLOBAL ASM_PFX(gStmSmbase)
ASM_GLOBAL ASM_PFX(gStmXdSupported)
ASM_GLOBAL ASM_PFX(FeaturePcdGet (PcdCpuSmmStackGuard))
ASM_GLOBAL ASM_PFX(gStmSmiHandlerIdtr)
+ASM_GLOBAL ASM_PFX(gStmPsdOffset)
+ASM_GLOBAL ASM_PFX(gStmGdtSize)
+ASM_GLOBAL ASM_PFX(gStmGdtPtr)
.equ MSR_IA32_MISC_ENABLE, 0x1A0
.equ MSR_EFER, 0xc0000080
@@ -36,12 +41,13 @@ ASM_GLOBAL ASM_PFX(gStmSmiHandlerIdtr)
#
# Constants relating to TXT_PROCESSOR_SMM_DESCRIPTOR
#
-.equ DSC_OFFSET, 0xfb00
-.equ DSC_GDTPTR, 0x48
-.equ DSC_GDTSIZ, 0x50
-.equ DSC_CS, 0x14
-.equ DSC_DS, 0x16
-.equ DSC_SS, 0x18
+# .equ DSC_OFFSET, 0xfb00
+# .equ DSC_GDTPTR, 0x48
+# .equ DSC_GDTSIZ, 0x50
+#
+.equ DSC_CS, 0x14
+.equ DSC_DS, 0x16
+.equ DSC_SS, 0x18
.equ DSC_OTHERSEG, 0x1A
.equ PROTECT_MODE_CS, 0x08
@@ -55,11 +61,11 @@ _StmSmiEntryPoint:
.byte 0xbb # mov bx, imm16
.word _StmGdtDesc - _StmSmiEntryPoint + 0x8000
.byte 0x2e,0xa1 # mov ax, cs:[offset16]
- .word DSC_OFFSET + DSC_GDTSIZ
+ASM_PFX(gStmGdtSize): .space 2 # .word DSC_OFFSET + DSC_GDTSIZ
decl %eax
movl %eax, %cs:(%edi) # mov cs:[bx], ax
.byte 0x66,0x2e,0xa1 # mov eax, cs:[offset16]
- .word DSC_OFFSET + DSC_GDTPTR
+ASM_PFX(gStmGdtPtr): .space 2 # .word DSC_OFFSET + DSC_GDTPTR
movw %ax, %cs:2(%edi)
movw %ax, %bp # ebp = GDT base
.byte 0x66
@@ -167,7 +173,11 @@ XdDone:
movl %cr0, %ebx
orl $0x080010023, %ebx # enable paging + WP + NE + MP + PE
movl %ebx, %cr0
- leal DSC_OFFSET(%edi),%ebx
+
+ movl $ASM_PFX(gStmPsdOffset), %ebx # leal DSC_OFFSET(%edi), %ebx
+ movzxw (%ebx), %esi
+ leal (%edi, %esi), %ebx
+
movw DSC_DS(%ebx),%ax
movl %eax, %ds
movw DSC_OTHERSEG(%ebx),%ax
diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.asm b/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.asm
index 91dc1eb..4dbe276 100644
--- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.asm
+++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.asm
@@ -1,5 +1,7 @@
;------------------------------------------------------------------------------ ;
; Copyright (c) 2009 - 2017, Intel Corporation. All rights reserved.<BR>
+; Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>
+;
; This program and the accompanying materials
; are licensed and made available under the terms and conditions of the BSD License
; which accompanies this distribution. The full text of the license may be found at
@@ -29,13 +31,14 @@ MSR_EFER_XD EQU 0800h
;
; Constants relating to TXT_PROCESSOR_SMM_DESCRIPTOR
;
-DSC_OFFSET EQU 0fb00h
-DSC_GDTPTR EQU 48h
-DSC_GDTSIZ EQU 50h
-DSC_CS EQU 14h
-DSC_DS EQU 16h
-DSC_SS EQU 18h
-DSC_OTHERSEG EQU 1Ah
+; DSC_OFFSET EQU 0fb00h
+; DSC_GDTPTR EQU 48h
+; DSC_GDTSIZ EQU 50h
+;
+DSC_CS EQU 14h
+DSC_DS EQU 16h
+DSC_SS EQU 18h
+DSC_OTHERSEG EQU 1Ah
PROTECT_MODE_CS EQU 08h
PROTECT_MODE_DS EQU 20h
@@ -54,6 +57,9 @@ EXTERNDEF gStmSmbase:DWORD
EXTERNDEF gStmXdSupported:BYTE
EXTERNDEF FeaturePcdGet (PcdCpuSmmStackGuard):BYTE
EXTERNDEF gStmSmiHandlerIdtr:FWORD
+EXTERNDEF gStmPsdOffset:WORD
+EXTERNDEF gStmGdtSize:WORD
+EXTERNDEF gStmGdtPtr:WORD
.code
@@ -63,11 +69,11 @@ _StmSmiEntryPoint:
DB 0bbh ; mov bx, imm16
DW offset _StmGdtDesc - _StmSmiEntryPoint + 8000h
DB 2eh, 0a1h ; mov ax, cs:[offset16]
- DW DSC_OFFSET + DSC_GDTSIZ
+gStmGdtSize DW ? ; DSC_OFFSET + DSC_GDTSIZ
dec eax
mov cs:[edi], eax ; mov cs:[bx], ax
DB 66h, 2eh, 0a1h ; mov eax, cs:[offset16]
- DW DSC_OFFSET + DSC_GDTPTR
+gStmGdtPtr DW ? ; DSC_OFFSET + DSC_GDTPTR
mov cs:[edi + 2], ax ; mov cs:[bx + 2], eax
mov bp, ax ; ebp = GDT base
DB 66h
@@ -174,7 +180,10 @@ gStmXdSupported DB 1
mov ebx, cr0
or ebx, 080010023h ; enable paging + WP + NE + MP + PE
mov cr0, ebx
- lea ebx, [edi + DSC_OFFSET]
+
+ movzx esi, word ptr [gStmPsdOffset] ; lea ebx, [edi + DSC_OFFSET]
+ lea ebx, [edi + esi] ;
+
mov ax, [ebx + DSC_DS]
mov ds, eax
mov ax, [ebx + DSC_OTHERSEG]
diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.nasm b/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.nasm
index 00c0f067..023923a 100644
--- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.nasm
+++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.nasm
@@ -1,5 +1,7 @@
;------------------------------------------------------------------------------ ;
; Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
+; Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>
+;
; This program and the accompanying materials
; are licensed and made available under the terms and conditions of the BSD License
; which accompanies this distribution. The full text of the license may be found at
@@ -25,17 +27,18 @@
;
; Constants relating to TXT_PROCESSOR_SMM_DESCRIPTOR
;
-%define DSC_OFFSET 0xfb00
-%define DSC_GDTPTR 0x48
-%define DSC_GDTSIZ 0x50
-%define DSC_CS 0x14
-%define DSC_DS 0x16
-%define DSC_SS 0x18
-%define DSC_OTHERSEG 0x1a
+; %define DSC_OFFSET 0xfb00
+; %define DSC_GDTPTR 0x48
+; %define DSC_GDTSIZ 0x50
+;
+%define DSC_CS 0x14
+%define DSC_DS 0x16
+%define DSC_SS 0x18
+%define DSC_OTHERSEG 0x1a
%define PROTECT_MODE_CS 0x8
%define PROTECT_MODE_DS 0x20
-%define TSS_SEGMENT 0x40
+%define TSS_SEGMENT 0x40
extern ASM_PFX(SmiRendezvous)
extern ASM_PFX(FeaturePcdGet (PcdCpuSmmStackGuard))
@@ -51,6 +54,10 @@ global ASM_PFX(gStmSmbase)
global ASM_PFX(gStmXdSupported)
extern ASM_PFX(gStmSmiHandlerIdtr)
+extern ASM_PFX(gStmPsdOffset)
+global ASM_PFX(gStmGdtSize)
+global ASM_PFX(gStmGdtPtr)
+
ASM_PFX(gStmSmiCr3) EQU StmSmiCr3Patch - 4
ASM_PFX(gStmSmiStack) EQU StmSmiStackPatch - 4
ASM_PFX(gStmSmbase) EQU StmSmbasePatch - 4
@@ -62,10 +69,18 @@ BITS 16
ASM_PFX(gcStmSmiHandlerTemplate):
_StmSmiEntryPoint:
mov bx, _StmGdtDesc - _StmSmiEntryPoint + 0x8000
- mov ax,[cs:DSC_OFFSET + DSC_GDTSIZ]
+
+ mov eax, ASM_PFX(gStmGdtSize) ; mov ax, [cs:DSC_OFFSET + DSC_GDTSIZ]
+ mov si, [cs:eax] ;
+ mov ax, [cs:si] ;
+
dec ax
mov [cs:bx], ax
- mov eax, [cs:DSC_OFFSET + DSC_GDTPTR]
+
+ mov eax, ASM_PFX(gStmGdtPtr) ; mov eax, [cs:DSC_OFFSET + DSC_GDTPTR]
+ mov si, [cs:eax] ;
+ mov eax, [cs:si] ;
+
mov [cs:bx + 2], eax
mov ebp, eax ; ebp = GDT base
o32 lgdt [cs:bx] ; lgdt fword ptr cs:[bx]
@@ -166,7 +181,10 @@ StmXdSupportedPatch:
mov ebx, cr0
or ebx, 0x80010023 ; enable paging + WP + NE + MP + PE
mov cr0, ebx
- lea ebx, [edi + DSC_OFFSET]
+
+ movzx esi, word [ASM_PFX(gStmPsdOffset)] ; lea ebx, [edi + DSC_OFFSET]
+ lea ebx, [edi + esi] ;
+
mov ax, [ebx + DSC_DS]
mov ds, eax
mov ax, [ebx + DSC_OTHERSEG]
@@ -271,5 +289,8 @@ _StmSmiHandler:
; STM init finish
jmp CommonHandler
+ASM_PFX(gStmGdtSize) : RESW 1
+ASM_PFX(gStmGdtPtr) : RESW 1
+
ASM_PFX(gcStmSmiHandlerSize) : DW $ - _StmSmiEntryPoint
ASM_PFX(gcStmSmiHandlerOffset) : DW _StmSmiHandler - _StmSmiEntryPoint
diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCommon.h b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCommon.h
new file mode 100644
index 0000000..78b3a5b
--- /dev/null
+++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCommon.h
@@ -0,0 +1,48 @@
+/** @file
+ Common declarations
+
+ Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _SMM_COMMON_H_
+#define _SMM_COMMON_H_
+
+#include <Register/Amd/Cpuid.h>
+
+//
+// Definitions for AMD systems are based on contents of the
+// AMD64 Architecture Programmer's Manual
+// Volume 2: System Programming, Section 10 System-Management Mode
+//
+#define AMD_SMRAM_SAVE_STATE_MAP_OFFSET 0xfe00
+#define AMD_SMM_PSD_OFFSET 0xfc00
+
+//
+// External global variables for SMRAM offsets
+//
+extern UINT16 gSmramStateMapOffset;
+extern UINT16 gSmmPsdOffset;
+
+
+/**
+ Determine if the standard CPU signature is "AuthenticAMD".
+
+ @retval TRUE The CPU signature matches.
+ @retval FALSE The CPU signature does not match.
+
+**/
+BOOLEAN
+SmmStandardSignatureIsAuthenticAMD (
+ VOID
+ );
+
+#endif
diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c
index 2d2bc6d..1c12095 100644
--- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c
+++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c
@@ -1,14 +1,16 @@
/** @file
-The CPU specific programming for PiSmmCpuDxeSmm module.
+ The CPU specific programming for PiSmmCpuDxeSmm module.
-Copyright (c) 2010 - 2016, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials
-are licensed and made available under the terms and conditions of the BSD License
-which accompanies this distribution. The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php
+ Copyright (c) 2010 - 2016, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
@@ -22,6 +24,8 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#include <Register/Cpuid.h>
#include <Register/SmramSaveStateMap.h>
+#include "SmmCommon.h"
+
//
// Machine Specific Registers (MSRs)
//
@@ -41,6 +45,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#define SMM_FEATURES_LIB_IA32_MCA_CAP 0x17D
#define SMM_CODE_ACCESS_CHK_BIT BIT58
+
/**
Internal worker function that is called to complete CPU initialization at the
end of SmmCpuFeaturesInitializeProcessor().
@@ -77,6 +82,13 @@ BOOLEAN mNeedConfigureMtrrs = TRUE;
//
BOOLEAN *mSmrrEnabled;
+//
+// Set default value for SMRAM offset
+// from <Register/SmramSaveStateMap.h>
+//
+UINT16 gSmramStateMapOffset = SMRAM_SAVE_STATE_MAP_OFFSET;
+
+
/**
The constructor function
@@ -99,6 +111,13 @@ SmmCpuFeaturesLibConstructor (
UINTN ModelId;
//
+ // Override SMRAM offset for AMD
+ //
+ if (SmmStandardSignatureIsAuthenticAMD ()) {
+ gSmramStateMapOffset = AMD_SMRAM_SAVE_STATE_MAP_OFFSET;
+ }
+
+ //
// Retrieve CPU Family and Model
//
AsmCpuid (CPUID_VERSION_INFO, &RegEax, NULL, NULL, &RegEdx);
@@ -224,7 +243,7 @@ SmmCpuFeaturesInitializeProcessor (
//
// Configure SMBASE.
//
- CpuState = (SMRAM_SAVE_STATE_MAP *)(UINTN)(SMM_DEFAULT_SMBASE + SMRAM_SAVE_STATE_MAP_OFFSET);
+ CpuState = (SMRAM_SAVE_STATE_MAP *)(UINTN)(SMM_DEFAULT_SMBASE + gSmramStateMapOffset);
CpuState->x86.SMBASE = (UINT32)CpuHotPlugData->SmBase[CpuIndex];
//
@@ -630,3 +649,25 @@ SmmCpuFeaturesAllocatePageTableMemory (
return NULL;
}
+
+/**
+ Determine if the standard CPU signature is "AuthenticAMD".
+
+ @retval TRUE The CPU signature matches.
+ @retval FALSE The CPU signature does not match.
+
+**/
+BOOLEAN
+SmmStandardSignatureIsAuthenticAMD (
+ VOID
+ )
+{
+ UINT32 RegEbx;
+ UINT32 RegEcx;
+ UINT32 RegEdx;
+
+ AsmCpuid (CPUID_SIGNATURE, NULL, &RegEbx, &RegEcx, &RegEdx);
+ return (RegEbx == CPUID_SIGNATURE_AUTHENTIC_AMD_EBX &&
+ RegEcx == CPUID_SIGNATURE_AUTHENTIC_AMD_ECX &&
+ RegEdx == CPUID_SIGNATURE_AUTHENTIC_AMD_EDX);
+}
diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf
index 77908b0..6a39d4b 100644
--- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf
+++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf
@@ -2,6 +2,8 @@
# The CPU specific programming for PiSmmCpuDxeSmm module.
#
# Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>
+#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
@@ -24,6 +26,7 @@
[Sources]
SmmCpuFeaturesLib.c
+ SmmCommon.h
SmmCpuFeaturesLibNoStm.c
[Packages]
diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibStm.inf b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibStm.inf
index db8dcdc..a76bed6 100644
--- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibStm.inf
+++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibStm.inf
@@ -3,6 +3,8 @@
# is included.
#
# Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>
+#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
@@ -25,6 +27,7 @@
[Sources]
SmmCpuFeaturesLib.c
+ SmmCommon.h
SmmStm.c
SmmStm.h
diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c
index 45015b8..5f7c3db 100644
--- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c
+++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c
@@ -2,6 +2,8 @@
SMM STM support functions
Copyright (c) 2015 - 2017, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>
+
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@@ -28,6 +30,8 @@
#include <Protocol/MpService.h>
#include "SmmStm.h"
+#include "SmmCommon.h"
+
#define TXT_EVTYPE_BASE 0x400
#define TXT_EVTYPE_STM_HASH (TXT_EVTYPE_BASE + 14)
@@ -97,6 +101,20 @@ extern volatile UINT8 gcStmSmiHandlerTemplate[];
extern CONST UINT16 gcStmSmiHandlerSize;
extern UINT16 gcStmSmiHandlerOffset;
extern BOOLEAN gStmXdSupported;
+extern UINT16 gStmGdtSize;
+extern UINT16 gStmGdtPtr;
+
+//
+// Constants relating to TXT_PROCESSOR_SMM_DESCRIPTOR
+//
+#define TXT_PSD_GDTPTR 0x48
+#define TXT_PSD_GDTSIZE 0x50
+
+//
+// Set default value for PSD offset in SMRAM
+// from <Register/StmApi.h>
+//
+UINT16 gStmPsdOffset = TXT_SMM_PSD_OFFSET;
//
// Variables used by SMI Handler
@@ -145,6 +163,19 @@ SmmCpuFeaturesLibStmConstructor (
ASSERT_EFI_ERROR (Status);
//
+ // Override PSD offset for AMD
+ //
+ if (SmmStandardSignatureIsAuthenticAMD ()) {
+ gStmPsdOffset = AMD_SMM_PSD_OFFSET;
+ }
+
+ //
+ // Initialize STM global variables associated with SMI Handler
+ //
+ gStmGdtSize = gStmPsdOffset + TXT_PSD_GDTSIZE;
+ gStmGdtPtr = gStmPsdOffset + TXT_PSD_GDTPTR;
+
+ //
// Lookup the MP Services Protocol
//
Status = gBS->LocateProtocol (
@@ -276,8 +307,8 @@ SmmCpuFeaturesInstallSmiHandler (
UINT32 RegEdx;
EFI_PROCESSOR_INFORMATION ProcessorInfo;
- CopyMem ((VOID *)((UINTN)SmBase + TXT_SMM_PSD_OFFSET), &gcStmPsd, sizeof (gcStmPsd));
- Psd = (TXT_PROCESSOR_SMM_DESCRIPTOR *)(VOID *)((UINTN)SmBase + TXT_SMM_PSD_OFFSET);
+ CopyMem ((VOID *)((UINTN)SmBase + gStmPsdOffset), &gcStmPsd, sizeof (gcStmPsd));
+ Psd = (TXT_PROCESSOR_SMM_DESCRIPTOR *)(VOID *)((UINTN)SmBase + gStmPsdOffset);
Psd->SmmGdtPtr = GdtBase;
Psd->SmmGdtSize = (UINT32)GdtSize;
@@ -416,7 +447,7 @@ SmmEndOfDxeEventNotify (
}
for (Index = 0; Index < gSmst->NumberOfCpus; Index++) {
- Psd = (TXT_PROCESSOR_SMM_DESCRIPTOR *)((UINTN)gSmst->CpuSaveState[Index] - SMRAM_SAVE_STATE_MAP_OFFSET + TXT_SMM_PSD_OFFSET);
+ Psd = (TXT_PROCESSOR_SMM_DESCRIPTOR *)((UINTN)gSmst->CpuSaveState[Index] - gSmramStateMapOffset + gStmPsdOffset);
DEBUG ((DEBUG_INFO, "Index=%d Psd=%p Rsdp=%p\n", Index, Psd, Rsdp));
Psd->AcpiRsdp = (UINT64)(UINTN)Rsdp;
}
@@ -1266,7 +1297,7 @@ NotifyStmResourceChange (
TXT_PROCESSOR_SMM_DESCRIPTOR *Psd;
for (Index = 0; Index < gSmst->NumberOfCpus; Index++) {
- Psd = (TXT_PROCESSOR_SMM_DESCRIPTOR *)((UINTN)gSmst->CpuSaveState[Index] - SMRAM_SAVE_STATE_MAP_OFFSET + TXT_SMM_PSD_OFFSET);
+ Psd = (TXT_PROCESSOR_SMM_DESCRIPTOR *)((UINTN)gSmst->CpuSaveState[Index] - gSmramStateMapOffset + gStmPsdOffset);
Psd->BiosHwResourceRequirementsPtr = (UINT64)(UINTN)StmResource;
}
return ;
diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.S b/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.S
index 1f9f91c..5f3386a 100644
--- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.S
+++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.S
@@ -1,6 +1,8 @@
#------------------------------------------------------------------------------
#
# Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>
+#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
@@ -27,6 +29,9 @@ ASM_GLOBAL ASM_PFX(gStmSmiStack)
ASM_GLOBAL ASM_PFX(gStmSmbase)
ASM_GLOBAL ASM_PFX(gStmXdSupported)
ASM_GLOBAL ASM_PFX(gStmSmiHandlerIdtr)
+ASM_GLOBAL ASM_PFX(gStmPsdOffset)
+ASM_GLOBAL ASM_PFX(gStmGdtSize)
+ASM_GLOBAL ASM_PFX(gStmGdtPtr)
.equ MSR_IA32_MISC_ENABLE, 0x1A0
.equ MSR_EFER, 0xc0000080
@@ -35,12 +40,13 @@ ASM_GLOBAL ASM_PFX(gStmSmiHandlerIdtr)
#
# Constants relating to TXT_PROCESSOR_SMM_DESCRIPTOR
#
-.equ DSC_OFFSET, 0xfb00
-.equ DSC_GDTPTR, 0x48
-.equ DSC_GDTSIZ, 0x50
-.equ DSC_CS, 0x14
-.equ DSC_DS, 0x16
-.equ DSC_SS, 0x18
+# .equ DSC_OFFSET, 0xfb00
+# .equ DSC_GDTPTR, 0x48
+# .equ DSC_GDTSIZ, 0x50
+#
+.equ DSC_CS, 0x14
+.equ DSC_DS, 0x16
+.equ DSC_SS, 0x18
.equ DSC_OTHERSEG, 0x1a
#
# Constants relating to CPU State Save Area
@@ -71,12 +77,12 @@ _StmSmiEntryPoint:
# fix GDT descriptor
#
.byte 0x2e,0xa1 # mov ax, cs:[offset16]
- .word DSC_OFFSET + DSC_GDTSIZ
+ASM_PFX(gStmGdtSize): .space 2 # .word DSC_OFFSET + DSC_GDTSIZ
.byte 0x48 # dec ax
.byte 0x2e
movl %eax, (%rdi) # mov cs:[bx], ax
.byte 0x66,0x2e,0xa1 # mov eax, cs:[offset16]
- .word DSC_OFFSET + DSC_GDTPTR
+ASM_PFX(gStmGdtPtr): .space 2 # .word DSC_OFFSET + DSC_GDTPTR
.byte 0x2e
movw %ax, 2(%rdi)
.byte 0x66,0x2e
@@ -183,7 +189,11 @@ Base:
LongMode: # long mode (64-bit code) starts here
movabsq $ASM_PFX(gStmSmiHandlerIdtr), %rax
lidt (%rax)
- lea (DSC_OFFSET)(%rdi), %ebx
+
+ movl $ASM_PFX(gStmPsdOffset), %ebx # lea (DSC_OFFSET)(%rdi), %ebx
+ movzxw (%ebx), %rsi
+ leal (%rdi, %rsi), %ebx
+
movw DSC_DS(%rbx), %ax
movl %eax,%ds
movw DSC_OTHERSEG(%rbx), %ax
diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.asm b/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.asm
index ad51e07..10913df 100644
--- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.asm
+++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.asm
@@ -1,5 +1,7 @@
;------------------------------------------------------------------------------ ;
; Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.<BR>
+; Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>
+;
; This program and the accompanying materials
; are licensed and made available under the terms and conditions of the BSD License
; which accompanies this distribution. The full text of the license may be found at
@@ -32,6 +34,10 @@ EXTERNDEF gStmSmiStack:DWORD
EXTERNDEF gStmSmbase:DWORD
EXTERNDEF gStmXdSupported:BYTE
EXTERNDEF gStmSmiHandlerIdtr:FWORD
+EXTERNDEF gStmPsdOffset:WORD
+EXTERNDEF gStmGdtSize:WORD
+EXTERNDEF gStmGdtPtr:WORD
+
MSR_IA32_MISC_ENABLE EQU 1A0h
MSR_EFER EQU 0c0000080h
@@ -40,13 +46,14 @@ MSR_EFER_XD EQU 0800h
;
; Constants relating to TXT_PROCESSOR_SMM_DESCRIPTOR
;
-DSC_OFFSET EQU 0fb00h
-DSC_GDTPTR EQU 48h
-DSC_GDTSIZ EQU 50h
-DSC_CS EQU 14h
-DSC_DS EQU 16h
-DSC_SS EQU 18h
-DSC_OTHERSEG EQU 1ah
+; DSC_OFFSET EQU 0fb00h
+; DSC_GDTPTR EQU 48h
+; DSC_GDTSIZ EQU 50h
+;
+DSC_CS EQU 14h
+DSC_DS EQU 16h
+DSC_SS EQU 18h
+DSC_OTHERSEG EQU 1ah
;
; Constants relating to CPU State Save Area
;
@@ -74,12 +81,12 @@ _StmSmiEntryPoint:
DW offset _StmGdtDesc - _StmSmiEntryPoint + 8000h ; bx = GdtDesc offset
; fix GDT descriptor
DB 2eh, 0a1h ; mov ax, cs:[offset16]
- DW DSC_OFFSET + DSC_GDTSIZ
+gStmGdtSize DW ? ; DSC_OFFSET + DSC_GDTSIZ
DB 48h ; dec ax
DB 2eh
mov [rdi], eax ; mov cs:[bx], ax
DB 66h, 2eh, 0a1h ; mov eax, cs:[offset16]
- DW DSC_OFFSET + DSC_GDTPTR
+gStmGdtPtr DW ? ; DSC_OFFSET + DSC_GDTPTR
DB 2eh
mov [rdi + 2], ax ; mov cs:[bx + 2], eax
DB 66h, 2eh
@@ -178,7 +185,10 @@ Base:
@LongMode: ; long mode (64-bit code) starts here
mov rax, offset gStmSmiHandlerIdtr
lidt fword ptr [rax]
- lea ebx, [rdi + DSC_OFFSET]
+
+ movzx rsi, word ptr [gStmPsdOffset] ; lea ebx, [rdi + DSC_OFFSET]
+ lea ebx, [rdi + rsi] ;
+
mov ax, [rbx + DSC_DS]
mov ds, eax
mov ax, [rbx + DSC_OTHERSEG]
diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.nasm b/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.nasm
index bcac643..df4c5a2 100644
--- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.nasm
+++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.nasm
@@ -1,5 +1,7 @@
;------------------------------------------------------------------------------ ;
; Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
+; Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>
+;
; This program and the accompanying materials
; are licensed and made available under the terms and conditions of the BSD License
; which accompanies this distribution. The full text of the license may be found at
@@ -29,13 +31,14 @@
;
; Constants relating to TXT_PROCESSOR_SMM_DESCRIPTOR
;
-%define DSC_OFFSET 0xfb00
-%define DSC_GDTPTR 0x48
-%define DSC_GDTSIZ 0x50
-%define DSC_CS 0x14
-%define DSC_DS 0x16
-%define DSC_SS 0x18
-%define DSC_OTHERSEG 0x1a
+; %define DSC_OFFSET 0xfb00
+; %define DSC_GDTPTR 0x48
+; %define DSC_GDTSIZ 0x50
+;
+%define DSC_CS 0x14
+%define DSC_DS 0x16
+%define DSC_SS 0x18
+%define DSC_OTHERSEG 0x1a
;
; Constants relating to CPU State Save Area
;
@@ -44,9 +47,9 @@
%define PROTECT_MODE_CS 0x8
%define PROTECT_MODE_DS 0x20
-%define LONG_MODE_CS 0x38
-%define TSS_SEGMENT 0x40
-%define GDT_SIZE 0x50
+%define LONG_MODE_CS 0x38
+%define TSS_SEGMENT 0x40
+%define GDT_SIZE 0x50
extern ASM_PFX(SmiRendezvous)
extern ASM_PFX(gStmSmiHandlerIdtr)
@@ -61,6 +64,10 @@ global ASM_PFX(gcStmSmiHandlerTemplate)
global ASM_PFX(gcStmSmiHandlerSize)
global ASM_PFX(gcStmSmiHandlerOffset)
+extern ASM_PFX(gStmPsdOffset)
+global ASM_PFX(gStmGdtSize)
+global ASM_PFX(gStmGdtPtr)
+
ASM_PFX(gStmSmbase) EQU StmSmbasePatch - 4
ASM_PFX(gStmSmiStack) EQU StmSmiStackPatch - 4
ASM_PFX(gStmSmiCr3) EQU StmSmiCr3Patch - 4
@@ -73,10 +80,18 @@ BITS 16
ASM_PFX(gcStmSmiHandlerTemplate):
_StmSmiEntryPoint:
mov bx, _StmGdtDesc - _StmSmiEntryPoint + 0x8000
- mov ax,[cs:DSC_OFFSET + DSC_GDTSIZ]
+
+ mov eax, ASM_PFX(gStmGdtSize) ; mov ax, [cs:DSC_OFFSET + DSC_GDTSIZ]
+ mov si, [cs:eax] ;
+ mov ax, [cs:si] ;
+
dec ax
mov [cs:bx], ax
- mov eax, [cs:DSC_OFFSET + DSC_GDTPTR]
+
+ mov eax, ASM_PFX(gStmGdtPtr) ; mov eax, [cs:DSC_OFFSET + DSC_GDTPTR]
+ mov si, [cs:eax] ;
+ mov eax, [cs:si] ;
+
mov [cs:bx + 2], eax
o32 lgdt [cs:bx] ; lgdt fword ptr cs:[bx]
mov ax, PROTECT_MODE_CS
@@ -166,7 +181,10 @@ Base:
@LongMode: ; long mode (64-bit code) starts here
mov rax, ASM_PFX(gStmSmiHandlerIdtr)
lidt [rax]
- lea ebx, [rdi + DSC_OFFSET]
+
+ movzx rsi, word [ASM_PFX(gStmPsdOffset)] ; lea ebx, [rdi + DSC_OFFSET]
+ lea ebx, [rdi + rsi] ;
+
mov ax, [rbx + DSC_DS]
mov ds, eax
mov ax, [rbx + DSC_OTHERSEG]
@@ -262,5 +280,8 @@ _StmSmiHandler:
; STM init finish
jmp CommonHandler
+ASM_PFX(gStmGdtSize) : RESW 1
+ASM_PFX(gStmGdtPtr) : RESW 1
+
ASM_PFX(gcStmSmiHandlerSize) : DW $ - _StmSmiEntryPoint
ASM_PFX(gcStmSmiHandlerOffset) : DW _StmSmiHandler - _StmSmiEntryPoint
--
2.7.4
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH v5 2/2] UefiCpuPkg/PiSmmCpuDxeSmm: Use global variables to replace macros
2017-10-11 19:45 [PATCH v5 0/2] Enhanced SMM support for AMD-based x86 systems Leo Duran
2017-10-11 19:45 ` [PATCH v5 1/2] UefiCpuPkg/SmmCpuFeaturesLib: Use global variables to replace macros Leo Duran
@ 2017-10-11 19:45 ` Leo Duran
2017-10-13 1:52 ` [PATCH v5 0/2] Enhanced SMM support for AMD-based x86 systems Yao, Jiewen
2 siblings, 0 replies; 30+ messages in thread
From: Leo Duran @ 2017-10-11 19:45 UTC (permalink / raw)
To: edk2-devel
Cc: Leo Duran, Jiewen Yao, Ruiyu Ni, Michael D Kinney, Jordan Justen,
Liming Gao
Set global variables on Entry function based on CPUID checks.
The variables replace Intel macros to allow support on AMD x86 systems.
Specifically, the replaced macros are:
1) SRAM_SAVE_STATE_MAP_OFFSET
2) SMM_PSD_OFFSET
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Ruiyu Ni <ruiyu.ni@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Leo Duran <leo.duran@amd.com>
---
UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/Semaphore.c | 22 ++++---
UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.S | 28 ++++++---
UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.asm | 21 +++++--
UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm | 43 +++++++++----
UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c | 72 ++++++++++++++++++++--
UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h | 17 ++++-
UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c | 18 +++---
UefiCpuPkg/PiSmmCpuDxeSmm/SmramSaveState.c | 20 +++---
UefiCpuPkg/PiSmmCpuDxeSmm/X64/Semaphore.c | 22 ++++---
UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.S | 34 ++++++----
UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.asm | 22 +++++--
UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm | 45 ++++++++++----
12 files changed, 265 insertions(+), 99 deletions(-)
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/Semaphore.c b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/Semaphore.c
index 02a866b..7b2e5fb 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/Semaphore.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/Semaphore.c
@@ -1,15 +1,17 @@
/** @file
-Semaphore mechanism to indicate to the BSP that an AP has exited SMM
-after SMBASE relocation.
+ Semaphore mechanism to indicate to the BSP that an AP has exited SMM
+ after SMBASE relocation.
-Copyright (c) 2009 - 2015, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials
-are licensed and made available under the terms and conditions of the BSD License
-which accompanies this distribution. The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php
+ Copyright (c) 2009 - 2015, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
@@ -38,7 +40,7 @@ SemaphoreHook (
mRebasedFlag = RebasedFlag;
- CpuState = (SMRAM_SAVE_STATE_MAP *)(UINTN)(SMM_DEFAULT_SMBASE + SMRAM_SAVE_STATE_MAP_OFFSET);
+ CpuState = (SMRAM_SAVE_STATE_MAP *)(UINTN)(SMM_DEFAULT_SMBASE + gSmmSmramStateMapOffset);
mSmmRelocationOriginalAddress = (UINTN)HookReturnFromSmm (
CpuIndex,
CpuState,
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.S b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.S
index 3243a91..d25c099 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.S
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.S
@@ -1,6 +1,8 @@
#------------------------------------------------------------------------------
#
# Copyright (c) 2009 - 2017, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>
+#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
@@ -27,6 +29,9 @@ ASM_GLOBAL ASM_PFX(gSmbase)
ASM_GLOBAL ASM_PFX(mXdSupported)
ASM_GLOBAL ASM_PFX(FeaturePcdGet (PcdCpuSmmStackGuard))
ASM_GLOBAL ASM_PFX(gSmiHandlerIdtr)
+ASM_GLOBAL ASM_PFX(gSmmPsdOffset)
+ASM_GLOBAL ASM_PFX(gPsdGdtSize)
+ASM_GLOBAL ASM_PFX(gPsdGdtPtr)
.equ MSR_IA32_MISC_ENABLE, 0x1A0
.equ MSR_EFER, 0xc0000080
@@ -35,12 +40,13 @@ ASM_GLOBAL ASM_PFX(gSmiHandlerIdtr)
#
# Constants relating to PROCESSOR_SMM_DESCRIPTOR
#
-.equ DSC_OFFSET, 0xfb00
-.equ DSC_GDTPTR, 0x30
-.equ DSC_GDTSIZ, 0x38
-.equ DSC_CS, 14
-.equ DSC_DS, 16
-.equ DSC_SS, 18
+# .equ DSC_OFFSET, 0xfb00
+# .equ DSC_GDTPTR, 0x30
+# .equ DSC_GDTSIZ, 0x38
+#
+.equ DSC_CS, 14
+.equ DSC_DS, 16
+.equ DSC_SS, 18
.equ DSC_OTHERSEG, 20
.equ PROTECT_MODE_CS, 0x08
@@ -55,11 +61,11 @@ _SmiEntryPoint:
.byte 0xbb # mov bx, imm16
.word _GdtDesc - _SmiEntryPoint + 0x8000
.byte 0x2e,0xa1 # mov ax, cs:[offset16]
- .word DSC_OFFSET + DSC_GDTSIZ
+ASM_PFX(gPsdGdtSize): .space 2 # .word DSC_OFFSET + DSC_GDTSIZ
decl %eax
movl %eax, %cs:(%edi) # mov cs:[bx], ax
.byte 0x66,0x2e,0xa1 # mov eax, cs:[offset16]
- .word DSC_OFFSET + DSC_GDTPTR
+ASM_PFX(gPsdGdtPtr): .space 2 # .word DSC_OFFSET + DSC_GDTPTR
movw %ax, %cs:2(%edi)
movw %ax, %bp # ebp = GDT base
.byte 0x66
@@ -167,7 +173,11 @@ NxeDone:
movl %cr0, %ebx
orl $0x080010023, %ebx # enable paging + WP + NE + MP + PE
movl %ebx, %cr0
- leal DSC_OFFSET(%edi),%ebx
+
+ movl $ASM_PFX(gSmmPsdOffset), %ebx # leal DSC_OFFSET(%edi), %ebx
+ movzxw (%ebx), %esi
+ leal (%edi, %esi), %ebx
+
movw DSC_DS(%ebx),%ax
movl %eax, %ds
movw DSC_OTHERSEG(%ebx),%ax
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.asm b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.asm
index 8296f36..c9c471f 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.asm
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.asm
@@ -1,5 +1,7 @@
;------------------------------------------------------------------------------ ;
; Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.<BR>
+; Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>
+;
; This program and the accompanying materials
; are licensed and made available under the terms and conditions of the BSD License
; which accompanies this distribution. The full text of the license may be found at
@@ -29,9 +31,10 @@ MSR_EFER_XD EQU 0800h
;
; Constants relating to PROCESSOR_SMM_DESCRIPTOR
;
-DSC_OFFSET EQU 0fb00h
-DSC_GDTPTR EQU 30h
-DSC_GDTSIZ EQU 38h
+; DSC_OFFSET EQU 0fb00h
+; DSC_GDTPTR EQU 30h
+; DSC_GDTSIZ EQU 38h
+;
DSC_CS EQU 14
DSC_DS EQU 16
DSC_SS EQU 18
@@ -53,6 +56,9 @@ EXTERNDEF gSmbase:DWORD
EXTERNDEF mXdSupported:BYTE
EXTERNDEF FeaturePcdGet (PcdCpuSmmStackGuard):BYTE
EXTERNDEF gSmiHandlerIdtr:FWORD
+EXTERNDEF gSmmPsdOffset:WORD
+EXTERNDEF gPsdGdtSize:WORD
+EXTERNDEF gPsdGdtPtr:WORD
.code
@@ -62,11 +68,11 @@ _SmiEntryPoint:
DB 0bbh ; mov bx, imm16
DW offset _GdtDesc - _SmiEntryPoint + 8000h
DB 2eh, 0a1h ; mov ax, cs:[offset16]
- DW DSC_OFFSET + DSC_GDTSIZ
+gPsdGdtSize DW ? ; DSC_OFFSET + DSC_GDTSIZ
dec eax
mov cs:[edi], eax ; mov cs:[bx], ax
DB 66h, 2eh, 0a1h ; mov eax, cs:[offset16]
- DW DSC_OFFSET + DSC_GDTPTR
+gPsdGdtPtr DW ? ; DSC_OFFSET + DSC_GDTPTR
mov cs:[edi + 2], ax ; mov cs:[bx + 2], eax
mov bp, ax ; ebp = GDT base
DB 66h
@@ -173,7 +179,10 @@ mXdSupported DB 1
mov ebx, cr0
or ebx, 080010023h ; enable paging + WP + NE + MP + PE
mov cr0, ebx
- lea ebx, [edi + DSC_OFFSET]
+
+ movzx esi, word ptr [gSmmPsdOffset] ; lea ebx, [edi + DSC_OFFSET]
+ lea ebx, [edi + esi]
+
mov ax, [ebx + DSC_DS]
mov ds, eax
mov ax, [ebx + DSC_OTHERSEG]
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm
index 4d2383f..666233b 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm
@@ -1,5 +1,7 @@
;------------------------------------------------------------------------------ ;
; Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
+; Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>
+;
; This program and the accompanying materials
; are licensed and made available under the terms and conditions of the BSD License
; which accompanies this distribution. The full text of the license may be found at
@@ -25,17 +27,18 @@
;
; Constants relating to PROCESSOR_SMM_DESCRIPTOR
;
-%define DSC_OFFSET 0xfb00
-%define DSC_GDTPTR 0x30
-%define DSC_GDTSIZ 0x38
-%define DSC_CS 14
-%define DSC_DS 16
-%define DSC_SS 18
-%define DSC_OTHERSEG 20
+; %define DSC_OFFSET 0xfb00
+; %define DSC_GDTPTR 0x30
+; %define DSC_GDTSIZ 0x38
+;
+%define DSC_CS 14
+%define DSC_DS 16
+%define DSC_SS 18
+%define DSC_OTHERSEG 20
%define PROTECT_MODE_CS 0x8
%define PROTECT_MODE_DS 0x20
-%define TSS_SEGMENT 0x40
+%define TSS_SEGMENT 0x40
extern ASM_PFX(SmiRendezvous)
extern ASM_PFX(FeaturePcdGet (PcdCpuSmmStackGuard))
@@ -50,16 +53,28 @@ global ASM_PFX(gSmbase)
global ASM_PFX(mXdSupported)
extern ASM_PFX(gSmiHandlerIdtr)
+extern ASM_PFX(gSmmPsdOffset)
+global ASM_PFX(gPsdGdtSize)
+global ASM_PFX(gPsdGdtPtr)
+
SECTION .text
BITS 16
ASM_PFX(gcSmiHandlerTemplate):
_SmiEntryPoint:
mov bx, _GdtDesc - _SmiEntryPoint + 0x8000
- mov ax,[cs:DSC_OFFSET + DSC_GDTSIZ]
+
+ mov eax, ASM_PFX(gPsdGdtSize) ; mov ax, [cs:DSC_OFFSET + DSC_GDTSIZ]
+ mov si, [cs:eax] ;
+ mov ax, [cs:si] ;
+
dec ax
mov [cs:bx], ax
- mov eax, [cs:DSC_OFFSET + DSC_GDTPTR]
+
+ mov eax, ASM_PFX(gPsdGdtPtr) ; mov eax, [cs:DSC_OFFSET + DSC_GDTPTR]
+ mov si, [cs:eax] ;
+ mov eax, [cs:si] ;
+
mov [cs:bx + 2], eax
mov ebp, eax ; ebp = GDT base
o32 lgdt [cs:bx] ; lgdt fword ptr cs:[bx]
@@ -160,7 +175,10 @@ ASM_PFX(mXdSupported): DB 1
mov ebx, cr0
or ebx, 0x80010023 ; enable paging + WP + NE + MP + PE
mov cr0, ebx
- lea ebx, [edi + DSC_OFFSET]
+
+ movzx esi, word [ASM_PFX(gSmmPsdOffset)] ; lea ebx, [edi + DSC_OFFSET]
+ lea ebx, [edi + esi] ;
+
mov ax, [ebx + DSC_DS]
mov ds, eax
mov ax, [ebx + DSC_OTHERSEG]
@@ -205,5 +223,8 @@ ASM_PFX(SmiHandler):
.7:
rsm
+ASM_PFX(gPsdGdtSize): RESW 1
+ASM_PFX(gPsdGdtPtr) : RESW 1
+
ASM_PFX(gcSmiHandlerSize): DW $ - _SmiEntryPoint
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c
index 282d2e6..ad7c811 100755
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c
@@ -116,6 +116,31 @@ UINTN mSmmCpuSmramRangeCount;
UINT8 mPhysicalAddressBits;
+//
+// Set default value for SMRAM offset
+// from <Register/SmramSaveStateMap.h>
+//
+UINT16 gSmmSmramStateMapOffset = SMRAM_SAVE_STATE_MAP_OFFSET;
+
+//
+// Set default value for PSD offset in SMRAM
+//
+UINT16 gSmmPsdOffset = INTEL_SMM_PSD_OFFSET;
+
+//
+// Constants relating to PROCESSOR_SMM_DESCRIPTOR
+//
+#define SMM_PSD_GDTPTR 0x30
+#define SMM_PSD_GDTSIZE 0x38
+
+
+//
+// External global variables associated with SMI Handler Template
+//
+extern UINT16 gPsdGdtSize;
+extern UINT16 gPsdGdtPtr;
+
+
/**
Initialize IDT to setup exception handlers for SMM.
@@ -407,7 +432,7 @@ SmmRelocateBases (
gcSmiInitGdtr.Limit = gcSmiGdtr.Limit;
U8Ptr = (UINT8*)(UINTN)(SMM_DEFAULT_SMBASE + SMM_HANDLER_OFFSET);
- CpuStatePtr = (SMRAM_SAVE_STATE_MAP *)(UINTN)(SMM_DEFAULT_SMBASE + SMRAM_SAVE_STATE_MAP_OFFSET);
+ CpuStatePtr = (SMRAM_SAVE_STATE_MAP *)(UINTN)(SMM_DEFAULT_SMBASE + gSmmSmramStateMapOffset);
//
// Backup original contents at address 0x38000
@@ -500,6 +525,29 @@ SmmReadyToLockEventNotify (
}
/**
+ Determine if the standard CPU signature is "AuthenticAMD".
+
+ @retval TRUE The CPU signature matches.
+ @retval FALSE The CPU signature does not match.
+
+**/
+STATIC
+BOOLEAN
+StandardSignatureIsAuthenticAMD (
+ VOID
+ )
+{
+ UINT32 RegEbx;
+ UINT32 RegEcx;
+ UINT32 RegEdx;
+
+ AsmCpuid (CPUID_SIGNATURE, NULL, &RegEbx, &RegEcx, &RegEdx);
+ return (RegEbx == CPUID_SIGNATURE_AUTHENTIC_AMD_EBX &&
+ RegEcx == CPUID_SIGNATURE_AUTHENTIC_AMD_ECX &&
+ RegEdx == CPUID_SIGNATURE_AUTHENTIC_AMD_EDX);
+}
+
+/**
The module Entry Point of the CPU SMM driver.
@param ImageHandle The firmware allocated handle for the EFI image.
@@ -547,6 +595,20 @@ PiCpuSmmEntry (
);
//
+ // Override SMRAM offsets for AMD
+ //
+ if (StandardSignatureIsAuthenticAMD ()) {
+ gSmmSmramStateMapOffset = AMD_SMRAM_SAVE_STATE_MAP_OFFSET;
+ gSmmPsdOffset = AMD_SMM_PSD_OFFSET;
+ }
+
+ //
+ // Initialize PSD global variables associated with SMI Handler
+ //
+ gPsdGdtSize = gSmmPsdOffset + SMM_PSD_GDTSIZE;
+ gPsdGdtPtr = gSmmPsdOffset + SMM_PSD_GDTPTR;
+
+ //
// Fix segment address of the long-mode-switch jump
//
if (sizeof (UINTN) == sizeof (UINT64)) {
@@ -707,12 +769,12 @@ PiCpuSmmEntry (
//
// Compute tile size of buffer required to hold the CPU SMRAM Save State Map, extra CPU
- // specific context start starts at SMBASE + SMM_PSD_OFFSET, and the SMI entry point.
+ // specific context start starts at SMBASE + gSmmPsdOffset, and the SMI entry point.
// This size is rounded up to nearest power of 2.
//
TileCodeSize = GetSmiHandlerSize ();
TileCodeSize = ALIGN_VALUE(TileCodeSize, SIZE_4KB);
- TileDataSize = (SMRAM_SAVE_STATE_MAP_OFFSET - SMM_PSD_OFFSET) + sizeof (SMRAM_SAVE_STATE_MAP);
+ TileDataSize = (gSmmSmramStateMapOffset - gSmmPsdOffset) + sizeof (SMRAM_SAVE_STATE_MAP);
TileDataSize = ALIGN_VALUE(TileDataSize, SIZE_4KB);
TileSize = TileDataSize + TileCodeSize - 1;
TileSize = 2 * GetPowerOfTwo32 ((UINT32)TileSize);
@@ -725,7 +787,7 @@ PiCpuSmmEntry (
// the SMI Handler size must be reduced or the size of the extra CPU specific
// context must be reduced.
//
- ASSERT (TileSize <= (SMRAM_SAVE_STATE_MAP_OFFSET + sizeof (SMRAM_SAVE_STATE_MAP) - SMM_HANDLER_OFFSET));
+ ASSERT (TileSize <= (gSmmSmramStateMapOffset + sizeof (SMRAM_SAVE_STATE_MAP) - SMM_HANDLER_OFFSET));
//
// Allocate buffer for all of the tiles.
@@ -783,7 +845,7 @@ PiCpuSmmEntry (
for (Index = 0; Index < mMaxNumberOfCpus; Index++) {
mCpuHotPlugData.SmBase[Index] = (UINTN)Buffer + Index * TileSize - SMM_HANDLER_OFFSET;
gSmmCpuPrivate->CpuSaveStateSize[Index] = sizeof(SMRAM_SAVE_STATE_MAP);
- gSmmCpuPrivate->CpuSaveState[Index] = (VOID *)(mCpuHotPlugData.SmBase[Index] + SMRAM_SAVE_STATE_MAP_OFFSET);
+ gSmmCpuPrivate->CpuSaveState[Index] = (VOID *)(mCpuHotPlugData.SmBase[Index] + gSmmSmramStateMapOffset);
gSmmCpuPrivate->Operation[Index] = SmmCpuNone;
if (Index < mNumberOfCpus) {
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h
index 1cf85c1..8ad9d56 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h
@@ -56,6 +56,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#include <CpuHotPlugData.h>
#include <Register/Cpuid.h>
+#include <Register/Amd/Cpuid.h>
#include <Register/Msr.h>
#include "CpuService.h"
@@ -360,7 +361,21 @@ typedef struct {
UINT32 MsrIndex;
} MP_MSR_LOCK;
-#define SMM_PSD_OFFSET 0xfb00
+#define INTEL_SMM_PSD_OFFSET 0xfb00
+
+//
+// Definitions for AMD systems are based on contents of the
+// AMD64 Architecture Programmer's Manual
+// Volume 2: System Programming, Section 10 System-Management Mode
+//
+#define AMD_SMRAM_SAVE_STATE_MAP_OFFSET 0xfe00
+#define AMD_SMM_PSD_OFFSET 0xfc00
+
+//
+// External global variables for SMRAM offsets
+//
+extern UINT16 gSmmSmramStateMapOffset;
+extern UINT16 gSmmPsdOffset;
///
/// All global semaphores' pointer
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c
index 3ad5256..8707424 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c
@@ -1,13 +1,15 @@
/** @file
-Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials
-are licensed and made available under the terms and conditions of the BSD License
-which accompanies this distribution. The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php
+ Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
@@ -703,7 +705,7 @@ PatchSmmSaveStateMap (
TileCodeSize = GetSmiHandlerSize ();
TileCodeSize = ALIGN_VALUE(TileCodeSize, SIZE_4KB);
- TileDataSize = (SMRAM_SAVE_STATE_MAP_OFFSET - SMM_PSD_OFFSET) + sizeof (SMRAM_SAVE_STATE_MAP);
+ TileDataSize = (gSmmSmramStateMapOffset - gSmmPsdOffset) + sizeof (SMRAM_SAVE_STATE_MAP);
TileDataSize = ALIGN_VALUE(TileDataSize, SIZE_4KB);
TileSize = TileDataSize + TileCodeSize - 1;
TileSize = 2 * GetPowerOfTwo32 ((UINT32)TileSize);
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/SmramSaveState.c b/UefiCpuPkg/PiSmmCpuDxeSmm/SmramSaveState.c
index 3188d43..1f460b7 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/SmramSaveState.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/SmramSaveState.c
@@ -1,14 +1,16 @@
/** @file
-Provides services to access SMRAM Save State Map
+ Provides services to access SMRAM Save State Map
-Copyright (c) 2010 - 2017, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials
-are licensed and made available under the terms and conditions of the BSD License
-which accompanies this distribution. The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php
+ Copyright (c) 2010 - 2017, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
@@ -690,7 +692,7 @@ InstallSmiHandler (
//
// Initialize PROCESSOR_SMM_DESCRIPTOR
//
- Psd = (PROCESSOR_SMM_DESCRIPTOR *)(VOID *)((UINTN)SmBase + SMM_PSD_OFFSET);
+ Psd = (PROCESSOR_SMM_DESCRIPTOR *)(VOID *)((UINTN)SmBase + gSmmPsdOffset);
CopyMem (Psd, &gcPsd, sizeof (gcPsd));
Psd->SmmGdtPtr = (UINT64)GdtBase;
Psd->SmmGdtSize = (UINT32)GdtSize;
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/Semaphore.c b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/Semaphore.c
index 6dbcb08..3f52c7a 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/Semaphore.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/Semaphore.c
@@ -1,15 +1,17 @@
/** @file
-Semaphore mechanism to indicate to the BSP that an AP has exited SMM
-after SMBASE relocation.
+ Semaphore mechanism to indicate to the BSP that an AP has exited SMM
+ after SMBASE relocation.
-Copyright (c) 2009 - 2015, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials
-are licensed and made available under the terms and conditions of the BSD License
-which accompanies this distribution. The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php
+ Copyright (c) 2009 - 2015, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
@@ -51,7 +53,7 @@ SemaphoreHook (
mRebasedFlag = RebasedFlag;
mRebasedFlagAddr32 = (UINT32)(UINTN)mRebasedFlag;
- CpuState = (SMRAM_SAVE_STATE_MAP *)(UINTN)(SMM_DEFAULT_SMBASE + SMRAM_SAVE_STATE_MAP_OFFSET);
+ CpuState = (SMRAM_SAVE_STATE_MAP *)(UINTN)(SMM_DEFAULT_SMBASE + gSmmSmramStateMapOffset);
mSmmRelocationOriginalAddress = HookReturnFromSmm (
CpuIndex,
CpuState,
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.S b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.S
index 600d862..c3405ec 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.S
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.S
@@ -1,6 +1,8 @@
#------------------------------------------------------------------------------
#
# Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>
+#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
@@ -26,6 +28,9 @@ ASM_GLOBAL ASM_PFX(gSmiStack)
ASM_GLOBAL ASM_PFX(gSmbase)
ASM_GLOBAL ASM_PFX(mXdSupported)
ASM_GLOBAL ASM_PFX(gSmiHandlerIdtr)
+ASM_GLOBAL ASM_PFX(gSmmPsdOffset)
+ASM_GLOBAL ASM_PFX(gPsdGdtSize)
+ASM_GLOBAL ASM_PFX(gPsdGdtPtr)
.equ MSR_IA32_MISC_ENABLE, 0x1A0
.equ MSR_EFER, 0xc0000080
@@ -34,12 +39,13 @@ ASM_GLOBAL ASM_PFX(gSmiHandlerIdtr)
#
# Constants relating to PROCESSOR_SMM_DESCRIPTOR
#
-.equ DSC_OFFSET, 0xfb00
-.equ DSC_GDTPTR, 0x30
-.equ DSC_GDTSIZ, 0x38
-.equ DSC_CS, 14
-.equ DSC_DS, 16
-.equ DSC_SS, 18
+# .equ DSC_OFFSET, 0xfb00
+# .equ DSC_GDTPTR, 0x30
+# .equ DSC_GDTSIZ, 0x38
+#
+.equ DSC_CS, 14
+.equ DSC_DS, 16
+.equ DSC_SS, 18
.equ DSC_OTHERSEG, 20
#
# Constants relating to CPU State Save Area
@@ -49,9 +55,9 @@ ASM_GLOBAL ASM_PFX(gSmiHandlerIdtr)
.equ PROTECT_MODE_CS, 0x08
.equ PROTECT_MODE_DS, 0x20
-.equ LONG_MODE_CS, 0x38
-.equ TSS_SEGMENT, 0x40
-.equ GDT_SIZE, 0x50
+.equ LONG_MODE_CS, 0x38
+.equ TSS_SEGMENT, 0x40
+.equ GDT_SIZE, 0x50
.text
@@ -70,12 +76,12 @@ _SmiEntryPoint:
# fix GDT descriptor
#
.byte 0x2e,0xa1 # mov ax, cs:[offset16]
- .word DSC_OFFSET + DSC_GDTSIZ
+ASM_PFX(gPsdGdtSize): .space 2 # .word DSC_OFFSET + DSC_GDTSIZ
.byte 0x48 # dec ax
.byte 0x2e
movl %eax, (%rdi) # mov cs:[bx], ax
.byte 0x66,0x2e,0xa1 # mov eax, cs:[offset16]
- .word DSC_OFFSET + DSC_GDTPTR
+ASM_PFX(gPsdGdtPtr): .space 2 # .word DSC_OFFSET + DSC_GDTPTR
.byte 0x2e
movw %ax, 2(%rdi)
.byte 0x66,0x2e
@@ -182,7 +188,11 @@ Base:
LongMode: # long mode (64-bit code) starts here
movabsq $ASM_PFX(gSmiHandlerIdtr), %rax
lidt (%rax)
- lea (DSC_OFFSET)(%rdi), %ebx
+
+ movl $ASM_PFX(gSmmPsdOffset), %ebx # lea (DSC_OFFSET)(%rdi), %ebx
+ movzxw (%ebx), %rsi
+ leal (%rdi, %rsi), %ebx
+
movw DSC_DS(%rbx), %ax
movl %eax,%ds
movw DSC_OTHERSEG(%rbx), %ax
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.asm b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.asm
index c74f82a..72eeb1a 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.asm
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.asm
@@ -1,5 +1,7 @@
;------------------------------------------------------------------------------ ;
; Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.<BR>
+; Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>
+;
; This program and the accompanying materials
; are licensed and made available under the terms and conditions of the BSD License
; which accompanies this distribution. The full text of the license may be found at
@@ -31,6 +33,10 @@ EXTERNDEF gSmiStack:DWORD
EXTERNDEF gSmbase:DWORD
EXTERNDEF mXdSupported:BYTE
EXTERNDEF gSmiHandlerIdtr:FWORD
+EXTERNDEF gSmmPsdOffset:WORD
+EXTERNDEF gPsdGdtSize:WORD
+EXTERNDEF gPsdGdtPtr:WORD
+
MSR_IA32_MISC_ENABLE EQU 1A0h
MSR_EFER EQU 0c0000080h
@@ -39,9 +45,10 @@ MSR_EFER_XD EQU 0800h
;
; Constants relating to PROCESSOR_SMM_DESCRIPTOR
;
-DSC_OFFSET EQU 0fb00h
-DSC_GDTPTR EQU 30h
-DSC_GDTSIZ EQU 38h
+: DSC_OFFSET EQU 0fb00h
+; DSC_GDTPTR EQU 30h
+; DSC_GDTSIZ EQU 38h
+;
DSC_CS EQU 14
DSC_DS EQU 16
DSC_SS EQU 18
@@ -73,12 +80,12 @@ _SmiEntryPoint:
DW offset _GdtDesc - _SmiEntryPoint + 8000h ; bx = GdtDesc offset
; fix GDT descriptor
DB 2eh, 0a1h ; mov ax, cs:[offset16]
- DW DSC_OFFSET + DSC_GDTSIZ
+gPsdGdtSize DW ? ; DSC_OFFSET + DSC_GDTSIZ
DB 48h ; dec ax
DB 2eh
mov [rdi], eax ; mov cs:[bx], ax
DB 66h, 2eh, 0a1h ; mov eax, cs:[offset16]
- DW DSC_OFFSET + DSC_GDTPTR
+gPsdGdtPtr DW ? ; DSC_OFFSET + DSC_GDTPTR
DB 2eh
mov [rdi + 2], ax ; mov cs:[bx + 2], eax
DB 66h, 2eh
@@ -177,7 +184,10 @@ Base:
@LongMode: ; long mode (64-bit code) starts here
mov rax, offset gSmiHandlerIdtr
lidt fword ptr [rax]
- lea ebx, [rdi + DSC_OFFSET]
+
+ movzx rsi, word ptr [gSmmPsdOffset] ; lea ebx, [rdi + DSC_OFFSET]
+ lea ebx, [rdi + rsi] ;
+
mov ax, [rbx + DSC_DS]
mov ds, eax
mov ax, [rbx + DSC_OTHERSEG]
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm
index c3c094f..3a841c9 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm
@@ -1,5 +1,7 @@
;------------------------------------------------------------------------------ ;
; Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
+; Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>
+;
; This program and the accompanying materials
; are licensed and made available under the terms and conditions of the BSD License
; which accompanies this distribution. The full text of the license may be found at
@@ -29,12 +31,13 @@
;
; Constants relating to PROCESSOR_SMM_DESCRIPTOR
;
-%define DSC_OFFSET 0xfb00
-%define DSC_GDTPTR 0x30
-%define DSC_GDTSIZ 0x38
-%define DSC_CS 14
-%define DSC_DS 16
-%define DSC_SS 18
+; %define DSC_OFFSET 0xfb00
+; %define DSC_GDTPTR 0x30
+; %define DSC_GDTSIZ 0x38
+;
+%define DSC_CS 14
+%define DSC_DS 16
+%define DSC_SS 18
%define DSC_OTHERSEG 20
;
; Constants relating to CPU State Save Area
@@ -44,9 +47,9 @@
%define PROTECT_MODE_CS 0x8
%define PROTECT_MODE_DS 0x20
-%define LONG_MODE_CS 0x38
-%define TSS_SEGMENT 0x40
-%define GDT_SIZE 0x50
+%define LONG_MODE_CS 0x38
+%define TSS_SEGMENT 0x40
+%define GDT_SIZE 0x50
extern ASM_PFX(SmiRendezvous)
extern ASM_PFX(gSmiHandlerIdtr)
@@ -60,6 +63,10 @@ global ASM_PFX(gSmiCr3)
global ASM_PFX(gcSmiHandlerTemplate)
global ASM_PFX(gcSmiHandlerSize)
+extern ASM_PFX(gSmmPsdOffset)
+global ASM_PFX(gPsdGdtSize)
+global ASM_PFX(gPsdGdtPtr)
+
DEFAULT REL
SECTION .text
@@ -67,10 +74,18 @@ BITS 16
ASM_PFX(gcSmiHandlerTemplate):
_SmiEntryPoint:
mov bx, _GdtDesc - _SmiEntryPoint + 0x8000
- mov ax,[cs:DSC_OFFSET + DSC_GDTSIZ]
+
+ mov eax, ASM_PFX(gPsdGdtSize) ; mov ax, [cs:DSC_OFFSET + DSC_GDTSIZ]
+ mov si, [cs:eax] ;
+ mov ax, [cs:si] ;
+
dec ax
mov [cs:bx], ax
- mov eax, [cs:DSC_OFFSET + DSC_GDTPTR]
+
+ mov eax, ASM_PFX(gPsdGdtPtr) ; mov eax, [cs:DSC_OFFSET + DSC_GDTPTR]
+ mov si, [cs:eax] ;
+ mov eax, [cs:si] ;
+
mov [cs:bx + 2], eax
o32 lgdt [cs:bx] ; lgdt fword ptr cs:[bx]
mov ax, PROTECT_MODE_CS
@@ -160,7 +175,10 @@ Base:
@LongMode: ; long mode (64-bit code) starts here
mov rax, ASM_PFX(gSmiHandlerIdtr)
lidt [rax]
- lea ebx, [rdi + DSC_OFFSET]
+
+ movzx rsi, word [ASM_PFX(gSmmPsdOffset)] ; lea ebx, [rdi + DSC_OFFSET]
+ lea ebx, [rdi + rsi]
+
mov ax, [rbx + DSC_DS]
mov ds, eax
mov ax, [rbx + DSC_OTHERSEG]
@@ -220,5 +238,8 @@ _SmiHandler:
.1:
rsm
+ASM_PFX(gPsdGdtSize): RESW 1
+ASM_PFX(gPsdGdtPtr) : RESW 1
+
gcSmiHandlerSize DW $ - _SmiEntryPoint
--
2.7.4
^ permalink raw reply related [flat|nested] 30+ messages in thread
* Re: [PATCH v5 1/2] UefiCpuPkg/SmmCpuFeaturesLib: Use global variables to replace macros
2017-10-11 19:45 ` [PATCH v5 1/2] UefiCpuPkg/SmmCpuFeaturesLib: Use global variables to replace macros Leo Duran
@ 2017-10-12 21:40 ` Paolo Bonzini
2017-10-14 15:51 ` Duran, Leo
2017-10-17 14:19 ` Duran, Leo
1 sibling, 1 reply; 30+ messages in thread
From: Paolo Bonzini @ 2017-10-12 21:40 UTC (permalink / raw)
To: Leo Duran, edk2-devel
Cc: Ruiyu Ni, Jordan Justen, Liming Gao, Jiewen Yao, Michael D Kinney
On 11/10/2017 21:45, Leo Duran wrote:
> + // Override PSD offset for AMD
> + //
> + if (SmmStandardSignatureIsAuthenticAMD ()) {
> + gStmPsdOffset = AMD_SMM_PSD_OFFSET;
> + }
> +
I think the right thing to do here would be to use the SMM state save
map revision; in the case of AMD, the low 16 bits (IIRC) would be 0x0064.
Paolo
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH v5 0/2] Enhanced SMM support for AMD-based x86 systems.
2017-10-11 19:45 [PATCH v5 0/2] Enhanced SMM support for AMD-based x86 systems Leo Duran
2017-10-11 19:45 ` [PATCH v5 1/2] UefiCpuPkg/SmmCpuFeaturesLib: Use global variables to replace macros Leo Duran
2017-10-11 19:45 ` [PATCH v5 2/2] UefiCpuPkg/PiSmmCpuDxeSmm: " Leo Duran
@ 2017-10-13 1:52 ` Yao, Jiewen
2017-10-13 2:36 ` Yao, Jiewen
` (3 more replies)
2 siblings, 4 replies; 30+ messages in thread
From: Yao, Jiewen @ 2017-10-13 1:52 UTC (permalink / raw)
To: Leo Duran, edk2-devel@lists.01.org
HI Leo
Thank you very much. This patch looks good to me in general.
Some minor comment:
1) For AMD smm save state.
I saw Paolo gave the comment on how to detect AMD save state. I do not have strong opinion on that. I think you and Paolo can make decision.
I recommend we move AMD_SMRAM_SAVE_STATE_MAP_OFFSET to UefiCpuPkg\Include\Register\Amd\SmramSaveStateMap.h, because it is standard.
+//
+// Definitions for AMD systems are based on contents of the
+// AMD64 Architecture Programmer's Manual
+// Volume 2: System Programming, Section 10 System-Management Mode
+//
+#define AMD_SMRAM_SAVE_STATE_MAP_OFFSET 0xfe00
We can leave AMD_SMM_PSD_OFFSET in UefiCpuPkg/PiSmmCpuDxeSmm, if it is implementation specific.
+#define AMD_SMM_PSD_OFFSET 0xfc00
2) For Intel save state, I assume you already did some test to make sure there is no regression.
If so, would you please add some description on what test you have done?
For example,
If both IA32 and X64 are validated?
If all three .S, .asm, .nasm are validated?
If OS boot and S3 resume are validated?
If you did any other test, please also add.
Thank you
Yao Jiewen
> -----Original Message-----
> From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf Of Leo
> Duran
> Sent: Thursday, October 12, 2017 3:45 AM
> To: edk2-devel@lists.01.org
> Subject: [edk2] [PATCH v5 0/2] Enhanced SMM support for AMD-based x86
> systems.
>
> This patch-set replaces Intel-specific macros with global variables
> to provide support for AMD-based x86 systems.
>
> The replaced macros are:
> 1) SRAM_SAVE_STATE_MAP_OFFSET
> 2) TXT_SMM_PSD_OFFSET
> 3) SMM_PSD_OFFSET
>
> Changes since v4:
> Make runtime CPUID checks and use global variables instead of PCD's.
>
> Changes since v3:
> Correction on cover letter.
>
> Changes since v2:
> The intent of this revision is to maintain compatibility with existing
> packages. To that end, changes to OvmgfPkg and QuarkSocPkg are reverted.
> Moreover, pertinent macros are replaced in the C code, rather than on
> header files that are shared globally.
>
> Changes since v1:
> Revision to Cc list for UefiCpuPkg.
>
> Leo Duran (2):
> UefiCpuPkg/SmmCpuFeaturesLib: Use global variables to replace macros
> UefiCpuPkg/PiSmmCpuDxeSmm: Use global variables to replace macros
>
> .../Library/SmmCpuFeaturesLib/Ia32/SmiEntry.S | 28 ++++++---
> .../Library/SmmCpuFeaturesLib/Ia32/SmiEntry.asm | 29 ++++++---
> .../Library/SmmCpuFeaturesLib/Ia32/SmiEntry.nasm | 43 +++++++++----
> UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCommon.h | 48
> +++++++++++++++
> .../Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c | 59
> +++++++++++++++---
> .../SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf | 3 +
> .../SmmCpuFeaturesLib/SmmCpuFeaturesLibStm.inf | 3 +
> UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c | 39 ++++++++++--
> .../Library/SmmCpuFeaturesLib/X64/SmiEntry.S | 28 ++++++---
> .../Library/SmmCpuFeaturesLib/X64/SmiEntry.asm | 30 ++++++---
> .../Library/SmmCpuFeaturesLib/X64/SmiEntry.nasm | 47 ++++++++++----
> UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/Semaphore.c | 22 ++++---
> UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.S | 28 ++++++---
> UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.asm | 21 +++++--
> UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm | 43
> +++++++++----
> UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c | 72
> ++++++++++++++++++++--
> UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h | 17 ++++-
> UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c | 18 +++---
> UefiCpuPkg/PiSmmCpuDxeSmm/SmramSaveState.c | 20 +++---
> UefiCpuPkg/PiSmmCpuDxeSmm/X64/Semaphore.c | 22 ++++---
> UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.S | 34 ++++++----
> UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.asm | 22 +++++--
> UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm | 45
> ++++++++++----
> 23 files changed, 547 insertions(+), 174 deletions(-)
> create mode 100644 UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCommon.h
>
> --
> 2.7.4
>
> _______________________________________________
> edk2-devel mailing list
> edk2-devel@lists.01.org
> https://lists.01.org/mailman/listinfo/edk2-devel
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH v5 0/2] Enhanced SMM support for AMD-based x86 systems.
2017-10-13 1:52 ` [PATCH v5 0/2] Enhanced SMM support for AMD-based x86 systems Yao, Jiewen
@ 2017-10-13 2:36 ` Yao, Jiewen
2017-10-14 16:04 ` Duran, Leo
` (2 subsequent siblings)
3 siblings, 0 replies; 30+ messages in thread
From: Yao, Jiewen @ 2017-10-13 2:36 UTC (permalink / raw)
To: Yao, Jiewen, Leo Duran, edk2-devel@lists.01.org
Hi Leo
I just have another thought, when I review code again.
Do we *have to* make AMD SMM PSD offset to 0xfc00?
SMM PSD is just a *software* concept. Not hardware requirement.
What is broken, if we design AMD SMM PSD offset to be 0xfb00, (same as existing code)?
Thank you
Yao Jiewen
From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf Of Yao, Jiewen
Sent: Friday, October 13, 2017 9:53 AM
To: Leo Duran <leo.duran@amd.com>; edk2-devel@lists.01.org
Subject: Re: [edk2] [PATCH v5 0/2] Enhanced SMM support for AMD-based x86 systems.
HI Leo
Thank you very much. This patch looks good to me in general.
Some minor comment:
1) For AMD smm save state.
I saw Paolo gave the comment on how to detect AMD save state. I do not have strong opinion on that. I think you and Paolo can make decision.
I recommend we move AMD_SMRAM_SAVE_STATE_MAP_OFFSET to UefiCpuPkg\Include\Register\Amd\SmramSaveStateMap.h, because it is standard.
+//
+// Definitions for AMD systems are based on contents of the
+// AMD64 Architecture Programmer's Manual
+// Volume 2: System Programming, Section 10 System-Management Mode
+//
+#define AMD_SMRAM_SAVE_STATE_MAP_OFFSET 0xfe00
We can leave AMD_SMM_PSD_OFFSET in UefiCpuPkg/PiSmmCpuDxeSmm, if it is implementation specific.
+#define AMD_SMM_PSD_OFFSET 0xfc00
2) For Intel save state, I assume you already did some test to make sure there is no regression.
If so, would you please add some description on what test you have done?
For example,
If both IA32 and X64 are validated?
If all three .S, .asm, .nasm are validated?
If OS boot and S3 resume are validated?
If you did any other test, please also add.
Thank you
Yao Jiewen
> -----Original Message-----
> From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf Of Leo
> Duran
> Sent: Thursday, October 12, 2017 3:45 AM
> To: edk2-devel@lists.01.org<mailto:edk2-devel@lists.01.org>
> Subject: [edk2] [PATCH v5 0/2] Enhanced SMM support for AMD-based x86
> systems.
>
> This patch-set replaces Intel-specific macros with global variables
> to provide support for AMD-based x86 systems.
>
> The replaced macros are:
> 1) SRAM_SAVE_STATE_MAP_OFFSET
> 2) TXT_SMM_PSD_OFFSET
> 3) SMM_PSD_OFFSET
>
> Changes since v4:
> Make runtime CPUID checks and use global variables instead of PCD's.
>
> Changes since v3:
> Correction on cover letter.
>
> Changes since v2:
> The intent of this revision is to maintain compatibility with existing
> packages. To that end, changes to OvmgfPkg and QuarkSocPkg are reverted.
> Moreover, pertinent macros are replaced in the C code, rather than on
> header files that are shared globally.
>
> Changes since v1:
> Revision to Cc list for UefiCpuPkg.
>
> Leo Duran (2):
> UefiCpuPkg/SmmCpuFeaturesLib: Use global variables to replace macros
> UefiCpuPkg/PiSmmCpuDxeSmm: Use global variables to replace macros
>
> .../Library/SmmCpuFeaturesLib/Ia32/SmiEntry.S | 28 ++++++---
> .../Library/SmmCpuFeaturesLib/Ia32/SmiEntry.asm | 29 ++++++---
> .../Library/SmmCpuFeaturesLib/Ia32/SmiEntry.nasm | 43 +++++++++----
> UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCommon.h | 48
> +++++++++++++++
> .../Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c | 59
> +++++++++++++++---
> .../SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf | 3 +
> .../SmmCpuFeaturesLib/SmmCpuFeaturesLibStm.inf | 3 +
> UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c | 39 ++++++++++--
> .../Library/SmmCpuFeaturesLib/X64/SmiEntry.S | 28 ++++++---
> .../Library/SmmCpuFeaturesLib/X64/SmiEntry.asm | 30 ++++++---
> .../Library/SmmCpuFeaturesLib/X64/SmiEntry.nasm | 47 ++++++++++----
> UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/Semaphore.c | 22 ++++---
> UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.S | 28 ++++++---
> UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.asm | 21 +++++--
> UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm | 43
> +++++++++----
> UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c | 72
> ++++++++++++++++++++--
> UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h | 17 ++++-
> UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c | 18 +++---
> UefiCpuPkg/PiSmmCpuDxeSmm/SmramSaveState.c | 20 +++---
> UefiCpuPkg/PiSmmCpuDxeSmm/X64/Semaphore.c | 22 ++++---
> UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.S | 34 ++++++----
> UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.asm | 22 +++++--
> UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm | 45
> ++++++++++----
> 23 files changed, 547 insertions(+), 174 deletions(-)
> create mode 100644 UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCommon.h
>
> --
> 2.7.4
>
> _______________________________________________
> edk2-devel mailing list
> edk2-devel@lists.01.org<mailto:edk2-devel@lists.01.org>
> https://lists.01.org/mailman/listinfo/edk2-devel
_______________________________________________
edk2-devel mailing list
edk2-devel@lists.01.org<mailto:edk2-devel@lists.01.org>
https://lists.01.org/mailman/listinfo/edk2-devel
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH v5 1/2] UefiCpuPkg/SmmCpuFeaturesLib: Use global variables to replace macros
2017-10-12 21:40 ` Paolo Bonzini
@ 2017-10-14 15:51 ` Duran, Leo
2017-10-15 15:26 ` Paolo Bonzini
0 siblings, 1 reply; 30+ messages in thread
From: Duran, Leo @ 2017-10-14 15:51 UTC (permalink / raw)
To: Paolo Bonzini, edk2-devel@lists.01.org
Cc: Ruiyu Ni, Jordan Justen, Liming Gao, Jiewen Yao, Michael D Kinney
> -----Original Message-----
> From: Paolo Bonzini [mailto:paolo.bonzini@gmail.com] On Behalf Of Paolo
> Bonzini
> Sent: Thursday, October 12, 2017 4:41 PM
> To: Duran, Leo <leo.duran@amd.com>; edk2-devel@lists.01.org
> Cc: Ruiyu Ni <ruiyu.ni@intel.com>; Jordan Justen
> <jordan.l.justen@intel.com>; Liming Gao <liming.gao@intel.com>; Jiewen
> Yao <jiewen.yao@intel.com>; Michael D Kinney
> <michael.d.kinney@intel.com>
> Subject: Re: [edk2] [PATCH v5 1/2] UefiCpuPkg/SmmCpuFeaturesLib: Use
> global variables to replace macros
>
> On 11/10/2017 21:45, Leo Duran wrote:
> > + // Override PSD offset for AMD
> > + //
> > + if (SmmStandardSignatureIsAuthenticAMD ()) {
> > + gStmPsdOffset = AMD_SMM_PSD_OFFSET; }
> > +
>
> I think the right thing to do here would be to use the SMM state save map
> revision; in the case of AMD, the low 16 bits (IIRC) would be 0x0064.
>
> Paolo
Hi Paolo,
In its current form, the patch merely replaces the macros with global variables, and does not attempt to disrupt the existing execution flow.
But perhaps you can provide a bit more context (or an example) so that may better understand your suggestion?
Thanks,
Leo.
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH v5 0/2] Enhanced SMM support for AMD-based x86 systems.
2017-10-13 1:52 ` [PATCH v5 0/2] Enhanced SMM support for AMD-based x86 systems Yao, Jiewen
2017-10-13 2:36 ` Yao, Jiewen
@ 2017-10-14 16:04 ` Duran, Leo
2017-10-15 0:58 ` Yao, Jiewen
2017-10-14 16:08 ` Duran, Leo
2017-10-16 17:13 ` Paolo Bonzini
3 siblings, 1 reply; 30+ messages in thread
From: Duran, Leo @ 2017-10-14 16:04 UTC (permalink / raw)
To: Yao, Jiewen, edk2-devel@lists.01.org
> -----Original Message-----
> From: Yao, Jiewen [mailto:jiewen.yao@intel.com]
> Sent: Thursday, October 12, 2017 8:53 PM
> To: Duran, Leo <leo.duran@amd.com>; edk2-devel@lists.01.org
> Subject: RE: [edk2] [PATCH v5 0/2] Enhanced SMM support for AMD-based
> x86 systems.
>
> HI Leo
> Thank you very much. This patch looks good to me in general.
>
> Some minor comment:
>
> 1) For AMD smm save state.
> I saw Paolo gave the comment on how to detect AMD save state. I do not
> have strong opinion on that. I think you and Paolo can make decision.
>
> I recommend we move AMD_SMRAM_SAVE_STATE_MAP_OFFSET to
> UefiCpuPkg\Include\Register\Amd\SmramSaveStateMap.h, because it is
> standard.
Hi Yao,
Sure thing, I will do that.
Leo
> +//
> +// Definitions for AMD systems are based on contents of the // AMD64
> +Architecture Programmer's Manual // Volume 2: System Programming,
> +Section 10 System-Management Mode // #define
> +AMD_SMRAM_SAVE_STATE_MAP_OFFSET 0xfe00
>
> We can leave AMD_SMM_PSD_OFFSET in UefiCpuPkg/PiSmmCpuDxeSmm,
> if it is implementation specific.
> +#define AMD_SMM_PSD_OFFSET 0xfc00
>
>
>
> 2) For Intel save state, I assume you already did some test to make sure
> there is no regression.
> If so, would you please add some description on what test you have done?
> For example,
> If both IA32 and X64 are validated?
> If all three .S, .asm, .nasm are validated?
> If OS boot and S3 resume are validated?
>
> If you did any other test, please also add.
>
Hi Yao,
I have not done runtime validation testing.
Instead, I tested the assembly code snippets in a vacuum (in their .asm, .nasm, and .S forms),
to ensure the source produced the expected compiled code, and the expected execution.
So any runtime 'Tested-by' would be greatly appreciated
Thanks,
Leo.
> Thank you
> Yao Jiewen
>
>
> > -----Original Message-----
> > From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf Of
> > Leo Duran
> > Sent: Thursday, October 12, 2017 3:45 AM
> > To: edk2-devel@lists.01.org
> > Subject: [edk2] [PATCH v5 0/2] Enhanced SMM support for AMD-based x86
> > systems.
> >
> > This patch-set replaces Intel-specific macros with global variables to
> > provide support for AMD-based x86 systems.
> >
> > The replaced macros are:
> > 1) SRAM_SAVE_STATE_MAP_OFFSET
> > 2) TXT_SMM_PSD_OFFSET
> > 3) SMM_PSD_OFFSET
> >
> > Changes since v4:
> > Make runtime CPUID checks and use global variables instead of PCD's.
> >
> > Changes since v3:
> > Correction on cover letter.
> >
> > Changes since v2:
> > The intent of this revision is to maintain compatibility with existing
> > packages. To that end, changes to OvmgfPkg and QuarkSocPkg are
> reverted.
> > Moreover, pertinent macros are replaced in the C code, rather than on
> > header files that are shared globally.
> >
> > Changes since v1:
> > Revision to Cc list for UefiCpuPkg.
> >
> > Leo Duran (2):
> > UefiCpuPkg/SmmCpuFeaturesLib: Use global variables to replace macros
> > UefiCpuPkg/PiSmmCpuDxeSmm: Use global variables to replace macros
> >
> > .../Library/SmmCpuFeaturesLib/Ia32/SmiEntry.S | 28 ++++++---
> > .../Library/SmmCpuFeaturesLib/Ia32/SmiEntry.asm | 29 ++++++---
> > .../Library/SmmCpuFeaturesLib/Ia32/SmiEntry.nasm | 43 +++++++++----
> > UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCommon.h | 48
> > +++++++++++++++
> > .../Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c | 59
> > +++++++++++++++---
> > .../SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf | 3 +
> > .../SmmCpuFeaturesLib/SmmCpuFeaturesLibStm.inf | 3 +
> > UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c | 39 ++++++++++-
> -
> > .../Library/SmmCpuFeaturesLib/X64/SmiEntry.S | 28 ++++++---
> > .../Library/SmmCpuFeaturesLib/X64/SmiEntry.asm | 30 ++++++---
> > .../Library/SmmCpuFeaturesLib/X64/SmiEntry.nasm | 47 ++++++++++----
> > UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/Semaphore.c | 22 ++++---
> > UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.S | 28 ++++++---
> > UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.asm | 21 +++++--
> > UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm | 43
> > +++++++++----
> > UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c | 72
> > ++++++++++++++++++++--
> > UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h | 17 ++++-
> > UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c | 18
> +++---
> > UefiCpuPkg/PiSmmCpuDxeSmm/SmramSaveState.c | 20 +++---
> > UefiCpuPkg/PiSmmCpuDxeSmm/X64/Semaphore.c | 22 ++++---
> > UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.S | 34 ++++++----
> > UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.asm | 22 +++++--
> > UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm | 45
> > ++++++++++----
> > 23 files changed, 547 insertions(+), 174 deletions(-) create mode
> > 100644 UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCommon.h
> >
> > --
> > 2.7.4
> >
> > _______________________________________________
> > edk2-devel mailing list
> > edk2-devel@lists.01.org
> > https://lists.01.org/mailman/listinfo/edk2-devel
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH v5 0/2] Enhanced SMM support for AMD-based x86 systems.
2017-10-13 1:52 ` [PATCH v5 0/2] Enhanced SMM support for AMD-based x86 systems Yao, Jiewen
2017-10-13 2:36 ` Yao, Jiewen
2017-10-14 16:04 ` Duran, Leo
@ 2017-10-14 16:08 ` Duran, Leo
2017-10-16 17:13 ` Paolo Bonzini
3 siblings, 0 replies; 30+ messages in thread
From: Duran, Leo @ 2017-10-14 16:08 UTC (permalink / raw)
To: Yao, Jiewen, edk2-devel@lists.01.org
> -----Original Message-----
> From: Yao, Jiewen [mailto:jiewen.yao@intel.com]
> Sent: Thursday, October 12, 2017 9:37 PM
> To: Duran, Leo <leo.duran@amd.com>; edk2-devel@lists.01.org
> Subject: RE: [edk2] [PATCH v5 0/2] Enhanced SMM support for AMD-based
> x86 systems.
> Hi Leo
> I just have another thought, when I review code again.
>
> Do we *have to* make AMD SMM PSD offset to 0xfc00?
> SMM PSD is just a *software* concept. Not hardware requirement.
> What is broken, if we design AMD SMM PSD offset to be 0xfb00, (same as existing code)?
>
HI Yao,
I will look further into this to see if it's possible to re-use the same offset without too much pain.
Thanks,
Leo.
> Thank you
> Yao Jiewen
> -----Original Message-----
> From: Yao, Jiewen [mailto:jiewen.yao@intel.com]
> Sent: Thursday, October 12, 2017 8:53 PM
> To: Duran, Leo <leo.duran@amd.com>; edk2-devel@lists.01.org
> Subject: RE: [edk2] [PATCH v5 0/2] Enhanced SMM support for AMD-based
> x86 systems.
>
> HI Leo
> Thank you very much. This patch looks good to me in general.
>
> Some minor comment:
>
> 1) For AMD smm save state.
> I saw Paolo gave the comment on how to detect AMD save state. I do not
> have strong opinion on that. I think you and Paolo can make decision.
>
> I recommend we move AMD_SMRAM_SAVE_STATE_MAP_OFFSET to
> UefiCpuPkg\Include\Register\Amd\SmramSaveStateMap.h, because it is
> standard.
> +//
> +// Definitions for AMD systems are based on contents of the // AMD64
> +Architecture Programmer's Manual // Volume 2: System Programming,
> +Section 10 System-Management Mode // #define
> +AMD_SMRAM_SAVE_STATE_MAP_OFFSET 0xfe00
>
> We can leave AMD_SMM_PSD_OFFSET in UefiCpuPkg/PiSmmCpuDxeSmm,
> if it is implementation specific.
> +#define AMD_SMM_PSD_OFFSET 0xfc00
>
>
>
> 2) For Intel save state, I assume you already did some test to make sure
> there is no regression.
> If so, would you please add some description on what test you have done?
> For example,
> If both IA32 and X64 are validated?
> If all three .S, .asm, .nasm are validated?
> If OS boot and S3 resume are validated?
>
> If you did any other test, please also add.
>
> Thank you
> Yao Jiewen
>
>
> > -----Original Message-----
> > From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf Of
> > Leo Duran
> > Sent: Thursday, October 12, 2017 3:45 AM
> > To: edk2-devel@lists.01.org
> > Subject: [edk2] [PATCH v5 0/2] Enhanced SMM support for AMD-based x86
> > systems.
> >
> > This patch-set replaces Intel-specific macros with global variables to
> > provide support for AMD-based x86 systems.
> >
> > The replaced macros are:
> > 1) SRAM_SAVE_STATE_MAP_OFFSET
> > 2) TXT_SMM_PSD_OFFSET
> > 3) SMM_PSD_OFFSET
> >
> > Changes since v4:
> > Make runtime CPUID checks and use global variables instead of PCD's.
> >
> > Changes since v3:
> > Correction on cover letter.
> >
> > Changes since v2:
> > The intent of this revision is to maintain compatibility with existing
> > packages. To that end, changes to OvmgfPkg and QuarkSocPkg are
> reverted.
> > Moreover, pertinent macros are replaced in the C code, rather than on
> > header files that are shared globally.
> >
> > Changes since v1:
> > Revision to Cc list for UefiCpuPkg.
> >
> > Leo Duran (2):
> > UefiCpuPkg/SmmCpuFeaturesLib: Use global variables to replace macros
> > UefiCpuPkg/PiSmmCpuDxeSmm: Use global variables to replace macros
> >
> > .../Library/SmmCpuFeaturesLib/Ia32/SmiEntry.S | 28 ++++++---
> > .../Library/SmmCpuFeaturesLib/Ia32/SmiEntry.asm | 29 ++++++---
> > .../Library/SmmCpuFeaturesLib/Ia32/SmiEntry.nasm | 43 +++++++++----
> > UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCommon.h | 48
> > +++++++++++++++
> > .../Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c | 59
> > +++++++++++++++---
> > .../SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf | 3 +
> > .../SmmCpuFeaturesLib/SmmCpuFeaturesLibStm.inf | 3 +
> > UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c | 39 ++++++++++-
> -
> > .../Library/SmmCpuFeaturesLib/X64/SmiEntry.S | 28 ++++++---
> > .../Library/SmmCpuFeaturesLib/X64/SmiEntry.asm | 30 ++++++---
> > .../Library/SmmCpuFeaturesLib/X64/SmiEntry.nasm | 47 ++++++++++----
> > UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/Semaphore.c | 22 ++++---
> > UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.S | 28 ++++++---
> > UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.asm | 21 +++++--
> > UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm | 43
> > +++++++++----
> > UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c | 72
> > ++++++++++++++++++++--
> > UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h | 17 ++++-
> > UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c | 18
> +++---
> > UefiCpuPkg/PiSmmCpuDxeSmm/SmramSaveState.c | 20 +++---
> > UefiCpuPkg/PiSmmCpuDxeSmm/X64/Semaphore.c | 22 ++++---
> > UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.S | 34 ++++++----
> > UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.asm | 22 +++++--
> > UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm | 45
> > ++++++++++----
> > 23 files changed, 547 insertions(+), 174 deletions(-) create mode
> > 100644 UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCommon.h
> >
> > --
> > 2.7.4
> >
> > _______________________________________________
> > edk2-devel mailing list
> > edk2-devel@lists.01.org
> > https://lists.01.org/mailman/listinfo/edk2-devel
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH v5 0/2] Enhanced SMM support for AMD-based x86 systems.
2017-10-14 16:04 ` Duran, Leo
@ 2017-10-15 0:58 ` Yao, Jiewen
2017-10-16 17:06 ` Laszlo Ersek
0 siblings, 1 reply; 30+ messages in thread
From: Yao, Jiewen @ 2017-10-15 0:58 UTC (permalink / raw)
To: Duran, Leo; +Cc: edk2-devel@lists.01.org, Yao, Jiewen, Laszlo Ersek
for runtime test, I recommend using ovmf. You don't need real hardware. It can run both 32bit or 64bit. It can run in both Linux and windows.
You need use -D SMM_REQUIRE option to build ovmf.
If you have any problem, Laszlo is the good contact.
thank you!
Yao, Jiewen
> 在 2017年10月15日，上午12:04，Duran, Leo <leo.duran@amd.com> 写道：
>
>
>
>> -----Original Message-----
>> From: Yao, Jiewen [mailto:jiewen.yao@intel.com]
>> Sent: Thursday, October 12, 2017 8:53 PM
>> To: Duran, Leo <leo.duran@amd.com>; edk2-devel@lists.01.org
>> Subject: RE: [edk2] [PATCH v5 0/2] Enhanced SMM support for AMD-based
>> x86 systems.
>>
>> HI Leo
>> Thank you very much. This patch looks good to me in general.
>>
>> Some minor comment:
>>
>> 1) For AMD smm save state.
>> I saw Paolo gave the comment on how to detect AMD save state. I do not
>> have strong opinion on that. I think you and Paolo can make decision.
>>
>> I recommend we move AMD_SMRAM_SAVE_STATE_MAP_OFFSET to
>> UefiCpuPkg\Include\Register\Amd\SmramSaveStateMap.h, because it is
>> standard.
> Hi Yao,
>
> Sure thing, I will do that.
>
> Leo
>
>> +//
>> +// Definitions for AMD systems are based on contents of the // AMD64
>> +Architecture Programmer's Manual // Volume 2: System Programming,
>> +Section 10 System-Management Mode // #define
>> +AMD_SMRAM_SAVE_STATE_MAP_OFFSET 0xfe00
>>
>> We can leave AMD_SMM_PSD_OFFSET in UefiCpuPkg/PiSmmCpuDxeSmm,
>> if it is implementation specific.
>> +#define AMD_SMM_PSD_OFFSET 0xfc00
>>
>>
>>
>> 2) For Intel save state, I assume you already did some test to make sure
>> there is no regression.
>> If so, would you please add some description on what test you have done?
>> For example,
>> If both IA32 and X64 are validated?
>> If all three .S, .asm, .nasm are validated?
>> If OS boot and S3 resume are validated?
>>
>> If you did any other test, please also add.
>>
>
> Hi Yao,
>
> I have not done runtime validation testing.
> Instead, I tested the assembly code snippets in a vacuum (in their .asm, .nasm, and .S forms),
> to ensure the source produced the expected compiled code, and the expected execution.
>
> So any runtime 'Tested-by' would be greatly appreciated
> Thanks,
> Leo.
>
>> Thank you
>> Yao Jiewen
>>
>>
>>> -----Original Message-----
>>> From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf Of
>>> Leo Duran
>>> Sent: Thursday, October 12, 2017 3:45 AM
>>> To: edk2-devel@lists.01.org
>>> Subject: [edk2] [PATCH v5 0/2] Enhanced SMM support for AMD-based x86
>>> systems.
>>>
>>> This patch-set replaces Intel-specific macros with global variables to
>>> provide support for AMD-based x86 systems.
>>>
>>> The replaced macros are:
>>> 1) SRAM_SAVE_STATE_MAP_OFFSET
>>> 2) TXT_SMM_PSD_OFFSET
>>> 3) SMM_PSD_OFFSET
>>>
>>> Changes since v4:
>>> Make runtime CPUID checks and use global variables instead of PCD's.
>>>
>>> Changes since v3:
>>> Correction on cover letter.
>>>
>>> Changes since v2:
>>> The intent of this revision is to maintain compatibility with existing
>>> packages. To that end, changes to OvmgfPkg and QuarkSocPkg are
>> reverted.
>>> Moreover, pertinent macros are replaced in the C code, rather than on
>>> header files that are shared globally.
>>>
>>> Changes since v1:
>>> Revision to Cc list for UefiCpuPkg.
>>>
>>> Leo Duran (2):
>>> UefiCpuPkg/SmmCpuFeaturesLib: Use global variables to replace macros
>>> UefiCpuPkg/PiSmmCpuDxeSmm: Use global variables to replace macros
>>>
>>> .../Library/SmmCpuFeaturesLib/Ia32/SmiEntry.S | 28 ++++++---
>>> .../Library/SmmCpuFeaturesLib/Ia32/SmiEntry.asm | 29 ++++++---
>>> .../Library/SmmCpuFeaturesLib/Ia32/SmiEntry.nasm | 43 +++++++++----
>>> UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCommon.h | 48
>>> +++++++++++++++
>>> .../Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c | 59
>>> +++++++++++++++---
>>> .../SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf | 3 +
>>> .../SmmCpuFeaturesLib/SmmCpuFeaturesLibStm.inf | 3 +
>>> UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c | 39 ++++++++++-
>> -
>>> .../Library/SmmCpuFeaturesLib/X64/SmiEntry.S | 28 ++++++---
>>> .../Library/SmmCpuFeaturesLib/X64/SmiEntry.asm | 30 ++++++---
>>> .../Library/SmmCpuFeaturesLib/X64/SmiEntry.nasm | 47 ++++++++++----
>>> UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/Semaphore.c | 22 ++++---
>>> UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.S | 28 ++++++---
>>> UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.asm | 21 +++++--
>>> UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm | 43
>>> +++++++++----
>>> UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c | 72
>>> ++++++++++++++++++++--
>>> UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h | 17 ++++-
>>> UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c | 18
>> +++---
>>> UefiCpuPkg/PiSmmCpuDxeSmm/SmramSaveState.c | 20 +++---
>>> UefiCpuPkg/PiSmmCpuDxeSmm/X64/Semaphore.c | 22 ++++---
>>> UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.S | 34 ++++++----
>>> UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.asm | 22 +++++--
>>> UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm | 45
>>> ++++++++++----
>>> 23 files changed, 547 insertions(+), 174 deletions(-) create mode
>>> 100644 UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCommon.h
>>>
>>> --
>>> 2.7.4
>>>
>>> _______________________________________________
>>> edk2-devel mailing list
>>> edk2-devel@lists.01.org
>>> https://lists.01.org/mailman/listinfo/edk2-devel
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH v5 1/2] UefiCpuPkg/SmmCpuFeaturesLib: Use global variables to replace macros
2017-10-14 15:51 ` Duran, Leo
@ 2017-10-15 15:26 ` Paolo Bonzini
0 siblings, 0 replies; 30+ messages in thread
From: Paolo Bonzini @ 2017-10-15 15:26 UTC (permalink / raw)
To: Duran, Leo, edk2-devel@lists.01.org
Cc: Ruiyu Ni, Jordan Justen, Liming Gao, Jiewen Yao, Michael D Kinney
On 14/10/2017 17:51, Duran, Leo wrote:
>>> + // Override PSD offset for AMD
>>> + //
>>> + if (SmmStandardSignatureIsAuthenticAMD ()) {
>>> + gStmPsdOffset = AMD_SMM_PSD_OFFSET; }
>>> +
>> I think the right thing to do here would be to use the SMM state save map
>> revision; in the case of AMD, the low 16 bits (IIRC) would be 0x0064.
>>
> Hi Paolo,
>
> In its current form, the patch merely replaces the macros with global
> variables, and does not attempt to disrupt the existing execution
> flow. But perhaps you can provide a bit more context (or an example)
> so that may better understand your suggestion?
The offsets don't really depend on Intel vs. AMD, but rather on the
version of the state save map. QEMU and KVM for example always use the
AMD format because it's documented better (Intel doesn't document the
descriptor cache fields in the SDM), even if the CPUID vendor is
GenuineIntel.
I am not sure if you have the SMM state save map revision at this point
of the code, and likewise for 2/2. But if you do, it would be much
nicer for us virtualization folks if you used it instead of CPUID to
pick the offsets.
Paolo
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH v5 0/2] Enhanced SMM support for AMD-based x86 systems.
2017-10-15 0:58 ` Yao, Jiewen
@ 2017-10-16 17:06 ` Laszlo Ersek
2017-10-16 17:08 ` Paolo Bonzini
2017-10-16 17:31 ` Duran, Leo
0 siblings, 2 replies; 30+ messages in thread
From: Laszlo Ersek @ 2017-10-16 17:06 UTC (permalink / raw)
To: Yao, Jiewen, Duran, Leo; +Cc: edk2-devel@lists.01.org, Paolo Bonzini
On 10/15/17 02:58, Yao, Jiewen wrote:
> for runtime test, I recommend using ovmf. You don't need real hardware. It can run both 32bit or 64bit. It can run in both Linux and windows.
>
> You need use -D SMM_REQUIRE option to build ovmf.
> If you have any problem, Laszlo is the good contact.
I don't have much context about this series, but looking at the blurb, I
see that version 3 removed OvmfPkg patches:
> Changes since v2:
> The intent of this revision is to maintain compatibility with existing
> packages. To that end, changes to OvmgfPkg and QuarkSocPkg are
> reverted. Moreover, pertinent macros are replaced in the C code,
> rather than on header files that are shared globally.
Judged on the diffstat of patch #1 -- only
"UefiCpuPkg/Library/SmmCpuFeaturesLib" files are modified -- I would say
that changes in patch #1 are invisible to OVMF. The reason is that OVMF
uses a separate SmmCpuFeaturesLib instance, namely
OvmfPkg/Library/SmmCpuFeaturesLib
This means two things:
- changes from patch #1 cannot be tested with OVMF, simply because
"UefiCpuPkg/Library/SmmCpuFeaturesLib" is never built for OVMF;
- changes from patch #2 may or may not break SMM in OVMF, dependent on
whether patch #2 is tied closely to patch #1.
In order to see why OvmfPkg has a separate SmmCpuFeaturesLib instance,
please review the commit log:
git log --reverse -- OvmfPkg/Library/SmmCpuFeaturesLib
At this point I cannot determine if this patch set should ignore OvmfPkg
completely, or else patch #1 should be duplicated for
"OvmfPkg/Library/SmmCpuFeaturesLib" as well. (I guess I don't understand
the goal of the patch set -- I've read the blurb, but the problem has
not been stated well enough for me to understand. Or maybe it was stated
long ago, and I've forgotten it :) )
Leo, I have a separate request: the diffstats in the blurb and on patch
#1 are practically unreadable. This is because edk2 uses long names for
files and directories, and because the nesting can get deep -- and "git"
by default truncates the diffstat to quite narrow lines.
In order to avoid this, I recommend formatting edk2 patch sets as follows:
git format-patch --stat=1000 --stat-graph-width=20 ...
This makes the pathname column just as wide as necessary, while keeping
the actual "stats" column reasonably narrow.
Thanks,
Laszlo
>> 在 2017年10月15日，上午12:04，Duran, Leo <leo.duran@amd.com> 写道：
>>
>>
>>
>>> -----Original Message-----
>>> From: Yao, Jiewen [mailto:jiewen.yao@intel.com]
>>> Sent: Thursday, October 12, 2017 8:53 PM
>>> To: Duran, Leo <leo.duran@amd.com>; edk2-devel@lists.01.org
>>> Subject: RE: [edk2] [PATCH v5 0/2] Enhanced SMM support for AMD-based
>>> x86 systems.
>>>
>>> HI Leo
>>> Thank you very much. This patch looks good to me in general.
>>>
>>> Some minor comment:
>>>
>>> 1) For AMD smm save state.
>>> I saw Paolo gave the comment on how to detect AMD save state. I do not
>>> have strong opinion on that. I think you and Paolo can make decision.
>>>
>>> I recommend we move AMD_SMRAM_SAVE_STATE_MAP_OFFSET to
>>> UefiCpuPkg\Include\Register\Amd\SmramSaveStateMap.h, because it is
>>> standard.
>> Hi Yao,
>>
>> Sure thing, I will do that.
>>
>> Leo
>>
>>> +//
>>> +// Definitions for AMD systems are based on contents of the // AMD64
>>> +Architecture Programmer's Manual // Volume 2: System Programming,
>>> +Section 10 System-Management Mode // #define
>>> +AMD_SMRAM_SAVE_STATE_MAP_OFFSET 0xfe00
>>>
>>> We can leave AMD_SMM_PSD_OFFSET in UefiCpuPkg/PiSmmCpuDxeSmm,
>>> if it is implementation specific.
>>> +#define AMD_SMM_PSD_OFFSET 0xfc00
>>>
>>>
>>>
>>> 2) For Intel save state, I assume you already did some test to make sure
>>> there is no regression.
>>> If so, would you please add some description on what test you have done?
>>> For example,
>>> If both IA32 and X64 are validated?
>>> If all three .S, .asm, .nasm are validated?
>>> If OS boot and S3 resume are validated?
>>>
>>> If you did any other test, please also add.
>>>
>>
>> Hi Yao,
>>
>> I have not done runtime validation testing.
>> Instead, I tested the assembly code snippets in a vacuum (in their .asm, .nasm, and .S forms),
>> to ensure the source produced the expected compiled code, and the expected execution.
>>
>> So any runtime 'Tested-by' would be greatly appreciated
>> Thanks,
>> Leo.
>>
>>> Thank you
>>> Yao Jiewen
>>>
>>>
>>>> -----Original Message-----
>>>> From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf Of
>>>> Leo Duran
>>>> Sent: Thursday, October 12, 2017 3:45 AM
>>>> To: edk2-devel@lists.01.org
>>>> Subject: [edk2] [PATCH v5 0/2] Enhanced SMM support for AMD-based x86
>>>> systems.
>>>>
>>>> This patch-set replaces Intel-specific macros with global variables to
>>>> provide support for AMD-based x86 systems.
>>>>
>>>> The replaced macros are:
>>>> 1) SRAM_SAVE_STATE_MAP_OFFSET
>>>> 2) TXT_SMM_PSD_OFFSET
>>>> 3) SMM_PSD_OFFSET
>>>>
>>>> Changes since v4:
>>>> Make runtime CPUID checks and use global variables instead of PCD's.
>>>>
>>>> Changes since v3:
>>>> Correction on cover letter.
>>>>
>>>> Changes since v2:
>>>> The intent of this revision is to maintain compatibility with existing
>>>> packages. To that end, changes to OvmgfPkg and QuarkSocPkg are
>>> reverted.
>>>> Moreover, pertinent macros are replaced in the C code, rather than on
>>>> header files that are shared globally.
>>>>
>>>> Changes since v1:
>>>> Revision to Cc list for UefiCpuPkg.
>>>>
>>>> Leo Duran (2):
>>>> UefiCpuPkg/SmmCpuFeaturesLib: Use global variables to replace macros
>>>> UefiCpuPkg/PiSmmCpuDxeSmm: Use global variables to replace macros
>>>>
>>>> .../Library/SmmCpuFeaturesLib/Ia32/SmiEntry.S | 28 ++++++---
>>>> .../Library/SmmCpuFeaturesLib/Ia32/SmiEntry.asm | 29 ++++++---
>>>> .../Library/SmmCpuFeaturesLib/Ia32/SmiEntry.nasm | 43 +++++++++----
>>>> UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCommon.h | 48
>>>> +++++++++++++++
>>>> .../Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c | 59
>>>> +++++++++++++++---
>>>> .../SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf | 3 +
>>>> .../SmmCpuFeaturesLib/SmmCpuFeaturesLibStm.inf | 3 +
>>>> UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c | 39 ++++++++++-
>>> -
>>>> .../Library/SmmCpuFeaturesLib/X64/SmiEntry.S | 28 ++++++---
>>>> .../Library/SmmCpuFeaturesLib/X64/SmiEntry.asm | 30 ++++++---
>>>> .../Library/SmmCpuFeaturesLib/X64/SmiEntry.nasm | 47 ++++++++++----
>>>> UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/Semaphore.c | 22 ++++---
>>>> UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.S | 28 ++++++---
>>>> UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.asm | 21 +++++--
>>>> UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm | 43
>>>> +++++++++----
>>>> UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c | 72
>>>> ++++++++++++++++++++--
>>>> UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h | 17 ++++-
>>>> UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c | 18
>>> +++---
>>>> UefiCpuPkg/PiSmmCpuDxeSmm/SmramSaveState.c | 20 +++---
>>>> UefiCpuPkg/PiSmmCpuDxeSmm/X64/Semaphore.c | 22 ++++---
>>>> UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.S | 34 ++++++----
>>>> UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.asm | 22 +++++--
>>>> UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm | 45
>>>> ++++++++++----
>>>> 23 files changed, 547 insertions(+), 174 deletions(-) create mode
>>>> 100644 UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCommon.h
>>>>
>>>> --
>>>> 2.7.4
>>>>
>>>> _______________________________________________
>>>> edk2-devel mailing list
>>>> edk2-devel@lists.01.org
>>>> https://lists.01.org/mailman/listinfo/edk2-devel
> _______________________________________________
> edk2-devel mailing list
> edk2-devel@lists.01.org
> https://lists.01.org/mailman/listinfo/edk2-devel
>
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH v5 0/2] Enhanced SMM support for AMD-based x86 systems.
2017-10-16 17:06 ` Laszlo Ersek
@ 2017-10-16 17:08 ` Paolo Bonzini
2017-10-16 17:31 ` Duran, Leo
1 sibling, 0 replies; 30+ messages in thread
From: Paolo Bonzini @ 2017-10-16 17:08 UTC (permalink / raw)
To: Laszlo Ersek, Yao, Jiewen, Duran, Leo; +Cc: edk2-devel@lists.01.org
On 16/10/2017 19:06, Laszlo Ersek wrote:
> git log --reverse -- OvmfPkg/Library/SmmCpuFeaturesLib
>
> At this point I cannot determine if this patch set should ignore OvmfPkg
> completely, or else patch #1 should be duplicated for
> "OvmfPkg/Library/SmmCpuFeaturesLib" as well. (I guess I don't understand
> the goal of the patch set -- I've read the blurb, but the problem has
> not been stated well enough for me to understand. Or maybe it was stated
> long ago, and I've forgotten it :) )
I _think_ they should be duplicated, but I also don't understand the
goal and that is just from reasoning on why OVMF has a separate
SmmCpuFeaturesLib implementation.
Paolo
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH v5 0/2] Enhanced SMM support for AMD-based x86 systems.
2017-10-13 1:52 ` [PATCH v5 0/2] Enhanced SMM support for AMD-based x86 systems Yao, Jiewen
` (2 preceding siblings ...)
2017-10-14 16:08 ` Duran, Leo
@ 2017-10-16 17:13 ` Paolo Bonzini
3 siblings, 0 replies; 30+ messages in thread
From: Paolo Bonzini @ 2017-10-16 17:13 UTC (permalink / raw)
To: Yao, Jiewen, Leo Duran, edk2-devel@lists.01.org
On 13/10/2017 03:52, Yao, Jiewen wrote:
> I recommend we move AMD_SMRAM_SAVE_STATE_MAP_OFFSET to UefiCpuPkg\Include\Register\Amd\SmramSaveStateMap.h, because it is standard.
> +//
> +// Definitions for AMD systems are based on contents of the
> +// AMD64 Architecture Programmer's Manual
> +// Volume 2: System Programming, Section 10 System-Management Mode
> +//
> +#define AMD_SMRAM_SAVE_STATE_MAP_OFFSET 0xfe00
If I understand correctly, I think AMD can keep on using 0xfc00 and just
adjust the offsets up by 0x200 bytes. For example, QEMU_SMRAM_SAVE_STATE_MAP
in OvmfPkg/Include/Register/QemuSmramStateSaveMap.h is essentially the AMD
format and it starts with:
UINT8 Reserved0[0x200]; // 7c00h
UINT8 Reserved1[0xf8]; // 7e00h
See also the comment in SMRAM_SAVE_STATE_MAP32:
UINT8 Reserved[0x200]; // 7c00h
// Padded an extra 0x200 bytes so 32-bit and 64-bit
// SMRAM Save State Maps are the same size
UINT8 Reserved1[0xf8]; // 7e00h
Thanks,
Paolo
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH v5 0/2] Enhanced SMM support for AMD-based x86 systems.
2017-10-16 17:06 ` Laszlo Ersek
2017-10-16 17:08 ` Paolo Bonzini
@ 2017-10-16 17:31 ` Duran, Leo
2017-10-16 18:44 ` Laszlo Ersek
1 sibling, 1 reply; 30+ messages in thread
From: Duran, Leo @ 2017-10-16 17:31 UTC (permalink / raw)
To: 'Laszlo Ersek', Yao, Jiewen
Cc: edk2-devel@lists.01.org, Paolo Bonzini
> -----Original Message-----
> From: Laszlo Ersek [mailto:lersek@redhat.com]
> Sent: Monday, October 16, 2017 12:06 PM
> To: Yao, Jiewen <jiewen.yao@intel.com>; Duran, Leo
> <leo.duran@amd.com>
> Cc: edk2-devel@lists.01.org; Paolo Bonzini <pbonzini@redhat.com>
> Subject: Re: [edk2] [PATCH v5 0/2] Enhanced SMM support for AMD-based
> x86 systems.
>
> On 10/15/17 02:58, Yao, Jiewen wrote:
> > for runtime test, I recommend using ovmf. You don't need real hardware.
> It can run both 32bit or 64bit. It can run in both Linux and windows.
> >
> > You need use -D SMM_REQUIRE option to build ovmf.
> > If you have any problem, Laszlo is the good contact.
>
> I don't have much context about this series, but looking at the blurb, I see
> that version 3 removed OvmfPkg patches:
>
> > Changes since v2:
> > The intent of this revision is to maintain compatibility with existing
> > packages. To that end, changes to OvmgfPkg and QuarkSocPkg are
> > reverted. Moreover, pertinent macros are replaced in the C code,
> > rather than on header files that are shared globally.
>
> Judged on the diffstat of patch #1 -- only
> "UefiCpuPkg/Library/SmmCpuFeaturesLib" files are modified -- I would say
> that changes in patch #1 are invisible to OVMF. The reason is that OVMF uses
> a separate SmmCpuFeaturesLib instance, namely
>
> OvmfPkg/Library/SmmCpuFeaturesLib
>
> This means two things:
>
> - changes from patch #1 cannot be tested with OVMF, simply because
> "UefiCpuPkg/Library/SmmCpuFeaturesLib" is never built for OVMF;
>
> - changes from patch #2 may or may not break SMM in OVMF, dependent on
> whether patch #2 is tied closely to patch #1.
>
> In order to see why OvmfPkg has a separate SmmCpuFeaturesLib instance,
> please review the commit log:
>
> git log --reverse -- OvmfPkg/Library/SmmCpuFeaturesLib
>
> At this point I cannot determine if this patch set should ignore OvmfPkg
> completely, or else patch #1 should be duplicated for
> "OvmfPkg/Library/SmmCpuFeaturesLib" as well. (I guess I don't understand
> the goal of the patch set -- I've read the blurb, but the problem has not been
> stated well enough for me to understand. Or maybe it was stated long ago,
> and I've forgotten it :) )
>
Lazlo,
I purposely left out changes to OVMF and Quark, consistent with previous feedback.
Leo
>
> Leo, I have a separate request: the diffstats in the blurb and on patch
> #1 are practically unreadable. This is because edk2 uses long names for files
> and directories, and because the nesting can get deep -- and "git"
> by default truncates the diffstat to quite narrow lines.
>
> In order to avoid this, I recommend formatting edk2 patch sets as follows:
>
> git format-patch --stat=1000 --stat-graph-width=20 ...
>
Lazlo,
Sounds good. Will do.
Leo.
> This makes the pathname column just as wide as necessary, while keeping
> the actual "stats" column reasonably narrow.
>
> Thanks,
> Laszlo
>
> >> 在 2017年10月15日，上午12:04，Duran, Leo <leo.duran@amd.com>
> 写道：
> >>
> >>
> >>
> >>> -----Original Message-----
> >>> From: Yao, Jiewen [mailto:jiewen.yao@intel.com]
> >>> Sent: Thursday, October 12, 2017 8:53 PM
> >>> To: Duran, Leo <leo.duran@amd.com>; edk2-devel@lists.01.org
> >>> Subject: RE: [edk2] [PATCH v5 0/2] Enhanced SMM support for
> >>> AMD-based
> >>> x86 systems.
> >>>
> >>> HI Leo
> >>> Thank you very much. This patch looks good to me in general.
> >>>
> >>> Some minor comment:
> >>>
> >>> 1) For AMD smm save state.
> >>> I saw Paolo gave the comment on how to detect AMD save state. I do
> >>> not have strong opinion on that. I think you and Paolo can make
> decision.
> >>>
> >>> I recommend we move AMD_SMRAM_SAVE_STATE_MAP_OFFSET to
> >>> UefiCpuPkg\Include\Register\Amd\SmramSaveStateMap.h, because it
> is
> >>> standard.
> >> Hi Yao,
> >>
> >> Sure thing, I will do that.
> >>
> >> Leo
> >>
> >>> +//
> >>> +// Definitions for AMD systems are based on contents of the //
> >>> +AMD64 Architecture Programmer's Manual // Volume 2: System
> >>> +Programming, Section 10 System-Management Mode // #define
> >>> +AMD_SMRAM_SAVE_STATE_MAP_OFFSET 0xfe00
> >>>
> >>> We can leave AMD_SMM_PSD_OFFSET in
> UefiCpuPkg/PiSmmCpuDxeSmm, if it
> >>> is implementation specific.
> >>> +#define AMD_SMM_PSD_OFFSET 0xfc00
> >>>
> >>>
> >>>
> >>> 2) For Intel save state, I assume you already did some test to make
> >>> sure there is no regression.
> >>> If so, would you please add some description on what test you have
> done?
> >>> For example,
> >>> If both IA32 and X64 are validated?
> >>> If all three .S, .asm, .nasm are validated?
> >>> If OS boot and S3 resume are validated?
> >>>
> >>> If you did any other test, please also add.
> >>>
> >>
> >> Hi Yao,
> >>
> >> I have not done runtime validation testing.
> >> Instead, I tested the assembly code snippets in a vacuum (in their
> >> .asm, .nasm, and .S forms), to ensure the source produced the expected
> compiled code, and the expected execution.
> >>
> >> So any runtime 'Tested-by' would be greatly appreciated Thanks, Leo.
> >>
> >>> Thank you
> >>> Yao Jiewen
> >>>
> >>>
> >>>> -----Original Message-----
> >>>> From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf
> >>>> Of Leo Duran
> >>>> Sent: Thursday, October 12, 2017 3:45 AM
> >>>> To: edk2-devel@lists.01.org
> >>>> Subject: [edk2] [PATCH v5 0/2] Enhanced SMM support for AMD-based
> >>>> x86 systems.
> >>>>
> >>>> This patch-set replaces Intel-specific macros with global variables
> >>>> to provide support for AMD-based x86 systems.
> >>>>
> >>>> The replaced macros are:
> >>>> 1) SRAM_SAVE_STATE_MAP_OFFSET
> >>>> 2) TXT_SMM_PSD_OFFSET
> >>>> 3) SMM_PSD_OFFSET
> >>>>
> >>>> Changes since v4:
> >>>> Make runtime CPUID checks and use global variables instead of PCD's.
> >>>>
> >>>> Changes since v3:
> >>>> Correction on cover letter.
> >>>>
> >>>> Changes since v2:
> >>>> The intent of this revision is to maintain compatibility with
> >>>> existing packages. To that end, changes to OvmgfPkg and QuarkSocPkg
> >>>> are
> >>> reverted.
> >>>> Moreover, pertinent macros are replaced in the C code, rather than
> >>>> on header files that are shared globally.
> >>>>
> >>>> Changes since v1:
> >>>> Revision to Cc list for UefiCpuPkg.
> >>>>
> >>>> Leo Duran (2):
> >>>> UefiCpuPkg/SmmCpuFeaturesLib: Use global variables to replace
> >>>> macros
> >>>> UefiCpuPkg/PiSmmCpuDxeSmm: Use global variables to replace
> macros
> >>>>
> >>>> .../Library/SmmCpuFeaturesLib/Ia32/SmiEntry.S | 28 ++++++---
> >>>> .../Library/SmmCpuFeaturesLib/Ia32/SmiEntry.asm | 29 ++++++---
> >>>> .../Library/SmmCpuFeaturesLib/Ia32/SmiEntry.nasm | 43 +++++++++-
> ---
> >>>> UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCommon.h | 48
> >>>> +++++++++++++++
> >>>> .../Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c | 59
> >>>> +++++++++++++++---
> >>>> .../SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf | 3 +
> >>>> .../SmmCpuFeaturesLib/SmmCpuFeaturesLibStm.inf | 3 +
> >>>> UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c | 39
> ++++++++++-
> >>> -
> >>>> .../Library/SmmCpuFeaturesLib/X64/SmiEntry.S | 28 ++++++---
> >>>> .../Library/SmmCpuFeaturesLib/X64/SmiEntry.asm | 30 ++++++---
> >>>> .../Library/SmmCpuFeaturesLib/X64/SmiEntry.nasm | 47
> ++++++++++----
> >>>> UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/Semaphore.c | 22 ++++---
> >>>> UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.S | 28 ++++++---
> >>>> UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.asm | 21 +++++--
> >>>> UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm | 43
> >>>> +++++++++----
> >>>> UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c | 72
> >>>> ++++++++++++++++++++--
> >>>> UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h | 17 ++++-
> >>>> UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c | 18
> >>> +++---
> >>>> UefiCpuPkg/PiSmmCpuDxeSmm/SmramSaveState.c | 20 +++---
> >>>> UefiCpuPkg/PiSmmCpuDxeSmm/X64/Semaphore.c | 22 ++++---
> >>>> UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.S | 34 ++++++----
> >>>> UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.asm | 22 +++++--
> >>>> UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm | 45
> >>>> ++++++++++----
> >>>> 23 files changed, 547 insertions(+), 174 deletions(-) create mode
> >>>> 100644 UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCommon.h
> >>>>
> >>>> --
> >>>> 2.7.4
> >>>>
> >>>> _______________________________________________
> >>>> edk2-devel mailing list
> >>>> edk2-devel@lists.01.org
> >>>> https://lists.01.org/mailman/listinfo/edk2-devel
> > _______________________________________________
> > edk2-devel mailing list
> > edk2-devel@lists.01.org
> > https://lists.01.org/mailman/listinfo/edk2-devel
> >
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH v5 0/2] Enhanced SMM support for AMD-based x86 systems.
2017-10-16 17:31 ` Duran, Leo
@ 2017-10-16 18:44 ` Laszlo Ersek
2017-10-16 18:56 ` Duran, Leo
0 siblings, 1 reply; 30+ messages in thread
From: Laszlo Ersek @ 2017-10-16 18:44 UTC (permalink / raw)
To: Duran, Leo, Yao, Jiewen; +Cc: edk2-devel@lists.01.org, Paolo Bonzini
On 10/16/17 19:31, Duran, Leo wrote:
>
>
>> -----Original Message-----
>> From: Laszlo Ersek [mailto:lersek@redhat.com]
>> Sent: Monday, October 16, 2017 12:06 PM
>> To: Yao, Jiewen <jiewen.yao@intel.com>; Duran, Leo
>> <leo.duran@amd.com>
>> Cc: edk2-devel@lists.01.org; Paolo Bonzini <pbonzini@redhat.com>
>> Subject: Re: [edk2] [PATCH v5 0/2] Enhanced SMM support for AMD-based
>> x86 systems.
>>
>> On 10/15/17 02:58, Yao, Jiewen wrote:
>>> for runtime test, I recommend using ovmf. You don't need real hardware.
>> It can run both 32bit or 64bit. It can run in both Linux and windows.
>>>
>>> You need use -D SMM_REQUIRE option to build ovmf.
>>> If you have any problem, Laszlo is the good contact.
>>
>> I don't have much context about this series, but looking at the blurb, I see
>> that version 3 removed OvmfPkg patches:
>>
>>> Changes since v2:
>>> The intent of this revision is to maintain compatibility with existing
>>> packages. To that end, changes to OvmgfPkg and QuarkSocPkg are
>>> reverted. Moreover, pertinent macros are replaced in the C code,
>>> rather than on header files that are shared globally.
>>
>> Judged on the diffstat of patch #1 -- only
>> "UefiCpuPkg/Library/SmmCpuFeaturesLib" files are modified -- I would say
>> that changes in patch #1 are invisible to OVMF. The reason is that OVMF uses
>> a separate SmmCpuFeaturesLib instance, namely
>>
>> OvmfPkg/Library/SmmCpuFeaturesLib
>>
>> This means two things:
>>
>> - changes from patch #1 cannot be tested with OVMF, simply because
>> "UefiCpuPkg/Library/SmmCpuFeaturesLib" is never built for OVMF;
>>
>> - changes from patch #2 may or may not break SMM in OVMF, dependent on
>> whether patch #2 is tied closely to patch #1.
>>
>> In order to see why OvmfPkg has a separate SmmCpuFeaturesLib instance,
>> please review the commit log:
>>
>> git log --reverse -- OvmfPkg/Library/SmmCpuFeaturesLib
>>
>> At this point I cannot determine if this patch set should ignore OvmfPkg
>> completely, or else patch #1 should be duplicated for
>> "OvmfPkg/Library/SmmCpuFeaturesLib" as well. (I guess I don't understand
>> the goal of the patch set -- I've read the blurb, but the problem has not been
>> stated well enough for me to understand. Or maybe it was stated long ago,
>> and I've forgotten it :) )
>>
>
> Lazlo,
> I purposely left out changes to OVMF and Quark, consistent with previous feedback.
I've found my previous comments:
http://mid.mail-archive.com/2d3efa5a-ad72-bb35-1e6a-b9b78379337c@redhat.com
There I only suggested a different (more telling) subject for the
OvmfPkg patch, and wrote,
> (Of course I realize the patch might entirely be replaced in the next
> version, based on Jiewen's and Mike's feedback -- that's OK with me, I
> just wanted to give an example.)
I didn't try to validate Jiewen's / Mike's feedback; I just stated *if*,
according to them, patching OvmfPkg was not necessary, I'd be OK with that.
Since we're talking anyway, can you (and/or Jiewen & Mike) please state
the problem being solved here, and explain why patching the
SmmCpuFeaturesLib instance in OvmfPkg is, or is not, necessary to update?
Hmmm... Is it the case that
UefiCpuPkg/Library/SmmCpuFeaturesLib
runs correctly on Intel *hosts* only at the moment (so it needs fixing,
for AMD *hosts*), while
OvmfPkg/Library/SmmCpuFeaturesLib
deals with AMD-looking *guests* anyway, so it needs no fixing, for AMD
compatibility?
If this is correct, then I agree patch #1 does not need to be duplicated
for OvmfPkg.
*However*, in turn, patch #2 (for PiSmmCpuDxeSmm) might be necessary to
update for QEMU. PiSmmCpuDxeSmm runs on both bare metal and on QEMU.
And, as Paolo says, a pure CPUID / manufacturer check (for determining
the state save layout) is wrong on QEMU, even if the same would work on
bare metal:
@@ -547,6 +595,20 @@ PiCpuSmmEntry (
);
//
+ // Override SMRAM offsets for AMD
+ //
+ if (StandardSignatureIsAuthenticAMD ()) {
+ gSmmSmramStateMapOffset = AMD_SMRAM_SAVE_STATE_MAP_OFFSET;
+ gSmmPsdOffset = AMD_SMM_PSD_OFFSET;
+ }
+
If patch v5 2/2 is merely a refactoring (i.e., it causes PiSmmCpuDxeSmm
to behave exactly the same as before, just with an improved
implementation), then I agree a CPUID-based check is not necessarily a
bug (regression). Instead, it might be called a missed opportunity (or,
more nicely put, a "basis") for bringing PiSmmCpuDxeSmm closer to QEMU.
My apologies if I'm confused.
Thanks
Laszlo
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH v5 0/2] Enhanced SMM support for AMD-based x86 systems.
2017-10-16 18:44 ` Laszlo Ersek
@ 2017-10-16 18:56 ` Duran, Leo
0 siblings, 0 replies; 30+ messages in thread
From: Duran, Leo @ 2017-10-16 18:56 UTC (permalink / raw)
To: 'Laszlo Ersek', Yao, Jiewen
Cc: edk2-devel@lists.01.org, Paolo Bonzini
> -----Original Message-----
> From: Laszlo Ersek [mailto:lersek@redhat.com]
> Sent: Monday, October 16, 2017 1:44 PM
> To: Duran, Leo <leo.duran@amd.com>; Yao, Jiewen
> <jiewen.yao@intel.com>
> Cc: edk2-devel@lists.01.org; Paolo Bonzini <pbonzini@redhat.com>
> Subject: Re: [edk2] [PATCH v5 0/2] Enhanced SMM support for AMD-based
> x86 systems.
>
> On 10/16/17 19:31, Duran, Leo wrote:
> >
> >
> >> -----Original Message-----
> >> From: Laszlo Ersek [mailto:lersek@redhat.com]
> >> Sent: Monday, October 16, 2017 12:06 PM
> >> To: Yao, Jiewen <jiewen.yao@intel.com>; Duran, Leo
> >> <leo.duran@amd.com>
> >> Cc: edk2-devel@lists.01.org; Paolo Bonzini <pbonzini@redhat.com>
> >> Subject: Re: [edk2] [PATCH v5 0/2] Enhanced SMM support for AMD-
> based
> >> x86 systems.
> >>
> >> On 10/15/17 02:58, Yao, Jiewen wrote:
> >>> for runtime test, I recommend using ovmf. You don't need real
> hardware.
> >> It can run both 32bit or 64bit. It can run in both Linux and windows.
> >>>
> >>> You need use -D SMM_REQUIRE option to build ovmf.
> >>> If you have any problem, Laszlo is the good contact.
> >>
> >> I don't have much context about this series, but looking at the
> >> blurb, I see that version 3 removed OvmfPkg patches:
> >>
> >>> Changes since v2:
> >>> The intent of this revision is to maintain compatibility with
> >>> existing packages. To that end, changes to OvmgfPkg and QuarkSocPkg
> >>> are reverted. Moreover, pertinent macros are replaced in the C code,
> >>> rather than on header files that are shared globally.
> >>
> >> Judged on the diffstat of patch #1 -- only
> >> "UefiCpuPkg/Library/SmmCpuFeaturesLib" files are modified -- I would
> >> say that changes in patch #1 are invisible to OVMF. The reason is
> >> that OVMF uses a separate SmmCpuFeaturesLib instance, namely
> >>
> >> OvmfPkg/Library/SmmCpuFeaturesLib
> >>
> >> This means two things:
> >>
> >> - changes from patch #1 cannot be tested with OVMF, simply because
> >> "UefiCpuPkg/Library/SmmCpuFeaturesLib" is never built for OVMF;
> >>
> >> - changes from patch #2 may or may not break SMM in OVMF, dependent
> on
> >> whether patch #2 is tied closely to patch #1.
> >>
> >> In order to see why OvmfPkg has a separate SmmCpuFeaturesLib
> >> instance, please review the commit log:
> >>
> >> git log --reverse -- OvmfPkg/Library/SmmCpuFeaturesLib
> >>
> >> At this point I cannot determine if this patch set should ignore
> >> OvmfPkg completely, or else patch #1 should be duplicated for
> >> "OvmfPkg/Library/SmmCpuFeaturesLib" as well. (I guess I don't
> >> understand the goal of the patch set -- I've read the blurb, but the
> >> problem has not been stated well enough for me to understand. Or
> >> maybe it was stated long ago, and I've forgotten it :) )
> >>
> >
> > Lazlo,
> > I purposely left out changes to OVMF and Quark, consistent with previous
> feedback.
>
> I've found my previous comments:
>
> http://mid.mail-archive.com/2d3efa5a-ad72-bb35-1e6a-
> b9b78379337c@redhat.com
>
> There I only suggested a different (more telling) subject for the OvmfPkg
> patch, and wrote,
>
> > (Of course I realize the patch might entirely be replaced in the next
> > version, based on Jiewen's and Mike's feedback -- that's OK with me, I
> > just wanted to give an example.)
>
> I didn't try to validate Jiewen's / Mike's feedback; I just stated *if*, according
> to them, patching OvmfPkg was not necessary, I'd be OK with that.
>
> Since we're talking anyway, can you (and/or Jiewen & Mike) please state the
> problem being solved here, and explain why patching the
> SmmCpuFeaturesLib instance in OvmfPkg is, or is not, necessary to update?
>
> Hmmm... Is it the case that
>
> UefiCpuPkg/Library/SmmCpuFeaturesLib
>
> runs correctly on Intel *hosts* only at the moment (so it needs fixing, for
> AMD *hosts*), while
>
> OvmfPkg/Library/SmmCpuFeaturesLib
>
> deals with AMD-looking *guests* anyway, so it needs no fixing, for AMD
> compatibility?
>
> If this is correct, then I agree patch #1 does not need to be duplicated for
> OvmfPkg.
Lazlo,
Yes, that is my understanding.
>
> *However*, in turn, patch #2 (for PiSmmCpuDxeSmm) might be necessary to
> update for QEMU. PiSmmCpuDxeSmm runs on both bare metal and on
> QEMU.
> And, as Paolo says, a pure CPUID / manufacturer check (for determining the
> state save layout) is wrong on QEMU, even if the same would work on bare
> metal:
>
> @@ -547,6 +595,20 @@ PiCpuSmmEntry (
> );
>
> //
> + // Override SMRAM offsets for AMD
> + //
> + if (StandardSignatureIsAuthenticAMD ()) {
> + gSmmSmramStateMapOffset =
> AMD_SMRAM_SAVE_STATE_MAP_OFFSET;
> + gSmmPsdOffset = AMD_SMM_PSD_OFFSET; }
> +
>
> If patch v5 2/2 is merely a refactoring (i.e., it causes PiSmmCpuDxeSmm to
> behave exactly the same as before, just with an improved implementation),
> then I agree a CPUID-based check is not necessarily a bug (regression).
> Instead, it might be called a missed opportunity (or, more nicely put, a
> "basis") for bringing PiSmmCpuDxeSmm closer to QEMU.
Lazlo,
1) Per feedback from Yao:
I'm currently investigating if we *really*really* have to change the PSD offset.
2) Per feedback from Paolo:
And if the PSD offset change is indeed required, I will investigate an alternate detection mechanism.
Thanks.
Leo
>
> My apologies if I'm confused.
>
> Thanks
> Laszlo
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH v5 1/2] UefiCpuPkg/SmmCpuFeaturesLib: Use global variables to replace macros
2017-10-11 19:45 ` [PATCH v5 1/2] UefiCpuPkg/SmmCpuFeaturesLib: Use global variables to replace macros Leo Duran
2017-10-12 21:40 ` Paolo Bonzini
@ 2017-10-17 14:19 ` Duran, Leo
2017-10-17 14:23 ` Laszlo Ersek
2017-10-17 14:50 ` Yao, Jiewen
1 sibling, 2 replies; 30+ messages in thread
From: Duran, Leo @ 2017-10-17 14:19 UTC (permalink / raw)
To: edk2-devel@lists.01.org, Jiewen Yao, 'Laszlo Ersek',
Paolo Bonzini
Cc: Ruiyu Ni, Michael D Kinney, Jordan Justen, Liming Gao
Yao, Lazlo, et al,
For the SRAM_SAVE_STATE_MAP_OFFSET:
I propose returning the value by a function in SmmCpuFeaturesLib... Here's the rationale:
- The value is fixed per CPU architecture, so this qualifies as a CPU feature.
- The logic for CPU architecture detection would be in one place (e.g., PiSmmCpuDxeSmm would call the library function)
- The OVMF and Quark instances of the library could just return the current (default) value, so no compatibility issues.
if you agree with this is an acceptable solution, I will submit a revised patch-set to address just the SRAM_SAVE_STATE_MAP_OFFSET.
(BTW, I'm re-evaluating the changes submitted for the PSD offset, with the goal of just using the default value and dropping those changes)
Thanks,
Leo.
> -----Original Message-----
> From: Duran, Leo
> Sent: Wednesday, October 11, 2017 2:46 PM
> To: edk2-devel@lists.01.org
> Cc: Duran, Leo <leo.duran@amd.com>; Jiewen Yao
> <jiewen.yao@intel.com>; Ruiyu Ni <ruiyu.ni@intel.com>; Michael D Kinney
> <michael.d.kinney@intel.com>; Jordan Justen <jordan.l.justen@intel.com>;
> Liming Gao <liming.gao@intel.com>
> Subject: [PATCH v5 1/2] UefiCpuPkg/SmmCpuFeaturesLib: Use global
> variables to replace macros
>
> Set global variables on Constructor function based on CPUID checks.
> The variables replace Intel macros to allow support on AMD x86 systems.
>
> Specifically, the replaced macros are:
> 1) SRAM_SAVE_STATE_MAP_OFFSET
> 2) TXT_SMM_PSD_OFFSET
>
> Cc: Jiewen Yao <jiewen.yao@intel.com>
> Cc: Ruiyu Ni <ruiyu.ni@intel.com>
> Cc: Michael D Kinney <michael.d.kinney@intel.com>
> Cc: Jordan Justen <jordan.l.justen@intel.com>
> Cc: Liming Gao <liming.gao@intel.com>
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Leo Duran <leo.duran@amd.com>
> ---
> .../Library/SmmCpuFeaturesLib/Ia32/SmiEntry.S | 28 ++++++----
> .../Library/SmmCpuFeaturesLib/Ia32/SmiEntry.asm | 29 +++++++----
> .../Library/SmmCpuFeaturesLib/Ia32/SmiEntry.nasm | 43 ++++++++++++---
> -
> UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCommon.h | 48
> ++++++++++++++++++
> .../Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c | 59
> ++++++++++++++++++----
> .../SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf | 3 ++
> .../SmmCpuFeaturesLib/SmmCpuFeaturesLibStm.inf | 3 ++
> UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c | 39
> ++++++++++++--
> .../Library/SmmCpuFeaturesLib/X64/SmiEntry.S | 28 ++++++----
> .../Library/SmmCpuFeaturesLib/X64/SmiEntry.asm | 30 +++++++----
> .../Library/SmmCpuFeaturesLib/X64/SmiEntry.nasm | 47 ++++++++++++---
> --
> 11 files changed, 282 insertions(+), 75 deletions(-) create mode 100644
> UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCommon.h
>
> diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.S
> b/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.S
> index 4c0f8c8..c7b49d7 100644
> --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.S
> +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.S
> @@ -1,6 +1,8 @@
> #------------------------------------------------------------------------------
> #
> # Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.<BR>
> +# Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR> #
> # This program and the accompanying materials # are licensed and made
> available under the terms and conditions of the BSD License # which
> accompanies this distribution. The full text of the license may be found at
> @@ -28,6 +30,9 @@ ASM_GLOBAL ASM_PFX(gStmSmbase) ASM_GLOBAL
> ASM_PFX(gStmXdSupported) ASM_GLOBAL ASM_PFX(FeaturePcdGet
> (PcdCpuSmmStackGuard)) ASM_GLOBAL ASM_PFX(gStmSmiHandlerIdtr)
> +ASM_GLOBAL ASM_PFX(gStmPsdOffset)
> +ASM_GLOBAL ASM_PFX(gStmGdtSize)
> +ASM_GLOBAL ASM_PFX(gStmGdtPtr)
>
> .equ MSR_IA32_MISC_ENABLE, 0x1A0
> .equ MSR_EFER, 0xc0000080
> @@ -36,12 +41,13 @@ ASM_GLOBAL ASM_PFX(gStmSmiHandlerIdtr) # #
> Constants relating to TXT_PROCESSOR_SMM_DESCRIPTOR #
> -.equ DSC_OFFSET, 0xfb00
> -.equ DSC_GDTPTR, 0x48
> -.equ DSC_GDTSIZ, 0x50
> -.equ DSC_CS, 0x14
> -.equ DSC_DS, 0x16
> -.equ DSC_SS, 0x18
> +# .equ DSC_OFFSET, 0xfb00
> +# .equ DSC_GDTPTR, 0x48
> +# .equ DSC_GDTSIZ, 0x50
> +#
> +.equ DSC_CS, 0x14
> +.equ DSC_DS, 0x16
> +.equ DSC_SS, 0x18
> .equ DSC_OTHERSEG, 0x1A
>
> .equ PROTECT_MODE_CS, 0x08
> @@ -55,11 +61,11 @@ _StmSmiEntryPoint:
> .byte 0xbb # mov bx, imm16
> .word _StmGdtDesc - _StmSmiEntryPoint + 0x8000
> .byte 0x2e,0xa1 # mov ax, cs:[offset16]
> - .word DSC_OFFSET + DSC_GDTSIZ
> +ASM_PFX(gStmGdtSize): .space 2 # .word DSC_OFFSET + DSC_GDTSIZ
> decl %eax
> movl %eax, %cs:(%edi) # mov cs:[bx], ax
> .byte 0x66,0x2e,0xa1 # mov eax, cs:[offset16]
> - .word DSC_OFFSET + DSC_GDTPTR
> +ASM_PFX(gStmGdtPtr): .space 2 # .word DSC_OFFSET + DSC_GDTPTR
> movw %ax, %cs:2(%edi)
> movw %ax, %bp # ebp = GDT base
> .byte 0x66
> @@ -167,7 +173,11 @@ XdDone:
> movl %cr0, %ebx
> orl $0x080010023, %ebx # enable paging + WP + NE + MP + PE
> movl %ebx, %cr0
> - leal DSC_OFFSET(%edi),%ebx
> +
> + movl $ASM_PFX(gStmPsdOffset), %ebx # leal DSC_OFFSET(%edi),
> %ebx
> + movzxw (%ebx), %esi
> + leal (%edi, %esi), %ebx
> +
> movw DSC_DS(%ebx),%ax
> movl %eax, %ds
> movw DSC_OTHERSEG(%ebx),%ax
> diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.asm
> b/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.asm
> index 91dc1eb..4dbe276 100644
> --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.asm
> +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.asm
> @@ -1,5 +1,7 @@
> ;------------------------------------------------------------------------------ ; ;
> Copyright (c) 2009 - 2017, Intel Corporation. All rights reserved.<BR>
> +; Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR> ;
> ; This program and the accompanying materials ; are licensed and made
> available under the terms and conditions of the BSD License ; which
> accompanies this distribution. The full text of the license may be found at
> @@ -29,13 +31,14 @@ MSR_EFER_XD EQU 0800h
> ;
> ; Constants relating to TXT_PROCESSOR_SMM_DESCRIPTOR ;
> -DSC_OFFSET EQU 0fb00h
> -DSC_GDTPTR EQU 48h
> -DSC_GDTSIZ EQU 50h
> -DSC_CS EQU 14h
> -DSC_DS EQU 16h
> -DSC_SS EQU 18h
> -DSC_OTHERSEG EQU 1Ah
> +; DSC_OFFSET EQU 0fb00h
> +; DSC_GDTPTR EQU 48h
> +; DSC_GDTSIZ EQU 50h
> +;
> +DSC_CS EQU 14h
> +DSC_DS EQU 16h
> +DSC_SS EQU 18h
> +DSC_OTHERSEG EQU 1Ah
>
> PROTECT_MODE_CS EQU 08h
> PROTECT_MODE_DS EQU 20h
> @@ -54,6 +57,9 @@ EXTERNDEF gStmSmbase:DWORD
> EXTERNDEF gStmXdSupported:BYTE
> EXTERNDEF FeaturePcdGet (PcdCpuSmmStackGuard):BYTE
> EXTERNDEF gStmSmiHandlerIdtr:FWORD
> +EXTERNDEF gStmPsdOffset:WORD
> +EXTERNDEF gStmGdtSize:WORD
> +EXTERNDEF gStmGdtPtr:WORD
>
> .code
>
> @@ -63,11 +69,11 @@ _StmSmiEntryPoint:
> DB 0bbh ; mov bx, imm16
> DW offset _StmGdtDesc - _StmSmiEntryPoint + 8000h
> DB 2eh, 0a1h ; mov ax, cs:[offset16]
> - DW DSC_OFFSET + DSC_GDTSIZ
> +gStmGdtSize DW ? ; DSC_OFFSET + DSC_GDTSIZ
> dec eax
> mov cs:[edi], eax ; mov cs:[bx], ax
> DB 66h, 2eh, 0a1h ; mov eax, cs:[offset16]
> - DW DSC_OFFSET + DSC_GDTPTR
> +gStmGdtPtr DW ? ; DSC_OFFSET + DSC_GDTPTR
> mov cs:[edi + 2], ax ; mov cs:[bx + 2], eax
> mov bp, ax ; ebp = GDT base
> DB 66h
> @@ -174,7 +180,10 @@ gStmXdSupported DB 1
> mov ebx, cr0
> or ebx, 080010023h ; enable paging + WP + NE + MP + PE
> mov cr0, ebx
> - lea ebx, [edi + DSC_OFFSET]
> +
> + movzx esi, word ptr [gStmPsdOffset] ; lea ebx, [edi + DSC_OFFSET]
> + lea ebx, [edi + esi] ;
> +
> mov ax, [ebx + DSC_DS]
> mov ds, eax
> mov ax, [ebx + DSC_OTHERSEG]
> diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.nasm
> b/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.nasm
> index 00c0f067..023923a 100644
> --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.nasm
> +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.nasm
> @@ -1,5 +1,7 @@
> ;------------------------------------------------------------------------------ ; ;
> Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
> +; Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR> ;
> ; This program and the accompanying materials ; are licensed and made
> available under the terms and conditions of the BSD License ; which
> accompanies this distribution. The full text of the license may be found at
> @@ -25,17 +27,18 @@ ; ; Constants relating to
> TXT_PROCESSOR_SMM_DESCRIPTOR ; -%define DSC_OFFSET 0xfb00 -
> %define DSC_GDTPTR 0x48 -%define DSC_GDTSIZ 0x50 -%define DSC_CS
> 0x14 -%define DSC_DS 0x16 -%define DSC_SS 0x18 -%define DSC_OTHERSEG
> 0x1a
> +; %define DSC_OFFSET 0xfb00
> +; %define DSC_GDTPTR 0x48
> +; %define DSC_GDTSIZ 0x50
> +;
> +%define DSC_CS 0x14
> +%define DSC_DS 0x16
> +%define DSC_SS 0x18
> +%define DSC_OTHERSEG 0x1a
>
> %define PROTECT_MODE_CS 0x8
> %define PROTECT_MODE_DS 0x20
> -%define TSS_SEGMENT 0x40
> +%define TSS_SEGMENT 0x40
>
> extern ASM_PFX(SmiRendezvous)
> extern ASM_PFX(FeaturePcdGet (PcdCpuSmmStackGuard)) @@ -51,6
> +54,10 @@ global ASM_PFX(gStmSmbase) global
> ASM_PFX(gStmXdSupported) extern ASM_PFX(gStmSmiHandlerIdtr)
>
> +extern ASM_PFX(gStmPsdOffset)
> +global ASM_PFX(gStmGdtSize)
> +global ASM_PFX(gStmGdtPtr)
> +
> ASM_PFX(gStmSmiCr3) EQU StmSmiCr3Patch - 4
> ASM_PFX(gStmSmiStack) EQU StmSmiStackPatch - 4
> ASM_PFX(gStmSmbase) EQU StmSmbasePatch - 4
> @@ -62,10 +69,18 @@ BITS 16
> ASM_PFX(gcStmSmiHandlerTemplate):
> _StmSmiEntryPoint:
> mov bx, _StmGdtDesc - _StmSmiEntryPoint + 0x8000
> - mov ax,[cs:DSC_OFFSET + DSC_GDTSIZ]
> +
> + mov eax, ASM_PFX(gStmGdtSize) ; mov ax, [cs:DSC_OFFSET +
> DSC_GDTSIZ]
> + mov si, [cs:eax] ;
> + mov ax, [cs:si] ;
> +
> dec ax
> mov [cs:bx], ax
> - mov eax, [cs:DSC_OFFSET + DSC_GDTPTR]
> +
> + mov eax, ASM_PFX(gStmGdtPtr) ; mov eax, [cs:DSC_OFFSET +
> DSC_GDTPTR]
> + mov si, [cs:eax] ;
> + mov eax, [cs:si] ;
> +
> mov [cs:bx + 2], eax
> mov ebp, eax ; ebp = GDT base
> o32 lgdt [cs:bx] ; lgdt fword ptr cs:[bx]
> @@ -166,7 +181,10 @@ StmXdSupportedPatch:
> mov ebx, cr0
> or ebx, 0x80010023 ; enable paging + WP + NE + MP + PE
> mov cr0, ebx
> - lea ebx, [edi + DSC_OFFSET]
> +
> + movzx esi, word [ASM_PFX(gStmPsdOffset)] ; lea ebx, [edi +
> DSC_OFFSET]
> + lea ebx, [edi + esi] ;
> +
> mov ax, [ebx + DSC_DS]
> mov ds, eax
> mov ax, [ebx + DSC_OTHERSEG]
> @@ -271,5 +289,8 @@ _StmSmiHandler:
> ; STM init finish
> jmp CommonHandler
>
> +ASM_PFX(gStmGdtSize) : RESW 1
> +ASM_PFX(gStmGdtPtr) : RESW 1
> +
> ASM_PFX(gcStmSmiHandlerSize) : DW $ - _StmSmiEntryPoint
> ASM_PFX(gcStmSmiHandlerOffset) : DW _StmSmiHandler -
> _StmSmiEntryPoint
> diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCommon.h
> b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCommon.h
> new file mode 100644
> index 0000000..78b3a5b
> --- /dev/null
> +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCommon.h
> @@ -0,0 +1,48 @@
> +/** @file
> + Common declarations
> +
> + Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>
> +
> + This program and the accompanying materials are licensed and made
> + available under the terms and conditions of the BSD License which
> + accompanies this distribution. The full text of the license may be
> + found at http://opensource.org/licenses/bsd-license.php.
> +
> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
> BASIS,
> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
> EXPRESS OR IMPLIED.
> +
> +**/
> +
> +#ifndef _SMM_COMMON_H_
> +#define _SMM_COMMON_H_
> +
> +#include <Register/Amd/Cpuid.h>
> +
> +//
> +// Definitions for AMD systems are based on contents of the // AMD64
> +Architecture Programmer's Manual // Volume 2: System Programming,
> +Section 10 System-Management Mode // #define
> +AMD_SMRAM_SAVE_STATE_MAP_OFFSET 0xfe00
> +#define AMD_SMM_PSD_OFFSET 0xfc00
> +
> +//
> +// External global variables for SMRAM offsets // extern UINT16
> +gSmramStateMapOffset; extern UINT16 gSmmPsdOffset;
> +
> +
> +/**
> + Determine if the standard CPU signature is "AuthenticAMD".
> +
> + @retval TRUE The CPU signature matches.
> + @retval FALSE The CPU signature does not match.
> +
> +**/
> +BOOLEAN
> +SmmStandardSignatureIsAuthenticAMD (
> + VOID
> + );
> +
> +#endif
> diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c
> b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c
> index 2d2bc6d..1c12095 100644
> --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c
> +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c
> @@ -1,14 +1,16 @@
> /** @file
> -The CPU specific programming for PiSmmCpuDxeSmm module.
> + The CPU specific programming for PiSmmCpuDxeSmm module.
>
> -Copyright (c) 2010 - 2016, Intel Corporation. All rights reserved.<BR> -This
> program and the accompanying materials -are licensed and made available
> under the terms and conditions of the BSD License -which accompanies this
> distribution. The full text of the license may be found at -
> http://opensource.org/licenses/bsd-license.php
> + Copyright (c) 2010 - 2016, Intel Corporation. All rights
> + reserved.<BR> Copyright (c) 2017, AMD Incorporated. All rights
> + reserved.<BR>
>
> -THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
> BASIS, -WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
> EXPRESS OR IMPLIED.
> + This program and the accompanying materials are licensed and made
> + available under the terms and conditions of the BSD License which
> + accompanies this distribution. The full text of the license may be
> + found at http://opensource.org/licenses/bsd-license.php
> +
> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
> BASIS,
> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
> EXPRESS OR IMPLIED.
>
> **/
>
> @@ -22,6 +24,8 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY
> KIND, EITHER EXPRESS OR IMPLIED.
> #include <Register/Cpuid.h>
> #include <Register/SmramSaveStateMap.h>
>
> +#include "SmmCommon.h"
> +
> //
> // Machine Specific Registers (MSRs)
> //
> @@ -41,6 +45,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY
> KIND, EITHER EXPRESS OR IMPLIED.
> #define SMM_FEATURES_LIB_IA32_MCA_CAP 0x17D
> #define SMM_CODE_ACCESS_CHK_BIT BIT58
>
> +
> /**
> Internal worker function that is called to complete CPU initialization at the
> end of SmmCpuFeaturesInitializeProcessor().
> @@ -77,6 +82,13 @@ BOOLEAN mNeedConfigureMtrrs = TRUE; //
> BOOLEAN *mSmrrEnabled;
>
> +//
> +// Set default value for SMRAM offset
> +// from <Register/SmramSaveStateMap.h> //
> +UINT16 gSmramStateMapOffset = SMRAM_SAVE_STATE_MAP_OFFSET;
> +
> +
> /**
> The constructor function
>
> @@ -99,6 +111,13 @@ SmmCpuFeaturesLibConstructor (
> UINTN ModelId;
>
> //
> + // Override SMRAM offset for AMD
> + //
> + if (SmmStandardSignatureIsAuthenticAMD ()) {
> + gSmramStateMapOffset = AMD_SMRAM_SAVE_STATE_MAP_OFFSET; }
> +
> + //
> // Retrieve CPU Family and Model
> //
> AsmCpuid (CPUID_VERSION_INFO, &RegEax, NULL, NULL, &RegEdx); @@ -
> 224,7 +243,7 @@ SmmCpuFeaturesInitializeProcessor (
> //
> // Configure SMBASE.
> //
> - CpuState = (SMRAM_SAVE_STATE_MAP
> *)(UINTN)(SMM_DEFAULT_SMBASE +
> SMRAM_SAVE_STATE_MAP_OFFSET);
> + CpuState = (SMRAM_SAVE_STATE_MAP
> *)(UINTN)(SMM_DEFAULT_SMBASE +
> + gSmramStateMapOffset);
> CpuState->x86.SMBASE = (UINT32)CpuHotPlugData->SmBase[CpuIndex];
>
> //
> @@ -630,3 +649,25 @@ SmmCpuFeaturesAllocatePageTableMemory (
> return NULL;
> }
>
> +
> +/**
> + Determine if the standard CPU signature is "AuthenticAMD".
> +
> + @retval TRUE The CPU signature matches.
> + @retval FALSE The CPU signature does not match.
> +
> +**/
> +BOOLEAN
> +SmmStandardSignatureIsAuthenticAMD (
> + VOID
> + )
> +{
> + UINT32 RegEbx;
> + UINT32 RegEcx;
> + UINT32 RegEdx;
> +
> + AsmCpuid (CPUID_SIGNATURE, NULL, &RegEbx, &RegEcx, &RegEdx);
> + return (RegEbx == CPUID_SIGNATURE_AUTHENTIC_AMD_EBX &&
> + RegEcx == CPUID_SIGNATURE_AUTHENTIC_AMD_ECX &&
> + RegEdx == CPUID_SIGNATURE_AUTHENTIC_AMD_EDX);
> +}
> diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf
> b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf
> index 77908b0..6a39d4b 100644
> --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf
> +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf
> @@ -2,6 +2,8 @@
> # The CPU specific programming for PiSmmCpuDxeSmm module.
> #
> # Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.<BR>
> +# Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR> #
> # This program and the accompanying materials # are licensed and made
> available under the terms and conditions of the BSD License # which
> accompanies this distribution. The full text of the license may be found at
> @@ -24,6 +26,7 @@
>
> [Sources]
> SmmCpuFeaturesLib.c
> + SmmCommon.h
> SmmCpuFeaturesLibNoStm.c
>
> [Packages]
> diff --git
> a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibStm.inf
> b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibStm.inf
> index db8dcdc..a76bed6 100644
> --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibStm.inf
> +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibStm.inf
> @@ -3,6 +3,8 @@
> # is included.
> #
> # Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.<BR>
> +# Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR> #
> # This program and the accompanying materials # are licensed and made
> available under the terms and conditions of the BSD License # which
> accompanies this distribution. The full text of the license may be found at
> @@ -25,6 +27,7 @@
>
> [Sources]
> SmmCpuFeaturesLib.c
> + SmmCommon.h
> SmmStm.c
> SmmStm.h
>
> diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c
> b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c
> index 45015b8..5f7c3db 100644
> --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c
> +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c
> @@ -2,6 +2,8 @@
> SMM STM support functions
>
> Copyright (c) 2015 - 2017, Intel Corporation. All rights reserved.<BR>
> + Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>
> +
> This program and the accompanying materials
> are licensed and made available under the terms and conditions of the BSD
> License
> which accompanies this distribution. The full text of the license may be
> found at @@ -28,6 +30,8 @@ #include <Protocol/MpService.h>
>
> #include "SmmStm.h"
> +#include "SmmCommon.h"
> +
>
> #define TXT_EVTYPE_BASE 0x400
> #define TXT_EVTYPE_STM_HASH (TXT_EVTYPE_BASE + 14)
> @@ -97,6 +101,20 @@ extern volatile UINT8
> gcStmSmiHandlerTemplate[];
> extern CONST UINT16 gcStmSmiHandlerSize;
> extern UINT16 gcStmSmiHandlerOffset;
> extern BOOLEAN gStmXdSupported;
> +extern UINT16 gStmGdtSize;
> +extern UINT16 gStmGdtPtr;
> +
> +//
> +// Constants relating to TXT_PROCESSOR_SMM_DESCRIPTOR //
> +#define TXT_PSD_GDTPTR 0x48
> +#define TXT_PSD_GDTSIZE 0x50
> +
> +//
> +// Set default value for PSD offset in SMRAM // from
> +<Register/StmApi.h> //
> +UINT16 gStmPsdOffset = TXT_SMM_PSD_OFFSET;
>
> //
> // Variables used by SMI Handler
> @@ -145,6 +163,19 @@ SmmCpuFeaturesLibStmConstructor (
> ASSERT_EFI_ERROR (Status);
>
> //
> + // Override PSD offset for AMD
> + //
> + if (SmmStandardSignatureIsAuthenticAMD ()) {
> + gStmPsdOffset = AMD_SMM_PSD_OFFSET; }
> +
> + //
> + // Initialize STM global variables associated with SMI Handler //
> + gStmGdtSize = gStmPsdOffset + TXT_PSD_GDTSIZE; gStmGdtPtr =
> + gStmPsdOffset + TXT_PSD_GDTPTR;
> +
> + //
> // Lookup the MP Services Protocol
> //
> Status = gBS->LocateProtocol (
> @@ -276,8 +307,8 @@ SmmCpuFeaturesInstallSmiHandler (
> UINT32 RegEdx;
> EFI_PROCESSOR_INFORMATION ProcessorInfo;
>
> - CopyMem ((VOID *)((UINTN)SmBase + TXT_SMM_PSD_OFFSET),
> &gcStmPsd, sizeof (gcStmPsd));
> - Psd = (TXT_PROCESSOR_SMM_DESCRIPTOR *)(VOID *)((UINTN)SmBase +
> TXT_SMM_PSD_OFFSET);
> + CopyMem ((VOID *)((UINTN)SmBase + gStmPsdOffset), &gcStmPsd,
> sizeof
> + (gcStmPsd)); Psd = (TXT_PROCESSOR_SMM_DESCRIPTOR *)(VOID
> + *)((UINTN)SmBase + gStmPsdOffset);
> Psd->SmmGdtPtr = GdtBase;
> Psd->SmmGdtSize = (UINT32)GdtSize;
>
> @@ -416,7 +447,7 @@ SmmEndOfDxeEventNotify (
> }
>
> for (Index = 0; Index < gSmst->NumberOfCpus; Index++) {
> - Psd = (TXT_PROCESSOR_SMM_DESCRIPTOR *)((UINTN)gSmst-
> >CpuSaveState[Index] - SMRAM_SAVE_STATE_MAP_OFFSET +
> TXT_SMM_PSD_OFFSET);
> + Psd = (TXT_PROCESSOR_SMM_DESCRIPTOR
> + *)((UINTN)gSmst->CpuSaveState[Index] - gSmramStateMapOffset +
> + gStmPsdOffset);
> DEBUG ((DEBUG_INFO, "Index=%d Psd=%p Rsdp=%p\n", Index, Psd,
> Rsdp));
> Psd->AcpiRsdp = (UINT64)(UINTN)Rsdp;
> }
> @@ -1266,7 +1297,7 @@ NotifyStmResourceChange (
> TXT_PROCESSOR_SMM_DESCRIPTOR *Psd;
>
> for (Index = 0; Index < gSmst->NumberOfCpus; Index++) {
> - Psd = (TXT_PROCESSOR_SMM_DESCRIPTOR *)((UINTN)gSmst-
> >CpuSaveState[Index] - SMRAM_SAVE_STATE_MAP_OFFSET +
> TXT_SMM_PSD_OFFSET);
> + Psd = (TXT_PROCESSOR_SMM_DESCRIPTOR
> + *)((UINTN)gSmst->CpuSaveState[Index] - gSmramStateMapOffset +
> + gStmPsdOffset);
> Psd->BiosHwResourceRequirementsPtr = (UINT64)(UINTN)StmResource;
> }
> return ;
> diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.S
> b/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.S
> index 1f9f91c..5f3386a 100644
> --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.S
> +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.S
> @@ -1,6 +1,8 @@
> #------------------------------------------------------------------------------
> #
> # Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.<BR>
> +# Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR> #
> # This program and the accompanying materials # are licensed and made
> available under the terms and conditions of the BSD License # which
> accompanies this distribution. The full text of the license may be found at
> @@ -27,6 +29,9 @@ ASM_GLOBAL ASM_PFX(gStmSmiStack) ASM_GLOBAL
> ASM_PFX(gStmSmbase) ASM_GLOBAL ASM_PFX(gStmXdSupported)
> ASM_GLOBAL ASM_PFX(gStmSmiHandlerIdtr)
> +ASM_GLOBAL ASM_PFX(gStmPsdOffset)
> +ASM_GLOBAL ASM_PFX(gStmGdtSize)
> +ASM_GLOBAL ASM_PFX(gStmGdtPtr)
>
> .equ MSR_IA32_MISC_ENABLE, 0x1A0
> .equ MSR_EFER, 0xc0000080
> @@ -35,12 +40,13 @@ ASM_GLOBAL ASM_PFX(gStmSmiHandlerIdtr) # #
> Constants relating to TXT_PROCESSOR_SMM_DESCRIPTOR #
> -.equ DSC_OFFSET, 0xfb00
> -.equ DSC_GDTPTR, 0x48
> -.equ DSC_GDTSIZ, 0x50
> -.equ DSC_CS, 0x14
> -.equ DSC_DS, 0x16
> -.equ DSC_SS, 0x18
> +# .equ DSC_OFFSET, 0xfb00
> +# .equ DSC_GDTPTR, 0x48
> +# .equ DSC_GDTSIZ, 0x50
> +#
> +.equ DSC_CS, 0x14
> +.equ DSC_DS, 0x16
> +.equ DSC_SS, 0x18
> .equ DSC_OTHERSEG, 0x1a
> #
> # Constants relating to CPU State Save Area @@ -71,12 +77,12 @@
> _StmSmiEntryPoint:
> # fix GDT descriptor
> #
> .byte 0x2e,0xa1 # mov ax, cs:[offset16]
> - .word DSC_OFFSET + DSC_GDTSIZ
> +ASM_PFX(gStmGdtSize): .space 2 # .word DSC_OFFSET + DSC_GDTSIZ
> .byte 0x48 # dec ax
> .byte 0x2e
> movl %eax, (%rdi) # mov cs:[bx], ax
> .byte 0x66,0x2e,0xa1 # mov eax, cs:[offset16]
> - .word DSC_OFFSET + DSC_GDTPTR
> +ASM_PFX(gStmGdtPtr): .space 2 # .word DSC_OFFSET + DSC_GDTPTR
> .byte 0x2e
> movw %ax, 2(%rdi)
> .byte 0x66,0x2e
> @@ -183,7 +189,11 @@ Base:
> LongMode: # long mode (64-bit code) starts here
> movabsq $ASM_PFX(gStmSmiHandlerIdtr), %rax
> lidt (%rax)
> - lea (DSC_OFFSET)(%rdi), %ebx
> +
> + movl $ASM_PFX(gStmPsdOffset), %ebx # lea (DSC_OFFSET)(%rdi),
> %ebx
> + movzxw (%ebx), %rsi
> + leal (%rdi, %rsi), %ebx
> +
> movw DSC_DS(%rbx), %ax
> movl %eax,%ds
> movw DSC_OTHERSEG(%rbx), %ax
> diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.asm
> b/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.asm
> index ad51e07..10913df 100644
> --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.asm
> +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.asm
> @@ -1,5 +1,7 @@
> ;------------------------------------------------------------------------------ ; ;
> Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.<BR>
> +; Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR> ;
> ; This program and the accompanying materials ; are licensed and made
> available under the terms and conditions of the BSD License ; which
> accompanies this distribution. The full text of the license may be found at
> @@ -32,6 +34,10 @@ EXTERNDEF gStmSmiStack:DWORD
> EXTERNDEF gStmSmbase:DWORD
> EXTERNDEF gStmXdSupported:BYTE
> EXTERNDEF gStmSmiHandlerIdtr:FWORD
> +EXTERNDEF gStmPsdOffset:WORD
> +EXTERNDEF gStmGdtSize:WORD
> +EXTERNDEF gStmGdtPtr:WORD
> +
>
> MSR_IA32_MISC_ENABLE EQU 1A0h
> MSR_EFER EQU 0c0000080h
> @@ -40,13 +46,14 @@ MSR_EFER_XD EQU 0800h
> ;
> ; Constants relating to TXT_PROCESSOR_SMM_DESCRIPTOR ;
> -DSC_OFFSET EQU 0fb00h
> -DSC_GDTPTR EQU 48h
> -DSC_GDTSIZ EQU 50h
> -DSC_CS EQU 14h
> -DSC_DS EQU 16h
> -DSC_SS EQU 18h
> -DSC_OTHERSEG EQU 1ah
> +; DSC_OFFSET EQU 0fb00h
> +; DSC_GDTPTR EQU 48h
> +; DSC_GDTSIZ EQU 50h
> +;
> +DSC_CS EQU 14h
> +DSC_DS EQU 16h
> +DSC_SS EQU 18h
> +DSC_OTHERSEG EQU 1ah
> ;
> ; Constants relating to CPU State Save Area ; @@ -74,12 +81,12 @@
> _StmSmiEntryPoint:
> DW offset _StmGdtDesc - _StmSmiEntryPoint + 8000h ; bx = GdtDesc
> offset
> ; fix GDT descriptor
> DB 2eh, 0a1h ; mov ax, cs:[offset16]
> - DW DSC_OFFSET + DSC_GDTSIZ
> +gStmGdtSize DW ? ; DSC_OFFSET + DSC_GDTSIZ
> DB 48h ; dec ax
> DB 2eh
> mov [rdi], eax ; mov cs:[bx], ax
> DB 66h, 2eh, 0a1h ; mov eax, cs:[offset16]
> - DW DSC_OFFSET + DSC_GDTPTR
> +gStmGdtPtr DW ? ; DSC_OFFSET + DSC_GDTPTR
> DB 2eh
> mov [rdi + 2], ax ; mov cs:[bx + 2], eax
> DB 66h, 2eh
> @@ -178,7 +185,10 @@ Base:
> @LongMode: ; long mode (64-bit code) starts here
> mov rax, offset gStmSmiHandlerIdtr
> lidt fword ptr [rax]
> - lea ebx, [rdi + DSC_OFFSET]
> +
> + movzx rsi, word ptr [gStmPsdOffset] ; lea ebx, [rdi + DSC_OFFSET]
> + lea ebx, [rdi + rsi] ;
> +
> mov ax, [rbx + DSC_DS]
> mov ds, eax
> mov ax, [rbx + DSC_OTHERSEG]
> diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.nasm
> b/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.nasm
> index bcac643..df4c5a2 100644
> --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.nasm
> +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.nasm
> @@ -1,5 +1,7 @@
> ;------------------------------------------------------------------------------ ; ;
> Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
> +; Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR> ;
> ; This program and the accompanying materials ; are licensed and made
> available under the terms and conditions of the BSD License ; which
> accompanies this distribution. The full text of the license may be found at
> @@ -29,13 +31,14 @@ ; ; Constants relating to
> TXT_PROCESSOR_SMM_DESCRIPTOR ; -%define DSC_OFFSET 0xfb00 -
> %define DSC_GDTPTR 0x48 -%define DSC_GDTSIZ 0x50 -%define DSC_CS
> 0x14 -%define DSC_DS 0x16 -%define DSC_SS 0x18 -%define DSC_OTHERSEG
> 0x1a
> +; %define DSC_OFFSET 0xfb00
> +; %define DSC_GDTPTR 0x48
> +; %define DSC_GDTSIZ 0x50
> +;
> +%define DSC_CS 0x14
> +%define DSC_DS 0x16
> +%define DSC_SS 0x18
> +%define DSC_OTHERSEG 0x1a
> ;
> ; Constants relating to CPU State Save Area ; @@ -44,9 +47,9 @@
>
> %define PROTECT_MODE_CS 0x8
> %define PROTECT_MODE_DS 0x20
> -%define LONG_MODE_CS 0x38
> -%define TSS_SEGMENT 0x40
> -%define GDT_SIZE 0x50
> +%define LONG_MODE_CS 0x38
> +%define TSS_SEGMENT 0x40
> +%define GDT_SIZE 0x50
>
> extern ASM_PFX(SmiRendezvous)
> extern ASM_PFX(gStmSmiHandlerIdtr)
> @@ -61,6 +64,10 @@ global ASM_PFX(gcStmSmiHandlerTemplate) global
> ASM_PFX(gcStmSmiHandlerSize) global ASM_PFX(gcStmSmiHandlerOffset)
>
> +extern ASM_PFX(gStmPsdOffset)
> +global ASM_PFX(gStmGdtSize)
> +global ASM_PFX(gStmGdtPtr)
> +
> ASM_PFX(gStmSmbase) EQU StmSmbasePatch - 4
> ASM_PFX(gStmSmiStack) EQU StmSmiStackPatch - 4
> ASM_PFX(gStmSmiCr3) EQU StmSmiCr3Patch - 4
> @@ -73,10 +80,18 @@ BITS 16
> ASM_PFX(gcStmSmiHandlerTemplate):
> _StmSmiEntryPoint:
> mov bx, _StmGdtDesc - _StmSmiEntryPoint + 0x8000
> - mov ax,[cs:DSC_OFFSET + DSC_GDTSIZ]
> +
> + mov eax, ASM_PFX(gStmGdtSize) ; mov ax, [cs:DSC_OFFSET +
> DSC_GDTSIZ]
> + mov si, [cs:eax] ;
> + mov ax, [cs:si] ;
> +
> dec ax
> mov [cs:bx], ax
> - mov eax, [cs:DSC_OFFSET + DSC_GDTPTR]
> +
> + mov eax, ASM_PFX(gStmGdtPtr) ; mov eax, [cs:DSC_OFFSET +
> DSC_GDTPTR]
> + mov si, [cs:eax] ;
> + mov eax, [cs:si] ;
> +
> mov [cs:bx + 2], eax
> o32 lgdt [cs:bx] ; lgdt fword ptr cs:[bx]
> mov ax, PROTECT_MODE_CS
> @@ -166,7 +181,10 @@ Base:
> @LongMode: ; long mode (64-bit code) starts here
> mov rax, ASM_PFX(gStmSmiHandlerIdtr)
> lidt [rax]
> - lea ebx, [rdi + DSC_OFFSET]
> +
> + movzx rsi, word [ASM_PFX(gStmPsdOffset)] ; lea ebx, [rdi +
> DSC_OFFSET]
> + lea ebx, [rdi + rsi] ;
> +
> mov ax, [rbx + DSC_DS]
> mov ds, eax
> mov ax, [rbx + DSC_OTHERSEG]
> @@ -262,5 +280,8 @@ _StmSmiHandler:
> ; STM init finish
> jmp CommonHandler
>
> +ASM_PFX(gStmGdtSize) : RESW 1
> +ASM_PFX(gStmGdtPtr) : RESW 1
> +
> ASM_PFX(gcStmSmiHandlerSize) : DW $ - _StmSmiEntryPoint
> ASM_PFX(gcStmSmiHandlerOffset) : DW _StmSmiHandler -
> _StmSmiEntryPoint
> --
> 2.7.4
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH v5 1/2] UefiCpuPkg/SmmCpuFeaturesLib: Use global variables to replace macros
2017-10-17 14:19 ` Duran, Leo
@ 2017-10-17 14:23 ` Laszlo Ersek
2017-10-17 14:37 ` Paolo Bonzini
2017-10-17 14:50 ` Yao, Jiewen
1 sibling, 1 reply; 30+ messages in thread
From: Laszlo Ersek @ 2017-10-17 14:23 UTC (permalink / raw)
To: Duran, Leo, edk2-devel@lists.01.org, Jiewen Yao, Paolo Bonzini
Cc: Ruiyu Ni, Michael D Kinney, Jordan Justen, Liming Gao
On 10/17/17 16:19, Duran, Leo wrote:
> Yao, Lazlo, et al,
>
> For the SRAM_SAVE_STATE_MAP_OFFSET:
> I propose returning the value by a function in SmmCpuFeaturesLib...
This has crossed my mind (superficially :) ), and I support your idea.
Paolo, can you please comment?
Thanks!
Laszlo
> Here's the rationale:
> - The value is fixed per CPU architecture, so this qualifies as a CPU feature.
> - The logic for CPU architecture detection would be in one place (e.g., PiSmmCpuDxeSmm would call the library function)
> - The OVMF and Quark instances of the library could just return the current (default) value, so no compatibility issues.
>
> if you agree with this is an acceptable solution, I will submit a revised patch-set to address just the SRAM_SAVE_STATE_MAP_OFFSET.
> (BTW, I'm re-evaluating the changes submitted for the PSD offset, with the goal of just using the default value and dropping those changes)
>
> Thanks,
> Leo.
>
>> -----Original Message-----
>> From: Duran, Leo
>> Sent: Wednesday, October 11, 2017 2:46 PM
>> To: edk2-devel@lists.01.org
>> Cc: Duran, Leo <leo.duran@amd.com>; Jiewen Yao
>> <jiewen.yao@intel.com>; Ruiyu Ni <ruiyu.ni@intel.com>; Michael D Kinney
>> <michael.d.kinney@intel.com>; Jordan Justen <jordan.l.justen@intel.com>;
>> Liming Gao <liming.gao@intel.com>
>> Subject: [PATCH v5 1/2] UefiCpuPkg/SmmCpuFeaturesLib: Use global
>> variables to replace macros
>>
>> Set global variables on Constructor function based on CPUID checks.
>> The variables replace Intel macros to allow support on AMD x86 systems.
>>
>> Specifically, the replaced macros are:
>> 1) SRAM_SAVE_STATE_MAP_OFFSET
>> 2) TXT_SMM_PSD_OFFSET
>>
>> Cc: Jiewen Yao <jiewen.yao@intel.com>
>> Cc: Ruiyu Ni <ruiyu.ni@intel.com>
>> Cc: Michael D Kinney <michael.d.kinney@intel.com>
>> Cc: Jordan Justen <jordan.l.justen@intel.com>
>> Cc: Liming Gao <liming.gao@intel.com>
>> Contributed-under: TianoCore Contribution Agreement 1.1
>> Signed-off-by: Leo Duran <leo.duran@amd.com>
>> ---
>> .../Library/SmmCpuFeaturesLib/Ia32/SmiEntry.S | 28 ++++++----
>> .../Library/SmmCpuFeaturesLib/Ia32/SmiEntry.asm | 29 +++++++----
>> .../Library/SmmCpuFeaturesLib/Ia32/SmiEntry.nasm | 43 ++++++++++++---
>> -
>> UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCommon.h | 48
>> ++++++++++++++++++
>> .../Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c | 59
>> ++++++++++++++++++----
>> .../SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf | 3 ++
>> .../SmmCpuFeaturesLib/SmmCpuFeaturesLibStm.inf | 3 ++
>> UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c | 39
>> ++++++++++++--
>> .../Library/SmmCpuFeaturesLib/X64/SmiEntry.S | 28 ++++++----
>> .../Library/SmmCpuFeaturesLib/X64/SmiEntry.asm | 30 +++++++----
>> .../Library/SmmCpuFeaturesLib/X64/SmiEntry.nasm | 47 ++++++++++++---
>> --
>> 11 files changed, 282 insertions(+), 75 deletions(-) create mode 100644
>> UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCommon.h
>>
>> diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.S
>> b/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.S
>> index 4c0f8c8..c7b49d7 100644
>> --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.S
>> +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.S
>> @@ -1,6 +1,8 @@
>> #------------------------------------------------------------------------------
>> #
>> # Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.<BR>
>> +# Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR> #
>> # This program and the accompanying materials # are licensed and made
>> available under the terms and conditions of the BSD License # which
>> accompanies this distribution. The full text of the license may be found at
>> @@ -28,6 +30,9 @@ ASM_GLOBAL ASM_PFX(gStmSmbase) ASM_GLOBAL
>> ASM_PFX(gStmXdSupported) ASM_GLOBAL ASM_PFX(FeaturePcdGet
>> (PcdCpuSmmStackGuard)) ASM_GLOBAL ASM_PFX(gStmSmiHandlerIdtr)
>> +ASM_GLOBAL ASM_PFX(gStmPsdOffset)
>> +ASM_GLOBAL ASM_PFX(gStmGdtSize)
>> +ASM_GLOBAL ASM_PFX(gStmGdtPtr)
>>
>> .equ MSR_IA32_MISC_ENABLE, 0x1A0
>> .equ MSR_EFER, 0xc0000080
>> @@ -36,12 +41,13 @@ ASM_GLOBAL ASM_PFX(gStmSmiHandlerIdtr) # #
>> Constants relating to TXT_PROCESSOR_SMM_DESCRIPTOR #
>> -.equ DSC_OFFSET, 0xfb00
>> -.equ DSC_GDTPTR, 0x48
>> -.equ DSC_GDTSIZ, 0x50
>> -.equ DSC_CS, 0x14
>> -.equ DSC_DS, 0x16
>> -.equ DSC_SS, 0x18
>> +# .equ DSC_OFFSET, 0xfb00
>> +# .equ DSC_GDTPTR, 0x48
>> +# .equ DSC_GDTSIZ, 0x50
>> +#
>> +.equ DSC_CS, 0x14
>> +.equ DSC_DS, 0x16
>> +.equ DSC_SS, 0x18
>> .equ DSC_OTHERSEG, 0x1A
>>
>> .equ PROTECT_MODE_CS, 0x08
>> @@ -55,11 +61,11 @@ _StmSmiEntryPoint:
>> .byte 0xbb # mov bx, imm16
>> .word _StmGdtDesc - _StmSmiEntryPoint + 0x8000
>> .byte 0x2e,0xa1 # mov ax, cs:[offset16]
>> - .word DSC_OFFSET + DSC_GDTSIZ
>> +ASM_PFX(gStmGdtSize): .space 2 # .word DSC_OFFSET + DSC_GDTSIZ
>> decl %eax
>> movl %eax, %cs:(%edi) # mov cs:[bx], ax
>> .byte 0x66,0x2e,0xa1 # mov eax, cs:[offset16]
>> - .word DSC_OFFSET + DSC_GDTPTR
>> +ASM_PFX(gStmGdtPtr): .space 2 # .word DSC_OFFSET + DSC_GDTPTR
>> movw %ax, %cs:2(%edi)
>> movw %ax, %bp # ebp = GDT base
>> .byte 0x66
>> @@ -167,7 +173,11 @@ XdDone:
>> movl %cr0, %ebx
>> orl $0x080010023, %ebx # enable paging + WP + NE + MP + PE
>> movl %ebx, %cr0
>> - leal DSC_OFFSET(%edi),%ebx
>> +
>> + movl $ASM_PFX(gStmPsdOffset), %ebx # leal DSC_OFFSET(%edi),
>> %ebx
>> + movzxw (%ebx), %esi
>> + leal (%edi, %esi), %ebx
>> +
>> movw DSC_DS(%ebx),%ax
>> movl %eax, %ds
>> movw DSC_OTHERSEG(%ebx),%ax
>> diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.asm
>> b/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.asm
>> index 91dc1eb..4dbe276 100644
>> --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.asm
>> +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.asm
>> @@ -1,5 +1,7 @@
>> ;------------------------------------------------------------------------------ ; ;
>> Copyright (c) 2009 - 2017, Intel Corporation. All rights reserved.<BR>
>> +; Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR> ;
>> ; This program and the accompanying materials ; are licensed and made
>> available under the terms and conditions of the BSD License ; which
>> accompanies this distribution. The full text of the license may be found at
>> @@ -29,13 +31,14 @@ MSR_EFER_XD EQU 0800h
>> ;
>> ; Constants relating to TXT_PROCESSOR_SMM_DESCRIPTOR ;
>> -DSC_OFFSET EQU 0fb00h
>> -DSC_GDTPTR EQU 48h
>> -DSC_GDTSIZ EQU 50h
>> -DSC_CS EQU 14h
>> -DSC_DS EQU 16h
>> -DSC_SS EQU 18h
>> -DSC_OTHERSEG EQU 1Ah
>> +; DSC_OFFSET EQU 0fb00h
>> +; DSC_GDTPTR EQU 48h
>> +; DSC_GDTSIZ EQU 50h
>> +;
>> +DSC_CS EQU 14h
>> +DSC_DS EQU 16h
>> +DSC_SS EQU 18h
>> +DSC_OTHERSEG EQU 1Ah
>>
>> PROTECT_MODE_CS EQU 08h
>> PROTECT_MODE_DS EQU 20h
>> @@ -54,6 +57,9 @@ EXTERNDEF gStmSmbase:DWORD
>> EXTERNDEF gStmXdSupported:BYTE
>> EXTERNDEF FeaturePcdGet (PcdCpuSmmStackGuard):BYTE
>> EXTERNDEF gStmSmiHandlerIdtr:FWORD
>> +EXTERNDEF gStmPsdOffset:WORD
>> +EXTERNDEF gStmGdtSize:WORD
>> +EXTERNDEF gStmGdtPtr:WORD
>>
>> .code
>>
>> @@ -63,11 +69,11 @@ _StmSmiEntryPoint:
>> DB 0bbh ; mov bx, imm16
>> DW offset _StmGdtDesc - _StmSmiEntryPoint + 8000h
>> DB 2eh, 0a1h ; mov ax, cs:[offset16]
>> - DW DSC_OFFSET + DSC_GDTSIZ
>> +gStmGdtSize DW ? ; DSC_OFFSET + DSC_GDTSIZ
>> dec eax
>> mov cs:[edi], eax ; mov cs:[bx], ax
>> DB 66h, 2eh, 0a1h ; mov eax, cs:[offset16]
>> - DW DSC_OFFSET + DSC_GDTPTR
>> +gStmGdtPtr DW ? ; DSC_OFFSET + DSC_GDTPTR
>> mov cs:[edi + 2], ax ; mov cs:[bx + 2], eax
>> mov bp, ax ; ebp = GDT base
>> DB 66h
>> @@ -174,7 +180,10 @@ gStmXdSupported DB 1
>> mov ebx, cr0
>> or ebx, 080010023h ; enable paging + WP + NE + MP + PE
>> mov cr0, ebx
>> - lea ebx, [edi + DSC_OFFSET]
>> +
>> + movzx esi, word ptr [gStmPsdOffset] ; lea ebx, [edi + DSC_OFFSET]
>> + lea ebx, [edi + esi] ;
>> +
>> mov ax, [ebx + DSC_DS]
>> mov ds, eax
>> mov ax, [ebx + DSC_OTHERSEG]
>> diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.nasm
>> b/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.nasm
>> index 00c0f067..023923a 100644
>> --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.nasm
>> +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.nasm
>> @@ -1,5 +1,7 @@
>> ;------------------------------------------------------------------------------ ; ;
>> Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
>> +; Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR> ;
>> ; This program and the accompanying materials ; are licensed and made
>> available under the terms and conditions of the BSD License ; which
>> accompanies this distribution. The full text of the license may be found at
>> @@ -25,17 +27,18 @@ ; ; Constants relating to
>> TXT_PROCESSOR_SMM_DESCRIPTOR ; -%define DSC_OFFSET 0xfb00 -
>> %define DSC_GDTPTR 0x48 -%define DSC_GDTSIZ 0x50 -%define DSC_CS
>> 0x14 -%define DSC_DS 0x16 -%define DSC_SS 0x18 -%define DSC_OTHERSEG
>> 0x1a
>> +; %define DSC_OFFSET 0xfb00
>> +; %define DSC_GDTPTR 0x48
>> +; %define DSC_GDTSIZ 0x50
>> +;
>> +%define DSC_CS 0x14
>> +%define DSC_DS 0x16
>> +%define DSC_SS 0x18
>> +%define DSC_OTHERSEG 0x1a
>>
>> %define PROTECT_MODE_CS 0x8
>> %define PROTECT_MODE_DS 0x20
>> -%define TSS_SEGMENT 0x40
>> +%define TSS_SEGMENT 0x40
>>
>> extern ASM_PFX(SmiRendezvous)
>> extern ASM_PFX(FeaturePcdGet (PcdCpuSmmStackGuard)) @@ -51,6
>> +54,10 @@ global ASM_PFX(gStmSmbase) global
>> ASM_PFX(gStmXdSupported) extern ASM_PFX(gStmSmiHandlerIdtr)
>>
>> +extern ASM_PFX(gStmPsdOffset)
>> +global ASM_PFX(gStmGdtSize)
>> +global ASM_PFX(gStmGdtPtr)
>> +
>> ASM_PFX(gStmSmiCr3) EQU StmSmiCr3Patch - 4
>> ASM_PFX(gStmSmiStack) EQU StmSmiStackPatch - 4
>> ASM_PFX(gStmSmbase) EQU StmSmbasePatch - 4
>> @@ -62,10 +69,18 @@ BITS 16
>> ASM_PFX(gcStmSmiHandlerTemplate):
>> _StmSmiEntryPoint:
>> mov bx, _StmGdtDesc - _StmSmiEntryPoint + 0x8000
>> - mov ax,[cs:DSC_OFFSET + DSC_GDTSIZ]
>> +
>> + mov eax, ASM_PFX(gStmGdtSize) ; mov ax, [cs:DSC_OFFSET +
>> DSC_GDTSIZ]
>> + mov si, [cs:eax] ;
>> + mov ax, [cs:si] ;
>> +
>> dec ax
>> mov [cs:bx], ax
>> - mov eax, [cs:DSC_OFFSET + DSC_GDTPTR]
>> +
>> + mov eax, ASM_PFX(gStmGdtPtr) ; mov eax, [cs:DSC_OFFSET +
>> DSC_GDTPTR]
>> + mov si, [cs:eax] ;
>> + mov eax, [cs:si] ;
>> +
>> mov [cs:bx + 2], eax
>> mov ebp, eax ; ebp = GDT base
>> o32 lgdt [cs:bx] ; lgdt fword ptr cs:[bx]
>> @@ -166,7 +181,10 @@ StmXdSupportedPatch:
>> mov ebx, cr0
>> or ebx, 0x80010023 ; enable paging + WP + NE + MP + PE
>> mov cr0, ebx
>> - lea ebx, [edi + DSC_OFFSET]
>> +
>> + movzx esi, word [ASM_PFX(gStmPsdOffset)] ; lea ebx, [edi +
>> DSC_OFFSET]
>> + lea ebx, [edi + esi] ;
>> +
>> mov ax, [ebx + DSC_DS]
>> mov ds, eax
>> mov ax, [ebx + DSC_OTHERSEG]
>> @@ -271,5 +289,8 @@ _StmSmiHandler:
>> ; STM init finish
>> jmp CommonHandler
>>
>> +ASM_PFX(gStmGdtSize) : RESW 1
>> +ASM_PFX(gStmGdtPtr) : RESW 1
>> +
>> ASM_PFX(gcStmSmiHandlerSize) : DW $ - _StmSmiEntryPoint
>> ASM_PFX(gcStmSmiHandlerOffset) : DW _StmSmiHandler -
>> _StmSmiEntryPoint
>> diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCommon.h
>> b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCommon.h
>> new file mode 100644
>> index 0000000..78b3a5b
>> --- /dev/null
>> +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCommon.h
>> @@ -0,0 +1,48 @@
>> +/** @file
>> + Common declarations
>> +
>> + Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>
>> +
>> + This program and the accompanying materials are licensed and made
>> + available under the terms and conditions of the BSD License which
>> + accompanies this distribution. The full text of the license may be
>> + found at http://opensource.org/licenses/bsd-license.php.
>> +
>> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
>> BASIS,
>> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
>> EXPRESS OR IMPLIED.
>> +
>> +**/
>> +
>> +#ifndef _SMM_COMMON_H_
>> +#define _SMM_COMMON_H_
>> +
>> +#include <Register/Amd/Cpuid.h>
>> +
>> +//
>> +// Definitions for AMD systems are based on contents of the // AMD64
>> +Architecture Programmer's Manual // Volume 2: System Programming,
>> +Section 10 System-Management Mode // #define
>> +AMD_SMRAM_SAVE_STATE_MAP_OFFSET 0xfe00
>> +#define AMD_SMM_PSD_OFFSET 0xfc00
>> +
>> +//
>> +// External global variables for SMRAM offsets // extern UINT16
>> +gSmramStateMapOffset; extern UINT16 gSmmPsdOffset;
>> +
>> +
>> +/**
>> + Determine if the standard CPU signature is "AuthenticAMD".
>> +
>> + @retval TRUE The CPU signature matches.
>> + @retval FALSE The CPU signature does not match.
>> +
>> +**/
>> +BOOLEAN
>> +SmmStandardSignatureIsAuthenticAMD (
>> + VOID
>> + );
>> +
>> +#endif
>> diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c
>> b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c
>> index 2d2bc6d..1c12095 100644
>> --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c
>> +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c
>> @@ -1,14 +1,16 @@
>> /** @file
>> -The CPU specific programming for PiSmmCpuDxeSmm module.
>> + The CPU specific programming for PiSmmCpuDxeSmm module.
>>
>> -Copyright (c) 2010 - 2016, Intel Corporation. All rights reserved.<BR> -This
>> program and the accompanying materials -are licensed and made available
>> under the terms and conditions of the BSD License -which accompanies this
>> distribution. The full text of the license may be found at -
>> http://opensource.org/licenses/bsd-license.php
>> + Copyright (c) 2010 - 2016, Intel Corporation. All rights
>> + reserved.<BR> Copyright (c) 2017, AMD Incorporated. All rights
>> + reserved.<BR>
>>
>> -THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
>> BASIS, -WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
>> EXPRESS OR IMPLIED.
>> + This program and the accompanying materials are licensed and made
>> + available under the terms and conditions of the BSD License which
>> + accompanies this distribution. The full text of the license may be
>> + found at http://opensource.org/licenses/bsd-license.php
>> +
>> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
>> BASIS,
>> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
>> EXPRESS OR IMPLIED.
>>
>> **/
>>
>> @@ -22,6 +24,8 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY
>> KIND, EITHER EXPRESS OR IMPLIED.
>> #include <Register/Cpuid.h>
>> #include <Register/SmramSaveStateMap.h>
>>
>> +#include "SmmCommon.h"
>> +
>> //
>> // Machine Specific Registers (MSRs)
>> //
>> @@ -41,6 +45,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY
>> KIND, EITHER EXPRESS OR IMPLIED.
>> #define SMM_FEATURES_LIB_IA32_MCA_CAP 0x17D
>> #define SMM_CODE_ACCESS_CHK_BIT BIT58
>>
>> +
>> /**
>> Internal worker function that is called to complete CPU initialization at the
>> end of SmmCpuFeaturesInitializeProcessor().
>> @@ -77,6 +82,13 @@ BOOLEAN mNeedConfigureMtrrs = TRUE; //
>> BOOLEAN *mSmrrEnabled;
>>
>> +//
>> +// Set default value for SMRAM offset
>> +// from <Register/SmramSaveStateMap.h> //
>> +UINT16 gSmramStateMapOffset = SMRAM_SAVE_STATE_MAP_OFFSET;
>> +
>> +
>> /**
>> The constructor function
>>
>> @@ -99,6 +111,13 @@ SmmCpuFeaturesLibConstructor (
>> UINTN ModelId;
>>
>> //
>> + // Override SMRAM offset for AMD
>> + //
>> + if (SmmStandardSignatureIsAuthenticAMD ()) {
>> + gSmramStateMapOffset = AMD_SMRAM_SAVE_STATE_MAP_OFFSET; }
>> +
>> + //
>> // Retrieve CPU Family and Model
>> //
>> AsmCpuid (CPUID_VERSION_INFO, &RegEax, NULL, NULL, &RegEdx); @@ -
>> 224,7 +243,7 @@ SmmCpuFeaturesInitializeProcessor (
>> //
>> // Configure SMBASE.
>> //
>> - CpuState = (SMRAM_SAVE_STATE_MAP
>> *)(UINTN)(SMM_DEFAULT_SMBASE +
>> SMRAM_SAVE_STATE_MAP_OFFSET);
>> + CpuState = (SMRAM_SAVE_STATE_MAP
>> *)(UINTN)(SMM_DEFAULT_SMBASE +
>> + gSmramStateMapOffset);
>> CpuState->x86.SMBASE = (UINT32)CpuHotPlugData->SmBase[CpuIndex];
>>
>> //
>> @@ -630,3 +649,25 @@ SmmCpuFeaturesAllocatePageTableMemory (
>> return NULL;
>> }
>>
>> +
>> +/**
>> + Determine if the standard CPU signature is "AuthenticAMD".
>> +
>> + @retval TRUE The CPU signature matches.
>> + @retval FALSE The CPU signature does not match.
>> +
>> +**/
>> +BOOLEAN
>> +SmmStandardSignatureIsAuthenticAMD (
>> + VOID
>> + )
>> +{
>> + UINT32 RegEbx;
>> + UINT32 RegEcx;
>> + UINT32 RegEdx;
>> +
>> + AsmCpuid (CPUID_SIGNATURE, NULL, &RegEbx, &RegEcx, &RegEdx);
>> + return (RegEbx == CPUID_SIGNATURE_AUTHENTIC_AMD_EBX &&
>> + RegEcx == CPUID_SIGNATURE_AUTHENTIC_AMD_ECX &&
>> + RegEdx == CPUID_SIGNATURE_AUTHENTIC_AMD_EDX);
>> +}
>> diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf
>> b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf
>> index 77908b0..6a39d4b 100644
>> --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf
>> +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf
>> @@ -2,6 +2,8 @@
>> # The CPU specific programming for PiSmmCpuDxeSmm module.
>> #
>> # Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.<BR>
>> +# Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR> #
>> # This program and the accompanying materials # are licensed and made
>> available under the terms and conditions of the BSD License # which
>> accompanies this distribution. The full text of the license may be found at
>> @@ -24,6 +26,7 @@
>>
>> [Sources]
>> SmmCpuFeaturesLib.c
>> + SmmCommon.h
>> SmmCpuFeaturesLibNoStm.c
>>
>> [Packages]
>> diff --git
>> a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibStm.inf
>> b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibStm.inf
>> index db8dcdc..a76bed6 100644
>> --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibStm.inf
>> +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibStm.inf
>> @@ -3,6 +3,8 @@
>> # is included.
>> #
>> # Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.<BR>
>> +# Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR> #
>> # This program and the accompanying materials # are licensed and made
>> available under the terms and conditions of the BSD License # which
>> accompanies this distribution. The full text of the license may be found at
>> @@ -25,6 +27,7 @@
>>
>> [Sources]
>> SmmCpuFeaturesLib.c
>> + SmmCommon.h
>> SmmStm.c
>> SmmStm.h
>>
>> diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c
>> b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c
>> index 45015b8..5f7c3db 100644
>> --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c
>> +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c
>> @@ -2,6 +2,8 @@
>> SMM STM support functions
>>
>> Copyright (c) 2015 - 2017, Intel Corporation. All rights reserved.<BR>
>> + Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>
>> +
>> This program and the accompanying materials
>> are licensed and made available under the terms and conditions of the BSD
>> License
>> which accompanies this distribution. The full text of the license may be
>> found at @@ -28,6 +30,8 @@ #include <Protocol/MpService.h>
>>
>> #include "SmmStm.h"
>> +#include "SmmCommon.h"
>> +
>>
>> #define TXT_EVTYPE_BASE 0x400
>> #define TXT_EVTYPE_STM_HASH (TXT_EVTYPE_BASE + 14)
>> @@ -97,6 +101,20 @@ extern volatile UINT8
>> gcStmSmiHandlerTemplate[];
>> extern CONST UINT16 gcStmSmiHandlerSize;
>> extern UINT16 gcStmSmiHandlerOffset;
>> extern BOOLEAN gStmXdSupported;
>> +extern UINT16 gStmGdtSize;
>> +extern UINT16 gStmGdtPtr;
>> +
>> +//
>> +// Constants relating to TXT_PROCESSOR_SMM_DESCRIPTOR //
>> +#define TXT_PSD_GDTPTR 0x48
>> +#define TXT_PSD_GDTSIZE 0x50
>> +
>> +//
>> +// Set default value for PSD offset in SMRAM // from
>> +<Register/StmApi.h> //
>> +UINT16 gStmPsdOffset = TXT_SMM_PSD_OFFSET;
>>
>> //
>> // Variables used by SMI Handler
>> @@ -145,6 +163,19 @@ SmmCpuFeaturesLibStmConstructor (
>> ASSERT_EFI_ERROR (Status);
>>
>> //
>> + // Override PSD offset for AMD
>> + //
>> + if (SmmStandardSignatureIsAuthenticAMD ()) {
>> + gStmPsdOffset = AMD_SMM_PSD_OFFSET; }
>> +
>> + //
>> + // Initialize STM global variables associated with SMI Handler //
>> + gStmGdtSize = gStmPsdOffset + TXT_PSD_GDTSIZE; gStmGdtPtr =
>> + gStmPsdOffset + TXT_PSD_GDTPTR;
>> +
>> + //
>> // Lookup the MP Services Protocol
>> //
>> Status = gBS->LocateProtocol (
>> @@ -276,8 +307,8 @@ SmmCpuFeaturesInstallSmiHandler (
>> UINT32 RegEdx;
>> EFI_PROCESSOR_INFORMATION ProcessorInfo;
>>
>> - CopyMem ((VOID *)((UINTN)SmBase + TXT_SMM_PSD_OFFSET),
>> &gcStmPsd, sizeof (gcStmPsd));
>> - Psd = (TXT_PROCESSOR_SMM_DESCRIPTOR *)(VOID *)((UINTN)SmBase +
>> TXT_SMM_PSD_OFFSET);
>> + CopyMem ((VOID *)((UINTN)SmBase + gStmPsdOffset), &gcStmPsd,
>> sizeof
>> + (gcStmPsd)); Psd = (TXT_PROCESSOR_SMM_DESCRIPTOR *)(VOID
>> + *)((UINTN)SmBase + gStmPsdOffset);
>> Psd->SmmGdtPtr = GdtBase;
>> Psd->SmmGdtSize = (UINT32)GdtSize;
>>
>> @@ -416,7 +447,7 @@ SmmEndOfDxeEventNotify (
>> }
>>
>> for (Index = 0; Index < gSmst->NumberOfCpus; Index++) {
>> - Psd = (TXT_PROCESSOR_SMM_DESCRIPTOR *)((UINTN)gSmst-
>>> CpuSaveState[Index] - SMRAM_SAVE_STATE_MAP_OFFSET +
>> TXT_SMM_PSD_OFFSET);
>> + Psd = (TXT_PROCESSOR_SMM_DESCRIPTOR
>> + *)((UINTN)gSmst->CpuSaveState[Index] - gSmramStateMapOffset +
>> + gStmPsdOffset);
>> DEBUG ((DEBUG_INFO, "Index=%d Psd=%p Rsdp=%p\n", Index, Psd,
>> Rsdp));
>> Psd->AcpiRsdp = (UINT64)(UINTN)Rsdp;
>> }
>> @@ -1266,7 +1297,7 @@ NotifyStmResourceChange (
>> TXT_PROCESSOR_SMM_DESCRIPTOR *Psd;
>>
>> for (Index = 0; Index < gSmst->NumberOfCpus; Index++) {
>> - Psd = (TXT_PROCESSOR_SMM_DESCRIPTOR *)((UINTN)gSmst-
>>> CpuSaveState[Index] - SMRAM_SAVE_STATE_MAP_OFFSET +
>> TXT_SMM_PSD_OFFSET);
>> + Psd = (TXT_PROCESSOR_SMM_DESCRIPTOR
>> + *)((UINTN)gSmst->CpuSaveState[Index] - gSmramStateMapOffset +
>> + gStmPsdOffset);
>> Psd->BiosHwResourceRequirementsPtr = (UINT64)(UINTN)StmResource;
>> }
>> return ;
>> diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.S
>> b/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.S
>> index 1f9f91c..5f3386a 100644
>> --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.S
>> +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.S
>> @@ -1,6 +1,8 @@
>> #------------------------------------------------------------------------------
>> #
>> # Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.<BR>
>> +# Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR> #
>> # This program and the accompanying materials # are licensed and made
>> available under the terms and conditions of the BSD License # which
>> accompanies this distribution. The full text of the license may be found at
>> @@ -27,6 +29,9 @@ ASM_GLOBAL ASM_PFX(gStmSmiStack) ASM_GLOBAL
>> ASM_PFX(gStmSmbase) ASM_GLOBAL ASM_PFX(gStmXdSupported)
>> ASM_GLOBAL ASM_PFX(gStmSmiHandlerIdtr)
>> +ASM_GLOBAL ASM_PFX(gStmPsdOffset)
>> +ASM_GLOBAL ASM_PFX(gStmGdtSize)
>> +ASM_GLOBAL ASM_PFX(gStmGdtPtr)
>>
>> .equ MSR_IA32_MISC_ENABLE, 0x1A0
>> .equ MSR_EFER, 0xc0000080
>> @@ -35,12 +40,13 @@ ASM_GLOBAL ASM_PFX(gStmSmiHandlerIdtr) # #
>> Constants relating to TXT_PROCESSOR_SMM_DESCRIPTOR #
>> -.equ DSC_OFFSET, 0xfb00
>> -.equ DSC_GDTPTR, 0x48
>> -.equ DSC_GDTSIZ, 0x50
>> -.equ DSC_CS, 0x14
>> -.equ DSC_DS, 0x16
>> -.equ DSC_SS, 0x18
>> +# .equ DSC_OFFSET, 0xfb00
>> +# .equ DSC_GDTPTR, 0x48
>> +# .equ DSC_GDTSIZ, 0x50
>> +#
>> +.equ DSC_CS, 0x14
>> +.equ DSC_DS, 0x16
>> +.equ DSC_SS, 0x18
>> .equ DSC_OTHERSEG, 0x1a
>> #
>> # Constants relating to CPU State Save Area @@ -71,12 +77,12 @@
>> _StmSmiEntryPoint:
>> # fix GDT descriptor
>> #
>> .byte 0x2e,0xa1 # mov ax, cs:[offset16]
>> - .word DSC_OFFSET + DSC_GDTSIZ
>> +ASM_PFX(gStmGdtSize): .space 2 # .word DSC_OFFSET + DSC_GDTSIZ
>> .byte 0x48 # dec ax
>> .byte 0x2e
>> movl %eax, (%rdi) # mov cs:[bx], ax
>> .byte 0x66,0x2e,0xa1 # mov eax, cs:[offset16]
>> - .word DSC_OFFSET + DSC_GDTPTR
>> +ASM_PFX(gStmGdtPtr): .space 2 # .word DSC_OFFSET + DSC_GDTPTR
>> .byte 0x2e
>> movw %ax, 2(%rdi)
>> .byte 0x66,0x2e
>> @@ -183,7 +189,11 @@ Base:
>> LongMode: # long mode (64-bit code) starts here
>> movabsq $ASM_PFX(gStmSmiHandlerIdtr), %rax
>> lidt (%rax)
>> - lea (DSC_OFFSET)(%rdi), %ebx
>> +
>> + movl $ASM_PFX(gStmPsdOffset), %ebx # lea (DSC_OFFSET)(%rdi),
>> %ebx
>> + movzxw (%ebx), %rsi
>> + leal (%rdi, %rsi), %ebx
>> +
>> movw DSC_DS(%rbx), %ax
>> movl %eax,%ds
>> movw DSC_OTHERSEG(%rbx), %ax
>> diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.asm
>> b/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.asm
>> index ad51e07..10913df 100644
>> --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.asm
>> +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.asm
>> @@ -1,5 +1,7 @@
>> ;------------------------------------------------------------------------------ ; ;
>> Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.<BR>
>> +; Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR> ;
>> ; This program and the accompanying materials ; are licensed and made
>> available under the terms and conditions of the BSD License ; which
>> accompanies this distribution. The full text of the license may be found at
>> @@ -32,6 +34,10 @@ EXTERNDEF gStmSmiStack:DWORD
>> EXTERNDEF gStmSmbase:DWORD
>> EXTERNDEF gStmXdSupported:BYTE
>> EXTERNDEF gStmSmiHandlerIdtr:FWORD
>> +EXTERNDEF gStmPsdOffset:WORD
>> +EXTERNDEF gStmGdtSize:WORD
>> +EXTERNDEF gStmGdtPtr:WORD
>> +
>>
>> MSR_IA32_MISC_ENABLE EQU 1A0h
>> MSR_EFER EQU 0c0000080h
>> @@ -40,13 +46,14 @@ MSR_EFER_XD EQU 0800h
>> ;
>> ; Constants relating to TXT_PROCESSOR_SMM_DESCRIPTOR ;
>> -DSC_OFFSET EQU 0fb00h
>> -DSC_GDTPTR EQU 48h
>> -DSC_GDTSIZ EQU 50h
>> -DSC_CS EQU 14h
>> -DSC_DS EQU 16h
>> -DSC_SS EQU 18h
>> -DSC_OTHERSEG EQU 1ah
>> +; DSC_OFFSET EQU 0fb00h
>> +; DSC_GDTPTR EQU 48h
>> +; DSC_GDTSIZ EQU 50h
>> +;
>> +DSC_CS EQU 14h
>> +DSC_DS EQU 16h
>> +DSC_SS EQU 18h
>> +DSC_OTHERSEG EQU 1ah
>> ;
>> ; Constants relating to CPU State Save Area ; @@ -74,12 +81,12 @@
>> _StmSmiEntryPoint:
>> DW offset _StmGdtDesc - _StmSmiEntryPoint + 8000h ; bx = GdtDesc
>> offset
>> ; fix GDT descriptor
>> DB 2eh, 0a1h ; mov ax, cs:[offset16]
>> - DW DSC_OFFSET + DSC_GDTSIZ
>> +gStmGdtSize DW ? ; DSC_OFFSET + DSC_GDTSIZ
>> DB 48h ; dec ax
>> DB 2eh
>> mov [rdi], eax ; mov cs:[bx], ax
>> DB 66h, 2eh, 0a1h ; mov eax, cs:[offset16]
>> - DW DSC_OFFSET + DSC_GDTPTR
>> +gStmGdtPtr DW ? ; DSC_OFFSET + DSC_GDTPTR
>> DB 2eh
>> mov [rdi + 2], ax ; mov cs:[bx + 2], eax
>> DB 66h, 2eh
>> @@ -178,7 +185,10 @@ Base:
>> @LongMode: ; long mode (64-bit code) starts here
>> mov rax, offset gStmSmiHandlerIdtr
>> lidt fword ptr [rax]
>> - lea ebx, [rdi + DSC_OFFSET]
>> +
>> + movzx rsi, word ptr [gStmPsdOffset] ; lea ebx, [rdi + DSC_OFFSET]
>> + lea ebx, [rdi + rsi] ;
>> +
>> mov ax, [rbx + DSC_DS]
>> mov ds, eax
>> mov ax, [rbx + DSC_OTHERSEG]
>> diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.nasm
>> b/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.nasm
>> index bcac643..df4c5a2 100644
>> --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.nasm
>> +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.nasm
>> @@ -1,5 +1,7 @@
>> ;------------------------------------------------------------------------------ ; ;
>> Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
>> +; Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR> ;
>> ; This program and the accompanying materials ; are licensed and made
>> available under the terms and conditions of the BSD License ; which
>> accompanies this distribution. The full text of the license may be found at
>> @@ -29,13 +31,14 @@ ; ; Constants relating to
>> TXT_PROCESSOR_SMM_DESCRIPTOR ; -%define DSC_OFFSET 0xfb00 -
>> %define DSC_GDTPTR 0x48 -%define DSC_GDTSIZ 0x50 -%define DSC_CS
>> 0x14 -%define DSC_DS 0x16 -%define DSC_SS 0x18 -%define DSC_OTHERSEG
>> 0x1a
>> +; %define DSC_OFFSET 0xfb00
>> +; %define DSC_GDTPTR 0x48
>> +; %define DSC_GDTSIZ 0x50
>> +;
>> +%define DSC_CS 0x14
>> +%define DSC_DS 0x16
>> +%define DSC_SS 0x18
>> +%define DSC_OTHERSEG 0x1a
>> ;
>> ; Constants relating to CPU State Save Area ; @@ -44,9 +47,9 @@
>>
>> %define PROTECT_MODE_CS 0x8
>> %define PROTECT_MODE_DS 0x20
>> -%define LONG_MODE_CS 0x38
>> -%define TSS_SEGMENT 0x40
>> -%define GDT_SIZE 0x50
>> +%define LONG_MODE_CS 0x38
>> +%define TSS_SEGMENT 0x40
>> +%define GDT_SIZE 0x50
>>
>> extern ASM_PFX(SmiRendezvous)
>> extern ASM_PFX(gStmSmiHandlerIdtr)
>> @@ -61,6 +64,10 @@ global ASM_PFX(gcStmSmiHandlerTemplate) global
>> ASM_PFX(gcStmSmiHandlerSize) global ASM_PFX(gcStmSmiHandlerOffset)
>>
>> +extern ASM_PFX(gStmPsdOffset)
>> +global ASM_PFX(gStmGdtSize)
>> +global ASM_PFX(gStmGdtPtr)
>> +
>> ASM_PFX(gStmSmbase) EQU StmSmbasePatch - 4
>> ASM_PFX(gStmSmiStack) EQU StmSmiStackPatch - 4
>> ASM_PFX(gStmSmiCr3) EQU StmSmiCr3Patch - 4
>> @@ -73,10 +80,18 @@ BITS 16
>> ASM_PFX(gcStmSmiHandlerTemplate):
>> _StmSmiEntryPoint:
>> mov bx, _StmGdtDesc - _StmSmiEntryPoint + 0x8000
>> - mov ax,[cs:DSC_OFFSET + DSC_GDTSIZ]
>> +
>> + mov eax, ASM_PFX(gStmGdtSize) ; mov ax, [cs:DSC_OFFSET +
>> DSC_GDTSIZ]
>> + mov si, [cs:eax] ;
>> + mov ax, [cs:si] ;
>> +
>> dec ax
>> mov [cs:bx], ax
>> - mov eax, [cs:DSC_OFFSET + DSC_GDTPTR]
>> +
>> + mov eax, ASM_PFX(gStmGdtPtr) ; mov eax, [cs:DSC_OFFSET +
>> DSC_GDTPTR]
>> + mov si, [cs:eax] ;
>> + mov eax, [cs:si] ;
>> +
>> mov [cs:bx + 2], eax
>> o32 lgdt [cs:bx] ; lgdt fword ptr cs:[bx]
>> mov ax, PROTECT_MODE_CS
>> @@ -166,7 +181,10 @@ Base:
>> @LongMode: ; long mode (64-bit code) starts here
>> mov rax, ASM_PFX(gStmSmiHandlerIdtr)
>> lidt [rax]
>> - lea ebx, [rdi + DSC_OFFSET]
>> +
>> + movzx rsi, word [ASM_PFX(gStmPsdOffset)] ; lea ebx, [rdi +
>> DSC_OFFSET]
>> + lea ebx, [rdi + rsi] ;
>> +
>> mov ax, [rbx + DSC_DS]
>> mov ds, eax
>> mov ax, [rbx + DSC_OTHERSEG]
>> @@ -262,5 +280,8 @@ _StmSmiHandler:
>> ; STM init finish
>> jmp CommonHandler
>>
>> +ASM_PFX(gStmGdtSize) : RESW 1
>> +ASM_PFX(gStmGdtPtr) : RESW 1
>> +
>> ASM_PFX(gcStmSmiHandlerSize) : DW $ - _StmSmiEntryPoint
>> ASM_PFX(gcStmSmiHandlerOffset) : DW _StmSmiHandler -
>> _StmSmiEntryPoint
>> --
>> 2.7.4
>
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH v5 1/2] UefiCpuPkg/SmmCpuFeaturesLib: Use global variables to replace macros
2017-10-17 14:23 ` Laszlo Ersek
@ 2017-10-17 14:37 ` Paolo Bonzini
2017-10-17 14:50 ` Duran, Leo
0 siblings, 1 reply; 30+ messages in thread
From: Paolo Bonzini @ 2017-10-17 14:37 UTC (permalink / raw)
To: Laszlo Ersek, Duran, Leo, edk2-devel@lists.01.org, Jiewen Yao
Cc: Ruiyu Ni, Michael D Kinney, Jordan Justen, Liming Gao
On 17/10/2017 16:23, Laszlo Ersek wrote:
>> For the SRAM_SAVE_STATE_MAP_OFFSET:
>> I propose returning the value by a function in SmmCpuFeaturesLib...
> This has crossed my mind (superficially :) ), and I support your idea.
>
> Paolo, can you please comment?
I don't see a reason why AMD must use a state save map that only covers
the last 512 bytes rather than the whole 1024, even if the first half is
unused...
Paolo
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH v5 1/2] UefiCpuPkg/SmmCpuFeaturesLib: Use global variables to replace macros
2017-10-17 14:37 ` Paolo Bonzini
@ 2017-10-17 14:50 ` Duran, Leo
2017-10-17 15:16 ` Paolo Bonzini
0 siblings, 1 reply; 30+ messages in thread
From: Duran, Leo @ 2017-10-17 14:50 UTC (permalink / raw)
To: 'Paolo Bonzini', Laszlo Ersek, edk2-devel@lists.01.org,
Jiewen Yao
Cc: Ruiyu Ni, Michael D Kinney, Jordan Justen, Liming Gao
> -----Original Message-----
> From: Paolo Bonzini [mailto:pbonzini@redhat.com]
> Sent: Tuesday, October 17, 2017 9:37 AM
> To: Laszlo Ersek <lersek@redhat.com>; Duran, Leo <leo.duran@amd.com>;
> edk2-devel@lists.01.org; Jiewen Yao <jiewen.yao@intel.com>
> Cc: Ruiyu Ni <ruiyu.ni@intel.com>; Michael D Kinney
> <michael.d.kinney@intel.com>; Jordan Justen <jordan.l.justen@intel.com>;
> Liming Gao <liming.gao@intel.com>
> Subject: Re: [PATCH v5 1/2] UefiCpuPkg/SmmCpuFeaturesLib: Use global
> variables to replace macros
>
> On 17/10/2017 16:23, Laszlo Ersek wrote:
> >> For the SRAM_SAVE_STATE_MAP_OFFSET:
> >> I propose returning the value by a function in SmmCpuFeaturesLib...
> > This has crossed my mind (superficially :) ), and I support your idea.
> >
> > Paolo, can you please comment?
>
> I don't see a reason why AMD must use a state save map that only covers the
> last 512 bytes rather than the whole 1024, even if the first half is unused...
>
> Paolo
To me,
- This proposed library function seems appropriate in the context of CPU features (i..e, this is not a hack)
- I'd argue having to save & restore 512 "unused" bytes per SMI is significant overheard that can be avoided.
- The proposed change is not intrusive not does it add significant amount of code.
Is there a technical reason for a "thumbs down"?
Thanks,
Leo
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH v5 1/2] UefiCpuPkg/SmmCpuFeaturesLib: Use global variables to replace macros
2017-10-17 14:19 ` Duran, Leo
2017-10-17 14:23 ` Laszlo Ersek
@ 2017-10-17 14:50 ` Yao, Jiewen
2017-10-17 15:14 ` Laszlo Ersek
2017-10-17 16:30 ` Duran, Leo
1 sibling, 2 replies; 30+ messages in thread
From: Yao, Jiewen @ 2017-10-17 14:50 UTC (permalink / raw)
To: Duran, Leo
Cc: edk2-devel@lists.01.org, Laszlo Ersek, Paolo Bonzini, Ni, Ruiyu,
Kinney, Michael D, Justen, Jordan L, Gao, Liming
I think it is unnecessary. All intel CPU is using same offset. All amd CPU is using same offset. It can be identified easily by code.
Adding a new API now is also an incompatible change because that requires all existing featurelib change to add a new API. We have lots of close source platform using its own featurelib.
May I know what problem we are trying to resolve by adding a new API?
thank you!
Yao, Jiewen
> 在 2017年10月17日，下午10:20，Duran, Leo <leo.duran@amd.com> 写道：
>
> Yao, Lazlo, et al,
>
> For the SRAM_SAVE_STATE_MAP_OFFSET:
> I propose returning the value by a function in SmmCpuFeaturesLib... Here's the rationale:
> - The value is fixed per CPU architecture, so this qualifies as a CPU feature.
> - The logic for CPU architecture detection would be in one place (e.g., PiSmmCpuDxeSmm would call the library function)
> - The OVMF and Quark instances of the library could just return the current (default) value, so no compatibility issues.
>
> if you agree with this is an acceptable solution, I will submit a revised patch-set to address just the SRAM_SAVE_STATE_MAP_OFFSET.
> (BTW, I'm re-evaluating the changes submitted for the PSD offset, with the goal of just using the default value and dropping those changes)
>
> Thanks,
> Leo.
>
>> -----Original Message-----
>> From: Duran, Leo
>> Sent: Wednesday, October 11, 2017 2:46 PM
>> To: edk2-devel@lists.01.org
>> Cc: Duran, Leo <leo.duran@amd.com>; Jiewen Yao
>> <jiewen.yao@intel.com>; Ruiyu Ni <ruiyu.ni@intel.com>; Michael D Kinney
>> <michael.d.kinney@intel.com>; Jordan Justen <jordan.l.justen@intel.com>;
>> Liming Gao <liming.gao@intel.com>
>> Subject: [PATCH v5 1/2] UefiCpuPkg/SmmCpuFeaturesLib: Use global
>> variables to replace macros
>>
>> Set global variables on Constructor function based on CPUID checks.
>> The variables replace Intel macros to allow support on AMD x86 systems.
>>
>> Specifically, the replaced macros are:
>> 1) SRAM_SAVE_STATE_MAP_OFFSET
>> 2) TXT_SMM_PSD_OFFSET
>>
>> Cc: Jiewen Yao <jiewen.yao@intel.com>
>> Cc: Ruiyu Ni <ruiyu.ni@intel.com>
>> Cc: Michael D Kinney <michael.d.kinney@intel.com>
>> Cc: Jordan Justen <jordan.l.justen@intel.com>
>> Cc: Liming Gao <liming.gao@intel.com>
>> Contributed-under: TianoCore Contribution Agreement 1.1
>> Signed-off-by: Leo Duran <leo.duran@amd.com>
>> ---
>> .../Library/SmmCpuFeaturesLib/Ia32/SmiEntry.S | 28 ++++++----
>> .../Library/SmmCpuFeaturesLib/Ia32/SmiEntry.asm | 29 +++++++----
>> .../Library/SmmCpuFeaturesLib/Ia32/SmiEntry.nasm | 43 ++++++++++++---
>> -
>> UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCommon.h | 48
>> ++++++++++++++++++
>> .../Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c | 59
>> ++++++++++++++++++----
>> .../SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf | 3 ++
>> .../SmmCpuFeaturesLib/SmmCpuFeaturesLibStm.inf | 3 ++
>> UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c | 39
>> ++++++++++++--
>> .../Library/SmmCpuFeaturesLib/X64/SmiEntry.S | 28 ++++++----
>> .../Library/SmmCpuFeaturesLib/X64/SmiEntry.asm | 30 +++++++----
>> .../Library/SmmCpuFeaturesLib/X64/SmiEntry.nasm | 47 ++++++++++++---
>> --
>> 11 files changed, 282 insertions(+), 75 deletions(-) create mode 100644
>> UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCommon.h
>>
>> diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.S
>> b/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.S
>> index 4c0f8c8..c7b49d7 100644
>> --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.S
>> +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.S
>> @@ -1,6 +1,8 @@
>> #------------------------------------------------------------------------------
>> #
>> # Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.<BR>
>> +# Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR> #
>> # This program and the accompanying materials # are licensed and made
>> available under the terms and conditions of the BSD License # which
>> accompanies this distribution. The full text of the license may be found at
>> @@ -28,6 +30,9 @@ ASM_GLOBAL ASM_PFX(gStmSmbase) ASM_GLOBAL
>> ASM_PFX(gStmXdSupported) ASM_GLOBAL ASM_PFX(FeaturePcdGet
>> (PcdCpuSmmStackGuard)) ASM_GLOBAL ASM_PFX(gStmSmiHandlerIdtr)
>> +ASM_GLOBAL ASM_PFX(gStmPsdOffset)
>> +ASM_GLOBAL ASM_PFX(gStmGdtSize)
>> +ASM_GLOBAL ASM_PFX(gStmGdtPtr)
>>
>> .equ MSR_IA32_MISC_ENABLE, 0x1A0
>> .equ MSR_EFER, 0xc0000080
>> @@ -36,12 +41,13 @@ ASM_GLOBAL ASM_PFX(gStmSmiHandlerIdtr) # #
>> Constants relating to TXT_PROCESSOR_SMM_DESCRIPTOR #
>> -.equ DSC_OFFSET, 0xfb00
>> -.equ DSC_GDTPTR, 0x48
>> -.equ DSC_GDTSIZ, 0x50
>> -.equ DSC_CS, 0x14
>> -.equ DSC_DS, 0x16
>> -.equ DSC_SS, 0x18
>> +# .equ DSC_OFFSET, 0xfb00
>> +# .equ DSC_GDTPTR, 0x48
>> +# .equ DSC_GDTSIZ, 0x50
>> +#
>> +.equ DSC_CS, 0x14
>> +.equ DSC_DS, 0x16
>> +.equ DSC_SS, 0x18
>> .equ DSC_OTHERSEG, 0x1A
>>
>> .equ PROTECT_MODE_CS, 0x08
>> @@ -55,11 +61,11 @@ _StmSmiEntryPoint:
>> .byte 0xbb # mov bx, imm16
>> .word _StmGdtDesc - _StmSmiEntryPoint + 0x8000
>> .byte 0x2e,0xa1 # mov ax, cs:[offset16]
>> - .word DSC_OFFSET + DSC_GDTSIZ
>> +ASM_PFX(gStmGdtSize): .space 2 # .word DSC_OFFSET + DSC_GDTSIZ
>> decl %eax
>> movl %eax, %cs:(%edi) # mov cs:[bx], ax
>> .byte 0x66,0x2e,0xa1 # mov eax, cs:[offset16]
>> - .word DSC_OFFSET + DSC_GDTPTR
>> +ASM_PFX(gStmGdtPtr): .space 2 # .word DSC_OFFSET + DSC_GDTPTR
>> movw %ax, %cs:2(%edi)
>> movw %ax, %bp # ebp = GDT base
>> .byte 0x66
>> @@ -167,7 +173,11 @@ XdDone:
>> movl %cr0, %ebx
>> orl $0x080010023, %ebx # enable paging + WP + NE + MP + PE
>> movl %ebx, %cr0
>> - leal DSC_OFFSET(%edi),%ebx
>> +
>> + movl $ASM_PFX(gStmPsdOffset), %ebx # leal DSC_OFFSET(%edi),
>> %ebx
>> + movzxw (%ebx), %esi
>> + leal (%edi, %esi), %ebx
>> +
>> movw DSC_DS(%ebx),%ax
>> movl %eax, %ds
>> movw DSC_OTHERSEG(%ebx),%ax
>> diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.asm
>> b/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.asm
>> index 91dc1eb..4dbe276 100644
>> --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.asm
>> +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.asm
>> @@ -1,5 +1,7 @@
>> ;------------------------------------------------------------------------------ ; ;
>> Copyright (c) 2009 - 2017, Intel Corporation. All rights reserved.<BR>
>> +; Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR> ;
>> ; This program and the accompanying materials ; are licensed and made
>> available under the terms and conditions of the BSD License ; which
>> accompanies this distribution. The full text of the license may be found at
>> @@ -29,13 +31,14 @@ MSR_EFER_XD EQU 0800h
>> ;
>> ; Constants relating to TXT_PROCESSOR_SMM_DESCRIPTOR ;
>> -DSC_OFFSET EQU 0fb00h
>> -DSC_GDTPTR EQU 48h
>> -DSC_GDTSIZ EQU 50h
>> -DSC_CS EQU 14h
>> -DSC_DS EQU 16h
>> -DSC_SS EQU 18h
>> -DSC_OTHERSEG EQU 1Ah
>> +; DSC_OFFSET EQU 0fb00h
>> +; DSC_GDTPTR EQU 48h
>> +; DSC_GDTSIZ EQU 50h
>> +;
>> +DSC_CS EQU 14h
>> +DSC_DS EQU 16h
>> +DSC_SS EQU 18h
>> +DSC_OTHERSEG EQU 1Ah
>>
>> PROTECT_MODE_CS EQU 08h
>> PROTECT_MODE_DS EQU 20h
>> @@ -54,6 +57,9 @@ EXTERNDEF gStmSmbase:DWORD
>> EXTERNDEF gStmXdSupported:BYTE
>> EXTERNDEF FeaturePcdGet (PcdCpuSmmStackGuard):BYTE
>> EXTERNDEF gStmSmiHandlerIdtr:FWORD
>> +EXTERNDEF gStmPsdOffset:WORD
>> +EXTERNDEF gStmGdtSize:WORD
>> +EXTERNDEF gStmGdtPtr:WORD
>>
>> .code
>>
>> @@ -63,11 +69,11 @@ _StmSmiEntryPoint:
>> DB 0bbh ; mov bx, imm16
>> DW offset _StmGdtDesc - _StmSmiEntryPoint + 8000h
>> DB 2eh, 0a1h ; mov ax, cs:[offset16]
>> - DW DSC_OFFSET + DSC_GDTSIZ
>> +gStmGdtSize DW ? ; DSC_OFFSET + DSC_GDTSIZ
>> dec eax
>> mov cs:[edi], eax ; mov cs:[bx], ax
>> DB 66h, 2eh, 0a1h ; mov eax, cs:[offset16]
>> - DW DSC_OFFSET + DSC_GDTPTR
>> +gStmGdtPtr DW ? ; DSC_OFFSET + DSC_GDTPTR
>> mov cs:[edi + 2], ax ; mov cs:[bx + 2], eax
>> mov bp, ax ; ebp = GDT base
>> DB 66h
>> @@ -174,7 +180,10 @@ gStmXdSupported DB 1
>> mov ebx, cr0
>> or ebx, 080010023h ; enable paging + WP + NE + MP + PE
>> mov cr0, ebx
>> - lea ebx, [edi + DSC_OFFSET]
>> +
>> + movzx esi, word ptr [gStmPsdOffset] ; lea ebx, [edi + DSC_OFFSET]
>> + lea ebx, [edi + esi] ;
>> +
>> mov ax, [ebx + DSC_DS]
>> mov ds, eax
>> mov ax, [ebx + DSC_OTHERSEG]
>> diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.nasm
>> b/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.nasm
>> index 00c0f067..023923a 100644
>> --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.nasm
>> +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.nasm
>> @@ -1,5 +1,7 @@
>> ;------------------------------------------------------------------------------ ; ;
>> Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
>> +; Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR> ;
>> ; This program and the accompanying materials ; are licensed and made
>> available under the terms and conditions of the BSD License ; which
>> accompanies this distribution. The full text of the license may be found at
>> @@ -25,17 +27,18 @@ ; ; Constants relating to
>> TXT_PROCESSOR_SMM_DESCRIPTOR ; -%define DSC_OFFSET 0xfb00 -
>> %define DSC_GDTPTR 0x48 -%define DSC_GDTSIZ 0x50 -%define DSC_CS
>> 0x14 -%define DSC_DS 0x16 -%define DSC_SS 0x18 -%define DSC_OTHERSEG
>> 0x1a
>> +; %define DSC_OFFSET 0xfb00
>> +; %define DSC_GDTPTR 0x48
>> +; %define DSC_GDTSIZ 0x50
>> +;
>> +%define DSC_CS 0x14
>> +%define DSC_DS 0x16
>> +%define DSC_SS 0x18
>> +%define DSC_OTHERSEG 0x1a
>>
>> %define PROTECT_MODE_CS 0x8
>> %define PROTECT_MODE_DS 0x20
>> -%define TSS_SEGMENT 0x40
>> +%define TSS_SEGMENT 0x40
>>
>> extern ASM_PFX(SmiRendezvous)
>> extern ASM_PFX(FeaturePcdGet (PcdCpuSmmStackGuard)) @@ -51,6
>> +54,10 @@ global ASM_PFX(gStmSmbase) global
>> ASM_PFX(gStmXdSupported) extern ASM_PFX(gStmSmiHandlerIdtr)
>>
>> +extern ASM_PFX(gStmPsdOffset)
>> +global ASM_PFX(gStmGdtSize)
>> +global ASM_PFX(gStmGdtPtr)
>> +
>> ASM_PFX(gStmSmiCr3) EQU StmSmiCr3Patch - 4
>> ASM_PFX(gStmSmiStack) EQU StmSmiStackPatch - 4
>> ASM_PFX(gStmSmbase) EQU StmSmbasePatch - 4
>> @@ -62,10 +69,18 @@ BITS 16
>> ASM_PFX(gcStmSmiHandlerTemplate):
>> _StmSmiEntryPoint:
>> mov bx, _StmGdtDesc - _StmSmiEntryPoint + 0x8000
>> - mov ax,[cs:DSC_OFFSET + DSC_GDTSIZ]
>> +
>> + mov eax, ASM_PFX(gStmGdtSize) ; mov ax, [cs:DSC_OFFSET +
>> DSC_GDTSIZ]
>> + mov si, [cs:eax] ;
>> + mov ax, [cs:si] ;
>> +
>> dec ax
>> mov [cs:bx], ax
>> - mov eax, [cs:DSC_OFFSET + DSC_GDTPTR]
>> +
>> + mov eax, ASM_PFX(gStmGdtPtr) ; mov eax, [cs:DSC_OFFSET +
>> DSC_GDTPTR]
>> + mov si, [cs:eax] ;
>> + mov eax, [cs:si] ;
>> +
>> mov [cs:bx + 2], eax
>> mov ebp, eax ; ebp = GDT base
>> o32 lgdt [cs:bx] ; lgdt fword ptr cs:[bx]
>> @@ -166,7 +181,10 @@ StmXdSupportedPatch:
>> mov ebx, cr0
>> or ebx, 0x80010023 ; enable paging + WP + NE + MP + PE
>> mov cr0, ebx
>> - lea ebx, [edi + DSC_OFFSET]
>> +
>> + movzx esi, word [ASM_PFX(gStmPsdOffset)] ; lea ebx, [edi +
>> DSC_OFFSET]
>> + lea ebx, [edi + esi] ;
>> +
>> mov ax, [ebx + DSC_DS]
>> mov ds, eax
>> mov ax, [ebx + DSC_OTHERSEG]
>> @@ -271,5 +289,8 @@ _StmSmiHandler:
>> ; STM init finish
>> jmp CommonHandler
>>
>> +ASM_PFX(gStmGdtSize) : RESW 1
>> +ASM_PFX(gStmGdtPtr) : RESW 1
>> +
>> ASM_PFX(gcStmSmiHandlerSize) : DW $ - _StmSmiEntryPoint
>> ASM_PFX(gcStmSmiHandlerOffset) : DW _StmSmiHandler -
>> _StmSmiEntryPoint
>> diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCommon.h
>> b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCommon.h
>> new file mode 100644
>> index 0000000..78b3a5b
>> --- /dev/null
>> +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCommon.h
>> @@ -0,0 +1,48 @@
>> +/** @file
>> + Common declarations
>> +
>> + Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>
>> +
>> + This program and the accompanying materials are licensed and made
>> + available under the terms and conditions of the BSD License which
>> + accompanies this distribution. The full text of the license may be
>> + found at http://opensource.org/licenses/bsd-license.php.
>> +
>> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
>> BASIS,
>> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
>> EXPRESS OR IMPLIED.
>> +
>> +**/
>> +
>> +#ifndef _SMM_COMMON_H_
>> +#define _SMM_COMMON_H_
>> +
>> +#include <Register/Amd/Cpuid.h>
>> +
>> +//
>> +// Definitions for AMD systems are based on contents of the // AMD64
>> +Architecture Programmer's Manual // Volume 2: System Programming,
>> +Section 10 System-Management Mode // #define
>> +AMD_SMRAM_SAVE_STATE_MAP_OFFSET 0xfe00
>> +#define AMD_SMM_PSD_OFFSET 0xfc00
>> +
>> +//
>> +// External global variables for SMRAM offsets // extern UINT16
>> +gSmramStateMapOffset; extern UINT16 gSmmPsdOffset;
>> +
>> +
>> +/**
>> + Determine if the standard CPU signature is "AuthenticAMD".
>> +
>> + @retval TRUE The CPU signature matches.
>> + @retval FALSE The CPU signature does not match.
>> +
>> +**/
>> +BOOLEAN
>> +SmmStandardSignatureIsAuthenticAMD (
>> + VOID
>> + );
>> +
>> +#endif
>> diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c
>> b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c
>> index 2d2bc6d..1c12095 100644
>> --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c
>> +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c
>> @@ -1,14 +1,16 @@
>> /** @file
>> -The CPU specific programming for PiSmmCpuDxeSmm module.
>> + The CPU specific programming for PiSmmCpuDxeSmm module.
>>
>> -Copyright (c) 2010 - 2016, Intel Corporation. All rights reserved.<BR> -This
>> program and the accompanying materials -are licensed and made available
>> under the terms and conditions of the BSD License -which accompanies this
>> distribution. The full text of the license may be found at -
>> http://opensource.org/licenses/bsd-license.php
>> + Copyright (c) 2010 - 2016, Intel Corporation. All rights
>> + reserved.<BR> Copyright (c) 2017, AMD Incorporated. All rights
>> + reserved.<BR>
>>
>> -THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
>> BASIS, -WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
>> EXPRESS OR IMPLIED.
>> + This program and the accompanying materials are licensed and made
>> + available under the terms and conditions of the BSD License which
>> + accompanies this distribution. The full text of the license may be
>> + found at http://opensource.org/licenses/bsd-license.php
>> +
>> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
>> BASIS,
>> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
>> EXPRESS OR IMPLIED.
>>
>> **/
>>
>> @@ -22,6 +24,8 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY
>> KIND, EITHER EXPRESS OR IMPLIED.
>> #include <Register/Cpuid.h>
>> #include <Register/SmramSaveStateMap.h>
>>
>> +#include "SmmCommon.h"
>> +
>> //
>> // Machine Specific Registers (MSRs)
>> //
>> @@ -41,6 +45,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY
>> KIND, EITHER EXPRESS OR IMPLIED.
>> #define SMM_FEATURES_LIB_IA32_MCA_CAP 0x17D
>> #define SMM_CODE_ACCESS_CHK_BIT BIT58
>>
>> +
>> /**
>> Internal worker function that is called to complete CPU initialization at the
>> end of SmmCpuFeaturesInitializeProcessor().
>> @@ -77,6 +82,13 @@ BOOLEAN mNeedConfigureMtrrs = TRUE; //
>> BOOLEAN *mSmrrEnabled;
>>
>> +//
>> +// Set default value for SMRAM offset
>> +// from <Register/SmramSaveStateMap.h> //
>> +UINT16 gSmramStateMapOffset = SMRAM_SAVE_STATE_MAP_OFFSET;
>> +
>> +
>> /**
>> The constructor function
>>
>> @@ -99,6 +111,13 @@ SmmCpuFeaturesLibConstructor (
>> UINTN ModelId;
>>
>> //
>> + // Override SMRAM offset for AMD
>> + //
>> + if (SmmStandardSignatureIsAuthenticAMD ()) {
>> + gSmramStateMapOffset = AMD_SMRAM_SAVE_STATE_MAP_OFFSET; }
>> +
>> + //
>> // Retrieve CPU Family and Model
>> //
>> AsmCpuid (CPUID_VERSION_INFO, &RegEax, NULL, NULL, &RegEdx); @@ -
>> 224,7 +243,7 @@ SmmCpuFeaturesInitializeProcessor (
>> //
>> // Configure SMBASE.
>> //
>> - CpuState = (SMRAM_SAVE_STATE_MAP
>> *)(UINTN)(SMM_DEFAULT_SMBASE +
>> SMRAM_SAVE_STATE_MAP_OFFSET);
>> + CpuState = (SMRAM_SAVE_STATE_MAP
>> *)(UINTN)(SMM_DEFAULT_SMBASE +
>> + gSmramStateMapOffset);
>> CpuState->x86.SMBASE = (UINT32)CpuHotPlugData->SmBase[CpuIndex];
>>
>> //
>> @@ -630,3 +649,25 @@ SmmCpuFeaturesAllocatePageTableMemory (
>> return NULL;
>> }
>>
>> +
>> +/**
>> + Determine if the standard CPU signature is "AuthenticAMD".
>> +
>> + @retval TRUE The CPU signature matches.
>> + @retval FALSE The CPU signature does not match.
>> +
>> +**/
>> +BOOLEAN
>> +SmmStandardSignatureIsAuthenticAMD (
>> + VOID
>> + )
>> +{
>> + UINT32 RegEbx;
>> + UINT32 RegEcx;
>> + UINT32 RegEdx;
>> +
>> + AsmCpuid (CPUID_SIGNATURE, NULL, &RegEbx, &RegEcx, &RegEdx);
>> + return (RegEbx == CPUID_SIGNATURE_AUTHENTIC_AMD_EBX &&
>> + RegEcx == CPUID_SIGNATURE_AUTHENTIC_AMD_ECX &&
>> + RegEdx == CPUID_SIGNATURE_AUTHENTIC_AMD_EDX);
>> +}
>> diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf
>> b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf
>> index 77908b0..6a39d4b 100644
>> --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf
>> +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf
>> @@ -2,6 +2,8 @@
>> # The CPU specific programming for PiSmmCpuDxeSmm module.
>> #
>> # Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.<BR>
>> +# Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR> #
>> # This program and the accompanying materials # are licensed and made
>> available under the terms and conditions of the BSD License # which
>> accompanies this distribution. The full text of the license may be found at
>> @@ -24,6 +26,7 @@
>>
>> [Sources]
>> SmmCpuFeaturesLib.c
>> + SmmCommon.h
>> SmmCpuFeaturesLibNoStm.c
>>
>> [Packages]
>> diff --git
>> a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibStm.inf
>> b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibStm.inf
>> index db8dcdc..a76bed6 100644
>> --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibStm.inf
>> +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibStm.inf
>> @@ -3,6 +3,8 @@
>> # is included.
>> #
>> # Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.<BR>
>> +# Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR> #
>> # This program and the accompanying materials # are licensed and made
>> available under the terms and conditions of the BSD License # which
>> accompanies this distribution. The full text of the license may be found at
>> @@ -25,6 +27,7 @@
>>
>> [Sources]
>> SmmCpuFeaturesLib.c
>> + SmmCommon.h
>> SmmStm.c
>> SmmStm.h
>>
>> diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c
>> b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c
>> index 45015b8..5f7c3db 100644
>> --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c
>> +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c
>> @@ -2,6 +2,8 @@
>> SMM STM support functions
>>
>> Copyright (c) 2015 - 2017, Intel Corporation. All rights reserved.<BR>
>> + Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>
>> +
>> This program and the accompanying materials
>> are licensed and made available under the terms and conditions of the BSD
>> License
>> which accompanies this distribution. The full text of the license may be
>> found at @@ -28,6 +30,8 @@ #include <Protocol/MpService.h>
>>
>> #include "SmmStm.h"
>> +#include "SmmCommon.h"
>> +
>>
>> #define TXT_EVTYPE_BASE 0x400
>> #define TXT_EVTYPE_STM_HASH (TXT_EVTYPE_BASE + 14)
>> @@ -97,6 +101,20 @@ extern volatile UINT8
>> gcStmSmiHandlerTemplate[];
>> extern CONST UINT16 gcStmSmiHandlerSize;
>> extern UINT16 gcStmSmiHandlerOffset;
>> extern BOOLEAN gStmXdSupported;
>> +extern UINT16 gStmGdtSize;
>> +extern UINT16 gStmGdtPtr;
>> +
>> +//
>> +// Constants relating to TXT_PROCESSOR_SMM_DESCRIPTOR //
>> +#define TXT_PSD_GDTPTR 0x48
>> +#define TXT_PSD_GDTSIZE 0x50
>> +
>> +//
>> +// Set default value for PSD offset in SMRAM // from
>> +<Register/StmApi.h> //
>> +UINT16 gStmPsdOffset = TXT_SMM_PSD_OFFSET;
>>
>> //
>> // Variables used by SMI Handler
>> @@ -145,6 +163,19 @@ SmmCpuFeaturesLibStmConstructor (
>> ASSERT_EFI_ERROR (Status);
>>
>> //
>> + // Override PSD offset for AMD
>> + //
>> + if (SmmStandardSignatureIsAuthenticAMD ()) {
>> + gStmPsdOffset = AMD_SMM_PSD_OFFSET; }
>> +
>> + //
>> + // Initialize STM global variables associated with SMI Handler //
>> + gStmGdtSize = gStmPsdOffset + TXT_PSD_GDTSIZE; gStmGdtPtr =
>> + gStmPsdOffset + TXT_PSD_GDTPTR;
>> +
>> + //
>> // Lookup the MP Services Protocol
>> //
>> Status = gBS->LocateProtocol (
>> @@ -276,8 +307,8 @@ SmmCpuFeaturesInstallSmiHandler (
>> UINT32 RegEdx;
>> EFI_PROCESSOR_INFORMATION ProcessorInfo;
>>
>> - CopyMem ((VOID *)((UINTN)SmBase + TXT_SMM_PSD_OFFSET),
>> &gcStmPsd, sizeof (gcStmPsd));
>> - Psd = (TXT_PROCESSOR_SMM_DESCRIPTOR *)(VOID *)((UINTN)SmBase +
>> TXT_SMM_PSD_OFFSET);
>> + CopyMem ((VOID *)((UINTN)SmBase + gStmPsdOffset), &gcStmPsd,
>> sizeof
>> + (gcStmPsd)); Psd = (TXT_PROCESSOR_SMM_DESCRIPTOR *)(VOID
>> + *)((UINTN)SmBase + gStmPsdOffset);
>> Psd->SmmGdtPtr = GdtBase;
>> Psd->SmmGdtSize = (UINT32)GdtSize;
>>
>> @@ -416,7 +447,7 @@ SmmEndOfDxeEventNotify (
>> }
>>
>> for (Index = 0; Index < gSmst->NumberOfCpus; Index++) {
>> - Psd = (TXT_PROCESSOR_SMM_DESCRIPTOR *)((UINTN)gSmst-
>>> CpuSaveState[Index] - SMRAM_SAVE_STATE_MAP_OFFSET +
>> TXT_SMM_PSD_OFFSET);
>> + Psd = (TXT_PROCESSOR_SMM_DESCRIPTOR
>> + *)((UINTN)gSmst->CpuSaveState[Index] - gSmramStateMapOffset +
>> + gStmPsdOffset);
>> DEBUG ((DEBUG_INFO, "Index=%d Psd=%p Rsdp=%p\n", Index, Psd,
>> Rsdp));
>> Psd->AcpiRsdp = (UINT64)(UINTN)Rsdp;
>> }
>> @@ -1266,7 +1297,7 @@ NotifyStmResourceChange (
>> TXT_PROCESSOR_SMM_DESCRIPTOR *Psd;
>>
>> for (Index = 0; Index < gSmst->NumberOfCpus; Index++) {
>> - Psd = (TXT_PROCESSOR_SMM_DESCRIPTOR *)((UINTN)gSmst-
>>> CpuSaveState[Index] - SMRAM_SAVE_STATE_MAP_OFFSET +
>> TXT_SMM_PSD_OFFSET);
>> + Psd = (TXT_PROCESSOR_SMM_DESCRIPTOR
>> + *)((UINTN)gSmst->CpuSaveState[Index] - gSmramStateMapOffset +
>> + gStmPsdOffset);
>> Psd->BiosHwResourceRequirementsPtr = (UINT64)(UINTN)StmResource;
>> }
>> return ;
>> diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.S
>> b/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.S
>> index 1f9f91c..5f3386a 100644
>> --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.S
>> +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.S
>> @@ -1,6 +1,8 @@
>> #------------------------------------------------------------------------------
>> #
>> # Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.<BR>
>> +# Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR> #
>> # This program and the accompanying materials # are licensed and made
>> available under the terms and conditions of the BSD License # which
>> accompanies this distribution. The full text of the license may be found at
>> @@ -27,6 +29,9 @@ ASM_GLOBAL ASM_PFX(gStmSmiStack) ASM_GLOBAL
>> ASM_PFX(gStmSmbase) ASM_GLOBAL ASM_PFX(gStmXdSupported)
>> ASM_GLOBAL ASM_PFX(gStmSmiHandlerIdtr)
>> +ASM_GLOBAL ASM_PFX(gStmPsdOffset)
>> +ASM_GLOBAL ASM_PFX(gStmGdtSize)
>> +ASM_GLOBAL ASM_PFX(gStmGdtPtr)
>>
>> .equ MSR_IA32_MISC_ENABLE, 0x1A0
>> .equ MSR_EFER, 0xc0000080
>> @@ -35,12 +40,13 @@ ASM_GLOBAL ASM_PFX(gStmSmiHandlerIdtr) # #
>> Constants relating to TXT_PROCESSOR_SMM_DESCRIPTOR #
>> -.equ DSC_OFFSET, 0xfb00
>> -.equ DSC_GDTPTR, 0x48
>> -.equ DSC_GDTSIZ, 0x50
>> -.equ DSC_CS, 0x14
>> -.equ DSC_DS, 0x16
>> -.equ DSC_SS, 0x18
>> +# .equ DSC_OFFSET, 0xfb00
>> +# .equ DSC_GDTPTR, 0x48
>> +# .equ DSC_GDTSIZ, 0x50
>> +#
>> +.equ DSC_CS, 0x14
>> +.equ DSC_DS, 0x16
>> +.equ DSC_SS, 0x18
>> .equ DSC_OTHERSEG, 0x1a
>> #
>> # Constants relating to CPU State Save Area @@ -71,12 +77,12 @@
>> _StmSmiEntryPoint:
>> # fix GDT descriptor
>> #
>> .byte 0x2e,0xa1 # mov ax, cs:[offset16]
>> - .word DSC_OFFSET + DSC_GDTSIZ
>> +ASM_PFX(gStmGdtSize): .space 2 # .word DSC_OFFSET + DSC_GDTSIZ
>> .byte 0x48 # dec ax
>> .byte 0x2e
>> movl %eax, (%rdi) # mov cs:[bx], ax
>> .byte 0x66,0x2e,0xa1 # mov eax, cs:[offset16]
>> - .word DSC_OFFSET + DSC_GDTPTR
>> +ASM_PFX(gStmGdtPtr): .space 2 # .word DSC_OFFSET + DSC_GDTPTR
>> .byte 0x2e
>> movw %ax, 2(%rdi)
>> .byte 0x66,0x2e
>> @@ -183,7 +189,11 @@ Base:
>> LongMode: # long mode (64-bit code) starts here
>> movabsq $ASM_PFX(gStmSmiHandlerIdtr), %rax
>> lidt (%rax)
>> - lea (DSC_OFFSET)(%rdi), %ebx
>> +
>> + movl $ASM_PFX(gStmPsdOffset), %ebx # lea (DSC_OFFSET)(%rdi),
>> %ebx
>> + movzxw (%ebx), %rsi
>> + leal (%rdi, %rsi), %ebx
>> +
>> movw DSC_DS(%rbx), %ax
>> movl %eax,%ds
>> movw DSC_OTHERSEG(%rbx), %ax
>> diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.asm
>> b/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.asm
>> index ad51e07..10913df 100644
>> --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.asm
>> +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.asm
>> @@ -1,5 +1,7 @@
>> ;------------------------------------------------------------------------------ ; ;
>> Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.<BR>
>> +; Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR> ;
>> ; This program and the accompanying materials ; are licensed and made
>> available under the terms and conditions of the BSD License ; which
>> accompanies this distribution. The full text of the license may be found at
>> @@ -32,6 +34,10 @@ EXTERNDEF gStmSmiStack:DWORD
>> EXTERNDEF gStmSmbase:DWORD
>> EXTERNDEF gStmXdSupported:BYTE
>> EXTERNDEF gStmSmiHandlerIdtr:FWORD
>> +EXTERNDEF gStmPsdOffset:WORD
>> +EXTERNDEF gStmGdtSize:WORD
>> +EXTERNDEF gStmGdtPtr:WORD
>> +
>>
>> MSR_IA32_MISC_ENABLE EQU 1A0h
>> MSR_EFER EQU 0c0000080h
>> @@ -40,13 +46,14 @@ MSR_EFER_XD EQU 0800h
>> ;
>> ; Constants relating to TXT_PROCESSOR_SMM_DESCRIPTOR ;
>> -DSC_OFFSET EQU 0fb00h
>> -DSC_GDTPTR EQU 48h
>> -DSC_GDTSIZ EQU 50h
>> -DSC_CS EQU 14h
>> -DSC_DS EQU 16h
>> -DSC_SS EQU 18h
>> -DSC_OTHERSEG EQU 1ah
>> +; DSC_OFFSET EQU 0fb00h
>> +; DSC_GDTPTR EQU 48h
>> +; DSC_GDTSIZ EQU 50h
>> +;
>> +DSC_CS EQU 14h
>> +DSC_DS EQU 16h
>> +DSC_SS EQU 18h
>> +DSC_OTHERSEG EQU 1ah
>> ;
>> ; Constants relating to CPU State Save Area ; @@ -74,12 +81,12 @@
>> _StmSmiEntryPoint:
>> DW offset _StmGdtDesc - _StmSmiEntryPoint + 8000h ; bx = GdtDesc
>> offset
>> ; fix GDT descriptor
>> DB 2eh, 0a1h ; mov ax, cs:[offset16]
>> - DW DSC_OFFSET + DSC_GDTSIZ
>> +gStmGdtSize DW ? ; DSC_OFFSET + DSC_GDTSIZ
>> DB 48h ; dec ax
>> DB 2eh
>> mov [rdi], eax ; mov cs:[bx], ax
>> DB 66h, 2eh, 0a1h ; mov eax, cs:[offset16]
>> - DW DSC_OFFSET + DSC_GDTPTR
>> +gStmGdtPtr DW ? ; DSC_OFFSET + DSC_GDTPTR
>> DB 2eh
>> mov [rdi + 2], ax ; mov cs:[bx + 2], eax
>> DB 66h, 2eh
>> @@ -178,7 +185,10 @@ Base:
>> @LongMode: ; long mode (64-bit code) starts here
>> mov rax, offset gStmSmiHandlerIdtr
>> lidt fword ptr [rax]
>> - lea ebx, [rdi + DSC_OFFSET]
>> +
>> + movzx rsi, word ptr [gStmPsdOffset] ; lea ebx, [rdi + DSC_OFFSET]
>> + lea ebx, [rdi + rsi] ;
>> +
>> mov ax, [rbx + DSC_DS]
>> mov ds, eax
>> mov ax, [rbx + DSC_OTHERSEG]
>> diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.nasm
>> b/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.nasm
>> index bcac643..df4c5a2 100644
>> --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.nasm
>> +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.nasm
>> @@ -1,5 +1,7 @@
>> ;------------------------------------------------------------------------------ ; ;
>> Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
>> +; Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR> ;
>> ; This program and the accompanying materials ; are licensed and made
>> available under the terms and conditions of the BSD License ; which
>> accompanies this distribution. The full text of the license may be found at
>> @@ -29,13 +31,14 @@ ; ; Constants relating to
>> TXT_PROCESSOR_SMM_DESCRIPTOR ; -%define DSC_OFFSET 0xfb00 -
>> %define DSC_GDTPTR 0x48 -%define DSC_GDTSIZ 0x50 -%define DSC_CS
>> 0x14 -%define DSC_DS 0x16 -%define DSC_SS 0x18 -%define DSC_OTHERSEG
>> 0x1a
>> +; %define DSC_OFFSET 0xfb00
>> +; %define DSC_GDTPTR 0x48
>> +; %define DSC_GDTSIZ 0x50
>> +;
>> +%define DSC_CS 0x14
>> +%define DSC_DS 0x16
>> +%define DSC_SS 0x18
>> +%define DSC_OTHERSEG 0x1a
>> ;
>> ; Constants relating to CPU State Save Area ; @@ -44,9 +47,9 @@
>>
>> %define PROTECT_MODE_CS 0x8
>> %define PROTECT_MODE_DS 0x20
>> -%define LONG_MODE_CS 0x38
>> -%define TSS_SEGMENT 0x40
>> -%define GDT_SIZE 0x50
>> +%define LONG_MODE_CS 0x38
>> +%define TSS_SEGMENT 0x40
>> +%define GDT_SIZE 0x50
>>
>> extern ASM_PFX(SmiRendezvous)
>> extern ASM_PFX(gStmSmiHandlerIdtr)
>> @@ -61,6 +64,10 @@ global ASM_PFX(gcStmSmiHandlerTemplate) global
>> ASM_PFX(gcStmSmiHandlerSize) global ASM_PFX(gcStmSmiHandlerOffset)
>>
>> +extern ASM_PFX(gStmPsdOffset)
>> +global ASM_PFX(gStmGdtSize)
>> +global ASM_PFX(gStmGdtPtr)
>> +
>> ASM_PFX(gStmSmbase) EQU StmSmbasePatch - 4
>> ASM_PFX(gStmSmiStack) EQU StmSmiStackPatch - 4
>> ASM_PFX(gStmSmiCr3) EQU StmSmiCr3Patch - 4
>> @@ -73,10 +80,18 @@ BITS 16
>> ASM_PFX(gcStmSmiHandlerTemplate):
>> _StmSmiEntryPoint:
>> mov bx, _StmGdtDesc - _StmSmiEntryPoint + 0x8000
>> - mov ax,[cs:DSC_OFFSET + DSC_GDTSIZ]
>> +
>> + mov eax, ASM_PFX(gStmGdtSize) ; mov ax, [cs:DSC_OFFSET +
>> DSC_GDTSIZ]
>> + mov si, [cs:eax] ;
>> + mov ax, [cs:si] ;
>> +
>> dec ax
>> mov [cs:bx], ax
>> - mov eax, [cs:DSC_OFFSET + DSC_GDTPTR]
>> +
>> + mov eax, ASM_PFX(gStmGdtPtr) ; mov eax, [cs:DSC_OFFSET +
>> DSC_GDTPTR]
>> + mov si, [cs:eax] ;
>> + mov eax, [cs:si] ;
>> +
>> mov [cs:bx + 2], eax
>> o32 lgdt [cs:bx] ; lgdt fword ptr cs:[bx]
>> mov ax, PROTECT_MODE_CS
>> @@ -166,7 +181,10 @@ Base:
>> @LongMode: ; long mode (64-bit code) starts here
>> mov rax, ASM_PFX(gStmSmiHandlerIdtr)
>> lidt [rax]
>> - lea ebx, [rdi + DSC_OFFSET]
>> +
>> + movzx rsi, word [ASM_PFX(gStmPsdOffset)] ; lea ebx, [rdi +
>> DSC_OFFSET]
>> + lea ebx, [rdi + rsi] ;
>> +
>> mov ax, [rbx + DSC_DS]
>> mov ds, eax
>> mov ax, [rbx + DSC_OTHERSEG]
>> @@ -262,5 +280,8 @@ _StmSmiHandler:
>> ; STM init finish
>> jmp CommonHandler
>>
>> +ASM_PFX(gStmGdtSize) : RESW 1
>> +ASM_PFX(gStmGdtPtr) : RESW 1
>> +
>> ASM_PFX(gcStmSmiHandlerSize) : DW $ - _StmSmiEntryPoint
>> ASM_PFX(gcStmSmiHandlerOffset) : DW _StmSmiHandler -
>> _StmSmiEntryPoint
>> --
>> 2.7.4
>
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH v5 1/2] UefiCpuPkg/SmmCpuFeaturesLib: Use global variables to replace macros
2017-10-17 14:50 ` Yao, Jiewen
@ 2017-10-17 15:14 ` Laszlo Ersek
2017-10-17 16:40 ` Duran, Leo
2017-10-18 1:50 ` Yao, Jiewen
2017-10-17 16:30 ` Duran, Leo
1 sibling, 2 replies; 30+ messages in thread
From: Laszlo Ersek @ 2017-10-17 15:14 UTC (permalink / raw)
To: Yao, Jiewen, Duran, Leo
Cc: edk2-devel@lists.01.org, Paolo Bonzini, Ni, Ruiyu,
Kinney, Michael D, Justen, Jordan L, Gao, Liming
On 10/17/17 16:50, Yao, Jiewen wrote:
> I think it is unnecessary. All intel CPU is using same offset. All amd CPU is using same offset. It can be identified easily by code.
> Adding a new API now is also an incompatible change because that requires all existing featurelib change to add a new API. We have lots of close source platform using its own featurelib.
>
> May I know what problem we are trying to resolve by adding a new API?
QEMU (and hence OVMF) uses the AMD save state map even when it emulates
Intel CPUs.
The reason is that the Intel SDM does not specify the Intel save state
map in sufficient detail (for emulation by QEMU), while the AMD spec
does. So, as an emulation target, only the AMD one is implementable in
QEMU (and supportable in OVMF), regardless of whether QEMU reports the
virtual CPU manufacturer as Intel vs. AMD.
If PiSmmCpuDxeSmm used a CPUID check, saw "Intel" as manufacturer, and
then used the Intel definition of the save state map, then
PiSmmCpuDxeSmm would break on QEMU / as part of OVMF.
Thanks,
Laszlo
>
>
> thank you!
> Yao, Jiewen
>
>
>> 在 2017年10月17日，下午10:20，Duran, Leo <leo.duran@amd.com> 写道：
>>
>> Yao, Lazlo, et al,
>>
>> For the SRAM_SAVE_STATE_MAP_OFFSET:
>> I propose returning the value by a function in SmmCpuFeaturesLib... Here's the rationale:
>> - The value is fixed per CPU architecture, so this qualifies as a CPU feature.
>> - The logic for CPU architecture detection would be in one place (e.g., PiSmmCpuDxeSmm would call the library function)
>> - The OVMF and Quark instances of the library could just return the current (default) value, so no compatibility issues.
>>
>> if you agree with this is an acceptable solution, I will submit a revised patch-set to address just the SRAM_SAVE_STATE_MAP_OFFSET.
>> (BTW, I'm re-evaluating the changes submitted for the PSD offset, with the goal of just using the default value and dropping those changes)
>>
>> Thanks,
>> Leo.
>>
>>> -----Original Message-----
>>> From: Duran, Leo
>>> Sent: Wednesday, October 11, 2017 2:46 PM
>>> To: edk2-devel@lists.01.org
>>> Cc: Duran, Leo <leo.duran@amd.com>; Jiewen Yao
>>> <jiewen.yao@intel.com>; Ruiyu Ni <ruiyu.ni@intel.com>; Michael D Kinney
>>> <michael.d.kinney@intel.com>; Jordan Justen <jordan.l.justen@intel.com>;
>>> Liming Gao <liming.gao@intel.com>
>>> Subject: [PATCH v5 1/2] UefiCpuPkg/SmmCpuFeaturesLib: Use global
>>> variables to replace macros
>>>
>>> Set global variables on Constructor function based on CPUID checks.
>>> The variables replace Intel macros to allow support on AMD x86 systems.
>>>
>>> Specifically, the replaced macros are:
>>> 1) SRAM_SAVE_STATE_MAP_OFFSET
>>> 2) TXT_SMM_PSD_OFFSET
>>>
>>> Cc: Jiewen Yao <jiewen.yao@intel.com>
>>> Cc: Ruiyu Ni <ruiyu.ni@intel.com>
>>> Cc: Michael D Kinney <michael.d.kinney@intel.com>
>>> Cc: Jordan Justen <jordan.l.justen@intel.com>
>>> Cc: Liming Gao <liming.gao@intel.com>
>>> Contributed-under: TianoCore Contribution Agreement 1.1
>>> Signed-off-by: Leo Duran <leo.duran@amd.com>
>>> ---
>>> .../Library/SmmCpuFeaturesLib/Ia32/SmiEntry.S | 28 ++++++----
>>> .../Library/SmmCpuFeaturesLib/Ia32/SmiEntry.asm | 29 +++++++----
>>> .../Library/SmmCpuFeaturesLib/Ia32/SmiEntry.nasm | 43 ++++++++++++---
>>> -
>>> UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCommon.h | 48
>>> ++++++++++++++++++
>>> .../Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c | 59
>>> ++++++++++++++++++----
>>> .../SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf | 3 ++
>>> .../SmmCpuFeaturesLib/SmmCpuFeaturesLibStm.inf | 3 ++
>>> UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c | 39
>>> ++++++++++++--
>>> .../Library/SmmCpuFeaturesLib/X64/SmiEntry.S | 28 ++++++----
>>> .../Library/SmmCpuFeaturesLib/X64/SmiEntry.asm | 30 +++++++----
>>> .../Library/SmmCpuFeaturesLib/X64/SmiEntry.nasm | 47 ++++++++++++---
>>> --
>>> 11 files changed, 282 insertions(+), 75 deletions(-) create mode 100644
>>> UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCommon.h
>>>
>>> diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.S
>>> b/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.S
>>> index 4c0f8c8..c7b49d7 100644
>>> --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.S
>>> +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.S
>>> @@ -1,6 +1,8 @@
>>> #------------------------------------------------------------------------------
>>> #
>>> # Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.<BR>
>>> +# Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR> #
>>> # This program and the accompanying materials # are licensed and made
>>> available under the terms and conditions of the BSD License # which
>>> accompanies this distribution. The full text of the license may be found at
>>> @@ -28,6 +30,9 @@ ASM_GLOBAL ASM_PFX(gStmSmbase) ASM_GLOBAL
>>> ASM_PFX(gStmXdSupported) ASM_GLOBAL ASM_PFX(FeaturePcdGet
>>> (PcdCpuSmmStackGuard)) ASM_GLOBAL ASM_PFX(gStmSmiHandlerIdtr)
>>> +ASM_GLOBAL ASM_PFX(gStmPsdOffset)
>>> +ASM_GLOBAL ASM_PFX(gStmGdtSize)
>>> +ASM_GLOBAL ASM_PFX(gStmGdtPtr)
>>>
>>> .equ MSR_IA32_MISC_ENABLE, 0x1A0
>>> .equ MSR_EFER, 0xc0000080
>>> @@ -36,12 +41,13 @@ ASM_GLOBAL ASM_PFX(gStmSmiHandlerIdtr) # #
>>> Constants relating to TXT_PROCESSOR_SMM_DESCRIPTOR #
>>> -.equ DSC_OFFSET, 0xfb00
>>> -.equ DSC_GDTPTR, 0x48
>>> -.equ DSC_GDTSIZ, 0x50
>>> -.equ DSC_CS, 0x14
>>> -.equ DSC_DS, 0x16
>>> -.equ DSC_SS, 0x18
>>> +# .equ DSC_OFFSET, 0xfb00
>>> +# .equ DSC_GDTPTR, 0x48
>>> +# .equ DSC_GDTSIZ, 0x50
>>> +#
>>> +.equ DSC_CS, 0x14
>>> +.equ DSC_DS, 0x16
>>> +.equ DSC_SS, 0x18
>>> .equ DSC_OTHERSEG, 0x1A
>>>
>>> .equ PROTECT_MODE_CS, 0x08
>>> @@ -55,11 +61,11 @@ _StmSmiEntryPoint:
>>> .byte 0xbb # mov bx, imm16
>>> .word _StmGdtDesc - _StmSmiEntryPoint + 0x8000
>>> .byte 0x2e,0xa1 # mov ax, cs:[offset16]
>>> - .word DSC_OFFSET + DSC_GDTSIZ
>>> +ASM_PFX(gStmGdtSize): .space 2 # .word DSC_OFFSET + DSC_GDTSIZ
>>> decl %eax
>>> movl %eax, %cs:(%edi) # mov cs:[bx], ax
>>> .byte 0x66,0x2e,0xa1 # mov eax, cs:[offset16]
>>> - .word DSC_OFFSET + DSC_GDTPTR
>>> +ASM_PFX(gStmGdtPtr): .space 2 # .word DSC_OFFSET + DSC_GDTPTR
>>> movw %ax, %cs:2(%edi)
>>> movw %ax, %bp # ebp = GDT base
>>> .byte 0x66
>>> @@ -167,7 +173,11 @@ XdDone:
>>> movl %cr0, %ebx
>>> orl $0x080010023, %ebx # enable paging + WP + NE + MP + PE
>>> movl %ebx, %cr0
>>> - leal DSC_OFFSET(%edi),%ebx
>>> +
>>> + movl $ASM_PFX(gStmPsdOffset), %ebx # leal DSC_OFFSET(%edi),
>>> %ebx
>>> + movzxw (%ebx), %esi
>>> + leal (%edi, %esi), %ebx
>>> +
>>> movw DSC_DS(%ebx),%ax
>>> movl %eax, %ds
>>> movw DSC_OTHERSEG(%ebx),%ax
>>> diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.asm
>>> b/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.asm
>>> index 91dc1eb..4dbe276 100644
>>> --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.asm
>>> +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.asm
>>> @@ -1,5 +1,7 @@
>>> ;------------------------------------------------------------------------------ ; ;
>>> Copyright (c) 2009 - 2017, Intel Corporation. All rights reserved.<BR>
>>> +; Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR> ;
>>> ; This program and the accompanying materials ; are licensed and made
>>> available under the terms and conditions of the BSD License ; which
>>> accompanies this distribution. The full text of the license may be found at
>>> @@ -29,13 +31,14 @@ MSR_EFER_XD EQU 0800h
>>> ;
>>> ; Constants relating to TXT_PROCESSOR_SMM_DESCRIPTOR ;
>>> -DSC_OFFSET EQU 0fb00h
>>> -DSC_GDTPTR EQU 48h
>>> -DSC_GDTSIZ EQU 50h
>>> -DSC_CS EQU 14h
>>> -DSC_DS EQU 16h
>>> -DSC_SS EQU 18h
>>> -DSC_OTHERSEG EQU 1Ah
>>> +; DSC_OFFSET EQU 0fb00h
>>> +; DSC_GDTPTR EQU 48h
>>> +; DSC_GDTSIZ EQU 50h
>>> +;
>>> +DSC_CS EQU 14h
>>> +DSC_DS EQU 16h
>>> +DSC_SS EQU 18h
>>> +DSC_OTHERSEG EQU 1Ah
>>>
>>> PROTECT_MODE_CS EQU 08h
>>> PROTECT_MODE_DS EQU 20h
>>> @@ -54,6 +57,9 @@ EXTERNDEF gStmSmbase:DWORD
>>> EXTERNDEF gStmXdSupported:BYTE
>>> EXTERNDEF FeaturePcdGet (PcdCpuSmmStackGuard):BYTE
>>> EXTERNDEF gStmSmiHandlerIdtr:FWORD
>>> +EXTERNDEF gStmPsdOffset:WORD
>>> +EXTERNDEF gStmGdtSize:WORD
>>> +EXTERNDEF gStmGdtPtr:WORD
>>>
>>> .code
>>>
>>> @@ -63,11 +69,11 @@ _StmSmiEntryPoint:
>>> DB 0bbh ; mov bx, imm16
>>> DW offset _StmGdtDesc - _StmSmiEntryPoint + 8000h
>>> DB 2eh, 0a1h ; mov ax, cs:[offset16]
>>> - DW DSC_OFFSET + DSC_GDTSIZ
>>> +gStmGdtSize DW ? ; DSC_OFFSET + DSC_GDTSIZ
>>> dec eax
>>> mov cs:[edi], eax ; mov cs:[bx], ax
>>> DB 66h, 2eh, 0a1h ; mov eax, cs:[offset16]
>>> - DW DSC_OFFSET + DSC_GDTPTR
>>> +gStmGdtPtr DW ? ; DSC_OFFSET + DSC_GDTPTR
>>> mov cs:[edi + 2], ax ; mov cs:[bx + 2], eax
>>> mov bp, ax ; ebp = GDT base
>>> DB 66h
>>> @@ -174,7 +180,10 @@ gStmXdSupported DB 1
>>> mov ebx, cr0
>>> or ebx, 080010023h ; enable paging + WP + NE + MP + PE
>>> mov cr0, ebx
>>> - lea ebx, [edi + DSC_OFFSET]
>>> +
>>> + movzx esi, word ptr [gStmPsdOffset] ; lea ebx, [edi + DSC_OFFSET]
>>> + lea ebx, [edi + esi] ;
>>> +
>>> mov ax, [ebx + DSC_DS]
>>> mov ds, eax
>>> mov ax, [ebx + DSC_OTHERSEG]
>>> diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.nasm
>>> b/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.nasm
>>> index 00c0f067..023923a 100644
>>> --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.nasm
>>> +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.nasm
>>> @@ -1,5 +1,7 @@
>>> ;------------------------------------------------------------------------------ ; ;
>>> Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
>>> +; Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR> ;
>>> ; This program and the accompanying materials ; are licensed and made
>>> available under the terms and conditions of the BSD License ; which
>>> accompanies this distribution. The full text of the license may be found at
>>> @@ -25,17 +27,18 @@ ; ; Constants relating to
>>> TXT_PROCESSOR_SMM_DESCRIPTOR ; -%define DSC_OFFSET 0xfb00 -
>>> %define DSC_GDTPTR 0x48 -%define DSC_GDTSIZ 0x50 -%define DSC_CS
>>> 0x14 -%define DSC_DS 0x16 -%define DSC_SS 0x18 -%define DSC_OTHERSEG
>>> 0x1a
>>> +; %define DSC_OFFSET 0xfb00
>>> +; %define DSC_GDTPTR 0x48
>>> +; %define DSC_GDTSIZ 0x50
>>> +;
>>> +%define DSC_CS 0x14
>>> +%define DSC_DS 0x16
>>> +%define DSC_SS 0x18
>>> +%define DSC_OTHERSEG 0x1a
>>>
>>> %define PROTECT_MODE_CS 0x8
>>> %define PROTECT_MODE_DS 0x20
>>> -%define TSS_SEGMENT 0x40
>>> +%define TSS_SEGMENT 0x40
>>>
>>> extern ASM_PFX(SmiRendezvous)
>>> extern ASM_PFX(FeaturePcdGet (PcdCpuSmmStackGuard)) @@ -51,6
>>> +54,10 @@ global ASM_PFX(gStmSmbase) global
>>> ASM_PFX(gStmXdSupported) extern ASM_PFX(gStmSmiHandlerIdtr)
>>>
>>> +extern ASM_PFX(gStmPsdOffset)
>>> +global ASM_PFX(gStmGdtSize)
>>> +global ASM_PFX(gStmGdtPtr)
>>> +
>>> ASM_PFX(gStmSmiCr3) EQU StmSmiCr3Patch - 4
>>> ASM_PFX(gStmSmiStack) EQU StmSmiStackPatch - 4
>>> ASM_PFX(gStmSmbase) EQU StmSmbasePatch - 4
>>> @@ -62,10 +69,18 @@ BITS 16
>>> ASM_PFX(gcStmSmiHandlerTemplate):
>>> _StmSmiEntryPoint:
>>> mov bx, _StmGdtDesc - _StmSmiEntryPoint + 0x8000
>>> - mov ax,[cs:DSC_OFFSET + DSC_GDTSIZ]
>>> +
>>> + mov eax, ASM_PFX(gStmGdtSize) ; mov ax, [cs:DSC_OFFSET +
>>> DSC_GDTSIZ]
>>> + mov si, [cs:eax] ;
>>> + mov ax, [cs:si] ;
>>> +
>>> dec ax
>>> mov [cs:bx], ax
>>> - mov eax, [cs:DSC_OFFSET + DSC_GDTPTR]
>>> +
>>> + mov eax, ASM_PFX(gStmGdtPtr) ; mov eax, [cs:DSC_OFFSET +
>>> DSC_GDTPTR]
>>> + mov si, [cs:eax] ;
>>> + mov eax, [cs:si] ;
>>> +
>>> mov [cs:bx + 2], eax
>>> mov ebp, eax ; ebp = GDT base
>>> o32 lgdt [cs:bx] ; lgdt fword ptr cs:[bx]
>>> @@ -166,7 +181,10 @@ StmXdSupportedPatch:
>>> mov ebx, cr0
>>> or ebx, 0x80010023 ; enable paging + WP + NE + MP + PE
>>> mov cr0, ebx
>>> - lea ebx, [edi + DSC_OFFSET]
>>> +
>>> + movzx esi, word [ASM_PFX(gStmPsdOffset)] ; lea ebx, [edi +
>>> DSC_OFFSET]
>>> + lea ebx, [edi + esi] ;
>>> +
>>> mov ax, [ebx + DSC_DS]
>>> mov ds, eax
>>> mov ax, [ebx + DSC_OTHERSEG]
>>> @@ -271,5 +289,8 @@ _StmSmiHandler:
>>> ; STM init finish
>>> jmp CommonHandler
>>>
>>> +ASM_PFX(gStmGdtSize) : RESW 1
>>> +ASM_PFX(gStmGdtPtr) : RESW 1
>>> +
>>> ASM_PFX(gcStmSmiHandlerSize) : DW $ - _StmSmiEntryPoint
>>> ASM_PFX(gcStmSmiHandlerOffset) : DW _StmSmiHandler -
>>> _StmSmiEntryPoint
>>> diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCommon.h
>>> b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCommon.h
>>> new file mode 100644
>>> index 0000000..78b3a5b
>>> --- /dev/null
>>> +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCommon.h
>>> @@ -0,0 +1,48 @@
>>> +/** @file
>>> + Common declarations
>>> +
>>> + Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>
>>> +
>>> + This program and the accompanying materials are licensed and made
>>> + available under the terms and conditions of the BSD License which
>>> + accompanies this distribution. The full text of the license may be
>>> + found at http://opensource.org/licenses/bsd-license.php.
>>> +
>>> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
>>> BASIS,
>>> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
>>> EXPRESS OR IMPLIED.
>>> +
>>> +**/
>>> +
>>> +#ifndef _SMM_COMMON_H_
>>> +#define _SMM_COMMON_H_
>>> +
>>> +#include <Register/Amd/Cpuid.h>
>>> +
>>> +//
>>> +// Definitions for AMD systems are based on contents of the // AMD64
>>> +Architecture Programmer's Manual // Volume 2: System Programming,
>>> +Section 10 System-Management Mode // #define
>>> +AMD_SMRAM_SAVE_STATE_MAP_OFFSET 0xfe00
>>> +#define AMD_SMM_PSD_OFFSET 0xfc00
>>> +
>>> +//
>>> +// External global variables for SMRAM offsets // extern UINT16
>>> +gSmramStateMapOffset; extern UINT16 gSmmPsdOffset;
>>> +
>>> +
>>> +/**
>>> + Determine if the standard CPU signature is "AuthenticAMD".
>>> +
>>> + @retval TRUE The CPU signature matches.
>>> + @retval FALSE The CPU signature does not match.
>>> +
>>> +**/
>>> +BOOLEAN
>>> +SmmStandardSignatureIsAuthenticAMD (
>>> + VOID
>>> + );
>>> +
>>> +#endif
>>> diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c
>>> b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c
>>> index 2d2bc6d..1c12095 100644
>>> --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c
>>> +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c
>>> @@ -1,14 +1,16 @@
>>> /** @file
>>> -The CPU specific programming for PiSmmCpuDxeSmm module.
>>> + The CPU specific programming for PiSmmCpuDxeSmm module.
>>>
>>> -Copyright (c) 2010 - 2016, Intel Corporation. All rights reserved.<BR> -This
>>> program and the accompanying materials -are licensed and made available
>>> under the terms and conditions of the BSD License -which accompanies this
>>> distribution. The full text of the license may be found at -
>>> http://opensource.org/licenses/bsd-license.php
>>> + Copyright (c) 2010 - 2016, Intel Corporation. All rights
>>> + reserved.<BR> Copyright (c) 2017, AMD Incorporated. All rights
>>> + reserved.<BR>
>>>
>>> -THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
>>> BASIS, -WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
>>> EXPRESS OR IMPLIED.
>>> + This program and the accompanying materials are licensed and made
>>> + available under the terms and conditions of the BSD License which
>>> + accompanies this distribution. The full text of the license may be
>>> + found at http://opensource.org/licenses/bsd-license.php
>>> +
>>> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
>>> BASIS,
>>> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
>>> EXPRESS OR IMPLIED.
>>>
>>> **/
>>>
>>> @@ -22,6 +24,8 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY
>>> KIND, EITHER EXPRESS OR IMPLIED.
>>> #include <Register/Cpuid.h>
>>> #include <Register/SmramSaveStateMap.h>
>>>
>>> +#include "SmmCommon.h"
>>> +
>>> //
>>> // Machine Specific Registers (MSRs)
>>> //
>>> @@ -41,6 +45,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY
>>> KIND, EITHER EXPRESS OR IMPLIED.
>>> #define SMM_FEATURES_LIB_IA32_MCA_CAP 0x17D
>>> #define SMM_CODE_ACCESS_CHK_BIT BIT58
>>>
>>> +
>>> /**
>>> Internal worker function that is called to complete CPU initialization at the
>>> end of SmmCpuFeaturesInitializeProcessor().
>>> @@ -77,6 +82,13 @@ BOOLEAN mNeedConfigureMtrrs = TRUE; //
>>> BOOLEAN *mSmrrEnabled;
>>>
>>> +//
>>> +// Set default value for SMRAM offset
>>> +// from <Register/SmramSaveStateMap.h> //
>>> +UINT16 gSmramStateMapOffset = SMRAM_SAVE_STATE_MAP_OFFSET;
>>> +
>>> +
>>> /**
>>> The constructor function
>>>
>>> @@ -99,6 +111,13 @@ SmmCpuFeaturesLibConstructor (
>>> UINTN ModelId;
>>>
>>> //
>>> + // Override SMRAM offset for AMD
>>> + //
>>> + if (SmmStandardSignatureIsAuthenticAMD ()) {
>>> + gSmramStateMapOffset = AMD_SMRAM_SAVE_STATE_MAP_OFFSET; }
>>> +
>>> + //
>>> // Retrieve CPU Family and Model
>>> //
>>> AsmCpuid (CPUID_VERSION_INFO, &RegEax, NULL, NULL, &RegEdx); @@ -
>>> 224,7 +243,7 @@ SmmCpuFeaturesInitializeProcessor (
>>> //
>>> // Configure SMBASE.
>>> //
>>> - CpuState = (SMRAM_SAVE_STATE_MAP
>>> *)(UINTN)(SMM_DEFAULT_SMBASE +
>>> SMRAM_SAVE_STATE_MAP_OFFSET);
>>> + CpuState = (SMRAM_SAVE_STATE_MAP
>>> *)(UINTN)(SMM_DEFAULT_SMBASE +
>>> + gSmramStateMapOffset);
>>> CpuState->x86.SMBASE = (UINT32)CpuHotPlugData->SmBase[CpuIndex];
>>>
>>> //
>>> @@ -630,3 +649,25 @@ SmmCpuFeaturesAllocatePageTableMemory (
>>> return NULL;
>>> }
>>>
>>> +
>>> +/**
>>> + Determine if the standard CPU signature is "AuthenticAMD".
>>> +
>>> + @retval TRUE The CPU signature matches.
>>> + @retval FALSE The CPU signature does not match.
>>> +
>>> +**/
>>> +BOOLEAN
>>> +SmmStandardSignatureIsAuthenticAMD (
>>> + VOID
>>> + )
>>> +{
>>> + UINT32 RegEbx;
>>> + UINT32 RegEcx;
>>> + UINT32 RegEdx;
>>> +
>>> + AsmCpuid (CPUID_SIGNATURE, NULL, &RegEbx, &RegEcx, &RegEdx);
>>> + return (RegEbx == CPUID_SIGNATURE_AUTHENTIC_AMD_EBX &&
>>> + RegEcx == CPUID_SIGNATURE_AUTHENTIC_AMD_ECX &&
>>> + RegEdx == CPUID_SIGNATURE_AUTHENTIC_AMD_EDX);
>>> +}
>>> diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf
>>> b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf
>>> index 77908b0..6a39d4b 100644
>>> --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf
>>> +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf
>>> @@ -2,6 +2,8 @@
>>> # The CPU specific programming for PiSmmCpuDxeSmm module.
>>> #
>>> # Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.<BR>
>>> +# Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR> #
>>> # This program and the accompanying materials # are licensed and made
>>> available under the terms and conditions of the BSD License # which
>>> accompanies this distribution. The full text of the license may be found at
>>> @@ -24,6 +26,7 @@
>>>
>>> [Sources]
>>> SmmCpuFeaturesLib.c
>>> + SmmCommon.h
>>> SmmCpuFeaturesLibNoStm.c
>>>
>>> [Packages]
>>> diff --git
>>> a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibStm.inf
>>> b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibStm.inf
>>> index db8dcdc..a76bed6 100644
>>> --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibStm.inf
>>> +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibStm.inf
>>> @@ -3,6 +3,8 @@
>>> # is included.
>>> #
>>> # Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.<BR>
>>> +# Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR> #
>>> # This program and the accompanying materials # are licensed and made
>>> available under the terms and conditions of the BSD License # which
>>> accompanies this distribution. The full text of the license may be found at
>>> @@ -25,6 +27,7 @@
>>>
>>> [Sources]
>>> SmmCpuFeaturesLib.c
>>> + SmmCommon.h
>>> SmmStm.c
>>> SmmStm.h
>>>
>>> diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c
>>> b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c
>>> index 45015b8..5f7c3db 100644
>>> --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c
>>> +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c
>>> @@ -2,6 +2,8 @@
>>> SMM STM support functions
>>>
>>> Copyright (c) 2015 - 2017, Intel Corporation. All rights reserved.<BR>
>>> + Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>
>>> +
>>> This program and the accompanying materials
>>> are licensed and made available under the terms and conditions of the BSD
>>> License
>>> which accompanies this distribution. The full text of the license may be
>>> found at @@ -28,6 +30,8 @@ #include <Protocol/MpService.h>
>>>
>>> #include "SmmStm.h"
>>> +#include "SmmCommon.h"
>>> +
>>>
>>> #define TXT_EVTYPE_BASE 0x400
>>> #define TXT_EVTYPE_STM_HASH (TXT_EVTYPE_BASE + 14)
>>> @@ -97,6 +101,20 @@ extern volatile UINT8
>>> gcStmSmiHandlerTemplate[];
>>> extern CONST UINT16 gcStmSmiHandlerSize;
>>> extern UINT16 gcStmSmiHandlerOffset;
>>> extern BOOLEAN gStmXdSupported;
>>> +extern UINT16 gStmGdtSize;
>>> +extern UINT16 gStmGdtPtr;
>>> +
>>> +//
>>> +// Constants relating to TXT_PROCESSOR_SMM_DESCRIPTOR //
>>> +#define TXT_PSD_GDTPTR 0x48
>>> +#define TXT_PSD_GDTSIZE 0x50
>>> +
>>> +//
>>> +// Set default value for PSD offset in SMRAM // from
>>> +<Register/StmApi.h> //
>>> +UINT16 gStmPsdOffset = TXT_SMM_PSD_OFFSET;
>>>
>>> //
>>> // Variables used by SMI Handler
>>> @@ -145,6 +163,19 @@ SmmCpuFeaturesLibStmConstructor (
>>> ASSERT_EFI_ERROR (Status);
>>>
>>> //
>>> + // Override PSD offset for AMD
>>> + //
>>> + if (SmmStandardSignatureIsAuthenticAMD ()) {
>>> + gStmPsdOffset = AMD_SMM_PSD_OFFSET; }
>>> +
>>> + //
>>> + // Initialize STM global variables associated with SMI Handler //
>>> + gStmGdtSize = gStmPsdOffset + TXT_PSD_GDTSIZE; gStmGdtPtr =
>>> + gStmPsdOffset + TXT_PSD_GDTPTR;
>>> +
>>> + //
>>> // Lookup the MP Services Protocol
>>> //
>>> Status = gBS->LocateProtocol (
>>> @@ -276,8 +307,8 @@ SmmCpuFeaturesInstallSmiHandler (
>>> UINT32 RegEdx;
>>> EFI_PROCESSOR_INFORMATION ProcessorInfo;
>>>
>>> - CopyMem ((VOID *)((UINTN)SmBase + TXT_SMM_PSD_OFFSET),
>>> &gcStmPsd, sizeof (gcStmPsd));
>>> - Psd = (TXT_PROCESSOR_SMM_DESCRIPTOR *)(VOID *)((UINTN)SmBase +
>>> TXT_SMM_PSD_OFFSET);
>>> + CopyMem ((VOID *)((UINTN)SmBase + gStmPsdOffset), &gcStmPsd,
>>> sizeof
>>> + (gcStmPsd)); Psd = (TXT_PROCESSOR_SMM_DESCRIPTOR *)(VOID
>>> + *)((UINTN)SmBase + gStmPsdOffset);
>>> Psd->SmmGdtPtr = GdtBase;
>>> Psd->SmmGdtSize = (UINT32)GdtSize;
>>>
>>> @@ -416,7 +447,7 @@ SmmEndOfDxeEventNotify (
>>> }
>>>
>>> for (Index = 0; Index < gSmst->NumberOfCpus; Index++) {
>>> - Psd = (TXT_PROCESSOR_SMM_DESCRIPTOR *)((UINTN)gSmst-
>>>> CpuSaveState[Index] - SMRAM_SAVE_STATE_MAP_OFFSET +
>>> TXT_SMM_PSD_OFFSET);
>>> + Psd = (TXT_PROCESSOR_SMM_DESCRIPTOR
>>> + *)((UINTN)gSmst->CpuSaveState[Index] - gSmramStateMapOffset +
>>> + gStmPsdOffset);
>>> DEBUG ((DEBUG_INFO, "Index=%d Psd=%p Rsdp=%p\n", Index, Psd,
>>> Rsdp));
>>> Psd->AcpiRsdp = (UINT64)(UINTN)Rsdp;
>>> }
>>> @@ -1266,7 +1297,7 @@ NotifyStmResourceChange (
>>> TXT_PROCESSOR_SMM_DESCRIPTOR *Psd;
>>>
>>> for (Index = 0; Index < gSmst->NumberOfCpus; Index++) {
>>> - Psd = (TXT_PROCESSOR_SMM_DESCRIPTOR *)((UINTN)gSmst-
>>>> CpuSaveState[Index] - SMRAM_SAVE_STATE_MAP_OFFSET +
>>> TXT_SMM_PSD_OFFSET);
>>> + Psd = (TXT_PROCESSOR_SMM_DESCRIPTOR
>>> + *)((UINTN)gSmst->CpuSaveState[Index] - gSmramStateMapOffset +
>>> + gStmPsdOffset);
>>> Psd->BiosHwResourceRequirementsPtr = (UINT64)(UINTN)StmResource;
>>> }
>>> return ;
>>> diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.S
>>> b/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.S
>>> index 1f9f91c..5f3386a 100644
>>> --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.S
>>> +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.S
>>> @@ -1,6 +1,8 @@
>>> #------------------------------------------------------------------------------
>>> #
>>> # Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.<BR>
>>> +# Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR> #
>>> # This program and the accompanying materials # are licensed and made
>>> available under the terms and conditions of the BSD License # which
>>> accompanies this distribution. The full text of the license may be found at
>>> @@ -27,6 +29,9 @@ ASM_GLOBAL ASM_PFX(gStmSmiStack) ASM_GLOBAL
>>> ASM_PFX(gStmSmbase) ASM_GLOBAL ASM_PFX(gStmXdSupported)
>>> ASM_GLOBAL ASM_PFX(gStmSmiHandlerIdtr)
>>> +ASM_GLOBAL ASM_PFX(gStmPsdOffset)
>>> +ASM_GLOBAL ASM_PFX(gStmGdtSize)
>>> +ASM_GLOBAL ASM_PFX(gStmGdtPtr)
>>>
>>> .equ MSR_IA32_MISC_ENABLE, 0x1A0
>>> .equ MSR_EFER, 0xc0000080
>>> @@ -35,12 +40,13 @@ ASM_GLOBAL ASM_PFX(gStmSmiHandlerIdtr) # #
>>> Constants relating to TXT_PROCESSOR_SMM_DESCRIPTOR #
>>> -.equ DSC_OFFSET, 0xfb00
>>> -.equ DSC_GDTPTR, 0x48
>>> -.equ DSC_GDTSIZ, 0x50
>>> -.equ DSC_CS, 0x14
>>> -.equ DSC_DS, 0x16
>>> -.equ DSC_SS, 0x18
>>> +# .equ DSC_OFFSET, 0xfb00
>>> +# .equ DSC_GDTPTR, 0x48
>>> +# .equ DSC_GDTSIZ, 0x50
>>> +#
>>> +.equ DSC_CS, 0x14
>>> +.equ DSC_DS, 0x16
>>> +.equ DSC_SS, 0x18
>>> .equ DSC_OTHERSEG, 0x1a
>>> #
>>> # Constants relating to CPU State Save Area @@ -71,12 +77,12 @@
>>> _StmSmiEntryPoint:
>>> # fix GDT descriptor
>>> #
>>> .byte 0x2e,0xa1 # mov ax, cs:[offset16]
>>> - .word DSC_OFFSET + DSC_GDTSIZ
>>> +ASM_PFX(gStmGdtSize): .space 2 # .word DSC_OFFSET + DSC_GDTSIZ
>>> .byte 0x48 # dec ax
>>> .byte 0x2e
>>> movl %eax, (%rdi) # mov cs:[bx], ax
>>> .byte 0x66,0x2e,0xa1 # mov eax, cs:[offset16]
>>> - .word DSC_OFFSET + DSC_GDTPTR
>>> +ASM_PFX(gStmGdtPtr): .space 2 # .word DSC_OFFSET + DSC_GDTPTR
>>> .byte 0x2e
>>> movw %ax, 2(%rdi)
>>> .byte 0x66,0x2e
>>> @@ -183,7 +189,11 @@ Base:
>>> LongMode: # long mode (64-bit code) starts here
>>> movabsq $ASM_PFX(gStmSmiHandlerIdtr), %rax
>>> lidt (%rax)
>>> - lea (DSC_OFFSET)(%rdi), %ebx
>>> +
>>> + movl $ASM_PFX(gStmPsdOffset), %ebx # lea (DSC_OFFSET)(%rdi),
>>> %ebx
>>> + movzxw (%ebx), %rsi
>>> + leal (%rdi, %rsi), %ebx
>>> +
>>> movw DSC_DS(%rbx), %ax
>>> movl %eax,%ds
>>> movw DSC_OTHERSEG(%rbx), %ax
>>> diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.asm
>>> b/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.asm
>>> index ad51e07..10913df 100644
>>> --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.asm
>>> +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.asm
>>> @@ -1,5 +1,7 @@
>>> ;------------------------------------------------------------------------------ ; ;
>>> Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.<BR>
>>> +; Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR> ;
>>> ; This program and the accompanying materials ; are licensed and made
>>> available under the terms and conditions of the BSD License ; which
>>> accompanies this distribution. The full text of the license may be found at
>>> @@ -32,6 +34,10 @@ EXTERNDEF gStmSmiStack:DWORD
>>> EXTERNDEF gStmSmbase:DWORD
>>> EXTERNDEF gStmXdSupported:BYTE
>>> EXTERNDEF gStmSmiHandlerIdtr:FWORD
>>> +EXTERNDEF gStmPsdOffset:WORD
>>> +EXTERNDEF gStmGdtSize:WORD
>>> +EXTERNDEF gStmGdtPtr:WORD
>>> +
>>>
>>> MSR_IA32_MISC_ENABLE EQU 1A0h
>>> MSR_EFER EQU 0c0000080h
>>> @@ -40,13 +46,14 @@ MSR_EFER_XD EQU 0800h
>>> ;
>>> ; Constants relating to TXT_PROCESSOR_SMM_DESCRIPTOR ;
>>> -DSC_OFFSET EQU 0fb00h
>>> -DSC_GDTPTR EQU 48h
>>> -DSC_GDTSIZ EQU 50h
>>> -DSC_CS EQU 14h
>>> -DSC_DS EQU 16h
>>> -DSC_SS EQU 18h
>>> -DSC_OTHERSEG EQU 1ah
>>> +; DSC_OFFSET EQU 0fb00h
>>> +; DSC_GDTPTR EQU 48h
>>> +; DSC_GDTSIZ EQU 50h
>>> +;
>>> +DSC_CS EQU 14h
>>> +DSC_DS EQU 16h
>>> +DSC_SS EQU 18h
>>> +DSC_OTHERSEG EQU 1ah
>>> ;
>>> ; Constants relating to CPU State Save Area ; @@ -74,12 +81,12 @@
>>> _StmSmiEntryPoint:
>>> DW offset _StmGdtDesc - _StmSmiEntryPoint + 8000h ; bx = GdtDesc
>>> offset
>>> ; fix GDT descriptor
>>> DB 2eh, 0a1h ; mov ax, cs:[offset16]
>>> - DW DSC_OFFSET + DSC_GDTSIZ
>>> +gStmGdtSize DW ? ; DSC_OFFSET + DSC_GDTSIZ
>>> DB 48h ; dec ax
>>> DB 2eh
>>> mov [rdi], eax ; mov cs:[bx], ax
>>> DB 66h, 2eh, 0a1h ; mov eax, cs:[offset16]
>>> - DW DSC_OFFSET + DSC_GDTPTR
>>> +gStmGdtPtr DW ? ; DSC_OFFSET + DSC_GDTPTR
>>> DB 2eh
>>> mov [rdi + 2], ax ; mov cs:[bx + 2], eax
>>> DB 66h, 2eh
>>> @@ -178,7 +185,10 @@ Base:
>>> @LongMode: ; long mode (64-bit code) starts here
>>> mov rax, offset gStmSmiHandlerIdtr
>>> lidt fword ptr [rax]
>>> - lea ebx, [rdi + DSC_OFFSET]
>>> +
>>> + movzx rsi, word ptr [gStmPsdOffset] ; lea ebx, [rdi + DSC_OFFSET]
>>> + lea ebx, [rdi + rsi] ;
>>> +
>>> mov ax, [rbx + DSC_DS]
>>> mov ds, eax
>>> mov ax, [rbx + DSC_OTHERSEG]
>>> diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.nasm
>>> b/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.nasm
>>> index bcac643..df4c5a2 100644
>>> --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.nasm
>>> +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.nasm
>>> @@ -1,5 +1,7 @@
>>> ;------------------------------------------------------------------------------ ; ;
>>> Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
>>> +; Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR> ;
>>> ; This program and the accompanying materials ; are licensed and made
>>> available under the terms and conditions of the BSD License ; which
>>> accompanies this distribution. The full text of the license may be found at
>>> @@ -29,13 +31,14 @@ ; ; Constants relating to
>>> TXT_PROCESSOR_SMM_DESCRIPTOR ; -%define DSC_OFFSET 0xfb00 -
>>> %define DSC_GDTPTR 0x48 -%define DSC_GDTSIZ 0x50 -%define DSC_CS
>>> 0x14 -%define DSC_DS 0x16 -%define DSC_SS 0x18 -%define DSC_OTHERSEG
>>> 0x1a
>>> +; %define DSC_OFFSET 0xfb00
>>> +; %define DSC_GDTPTR 0x48
>>> +; %define DSC_GDTSIZ 0x50
>>> +;
>>> +%define DSC_CS 0x14
>>> +%define DSC_DS 0x16
>>> +%define DSC_SS 0x18
>>> +%define DSC_OTHERSEG 0x1a
>>> ;
>>> ; Constants relating to CPU State Save Area ; @@ -44,9 +47,9 @@
>>>
>>> %define PROTECT_MODE_CS 0x8
>>> %define PROTECT_MODE_DS 0x20
>>> -%define LONG_MODE_CS 0x38
>>> -%define TSS_SEGMENT 0x40
>>> -%define GDT_SIZE 0x50
>>> +%define LONG_MODE_CS 0x38
>>> +%define TSS_SEGMENT 0x40
>>> +%define GDT_SIZE 0x50
>>>
>>> extern ASM_PFX(SmiRendezvous)
>>> extern ASM_PFX(gStmSmiHandlerIdtr)
>>> @@ -61,6 +64,10 @@ global ASM_PFX(gcStmSmiHandlerTemplate) global
>>> ASM_PFX(gcStmSmiHandlerSize) global ASM_PFX(gcStmSmiHandlerOffset)
>>>
>>> +extern ASM_PFX(gStmPsdOffset)
>>> +global ASM_PFX(gStmGdtSize)
>>> +global ASM_PFX(gStmGdtPtr)
>>> +
>>> ASM_PFX(gStmSmbase) EQU StmSmbasePatch - 4
>>> ASM_PFX(gStmSmiStack) EQU StmSmiStackPatch - 4
>>> ASM_PFX(gStmSmiCr3) EQU StmSmiCr3Patch - 4
>>> @@ -73,10 +80,18 @@ BITS 16
>>> ASM_PFX(gcStmSmiHandlerTemplate):
>>> _StmSmiEntryPoint:
>>> mov bx, _StmGdtDesc - _StmSmiEntryPoint + 0x8000
>>> - mov ax,[cs:DSC_OFFSET + DSC_GDTSIZ]
>>> +
>>> + mov eax, ASM_PFX(gStmGdtSize) ; mov ax, [cs:DSC_OFFSET +
>>> DSC_GDTSIZ]
>>> + mov si, [cs:eax] ;
>>> + mov ax, [cs:si] ;
>>> +
>>> dec ax
>>> mov [cs:bx], ax
>>> - mov eax, [cs:DSC_OFFSET + DSC_GDTPTR]
>>> +
>>> + mov eax, ASM_PFX(gStmGdtPtr) ; mov eax, [cs:DSC_OFFSET +
>>> DSC_GDTPTR]
>>> + mov si, [cs:eax] ;
>>> + mov eax, [cs:si] ;
>>> +
>>> mov [cs:bx + 2], eax
>>> o32 lgdt [cs:bx] ; lgdt fword ptr cs:[bx]
>>> mov ax, PROTECT_MODE_CS
>>> @@ -166,7 +181,10 @@ Base:
>>> @LongMode: ; long mode (64-bit code) starts here
>>> mov rax, ASM_PFX(gStmSmiHandlerIdtr)
>>> lidt [rax]
>>> - lea ebx, [rdi + DSC_OFFSET]
>>> +
>>> + movzx rsi, word [ASM_PFX(gStmPsdOffset)] ; lea ebx, [rdi +
>>> DSC_OFFSET]
>>> + lea ebx, [rdi + rsi] ;
>>> +
>>> mov ax, [rbx + DSC_DS]
>>> mov ds, eax
>>> mov ax, [rbx + DSC_OTHERSEG]
>>> @@ -262,5 +280,8 @@ _StmSmiHandler:
>>> ; STM init finish
>>> jmp CommonHandler
>>>
>>> +ASM_PFX(gStmGdtSize) : RESW 1
>>> +ASM_PFX(gStmGdtPtr) : RESW 1
>>> +
>>> ASM_PFX(gcStmSmiHandlerSize) : DW $ - _StmSmiEntryPoint
>>> ASM_PFX(gcStmSmiHandlerOffset) : DW _StmSmiHandler -
>>> _StmSmiEntryPoint
>>> --
>>> 2.7.4
>>
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH v5 1/2] UefiCpuPkg/SmmCpuFeaturesLib: Use global variables to replace macros
2017-10-17 14:50 ` Duran, Leo
@ 2017-10-17 15:16 ` Paolo Bonzini
0 siblings, 0 replies; 30+ messages in thread
From: Paolo Bonzini @ 2017-10-17 15:16 UTC (permalink / raw)
To: Duran, Leo, Laszlo Ersek, edk2-devel@lists.01.org, Jiewen Yao
Cc: Ruiyu Ni, Michael D Kinney, Jordan Justen, Liming Gao
On 17/10/2017 16:50, Duran, Leo wrote:
> To me,
> - This proposed library function seems appropriate in the context of CPU features (i..e, this is not a hack)
> - I'd argue having to save & restore 512 "unused" bytes per SMI is significant overheard that can be avoided.
Can it be measured, and why is it not an issue for Intel?
Paolo
> - The proposed change is not intrusive not does it add significant amount of code.
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH v5 1/2] UefiCpuPkg/SmmCpuFeaturesLib: Use global variables to replace macros
2017-10-17 14:50 ` Yao, Jiewen
2017-10-17 15:14 ` Laszlo Ersek
@ 2017-10-17 16:30 ` Duran, Leo
1 sibling, 0 replies; 30+ messages in thread
From: Duran, Leo @ 2017-10-17 16:30 UTC (permalink / raw)
To: 'Yao, Jiewen'
Cc: edk2-devel@lists.01.org, Laszlo Ersek, Paolo Bonzini, Ni, Ruiyu,
Kinney, Michael D, Justen, Jordan L, Gao, Liming
> -----Original Message-----
> From: Yao, Jiewen [mailto:jiewen.yao@intel.com]
> Sent: Tuesday, October 17, 2017 9:51 AM
> To: Duran, Leo <leo.duran@amd.com>
> Cc: edk2-devel@lists.01.org; Laszlo Ersek <lersek@redhat.com>; Paolo
> Bonzini <pbonzini@redhat.com>; Ni, Ruiyu <ruiyu.ni@intel.com>; Kinney,
> Michael D <michael.d.kinney@intel.com>; Justen, Jordan L
> <jordan.l.justen@intel.com>; Gao, Liming <liming.gao@intel.com>
> Subject: Re: [PATCH v5 1/2] UefiCpuPkg/SmmCpuFeaturesLib: Use global
> variables to replace macros
>
> I think it is unnecessary. All intel CPU is using same offset. All amd CPU is
> using same offset. It can be identified easily by code.
> Adding a new API now is also an incompatible change because that requires
> all existing featurelib change to add a new API. We have lots of close source
> platform using its own featurelib.
>
> May I know what problem we are trying to resolve by adding a new API?
Yao,
The idea is to have PiSmmDxeSmm invoke the API to get the 'real' SAVE_STATE_AREA offset, which is different on Intel vs AMD.
But as Paolo points out, it really comes down to dealing with 0x200 bytes of padding (0xFC00->0xFE00).... which an instance of SmmCpuFeaturesLib may solve.
Anyway,
I'm going to look into leaving the definition of SRAM_SAVE_STATE_MAP_OFFSET as-is (@ 0xFC00), and see I can deal with the 0x200 bytes in the library.
And if that all works out, then we'll just drop this whole patch series!
Thanks,
Leo.
>
> thank you!
> Yao, Jiewen
>
>
> > 在 2017年10月17日，下午10:20，Duran, Leo <leo.duran@amd.com> 写
> 道：
> >
> > Yao, Lazlo, et al,
> >
> > For the SRAM_SAVE_STATE_MAP_OFFSET:
> > I propose returning the value by a function in SmmCpuFeaturesLib... Here's
> the rationale:
> > - The value is fixed per CPU architecture, so this qualifies as a CPU feature.
> > - The logic for CPU architecture detection would be in one place
> > (e.g., PiSmmCpuDxeSmm would call the library function)
> > - The OVMF and Quark instances of the library could just return the current
> (default) value, so no compatibility issues.
> >
> > if you agree with this is an acceptable solution, I will submit a revised patch-
> set to address just the SRAM_SAVE_STATE_MAP_OFFSET.
> > (BTW, I'm re-evaluating the changes submitted for the PSD offset, with
> > the goal of just using the default value and dropping those changes)
> >
> > Thanks,
> > Leo.
> >
> >> -----Original Message-----
> >> From: Duran, Leo
> >> Sent: Wednesday, October 11, 2017 2:46 PM
> >> To: edk2-devel@lists.01.org
> >> Cc: Duran, Leo <leo.duran@amd.com>; Jiewen Yao
> >> <jiewen.yao@intel.com>; Ruiyu Ni <ruiyu.ni@intel.com>; Michael D
> >> Kinney <michael.d.kinney@intel.com>; Jordan Justen
> >> <jordan.l.justen@intel.com>; Liming Gao <liming.gao@intel.com>
> >> Subject: [PATCH v5 1/2] UefiCpuPkg/SmmCpuFeaturesLib: Use global
> >> variables to replace macros
> >>
> >> Set global variables on Constructor function based on CPUID checks.
> >> The variables replace Intel macros to allow support on AMD x86 systems.
> >>
> >> Specifically, the replaced macros are:
> >> 1) SRAM_SAVE_STATE_MAP_OFFSET
> >> 2) TXT_SMM_PSD_OFFSET
> >>
> >> Cc: Jiewen Yao <jiewen.yao@intel.com>
> >> Cc: Ruiyu Ni <ruiyu.ni@intel.com>
> >> Cc: Michael D Kinney <michael.d.kinney@intel.com>
> >> Cc: Jordan Justen <jordan.l.justen@intel.com>
> >> Cc: Liming Gao <liming.gao@intel.com>
> >> Contributed-under: TianoCore Contribution Agreement 1.1
> >> Signed-off-by: Leo Duran <leo.duran@amd.com>
> >> ---
> >> .../Library/SmmCpuFeaturesLib/Ia32/SmiEntry.S | 28 ++++++----
> >> .../Library/SmmCpuFeaturesLib/Ia32/SmiEntry.asm | 29 +++++++----
> >> .../Library/SmmCpuFeaturesLib/Ia32/SmiEntry.nasm | 43
> ++++++++++++---
> >> -
> >> UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCommon.h | 48
> >> ++++++++++++++++++
> >> .../Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c | 59
> >> ++++++++++++++++++----
> >> .../SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf | 3 ++
> >> .../SmmCpuFeaturesLib/SmmCpuFeaturesLibStm.inf | 3 ++
> >> UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c | 39
> >> ++++++++++++--
> >> .../Library/SmmCpuFeaturesLib/X64/SmiEntry.S | 28 ++++++----
> >> .../Library/SmmCpuFeaturesLib/X64/SmiEntry.asm | 30 +++++++----
> >> .../Library/SmmCpuFeaturesLib/X64/SmiEntry.nasm | 47
> ++++++++++++---
> >> --
> >> 11 files changed, 282 insertions(+), 75 deletions(-) create mode
> >> 100644 UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCommon.h
> >>
> >> diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.S
> >> b/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.S
> >> index 4c0f8c8..c7b49d7 100644
> >> --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.S
> >> +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.S
> >> @@ -1,6 +1,8 @@
> >> #--------------------------------------------------------------------
> >> ----------
> >> #
> >> # Copyright (c) 2009 - 2016, Intel Corporation. All rights
> >> reserved.<BR>
> >> +# Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR> #
> >> # This program and the accompanying materials # are licensed and
> >> made available under the terms and conditions of the BSD License #
> >> which accompanies this distribution. The full text of the license
> >> may be found at @@ -28,6 +30,9 @@ ASM_GLOBAL
> ASM_PFX(gStmSmbase)
> >> ASM_GLOBAL
> >> ASM_PFX(gStmXdSupported) ASM_GLOBAL ASM_PFX(FeaturePcdGet
> >> (PcdCpuSmmStackGuard)) ASM_GLOBAL
> ASM_PFX(gStmSmiHandlerIdtr)
> >> +ASM_GLOBAL ASM_PFX(gStmPsdOffset)
> >> +ASM_GLOBAL ASM_PFX(gStmGdtSize)
> >> +ASM_GLOBAL ASM_PFX(gStmGdtPtr)
> >>
> >> .equ MSR_IA32_MISC_ENABLE, 0x1A0
> >> .equ MSR_EFER, 0xc0000080
> >> @@ -36,12 +41,13 @@ ASM_GLOBAL ASM_PFX(gStmSmiHandlerIdtr) #
> #
> >> Constants relating to TXT_PROCESSOR_SMM_DESCRIPTOR #
> >> -.equ DSC_OFFSET, 0xfb00
> >> -.equ DSC_GDTPTR, 0x48
> >> -.equ DSC_GDTSIZ, 0x50
> >> -.equ DSC_CS, 0x14
> >> -.equ DSC_DS, 0x16
> >> -.equ DSC_SS, 0x18
> >> +# .equ DSC_OFFSET, 0xfb00
> >> +# .equ DSC_GDTPTR, 0x48
> >> +# .equ DSC_GDTSIZ, 0x50
> >> +#
> >> +.equ DSC_CS, 0x14
> >> +.equ DSC_DS, 0x16
> >> +.equ DSC_SS, 0x18
> >> .equ DSC_OTHERSEG, 0x1A
> >>
> >> .equ PROTECT_MODE_CS, 0x08
> >> @@ -55,11 +61,11 @@ _StmSmiEntryPoint:
> >> .byte 0xbb # mov bx, imm16
> >> .word _StmGdtDesc - _StmSmiEntryPoint + 0x8000
> >> .byte 0x2e,0xa1 # mov ax, cs:[offset16]
> >> - .word DSC_OFFSET + DSC_GDTSIZ
> >> +ASM_PFX(gStmGdtSize): .space 2 # .word DSC_OFFSET +
> DSC_GDTSIZ
> >> decl %eax
> >> movl %eax, %cs:(%edi) # mov cs:[bx], ax
> >> .byte 0x66,0x2e,0xa1 # mov eax, cs:[offset16]
> >> - .word DSC_OFFSET + DSC_GDTPTR
> >> +ASM_PFX(gStmGdtPtr): .space 2 # .word DSC_OFFSET +
> DSC_GDTPTR
> >> movw %ax, %cs:2(%edi)
> >> movw %ax, %bp # ebp = GDT base
> >> .byte 0x66
> >> @@ -167,7 +173,11 @@ XdDone:
> >> movl %cr0, %ebx
> >> orl $0x080010023, %ebx # enable paging + WP + NE + MP + PE
> >> movl %ebx, %cr0
> >> - leal DSC_OFFSET(%edi),%ebx
> >> +
> >> + movl $ASM_PFX(gStmPsdOffset), %ebx # leal DSC_OFFSET(%edi),
> >> %ebx
> >> + movzxw (%ebx), %esi
> >> + leal (%edi, %esi), %ebx
> >> +
> >> movw DSC_DS(%ebx),%ax
> >> movl %eax, %ds
> >> movw DSC_OTHERSEG(%ebx),%ax
> >> diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.asm
> >> b/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.asm
> >> index 91dc1eb..4dbe276 100644
> >> --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.asm
> >> +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.asm
> >> @@ -1,5 +1,7 @@
> >> ;--------------------------------------------------------------------
> >> ---------- ; ; Copyright (c) 2009 - 2017, Intel Corporation. All
> >> rights reserved.<BR>
> >> +; Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR> ;
> >> ; This program and the accompanying materials ; are licensed and
> >> made available under the terms and conditions of the BSD License ;
> >> which accompanies this distribution. The full text of the license may be
> found at
> >> @@ -29,13 +31,14 @@ MSR_EFER_XD EQU 0800h
> >> ;
> >> ; Constants relating to TXT_PROCESSOR_SMM_DESCRIPTOR ;
> >> -DSC_OFFSET EQU 0fb00h
> >> -DSC_GDTPTR EQU 48h
> >> -DSC_GDTSIZ EQU 50h
> >> -DSC_CS EQU 14h
> >> -DSC_DS EQU 16h
> >> -DSC_SS EQU 18h
> >> -DSC_OTHERSEG EQU 1Ah
> >> +; DSC_OFFSET EQU 0fb00h
> >> +; DSC_GDTPTR EQU 48h
> >> +; DSC_GDTSIZ EQU 50h
> >> +;
> >> +DSC_CS EQU 14h
> >> +DSC_DS EQU 16h
> >> +DSC_SS EQU 18h
> >> +DSC_OTHERSEG EQU 1Ah
> >>
> >> PROTECT_MODE_CS EQU 08h
> >> PROTECT_MODE_DS EQU 20h
> >> @@ -54,6 +57,9 @@ EXTERNDEF gStmSmbase:DWORD
> >> EXTERNDEF gStmXdSupported:BYTE
> >> EXTERNDEF FeaturePcdGet (PcdCpuSmmStackGuard):BYTE
> >> EXTERNDEF gStmSmiHandlerIdtr:FWORD
> >> +EXTERNDEF gStmPsdOffset:WORD
> >> +EXTERNDEF gStmGdtSize:WORD
> >> +EXTERNDEF gStmGdtPtr:WORD
> >>
> >> .code
> >>
> >> @@ -63,11 +69,11 @@ _StmSmiEntryPoint:
> >> DB 0bbh ; mov bx, imm16
> >> DW offset _StmGdtDesc - _StmSmiEntryPoint + 8000h
> >> DB 2eh, 0a1h ; mov ax, cs:[offset16]
> >> - DW DSC_OFFSET + DSC_GDTSIZ
> >> +gStmGdtSize DW ? ; DSC_OFFSET + DSC_GDTSIZ
> >> dec eax
> >> mov cs:[edi], eax ; mov cs:[bx], ax
> >> DB 66h, 2eh, 0a1h ; mov eax, cs:[offset16]
> >> - DW DSC_OFFSET + DSC_GDTPTR
> >> +gStmGdtPtr DW ? ; DSC_OFFSET + DSC_GDTPTR
> >> mov cs:[edi + 2], ax ; mov cs:[bx + 2], eax
> >> mov bp, ax ; ebp = GDT base
> >> DB 66h
> >> @@ -174,7 +180,10 @@ gStmXdSupported DB 1
> >> mov ebx, cr0
> >> or ebx, 080010023h ; enable paging + WP + NE + MP + PE
> >> mov cr0, ebx
> >> - lea ebx, [edi + DSC_OFFSET]
> >> +
> >> + movzx esi, word ptr [gStmPsdOffset] ; lea ebx, [edi + DSC_OFFSET]
> >> + lea ebx, [edi + esi] ;
> >> +
> >> mov ax, [ebx + DSC_DS]
> >> mov ds, eax
> >> mov ax, [ebx + DSC_OTHERSEG]
> >> diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.nasm
> >> b/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.nasm
> >> index 00c0f067..023923a 100644
> >> --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.nasm
> >> +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.nasm
> >> @@ -1,5 +1,7 @@
> >> ;--------------------------------------------------------------------
> >> ---------- ; ; Copyright (c) 2016 - 2017, Intel Corporation. All
> >> rights reserved.<BR>
> >> +; Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR> ;
> >> ; This program and the accompanying materials ; are licensed and
> >> made available under the terms and conditions of the BSD License ;
> >> which accompanies this distribution. The full text of the license
> >> may be found at @@ -25,17 +27,18 @@ ; ; Constants relating to
> >> TXT_PROCESSOR_SMM_DESCRIPTOR ; -%define DSC_OFFSET 0xfb00 -
> %define
> >> DSC_GDTPTR 0x48 -%define DSC_GDTSIZ 0x50 -%define DSC_CS
> >> 0x14 -%define DSC_DS 0x16 -%define DSC_SS 0x18 -%define
> DSC_OTHERSEG
> >> 0x1a
> >> +; %define DSC_OFFSET 0xfb00
> >> +; %define DSC_GDTPTR 0x48
> >> +; %define DSC_GDTSIZ 0x50
> >> +;
> >> +%define DSC_CS 0x14
> >> +%define DSC_DS 0x16
> >> +%define DSC_SS 0x18
> >> +%define DSC_OTHERSEG 0x1a
> >>
> >> %define PROTECT_MODE_CS 0x8
> >> %define PROTECT_MODE_DS 0x20
> >> -%define TSS_SEGMENT 0x40
> >> +%define TSS_SEGMENT 0x40
> >>
> >> extern ASM_PFX(SmiRendezvous)
> >> extern ASM_PFX(FeaturePcdGet (PcdCpuSmmStackGuard)) @@ -51,6
> >> +54,10 @@ global ASM_PFX(gStmSmbase) global
> >> ASM_PFX(gStmXdSupported) extern ASM_PFX(gStmSmiHandlerIdtr)
> >>
> >> +extern ASM_PFX(gStmPsdOffset)
> >> +global ASM_PFX(gStmGdtSize)
> >> +global ASM_PFX(gStmGdtPtr)
> >> +
> >> ASM_PFX(gStmSmiCr3) EQU StmSmiCr3Patch - 4
> >> ASM_PFX(gStmSmiStack) EQU StmSmiStackPatch - 4
> >> ASM_PFX(gStmSmbase) EQU StmSmbasePatch - 4
> >> @@ -62,10 +69,18 @@ BITS 16
> >> ASM_PFX(gcStmSmiHandlerTemplate):
> >> _StmSmiEntryPoint:
> >> mov bx, _StmGdtDesc - _StmSmiEntryPoint + 0x8000
> >> - mov ax,[cs:DSC_OFFSET + DSC_GDTSIZ]
> >> +
> >> + mov eax, ASM_PFX(gStmGdtSize) ; mov ax, [cs:DSC_OFFSET +
> >> DSC_GDTSIZ]
> >> + mov si, [cs:eax] ;
> >> + mov ax, [cs:si] ;
> >> +
> >> dec ax
> >> mov [cs:bx], ax
> >> - mov eax, [cs:DSC_OFFSET + DSC_GDTPTR]
> >> +
> >> + mov eax, ASM_PFX(gStmGdtPtr) ; mov eax, [cs:DSC_OFFSET +
> >> DSC_GDTPTR]
> >> + mov si, [cs:eax] ;
> >> + mov eax, [cs:si] ;
> >> +
> >> mov [cs:bx + 2], eax
> >> mov ebp, eax ; ebp = GDT base
> >> o32 lgdt [cs:bx] ; lgdt fword ptr cs:[bx]
> >> @@ -166,7 +181,10 @@ StmXdSupportedPatch:
> >> mov ebx, cr0
> >> or ebx, 0x80010023 ; enable paging + WP + NE + MP + PE
> >> mov cr0, ebx
> >> - lea ebx, [edi + DSC_OFFSET]
> >> +
> >> + movzx esi, word [ASM_PFX(gStmPsdOffset)] ; lea ebx, [edi +
> >> DSC_OFFSET]
> >> + lea ebx, [edi + esi] ;
> >> +
> >> mov ax, [ebx + DSC_DS]
> >> mov ds, eax
> >> mov ax, [ebx + DSC_OTHERSEG]
> >> @@ -271,5 +289,8 @@ _StmSmiHandler:
> >> ; STM init finish
> >> jmp CommonHandler
> >>
> >> +ASM_PFX(gStmGdtSize) : RESW 1
> >> +ASM_PFX(gStmGdtPtr) : RESW 1
> >> +
> >> ASM_PFX(gcStmSmiHandlerSize) : DW $ - _StmSmiEntryPoint
> >> ASM_PFX(gcStmSmiHandlerOffset) : DW _StmSmiHandler -
> >> _StmSmiEntryPoint
> >> diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCommon.h
> >> b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCommon.h
> >> new file mode 100644
> >> index 0000000..78b3a5b
> >> --- /dev/null
> >> +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCommon.h
> >> @@ -0,0 +1,48 @@
> >> +/** @file
> >> + Common declarations
> >> +
> >> + Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>
> >> +
> >> + This program and the accompanying materials are licensed and made
> >> + available under the terms and conditions of the BSD License which
> >> + accompanies this distribution. The full text of the license may be
> >> + found at http://opensource.org/licenses/bsd-license.php.
> >> +
> >> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
> >> BASIS,
> >> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
> >> EXPRESS OR IMPLIED.
> >> +
> >> +**/
> >> +
> >> +#ifndef _SMM_COMMON_H_
> >> +#define _SMM_COMMON_H_
> >> +
> >> +#include <Register/Amd/Cpuid.h>
> >> +
> >> +//
> >> +// Definitions for AMD systems are based on contents of the // AMD64
> >> +Architecture Programmer's Manual // Volume 2: System Programming,
> >> +Section 10 System-Management Mode // #define
> >> +AMD_SMRAM_SAVE_STATE_MAP_OFFSET 0xfe00
> >> +#define AMD_SMM_PSD_OFFSET 0xfc00
> >> +
> >> +//
> >> +// External global variables for SMRAM offsets // extern UINT16
> >> +gSmramStateMapOffset; extern UINT16 gSmmPsdOffset;
> >> +
> >> +
> >> +/**
> >> + Determine if the standard CPU signature is "AuthenticAMD".
> >> +
> >> + @retval TRUE The CPU signature matches.
> >> + @retval FALSE The CPU signature does not match.
> >> +
> >> +**/
> >> +BOOLEAN
> >> +SmmStandardSignatureIsAuthenticAMD (
> >> + VOID
> >> + );
> >> +
> >> +#endif
> >> diff --git
> a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c
> >> b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c
> >> index 2d2bc6d..1c12095 100644
> >> --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c
> >> +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c
> >> @@ -1,14 +1,16 @@
> >> /** @file
> >> -The CPU specific programming for PiSmmCpuDxeSmm module.
> >> + The CPU specific programming for PiSmmCpuDxeSmm module.
> >>
> >> -Copyright (c) 2010 - 2016, Intel Corporation. All rights
> >> reserved.<BR> -This program and the accompanying materials -are
> >> licensed and made available under the terms and conditions of the BSD
> >> License -which accompanies this distribution. The full text of the
> >> license may be found at -
> >> http://opensource.org/licenses/bsd-license.php
> >> + Copyright (c) 2010 - 2016, Intel Corporation. All rights
> >> + reserved.<BR> Copyright (c) 2017, AMD Incorporated. All rights
> >> + reserved.<BR>
> >>
> >> -THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
> >> BASIS, -WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND,
> EITHER
> >> EXPRESS OR IMPLIED.
> >> + This program and the accompanying materials are licensed and made
> >> + available under the terms and conditions of the BSD License which
> >> + accompanies this distribution. The full text of the license may be
> >> + found at http://opensource.org/licenses/bsd-license.php
> >> +
> >> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
> >> BASIS,
> >> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
> >> EXPRESS OR IMPLIED.
> >>
> >> **/
> >>
> >> @@ -22,6 +24,8 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF
> ANY KIND,
> >> EITHER EXPRESS OR IMPLIED.
> >> #include <Register/Cpuid.h>
> >> #include <Register/SmramSaveStateMap.h>
> >>
> >> +#include "SmmCommon.h"
> >> +
> >> //
> >> // Machine Specific Registers (MSRs)
> >> //
> >> @@ -41,6 +45,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF
> ANY KIND,
> >> EITHER EXPRESS OR IMPLIED.
> >> #define SMM_FEATURES_LIB_IA32_MCA_CAP 0x17D
> >> #define SMM_CODE_ACCESS_CHK_BIT BIT58
> >>
> >> +
> >> /**
> >> Internal worker function that is called to complete CPU initialization at
> the
> >> end of SmmCpuFeaturesInitializeProcessor().
> >> @@ -77,6 +82,13 @@ BOOLEAN mNeedConfigureMtrrs = TRUE; //
> BOOLEAN
> >> *mSmrrEnabled;
> >>
> >> +//
> >> +// Set default value for SMRAM offset // from
> >> +<Register/SmramSaveStateMap.h> //
> >> +UINT16 gSmramStateMapOffset =
> SMRAM_SAVE_STATE_MAP_OFFSET;
> >> +
> >> +
> >> /**
> >> The constructor function
> >>
> >> @@ -99,6 +111,13 @@ SmmCpuFeaturesLibConstructor (
> >> UINTN ModelId;
> >>
> >> //
> >> + // Override SMRAM offset for AMD
> >> + //
> >> + if (SmmStandardSignatureIsAuthenticAMD ()) {
> >> + gSmramStateMapOffset =
> AMD_SMRAM_SAVE_STATE_MAP_OFFSET; }
> >> +
> >> + //
> >> // Retrieve CPU Family and Model
> >> //
> >> AsmCpuid (CPUID_VERSION_INFO, &RegEax, NULL, NULL, &RegEdx);
> @@ -
> >> 224,7 +243,7 @@ SmmCpuFeaturesInitializeProcessor (
> >> //
> >> // Configure SMBASE.
> >> //
> >> - CpuState = (SMRAM_SAVE_STATE_MAP
> >> *)(UINTN)(SMM_DEFAULT_SMBASE +
> >> SMRAM_SAVE_STATE_MAP_OFFSET);
> >> + CpuState = (SMRAM_SAVE_STATE_MAP
> >> *)(UINTN)(SMM_DEFAULT_SMBASE +
> >> + gSmramStateMapOffset);
> >> CpuState->x86.SMBASE = (UINT32)CpuHotPlugData-
> >SmBase[CpuIndex];
> >>
> >> //
> >> @@ -630,3 +649,25 @@ SmmCpuFeaturesAllocatePageTableMemory (
> >> return NULL;
> >> }
> >>
> >> +
> >> +/**
> >> + Determine if the standard CPU signature is "AuthenticAMD".
> >> +
> >> + @retval TRUE The CPU signature matches.
> >> + @retval FALSE The CPU signature does not match.
> >> +
> >> +**/
> >> +BOOLEAN
> >> +SmmStandardSignatureIsAuthenticAMD (
> >> + VOID
> >> + )
> >> +{
> >> + UINT32 RegEbx;
> >> + UINT32 RegEcx;
> >> + UINT32 RegEdx;
> >> +
> >> + AsmCpuid (CPUID_SIGNATURE, NULL, &RegEbx, &RegEcx, &RegEdx);
> >> + return (RegEbx == CPUID_SIGNATURE_AUTHENTIC_AMD_EBX &&
> >> + RegEcx == CPUID_SIGNATURE_AUTHENTIC_AMD_ECX &&
> >> + RegEdx == CPUID_SIGNATURE_AUTHENTIC_AMD_EDX);
> >> +}
> >> diff --git
> >> a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf
> >> b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf
> >> index 77908b0..6a39d4b 100644
> >> --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf
> >> +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf
> >> @@ -2,6 +2,8 @@
> >> # The CPU specific programming for PiSmmCpuDxeSmm module.
> >> #
> >> # Copyright (c) 2009 - 2016, Intel Corporation. All rights
> >> reserved.<BR>
> >> +# Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR> #
> >> # This program and the accompanying materials # are licensed and
> >> made available under the terms and conditions of the BSD License #
> >> which accompanies this distribution. The full text of the license
> >> may be found at @@ -24,6 +26,7 @@
> >>
> >> [Sources]
> >> SmmCpuFeaturesLib.c
> >> + SmmCommon.h
> >> SmmCpuFeaturesLibNoStm.c
> >>
> >> [Packages]
> >> diff --git
> >> a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibStm.inf
> >> b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibStm.inf
> >> index db8dcdc..a76bed6 100644
> >> ---
> a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibStm.inf
> >> +++
> b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibStm.inf
> >> @@ -3,6 +3,8 @@
> >> # is included.
> >> #
> >> # Copyright (c) 2009 - 2016, Intel Corporation. All rights
> >> reserved.<BR>
> >> +# Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR> #
> >> # This program and the accompanying materials # are licensed and
> >> made available under the terms and conditions of the BSD License #
> >> which accompanies this distribution. The full text of the license
> >> may be found at @@ -25,6 +27,7 @@
> >>
> >> [Sources]
> >> SmmCpuFeaturesLib.c
> >> + SmmCommon.h
> >> SmmStm.c
> >> SmmStm.h
> >>
> >> diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c
> >> b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c
> >> index 45015b8..5f7c3db 100644
> >> --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c
> >> +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c
> >> @@ -2,6 +2,8 @@
> >> SMM STM support functions
> >>
> >> Copyright (c) 2015 - 2017, Intel Corporation. All rights
> >> reserved.<BR>
> >> + Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>
> >> +
> >> This program and the accompanying materials
> >> are licensed and made available under the terms and conditions of
> >> the BSD License
> >> which accompanies this distribution. The full text of the license
> >> may be found at @@ -28,6 +30,8 @@ #include <Protocol/MpService.h>
> >>
> >> #include "SmmStm.h"
> >> +#include "SmmCommon.h"
> >> +
> >>
> >> #define TXT_EVTYPE_BASE 0x400
> >> #define TXT_EVTYPE_STM_HASH (TXT_EVTYPE_BASE + 14)
> >> @@ -97,6 +101,20 @@ extern volatile UINT8
> gcStmSmiHandlerTemplate[];
> >> extern CONST UINT16 gcStmSmiHandlerSize;
> >> extern UINT16 gcStmSmiHandlerOffset;
> >> extern BOOLEAN gStmXdSupported;
> >> +extern UINT16 gStmGdtSize;
> >> +extern UINT16 gStmGdtPtr;
> >> +
> >> +//
> >> +// Constants relating to TXT_PROCESSOR_SMM_DESCRIPTOR //
> >> +#define TXT_PSD_GDTPTR 0x48
> >> +#define TXT_PSD_GDTSIZE 0x50
> >> +
> >> +//
> >> +// Set default value for PSD offset in SMRAM // from
> >> +<Register/StmApi.h> //
> >> +UINT16 gStmPsdOffset = TXT_SMM_PSD_OFFSET;
> >>
> >> //
> >> // Variables used by SMI Handler
> >> @@ -145,6 +163,19 @@ SmmCpuFeaturesLibStmConstructor (
> >> ASSERT_EFI_ERROR (Status);
> >>
> >> //
> >> + // Override PSD offset for AMD
> >> + //
> >> + if (SmmStandardSignatureIsAuthenticAMD ()) {
> >> + gStmPsdOffset = AMD_SMM_PSD_OFFSET; }
> >> +
> >> + //
> >> + // Initialize STM global variables associated with SMI Handler //
> >> + gStmGdtSize = gStmPsdOffset + TXT_PSD_GDTSIZE; gStmGdtPtr =
> >> + gStmPsdOffset + TXT_PSD_GDTPTR;
> >> +
> >> + //
> >> // Lookup the MP Services Protocol
> >> //
> >> Status = gBS->LocateProtocol (
> >> @@ -276,8 +307,8 @@ SmmCpuFeaturesInstallSmiHandler (
> >> UINT32 RegEdx;
> >> EFI_PROCESSOR_INFORMATION ProcessorInfo;
> >>
> >> - CopyMem ((VOID *)((UINTN)SmBase + TXT_SMM_PSD_OFFSET),
> &gcStmPsd,
> >> sizeof (gcStmPsd));
> >> - Psd = (TXT_PROCESSOR_SMM_DESCRIPTOR *)(VOID
> *)((UINTN)SmBase +
> >> TXT_SMM_PSD_OFFSET);
> >> + CopyMem ((VOID *)((UINTN)SmBase + gStmPsdOffset), &gcStmPsd,
> >> sizeof
> >> + (gcStmPsd)); Psd = (TXT_PROCESSOR_SMM_DESCRIPTOR *)(VOID
> >> + *)((UINTN)SmBase + gStmPsdOffset);
> >> Psd->SmmGdtPtr = GdtBase;
> >> Psd->SmmGdtSize = (UINT32)GdtSize;
> >>
> >> @@ -416,7 +447,7 @@ SmmEndOfDxeEventNotify (
> >> }
> >>
> >> for (Index = 0; Index < gSmst->NumberOfCpus; Index++) {
> >> - Psd = (TXT_PROCESSOR_SMM_DESCRIPTOR *)((UINTN)gSmst-
> >>> CpuSaveState[Index] - SMRAM_SAVE_STATE_MAP_OFFSET +
> >> TXT_SMM_PSD_OFFSET);
> >> + Psd = (TXT_PROCESSOR_SMM_DESCRIPTOR
> >> + *)((UINTN)gSmst->CpuSaveState[Index] - gSmramStateMapOffset +
> >> + gStmPsdOffset);
> >> DEBUG ((DEBUG_INFO, "Index=%d Psd=%p Rsdp=%p\n", Index, Psd,
> >> Rsdp));
> >> Psd->AcpiRsdp = (UINT64)(UINTN)Rsdp;
> >> }
> >> @@ -1266,7 +1297,7 @@ NotifyStmResourceChange (
> >> TXT_PROCESSOR_SMM_DESCRIPTOR *Psd;
> >>
> >> for (Index = 0; Index < gSmst->NumberOfCpus; Index++) {
> >> - Psd = (TXT_PROCESSOR_SMM_DESCRIPTOR *)((UINTN)gSmst-
> >>> CpuSaveState[Index] - SMRAM_SAVE_STATE_MAP_OFFSET +
> >> TXT_SMM_PSD_OFFSET);
> >> + Psd = (TXT_PROCESSOR_SMM_DESCRIPTOR
> >> + *)((UINTN)gSmst->CpuSaveState[Index] - gSmramStateMapOffset +
> >> + gStmPsdOffset);
> >> Psd->BiosHwResourceRequirementsPtr =
> (UINT64)(UINTN)StmResource;
> >> }
> >> return ;
> >> diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.S
> >> b/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.S
> >> index 1f9f91c..5f3386a 100644
> >> --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.S
> >> +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.S
> >> @@ -1,6 +1,8 @@
> >> #--------------------------------------------------------------------
> >> ----------
> >> #
> >> # Copyright (c) 2009 - 2016, Intel Corporation. All rights
> >> reserved.<BR>
> >> +# Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR> #
> >> # This program and the accompanying materials # are licensed and
> >> made available under the terms and conditions of the BSD License #
> >> which accompanies this distribution. The full text of the license
> >> may be found at @@ -27,6 +29,9 @@ ASM_GLOBAL
> ASM_PFX(gStmSmiStack)
> >> ASM_GLOBAL
> >> ASM_PFX(gStmSmbase) ASM_GLOBAL ASM_PFX(gStmXdSupported)
> ASM_GLOBAL
> >> ASM_PFX(gStmSmiHandlerIdtr)
> >> +ASM_GLOBAL ASM_PFX(gStmPsdOffset)
> >> +ASM_GLOBAL ASM_PFX(gStmGdtSize)
> >> +ASM_GLOBAL ASM_PFX(gStmGdtPtr)
> >>
> >> .equ MSR_IA32_MISC_ENABLE, 0x1A0
> >> .equ MSR_EFER, 0xc0000080
> >> @@ -35,12 +40,13 @@ ASM_GLOBAL ASM_PFX(gStmSmiHandlerIdtr) #
> #
> >> Constants relating to TXT_PROCESSOR_SMM_DESCRIPTOR #
> >> -.equ DSC_OFFSET, 0xfb00
> >> -.equ DSC_GDTPTR, 0x48
> >> -.equ DSC_GDTSIZ, 0x50
> >> -.equ DSC_CS, 0x14
> >> -.equ DSC_DS, 0x16
> >> -.equ DSC_SS, 0x18
> >> +# .equ DSC_OFFSET, 0xfb00
> >> +# .equ DSC_GDTPTR, 0x48
> >> +# .equ DSC_GDTSIZ, 0x50
> >> +#
> >> +.equ DSC_CS, 0x14
> >> +.equ DSC_DS, 0x16
> >> +.equ DSC_SS, 0x18
> >> .equ DSC_OTHERSEG, 0x1a
> >> #
> >> # Constants relating to CPU State Save Area @@ -71,12 +77,12 @@
> >> _StmSmiEntryPoint:
> >> # fix GDT descriptor
> >> #
> >> .byte 0x2e,0xa1 # mov ax, cs:[offset16]
> >> - .word DSC_OFFSET + DSC_GDTSIZ
> >> +ASM_PFX(gStmGdtSize): .space 2 # .word DSC_OFFSET +
> DSC_GDTSIZ
> >> .byte 0x48 # dec ax
> >> .byte 0x2e
> >> movl %eax, (%rdi) # mov cs:[bx], ax
> >> .byte 0x66,0x2e,0xa1 # mov eax, cs:[offset16]
> >> - .word DSC_OFFSET + DSC_GDTPTR
> >> +ASM_PFX(gStmGdtPtr): .space 2 # .word DSC_OFFSET +
> DSC_GDTPTR
> >> .byte 0x2e
> >> movw %ax, 2(%rdi)
> >> .byte 0x66,0x2e
> >> @@ -183,7 +189,11 @@ Base:
> >> LongMode: # long mode (64-bit code) starts here
> >> movabsq $ASM_PFX(gStmSmiHandlerIdtr), %rax
> >> lidt (%rax)
> >> - lea (DSC_OFFSET)(%rdi), %ebx
> >> +
> >> + movl $ASM_PFX(gStmPsdOffset), %ebx # lea (DSC_OFFSET)(%rdi),
> >> %ebx
> >> + movzxw (%ebx), %rsi
> >> + leal (%rdi, %rsi), %ebx
> >> +
> >> movw DSC_DS(%rbx), %ax
> >> movl %eax,%ds
> >> movw DSC_OTHERSEG(%rbx), %ax
> >> diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.asm
> >> b/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.asm
> >> index ad51e07..10913df 100644
> >> --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.asm
> >> +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.asm
> >> @@ -1,5 +1,7 @@
> >> ;--------------------------------------------------------------------
> >> ---------- ; ; Copyright (c) 2009 - 2016, Intel Corporation. All
> >> rights reserved.<BR>
> >> +; Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR> ;
> >> ; This program and the accompanying materials ; are licensed and
> >> made available under the terms and conditions of the BSD License ;
> >> which accompanies this distribution. The full text of the license may be
> found at
> >> @@ -32,6 +34,10 @@ EXTERNDEF gStmSmiStack:DWORD
> >> EXTERNDEF gStmSmbase:DWORD
> >> EXTERNDEF gStmXdSupported:BYTE
> >> EXTERNDEF gStmSmiHandlerIdtr:FWORD
> >> +EXTERNDEF gStmPsdOffset:WORD
> >> +EXTERNDEF gStmGdtSize:WORD
> >> +EXTERNDEF gStmGdtPtr:WORD
> >> +
> >>
> >> MSR_IA32_MISC_ENABLE EQU 1A0h
> >> MSR_EFER EQU 0c0000080h
> >> @@ -40,13 +46,14 @@ MSR_EFER_XD EQU 0800h
> >> ;
> >> ; Constants relating to TXT_PROCESSOR_SMM_DESCRIPTOR ;
> >> -DSC_OFFSET EQU 0fb00h
> >> -DSC_GDTPTR EQU 48h
> >> -DSC_GDTSIZ EQU 50h
> >> -DSC_CS EQU 14h
> >> -DSC_DS EQU 16h
> >> -DSC_SS EQU 18h
> >> -DSC_OTHERSEG EQU 1ah
> >> +; DSC_OFFSET EQU 0fb00h
> >> +; DSC_GDTPTR EQU 48h
> >> +; DSC_GDTSIZ EQU 50h
> >> +;
> >> +DSC_CS EQU 14h
> >> +DSC_DS EQU 16h
> >> +DSC_SS EQU 18h
> >> +DSC_OTHERSEG EQU 1ah
> >> ;
> >> ; Constants relating to CPU State Save Area ; @@ -74,12 +81,12 @@
> >> _StmSmiEntryPoint:
> >> DW offset _StmGdtDesc - _StmSmiEntryPoint + 8000h ; bx = GdtDesc
> >> offset
> >> ; fix GDT descriptor
> >> DB 2eh, 0a1h ; mov ax, cs:[offset16]
> >> - DW DSC_OFFSET + DSC_GDTSIZ
> >> +gStmGdtSize DW ? ; DSC_OFFSET + DSC_GDTSIZ
> >> DB 48h ; dec ax
> >> DB 2eh
> >> mov [rdi], eax ; mov cs:[bx], ax
> >> DB 66h, 2eh, 0a1h ; mov eax, cs:[offset16]
> >> - DW DSC_OFFSET + DSC_GDTPTR
> >> +gStmGdtPtr DW ? ; DSC_OFFSET + DSC_GDTPTR
> >> DB 2eh
> >> mov [rdi + 2], ax ; mov cs:[bx + 2], eax
> >> DB 66h, 2eh
> >> @@ -178,7 +185,10 @@ Base:
> >> @LongMode: ; long mode (64-bit code) starts here
> >> mov rax, offset gStmSmiHandlerIdtr
> >> lidt fword ptr [rax]
> >> - lea ebx, [rdi + DSC_OFFSET]
> >> +
> >> + movzx rsi, word ptr [gStmPsdOffset] ; lea ebx, [rdi + DSC_OFFSET]
> >> + lea ebx, [rdi + rsi] ;
> >> +
> >> mov ax, [rbx + DSC_DS]
> >> mov ds, eax
> >> mov ax, [rbx + DSC_OTHERSEG]
> >> diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.nasm
> >> b/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.nasm
> >> index bcac643..df4c5a2 100644
> >> --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.nasm
> >> +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.nasm
> >> @@ -1,5 +1,7 @@
> >> ;--------------------------------------------------------------------
> >> ---------- ; ; Copyright (c) 2016 - 2017, Intel Corporation. All
> >> rights reserved.<BR>
> >> +; Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR> ;
> >> ; This program and the accompanying materials ; are licensed and
> >> made available under the terms and conditions of the BSD License ;
> >> which accompanies this distribution. The full text of the license
> >> may be found at @@ -29,13 +31,14 @@ ; ; Constants relating to
> >> TXT_PROCESSOR_SMM_DESCRIPTOR ; -%define DSC_OFFSET 0xfb00 -
> %define
> >> DSC_GDTPTR 0x48 -%define DSC_GDTSIZ 0x50 -%define DSC_CS
> >> 0x14 -%define DSC_DS 0x16 -%define DSC_SS 0x18 -%define
> DSC_OTHERSEG
> >> 0x1a
> >> +; %define DSC_OFFSET 0xfb00
> >> +; %define DSC_GDTPTR 0x48
> >> +; %define DSC_GDTSIZ 0x50
> >> +;
> >> +%define DSC_CS 0x14
> >> +%define DSC_DS 0x16
> >> +%define DSC_SS 0x18
> >> +%define DSC_OTHERSEG 0x1a
> >> ;
> >> ; Constants relating to CPU State Save Area ; @@ -44,9 +47,9 @@
> >>
> >> %define PROTECT_MODE_CS 0x8
> >> %define PROTECT_MODE_DS 0x20
> >> -%define LONG_MODE_CS 0x38
> >> -%define TSS_SEGMENT 0x40
> >> -%define GDT_SIZE 0x50
> >> +%define LONG_MODE_CS 0x38
> >> +%define TSS_SEGMENT 0x40
> >> +%define GDT_SIZE 0x50
> >>
> >> extern ASM_PFX(SmiRendezvous)
> >> extern ASM_PFX(gStmSmiHandlerIdtr)
> >> @@ -61,6 +64,10 @@ global ASM_PFX(gcStmSmiHandlerTemplate) global
> >> ASM_PFX(gcStmSmiHandlerSize) global
> ASM_PFX(gcStmSmiHandlerOffset)
> >>
> >> +extern ASM_PFX(gStmPsdOffset)
> >> +global ASM_PFX(gStmGdtSize)
> >> +global ASM_PFX(gStmGdtPtr)
> >> +
> >> ASM_PFX(gStmSmbase) EQU StmSmbasePatch - 4
> >> ASM_PFX(gStmSmiStack) EQU StmSmiStackPatch - 4
> >> ASM_PFX(gStmSmiCr3) EQU StmSmiCr3Patch - 4
> >> @@ -73,10 +80,18 @@ BITS 16
> >> ASM_PFX(gcStmSmiHandlerTemplate):
> >> _StmSmiEntryPoint:
> >> mov bx, _StmGdtDesc - _StmSmiEntryPoint + 0x8000
> >> - mov ax,[cs:DSC_OFFSET + DSC_GDTSIZ]
> >> +
> >> + mov eax, ASM_PFX(gStmGdtSize) ; mov ax, [cs:DSC_OFFSET +
> >> DSC_GDTSIZ]
> >> + mov si, [cs:eax] ;
> >> + mov ax, [cs:si] ;
> >> +
> >> dec ax
> >> mov [cs:bx], ax
> >> - mov eax, [cs:DSC_OFFSET + DSC_GDTPTR]
> >> +
> >> + mov eax, ASM_PFX(gStmGdtPtr) ; mov eax, [cs:DSC_OFFSET +
> >> DSC_GDTPTR]
> >> + mov si, [cs:eax] ;
> >> + mov eax, [cs:si] ;
> >> +
> >> mov [cs:bx + 2], eax
> >> o32 lgdt [cs:bx] ; lgdt fword ptr cs:[bx]
> >> mov ax, PROTECT_MODE_CS
> >> @@ -166,7 +181,10 @@ Base:
> >> @LongMode: ; long mode (64-bit code) starts here
> >> mov rax, ASM_PFX(gStmSmiHandlerIdtr)
> >> lidt [rax]
> >> - lea ebx, [rdi + DSC_OFFSET]
> >> +
> >> + movzx rsi, word [ASM_PFX(gStmPsdOffset)] ; lea ebx, [rdi +
> >> DSC_OFFSET]
> >> + lea ebx, [rdi + rsi] ;
> >> +
> >> mov ax, [rbx + DSC_DS]
> >> mov ds, eax
> >> mov ax, [rbx + DSC_OTHERSEG]
> >> @@ -262,5 +280,8 @@ _StmSmiHandler:
> >> ; STM init finish
> >> jmp CommonHandler
> >>
> >> +ASM_PFX(gStmGdtSize) : RESW 1
> >> +ASM_PFX(gStmGdtPtr) : RESW 1
> >> +
> >> ASM_PFX(gcStmSmiHandlerSize) : DW $ - _StmSmiEntryPoint
> >> ASM_PFX(gcStmSmiHandlerOffset) : DW _StmSmiHandler -
> >> _StmSmiEntryPoint
> >> --
> >> 2.7.4
> >
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH v5 1/2] UefiCpuPkg/SmmCpuFeaturesLib: Use global variables to replace macros
2017-10-17 15:14 ` Laszlo Ersek
@ 2017-10-17 16:40 ` Duran, Leo
2017-10-18 1:50 ` Yao, Jiewen
1 sibling, 0 replies; 30+ messages in thread
From: Duran, Leo @ 2017-10-17 16:40 UTC (permalink / raw)
To: 'Laszlo Ersek', Yao, Jiewen
Cc: edk2-devel@lists.01.org, Paolo Bonzini, Ni, Ruiyu,
Kinney, Michael D, Justen, Jordan L, Gao, Liming
> -----Original Message-----
> From: Laszlo Ersek [mailto:lersek@redhat.com]
> Sent: Tuesday, October 17, 2017 10:15 AM
> To: Yao, Jiewen <jiewen.yao@intel.com>; Duran, Leo
> <leo.duran@amd.com>
> Cc: edk2-devel@lists.01.org; Paolo Bonzini <pbonzini@redhat.com>; Ni,
> Ruiyu <ruiyu.ni@intel.com>; Kinney, Michael D
> <michael.d.kinney@intel.com>; Justen, Jordan L
> <jordan.l.justen@intel.com>; Gao, Liming <liming.gao@intel.com>
> Subject: Re: [PATCH v5 1/2] UefiCpuPkg/SmmCpuFeaturesLib: Use global
> variables to replace macros
>
> On 10/17/17 16:50, Yao, Jiewen wrote:
> > I think it is unnecessary. All intel CPU is using same offset. All amd CPU is
> using same offset. It can be identified easily by code.
> > Adding a new API now is also an incompatible change because that requires
> all existing featurelib change to add a new API. We have lots of close source
> platform using its own featurelib.
> >
> > May I know what problem we are trying to resolve by adding a new API?
>
> QEMU (and hence OVMF) uses the AMD save state map even when it
> emulates Intel CPUs.
>
> The reason is that the Intel SDM does not specify the Intel save state map in
> sufficient detail (for emulation by QEMU), while the AMD spec does. So, as
> an emulation target, only the AMD one is implementable in QEMU (and
> supportable in OVMF), regardless of whether QEMU reports the virtual CPU
> manufacturer as Intel vs. AMD.
>
> If PiSmmCpuDxeSmm used a CPUID check, saw "Intel" as manufacturer, and
> then used the Intel definition of the save state map, then
> PiSmmCpuDxeSmm would break on QEMU / as part of OVMF.
>
Lazlo,
Agreed... Which is why I proposed having PiSmmCpuDxeSmm invoke the library API instead of doing the check on its own.
And since OVMF has its instance of the library, then you should be fine.
But anyway,
I'm looking at dropping this whole patch series, if an instance of SmmCpuFeaturesLib can deal with the offset issues.
Thanks,
Leo.
> Thanks,
> Laszlo
>
> >
> >
> > thank you!
> > Yao, Jiewen
> >
> >
> >> 在 2017年10月17日，下午10:20，Duran, Leo <leo.duran@amd.com>
> 写道：
> >>
> >> Yao, Lazlo, et al,
> >>
> >> For the SRAM_SAVE_STATE_MAP_OFFSET:
> >> I propose returning the value by a function in SmmCpuFeaturesLib...
> Here's the rationale:
> >> - The value is fixed per CPU architecture, so this qualifies as a CPU feature.
> >> - The logic for CPU architecture detection would be in one place
> >> (e.g., PiSmmCpuDxeSmm would call the library function)
> >> - The OVMF and Quark instances of the library could just return the
> current (default) value, so no compatibility issues.
> >>
> >> if you agree with this is an acceptable solution, I will submit a revised
> patch-set to address just the SRAM_SAVE_STATE_MAP_OFFSET.
> >> (BTW, I'm re-evaluating the changes submitted for the PSD offset,
> >> with the goal of just using the default value and dropping those
> >> changes)
> >>
> >> Thanks,
> >> Leo.
> >>
> >>> -----Original Message-----
> >>> From: Duran, Leo
> >>> Sent: Wednesday, October 11, 2017 2:46 PM
> >>> To: edk2-devel@lists.01.org
> >>> Cc: Duran, Leo <leo.duran@amd.com>; Jiewen Yao
> >>> <jiewen.yao@intel.com>; Ruiyu Ni <ruiyu.ni@intel.com>; Michael D
> >>> Kinney <michael.d.kinney@intel.com>; Jordan Justen
> >>> <jordan.l.justen@intel.com>; Liming Gao <liming.gao@intel.com>
> >>> Subject: [PATCH v5 1/2] UefiCpuPkg/SmmCpuFeaturesLib: Use global
> >>> variables to replace macros
> >>>
> >>> Set global variables on Constructor function based on CPUID checks.
> >>> The variables replace Intel macros to allow support on AMD x86 systems.
> >>>
> >>> Specifically, the replaced macros are:
> >>> 1) SRAM_SAVE_STATE_MAP_OFFSET
> >>> 2) TXT_SMM_PSD_OFFSET
> >>>
> >>> Cc: Jiewen Yao <jiewen.yao@intel.com>
> >>> Cc: Ruiyu Ni <ruiyu.ni@intel.com>
> >>> Cc: Michael D Kinney <michael.d.kinney@intel.com>
> >>> Cc: Jordan Justen <jordan.l.justen@intel.com>
> >>> Cc: Liming Gao <liming.gao@intel.com>
> >>> Contributed-under: TianoCore Contribution Agreement 1.1
> >>> Signed-off-by: Leo Duran <leo.duran@amd.com>
> >>> ---
> >>> .../Library/SmmCpuFeaturesLib/Ia32/SmiEntry.S | 28 ++++++----
> >>> .../Library/SmmCpuFeaturesLib/Ia32/SmiEntry.asm | 29 +++++++----
> >>> .../Library/SmmCpuFeaturesLib/Ia32/SmiEntry.nasm | 43
> ++++++++++++---
> >>> -
> >>> UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCommon.h | 48
> >>> ++++++++++++++++++
> >>> .../Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c | 59
> >>> ++++++++++++++++++----
> >>> .../SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf | 3 ++
> >>> .../SmmCpuFeaturesLib/SmmCpuFeaturesLibStm.inf | 3 ++
> >>> UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c | 39
> >>> ++++++++++++--
> >>> .../Library/SmmCpuFeaturesLib/X64/SmiEntry.S | 28 ++++++----
> >>> .../Library/SmmCpuFeaturesLib/X64/SmiEntry.asm | 30 +++++++----
> >>> .../Library/SmmCpuFeaturesLib/X64/SmiEntry.nasm | 47
> ++++++++++++---
> >>> --
> >>> 11 files changed, 282 insertions(+), 75 deletions(-) create mode
> >>> 100644 UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCommon.h
> >>>
> >>> diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.S
> >>> b/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.S
> >>> index 4c0f8c8..c7b49d7 100644
> >>> --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.S
> >>> +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.S
> >>> @@ -1,6 +1,8 @@
> >>> #-------------------------------------------------------------------
> >>> -----------
> >>> #
> >>> # Copyright (c) 2009 - 2016, Intel Corporation. All rights
> >>> reserved.<BR>
> >>> +# Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR> #
> >>> # This program and the accompanying materials # are licensed and
> >>> made available under the terms and conditions of the BSD License #
> >>> which accompanies this distribution. The full text of the license
> >>> may be found at @@ -28,6 +30,9 @@ ASM_GLOBAL
> ASM_PFX(gStmSmbase)
> >>> ASM_GLOBAL
> >>> ASM_PFX(gStmXdSupported) ASM_GLOBAL ASM_PFX(FeaturePcdGet
> >>> (PcdCpuSmmStackGuard)) ASM_GLOBAL
> ASM_PFX(gStmSmiHandlerIdtr)
> >>> +ASM_GLOBAL ASM_PFX(gStmPsdOffset)
> >>> +ASM_GLOBAL ASM_PFX(gStmGdtSize)
> >>> +ASM_GLOBAL ASM_PFX(gStmGdtPtr)
> >>>
> >>> .equ MSR_IA32_MISC_ENABLE, 0x1A0
> >>> .equ MSR_EFER, 0xc0000080
> >>> @@ -36,12 +41,13 @@ ASM_GLOBAL ASM_PFX(gStmSmiHandlerIdtr) #
> #
> >>> Constants relating to TXT_PROCESSOR_SMM_DESCRIPTOR #
> >>> -.equ DSC_OFFSET, 0xfb00
> >>> -.equ DSC_GDTPTR, 0x48
> >>> -.equ DSC_GDTSIZ, 0x50
> >>> -.equ DSC_CS, 0x14
> >>> -.equ DSC_DS, 0x16
> >>> -.equ DSC_SS, 0x18
> >>> +# .equ DSC_OFFSET, 0xfb00
> >>> +# .equ DSC_GDTPTR, 0x48
> >>> +# .equ DSC_GDTSIZ, 0x50
> >>> +#
> >>> +.equ DSC_CS, 0x14
> >>> +.equ DSC_DS, 0x16
> >>> +.equ DSC_SS, 0x18
> >>> .equ DSC_OTHERSEG, 0x1A
> >>>
> >>> .equ PROTECT_MODE_CS, 0x08
> >>> @@ -55,11 +61,11 @@ _StmSmiEntryPoint:
> >>> .byte 0xbb # mov bx, imm16
> >>> .word _StmGdtDesc - _StmSmiEntryPoint + 0x8000
> >>> .byte 0x2e,0xa1 # mov ax, cs:[offset16]
> >>> - .word DSC_OFFSET + DSC_GDTSIZ
> >>> +ASM_PFX(gStmGdtSize): .space 2 # .word DSC_OFFSET +
> DSC_GDTSIZ
> >>> decl %eax
> >>> movl %eax, %cs:(%edi) # mov cs:[bx], ax
> >>> .byte 0x66,0x2e,0xa1 # mov eax, cs:[offset16]
> >>> - .word DSC_OFFSET + DSC_GDTPTR
> >>> +ASM_PFX(gStmGdtPtr): .space 2 # .word DSC_OFFSET +
> DSC_GDTPTR
> >>> movw %ax, %cs:2(%edi)
> >>> movw %ax, %bp # ebp = GDT base
> >>> .byte 0x66
> >>> @@ -167,7 +173,11 @@ XdDone:
> >>> movl %cr0, %ebx
> >>> orl $0x080010023, %ebx # enable paging + WP + NE + MP + PE
> >>> movl %ebx, %cr0
> >>> - leal DSC_OFFSET(%edi),%ebx
> >>> +
> >>> + movl $ASM_PFX(gStmPsdOffset), %ebx # leal DSC_OFFSET(%edi),
> >>> %ebx
> >>> + movzxw (%ebx), %esi
> >>> + leal (%edi, %esi), %ebx
> >>> +
> >>> movw DSC_DS(%ebx),%ax
> >>> movl %eax, %ds
> >>> movw DSC_OTHERSEG(%ebx),%ax
> >>> diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.asm
> >>> b/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.asm
> >>> index 91dc1eb..4dbe276 100644
> >>> --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.asm
> >>> +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.asm
> >>> @@ -1,5 +1,7 @@
> >>> ;-------------------------------------------------------------------
> >>> ----------- ; ; Copyright (c) 2009 - 2017, Intel Corporation. All
> >>> rights reserved.<BR>
> >>> +; Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR> ;
> >>> ; This program and the accompanying materials ; are licensed and
> >>> made available under the terms and conditions of the BSD License ;
> >>> which accompanies this distribution. The full text of the license may be
> found at
> >>> @@ -29,13 +31,14 @@ MSR_EFER_XD EQU 0800h
> >>> ;
> >>> ; Constants relating to TXT_PROCESSOR_SMM_DESCRIPTOR ;
> >>> -DSC_OFFSET EQU 0fb00h
> >>> -DSC_GDTPTR EQU 48h
> >>> -DSC_GDTSIZ EQU 50h
> >>> -DSC_CS EQU 14h
> >>> -DSC_DS EQU 16h
> >>> -DSC_SS EQU 18h
> >>> -DSC_OTHERSEG EQU 1Ah
> >>> +; DSC_OFFSET EQU 0fb00h
> >>> +; DSC_GDTPTR EQU 48h
> >>> +; DSC_GDTSIZ EQU 50h
> >>> +;
> >>> +DSC_CS EQU 14h
> >>> +DSC_DS EQU 16h
> >>> +DSC_SS EQU 18h
> >>> +DSC_OTHERSEG EQU 1Ah
> >>>
> >>> PROTECT_MODE_CS EQU 08h
> >>> PROTECT_MODE_DS EQU 20h
> >>> @@ -54,6 +57,9 @@ EXTERNDEF gStmSmbase:DWORD
> >>> EXTERNDEF gStmXdSupported:BYTE
> >>> EXTERNDEF FeaturePcdGet (PcdCpuSmmStackGuard):BYTE
> >>> EXTERNDEF gStmSmiHandlerIdtr:FWORD
> >>> +EXTERNDEF gStmPsdOffset:WORD
> >>> +EXTERNDEF gStmGdtSize:WORD
> >>> +EXTERNDEF gStmGdtPtr:WORD
> >>>
> >>> .code
> >>>
> >>> @@ -63,11 +69,11 @@ _StmSmiEntryPoint:
> >>> DB 0bbh ; mov bx, imm16
> >>> DW offset _StmGdtDesc - _StmSmiEntryPoint + 8000h
> >>> DB 2eh, 0a1h ; mov ax, cs:[offset16]
> >>> - DW DSC_OFFSET + DSC_GDTSIZ
> >>> +gStmGdtSize DW ? ; DSC_OFFSET + DSC_GDTSIZ
> >>> dec eax
> >>> mov cs:[edi], eax ; mov cs:[bx], ax
> >>> DB 66h, 2eh, 0a1h ; mov eax, cs:[offset16]
> >>> - DW DSC_OFFSET + DSC_GDTPTR
> >>> +gStmGdtPtr DW ? ; DSC_OFFSET + DSC_GDTPTR
> >>> mov cs:[edi + 2], ax ; mov cs:[bx + 2], eax
> >>> mov bp, ax ; ebp = GDT base
> >>> DB 66h
> >>> @@ -174,7 +180,10 @@ gStmXdSupported DB 1
> >>> mov ebx, cr0
> >>> or ebx, 080010023h ; enable paging + WP + NE + MP + PE
> >>> mov cr0, ebx
> >>> - lea ebx, [edi + DSC_OFFSET]
> >>> +
> >>> + movzx esi, word ptr [gStmPsdOffset] ; lea ebx, [edi +
> DSC_OFFSET]
> >>> + lea ebx, [edi + esi] ;
> >>> +
> >>> mov ax, [ebx + DSC_DS]
> >>> mov ds, eax
> >>> mov ax, [ebx + DSC_OTHERSEG]
> >>> diff --git
> a/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.nasm
> >>> b/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.nasm
> >>> index 00c0f067..023923a 100644
> >>> --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.nasm
> >>> +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.nasm
> >>> @@ -1,5 +1,7 @@
> >>> ;-------------------------------------------------------------------
> >>> ----------- ; ; Copyright (c) 2016 - 2017, Intel Corporation. All
> >>> rights reserved.<BR>
> >>> +; Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR> ;
> >>> ; This program and the accompanying materials ; are licensed and
> >>> made available under the terms and conditions of the BSD License ;
> >>> which accompanies this distribution. The full text of the license
> >>> may be found at @@ -25,17 +27,18 @@ ; ; Constants relating to
> >>> TXT_PROCESSOR_SMM_DESCRIPTOR ; -%define DSC_OFFSET 0xfb00 -
> %define
> >>> DSC_GDTPTR 0x48 -%define DSC_GDTSIZ 0x50 -%define DSC_CS
> >>> 0x14 -%define DSC_DS 0x16 -%define DSC_SS 0x18 -%define
> DSC_OTHERSEG
> >>> 0x1a
> >>> +; %define DSC_OFFSET 0xfb00
> >>> +; %define DSC_GDTPTR 0x48
> >>> +; %define DSC_GDTSIZ 0x50
> >>> +;
> >>> +%define DSC_CS 0x14
> >>> +%define DSC_DS 0x16
> >>> +%define DSC_SS 0x18
> >>> +%define DSC_OTHERSEG 0x1a
> >>>
> >>> %define PROTECT_MODE_CS 0x8
> >>> %define PROTECT_MODE_DS 0x20
> >>> -%define TSS_SEGMENT 0x40
> >>> +%define TSS_SEGMENT 0x40
> >>>
> >>> extern ASM_PFX(SmiRendezvous)
> >>> extern ASM_PFX(FeaturePcdGet (PcdCpuSmmStackGuard)) @@ -51,6
> >>> +54,10 @@ global ASM_PFX(gStmSmbase) global
> >>> ASM_PFX(gStmXdSupported) extern ASM_PFX(gStmSmiHandlerIdtr)
> >>>
> >>> +extern ASM_PFX(gStmPsdOffset)
> >>> +global ASM_PFX(gStmGdtSize)
> >>> +global ASM_PFX(gStmGdtPtr)
> >>> +
> >>> ASM_PFX(gStmSmiCr3) EQU StmSmiCr3Patch - 4
> >>> ASM_PFX(gStmSmiStack) EQU StmSmiStackPatch - 4
> >>> ASM_PFX(gStmSmbase) EQU StmSmbasePatch - 4
> >>> @@ -62,10 +69,18 @@ BITS 16
> >>> ASM_PFX(gcStmSmiHandlerTemplate):
> >>> _StmSmiEntryPoint:
> >>> mov bx, _StmGdtDesc - _StmSmiEntryPoint + 0x8000
> >>> - mov ax,[cs:DSC_OFFSET + DSC_GDTSIZ]
> >>> +
> >>> + mov eax, ASM_PFX(gStmGdtSize) ; mov ax, [cs:DSC_OFFSET +
> >>> DSC_GDTSIZ]
> >>> + mov si, [cs:eax] ;
> >>> + mov ax, [cs:si] ;
> >>> +
> >>> dec ax
> >>> mov [cs:bx], ax
> >>> - mov eax, [cs:DSC_OFFSET + DSC_GDTPTR]
> >>> +
> >>> + mov eax, ASM_PFX(gStmGdtPtr) ; mov eax, [cs:DSC_OFFSET +
> >>> DSC_GDTPTR]
> >>> + mov si, [cs:eax] ;
> >>> + mov eax, [cs:si] ;
> >>> +
> >>> mov [cs:bx + 2], eax
> >>> mov ebp, eax ; ebp = GDT base
> >>> o32 lgdt [cs:bx] ; lgdt fword ptr cs:[bx]
> >>> @@ -166,7 +181,10 @@ StmXdSupportedPatch:
> >>> mov ebx, cr0
> >>> or ebx, 0x80010023 ; enable paging + WP + NE + MP + PE
> >>> mov cr0, ebx
> >>> - lea ebx, [edi + DSC_OFFSET]
> >>> +
> >>> + movzx esi, word [ASM_PFX(gStmPsdOffset)] ; lea ebx, [edi +
> >>> DSC_OFFSET]
> >>> + lea ebx, [edi + esi] ;
> >>> +
> >>> mov ax, [ebx + DSC_DS]
> >>> mov ds, eax
> >>> mov ax, [ebx + DSC_OTHERSEG]
> >>> @@ -271,5 +289,8 @@ _StmSmiHandler:
> >>> ; STM init finish
> >>> jmp CommonHandler
> >>>
> >>> +ASM_PFX(gStmGdtSize) : RESW 1
> >>> +ASM_PFX(gStmGdtPtr) : RESW 1
> >>> +
> >>> ASM_PFX(gcStmSmiHandlerSize) : DW $ - _StmSmiEntryPoint
> >>> ASM_PFX(gcStmSmiHandlerOffset) : DW _StmSmiHandler -
> >>> _StmSmiEntryPoint
> >>> diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCommon.h
> >>> b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCommon.h
> >>> new file mode 100644
> >>> index 0000000..78b3a5b
> >>> --- /dev/null
> >>> +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCommon.h
> >>> @@ -0,0 +1,48 @@
> >>> +/** @file
> >>> + Common declarations
> >>> +
> >>> + Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>
> >>> +
> >>> + This program and the accompanying materials are licensed and
> >>> + made available under the terms and conditions of the BSD License
> >>> + which accompanies this distribution. The full text of the license
> >>> + may be found at http://opensource.org/licenses/bsd-license.php.
> >>> +
> >>> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS
> IS"
> >>> BASIS,
> >>> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
> >>> EXPRESS OR IMPLIED.
> >>> +
> >>> +**/
> >>> +
> >>> +#ifndef _SMM_COMMON_H_
> >>> +#define _SMM_COMMON_H_
> >>> +
> >>> +#include <Register/Amd/Cpuid.h>
> >>> +
> >>> +//
> >>> +// Definitions for AMD systems are based on contents of the //
> >>> +AMD64 Architecture Programmer's Manual // Volume 2: System
> >>> +Programming, Section 10 System-Management Mode // #define
> >>> +AMD_SMRAM_SAVE_STATE_MAP_OFFSET 0xfe00
> >>> +#define AMD_SMM_PSD_OFFSET 0xfc00
> >>> +
> >>> +//
> >>> +// External global variables for SMRAM offsets // extern UINT16
> >>> +gSmramStateMapOffset; extern UINT16 gSmmPsdOffset;
> >>> +
> >>> +
> >>> +/**
> >>> + Determine if the standard CPU signature is "AuthenticAMD".
> >>> +
> >>> + @retval TRUE The CPU signature matches.
> >>> + @retval FALSE The CPU signature does not match.
> >>> +
> >>> +**/
> >>> +BOOLEAN
> >>> +SmmStandardSignatureIsAuthenticAMD (
> >>> + VOID
> >>> + );
> >>> +
> >>> +#endif
> >>> diff --git
> >>> a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c
> >>> b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c
> >>> index 2d2bc6d..1c12095 100644
> >>> --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c
> >>> +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c
> >>> @@ -1,14 +1,16 @@
> >>> /** @file
> >>> -The CPU specific programming for PiSmmCpuDxeSmm module.
> >>> + The CPU specific programming for PiSmmCpuDxeSmm module.
> >>>
> >>> -Copyright (c) 2010 - 2016, Intel Corporation. All rights
> >>> reserved.<BR> -This program and the accompanying materials -are
> >>> licensed and made available under the terms and conditions of the
> >>> BSD License -which accompanies this distribution. The full text of
> >>> the license may be found at -
> >>> http://opensource.org/licenses/bsd-license.php
> >>> + Copyright (c) 2010 - 2016, Intel Corporation. All rights
> >>> + reserved.<BR> Copyright (c) 2017, AMD Incorporated. All rights
> >>> + reserved.<BR>
> >>>
> >>> -THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
> >>> BASIS, -WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND,
> EITHER
> >>> EXPRESS OR IMPLIED.
> >>> + This program and the accompanying materials are licensed and
> >>> + made available under the terms and conditions of the BSD License
> >>> + which accompanies this distribution. The full text of the license
> >>> + may be found at http://opensource.org/licenses/bsd-license.php
> >>> +
> >>> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS
> IS"
> >>> BASIS,
> >>> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
> >>> EXPRESS OR IMPLIED.
> >>>
> >>> **/
> >>>
> >>> @@ -22,6 +24,8 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF
> ANY KIND,
> >>> EITHER EXPRESS OR IMPLIED.
> >>> #include <Register/Cpuid.h>
> >>> #include <Register/SmramSaveStateMap.h>
> >>>
> >>> +#include "SmmCommon.h"
> >>> +
> >>> //
> >>> // Machine Specific Registers (MSRs) // @@ -41,6 +45,7 @@ WITHOUT
> >>> WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR
> >>> IMPLIED.
> >>> #define SMM_FEATURES_LIB_IA32_MCA_CAP 0x17D
> >>> #define SMM_CODE_ACCESS_CHK_BIT BIT58
> >>>
> >>> +
> >>> /**
> >>> Internal worker function that is called to complete CPU initialization at
> the
> >>> end of SmmCpuFeaturesInitializeProcessor().
> >>> @@ -77,6 +82,13 @@ BOOLEAN mNeedConfigureMtrrs = TRUE; //
> BOOLEAN
> >>> *mSmrrEnabled;
> >>>
> >>> +//
> >>> +// Set default value for SMRAM offset // from
> >>> +<Register/SmramSaveStateMap.h> //
> >>> +UINT16 gSmramStateMapOffset =
> SMRAM_SAVE_STATE_MAP_OFFSET;
> >>> +
> >>> +
> >>> /**
> >>> The constructor function
> >>>
> >>> @@ -99,6 +111,13 @@ SmmCpuFeaturesLibConstructor (
> >>> UINTN ModelId;
> >>>
> >>> //
> >>> + // Override SMRAM offset for AMD
> >>> + //
> >>> + if (SmmStandardSignatureIsAuthenticAMD ()) {
> >>> + gSmramStateMapOffset =
> AMD_SMRAM_SAVE_STATE_MAP_OFFSET; }
> >>> +
> >>> + //
> >>> // Retrieve CPU Family and Model
> >>> //
> >>> AsmCpuid (CPUID_VERSION_INFO, &RegEax, NULL, NULL, &RegEdx);
> @@ -
> >>> 224,7 +243,7 @@ SmmCpuFeaturesInitializeProcessor (
> >>> //
> >>> // Configure SMBASE.
> >>> //
> >>> - CpuState = (SMRAM_SAVE_STATE_MAP
> >>> *)(UINTN)(SMM_DEFAULT_SMBASE +
> >>> SMRAM_SAVE_STATE_MAP_OFFSET);
> >>> + CpuState = (SMRAM_SAVE_STATE_MAP
> >>> *)(UINTN)(SMM_DEFAULT_SMBASE +
> >>> + gSmramStateMapOffset);
> >>> CpuState->x86.SMBASE = (UINT32)CpuHotPlugData-
> >SmBase[CpuIndex];
> >>>
> >>> //
> >>> @@ -630,3 +649,25 @@ SmmCpuFeaturesAllocatePageTableMemory (
> >>> return NULL;
> >>> }
> >>>
> >>> +
> >>> +/**
> >>> + Determine if the standard CPU signature is "AuthenticAMD".
> >>> +
> >>> + @retval TRUE The CPU signature matches.
> >>> + @retval FALSE The CPU signature does not match.
> >>> +
> >>> +**/
> >>> +BOOLEAN
> >>> +SmmStandardSignatureIsAuthenticAMD (
> >>> + VOID
> >>> + )
> >>> +{
> >>> + UINT32 RegEbx;
> >>> + UINT32 RegEcx;
> >>> + UINT32 RegEdx;
> >>> +
> >>> + AsmCpuid (CPUID_SIGNATURE, NULL, &RegEbx, &RegEcx, &RegEdx);
> >>> + return (RegEbx == CPUID_SIGNATURE_AUTHENTIC_AMD_EBX &&
> >>> + RegEcx == CPUID_SIGNATURE_AUTHENTIC_AMD_ECX &&
> >>> + RegEdx == CPUID_SIGNATURE_AUTHENTIC_AMD_EDX);
> >>> +}
> >>> diff --git
> >>> a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf
> >>> b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf
> >>> index 77908b0..6a39d4b 100644
> >>> --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf
> >>> +++
> b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf
> >>> @@ -2,6 +2,8 @@
> >>> # The CPU specific programming for PiSmmCpuDxeSmm module.
> >>> #
> >>> # Copyright (c) 2009 - 2016, Intel Corporation. All rights
> >>> reserved.<BR>
> >>> +# Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR> #
> >>> # This program and the accompanying materials # are licensed and
> >>> made available under the terms and conditions of the BSD License #
> >>> which accompanies this distribution. The full text of the license
> >>> may be found at @@ -24,6 +26,7 @@
> >>>
> >>> [Sources]
> >>> SmmCpuFeaturesLib.c
> >>> + SmmCommon.h
> >>> SmmCpuFeaturesLibNoStm.c
> >>>
> >>> [Packages]
> >>> diff --git
> >>> a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibStm.inf
> >>> b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibStm.inf
> >>> index db8dcdc..a76bed6 100644
> >>> ---
> a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibStm.inf
> >>> +++
> b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibStm.inf
> >>> @@ -3,6 +3,8 @@
> >>> # is included.
> >>> #
> >>> # Copyright (c) 2009 - 2016, Intel Corporation. All rights
> >>> reserved.<BR>
> >>> +# Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR> #
> >>> # This program and the accompanying materials # are licensed and
> >>> made available under the terms and conditions of the BSD License #
> >>> which accompanies this distribution. The full text of the license
> >>> may be found at @@ -25,6 +27,7 @@
> >>>
> >>> [Sources]
> >>> SmmCpuFeaturesLib.c
> >>> + SmmCommon.h
> >>> SmmStm.c
> >>> SmmStm.h
> >>>
> >>> diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c
> >>> b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c
> >>> index 45015b8..5f7c3db 100644
> >>> --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c
> >>> +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c
> >>> @@ -2,6 +2,8 @@
> >>> SMM STM support functions
> >>>
> >>> Copyright (c) 2015 - 2017, Intel Corporation. All rights
> >>> reserved.<BR>
> >>> + Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>
> >>> +
> >>> This program and the accompanying materials
> >>> are licensed and made available under the terms and conditions of
> >>> the BSD License
> >>> which accompanies this distribution. The full text of the license
> >>> may be found at @@ -28,6 +30,8 @@ #include <Protocol/MpService.h>
> >>>
> >>> #include "SmmStm.h"
> >>> +#include "SmmCommon.h"
> >>> +
> >>>
> >>> #define TXT_EVTYPE_BASE 0x400
> >>> #define TXT_EVTYPE_STM_HASH (TXT_EVTYPE_BASE + 14)
> >>> @@ -97,6 +101,20 @@ extern volatile UINT8
> gcStmSmiHandlerTemplate[];
> >>> extern CONST UINT16 gcStmSmiHandlerSize;
> >>> extern UINT16 gcStmSmiHandlerOffset;
> >>> extern BOOLEAN gStmXdSupported;
> >>> +extern UINT16 gStmGdtSize;
> >>> +extern UINT16 gStmGdtPtr;
> >>> +
> >>> +//
> >>> +// Constants relating to TXT_PROCESSOR_SMM_DESCRIPTOR //
> >>> +#define TXT_PSD_GDTPTR 0x48
> >>> +#define TXT_PSD_GDTSIZE 0x50
> >>> +
> >>> +//
> >>> +// Set default value for PSD offset in SMRAM // from
> >>> +<Register/StmApi.h> //
> >>> +UINT16 gStmPsdOffset = TXT_SMM_PSD_OFFSET;
> >>>
> >>> //
> >>> // Variables used by SMI Handler
> >>> @@ -145,6 +163,19 @@ SmmCpuFeaturesLibStmConstructor (
> >>> ASSERT_EFI_ERROR (Status);
> >>>
> >>> //
> >>> + // Override PSD offset for AMD
> >>> + //
> >>> + if (SmmStandardSignatureIsAuthenticAMD ()) {
> >>> + gStmPsdOffset = AMD_SMM_PSD_OFFSET; }
> >>> +
> >>> + //
> >>> + // Initialize STM global variables associated with SMI Handler
> >>> + // gStmGdtSize = gStmPsdOffset + TXT_PSD_GDTSIZE; gStmGdtPtr =
> >>> + gStmPsdOffset + TXT_PSD_GDTPTR;
> >>> +
> >>> + //
> >>> // Lookup the MP Services Protocol
> >>> //
> >>> Status = gBS->LocateProtocol (
> >>> @@ -276,8 +307,8 @@ SmmCpuFeaturesInstallSmiHandler (
> >>> UINT32 RegEdx;
> >>> EFI_PROCESSOR_INFORMATION ProcessorInfo;
> >>>
> >>> - CopyMem ((VOID *)((UINTN)SmBase + TXT_SMM_PSD_OFFSET),
> &gcStmPsd,
> >>> sizeof (gcStmPsd));
> >>> - Psd = (TXT_PROCESSOR_SMM_DESCRIPTOR *)(VOID
> *)((UINTN)SmBase +
> >>> TXT_SMM_PSD_OFFSET);
> >>> + CopyMem ((VOID *)((UINTN)SmBase + gStmPsdOffset), &gcStmPsd,
> >>> sizeof
> >>> + (gcStmPsd)); Psd = (TXT_PROCESSOR_SMM_DESCRIPTOR *)(VOID
> >>> + *)((UINTN)SmBase + gStmPsdOffset);
> >>> Psd->SmmGdtPtr = GdtBase;
> >>> Psd->SmmGdtSize = (UINT32)GdtSize;
> >>>
> >>> @@ -416,7 +447,7 @@ SmmEndOfDxeEventNotify (
> >>> }
> >>>
> >>> for (Index = 0; Index < gSmst->NumberOfCpus; Index++) {
> >>> - Psd = (TXT_PROCESSOR_SMM_DESCRIPTOR *)((UINTN)gSmst-
> >>>> CpuSaveState[Index] - SMRAM_SAVE_STATE_MAP_OFFSET +
> >>> TXT_SMM_PSD_OFFSET);
> >>> + Psd = (TXT_PROCESSOR_SMM_DESCRIPTOR
> >>> + *)((UINTN)gSmst->CpuSaveState[Index] - gSmramStateMapOffset +
> >>> + gStmPsdOffset);
> >>> DEBUG ((DEBUG_INFO, "Index=%d Psd=%p Rsdp=%p\n", Index, Psd,
> >>> Rsdp));
> >>> Psd->AcpiRsdp = (UINT64)(UINTN)Rsdp;
> >>> }
> >>> @@ -1266,7 +1297,7 @@ NotifyStmResourceChange (
> >>> TXT_PROCESSOR_SMM_DESCRIPTOR *Psd;
> >>>
> >>> for (Index = 0; Index < gSmst->NumberOfCpus; Index++) {
> >>> - Psd = (TXT_PROCESSOR_SMM_DESCRIPTOR *)((UINTN)gSmst-
> >>>> CpuSaveState[Index] - SMRAM_SAVE_STATE_MAP_OFFSET +
> >>> TXT_SMM_PSD_OFFSET);
> >>> + Psd = (TXT_PROCESSOR_SMM_DESCRIPTOR
> >>> + *)((UINTN)gSmst->CpuSaveState[Index] - gSmramStateMapOffset +
> >>> + gStmPsdOffset);
> >>> Psd->BiosHwResourceRequirementsPtr =
> (UINT64)(UINTN)StmResource;
> >>> }
> >>> return ;
> >>> diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.S
> >>> b/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.S
> >>> index 1f9f91c..5f3386a 100644
> >>> --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.S
> >>> +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.S
> >>> @@ -1,6 +1,8 @@
> >>> #-------------------------------------------------------------------
> >>> -----------
> >>> #
> >>> # Copyright (c) 2009 - 2016, Intel Corporation. All rights
> >>> reserved.<BR>
> >>> +# Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR> #
> >>> # This program and the accompanying materials # are licensed and
> >>> made available under the terms and conditions of the BSD License #
> >>> which accompanies this distribution. The full text of the license
> >>> may be found at @@ -27,6 +29,9 @@ ASM_GLOBAL
> ASM_PFX(gStmSmiStack)
> >>> ASM_GLOBAL
> >>> ASM_PFX(gStmSmbase) ASM_GLOBAL ASM_PFX(gStmXdSupported)
> ASM_GLOBAL
> >>> ASM_PFX(gStmSmiHandlerIdtr)
> >>> +ASM_GLOBAL ASM_PFX(gStmPsdOffset)
> >>> +ASM_GLOBAL ASM_PFX(gStmGdtSize)
> >>> +ASM_GLOBAL ASM_PFX(gStmGdtPtr)
> >>>
> >>> .equ MSR_IA32_MISC_ENABLE, 0x1A0
> >>> .equ MSR_EFER, 0xc0000080
> >>> @@ -35,12 +40,13 @@ ASM_GLOBAL ASM_PFX(gStmSmiHandlerIdtr) #
> #
> >>> Constants relating to TXT_PROCESSOR_SMM_DESCRIPTOR #
> >>> -.equ DSC_OFFSET, 0xfb00
> >>> -.equ DSC_GDTPTR, 0x48
> >>> -.equ DSC_GDTSIZ, 0x50
> >>> -.equ DSC_CS, 0x14
> >>> -.equ DSC_DS, 0x16
> >>> -.equ DSC_SS, 0x18
> >>> +# .equ DSC_OFFSET, 0xfb00
> >>> +# .equ DSC_GDTPTR, 0x48
> >>> +# .equ DSC_GDTSIZ, 0x50
> >>> +#
> >>> +.equ DSC_CS, 0x14
> >>> +.equ DSC_DS, 0x16
> >>> +.equ DSC_SS, 0x18
> >>> .equ DSC_OTHERSEG, 0x1a
> >>> #
> >>> # Constants relating to CPU State Save Area @@ -71,12 +77,12 @@
> >>> _StmSmiEntryPoint:
> >>> # fix GDT descriptor
> >>> #
> >>> .byte 0x2e,0xa1 # mov ax, cs:[offset16]
> >>> - .word DSC_OFFSET + DSC_GDTSIZ
> >>> +ASM_PFX(gStmGdtSize): .space 2 # .word DSC_OFFSET +
> DSC_GDTSIZ
> >>> .byte 0x48 # dec ax
> >>> .byte 0x2e
> >>> movl %eax, (%rdi) # mov cs:[bx], ax
> >>> .byte 0x66,0x2e,0xa1 # mov eax, cs:[offset16]
> >>> - .word DSC_OFFSET + DSC_GDTPTR
> >>> +ASM_PFX(gStmGdtPtr): .space 2 # .word DSC_OFFSET +
> DSC_GDTPTR
> >>> .byte 0x2e
> >>> movw %ax, 2(%rdi)
> >>> .byte 0x66,0x2e
> >>> @@ -183,7 +189,11 @@ Base:
> >>> LongMode: # long mode (64-bit code) starts here
> >>> movabsq $ASM_PFX(gStmSmiHandlerIdtr), %rax
> >>> lidt (%rax)
> >>> - lea (DSC_OFFSET)(%rdi), %ebx
> >>> +
> >>> + movl $ASM_PFX(gStmPsdOffset), %ebx # lea
> (DSC_OFFSET)(%rdi),
> >>> %ebx
> >>> + movzxw (%ebx), %rsi
> >>> + leal (%rdi, %rsi), %ebx
> >>> +
> >>> movw DSC_DS(%rbx), %ax
> >>> movl %eax,%ds
> >>> movw DSC_OTHERSEG(%rbx), %ax
> >>> diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.asm
> >>> b/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.asm
> >>> index ad51e07..10913df 100644
> >>> --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.asm
> >>> +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.asm
> >>> @@ -1,5 +1,7 @@
> >>> ;-------------------------------------------------------------------
> >>> ----------- ; ; Copyright (c) 2009 - 2016, Intel Corporation. All
> >>> rights reserved.<BR>
> >>> +; Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR> ;
> >>> ; This program and the accompanying materials ; are licensed and
> >>> made available under the terms and conditions of the BSD License ;
> >>> which accompanies this distribution. The full text of the license may be
> found at
> >>> @@ -32,6 +34,10 @@ EXTERNDEF gStmSmiStack:DWORD
> >>> EXTERNDEF gStmSmbase:DWORD
> >>> EXTERNDEF gStmXdSupported:BYTE
> >>> EXTERNDEF gStmSmiHandlerIdtr:FWORD
> >>> +EXTERNDEF gStmPsdOffset:WORD
> >>> +EXTERNDEF gStmGdtSize:WORD
> >>> +EXTERNDEF gStmGdtPtr:WORD
> >>> +
> >>>
> >>> MSR_IA32_MISC_ENABLE EQU 1A0h
> >>> MSR_EFER EQU 0c0000080h
> >>> @@ -40,13 +46,14 @@ MSR_EFER_XD EQU 0800h
> >>> ;
> >>> ; Constants relating to TXT_PROCESSOR_SMM_DESCRIPTOR ;
> >>> -DSC_OFFSET EQU 0fb00h
> >>> -DSC_GDTPTR EQU 48h
> >>> -DSC_GDTSIZ EQU 50h
> >>> -DSC_CS EQU 14h
> >>> -DSC_DS EQU 16h
> >>> -DSC_SS EQU 18h
> >>> -DSC_OTHERSEG EQU 1ah
> >>> +; DSC_OFFSET EQU 0fb00h
> >>> +; DSC_GDTPTR EQU 48h
> >>> +; DSC_GDTSIZ EQU 50h
> >>> +;
> >>> +DSC_CS EQU 14h
> >>> +DSC_DS EQU 16h
> >>> +DSC_SS EQU 18h
> >>> +DSC_OTHERSEG EQU 1ah
> >>> ;
> >>> ; Constants relating to CPU State Save Area ; @@ -74,12 +81,12 @@
> >>> _StmSmiEntryPoint:
> >>> DW offset _StmGdtDesc - _StmSmiEntryPoint + 8000h ; bx =
> GdtDesc
> >>> offset
> >>> ; fix GDT descriptor
> >>> DB 2eh, 0a1h ; mov ax, cs:[offset16]
> >>> - DW DSC_OFFSET + DSC_GDTSIZ
> >>> +gStmGdtSize DW ? ; DSC_OFFSET + DSC_GDTSIZ
> >>> DB 48h ; dec ax
> >>> DB 2eh
> >>> mov [rdi], eax ; mov cs:[bx], ax
> >>> DB 66h, 2eh, 0a1h ; mov eax, cs:[offset16]
> >>> - DW DSC_OFFSET + DSC_GDTPTR
> >>> +gStmGdtPtr DW ? ; DSC_OFFSET + DSC_GDTPTR
> >>> DB 2eh
> >>> mov [rdi + 2], ax ; mov cs:[bx + 2], eax
> >>> DB 66h, 2eh
> >>> @@ -178,7 +185,10 @@ Base:
> >>> @LongMode: ; long mode (64-bit code) starts here
> >>> mov rax, offset gStmSmiHandlerIdtr
> >>> lidt fword ptr [rax]
> >>> - lea ebx, [rdi + DSC_OFFSET]
> >>> +
> >>> + movzx rsi, word ptr [gStmPsdOffset] ; lea ebx, [rdi +
> DSC_OFFSET]
> >>> + lea ebx, [rdi + rsi] ;
> >>> +
> >>> mov ax, [rbx + DSC_DS]
> >>> mov ds, eax
> >>> mov ax, [rbx + DSC_OTHERSEG]
> >>> diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.nasm
> >>> b/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.nasm
> >>> index bcac643..df4c5a2 100644
> >>> --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.nasm
> >>> +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.nasm
> >>> @@ -1,5 +1,7 @@
> >>> ;-------------------------------------------------------------------
> >>> ----------- ; ; Copyright (c) 2016 - 2017, Intel Corporation. All
> >>> rights reserved.<BR>
> >>> +; Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR> ;
> >>> ; This program and the accompanying materials ; are licensed and
> >>> made available under the terms and conditions of the BSD License ;
> >>> which accompanies this distribution. The full text of the license
> >>> may be found at @@ -29,13 +31,14 @@ ; ; Constants relating to
> >>> TXT_PROCESSOR_SMM_DESCRIPTOR ; -%define DSC_OFFSET 0xfb00 -
> %define
> >>> DSC_GDTPTR 0x48 -%define DSC_GDTSIZ 0x50 -%define DSC_CS
> >>> 0x14 -%define DSC_DS 0x16 -%define DSC_SS 0x18 -%define
> DSC_OTHERSEG
> >>> 0x1a
> >>> +; %define DSC_OFFSET 0xfb00
> >>> +; %define DSC_GDTPTR 0x48
> >>> +; %define DSC_GDTSIZ 0x50
> >>> +;
> >>> +%define DSC_CS 0x14
> >>> +%define DSC_DS 0x16
> >>> +%define DSC_SS 0x18
> >>> +%define DSC_OTHERSEG 0x1a
> >>> ;
> >>> ; Constants relating to CPU State Save Area ; @@ -44,9 +47,9 @@
> >>>
> >>> %define PROTECT_MODE_CS 0x8
> >>> %define PROTECT_MODE_DS 0x20
> >>> -%define LONG_MODE_CS 0x38
> >>> -%define TSS_SEGMENT 0x40
> >>> -%define GDT_SIZE 0x50
> >>> +%define LONG_MODE_CS 0x38
> >>> +%define TSS_SEGMENT 0x40
> >>> +%define GDT_SIZE 0x50
> >>>
> >>> extern ASM_PFX(SmiRendezvous)
> >>> extern ASM_PFX(gStmSmiHandlerIdtr)
> >>> @@ -61,6 +64,10 @@ global ASM_PFX(gcStmSmiHandlerTemplate)
> global
> >>> ASM_PFX(gcStmSmiHandlerSize) global
> ASM_PFX(gcStmSmiHandlerOffset)
> >>>
> >>> +extern ASM_PFX(gStmPsdOffset)
> >>> +global ASM_PFX(gStmGdtSize)
> >>> +global ASM_PFX(gStmGdtPtr)
> >>> +
> >>> ASM_PFX(gStmSmbase) EQU StmSmbasePatch - 4
> >>> ASM_PFX(gStmSmiStack) EQU StmSmiStackPatch - 4
> >>> ASM_PFX(gStmSmiCr3) EQU StmSmiCr3Patch - 4
> >>> @@ -73,10 +80,18 @@ BITS 16
> >>> ASM_PFX(gcStmSmiHandlerTemplate):
> >>> _StmSmiEntryPoint:
> >>> mov bx, _StmGdtDesc - _StmSmiEntryPoint + 0x8000
> >>> - mov ax,[cs:DSC_OFFSET + DSC_GDTSIZ]
> >>> +
> >>> + mov eax, ASM_PFX(gStmGdtSize) ; mov ax, [cs:DSC_OFFSET +
> >>> DSC_GDTSIZ]
> >>> + mov si, [cs:eax] ;
> >>> + mov ax, [cs:si] ;
> >>> +
> >>> dec ax
> >>> mov [cs:bx], ax
> >>> - mov eax, [cs:DSC_OFFSET + DSC_GDTPTR]
> >>> +
> >>> + mov eax, ASM_PFX(gStmGdtPtr) ; mov eax, [cs:DSC_OFFSET +
> >>> DSC_GDTPTR]
> >>> + mov si, [cs:eax] ;
> >>> + mov eax, [cs:si] ;
> >>> +
> >>> mov [cs:bx + 2], eax
> >>> o32 lgdt [cs:bx] ; lgdt fword ptr cs:[bx]
> >>> mov ax, PROTECT_MODE_CS
> >>> @@ -166,7 +181,10 @@ Base:
> >>> @LongMode: ; long mode (64-bit code) starts here
> >>> mov rax, ASM_PFX(gStmSmiHandlerIdtr)
> >>> lidt [rax]
> >>> - lea ebx, [rdi + DSC_OFFSET]
> >>> +
> >>> + movzx rsi, word [ASM_PFX(gStmPsdOffset)] ; lea ebx, [rdi +
> >>> DSC_OFFSET]
> >>> + lea ebx, [rdi + rsi] ;
> >>> +
> >>> mov ax, [rbx + DSC_DS]
> >>> mov ds, eax
> >>> mov ax, [rbx + DSC_OTHERSEG]
> >>> @@ -262,5 +280,8 @@ _StmSmiHandler:
> >>> ; STM init finish
> >>> jmp CommonHandler
> >>>
> >>> +ASM_PFX(gStmGdtSize) : RESW 1
> >>> +ASM_PFX(gStmGdtPtr) : RESW 1
> >>> +
> >>> ASM_PFX(gcStmSmiHandlerSize) : DW $ - _StmSmiEntryPoint
> >>> ASM_PFX(gcStmSmiHandlerOffset) : DW _StmSmiHandler -
> >>> _StmSmiEntryPoint
> >>> --
> >>> 2.7.4
> >>
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH v5 1/2] UefiCpuPkg/SmmCpuFeaturesLib: Use global variables to replace macros
2017-10-17 15:14 ` Laszlo Ersek
2017-10-17 16:40 ` Duran, Leo
@ 2017-10-18 1:50 ` Yao, Jiewen
2017-10-18 14:36 ` Duran, Leo
1 sibling, 1 reply; 30+ messages in thread
From: Yao, Jiewen @ 2017-10-18 1:50 UTC (permalink / raw)
To: Laszlo Ersek, Duran, Leo
Cc: Ni, Ruiyu, Justen, Jordan L, edk2-devel@lists.01.org, Gao, Liming,
Kinney, Michael D, Paolo Bonzini
Thanks. Then I think Paolo’s suggestion makes more sense.
If we can use same off, that would be great.
If no, just check AMD version ID in SaveState.
Thank you
Yao Jiewen
From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf Of Laszlo Ersek
Sent: Tuesday, October 17, 2017 11:15 PM
To: Yao, Jiewen <jiewen.yao@intel.com>; Duran, Leo <leo.duran@amd.com>
Cc: Ni, Ruiyu <ruiyu.ni@intel.com>; Justen, Jordan L <jordan.l.justen@intel.com>; edk2-devel@lists.01.org; Gao, Liming <liming.gao@intel.com>; Kinney, Michael D <michael.d.kinney@intel.com>; Paolo Bonzini <pbonzini@redhat.com>
Subject: Re: [edk2] [PATCH v5 1/2] UefiCpuPkg/SmmCpuFeaturesLib: Use global variables to replace macros
On 10/17/17 16:50, Yao, Jiewen wrote:
> I think it is unnecessary. All intel CPU is using same offset. All amd CPU is using same offset. It can be identified easily by code.
> Adding a new API now is also an incompatible change because that requires all existing featurelib change to add a new API. We have lots of close source platform using its own featurelib.
>
> May I know what problem we are trying to resolve by adding a new API?
QEMU (and hence OVMF) uses the AMD save state map even when it emulates
Intel CPUs.
The reason is that the Intel SDM does not specify the Intel save state
map in sufficient detail (for emulation by QEMU), while the AMD spec
does. So, as an emulation target, only the AMD one is implementable in
QEMU (and supportable in OVMF), regardless of whether QEMU reports the
virtual CPU manufacturer as Intel vs. AMD.
If PiSmmCpuDxeSmm used a CPUID check, saw "Intel" as manufacturer, and
then used the Intel definition of the save state map, then
PiSmmCpuDxeSmm would break on QEMU / as part of OVMF.
Thanks,
Laszlo
>
>
> thank you!
> Yao, Jiewen
>
>
>> 在 2017年10月17日，下午10:20，Duran, Leo <leo.duran@amd.com<mailto:leo.duran@amd.com>> 写道：
>>
>> Yao, Lazlo, et al,
>>
>> For the SRAM_SAVE_STATE_MAP_OFFSET:
>> I propose returning the value by a function in SmmCpuFeaturesLib... Here's the rationale:
>> - The value is fixed per CPU architecture, so this qualifies as a CPU feature.
>> - The logic for CPU architecture detection would be in one place (e.g., PiSmmCpuDxeSmm would call the library function)
>> - The OVMF and Quark instances of the library could just return the current (default) value, so no compatibility issues.
>>
>> if you agree with this is an acceptable solution, I will submit a revised patch-set to address just the SRAM_SAVE_STATE_MAP_OFFSET.
>> (BTW, I'm re-evaluating the changes submitted for the PSD offset, with the goal of just using the default value and dropping those changes)
>>
>> Thanks,
>> Leo.
>>
>>> -----Original Message-----
>>> From: Duran, Leo
>>> Sent: Wednesday, October 11, 2017 2:46 PM
>>> To: edk2-devel@lists.01.org<mailto:edk2-devel@lists.01.org>
>>> Cc: Duran, Leo <leo.duran@amd.com<mailto:leo.duran@amd.com>>; Jiewen Yao
>>> <jiewen.yao@intel.com<mailto:jiewen.yao@intel.com>>; Ruiyu Ni <ruiyu.ni@intel.com<mailto:ruiyu.ni@intel.com>>; Michael D Kinney
>>> <michael.d.kinney@intel.com<mailto:michael.d.kinney@intel.com>>; Jordan Justen <jordan.l.justen@intel.com<mailto:jordan.l.justen@intel.com>>;
>>> Liming Gao <liming.gao@intel.com<mailto:liming.gao@intel.com>>
>>> Subject: [PATCH v5 1/2] UefiCpuPkg/SmmCpuFeaturesLib: Use global
>>> variables to replace macros
>>>
>>> Set global variables on Constructor function based on CPUID checks.
>>> The variables replace Intel macros to allow support on AMD x86 systems.
>>>
>>> Specifically, the replaced macros are:
>>> 1) SRAM_SAVE_STATE_MAP_OFFSET
>>> 2) TXT_SMM_PSD_OFFSET
>>>
>>> Cc: Jiewen Yao <jiewen.yao@intel.com<mailto:jiewen.yao@intel.com>>
>>> Cc: Ruiyu Ni <ruiyu.ni@intel.com<mailto:ruiyu.ni@intel.com>>
>>> Cc: Michael D Kinney <michael.d.kinney@intel.com<mailto:michael.d.kinney@intel.com>>
>>> Cc: Jordan Justen <jordan.l.justen@intel.com<mailto:jordan.l.justen@intel.com>>
>>> Cc: Liming Gao <liming.gao@intel.com<mailto:liming.gao@intel.com>>
>>> Contributed-under: TianoCore Contribution Agreement 1.1
>>> Signed-off-by: Leo Duran <leo.duran@amd.com<mailto:leo.duran@amd.com>>
>>> ---
>>> .../Library/SmmCpuFeaturesLib/Ia32/SmiEntry.S | 28 ++++++----
>>> .../Library/SmmCpuFeaturesLib/Ia32/SmiEntry.asm | 29 +++++++----
>>> .../Library/SmmCpuFeaturesLib/Ia32/SmiEntry.nasm | 43 ++++++++++++---
>>> -
>>> UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCommon.h | 48
>>> ++++++++++++++++++
>>> .../Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c | 59
>>> ++++++++++++++++++----
>>> .../SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf | 3 ++
>>> .../SmmCpuFeaturesLib/SmmCpuFeaturesLibStm.inf | 3 ++
>>> UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c | 39
>>> ++++++++++++--
>>> .../Library/SmmCpuFeaturesLib/X64/SmiEntry.S | 28 ++++++----
>>> .../Library/SmmCpuFeaturesLib/X64/SmiEntry.asm | 30 +++++++----
>>> .../Library/SmmCpuFeaturesLib/X64/SmiEntry.nasm | 47 ++++++++++++---
>>> --
>>> 11 files changed, 282 insertions(+), 75 deletions(-) create mode 100644
>>> UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCommon.h
>>>
>>> diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.S
>>> b/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.S
>>> index 4c0f8c8..c7b49d7 100644
>>> --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.S
>>> +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.S
>>> @@ -1,6 +1,8 @@
>>> #------------------------------------------------------------------------------
>>> #
>>> # Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.<BR>
>>> +# Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR> #
>>> # This program and the accompanying materials # are licensed and made
>>> available under the terms and conditions of the BSD License # which
>>> accompanies this distribution. The full text of the license may be found at
>>> @@ -28,6 +30,9 @@ ASM_GLOBAL ASM_PFX(gStmSmbase) ASM_GLOBAL
>>> ASM_PFX(gStmXdSupported) ASM_GLOBAL ASM_PFX(FeaturePcdGet
>>> (PcdCpuSmmStackGuard)) ASM_GLOBAL ASM_PFX(gStmSmiHandlerIdtr)
>>> +ASM_GLOBAL ASM_PFX(gStmPsdOffset)
>>> +ASM_GLOBAL ASM_PFX(gStmGdtSize)
>>> +ASM_GLOBAL ASM_PFX(gStmGdtPtr)
>>>
>>> .equ MSR_IA32_MISC_ENABLE, 0x1A0
>>> .equ MSR_EFER, 0xc0000080
>>> @@ -36,12 +41,13 @@ ASM_GLOBAL ASM_PFX(gStmSmiHandlerIdtr) # #
>>> Constants relating to TXT_PROCESSOR_SMM_DESCRIPTOR #
>>> -.equ DSC_OFFSET, 0xfb00
>>> -.equ DSC_GDTPTR, 0x48
>>> -.equ DSC_GDTSIZ, 0x50
>>> -.equ DSC_CS, 0x14
>>> -.equ DSC_DS, 0x16
>>> -.equ DSC_SS, 0x18
>>> +# .equ DSC_OFFSET, 0xfb00
>>> +# .equ DSC_GDTPTR, 0x48
>>> +# .equ DSC_GDTSIZ, 0x50
>>> +#
>>> +.equ DSC_CS, 0x14
>>> +.equ DSC_DS, 0x16
>>> +.equ DSC_SS, 0x18
>>> .equ DSC_OTHERSEG, 0x1A
>>>
>>> .equ PROTECT_MODE_CS, 0x08
>>> @@ -55,11 +61,11 @@ _StmSmiEntryPoint:
>>> .byte 0xbb # mov bx, imm16
>>> .word _StmGdtDesc - _StmSmiEntryPoint + 0x8000
>>> .byte 0x2e,0xa1 # mov ax, cs:[offset16]
>>> - .word DSC_OFFSET + DSC_GDTSIZ
>>> +ASM_PFX(gStmGdtSize): .space 2 # .word DSC_OFFSET + DSC_GDTSIZ
>>> decl %eax
>>> movl %eax, %cs:(%edi) # mov cs:[bx], ax
>>> .byte 0x66,0x2e,0xa1 # mov eax, cs:[offset16]
>>> - .word DSC_OFFSET + DSC_GDTPTR
>>> +ASM_PFX(gStmGdtPtr): .space 2 # .word DSC_OFFSET + DSC_GDTPTR
>>> movw %ax, %cs:2(%edi)
>>> movw %ax, %bp # ebp = GDT base
>>> .byte 0x66
>>> @@ -167,7 +173,11 @@ XdDone:
>>> movl %cr0, %ebx
>>> orl $0x080010023, %ebx # enable paging + WP + NE + MP + PE
>>> movl %ebx, %cr0
>>> - leal DSC_OFFSET(%edi),%ebx
>>> +
>>> + movl $ASM_PFX(gStmPsdOffset), %ebx # leal DSC_OFFSET(%edi),
>>> %ebx
>>> + movzxw (%ebx), %esi
>>> + leal (%edi, %esi), %ebx
>>> +
>>> movw DSC_DS(%ebx),%ax
>>> movl %eax, %ds
>>> movw DSC_OTHERSEG(%ebx),%ax
>>> diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.asm
>>> b/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.asm
>>> index 91dc1eb..4dbe276 100644
>>> --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.asm
>>> +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.asm
>>> @@ -1,5 +1,7 @@
>>> ;------------------------------------------------------------------------------ ; ;
>>> Copyright (c) 2009 - 2017, Intel Corporation. All rights reserved.<BR>
>>> +; Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR> ;
>>> ; This program and the accompanying materials ; are licensed and made
>>> available under the terms and conditions of the BSD License ; which
>>> accompanies this distribution. The full text of the license may be found at
>>> @@ -29,13 +31,14 @@ MSR_EFER_XD EQU 0800h
>>> ;
>>> ; Constants relating to TXT_PROCESSOR_SMM_DESCRIPTOR ;
>>> -DSC_OFFSET EQU 0fb00h
>>> -DSC_GDTPTR EQU 48h
>>> -DSC_GDTSIZ EQU 50h
>>> -DSC_CS EQU 14h
>>> -DSC_DS EQU 16h
>>> -DSC_SS EQU 18h
>>> -DSC_OTHERSEG EQU 1Ah
>>> +; DSC_OFFSET EQU 0fb00h
>>> +; DSC_GDTPTR EQU 48h
>>> +; DSC_GDTSIZ EQU 50h
>>> +;
>>> +DSC_CS EQU 14h
>>> +DSC_DS EQU 16h
>>> +DSC_SS EQU 18h
>>> +DSC_OTHERSEG EQU 1Ah
>>>
>>> PROTECT_MODE_CS EQU 08h
>>> PROTECT_MODE_DS EQU 20h
>>> @@ -54,6 +57,9 @@ EXTERNDEF gStmSmbase:DWORD
>>> EXTERNDEF gStmXdSupported:BYTE
>>> EXTERNDEF FeaturePcdGet (PcdCpuSmmStackGuard):BYTE
>>> EXTERNDEF gStmSmiHandlerIdtr:FWORD
>>> +EXTERNDEF gStmPsdOffset:WORD
>>> +EXTERNDEF gStmGdtSize:WORD
>>> +EXTERNDEF gStmGdtPtr:WORD
>>>
>>> .code
>>>
>>> @@ -63,11 +69,11 @@ _StmSmiEntryPoint:
>>> DB 0bbh ; mov bx, imm16
>>> DW offset _StmGdtDesc - _StmSmiEntryPoint + 8000h
>>> DB 2eh, 0a1h ; mov ax, cs:[offset16]
>>> - DW DSC_OFFSET + DSC_GDTSIZ
>>> +gStmGdtSize DW ? ; DSC_OFFSET + DSC_GDTSIZ
>>> dec eax
>>> mov cs:[edi], eax ; mov cs:[bx], ax
>>> DB 66h, 2eh, 0a1h ; mov eax, cs:[offset16]
>>> - DW DSC_OFFSET + DSC_GDTPTR
>>> +gStmGdtPtr DW ? ; DSC_OFFSET + DSC_GDTPTR
>>> mov cs:[edi + 2], ax ; mov cs:[bx + 2], eax
>>> mov bp, ax ; ebp = GDT base
>>> DB 66h
>>> @@ -174,7 +180,10 @@ gStmXdSupported DB 1
>>> mov ebx, cr0
>>> or ebx, 080010023h ; enable paging + WP + NE + MP + PE
>>> mov cr0, ebx
>>> - lea ebx, [edi + DSC_OFFSET]
>>> +
>>> + movzx esi, word ptr [gStmPsdOffset] ; lea ebx, [edi + DSC_OFFSET]
>>> + lea ebx, [edi + esi] ;
>>> +
>>> mov ax, [ebx + DSC_DS]
>>> mov ds, eax
>>> mov ax, [ebx + DSC_OTHERSEG]
>>> diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.nasm
>>> b/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.nasm
>>> index 00c0f067..023923a 100644
>>> --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.nasm
>>> +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.nasm
>>> @@ -1,5 +1,7 @@
>>> ;------------------------------------------------------------------------------ ; ;
>>> Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
>>> +; Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR> ;
>>> ; This program and the accompanying materials ; are licensed and made
>>> available under the terms and conditions of the BSD License ; which
>>> accompanies this distribution. The full text of the license may be found at
>>> @@ -25,17 +27,18 @@ ; ; Constants relating to
>>> TXT_PROCESSOR_SMM_DESCRIPTOR ; -%define DSC_OFFSET 0xfb00 -
>>> %define DSC_GDTPTR 0x48 -%define DSC_GDTSIZ 0x50 -%define DSC_CS
>>> 0x14 -%define DSC_DS 0x16 -%define DSC_SS 0x18 -%define DSC_OTHERSEG
>>> 0x1a
>>> +; %define DSC_OFFSET 0xfb00
>>> +; %define DSC_GDTPTR 0x48
>>> +; %define DSC_GDTSIZ 0x50
>>> +;
>>> +%define DSC_CS 0x14
>>> +%define DSC_DS 0x16
>>> +%define DSC_SS 0x18
>>> +%define DSC_OTHERSEG 0x1a
>>>
>>> %define PROTECT_MODE_CS 0x8
>>> %define PROTECT_MODE_DS 0x20
>>> -%define TSS_SEGMENT 0x40
>>> +%define TSS_SEGMENT 0x40
>>>
>>> extern ASM_PFX(SmiRendezvous)
>>> extern ASM_PFX(FeaturePcdGet (PcdCpuSmmStackGuard)) @@ -51,6
>>> +54,10 @@ global ASM_PFX(gStmSmbase) global
>>> ASM_PFX(gStmXdSupported) extern ASM_PFX(gStmSmiHandlerIdtr)
>>>
>>> +extern ASM_PFX(gStmPsdOffset)
>>> +global ASM_PFX(gStmGdtSize)
>>> +global ASM_PFX(gStmGdtPtr)
>>> +
>>> ASM_PFX(gStmSmiCr3) EQU StmSmiCr3Patch - 4
>>> ASM_PFX(gStmSmiStack) EQU StmSmiStackPatch - 4
>>> ASM_PFX(gStmSmbase) EQU StmSmbasePatch - 4
>>> @@ -62,10 +69,18 @@ BITS 16
>>> ASM_PFX(gcStmSmiHandlerTemplate):
>>> _StmSmiEntryPoint:
>>> mov bx, _StmGdtDesc - _StmSmiEntryPoint + 0x8000
>>> - mov ax,[cs:DSC_OFFSET + DSC_GDTSIZ]
>>> +
>>> + mov eax, ASM_PFX(gStmGdtSize) ; mov ax, [cs:DSC_OFFSET +
>>> DSC_GDTSIZ]
>>> + mov si, [cs:eax] ;
>>> + mov ax, [cs:si] ;
>>> +
>>> dec ax
>>> mov [cs:bx], ax
>>> - mov eax, [cs:DSC_OFFSET + DSC_GDTPTR]
>>> +
>>> + mov eax, ASM_PFX(gStmGdtPtr) ; mov eax, [cs:DSC_OFFSET +
>>> DSC_GDTPTR]
>>> + mov si, [cs:eax] ;
>>> + mov eax, [cs:si] ;
>>> +
>>> mov [cs:bx + 2], eax
>>> mov ebp, eax ; ebp = GDT base
>>> o32 lgdt [cs:bx] ; lgdt fword ptr cs:[bx]
>>> @@ -166,7 +181,10 @@ StmXdSupportedPatch:
>>> mov ebx, cr0
>>> or ebx, 0x80010023 ; enable paging + WP + NE + MP + PE
>>> mov cr0, ebx
>>> - lea ebx, [edi + DSC_OFFSET]
>>> +
>>> + movzx esi, word [ASM_PFX(gStmPsdOffset)] ; lea ebx, [edi +
>>> DSC_OFFSET]
>>> + lea ebx, [edi + esi] ;
>>> +
>>> mov ax, [ebx + DSC_DS]
>>> mov ds, eax
>>> mov ax, [ebx + DSC_OTHERSEG]
>>> @@ -271,5 +289,8 @@ _StmSmiHandler:
>>> ; STM init finish
>>> jmp CommonHandler
>>>
>>> +ASM_PFX(gStmGdtSize) : RESW 1
>>> +ASM_PFX(gStmGdtPtr) : RESW 1
>>> +
>>> ASM_PFX(gcStmSmiHandlerSize) : DW $ - _StmSmiEntryPoint
>>> ASM_PFX(gcStmSmiHandlerOffset) : DW _StmSmiHandler -
>>> _StmSmiEntryPoint
>>> diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCommon.h
>>> b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCommon.h
>>> new file mode 100644
>>> index 0000000..78b3a5b
>>> --- /dev/null
>>> +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCommon.h
>>> @@ -0,0 +1,48 @@
>>> +/** @file
>>> + Common declarations
>>> +
>>> + Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>
>>> +
>>> + This program and the accompanying materials are licensed and made
>>> + available under the terms and conditions of the BSD License which
>>> + accompanies this distribution. The full text of the license may be
>>> + found at http://opensource.org/licenses/bsd-license.php.
>>> +
>>> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
>>> BASIS,
>>> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
>>> EXPRESS OR IMPLIED.
>>> +
>>> +**/
>>> +
>>> +#ifndef _SMM_COMMON_H_
>>> +#define _SMM_COMMON_H_
>>> +
>>> +#include <Register/Amd/Cpuid.h>
>>> +
>>> +//
>>> +// Definitions for AMD systems are based on contents of the // AMD64
>>> +Architecture Programmer's Manual // Volume 2: System Programming,
>>> +Section 10 System-Management Mode // #define
>>> +AMD_SMRAM_SAVE_STATE_MAP_OFFSET 0xfe00
>>> +#define AMD_SMM_PSD_OFFSET 0xfc00
>>> +
>>> +//
>>> +// External global variables for SMRAM offsets // extern UINT16
>>> +gSmramStateMapOffset; extern UINT16 gSmmPsdOffset;
>>> +
>>> +
>>> +/**
>>> + Determine if the standard CPU signature is "AuthenticAMD".
>>> +
>>> + @retval TRUE The CPU signature matches.
>>> + @retval FALSE The CPU signature does not match.
>>> +
>>> +**/
>>> +BOOLEAN
>>> +SmmStandardSignatureIsAuthenticAMD (
>>> + VOID
>>> + );
>>> +
>>> +#endif
>>> diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c
>>> b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c
>>> index 2d2bc6d..1c12095 100644
>>> --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c
>>> +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c
>>> @@ -1,14 +1,16 @@
>>> /** @file
>>> -The CPU specific programming for PiSmmCpuDxeSmm module.
>>> + The CPU specific programming for PiSmmCpuDxeSmm module.
>>>
>>> -Copyright (c) 2010 - 2016, Intel Corporation. All rights reserved.<BR> -This
>>> program and the accompanying materials -are licensed and made available
>>> under the terms and conditions of the BSD License -which accompanies this
>>> distribution. The full text of the license may be found at -
>>> http://opensource.org/licenses/bsd-license.php
>>> + Copyright (c) 2010 - 2016, Intel Corporation. All rights
>>> + reserved.<BR> Copyright (c) 2017, AMD Incorporated. All rights
>>> + reserved.<BR>
>>>
>>> -THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
>>> BASIS, -WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
>>> EXPRESS OR IMPLIED.
>>> + This program and the accompanying materials are licensed and made
>>> + available under the terms and conditions of the BSD License which
>>> + accompanies this distribution. The full text of the license may be
>>> + found at http://opensource.org/licenses/bsd-license.php
>>> +
>>> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
>>> BASIS,
>>> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
>>> EXPRESS OR IMPLIED.
>>>
>>> **/
>>>
>>> @@ -22,6 +24,8 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY
>>> KIND, EITHER EXPRESS OR IMPLIED.
>>> #include <Register/Cpuid.h>
>>> #include <Register/SmramSaveStateMap.h>
>>>
>>> +#include "SmmCommon.h"
>>> +
>>> //
>>> // Machine Specific Registers (MSRs)
>>> //
>>> @@ -41,6 +45,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY
>>> KIND, EITHER EXPRESS OR IMPLIED.
>>> #define SMM_FEATURES_LIB_IA32_MCA_CAP 0x17D
>>> #define SMM_CODE_ACCESS_CHK_BIT BIT58
>>>
>>> +
>>> /**
>>> Internal worker function that is called to complete CPU initialization at the
>>> end of SmmCpuFeaturesInitializeProcessor().
>>> @@ -77,6 +82,13 @@ BOOLEAN mNeedConfigureMtrrs = TRUE; //
>>> BOOLEAN *mSmrrEnabled;
>>>
>>> +//
>>> +// Set default value for SMRAM offset
>>> +// from <Register/SmramSaveStateMap.h> //
>>> +UINT16 gSmramStateMapOffset = SMRAM_SAVE_STATE_MAP_OFFSET;
>>> +
>>> +
>>> /**
>>> The constructor function
>>>
>>> @@ -99,6 +111,13 @@ SmmCpuFeaturesLibConstructor (
>>> UINTN ModelId;
>>>
>>> //
>>> + // Override SMRAM offset for AMD
>>> + //
>>> + if (SmmStandardSignatureIsAuthenticAMD ()) {
>>> + gSmramStateMapOffset = AMD_SMRAM_SAVE_STATE_MAP_OFFSET; }
>>> +
>>> + //
>>> // Retrieve CPU Family and Model
>>> //
>>> AsmCpuid (CPUID_VERSION_INFO, &RegEax, NULL, NULL, &RegEdx); @@ -
>>> 224,7 +243,7 @@ SmmCpuFeaturesInitializeProcessor (
>>> //
>>> // Configure SMBASE.
>>> //
>>> - CpuState = (SMRAM_SAVE_STATE_MAP
>>> *)(UINTN)(SMM_DEFAULT_SMBASE +
>>> SMRAM_SAVE_STATE_MAP_OFFSET);
>>> + CpuState = (SMRAM_SAVE_STATE_MAP
>>> *)(UINTN)(SMM_DEFAULT_SMBASE +
>>> + gSmramStateMapOffset);
>>> CpuState->x86.SMBASE = (UINT32)CpuHotPlugData->SmBase[CpuIndex];
>>>
>>> //
>>> @@ -630,3 +649,25 @@ SmmCpuFeaturesAllocatePageTableMemory (
>>> return NULL;
>>> }
>>>
>>> +
>>> +/**
>>> + Determine if the standard CPU signature is "AuthenticAMD".
>>> +
>>> + @retval TRUE The CPU signature matches.
>>> + @retval FALSE The CPU signature does not match.
>>> +
>>> +**/
>>> +BOOLEAN
>>> +SmmStandardSignatureIsAuthenticAMD (
>>> + VOID
>>> + )
>>> +{
>>> + UINT32 RegEbx;
>>> + UINT32 RegEcx;
>>> + UINT32 RegEdx;
>>> +
>>> + AsmCpuid (CPUID_SIGNATURE, NULL, &RegEbx, &RegEcx, &RegEdx);
>>> + return (RegEbx == CPUID_SIGNATURE_AUTHENTIC_AMD_EBX &&
>>> + RegEcx == CPUID_SIGNATURE_AUTHENTIC_AMD_ECX &&
>>> + RegEdx == CPUID_SIGNATURE_AUTHENTIC_AMD_EDX);
>>> +}
>>> diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf
>>> b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf
>>> index 77908b0..6a39d4b 100644
>>> --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf
>>> +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf
>>> @@ -2,6 +2,8 @@
>>> # The CPU specific programming for PiSmmCpuDxeSmm module.
>>> #
>>> # Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.<BR>
>>> +# Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR> #
>>> # This program and the accompanying materials # are licensed and made
>>> available under the terms and conditions of the BSD License # which
>>> accompanies this distribution. The full text of the license may be found at
>>> @@ -24,6 +26,7 @@
>>>
>>> [Sources]
>>> SmmCpuFeaturesLib.c
>>> + SmmCommon.h
>>> SmmCpuFeaturesLibNoStm.c
>>>
>>> [Packages]
>>> diff --git
>>> a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibStm.inf
>>> b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibStm.inf
>>> index db8dcdc..a76bed6 100644
>>> --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibStm.inf
>>> +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibStm.inf
>>> @@ -3,6 +3,8 @@
>>> # is included.
>>> #
>>> # Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.<BR>
>>> +# Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR> #
>>> # This program and the accompanying materials # are licensed and made
>>> available under the terms and conditions of the BSD License # which
>>> accompanies this distribution. The full text of the license may be found at
>>> @@ -25,6 +27,7 @@
>>>
>>> [Sources]
>>> SmmCpuFeaturesLib.c
>>> + SmmCommon.h
>>> SmmStm.c
>>> SmmStm.h
>>>
>>> diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c
>>> b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c
>>> index 45015b8..5f7c3db 100644
>>> --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c
>>> +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c
>>> @@ -2,6 +2,8 @@
>>> SMM STM support functions
>>>
>>> Copyright (c) 2015 - 2017, Intel Corporation. All rights reserved.<BR>
>>> + Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>
>>> +
>>> This program and the accompanying materials
>>> are licensed and made available under the terms and conditions of the BSD
>>> License
>>> which accompanies this distribution. The full text of the license may be
>>> found at @@ -28,6 +30,8 @@ #include <Protocol/MpService.h>
>>>
>>> #include "SmmStm.h"
>>> +#include "SmmCommon.h"
>>> +
>>>
>>> #define TXT_EVTYPE_BASE 0x400
>>> #define TXT_EVTYPE_STM_HASH (TXT_EVTYPE_BASE + 14)
>>> @@ -97,6 +101,20 @@ extern volatile UINT8
>>> gcStmSmiHandlerTemplate[];
>>> extern CONST UINT16 gcStmSmiHandlerSize;
>>> extern UINT16 gcStmSmiHandlerOffset;
>>> extern BOOLEAN gStmXdSupported;
>>> +extern UINT16 gStmGdtSize;
>>> +extern UINT16 gStmGdtPtr;
>>> +
>>> +//
>>> +// Constants relating to TXT_PROCESSOR_SMM_DESCRIPTOR //
>>> +#define TXT_PSD_GDTPTR 0x48
>>> +#define TXT_PSD_GDTSIZE 0x50
>>> +
>>> +//
>>> +// Set default value for PSD offset in SMRAM // from
>>> +<Register/StmApi.h> //
>>> +UINT16 gStmPsdOffset = TXT_SMM_PSD_OFFSET;
>>>
>>> //
>>> // Variables used by SMI Handler
>>> @@ -145,6 +163,19 @@ SmmCpuFeaturesLibStmConstructor (
>>> ASSERT_EFI_ERROR (Status);
>>>
>>> //
>>> + // Override PSD offset for AMD
>>> + //
>>> + if (SmmStandardSignatureIsAuthenticAMD ()) {
>>> + gStmPsdOffset = AMD_SMM_PSD_OFFSET; }
>>> +
>>> + //
>>> + // Initialize STM global variables associated with SMI Handler //
>>> + gStmGdtSize = gStmPsdOffset + TXT_PSD_GDTSIZE; gStmGdtPtr =
>>> + gStmPsdOffset + TXT_PSD_GDTPTR;
>>> +
>>> + //
>>> // Lookup the MP Services Protocol
>>> //
>>> Status = gBS->LocateProtocol (
>>> @@ -276,8 +307,8 @@ SmmCpuFeaturesInstallSmiHandler (
>>> UINT32 RegEdx;
>>> EFI_PROCESSOR_INFORMATION ProcessorInfo;
>>>
>>> - CopyMem ((VOID *)((UINTN)SmBase + TXT_SMM_PSD_OFFSET),
>>> &gcStmPsd, sizeof (gcStmPsd));
>>> - Psd = (TXT_PROCESSOR_SMM_DESCRIPTOR *)(VOID *)((UINTN)SmBase +
>>> TXT_SMM_PSD_OFFSET);
>>> + CopyMem ((VOID *)((UINTN)SmBase + gStmPsdOffset), &gcStmPsd,
>>> sizeof
>>> + (gcStmPsd)); Psd = (TXT_PROCESSOR_SMM_DESCRIPTOR *)(VOID
>>> + *)((UINTN)SmBase + gStmPsdOffset);
>>> Psd->SmmGdtPtr = GdtBase;
>>> Psd->SmmGdtSize = (UINT32)GdtSize;
>>>
>>> @@ -416,7 +447,7 @@ SmmEndOfDxeEventNotify (
>>> }
>>>
>>> for (Index = 0; Index < gSmst->NumberOfCpus; Index++) {
>>> - Psd = (TXT_PROCESSOR_SMM_DESCRIPTOR *)((UINTN)gSmst-
>>>> CpuSaveState[Index] - SMRAM_SAVE_STATE_MAP_OFFSET +
>>> TXT_SMM_PSD_OFFSET);
>>> + Psd = (TXT_PROCESSOR_SMM_DESCRIPTOR
>>> + *)((UINTN)gSmst->CpuSaveState[Index] - gSmramStateMapOffset +
>>> + gStmPsdOffset);
>>> DEBUG ((DEBUG_INFO, "Index=%d Psd=%p Rsdp=%p\n", Index, Psd,
>>> Rsdp));
>>> Psd->AcpiRsdp = (UINT64)(UINTN)Rsdp;
>>> }
>>> @@ -1266,7 +1297,7 @@ NotifyStmResourceChange (
>>> TXT_PROCESSOR_SMM_DESCRIPTOR *Psd;
>>>
>>> for (Index = 0; Index < gSmst->NumberOfCpus; Index++) {
>>> - Psd = (TXT_PROCESSOR_SMM_DESCRIPTOR *)((UINTN)gSmst-
>>>> CpuSaveState[Index] - SMRAM_SAVE_STATE_MAP_OFFSET +
>>> TXT_SMM_PSD_OFFSET);
>>> + Psd = (TXT_PROCESSOR_SMM_DESCRIPTOR
>>> + *)((UINTN)gSmst->CpuSaveState[Index] - gSmramStateMapOffset +
>>> + gStmPsdOffset);
>>> Psd->BiosHwResourceRequirementsPtr = (UINT64)(UINTN)StmResource;
>>> }
>>> return ;
>>> diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.S
>>> b/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.S
>>> index 1f9f91c..5f3386a 100644
>>> --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.S
>>> +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.S
>>> @@ -1,6 +1,8 @@
>>> #------------------------------------------------------------------------------
>>> #
>>> # Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.<BR>
>>> +# Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR> #
>>> # This program and the accompanying materials # are licensed and made
>>> available under the terms and conditions of the BSD License # which
>>> accompanies this distribution. The full text of the license may be found at
>>> @@ -27,6 +29,9 @@ ASM_GLOBAL ASM_PFX(gStmSmiStack) ASM_GLOBAL
>>> ASM_PFX(gStmSmbase) ASM_GLOBAL ASM_PFX(gStmXdSupported)
>>> ASM_GLOBAL ASM_PFX(gStmSmiHandlerIdtr)
>>> +ASM_GLOBAL ASM_PFX(gStmPsdOffset)
>>> +ASM_GLOBAL ASM_PFX(gStmGdtSize)
>>> +ASM_GLOBAL ASM_PFX(gStmGdtPtr)
>>>
>>> .equ MSR_IA32_MISC_ENABLE, 0x1A0
>>> .equ MSR_EFER, 0xc0000080
>>> @@ -35,12 +40,13 @@ ASM_GLOBAL ASM_PFX(gStmSmiHandlerIdtr) # #
>>> Constants relating to TXT_PROCESSOR_SMM_DESCRIPTOR #
>>> -.equ DSC_OFFSET, 0xfb00
>>> -.equ DSC_GDTPTR, 0x48
>>> -.equ DSC_GDTSIZ, 0x50
>>> -.equ DSC_CS, 0x14
>>> -.equ DSC_DS, 0x16
>>> -.equ DSC_SS, 0x18
>>> +# .equ DSC_OFFSET, 0xfb00
>>> +# .equ DSC_GDTPTR, 0x48
>>> +# .equ DSC_GDTSIZ, 0x50
>>> +#
>>> +.equ DSC_CS, 0x14
>>> +.equ DSC_DS, 0x16
>>> +.equ DSC_SS, 0x18
>>> .equ DSC_OTHERSEG, 0x1a
>>> #
>>> # Constants relating to CPU State Save Area @@ -71,12 +77,12 @@
>>> _StmSmiEntryPoint:
>>> # fix GDT descriptor
>>> #
>>> .byte 0x2e,0xa1 # mov ax, cs:[offset16]
>>> - .word DSC_OFFSET + DSC_GDTSIZ
>>> +ASM_PFX(gStmGdtSize): .space 2 # .word DSC_OFFSET + DSC_GDTSIZ
>>> .byte 0x48 # dec ax
>>> .byte 0x2e
>>> movl %eax, (%rdi) # mov cs:[bx], ax
>>> .byte 0x66,0x2e,0xa1 # mov eax, cs:[offset16]
>>> - .word DSC_OFFSET + DSC_GDTPTR
>>> +ASM_PFX(gStmGdtPtr): .space 2 # .word DSC_OFFSET + DSC_GDTPTR
>>> .byte 0x2e
>>> movw %ax, 2(%rdi)
>>> .byte 0x66,0x2e
>>> @@ -183,7 +189,11 @@ Base:
>>> LongMode: # long mode (64-bit code) starts here
>>> movabsq $ASM_PFX(gStmSmiHandlerIdtr), %rax
>>> lidt (%rax)
>>> - lea (DSC_OFFSET)(%rdi), %ebx
>>> +
>>> + movl $ASM_PFX(gStmPsdOffset), %ebx # lea (DSC_OFFSET)(%rdi),
>>> %ebx
>>> + movzxw (%ebx), %rsi
>>> + leal (%rdi, %rsi), %ebx
>>> +
>>> movw DSC_DS(%rbx), %ax
>>> movl %eax,%ds
>>> movw DSC_OTHERSEG(%rbx), %ax
>>> diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.asm
>>> b/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.asm
>>> index ad51e07..10913df 100644
>>> --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.asm
>>> +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.asm
>>> @@ -1,5 +1,7 @@
>>> ;------------------------------------------------------------------------------ ; ;
>>> Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.<BR>
>>> +; Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR> ;
>>> ; This program and the accompanying materials ; are licensed and made
>>> available under the terms and conditions of the BSD License ; which
>>> accompanies this distribution. The full text of the license may be found at
>>> @@ -32,6 +34,10 @@ EXTERNDEF gStmSmiStack:DWORD
>>> EXTERNDEF gStmSmbase:DWORD
>>> EXTERNDEF gStmXdSupported:BYTE
>>> EXTERNDEF gStmSmiHandlerIdtr:FWORD
>>> +EXTERNDEF gStmPsdOffset:WORD
>>> +EXTERNDEF gStmGdtSize:WORD
>>> +EXTERNDEF gStmGdtPtr:WORD
>>> +
>>>
>>> MSR_IA32_MISC_ENABLE EQU 1A0h
>>> MSR_EFER EQU 0c0000080h
>>> @@ -40,13 +46,14 @@ MSR_EFER_XD EQU 0800h
>>> ;
>>> ; Constants relating to TXT_PROCESSOR_SMM_DESCRIPTOR ;
>>> -DSC_OFFSET EQU 0fb00h
>>> -DSC_GDTPTR EQU 48h
>>> -DSC_GDTSIZ EQU 50h
>>> -DSC_CS EQU 14h
>>> -DSC_DS EQU 16h
>>> -DSC_SS EQU 18h
>>> -DSC_OTHERSEG EQU 1ah
>>> +; DSC_OFFSET EQU 0fb00h
>>> +; DSC_GDTPTR EQU 48h
>>> +; DSC_GDTSIZ EQU 50h
>>> +;
>>> +DSC_CS EQU 14h
>>> +DSC_DS EQU 16h
>>> +DSC_SS EQU 18h
>>> +DSC_OTHERSEG EQU 1ah
>>> ;
>>> ; Constants relating to CPU State Save Area ; @@ -74,12 +81,12 @@
>>> _StmSmiEntryPoint:
>>> DW offset _StmGdtDesc - _StmSmiEntryPoint + 8000h ; bx = GdtDesc
>>> offset
>>> ; fix GDT descriptor
>>> DB 2eh, 0a1h ; mov ax, cs:[offset16]
>>> - DW DSC_OFFSET + DSC_GDTSIZ
>>> +gStmGdtSize DW ? ; DSC_OFFSET + DSC_GDTSIZ
>>> DB 48h ; dec ax
>>> DB 2eh
>>> mov [rdi], eax ; mov cs:[bx], ax
>>> DB 66h, 2eh, 0a1h ; mov eax, cs:[offset16]
>>> - DW DSC_OFFSET + DSC_GDTPTR
>>> +gStmGdtPtr DW ? ; DSC_OFFSET + DSC_GDTPTR
>>> DB 2eh
>>> mov [rdi + 2], ax ; mov cs:[bx + 2], eax
>>> DB 66h, 2eh
>>> @@ -178,7 +185,10 @@ Base:
>>> @LongMode: ; long mode (64-bit code) starts here
>>> mov rax, offset gStmSmiHandlerIdtr
>>> lidt fword ptr [rax]
>>> - lea ebx, [rdi + DSC_OFFSET]
>>> +
>>> + movzx rsi, word ptr [gStmPsdOffset] ; lea ebx, [rdi + DSC_OFFSET]
>>> + lea ebx, [rdi + rsi] ;
>>> +
>>> mov ax, [rbx + DSC_DS]
>>> mov ds, eax
>>> mov ax, [rbx + DSC_OTHERSEG]
>>> diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.nasm
>>> b/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.nasm
>>> index bcac643..df4c5a2 100644
>>> --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.nasm
>>> +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.nasm
>>> @@ -1,5 +1,7 @@
>>> ;------------------------------------------------------------------------------ ; ;
>>> Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
>>> +; Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR> ;
>>> ; This program and the accompanying materials ; are licensed and made
>>> available under the terms and conditions of the BSD License ; which
>>> accompanies this distribution. The full text of the license may be found at
>>> @@ -29,13 +31,14 @@ ; ; Constants relating to
>>> TXT_PROCESSOR_SMM_DESCRIPTOR ; -%define DSC_OFFSET 0xfb00 -
>>> %define DSC_GDTPTR 0x48 -%define DSC_GDTSIZ 0x50 -%define DSC_CS
>>> 0x14 -%define DSC_DS 0x16 -%define DSC_SS 0x18 -%define DSC_OTHERSEG
>>> 0x1a
>>> +; %define DSC_OFFSET 0xfb00
>>> +; %define DSC_GDTPTR 0x48
>>> +; %define DSC_GDTSIZ 0x50
>>> +;
>>> +%define DSC_CS 0x14
>>> +%define DSC_DS 0x16
>>> +%define DSC_SS 0x18
>>> +%define DSC_OTHERSEG 0x1a
>>> ;
>>> ; Constants relating to CPU State Save Area ; @@ -44,9 +47,9 @@
>>>
>>> %define PROTECT_MODE_CS 0x8
>>> %define PROTECT_MODE_DS 0x20
>>> -%define LONG_MODE_CS 0x38
>>> -%define TSS_SEGMENT 0x40
>>> -%define GDT_SIZE 0x50
>>> +%define LONG_MODE_CS 0x38
>>> +%define TSS_SEGMENT 0x40
>>> +%define GDT_SIZE 0x50
>>>
>>> extern ASM_PFX(SmiRendezvous)
>>> extern ASM_PFX(gStmSmiHandlerIdtr)
>>> @@ -61,6 +64,10 @@ global ASM_PFX(gcStmSmiHandlerTemplate) global
>>> ASM_PFX(gcStmSmiHandlerSize) global ASM_PFX(gcStmSmiHandlerOffset)
>>>
>>> +extern ASM_PFX(gStmPsdOffset)
>>> +global ASM_PFX(gStmGdtSize)
>>> +global ASM_PFX(gStmGdtPtr)
>>> +
>>> ASM_PFX(gStmSmbase) EQU StmSmbasePatch - 4
>>> ASM_PFX(gStmSmiStack) EQU StmSmiStackPatch - 4
>>> ASM_PFX(gStmSmiCr3) EQU StmSmiCr3Patch - 4
>>> @@ -73,10 +80,18 @@ BITS 16
>>> ASM_PFX(gcStmSmiHandlerTemplate):
>>> _StmSmiEntryPoint:
>>> mov bx, _StmGdtDesc - _StmSmiEntryPoint + 0x8000
>>> - mov ax,[cs:DSC_OFFSET + DSC_GDTSIZ]
>>> +
>>> + mov eax, ASM_PFX(gStmGdtSize) ; mov ax, [cs:DSC_OFFSET +
>>> DSC_GDTSIZ]
>>> + mov si, [cs:eax] ;
>>> + mov ax, [cs:si] ;
>>> +
>>> dec ax
>>> mov [cs:bx], ax
>>> - mov eax, [cs:DSC_OFFSET + DSC_GDTPTR]
>>> +
>>> + mov eax, ASM_PFX(gStmGdtPtr) ; mov eax, [cs:DSC_OFFSET +
>>> DSC_GDTPTR]
>>> + mov si, [cs:eax] ;
>>> + mov eax, [cs:si] ;
>>> +
>>> mov [cs:bx + 2], eax
>>> o32 lgdt [cs:bx] ; lgdt fword ptr cs:[bx]
>>> mov ax, PROTECT_MODE_CS
>>> @@ -166,7 +181,10 @@ Base:
>>> @LongMode: ; long mode (64-bit code) starts here
>>> mov rax, ASM_PFX(gStmSmiHandlerIdtr)
>>> lidt [rax]
>>> - lea ebx, [rdi + DSC_OFFSET]
>>> +
>>> + movzx rsi, word [ASM_PFX(gStmPsdOffset)] ; lea ebx, [rdi +
>>> DSC_OFFSET]
>>> + lea ebx, [rdi + rsi] ;
>>> +
>>> mov ax, [rbx + DSC_DS]
>>> mov ds, eax
>>> mov ax, [rbx + DSC_OTHERSEG]
>>> @@ -262,5 +280,8 @@ _StmSmiHandler:
>>> ; STM init finish
>>> jmp CommonHandler
>>>
>>> +ASM_PFX(gStmGdtSize) : RESW 1
>>> +ASM_PFX(gStmGdtPtr) : RESW 1
>>> +
>>> ASM_PFX(gcStmSmiHandlerSize) : DW $ - _StmSmiEntryPoint
>>> ASM_PFX(gcStmSmiHandlerOffset) : DW _StmSmiHandler -
>>> _StmSmiEntryPoint
>>> --
>>> 2.7.4
>>
_______________________________________________
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https://lists.01.org/mailman/listinfo/edk2-devel
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH v5 1/2] UefiCpuPkg/SmmCpuFeaturesLib: Use global variables to replace macros
2017-10-18 1:50 ` Yao, Jiewen
@ 2017-10-18 14:36 ` Duran, Leo
2017-10-19 7:00 ` Laszlo Ersek
0 siblings, 1 reply; 30+ messages in thread
From: Duran, Leo @ 2017-10-18 14:36 UTC (permalink / raw)
To: 'Yao, Jiewen', Laszlo Ersek, Paolo Bonzini,
edk2-devel@lists.01.org
Cc: Ni, Ruiyu, Justen, Jordan L, Gao, Liming, Kinney, Michael D
Yao, Paolo, Lazlo, et al,
The offset disparity has proved manageable within SmmCpuFeaturesLib, so I’m inclined to leave macro definitions as-is and just drop this patch-set.
Agreed?
Leo.
From: Yao, Jiewen [mailto:jiewen.yao@intel.com]
Sent: Tuesday, October 17, 2017 8:51 PM
To: Laszlo Ersek <lersek@redhat.com>; Duran, Leo <leo.duran@amd.com>
Cc: Ni, Ruiyu <ruiyu.ni@intel.com>; Justen, Jordan L <jordan.l.justen@intel.com>; edk2-devel@lists.01.org; Gao, Liming <liming.gao@intel.com>; Kinney, Michael D <michael.d.kinney@intel.com>; Paolo Bonzini <pbonzini@redhat.com>
Subject: RE: [edk2] [PATCH v5 1/2] UefiCpuPkg/SmmCpuFeaturesLib: Use global variables to replace macros
Thanks. Then I think Paolo’s suggestion makes more sense.
If we can use same off, that would be great.
If no, just check AMD version ID in SaveState.
Thank you
Yao Jiewen
From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf Of Laszlo Ersek
Sent: Tuesday, October 17, 2017 11:15 PM
To: Yao, Jiewen <jiewen.yao@intel.com<mailto:jiewen.yao@intel.com>>; Duran, Leo <leo.duran@amd.com<mailto:leo.duran@amd.com>>
Cc: Ni, Ruiyu <ruiyu.ni@intel.com<mailto:ruiyu.ni@intel.com>>; Justen, Jordan L <jordan.l.justen@intel.com<mailto:jordan.l.justen@intel.com>>; edk2-devel@lists.01.org<mailto:edk2-devel@lists.01.org>; Gao, Liming <liming.gao@intel.com<mailto:liming.gao@intel.com>>; Kinney, Michael D <michael.d.kinney@intel.com<mailto:michael.d.kinney@intel.com>>; Paolo Bonzini <pbonzini@redhat.com<mailto:pbonzini@redhat.com>>
Subject: Re: [edk2] [PATCH v5 1/2] UefiCpuPkg/SmmCpuFeaturesLib: Use global variables to replace macros
On 10/17/17 16:50, Yao, Jiewen wrote:
> I think it is unnecessary. All intel CPU is using same offset. All amd CPU is using same offset. It can be identified easily by code.
> Adding a new API now is also an incompatible change because that requires all existing featurelib change to add a new API. We have lots of close source platform using its own featurelib.
>
> May I know what problem we are trying to resolve by adding a new API?
QEMU (and hence OVMF) uses the AMD save state map even when it emulates
Intel CPUs.
The reason is that the Intel SDM does not specify the Intel save state
map in sufficient detail (for emulation by QEMU), while the AMD spec
does. So, as an emulation target, only the AMD one is implementable in
QEMU (and supportable in OVMF), regardless of whether QEMU reports the
virtual CPU manufacturer as Intel vs. AMD.
If PiSmmCpuDxeSmm used a CPUID check, saw "Intel" as manufacturer, and
then used the Intel definition of the save state map, then
PiSmmCpuDxeSmm would break on QEMU / as part of OVMF.
Thanks,
Laszlo
>
>
> thank you!
> Yao, Jiewen
>
>
>> 在 2017年10月17日，下午10:20，Duran, Leo <leo.duran@amd.com<mailto:leo.duran@amd.com>> 写道：
>>
>> Yao, Lazlo, et al,
>>
>> For the SRAM_SAVE_STATE_MAP_OFFSET:
>> I propose returning the value by a function in SmmCpuFeaturesLib... Here's the rationale:
>> - The value is fixed per CPU architecture, so this qualifies as a CPU feature.
>> - The logic for CPU architecture detection would be in one place (e.g., PiSmmCpuDxeSmm would call the library function)
>> - The OVMF and Quark instances of the library could just return the current (default) value, so no compatibility issues.
>>
>> if you agree with this is an acceptable solution, I will submit a revised patch-set to address just the SRAM_SAVE_STATE_MAP_OFFSET.
>> (BTW, I'm re-evaluating the changes submitted for the PSD offset, with the goal of just using the default value and dropping those changes)
>>
>> Thanks,
>> Leo.
>>
>>> -----Original Message-----
>>> From: Duran, Leo
>>> Sent: Wednesday, October 11, 2017 2:46 PM
>>> To: edk2-devel@lists.01.org<mailto:edk2-devel@lists.01.org>
>>> Cc: Duran, Leo <leo.duran@amd.com<mailto:leo.duran@amd.com>>; Jiewen Yao
>>> <jiewen.yao@intel.com<mailto:jiewen.yao@intel.com>>; Ruiyu Ni <ruiyu.ni@intel.com<mailto:ruiyu.ni@intel.com>>; Michael D Kinney
>>> <michael.d.kinney@intel.com<mailto:michael.d.kinney@intel.com>>; Jordan Justen <jordan.l.justen@intel.com<mailto:jordan.l.justen@intel.com>>;
>>> Liming Gao <liming.gao@intel.com<mailto:liming.gao@intel.com>>
>>> Subject: [PATCH v5 1/2] UefiCpuPkg/SmmCpuFeaturesLib: Use global
>>> variables to replace macros
>>>
>>> Set global variables on Constructor function based on CPUID checks.
>>> The variables replace Intel macros to allow support on AMD x86 systems.
>>>
>>> Specifically, the replaced macros are:
>>> 1) SRAM_SAVE_STATE_MAP_OFFSET
>>> 2) TXT_SMM_PSD_OFFSET
>>>
>>> Cc: Jiewen Yao <jiewen.yao@intel.com<mailto:jiewen.yao@intel.com>>
>>> Cc: Ruiyu Ni <ruiyu.ni@intel.com<mailto:ruiyu.ni@intel.com>>
>>> Cc: Michael D Kinney <michael.d.kinney@intel.com<mailto:michael.d.kinney@intel.com>>
>>> Cc: Jordan Justen <jordan.l.justen@intel.com<mailto:jordan.l.justen@intel.com>>
>>> Cc: Liming Gao <liming.gao@intel.com<mailto:liming.gao@intel.com>>
>>> Contributed-under: TianoCore Contribution Agreement 1.1
>>> Signed-off-by: Leo Duran <leo.duran@amd.com<mailto:leo.duran@amd.com>>
>>> ---
>>> .../Library/SmmCpuFeaturesLib/Ia32/SmiEntry.S | 28 ++++++----
>>> .../Library/SmmCpuFeaturesLib/Ia32/SmiEntry.asm | 29 +++++++----
>>> .../Library/SmmCpuFeaturesLib/Ia32/SmiEntry.nasm | 43 ++++++++++++---
>>> -
>>> UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCommon.h | 48
>>> ++++++++++++++++++
>>> .../Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c | 59
>>> ++++++++++++++++++----
>>> .../SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf | 3 ++
>>> .../SmmCpuFeaturesLib/SmmCpuFeaturesLibStm.inf | 3 ++
>>> UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c | 39
>>> ++++++++++++--
>>> .../Library/SmmCpuFeaturesLib/X64/SmiEntry.S | 28 ++++++----
>>> .../Library/SmmCpuFeaturesLib/X64/SmiEntry.asm | 30 +++++++----
>>> .../Library/SmmCpuFeaturesLib/X64/SmiEntry.nasm | 47 ++++++++++++---
>>> --
>>> 11 files changed, 282 insertions(+), 75 deletions(-) create mode 100644
>>> UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCommon.h
>>>
>>> diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.S
>>> b/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.S
>>> index 4c0f8c8..c7b49d7 100644
>>> --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.S
>>> +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.S
>>> @@ -1,6 +1,8 @@
>>> #------------------------------------------------------------------------------
>>> #
>>> # Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.<BR>
>>> +# Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR> #
>>> # This program and the accompanying materials # are licensed and made
>>> available under the terms and conditions of the BSD License # which
>>> accompanies this distribution. The full text of the license may be found at
>>> @@ -28,6 +30,9 @@ ASM_GLOBAL ASM_PFX(gStmSmbase) ASM_GLOBAL
>>> ASM_PFX(gStmXdSupported) ASM_GLOBAL ASM_PFX(FeaturePcdGet
>>> (PcdCpuSmmStackGuard)) ASM_GLOBAL ASM_PFX(gStmSmiHandlerIdtr)
>>> +ASM_GLOBAL ASM_PFX(gStmPsdOffset)
>>> +ASM_GLOBAL ASM_PFX(gStmGdtSize)
>>> +ASM_GLOBAL ASM_PFX(gStmGdtPtr)
>>>
>>> .equ MSR_IA32_MISC_ENABLE, 0x1A0
>>> .equ MSR_EFER, 0xc0000080
>>> @@ -36,12 +41,13 @@ ASM_GLOBAL ASM_PFX(gStmSmiHandlerIdtr) # #
>>> Constants relating to TXT_PROCESSOR_SMM_DESCRIPTOR #
>>> -.equ DSC_OFFSET, 0xfb00
>>> -.equ DSC_GDTPTR, 0x48
>>> -.equ DSC_GDTSIZ, 0x50
>>> -.equ DSC_CS, 0x14
>>> -.equ DSC_DS, 0x16
>>> -.equ DSC_SS, 0x18
>>> +# .equ DSC_OFFSET, 0xfb00
>>> +# .equ DSC_GDTPTR, 0x48
>>> +# .equ DSC_GDTSIZ, 0x50
>>> +#
>>> +.equ DSC_CS, 0x14
>>> +.equ DSC_DS, 0x16
>>> +.equ DSC_SS, 0x18
>>> .equ DSC_OTHERSEG, 0x1A
>>>
>>> .equ PROTECT_MODE_CS, 0x08
>>> @@ -55,11 +61,11 @@ _StmSmiEntryPoint:
>>> .byte 0xbb # mov bx, imm16
>>> .word _StmGdtDesc - _StmSmiEntryPoint + 0x8000
>>> .byte 0x2e,0xa1 # mov ax, cs:[offset16]
>>> - .word DSC_OFFSET + DSC_GDTSIZ
>>> +ASM_PFX(gStmGdtSize): .space 2 # .word DSC_OFFSET + DSC_GDTSIZ
>>> decl %eax
>>> movl %eax, %cs:(%edi) # mov cs:[bx], ax
>>> .byte 0x66,0x2e,0xa1 # mov eax, cs:[offset16]
>>> - .word DSC_OFFSET + DSC_GDTPTR
>>> +ASM_PFX(gStmGdtPtr): .space 2 # .word DSC_OFFSET + DSC_GDTPTR
>>> movw %ax, %cs:2(%edi)
>>> movw %ax, %bp # ebp = GDT base
>>> .byte 0x66
>>> @@ -167,7 +173,11 @@ XdDone:
>>> movl %cr0, %ebx
>>> orl $0x080010023, %ebx # enable paging + WP + NE + MP + PE
>>> movl %ebx, %cr0
>>> - leal DSC_OFFSET(%edi),%ebx
>>> +
>>> + movl $ASM_PFX(gStmPsdOffset), %ebx # leal DSC_OFFSET(%edi),
>>> %ebx
>>> + movzxw (%ebx), %esi
>>> + leal (%edi, %esi), %ebx
>>> +
>>> movw DSC_DS(%ebx),%ax
>>> movl %eax, %ds
>>> movw DSC_OTHERSEG(%ebx),%ax
>>> diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.asm
>>> b/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.asm
>>> index 91dc1eb..4dbe276 100644
>>> --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.asm
>>> +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.asm
>>> @@ -1,5 +1,7 @@
>>> ;------------------------------------------------------------------------------ ; ;
>>> Copyright (c) 2009 - 2017, Intel Corporation. All rights reserved.<BR>
>>> +; Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR> ;
>>> ; This program and the accompanying materials ; are licensed and made
>>> available under the terms and conditions of the BSD License ; which
>>> accompanies this distribution. The full text of the license may be found at
>>> @@ -29,13 +31,14 @@ MSR_EFER_XD EQU 0800h
>>> ;
>>> ; Constants relating to TXT_PROCESSOR_SMM_DESCRIPTOR ;
>>> -DSC_OFFSET EQU 0fb00h
>>> -DSC_GDTPTR EQU 48h
>>> -DSC_GDTSIZ EQU 50h
>>> -DSC_CS EQU 14h
>>> -DSC_DS EQU 16h
>>> -DSC_SS EQU 18h
>>> -DSC_OTHERSEG EQU 1Ah
>>> +; DSC_OFFSET EQU 0fb00h
>>> +; DSC_GDTPTR EQU 48h
>>> +; DSC_GDTSIZ EQU 50h
>>> +;
>>> +DSC_CS EQU 14h
>>> +DSC_DS EQU 16h
>>> +DSC_SS EQU 18h
>>> +DSC_OTHERSEG EQU 1Ah
>>>
>>> PROTECT_MODE_CS EQU 08h
>>> PROTECT_MODE_DS EQU 20h
>>> @@ -54,6 +57,9 @@ EXTERNDEF gStmSmbase:DWORD
>>> EXTERNDEF gStmXdSupported:BYTE
>>> EXTERNDEF FeaturePcdGet (PcdCpuSmmStackGuard):BYTE
>>> EXTERNDEF gStmSmiHandlerIdtr:FWORD
>>> +EXTERNDEF gStmPsdOffset:WORD
>>> +EXTERNDEF gStmGdtSize:WORD
>>> +EXTERNDEF gStmGdtPtr:WORD
>>>
>>> .code
>>>
>>> @@ -63,11 +69,11 @@ _StmSmiEntryPoint:
>>> DB 0bbh ; mov bx, imm16
>>> DW offset _StmGdtDesc - _StmSmiEntryPoint + 8000h
>>> DB 2eh, 0a1h ; mov ax, cs:[offset16]
>>> - DW DSC_OFFSET + DSC_GDTSIZ
>>> +gStmGdtSize DW ? ; DSC_OFFSET + DSC_GDTSIZ
>>> dec eax
>>> mov cs:[edi], eax ; mov cs:[bx], ax
>>> DB 66h, 2eh, 0a1h ; mov eax, cs:[offset16]
>>> - DW DSC_OFFSET + DSC_GDTPTR
>>> +gStmGdtPtr DW ? ; DSC_OFFSET + DSC_GDTPTR
>>> mov cs:[edi + 2], ax ; mov cs:[bx + 2], eax
>>> mov bp, ax ; ebp = GDT base
>>> DB 66h
>>> @@ -174,7 +180,10 @@ gStmXdSupported DB 1
>>> mov ebx, cr0
>>> or ebx, 080010023h ; enable paging + WP + NE + MP + PE
>>> mov cr0, ebx
>>> - lea ebx, [edi + DSC_OFFSET]
>>> +
>>> + movzx esi, word ptr [gStmPsdOffset] ; lea ebx, [edi + DSC_OFFSET]
>>> + lea ebx, [edi + esi] ;
>>> +
>>> mov ax, [ebx + DSC_DS]
>>> mov ds, eax
>>> mov ax, [ebx + DSC_OTHERSEG]
>>> diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.nasm
>>> b/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.nasm
>>> index 00c0f067..023923a 100644
>>> --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.nasm
>>> +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.nasm
>>> @@ -1,5 +1,7 @@
>>> ;------------------------------------------------------------------------------ ; ;
>>> Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
>>> +; Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR> ;
>>> ; This program and the accompanying materials ; are licensed and made
>>> available under the terms and conditions of the BSD License ; which
>>> accompanies this distribution. The full text of the license may be found at
>>> @@ -25,17 +27,18 @@ ; ; Constants relating to
>>> TXT_PROCESSOR_SMM_DESCRIPTOR ; -%define DSC_OFFSET 0xfb00 -
>>> %define DSC_GDTPTR 0x48 -%define DSC_GDTSIZ 0x50 -%define DSC_CS
>>> 0x14 -%define DSC_DS 0x16 -%define DSC_SS 0x18 -%define DSC_OTHERSEG
>>> 0x1a
>>> +; %define DSC_OFFSET 0xfb00
>>> +; %define DSC_GDTPTR 0x48
>>> +; %define DSC_GDTSIZ 0x50
>>> +;
>>> +%define DSC_CS 0x14
>>> +%define DSC_DS 0x16
>>> +%define DSC_SS 0x18
>>> +%define DSC_OTHERSEG 0x1a
>>>
>>> %define PROTECT_MODE_CS 0x8
>>> %define PROTECT_MODE_DS 0x20
>>> -%define TSS_SEGMENT 0x40
>>> +%define TSS_SEGMENT 0x40
>>>
>>> extern ASM_PFX(SmiRendezvous)
>>> extern ASM_PFX(FeaturePcdGet (PcdCpuSmmStackGuard)) @@ -51,6
>>> +54,10 @@ global ASM_PFX(gStmSmbase) global
>>> ASM_PFX(gStmXdSupported) extern ASM_PFX(gStmSmiHandlerIdtr)
>>>
>>> +extern ASM_PFX(gStmPsdOffset)
>>> +global ASM_PFX(gStmGdtSize)
>>> +global ASM_PFX(gStmGdtPtr)
>>> +
>>> ASM_PFX(gStmSmiCr3) EQU StmSmiCr3Patch - 4
>>> ASM_PFX(gStmSmiStack) EQU StmSmiStackPatch - 4
>>> ASM_PFX(gStmSmbase) EQU StmSmbasePatch - 4
>>> @@ -62,10 +69,18 @@ BITS 16
>>> ASM_PFX(gcStmSmiHandlerTemplate):
>>> _StmSmiEntryPoint:
>>> mov bx, _StmGdtDesc - _StmSmiEntryPoint + 0x8000
>>> - mov ax,[cs:DSC_OFFSET + DSC_GDTSIZ]
>>> +
>>> + mov eax, ASM_PFX(gStmGdtSize) ; mov ax, [cs:DSC_OFFSET +
>>> DSC_GDTSIZ]
>>> + mov si, [cs:eax] ;
>>> + mov ax, [cs:si] ;
>>> +
>>> dec ax
>>> mov [cs:bx], ax
>>> - mov eax, [cs:DSC_OFFSET + DSC_GDTPTR]
>>> +
>>> + mov eax, ASM_PFX(gStmGdtPtr) ; mov eax, [cs:DSC_OFFSET +
>>> DSC_GDTPTR]
>>> + mov si, [cs:eax] ;
>>> + mov eax, [cs:si] ;
>>> +
>>> mov [cs:bx + 2], eax
>>> mov ebp, eax ; ebp = GDT base
>>> o32 lgdt [cs:bx] ; lgdt fword ptr cs:[bx]
>>> @@ -166,7 +181,10 @@ StmXdSupportedPatch:
>>> mov ebx, cr0
>>> or ebx, 0x80010023 ; enable paging + WP + NE + MP + PE
>>> mov cr0, ebx
>>> - lea ebx, [edi + DSC_OFFSET]
>>> +
>>> + movzx esi, word [ASM_PFX(gStmPsdOffset)] ; lea ebx, [edi +
>>> DSC_OFFSET]
>>> + lea ebx, [edi + esi] ;
>>> +
>>> mov ax, [ebx + DSC_DS]
>>> mov ds, eax
>>> mov ax, [ebx + DSC_OTHERSEG]
>>> @@ -271,5 +289,8 @@ _StmSmiHandler:
>>> ; STM init finish
>>> jmp CommonHandler
>>>
>>> +ASM_PFX(gStmGdtSize) : RESW 1
>>> +ASM_PFX(gStmGdtPtr) : RESW 1
>>> +
>>> ASM_PFX(gcStmSmiHandlerSize) : DW $ - _StmSmiEntryPoint
>>> ASM_PFX(gcStmSmiHandlerOffset) : DW _StmSmiHandler -
>>> _StmSmiEntryPoint
>>> diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCommon.h
>>> b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCommon.h
>>> new file mode 100644
>>> index 0000000..78b3a5b
>>> --- /dev/null
>>> +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCommon.h
>>> @@ -0,0 +1,48 @@
>>> +/** @file
>>> + Common declarations
>>> +
>>> + Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>
>>> +
>>> + This program and the accompanying materials are licensed and made
>>> + available under the terms and conditions of the BSD License which
>>> + accompanies this distribution. The full text of the license may be
>>> + found at http://opensource.org/licenses/bsd-license.php.
>>> +
>>> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
>>> BASIS,
>>> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
>>> EXPRESS OR IMPLIED.
>>> +
>>> +**/
>>> +
>>> +#ifndef _SMM_COMMON_H_
>>> +#define _SMM_COMMON_H_
>>> +
>>> +#include <Register/Amd/Cpuid.h>
>>> +
>>> +//
>>> +// Definitions for AMD systems are based on contents of the // AMD64
>>> +Architecture Programmer's Manual // Volume 2: System Programming,
>>> +Section 10 System-Management Mode // #define
>>> +AMD_SMRAM_SAVE_STATE_MAP_OFFSET 0xfe00
>>> +#define AMD_SMM_PSD_OFFSET 0xfc00
>>> +
>>> +//
>>> +// External global variables for SMRAM offsets // extern UINT16
>>> +gSmramStateMapOffset; extern UINT16 gSmmPsdOffset;
>>> +
>>> +
>>> +/**
>>> + Determine if the standard CPU signature is "AuthenticAMD".
>>> +
>>> + @retval TRUE The CPU signature matches.
>>> + @retval FALSE The CPU signature does not match.
>>> +
>>> +**/
>>> +BOOLEAN
>>> +SmmStandardSignatureIsAuthenticAMD (
>>> + VOID
>>> + );
>>> +
>>> +#endif
>>> diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c
>>> b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c
>>> index 2d2bc6d..1c12095 100644
>>> --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c
>>> +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c
>>> @@ -1,14 +1,16 @@
>>> /** @file
>>> -The CPU specific programming for PiSmmCpuDxeSmm module.
>>> + The CPU specific programming for PiSmmCpuDxeSmm module.
>>>
>>> -Copyright (c) 2010 - 2016, Intel Corporation. All rights reserved.<BR> -This
>>> program and the accompanying materials -are licensed and made available
>>> under the terms and conditions of the BSD License -which accompanies this
>>> distribution. The full text of the license may be found at -
>>> http://opensource.org/licenses/bsd-license.php
>>> + Copyright (c) 2010 - 2016, Intel Corporation. All rights
>>> + reserved.<BR> Copyright (c) 2017, AMD Incorporated. All rights
>>> + reserved.<BR>
>>>
>>> -THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
>>> BASIS, -WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
>>> EXPRESS OR IMPLIED.
>>> + This program and the accompanying materials are licensed and made
>>> + available under the terms and conditions of the BSD License which
>>> + accompanies this distribution. The full text of the license may be
>>> + found at http://opensource.org/licenses/bsd-license.php
>>> +
>>> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
>>> BASIS,
>>> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
>>> EXPRESS OR IMPLIED.
>>>
>>> **/
>>>
>>> @@ -22,6 +24,8 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY
>>> KIND, EITHER EXPRESS OR IMPLIED.
>>> #include <Register/Cpuid.h>
>>> #include <Register/SmramSaveStateMap.h>
>>>
>>> +#include "SmmCommon.h"
>>> +
>>> //
>>> // Machine Specific Registers (MSRs)
>>> //
>>> @@ -41,6 +45,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY
>>> KIND, EITHER EXPRESS OR IMPLIED.
>>> #define SMM_FEATURES_LIB_IA32_MCA_CAP 0x17D
>>> #define SMM_CODE_ACCESS_CHK_BIT BIT58
>>>
>>> +
>>> /**
>>> Internal worker function that is called to complete CPU initialization at the
>>> end of SmmCpuFeaturesInitializeProcessor().
>>> @@ -77,6 +82,13 @@ BOOLEAN mNeedConfigureMtrrs = TRUE; //
>>> BOOLEAN *mSmrrEnabled;
>>>
>>> +//
>>> +// Set default value for SMRAM offset
>>> +// from <Register/SmramSaveStateMap.h> //
>>> +UINT16 gSmramStateMapOffset = SMRAM_SAVE_STATE_MAP_OFFSET;
>>> +
>>> +
>>> /**
>>> The constructor function
>>>
>>> @@ -99,6 +111,13 @@ SmmCpuFeaturesLibConstructor (
>>> UINTN ModelId;
>>>
>>> //
>>> + // Override SMRAM offset for AMD
>>> + //
>>> + if (SmmStandardSignatureIsAuthenticAMD ()) {
>>> + gSmramStateMapOffset = AMD_SMRAM_SAVE_STATE_MAP_OFFSET; }
>>> +
>>> + //
>>> // Retrieve CPU Family and Model
>>> //
>>> AsmCpuid (CPUID_VERSION_INFO, &RegEax, NULL, NULL, &RegEdx); @@ -
>>> 224,7 +243,7 @@ SmmCpuFeaturesInitializeProcessor (
>>> //
>>> // Configure SMBASE.
>>> //
>>> - CpuState = (SMRAM_SAVE_STATE_MAP
>>> *)(UINTN)(SMM_DEFAULT_SMBASE +
>>> SMRAM_SAVE_STATE_MAP_OFFSET);
>>> + CpuState = (SMRAM_SAVE_STATE_MAP
>>> *)(UINTN)(SMM_DEFAULT_SMBASE +
>>> + gSmramStateMapOffset);
>>> CpuState->x86.SMBASE = (UINT32)CpuHotPlugData->SmBase[CpuIndex];
>>>
>>> //
>>> @@ -630,3 +649,25 @@ SmmCpuFeaturesAllocatePageTableMemory (
>>> return NULL;
>>> }
>>>
>>> +
>>> +/**
>>> + Determine if the standard CPU signature is "AuthenticAMD".
>>> +
>>> + @retval TRUE The CPU signature matches.
>>> + @retval FALSE The CPU signature does not match.
>>> +
>>> +**/
>>> +BOOLEAN
>>> +SmmStandardSignatureIsAuthenticAMD (
>>> + VOID
>>> + )
>>> +{
>>> + UINT32 RegEbx;
>>> + UINT32 RegEcx;
>>> + UINT32 RegEdx;
>>> +
>>> + AsmCpuid (CPUID_SIGNATURE, NULL, &RegEbx, &RegEcx, &RegEdx);
>>> + return (RegEbx == CPUID_SIGNATURE_AUTHENTIC_AMD_EBX &&
>>> + RegEcx == CPUID_SIGNATURE_AUTHENTIC_AMD_ECX &&
>>> + RegEdx == CPUID_SIGNATURE_AUTHENTIC_AMD_EDX);
>>> +}
>>> diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf
>>> b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf
>>> index 77908b0..6a39d4b 100644
>>> --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf
>>> +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf
>>> @@ -2,6 +2,8 @@
>>> # The CPU specific programming for PiSmmCpuDxeSmm module.
>>> #
>>> # Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.<BR>
>>> +# Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR> #
>>> # This program and the accompanying materials # are licensed and made
>>> available under the terms and conditions of the BSD License # which
>>> accompanies this distribution. The full text of the license may be found at
>>> @@ -24,6 +26,7 @@
>>>
>>> [Sources]
>>> SmmCpuFeaturesLib.c
>>> + SmmCommon.h
>>> SmmCpuFeaturesLibNoStm.c
>>>
>>> [Packages]
>>> diff --git
>>> a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibStm.inf
>>> b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibStm.inf
>>> index db8dcdc..a76bed6 100644
>>> --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibStm.inf
>>> +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibStm.inf
>>> @@ -3,6 +3,8 @@
>>> # is included.
>>> #
>>> # Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.<BR>
>>> +# Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR> #
>>> # This program and the accompanying materials # are licensed and made
>>> available under the terms and conditions of the BSD License # which
>>> accompanies this distribution. The full text of the license may be found at
>>> @@ -25,6 +27,7 @@
>>>
>>> [Sources]
>>> SmmCpuFeaturesLib.c
>>> + SmmCommon.h
>>> SmmStm.c
>>> SmmStm.h
>>>
>>> diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c
>>> b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c
>>> index 45015b8..5f7c3db 100644
>>> --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c
>>> +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c
>>> @@ -2,6 +2,8 @@
>>> SMM STM support functions
>>>
>>> Copyright (c) 2015 - 2017, Intel Corporation. All rights reserved.<BR>
>>> + Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>
>>> +
>>> This program and the accompanying materials
>>> are licensed and made available under the terms and conditions of the BSD
>>> License
>>> which accompanies this distribution. The full text of the license may be
>>> found at @@ -28,6 +30,8 @@ #include <Protocol/MpService.h>
>>>
>>> #include "SmmStm.h"
>>> +#include "SmmCommon.h"
>>> +
>>>
>>> #define TXT_EVTYPE_BASE 0x400
>>> #define TXT_EVTYPE_STM_HASH (TXT_EVTYPE_BASE + 14)
>>> @@ -97,6 +101,20 @@ extern volatile UINT8
>>> gcStmSmiHandlerTemplate[];
>>> extern CONST UINT16 gcStmSmiHandlerSize;
>>> extern UINT16 gcStmSmiHandlerOffset;
>>> extern BOOLEAN gStmXdSupported;
>>> +extern UINT16 gStmGdtSize;
>>> +extern UINT16 gStmGdtPtr;
>>> +
>>> +//
>>> +// Constants relating to TXT_PROCESSOR_SMM_DESCRIPTOR //
>>> +#define TXT_PSD_GDTPTR 0x48
>>> +#define TXT_PSD_GDTSIZE 0x50
>>> +
>>> +//
>>> +// Set default value for PSD offset in SMRAM // from
>>> +<Register/StmApi.h> //
>>> +UINT16 gStmPsdOffset = TXT_SMM_PSD_OFFSET;
>>>
>>> //
>>> // Variables used by SMI Handler
>>> @@ -145,6 +163,19 @@ SmmCpuFeaturesLibStmConstructor (
>>> ASSERT_EFI_ERROR (Status);
>>>
>>> //
>>> + // Override PSD offset for AMD
>>> + //
>>> + if (SmmStandardSignatureIsAuthenticAMD ()) {
>>> + gStmPsdOffset = AMD_SMM_PSD_OFFSET; }
>>> +
>>> + //
>>> + // Initialize STM global variables associated with SMI Handler //
>>> + gStmGdtSize = gStmPsdOffset + TXT_PSD_GDTSIZE; gStmGdtPtr =
>>> + gStmPsdOffset + TXT_PSD_GDTPTR;
>>> +
>>> + //
>>> // Lookup the MP Services Protocol
>>> //
>>> Status = gBS->LocateProtocol (
>>> @@ -276,8 +307,8 @@ SmmCpuFeaturesInstallSmiHandler (
>>> UINT32 RegEdx;
>>> EFI_PROCESSOR_INFORMATION ProcessorInfo;
>>>
>>> - CopyMem ((VOID *)((UINTN)SmBase + TXT_SMM_PSD_OFFSET),
>>> &gcStmPsd, sizeof (gcStmPsd));
>>> - Psd = (TXT_PROCESSOR_SMM_DESCRIPTOR *)(VOID *)((UINTN)SmBase +
>>> TXT_SMM_PSD_OFFSET);
>>> + CopyMem ((VOID *)((UINTN)SmBase + gStmPsdOffset), &gcStmPsd,
>>> sizeof
>>> + (gcStmPsd)); Psd = (TXT_PROCESSOR_SMM_DESCRIPTOR *)(VOID
>>> + *)((UINTN)SmBase + gStmPsdOffset);
>>> Psd->SmmGdtPtr = GdtBase;
>>> Psd->SmmGdtSize = (UINT32)GdtSize;
>>>
>>> @@ -416,7 +447,7 @@ SmmEndOfDxeEventNotify (
>>> }
>>>
>>> for (Index = 0; Index < gSmst->NumberOfCpus; Index++) {
>>> - Psd = (TXT_PROCESSOR_SMM_DESCRIPTOR *)((UINTN)gSmst-
>>>> CpuSaveState[Index] - SMRAM_SAVE_STATE_MAP_OFFSET +
>>> TXT_SMM_PSD_OFFSET);
>>> + Psd = (TXT_PROCESSOR_SMM_DESCRIPTOR
>>> + *)((UINTN)gSmst->CpuSaveState[Index] - gSmramStateMapOffset +
>>> + gStmPsdOffset);
>>> DEBUG ((DEBUG_INFO, "Index=%d Psd=%p Rsdp=%p\n", Index, Psd,
>>> Rsdp));
>>> Psd->AcpiRsdp = (UINT64)(UINTN)Rsdp;
>>> }
>>> @@ -1266,7 +1297,7 @@ NotifyStmResourceChange (
>>> TXT_PROCESSOR_SMM_DESCRIPTOR *Psd;
>>>
>>> for (Index = 0; Index < gSmst->NumberOfCpus; Index++) {
>>> - Psd = (TXT_PROCESSOR_SMM_DESCRIPTOR *)((UINTN)gSmst-
>>>> CpuSaveState[Index] - SMRAM_SAVE_STATE_MAP_OFFSET +
>>> TXT_SMM_PSD_OFFSET);
>>> + Psd = (TXT_PROCESSOR_SMM_DESCRIPTOR
>>> + *)((UINTN)gSmst->CpuSaveState[Index] - gSmramStateMapOffset +
>>> + gStmPsdOffset);
>>> Psd->BiosHwResourceRequirementsPtr = (UINT64)(UINTN)StmResource;
>>> }
>>> return ;
>>> diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.S
>>> b/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.S
>>> index 1f9f91c..5f3386a 100644
>>> --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.S
>>> +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.S
>>> @@ -1,6 +1,8 @@
>>> #------------------------------------------------------------------------------
>>> #
>>> # Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.<BR>
>>> +# Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR> #
>>> # This program and the accompanying materials # are licensed and made
>>> available under the terms and conditions of the BSD License # which
>>> accompanies this distribution. The full text of the license may be found at
>>> @@ -27,6 +29,9 @@ ASM_GLOBAL ASM_PFX(gStmSmiStack) ASM_GLOBAL
>>> ASM_PFX(gStmSmbase) ASM_GLOBAL ASM_PFX(gStmXdSupported)
>>> ASM_GLOBAL ASM_PFX(gStmSmiHandlerIdtr)
>>> +ASM_GLOBAL ASM_PFX(gStmPsdOffset)
>>> +ASM_GLOBAL ASM_PFX(gStmGdtSize)
>>> +ASM_GLOBAL ASM_PFX(gStmGdtPtr)
>>>
>>> .equ MSR_IA32_MISC_ENABLE, 0x1A0
>>> .equ MSR_EFER, 0xc0000080
>>> @@ -35,12 +40,13 @@ ASM_GLOBAL ASM_PFX(gStmSmiHandlerIdtr) # #
>>> Constants relating to TXT_PROCESSOR_SMM_DESCRIPTOR #
>>> -.equ DSC_OFFSET, 0xfb00
>>> -.equ DSC_GDTPTR, 0x48
>>> -.equ DSC_GDTSIZ, 0x50
>>> -.equ DSC_CS, 0x14
>>> -.equ DSC_DS, 0x16
>>> -.equ DSC_SS, 0x18
>>> +# .equ DSC_OFFSET, 0xfb00
>>> +# .equ DSC_GDTPTR, 0x48
>>> +# .equ DSC_GDTSIZ, 0x50
>>> +#
>>> +.equ DSC_CS, 0x14
>>> +.equ DSC_DS, 0x16
>>> +.equ DSC_SS, 0x18
>>> .equ DSC_OTHERSEG, 0x1a
>>> #
>>> # Constants relating to CPU State Save Area @@ -71,12 +77,12 @@
>>> _StmSmiEntryPoint:
>>> # fix GDT descriptor
>>> #
>>> .byte 0x2e,0xa1 # mov ax, cs:[offset16]
>>> - .word DSC_OFFSET + DSC_GDTSIZ
>>> +ASM_PFX(gStmGdtSize): .space 2 # .word DSC_OFFSET + DSC_GDTSIZ
>>> .byte 0x48 # dec ax
>>> .byte 0x2e
>>> movl %eax, (%rdi) # mov cs:[bx], ax
>>> .byte 0x66,0x2e,0xa1 # mov eax, cs:[offset16]
>>> - .word DSC_OFFSET + DSC_GDTPTR
>>> +ASM_PFX(gStmGdtPtr): .space 2 # .word DSC_OFFSET + DSC_GDTPTR
>>> .byte 0x2e
>>> movw %ax, 2(%rdi)
>>> .byte 0x66,0x2e
>>> @@ -183,7 +189,11 @@ Base:
>>> LongMode: # long mode (64-bit code) starts here
>>> movabsq $ASM_PFX(gStmSmiHandlerIdtr), %rax
>>> lidt (%rax)
>>> - lea (DSC_OFFSET)(%rdi), %ebx
>>> +
>>> + movl $ASM_PFX(gStmPsdOffset), %ebx # lea (DSC_OFFSET)(%rdi),
>>> %ebx
>>> + movzxw (%ebx), %rsi
>>> + leal (%rdi, %rsi), %ebx
>>> +
>>> movw DSC_DS(%rbx), %ax
>>> movl %eax,%ds
>>> movw DSC_OTHERSEG(%rbx), %ax
>>> diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.asm
>>> b/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.asm
>>> index ad51e07..10913df 100644
>>> --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.asm
>>> +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.asm
>>> @@ -1,5 +1,7 @@
>>> ;------------------------------------------------------------------------------ ; ;
>>> Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.<BR>
>>> +; Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR> ;
>>> ; This program and the accompanying materials ; are licensed and made
>>> available under the terms and conditions of the BSD License ; which
>>> accompanies this distribution. The full text of the license may be found at
>>> @@ -32,6 +34,10 @@ EXTERNDEF gStmSmiStack:DWORD
>>> EXTERNDEF gStmSmbase:DWORD
>>> EXTERNDEF gStmXdSupported:BYTE
>>> EXTERNDEF gStmSmiHandlerIdtr:FWORD
>>> +EXTERNDEF gStmPsdOffset:WORD
>>> +EXTERNDEF gStmGdtSize:WORD
>>> +EXTERNDEF gStmGdtPtr:WORD
>>> +
>>>
>>> MSR_IA32_MISC_ENABLE EQU 1A0h
>>> MSR_EFER EQU 0c0000080h
>>> @@ -40,13 +46,14 @@ MSR_EFER_XD EQU 0800h
>>> ;
>>> ; Constants relating to TXT_PROCESSOR_SMM_DESCRIPTOR ;
>>> -DSC_OFFSET EQU 0fb00h
>>> -DSC_GDTPTR EQU 48h
>>> -DSC_GDTSIZ EQU 50h
>>> -DSC_CS EQU 14h
>>> -DSC_DS EQU 16h
>>> -DSC_SS EQU 18h
>>> -DSC_OTHERSEG EQU 1ah
>>> +; DSC_OFFSET EQU 0fb00h
>>> +; DSC_GDTPTR EQU 48h
>>> +; DSC_GDTSIZ EQU 50h
>>> +;
>>> +DSC_CS EQU 14h
>>> +DSC_DS EQU 16h
>>> +DSC_SS EQU 18h
>>> +DSC_OTHERSEG EQU 1ah
>>> ;
>>> ; Constants relating to CPU State Save Area ; @@ -74,12 +81,12 @@
>>> _StmSmiEntryPoint:
>>> DW offset _StmGdtDesc - _StmSmiEntryPoint + 8000h ; bx = GdtDesc
>>> offset
>>> ; fix GDT descriptor
>>> DB 2eh, 0a1h ; mov ax, cs:[offset16]
>>> - DW DSC_OFFSET + DSC_GDTSIZ
>>> +gStmGdtSize DW ? ; DSC_OFFSET + DSC_GDTSIZ
>>> DB 48h ; dec ax
>>> DB 2eh
>>> mov [rdi], eax ; mov cs:[bx], ax
>>> DB 66h, 2eh, 0a1h ; mov eax, cs:[offset16]
>>> - DW DSC_OFFSET + DSC_GDTPTR
>>> +gStmGdtPtr DW ? ; DSC_OFFSET + DSC_GDTPTR
>>> DB 2eh
>>> mov [rdi + 2], ax ; mov cs:[bx + 2], eax
>>> DB 66h, 2eh
>>> @@ -178,7 +185,10 @@ Base:
>>> @LongMode: ; long mode (64-bit code) starts here
>>> mov rax, offset gStmSmiHandlerIdtr
>>> lidt fword ptr [rax]
>>> - lea ebx, [rdi + DSC_OFFSET]
>>> +
>>> + movzx rsi, word ptr [gStmPsdOffset] ; lea ebx, [rdi + DSC_OFFSET]
>>> + lea ebx, [rdi + rsi] ;
>>> +
>>> mov ax, [rbx + DSC_DS]
>>> mov ds, eax
>>> mov ax, [rbx + DSC_OTHERSEG]
>>> diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.nasm
>>> b/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.nasm
>>> index bcac643..df4c5a2 100644
>>> --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.nasm
>>> +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.nasm
>>> @@ -1,5 +1,7 @@
>>> ;------------------------------------------------------------------------------ ; ;
>>> Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
>>> +; Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR> ;
>>> ; This program and the accompanying materials ; are licensed and made
>>> available under the terms and conditions of the BSD License ; which
>>> accompanies this distribution. The full text of the license may be found at
>>> @@ -29,13 +31,14 @@ ; ; Constants relating to
>>> TXT_PROCESSOR_SMM_DESCRIPTOR ; -%define DSC_OFFSET 0xfb00 -
>>> %define DSC_GDTPTR 0x48 -%define DSC_GDTSIZ 0x50 -%define DSC_CS
>>> 0x14 -%define DSC_DS 0x16 -%define DSC_SS 0x18 -%define DSC_OTHERSEG
>>> 0x1a
>>> +; %define DSC_OFFSET 0xfb00
>>> +; %define DSC_GDTPTR 0x48
>>> +; %define DSC_GDTSIZ 0x50
>>> +;
>>> +%define DSC_CS 0x14
>>> +%define DSC_DS 0x16
>>> +%define DSC_SS 0x18
>>> +%define DSC_OTHERSEG 0x1a
>>> ;
>>> ; Constants relating to CPU State Save Area ; @@ -44,9 +47,9 @@
>>>
>>> %define PROTECT_MODE_CS 0x8
>>> %define PROTECT_MODE_DS 0x20
>>> -%define LONG_MODE_CS 0x38
>>> -%define TSS_SEGMENT 0x40
>>> -%define GDT_SIZE 0x50
>>> +%define LONG_MODE_CS 0x38
>>> +%define TSS_SEGMENT 0x40
>>> +%define GDT_SIZE 0x50
>>>
>>> extern ASM_PFX(SmiRendezvous)
>>> extern ASM_PFX(gStmSmiHandlerIdtr)
>>> @@ -61,6 +64,10 @@ global ASM_PFX(gcStmSmiHandlerTemplate) global
>>> ASM_PFX(gcStmSmiHandlerSize) global ASM_PFX(gcStmSmiHandlerOffset)
>>>
>>> +extern ASM_PFX(gStmPsdOffset)
>>> +global ASM_PFX(gStmGdtSize)
>>> +global ASM_PFX(gStmGdtPtr)
>>> +
>>> ASM_PFX(gStmSmbase) EQU StmSmbasePatch - 4
>>> ASM_PFX(gStmSmiStack) EQU StmSmiStackPatch - 4
>>> ASM_PFX(gStmSmiCr3) EQU StmSmiCr3Patch - 4
>>> @@ -73,10 +80,18 @@ BITS 16
>>> ASM_PFX(gcStmSmiHandlerTemplate):
>>> _StmSmiEntryPoint:
>>> mov bx, _StmGdtDesc - _StmSmiEntryPoint + 0x8000
>>> - mov ax,[cs:DSC_OFFSET + DSC_GDTSIZ]
>>> +
>>> + mov eax, ASM_PFX(gStmGdtSize) ; mov ax, [cs:DSC_OFFSET +
>>> DSC_GDTSIZ]
>>> + mov si, [cs:eax] ;
>>> + mov ax, [cs:si] ;
>>> +
>>> dec ax
>>> mov [cs:bx], ax
>>> - mov eax, [cs:DSC_OFFSET + DSC_GDTPTR]
>>> +
>>> + mov eax, ASM_PFX(gStmGdtPtr) ; mov eax, [cs:DSC_OFFSET +
>>> DSC_GDTPTR]
>>> + mov si, [cs:eax] ;
>>> + mov eax, [cs:si] ;
>>> +
>>> mov [cs:bx + 2], eax
>>> o32 lgdt [cs:bx] ; lgdt fword ptr cs:[bx]
>>> mov ax, PROTECT_MODE_CS
>>> @@ -166,7 +181,10 @@ Base:
>>> @LongMode: ; long mode (64-bit code) starts here
>>> mov rax, ASM_PFX(gStmSmiHandlerIdtr)
>>> lidt [rax]
>>> - lea ebx, [rdi + DSC_OFFSET]
>>> +
>>> + movzx rsi, word [ASM_PFX(gStmPsdOffset)] ; lea ebx, [rdi +
>>> DSC_OFFSET]
>>> + lea ebx, [rdi + rsi] ;
>>> +
>>> mov ax, [rbx + DSC_DS]
>>> mov ds, eax
>>> mov ax, [rbx + DSC_OTHERSEG]
>>> @@ -262,5 +280,8 @@ _StmSmiHandler:
>>> ; STM init finish
>>> jmp CommonHandler
>>>
>>> +ASM_PFX(gStmGdtSize) : RESW 1
>>> +ASM_PFX(gStmGdtPtr) : RESW 1
>>> +
>>> ASM_PFX(gcStmSmiHandlerSize) : DW $ - _StmSmiEntryPoint
>>> ASM_PFX(gcStmSmiHandlerOffset) : DW _StmSmiHandler -
>>> _StmSmiEntryPoint
>>> --
>>> 2.7.4
>>
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^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH v5 1/2] UefiCpuPkg/SmmCpuFeaturesLib: Use global variables to replace macros
2017-10-18 14:36 ` Duran, Leo
@ 2017-10-19 7:00 ` Laszlo Ersek
2017-10-19 17:02 ` Duran, Leo
0 siblings, 1 reply; 30+ messages in thread
From: Laszlo Ersek @ 2017-10-19 7:00 UTC (permalink / raw)
To: Duran, Leo, 'Yao, Jiewen', Paolo Bonzini,
edk2-devel@lists.01.org
Cc: Ni, Ruiyu, Justen, Jordan L, Gao, Liming, Kinney, Michael D
On 10/18/17 16:36, Duran, Leo wrote:
> Yao, Paolo, Lazlo, et al,
>
> The offset disparity has proved manageable within SmmCpuFeaturesLib, so I’m inclined to leave macro definitions as-is and just drop this patch-set.
>
> Agreed?
Sure.
Out of curiosity, what does it mean for you that the offset disparity is
manageable in SmmCpuFeaturesLib? Will you send a different patch (set)
for UefiCpuPkg/SmmCpuFeaturesLib, or does it concern an
SmmCpuFeaturesLib instance that is private to AMD?
Thanks!
Laszlo
> From: Yao, Jiewen [mailto:jiewen.yao@intel.com]
> Sent: Tuesday, October 17, 2017 8:51 PM
> To: Laszlo Ersek <lersek@redhat.com>; Duran, Leo <leo.duran@amd.com>
> Cc: Ni, Ruiyu <ruiyu.ni@intel.com>; Justen, Jordan L <jordan.l.justen@intel.com>; edk2-devel@lists.01.org; Gao, Liming <liming.gao@intel.com>; Kinney, Michael D <michael.d.kinney@intel.com>; Paolo Bonzini <pbonzini@redhat.com>
> Subject: RE: [edk2] [PATCH v5 1/2] UefiCpuPkg/SmmCpuFeaturesLib: Use global variables to replace macros
>
> Thanks. Then I think Paolo’s suggestion makes more sense.
>
> If we can use same off, that would be great.
> If no, just check AMD version ID in SaveState.
>
> Thank you
> Yao Jiewen
>
> From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf Of Laszlo Ersek
> Sent: Tuesday, October 17, 2017 11:15 PM
> To: Yao, Jiewen <jiewen.yao@intel.com<mailto:jiewen.yao@intel.com>>; Duran, Leo <leo.duran@amd.com<mailto:leo.duran@amd.com>>
> Cc: Ni, Ruiyu <ruiyu.ni@intel.com<mailto:ruiyu.ni@intel.com>>; Justen, Jordan L <jordan.l.justen@intel.com<mailto:jordan.l.justen@intel.com>>; edk2-devel@lists.01.org<mailto:edk2-devel@lists.01.org>; Gao, Liming <liming.gao@intel.com<mailto:liming.gao@intel.com>>; Kinney, Michael D <michael.d.kinney@intel.com<mailto:michael.d.kinney@intel.com>>; Paolo Bonzini <pbonzini@redhat.com<mailto:pbonzini@redhat.com>>
> Subject: Re: [edk2] [PATCH v5 1/2] UefiCpuPkg/SmmCpuFeaturesLib: Use global variables to replace macros
>
> On 10/17/17 16:50, Yao, Jiewen wrote:
>> I think it is unnecessary. All intel CPU is using same offset. All amd CPU is using same offset. It can be identified easily by code.
>> Adding a new API now is also an incompatible change because that requires all existing featurelib change to add a new API. We have lots of close source platform using its own featurelib.
>>
>> May I know what problem we are trying to resolve by adding a new API?
>
> QEMU (and hence OVMF) uses the AMD save state map even when it emulates
> Intel CPUs.
>
> The reason is that the Intel SDM does not specify the Intel save state
> map in sufficient detail (for emulation by QEMU), while the AMD spec
> does. So, as an emulation target, only the AMD one is implementable in
> QEMU (and supportable in OVMF), regardless of whether QEMU reports the
> virtual CPU manufacturer as Intel vs. AMD.
>
> If PiSmmCpuDxeSmm used a CPUID check, saw "Intel" as manufacturer, and
> then used the Intel definition of the save state map, then
> PiSmmCpuDxeSmm would break on QEMU / as part of OVMF.
>
> Thanks,
> Laszlo
>
>>
>>
>> thank you!
>> Yao, Jiewen
>>
>>
>>> 在 2017年10月17日，下午10:20，Duran, Leo <leo.duran@amd.com<mailto:leo.duran@amd.com>> 写道：
>>>
>>> Yao, Lazlo, et al,
>>>
>>> For the SRAM_SAVE_STATE_MAP_OFFSET:
>>> I propose returning the value by a function in SmmCpuFeaturesLib... Here's the rationale:
>>> - The value is fixed per CPU architecture, so this qualifies as a CPU feature.
>>> - The logic for CPU architecture detection would be in one place (e.g., PiSmmCpuDxeSmm would call the library function)
>>> - The OVMF and Quark instances of the library could just return the current (default) value, so no compatibility issues.
>>>
>>> if you agree with this is an acceptable solution, I will submit a revised patch-set to address just the SRAM_SAVE_STATE_MAP_OFFSET.
>>> (BTW, I'm re-evaluating the changes submitted for the PSD offset, with the goal of just using the default value and dropping those changes)
>>>
>>> Thanks,
>>> Leo.
>>>
>>>> -----Original Message-----
>>>> From: Duran, Leo
>>>> Sent: Wednesday, October 11, 2017 2:46 PM
>>>> To: edk2-devel@lists.01.org<mailto:edk2-devel@lists.01.org>
>>>> Cc: Duran, Leo <leo.duran@amd.com<mailto:leo.duran@amd.com>>; Jiewen Yao
>>>> <jiewen.yao@intel.com<mailto:jiewen.yao@intel.com>>; Ruiyu Ni <ruiyu.ni@intel.com<mailto:ruiyu.ni@intel.com>>; Michael D Kinney
>>>> <michael.d.kinney@intel.com<mailto:michael.d.kinney@intel.com>>; Jordan Justen <jordan.l.justen@intel.com<mailto:jordan.l.justen@intel.com>>;
>>>> Liming Gao <liming.gao@intel.com<mailto:liming.gao@intel.com>>
>>>> Subject: [PATCH v5 1/2] UefiCpuPkg/SmmCpuFeaturesLib: Use global
>>>> variables to replace macros
>>>>
>>>> Set global variables on Constructor function based on CPUID checks.
>>>> The variables replace Intel macros to allow support on AMD x86 systems.
>>>>
>>>> Specifically, the replaced macros are:
>>>> 1) SRAM_SAVE_STATE_MAP_OFFSET
>>>> 2) TXT_SMM_PSD_OFFSET
>>>>
>>>> Cc: Jiewen Yao <jiewen.yao@intel.com<mailto:jiewen.yao@intel.com>>
>>>> Cc: Ruiyu Ni <ruiyu.ni@intel.com<mailto:ruiyu.ni@intel.com>>
>>>> Cc: Michael D Kinney <michael.d.kinney@intel.com<mailto:michael.d.kinney@intel.com>>
>>>> Cc: Jordan Justen <jordan.l.justen@intel.com<mailto:jordan.l.justen@intel.com>>
>>>> Cc: Liming Gao <liming.gao@intel.com<mailto:liming.gao@intel.com>>
>>>> Contributed-under: TianoCore Contribution Agreement 1.1
>>>> Signed-off-by: Leo Duran <leo.duran@amd.com<mailto:leo.duran@amd.com>>
>>>> ---
>>>> .../Library/SmmCpuFeaturesLib/Ia32/SmiEntry.S | 28 ++++++----
>>>> .../Library/SmmCpuFeaturesLib/Ia32/SmiEntry.asm | 29 +++++++----
>>>> .../Library/SmmCpuFeaturesLib/Ia32/SmiEntry.nasm | 43 ++++++++++++---
>>>> -
>>>> UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCommon.h | 48
>>>> ++++++++++++++++++
>>>> .../Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c | 59
>>>> ++++++++++++++++++----
>>>> .../SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf | 3 ++
>>>> .../SmmCpuFeaturesLib/SmmCpuFeaturesLibStm.inf | 3 ++
>>>> UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c | 39
>>>> ++++++++++++--
>>>> .../Library/SmmCpuFeaturesLib/X64/SmiEntry.S | 28 ++++++----
>>>> .../Library/SmmCpuFeaturesLib/X64/SmiEntry.asm | 30 +++++++----
>>>> .../Library/SmmCpuFeaturesLib/X64/SmiEntry.nasm | 47 ++++++++++++---
>>>> --
>>>> 11 files changed, 282 insertions(+), 75 deletions(-) create mode 100644
>>>> UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCommon.h
>>>>
>>>> diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.S
>>>> b/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.S
>>>> index 4c0f8c8..c7b49d7 100644
>>>> --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.S
>>>> +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.S
>>>> @@ -1,6 +1,8 @@
>>>> #------------------------------------------------------------------------------
>>>> #
>>>> # Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.<BR>
>>>> +# Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR> #
>>>> # This program and the accompanying materials # are licensed and made
>>>> available under the terms and conditions of the BSD License # which
>>>> accompanies this distribution. The full text of the license may be found at
>>>> @@ -28,6 +30,9 @@ ASM_GLOBAL ASM_PFX(gStmSmbase) ASM_GLOBAL
>>>> ASM_PFX(gStmXdSupported) ASM_GLOBAL ASM_PFX(FeaturePcdGet
>>>> (PcdCpuSmmStackGuard)) ASM_GLOBAL ASM_PFX(gStmSmiHandlerIdtr)
>>>> +ASM_GLOBAL ASM_PFX(gStmPsdOffset)
>>>> +ASM_GLOBAL ASM_PFX(gStmGdtSize)
>>>> +ASM_GLOBAL ASM_PFX(gStmGdtPtr)
>>>>
>>>> .equ MSR_IA32_MISC_ENABLE, 0x1A0
>>>> .equ MSR_EFER, 0xc0000080
>>>> @@ -36,12 +41,13 @@ ASM_GLOBAL ASM_PFX(gStmSmiHandlerIdtr) # #
>>>> Constants relating to TXT_PROCESSOR_SMM_DESCRIPTOR #
>>>> -.equ DSC_OFFSET, 0xfb00
>>>> -.equ DSC_GDTPTR, 0x48
>>>> -.equ DSC_GDTSIZ, 0x50
>>>> -.equ DSC_CS, 0x14
>>>> -.equ DSC_DS, 0x16
>>>> -.equ DSC_SS, 0x18
>>>> +# .equ DSC_OFFSET, 0xfb00
>>>> +# .equ DSC_GDTPTR, 0x48
>>>> +# .equ DSC_GDTSIZ, 0x50
>>>> +#
>>>> +.equ DSC_CS, 0x14
>>>> +.equ DSC_DS, 0x16
>>>> +.equ DSC_SS, 0x18
>>>> .equ DSC_OTHERSEG, 0x1A
>>>>
>>>> .equ PROTECT_MODE_CS, 0x08
>>>> @@ -55,11 +61,11 @@ _StmSmiEntryPoint:
>>>> .byte 0xbb # mov bx, imm16
>>>> .word _StmGdtDesc - _StmSmiEntryPoint + 0x8000
>>>> .byte 0x2e,0xa1 # mov ax, cs:[offset16]
>>>> - .word DSC_OFFSET + DSC_GDTSIZ
>>>> +ASM_PFX(gStmGdtSize): .space 2 # .word DSC_OFFSET + DSC_GDTSIZ
>>>> decl %eax
>>>> movl %eax, %cs:(%edi) # mov cs:[bx], ax
>>>> .byte 0x66,0x2e,0xa1 # mov eax, cs:[offset16]
>>>> - .word DSC_OFFSET + DSC_GDTPTR
>>>> +ASM_PFX(gStmGdtPtr): .space 2 # .word DSC_OFFSET + DSC_GDTPTR
>>>> movw %ax, %cs:2(%edi)
>>>> movw %ax, %bp # ebp = GDT base
>>>> .byte 0x66
>>>> @@ -167,7 +173,11 @@ XdDone:
>>>> movl %cr0, %ebx
>>>> orl $0x080010023, %ebx # enable paging + WP + NE + MP + PE
>>>> movl %ebx, %cr0
>>>> - leal DSC_OFFSET(%edi),%ebx
>>>> +
>>>> + movl $ASM_PFX(gStmPsdOffset), %ebx # leal DSC_OFFSET(%edi),
>>>> %ebx
>>>> + movzxw (%ebx), %esi
>>>> + leal (%edi, %esi), %ebx
>>>> +
>>>> movw DSC_DS(%ebx),%ax
>>>> movl %eax, %ds
>>>> movw DSC_OTHERSEG(%ebx),%ax
>>>> diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.asm
>>>> b/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.asm
>>>> index 91dc1eb..4dbe276 100644
>>>> --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.asm
>>>> +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.asm
>>>> @@ -1,5 +1,7 @@
>>>> ;------------------------------------------------------------------------------ ; ;
>>>> Copyright (c) 2009 - 2017, Intel Corporation. All rights reserved.<BR>
>>>> +; Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR> ;
>>>> ; This program and the accompanying materials ; are licensed and made
>>>> available under the terms and conditions of the BSD License ; which
>>>> accompanies this distribution. The full text of the license may be found at
>>>> @@ -29,13 +31,14 @@ MSR_EFER_XD EQU 0800h
>>>> ;
>>>> ; Constants relating to TXT_PROCESSOR_SMM_DESCRIPTOR ;
>>>> -DSC_OFFSET EQU 0fb00h
>>>> -DSC_GDTPTR EQU 48h
>>>> -DSC_GDTSIZ EQU 50h
>>>> -DSC_CS EQU 14h
>>>> -DSC_DS EQU 16h
>>>> -DSC_SS EQU 18h
>>>> -DSC_OTHERSEG EQU 1Ah
>>>> +; DSC_OFFSET EQU 0fb00h
>>>> +; DSC_GDTPTR EQU 48h
>>>> +; DSC_GDTSIZ EQU 50h
>>>> +;
>>>> +DSC_CS EQU 14h
>>>> +DSC_DS EQU 16h
>>>> +DSC_SS EQU 18h
>>>> +DSC_OTHERSEG EQU 1Ah
>>>>
>>>> PROTECT_MODE_CS EQU 08h
>>>> PROTECT_MODE_DS EQU 20h
>>>> @@ -54,6 +57,9 @@ EXTERNDEF gStmSmbase:DWORD
>>>> EXTERNDEF gStmXdSupported:BYTE
>>>> EXTERNDEF FeaturePcdGet (PcdCpuSmmStackGuard):BYTE
>>>> EXTERNDEF gStmSmiHandlerIdtr:FWORD
>>>> +EXTERNDEF gStmPsdOffset:WORD
>>>> +EXTERNDEF gStmGdtSize:WORD
>>>> +EXTERNDEF gStmGdtPtr:WORD
>>>>
>>>> .code
>>>>
>>>> @@ -63,11 +69,11 @@ _StmSmiEntryPoint:
>>>> DB 0bbh ; mov bx, imm16
>>>> DW offset _StmGdtDesc - _StmSmiEntryPoint + 8000h
>>>> DB 2eh, 0a1h ; mov ax, cs:[offset16]
>>>> - DW DSC_OFFSET + DSC_GDTSIZ
>>>> +gStmGdtSize DW ? ; DSC_OFFSET + DSC_GDTSIZ
>>>> dec eax
>>>> mov cs:[edi], eax ; mov cs:[bx], ax
>>>> DB 66h, 2eh, 0a1h ; mov eax, cs:[offset16]
>>>> - DW DSC_OFFSET + DSC_GDTPTR
>>>> +gStmGdtPtr DW ? ; DSC_OFFSET + DSC_GDTPTR
>>>> mov cs:[edi + 2], ax ; mov cs:[bx + 2], eax
>>>> mov bp, ax ; ebp = GDT base
>>>> DB 66h
>>>> @@ -174,7 +180,10 @@ gStmXdSupported DB 1
>>>> mov ebx, cr0
>>>> or ebx, 080010023h ; enable paging + WP + NE + MP + PE
>>>> mov cr0, ebx
>>>> - lea ebx, [edi + DSC_OFFSET]
>>>> +
>>>> + movzx esi, word ptr [gStmPsdOffset] ; lea ebx, [edi + DSC_OFFSET]
>>>> + lea ebx, [edi + esi] ;
>>>> +
>>>> mov ax, [ebx + DSC_DS]
>>>> mov ds, eax
>>>> mov ax, [ebx + DSC_OTHERSEG]
>>>> diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.nasm
>>>> b/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.nasm
>>>> index 00c0f067..023923a 100644
>>>> --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.nasm
>>>> +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.nasm
>>>> @@ -1,5 +1,7 @@
>>>> ;------------------------------------------------------------------------------ ; ;
>>>> Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
>>>> +; Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR> ;
>>>> ; This program and the accompanying materials ; are licensed and made
>>>> available under the terms and conditions of the BSD License ; which
>>>> accompanies this distribution. The full text of the license may be found at
>>>> @@ -25,17 +27,18 @@ ; ; Constants relating to
>>>> TXT_PROCESSOR_SMM_DESCRIPTOR ; -%define DSC_OFFSET 0xfb00 -
>>>> %define DSC_GDTPTR 0x48 -%define DSC_GDTSIZ 0x50 -%define DSC_CS
>>>> 0x14 -%define DSC_DS 0x16 -%define DSC_SS 0x18 -%define DSC_OTHERSEG
>>>> 0x1a
>>>> +; %define DSC_OFFSET 0xfb00
>>>> +; %define DSC_GDTPTR 0x48
>>>> +; %define DSC_GDTSIZ 0x50
>>>> +;
>>>> +%define DSC_CS 0x14
>>>> +%define DSC_DS 0x16
>>>> +%define DSC_SS 0x18
>>>> +%define DSC_OTHERSEG 0x1a
>>>>
>>>> %define PROTECT_MODE_CS 0x8
>>>> %define PROTECT_MODE_DS 0x20
>>>> -%define TSS_SEGMENT 0x40
>>>> +%define TSS_SEGMENT 0x40
>>>>
>>>> extern ASM_PFX(SmiRendezvous)
>>>> extern ASM_PFX(FeaturePcdGet (PcdCpuSmmStackGuard)) @@ -51,6
>>>> +54,10 @@ global ASM_PFX(gStmSmbase) global
>>>> ASM_PFX(gStmXdSupported) extern ASM_PFX(gStmSmiHandlerIdtr)
>>>>
>>>> +extern ASM_PFX(gStmPsdOffset)
>>>> +global ASM_PFX(gStmGdtSize)
>>>> +global ASM_PFX(gStmGdtPtr)
>>>> +
>>>> ASM_PFX(gStmSmiCr3) EQU StmSmiCr3Patch - 4
>>>> ASM_PFX(gStmSmiStack) EQU StmSmiStackPatch - 4
>>>> ASM_PFX(gStmSmbase) EQU StmSmbasePatch - 4
>>>> @@ -62,10 +69,18 @@ BITS 16
>>>> ASM_PFX(gcStmSmiHandlerTemplate):
>>>> _StmSmiEntryPoint:
>>>> mov bx, _StmGdtDesc - _StmSmiEntryPoint + 0x8000
>>>> - mov ax,[cs:DSC_OFFSET + DSC_GDTSIZ]
>>>> +
>>>> + mov eax, ASM_PFX(gStmGdtSize) ; mov ax, [cs:DSC_OFFSET +
>>>> DSC_GDTSIZ]
>>>> + mov si, [cs:eax] ;
>>>> + mov ax, [cs:si] ;
>>>> +
>>>> dec ax
>>>> mov [cs:bx], ax
>>>> - mov eax, [cs:DSC_OFFSET + DSC_GDTPTR]
>>>> +
>>>> + mov eax, ASM_PFX(gStmGdtPtr) ; mov eax, [cs:DSC_OFFSET +
>>>> DSC_GDTPTR]
>>>> + mov si, [cs:eax] ;
>>>> + mov eax, [cs:si] ;
>>>> +
>>>> mov [cs:bx + 2], eax
>>>> mov ebp, eax ; ebp = GDT base
>>>> o32 lgdt [cs:bx] ; lgdt fword ptr cs:[bx]
>>>> @@ -166,7 +181,10 @@ StmXdSupportedPatch:
>>>> mov ebx, cr0
>>>> or ebx, 0x80010023 ; enable paging + WP + NE + MP + PE
>>>> mov cr0, ebx
>>>> - lea ebx, [edi + DSC_OFFSET]
>>>> +
>>>> + movzx esi, word [ASM_PFX(gStmPsdOffset)] ; lea ebx, [edi +
>>>> DSC_OFFSET]
>>>> + lea ebx, [edi + esi] ;
>>>> +
>>>> mov ax, [ebx + DSC_DS]
>>>> mov ds, eax
>>>> mov ax, [ebx + DSC_OTHERSEG]
>>>> @@ -271,5 +289,8 @@ _StmSmiHandler:
>>>> ; STM init finish
>>>> jmp CommonHandler
>>>>
>>>> +ASM_PFX(gStmGdtSize) : RESW 1
>>>> +ASM_PFX(gStmGdtPtr) : RESW 1
>>>> +
>>>> ASM_PFX(gcStmSmiHandlerSize) : DW $ - _StmSmiEntryPoint
>>>> ASM_PFX(gcStmSmiHandlerOffset) : DW _StmSmiHandler -
>>>> _StmSmiEntryPoint
>>>> diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCommon.h
>>>> b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCommon.h
>>>> new file mode 100644
>>>> index 0000000..78b3a5b
>>>> --- /dev/null
>>>> +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCommon.h
>>>> @@ -0,0 +1,48 @@
>>>> +/** @file
>>>> + Common declarations
>>>> +
>>>> + Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>
>>>> +
>>>> + This program and the accompanying materials are licensed and made
>>>> + available under the terms and conditions of the BSD License which
>>>> + accompanies this distribution. The full text of the license may be
>>>> + found at http://opensource.org/licenses/bsd-license.php.
>>>> +
>>>> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
>>>> BASIS,
>>>> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
>>>> EXPRESS OR IMPLIED.
>>>> +
>>>> +**/
>>>> +
>>>> +#ifndef _SMM_COMMON_H_
>>>> +#define _SMM_COMMON_H_
>>>> +
>>>> +#include <Register/Amd/Cpuid.h>
>>>> +
>>>> +//
>>>> +// Definitions for AMD systems are based on contents of the // AMD64
>>>> +Architecture Programmer's Manual // Volume 2: System Programming,
>>>> +Section 10 System-Management Mode // #define
>>>> +AMD_SMRAM_SAVE_STATE_MAP_OFFSET 0xfe00
>>>> +#define AMD_SMM_PSD_OFFSET 0xfc00
>>>> +
>>>> +//
>>>> +// External global variables for SMRAM offsets // extern UINT16
>>>> +gSmramStateMapOffset; extern UINT16 gSmmPsdOffset;
>>>> +
>>>> +
>>>> +/**
>>>> + Determine if the standard CPU signature is "AuthenticAMD".
>>>> +
>>>> + @retval TRUE The CPU signature matches.
>>>> + @retval FALSE The CPU signature does not match.
>>>> +
>>>> +**/
>>>> +BOOLEAN
>>>> +SmmStandardSignatureIsAuthenticAMD (
>>>> + VOID
>>>> + );
>>>> +
>>>> +#endif
>>>> diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c
>>>> b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c
>>>> index 2d2bc6d..1c12095 100644
>>>> --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c
>>>> +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c
>>>> @@ -1,14 +1,16 @@
>>>> /** @file
>>>> -The CPU specific programming for PiSmmCpuDxeSmm module.
>>>> + The CPU specific programming for PiSmmCpuDxeSmm module.
>>>>
>>>> -Copyright (c) 2010 - 2016, Intel Corporation. All rights reserved.<BR> -This
>>>> program and the accompanying materials -are licensed and made available
>>>> under the terms and conditions of the BSD License -which accompanies this
>>>> distribution. The full text of the license may be found at -
>>>> http://opensource.org/licenses/bsd-license.php
>>>> + Copyright (c) 2010 - 2016, Intel Corporation. All rights
>>>> + reserved.<BR> Copyright (c) 2017, AMD Incorporated. All rights
>>>> + reserved.<BR>
>>>>
>>>> -THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
>>>> BASIS, -WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
>>>> EXPRESS OR IMPLIED.
>>>> + This program and the accompanying materials are licensed and made
>>>> + available under the terms and conditions of the BSD License which
>>>> + accompanies this distribution. The full text of the license may be
>>>> + found at http://opensource.org/licenses/bsd-license.php
>>>> +
>>>> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
>>>> BASIS,
>>>> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
>>>> EXPRESS OR IMPLIED.
>>>>
>>>> **/
>>>>
>>>> @@ -22,6 +24,8 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY
>>>> KIND, EITHER EXPRESS OR IMPLIED.
>>>> #include <Register/Cpuid.h>
>>>> #include <Register/SmramSaveStateMap.h>
>>>>
>>>> +#include "SmmCommon.h"
>>>> +
>>>> //
>>>> // Machine Specific Registers (MSRs)
>>>> //
>>>> @@ -41,6 +45,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY
>>>> KIND, EITHER EXPRESS OR IMPLIED.
>>>> #define SMM_FEATURES_LIB_IA32_MCA_CAP 0x17D
>>>> #define SMM_CODE_ACCESS_CHK_BIT BIT58
>>>>
>>>> +
>>>> /**
>>>> Internal worker function that is called to complete CPU initialization at the
>>>> end of SmmCpuFeaturesInitializeProcessor().
>>>> @@ -77,6 +82,13 @@ BOOLEAN mNeedConfigureMtrrs = TRUE; //
>>>> BOOLEAN *mSmrrEnabled;
>>>>
>>>> +//
>>>> +// Set default value for SMRAM offset
>>>> +// from <Register/SmramSaveStateMap.h> //
>>>> +UINT16 gSmramStateMapOffset = SMRAM_SAVE_STATE_MAP_OFFSET;
>>>> +
>>>> +
>>>> /**
>>>> The constructor function
>>>>
>>>> @@ -99,6 +111,13 @@ SmmCpuFeaturesLibConstructor (
>>>> UINTN ModelId;
>>>>
>>>> //
>>>> + // Override SMRAM offset for AMD
>>>> + //
>>>> + if (SmmStandardSignatureIsAuthenticAMD ()) {
>>>> + gSmramStateMapOffset = AMD_SMRAM_SAVE_STATE_MAP_OFFSET; }
>>>> +
>>>> + //
>>>> // Retrieve CPU Family and Model
>>>> //
>>>> AsmCpuid (CPUID_VERSION_INFO, &RegEax, NULL, NULL, &RegEdx); @@ -
>>>> 224,7 +243,7 @@ SmmCpuFeaturesInitializeProcessor (
>>>> //
>>>> // Configure SMBASE.
>>>> //
>>>> - CpuState = (SMRAM_SAVE_STATE_MAP
>>>> *)(UINTN)(SMM_DEFAULT_SMBASE +
>>>> SMRAM_SAVE_STATE_MAP_OFFSET);
>>>> + CpuState = (SMRAM_SAVE_STATE_MAP
>>>> *)(UINTN)(SMM_DEFAULT_SMBASE +
>>>> + gSmramStateMapOffset);
>>>> CpuState->x86.SMBASE = (UINT32)CpuHotPlugData->SmBase[CpuIndex];
>>>>
>>>> //
>>>> @@ -630,3 +649,25 @@ SmmCpuFeaturesAllocatePageTableMemory (
>>>> return NULL;
>>>> }
>>>>
>>>> +
>>>> +/**
>>>> + Determine if the standard CPU signature is "AuthenticAMD".
>>>> +
>>>> + @retval TRUE The CPU signature matches.
>>>> + @retval FALSE The CPU signature does not match.
>>>> +
>>>> +**/
>>>> +BOOLEAN
>>>> +SmmStandardSignatureIsAuthenticAMD (
>>>> + VOID
>>>> + )
>>>> +{
>>>> + UINT32 RegEbx;
>>>> + UINT32 RegEcx;
>>>> + UINT32 RegEdx;
>>>> +
>>>> + AsmCpuid (CPUID_SIGNATURE, NULL, &RegEbx, &RegEcx, &RegEdx);
>>>> + return (RegEbx == CPUID_SIGNATURE_AUTHENTIC_AMD_EBX &&
>>>> + RegEcx == CPUID_SIGNATURE_AUTHENTIC_AMD_ECX &&
>>>> + RegEdx == CPUID_SIGNATURE_AUTHENTIC_AMD_EDX);
>>>> +}
>>>> diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf
>>>> b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf
>>>> index 77908b0..6a39d4b 100644
>>>> --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf
>>>> +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf
>>>> @@ -2,6 +2,8 @@
>>>> # The CPU specific programming for PiSmmCpuDxeSmm module.
>>>> #
>>>> # Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.<BR>
>>>> +# Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR> #
>>>> # This program and the accompanying materials # are licensed and made
>>>> available under the terms and conditions of the BSD License # which
>>>> accompanies this distribution. The full text of the license may be found at
>>>> @@ -24,6 +26,7 @@
>>>>
>>>> [Sources]
>>>> SmmCpuFeaturesLib.c
>>>> + SmmCommon.h
>>>> SmmCpuFeaturesLibNoStm.c
>>>>
>>>> [Packages]
>>>> diff --git
>>>> a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibStm.inf
>>>> b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibStm.inf
>>>> index db8dcdc..a76bed6 100644
>>>> --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibStm.inf
>>>> +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibStm.inf
>>>> @@ -3,6 +3,8 @@
>>>> # is included.
>>>> #
>>>> # Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.<BR>
>>>> +# Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR> #
>>>> # This program and the accompanying materials # are licensed and made
>>>> available under the terms and conditions of the BSD License # which
>>>> accompanies this distribution. The full text of the license may be found at
>>>> @@ -25,6 +27,7 @@
>>>>
>>>> [Sources]
>>>> SmmCpuFeaturesLib.c
>>>> + SmmCommon.h
>>>> SmmStm.c
>>>> SmmStm.h
>>>>
>>>> diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c
>>>> b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c
>>>> index 45015b8..5f7c3db 100644
>>>> --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c
>>>> +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c
>>>> @@ -2,6 +2,8 @@
>>>> SMM STM support functions
>>>>
>>>> Copyright (c) 2015 - 2017, Intel Corporation. All rights reserved.<BR>
>>>> + Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>
>>>> +
>>>> This program and the accompanying materials
>>>> are licensed and made available under the terms and conditions of the BSD
>>>> License
>>>> which accompanies this distribution. The full text of the license may be
>>>> found at @@ -28,6 +30,8 @@ #include <Protocol/MpService.h>
>>>>
>>>> #include "SmmStm.h"
>>>> +#include "SmmCommon.h"
>>>> +
>>>>
>>>> #define TXT_EVTYPE_BASE 0x400
>>>> #define TXT_EVTYPE_STM_HASH (TXT_EVTYPE_BASE + 14)
>>>> @@ -97,6 +101,20 @@ extern volatile UINT8
>>>> gcStmSmiHandlerTemplate[];
>>>> extern CONST UINT16 gcStmSmiHandlerSize;
>>>> extern UINT16 gcStmSmiHandlerOffset;
>>>> extern BOOLEAN gStmXdSupported;
>>>> +extern UINT16 gStmGdtSize;
>>>> +extern UINT16 gStmGdtPtr;
>>>> +
>>>> +//
>>>> +// Constants relating to TXT_PROCESSOR_SMM_DESCRIPTOR //
>>>> +#define TXT_PSD_GDTPTR 0x48
>>>> +#define TXT_PSD_GDTSIZE 0x50
>>>> +
>>>> +//
>>>> +// Set default value for PSD offset in SMRAM // from
>>>> +<Register/StmApi.h> //
>>>> +UINT16 gStmPsdOffset = TXT_SMM_PSD_OFFSET;
>>>>
>>>> //
>>>> // Variables used by SMI Handler
>>>> @@ -145,6 +163,19 @@ SmmCpuFeaturesLibStmConstructor (
>>>> ASSERT_EFI_ERROR (Status);
>>>>
>>>> //
>>>> + // Override PSD offset for AMD
>>>> + //
>>>> + if (SmmStandardSignatureIsAuthenticAMD ()) {
>>>> + gStmPsdOffset = AMD_SMM_PSD_OFFSET; }
>>>> +
>>>> + //
>>>> + // Initialize STM global variables associated with SMI Handler //
>>>> + gStmGdtSize = gStmPsdOffset + TXT_PSD_GDTSIZE; gStmGdtPtr =
>>>> + gStmPsdOffset + TXT_PSD_GDTPTR;
>>>> +
>>>> + //
>>>> // Lookup the MP Services Protocol
>>>> //
>>>> Status = gBS->LocateProtocol (
>>>> @@ -276,8 +307,8 @@ SmmCpuFeaturesInstallSmiHandler (
>>>> UINT32 RegEdx;
>>>> EFI_PROCESSOR_INFORMATION ProcessorInfo;
>>>>
>>>> - CopyMem ((VOID *)((UINTN)SmBase + TXT_SMM_PSD_OFFSET),
>>>> &gcStmPsd, sizeof (gcStmPsd));
>>>> - Psd = (TXT_PROCESSOR_SMM_DESCRIPTOR *)(VOID *)((UINTN)SmBase +
>>>> TXT_SMM_PSD_OFFSET);
>>>> + CopyMem ((VOID *)((UINTN)SmBase + gStmPsdOffset), &gcStmPsd,
>>>> sizeof
>>>> + (gcStmPsd)); Psd = (TXT_PROCESSOR_SMM_DESCRIPTOR *)(VOID
>>>> + *)((UINTN)SmBase + gStmPsdOffset);
>>>> Psd->SmmGdtPtr = GdtBase;
>>>> Psd->SmmGdtSize = (UINT32)GdtSize;
>>>>
>>>> @@ -416,7 +447,7 @@ SmmEndOfDxeEventNotify (
>>>> }
>>>>
>>>> for (Index = 0; Index < gSmst->NumberOfCpus; Index++) {
>>>> - Psd = (TXT_PROCESSOR_SMM_DESCRIPTOR *)((UINTN)gSmst-
>>>>> CpuSaveState[Index] - SMRAM_SAVE_STATE_MAP_OFFSET +
>>>> TXT_SMM_PSD_OFFSET);
>>>> + Psd = (TXT_PROCESSOR_SMM_DESCRIPTOR
>>>> + *)((UINTN)gSmst->CpuSaveState[Index] - gSmramStateMapOffset +
>>>> + gStmPsdOffset);
>>>> DEBUG ((DEBUG_INFO, "Index=%d Psd=%p Rsdp=%p\n", Index, Psd,
>>>> Rsdp));
>>>> Psd->AcpiRsdp = (UINT64)(UINTN)Rsdp;
>>>> }
>>>> @@ -1266,7 +1297,7 @@ NotifyStmResourceChange (
>>>> TXT_PROCESSOR_SMM_DESCRIPTOR *Psd;
>>>>
>>>> for (Index = 0; Index < gSmst->NumberOfCpus; Index++) {
>>>> - Psd = (TXT_PROCESSOR_SMM_DESCRIPTOR *)((UINTN)gSmst-
>>>>> CpuSaveState[Index] - SMRAM_SAVE_STATE_MAP_OFFSET +
>>>> TXT_SMM_PSD_OFFSET);
>>>> + Psd = (TXT_PROCESSOR_SMM_DESCRIPTOR
>>>> + *)((UINTN)gSmst->CpuSaveState[Index] - gSmramStateMapOffset +
>>>> + gStmPsdOffset);
>>>> Psd->BiosHwResourceRequirementsPtr = (UINT64)(UINTN)StmResource;
>>>> }
>>>> return ;
>>>> diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.S
>>>> b/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.S
>>>> index 1f9f91c..5f3386a 100644
>>>> --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.S
>>>> +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.S
>>>> @@ -1,6 +1,8 @@
>>>> #------------------------------------------------------------------------------
>>>> #
>>>> # Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.<BR>
>>>> +# Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR> #
>>>> # This program and the accompanying materials # are licensed and made
>>>> available under the terms and conditions of the BSD License # which
>>>> accompanies this distribution. The full text of the license may be found at
>>>> @@ -27,6 +29,9 @@ ASM_GLOBAL ASM_PFX(gStmSmiStack) ASM_GLOBAL
>>>> ASM_PFX(gStmSmbase) ASM_GLOBAL ASM_PFX(gStmXdSupported)
>>>> ASM_GLOBAL ASM_PFX(gStmSmiHandlerIdtr)
>>>> +ASM_GLOBAL ASM_PFX(gStmPsdOffset)
>>>> +ASM_GLOBAL ASM_PFX(gStmGdtSize)
>>>> +ASM_GLOBAL ASM_PFX(gStmGdtPtr)
>>>>
>>>> .equ MSR_IA32_MISC_ENABLE, 0x1A0
>>>> .equ MSR_EFER, 0xc0000080
>>>> @@ -35,12 +40,13 @@ ASM_GLOBAL ASM_PFX(gStmSmiHandlerIdtr) # #
>>>> Constants relating to TXT_PROCESSOR_SMM_DESCRIPTOR #
>>>> -.equ DSC_OFFSET, 0xfb00
>>>> -.equ DSC_GDTPTR, 0x48
>>>> -.equ DSC_GDTSIZ, 0x50
>>>> -.equ DSC_CS, 0x14
>>>> -.equ DSC_DS, 0x16
>>>> -.equ DSC_SS, 0x18
>>>> +# .equ DSC_OFFSET, 0xfb00
>>>> +# .equ DSC_GDTPTR, 0x48
>>>> +# .equ DSC_GDTSIZ, 0x50
>>>> +#
>>>> +.equ DSC_CS, 0x14
>>>> +.equ DSC_DS, 0x16
>>>> +.equ DSC_SS, 0x18
>>>> .equ DSC_OTHERSEG, 0x1a
>>>> #
>>>> # Constants relating to CPU State Save Area @@ -71,12 +77,12 @@
>>>> _StmSmiEntryPoint:
>>>> # fix GDT descriptor
>>>> #
>>>> .byte 0x2e,0xa1 # mov ax, cs:[offset16]
>>>> - .word DSC_OFFSET + DSC_GDTSIZ
>>>> +ASM_PFX(gStmGdtSize): .space 2 # .word DSC_OFFSET + DSC_GDTSIZ
>>>> .byte 0x48 # dec ax
>>>> .byte 0x2e
>>>> movl %eax, (%rdi) # mov cs:[bx], ax
>>>> .byte 0x66,0x2e,0xa1 # mov eax, cs:[offset16]
>>>> - .word DSC_OFFSET + DSC_GDTPTR
>>>> +ASM_PFX(gStmGdtPtr): .space 2 # .word DSC_OFFSET + DSC_GDTPTR
>>>> .byte 0x2e
>>>> movw %ax, 2(%rdi)
>>>> .byte 0x66,0x2e
>>>> @@ -183,7 +189,11 @@ Base:
>>>> LongMode: # long mode (64-bit code) starts here
>>>> movabsq $ASM_PFX(gStmSmiHandlerIdtr), %rax
>>>> lidt (%rax)
>>>> - lea (DSC_OFFSET)(%rdi), %ebx
>>>> +
>>>> + movl $ASM_PFX(gStmPsdOffset), %ebx # lea (DSC_OFFSET)(%rdi),
>>>> %ebx
>>>> + movzxw (%ebx), %rsi
>>>> + leal (%rdi, %rsi), %ebx
>>>> +
>>>> movw DSC_DS(%rbx), %ax
>>>> movl %eax,%ds
>>>> movw DSC_OTHERSEG(%rbx), %ax
>>>> diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.asm
>>>> b/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.asm
>>>> index ad51e07..10913df 100644
>>>> --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.asm
>>>> +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.asm
>>>> @@ -1,5 +1,7 @@
>>>> ;------------------------------------------------------------------------------ ; ;
>>>> Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.<BR>
>>>> +; Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR> ;
>>>> ; This program and the accompanying materials ; are licensed and made
>>>> available under the terms and conditions of the BSD License ; which
>>>> accompanies this distribution. The full text of the license may be found at
>>>> @@ -32,6 +34,10 @@ EXTERNDEF gStmSmiStack:DWORD
>>>> EXTERNDEF gStmSmbase:DWORD
>>>> EXTERNDEF gStmXdSupported:BYTE
>>>> EXTERNDEF gStmSmiHandlerIdtr:FWORD
>>>> +EXTERNDEF gStmPsdOffset:WORD
>>>> +EXTERNDEF gStmGdtSize:WORD
>>>> +EXTERNDEF gStmGdtPtr:WORD
>>>> +
>>>>
>>>> MSR_IA32_MISC_ENABLE EQU 1A0h
>>>> MSR_EFER EQU 0c0000080h
>>>> @@ -40,13 +46,14 @@ MSR_EFER_XD EQU 0800h
>>>> ;
>>>> ; Constants relating to TXT_PROCESSOR_SMM_DESCRIPTOR ;
>>>> -DSC_OFFSET EQU 0fb00h
>>>> -DSC_GDTPTR EQU 48h
>>>> -DSC_GDTSIZ EQU 50h
>>>> -DSC_CS EQU 14h
>>>> -DSC_DS EQU 16h
>>>> -DSC_SS EQU 18h
>>>> -DSC_OTHERSEG EQU 1ah
>>>> +; DSC_OFFSET EQU 0fb00h
>>>> +; DSC_GDTPTR EQU 48h
>>>> +; DSC_GDTSIZ EQU 50h
>>>> +;
>>>> +DSC_CS EQU 14h
>>>> +DSC_DS EQU 16h
>>>> +DSC_SS EQU 18h
>>>> +DSC_OTHERSEG EQU 1ah
>>>> ;
>>>> ; Constants relating to CPU State Save Area ; @@ -74,12 +81,12 @@
>>>> _StmSmiEntryPoint:
>>>> DW offset _StmGdtDesc - _StmSmiEntryPoint + 8000h ; bx = GdtDesc
>>>> offset
>>>> ; fix GDT descriptor
>>>> DB 2eh, 0a1h ; mov ax, cs:[offset16]
>>>> - DW DSC_OFFSET + DSC_GDTSIZ
>>>> +gStmGdtSize DW ? ; DSC_OFFSET + DSC_GDTSIZ
>>>> DB 48h ; dec ax
>>>> DB 2eh
>>>> mov [rdi], eax ; mov cs:[bx], ax
>>>> DB 66h, 2eh, 0a1h ; mov eax, cs:[offset16]
>>>> - DW DSC_OFFSET + DSC_GDTPTR
>>>> +gStmGdtPtr DW ? ; DSC_OFFSET + DSC_GDTPTR
>>>> DB 2eh
>>>> mov [rdi + 2], ax ; mov cs:[bx + 2], eax
>>>> DB 66h, 2eh
>>>> @@ -178,7 +185,10 @@ Base:
>>>> @LongMode: ; long mode (64-bit code) starts here
>>>> mov rax, offset gStmSmiHandlerIdtr
>>>> lidt fword ptr [rax]
>>>> - lea ebx, [rdi + DSC_OFFSET]
>>>> +
>>>> + movzx rsi, word ptr [gStmPsdOffset] ; lea ebx, [rdi + DSC_OFFSET]
>>>> + lea ebx, [rdi + rsi] ;
>>>> +
>>>> mov ax, [rbx + DSC_DS]
>>>> mov ds, eax
>>>> mov ax, [rbx + DSC_OTHERSEG]
>>>> diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.nasm
>>>> b/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.nasm
>>>> index bcac643..df4c5a2 100644
>>>> --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.nasm
>>>> +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.nasm
>>>> @@ -1,5 +1,7 @@
>>>> ;------------------------------------------------------------------------------ ; ;
>>>> Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
>>>> +; Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR> ;
>>>> ; This program and the accompanying materials ; are licensed and made
>>>> available under the terms and conditions of the BSD License ; which
>>>> accompanies this distribution. The full text of the license may be found at
>>>> @@ -29,13 +31,14 @@ ; ; Constants relating to
>>>> TXT_PROCESSOR_SMM_DESCRIPTOR ; -%define DSC_OFFSET 0xfb00 -
>>>> %define DSC_GDTPTR 0x48 -%define DSC_GDTSIZ 0x50 -%define DSC_CS
>>>> 0x14 -%define DSC_DS 0x16 -%define DSC_SS 0x18 -%define DSC_OTHERSEG
>>>> 0x1a
>>>> +; %define DSC_OFFSET 0xfb00
>>>> +; %define DSC_GDTPTR 0x48
>>>> +; %define DSC_GDTSIZ 0x50
>>>> +;
>>>> +%define DSC_CS 0x14
>>>> +%define DSC_DS 0x16
>>>> +%define DSC_SS 0x18
>>>> +%define DSC_OTHERSEG 0x1a
>>>> ;
>>>> ; Constants relating to CPU State Save Area ; @@ -44,9 +47,9 @@
>>>>
>>>> %define PROTECT_MODE_CS 0x8
>>>> %define PROTECT_MODE_DS 0x20
>>>> -%define LONG_MODE_CS 0x38
>>>> -%define TSS_SEGMENT 0x40
>>>> -%define GDT_SIZE 0x50
>>>> +%define LONG_MODE_CS 0x38
>>>> +%define TSS_SEGMENT 0x40
>>>> +%define GDT_SIZE 0x50
>>>>
>>>> extern ASM_PFX(SmiRendezvous)
>>>> extern ASM_PFX(gStmSmiHandlerIdtr)
>>>> @@ -61,6 +64,10 @@ global ASM_PFX(gcStmSmiHandlerTemplate) global
>>>> ASM_PFX(gcStmSmiHandlerSize) global ASM_PFX(gcStmSmiHandlerOffset)
>>>>
>>>> +extern ASM_PFX(gStmPsdOffset)
>>>> +global ASM_PFX(gStmGdtSize)
>>>> +global ASM_PFX(gStmGdtPtr)
>>>> +
>>>> ASM_PFX(gStmSmbase) EQU StmSmbasePatch - 4
>>>> ASM_PFX(gStmSmiStack) EQU StmSmiStackPatch - 4
>>>> ASM_PFX(gStmSmiCr3) EQU StmSmiCr3Patch - 4
>>>> @@ -73,10 +80,18 @@ BITS 16
>>>> ASM_PFX(gcStmSmiHandlerTemplate):
>>>> _StmSmiEntryPoint:
>>>> mov bx, _StmGdtDesc - _StmSmiEntryPoint + 0x8000
>>>> - mov ax,[cs:DSC_OFFSET + DSC_GDTSIZ]
>>>> +
>>>> + mov eax, ASM_PFX(gStmGdtSize) ; mov ax, [cs:DSC_OFFSET +
>>>> DSC_GDTSIZ]
>>>> + mov si, [cs:eax] ;
>>>> + mov ax, [cs:si] ;
>>>> +
>>>> dec ax
>>>> mov [cs:bx], ax
>>>> - mov eax, [cs:DSC_OFFSET + DSC_GDTPTR]
>>>> +
>>>> + mov eax, ASM_PFX(gStmGdtPtr) ; mov eax, [cs:DSC_OFFSET +
>>>> DSC_GDTPTR]
>>>> + mov si, [cs:eax] ;
>>>> + mov eax, [cs:si] ;
>>>> +
>>>> mov [cs:bx + 2], eax
>>>> o32 lgdt [cs:bx] ; lgdt fword ptr cs:[bx]
>>>> mov ax, PROTECT_MODE_CS
>>>> @@ -166,7 +181,10 @@ Base:
>>>> @LongMode: ; long mode (64-bit code) starts here
>>>> mov rax, ASM_PFX(gStmSmiHandlerIdtr)
>>>> lidt [rax]
>>>> - lea ebx, [rdi + DSC_OFFSET]
>>>> +
>>>> + movzx rsi, word [ASM_PFX(gStmPsdOffset)] ; lea ebx, [rdi +
>>>> DSC_OFFSET]
>>>> + lea ebx, [rdi + rsi] ;
>>>> +
>>>> mov ax, [rbx + DSC_DS]
>>>> mov ds, eax
>>>> mov ax, [rbx + DSC_OTHERSEG]
>>>> @@ -262,5 +280,8 @@ _StmSmiHandler:
>>>> ; STM init finish
>>>> jmp CommonHandler
>>>>
>>>> +ASM_PFX(gStmGdtSize) : RESW 1
>>>> +ASM_PFX(gStmGdtPtr) : RESW 1
>>>> +
>>>> ASM_PFX(gcStmSmiHandlerSize) : DW $ - _StmSmiEntryPoint
>>>> ASM_PFX(gcStmSmiHandlerOffset) : DW _StmSmiHandler -
>>>> _StmSmiEntryPoint
>>>> --
>>>> 2.7.4
>>>
>
> _______________________________________________
> edk2-devel mailing list
> edk2-devel@lists.01.org<mailto:edk2-devel@lists.01.org>
> https://lists.01.org/mailman/listinfo/edk2-devel
>
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH v5 1/2] UefiCpuPkg/SmmCpuFeaturesLib: Use global variables to replace macros
2017-10-19 7:00 ` Laszlo Ersek
@ 2017-10-19 17:02 ` Duran, Leo
0 siblings, 0 replies; 30+ messages in thread
From: Duran, Leo @ 2017-10-19 17:02 UTC (permalink / raw)
To: 'Laszlo Ersek', 'Yao, Jiewen', Paolo Bonzini,
edk2-devel@lists.01.org
Cc: Ni, Ruiyu, Justen, Jordan L, Gao, Liming, Kinney, Michael D
> -----Original Message-----
> From: Laszlo Ersek [mailto:lersek@redhat.com]
> Sent: Thursday, October 19, 2017 2:01 AM
> To: Duran, Leo <leo.duran@amd.com>; 'Yao, Jiewen'
> <jiewen.yao@intel.com>; Paolo Bonzini <pbonzini@redhat.com>; edk2-
> devel@lists.01.org
> Cc: Ni, Ruiyu <ruiyu.ni@intel.com>; Justen, Jordan L
> <jordan.l.justen@intel.com>; Gao, Liming <liming.gao@intel.com>; Kinney,
> Michael D <michael.d.kinney@intel.com>
> Subject: Re: [edk2] [PATCH v5 1/2] UefiCpuPkg/SmmCpuFeaturesLib: Use
> global variables to replace macros
>
> On 10/18/17 16:36, Duran, Leo wrote:
> > Yao, Paolo, Lazlo, et al,
> >
> > The offset disparity has proved manageable within SmmCpuFeaturesLib, so
> I’m inclined to leave macro definitions as-is and just drop this patch-set.
> >
> > Agreed?
>
> Sure.
>
> Out of curiosity, what does it mean for you that the offset disparity is
> manageable in SmmCpuFeaturesLib? Will you send a different patch (set) for
> UefiCpuPkg/SmmCpuFeaturesLib, or does it concern an SmmCpuFeaturesLib
> instance that is private to AMD?
Lazlo,
It meant that I can account for the offset disparities in a platform-specific instance of the SmmCpuFeaturesLib library.
And no, I will not be pushing changes to the default SmmCpuFeaturesLib library in EDKII... Nor to the PiSmmCpuDxeSmm driver.
Thanks,
Leo.
>
> Thanks!
> Laszlo
>
>
> > From: Yao, Jiewen [mailto:jiewen.yao@intel.com]
> > Sent: Tuesday, October 17, 2017 8:51 PM
> > To: Laszlo Ersek <lersek@redhat.com>; Duran, Leo <leo.duran@amd.com>
> > Cc: Ni, Ruiyu <ruiyu.ni@intel.com>; Justen, Jordan L
> > <jordan.l.justen@intel.com>; edk2-devel@lists.01.org; Gao, Liming
> > <liming.gao@intel.com>; Kinney, Michael D
> > <michael.d.kinney@intel.com>; Paolo Bonzini <pbonzini@redhat.com>
> > Subject: RE: [edk2] [PATCH v5 1/2] UefiCpuPkg/SmmCpuFeaturesLib: Use
> > global variables to replace macros
> >
> > Thanks. Then I think Paolo’s suggestion makes more sense.
> >
> > If we can use same off, that would be great.
> > If no, just check AMD version ID in SaveState.
> >
> > Thank you
> > Yao Jiewen
> >
> > From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf Of
> > Laszlo Ersek
> > Sent: Tuesday, October 17, 2017 11:15 PM
> > To: Yao, Jiewen <jiewen.yao@intel.com<mailto:jiewen.yao@intel.com>>;
> > Duran, Leo <leo.duran@amd.com<mailto:leo.duran@amd.com>>
> > Cc: Ni, Ruiyu <ruiyu.ni@intel.com<mailto:ruiyu.ni@intel.com>>; Justen,
> > Jordan L
> > <jordan.l.justen@intel.com<mailto:jordan.l.justen@intel.com>>;
> > edk2-devel@lists.01.org<mailto:edk2-devel@lists.01.org>; Gao, Liming
> > <liming.gao@intel.com<mailto:liming.gao@intel.com>>; Kinney, Michael D
> > <michael.d.kinney@intel.com<mailto:michael.d.kinney@intel.com>>;
> Paolo
> > Bonzini <pbonzini@redhat.com<mailto:pbonzini@redhat.com>>
> > Subject: Re: [edk2] [PATCH v5 1/2] UefiCpuPkg/SmmCpuFeaturesLib: Use
> > global variables to replace macros
> >
> > On 10/17/17 16:50, Yao, Jiewen wrote:
> >> I think it is unnecessary. All intel CPU is using same offset. All amd CPU is
> using same offset. It can be identified easily by code.
> >> Adding a new API now is also an incompatible change because that
> requires all existing featurelib change to add a new API. We have lots of close
> source platform using its own featurelib.
> >>
> >> May I know what problem we are trying to resolve by adding a new API?
> >
> > QEMU (and hence OVMF) uses the AMD save state map even when it
> > emulates Intel CPUs.
> >
> > The reason is that the Intel SDM does not specify the Intel save state
> > map in sufficient detail (for emulation by QEMU), while the AMD spec
> > does. So, as an emulation target, only the AMD one is implementable in
> > QEMU (and supportable in OVMF), regardless of whether QEMU reports
> the
> > virtual CPU manufacturer as Intel vs. AMD.
> >
> > If PiSmmCpuDxeSmm used a CPUID check, saw "Intel" as manufacturer,
> and
> > then used the Intel definition of the save state map, then
> > PiSmmCpuDxeSmm would break on QEMU / as part of OVMF.
> >
> > Thanks,
> > Laszlo
> >
> >>
> >>
> >> thank you!
> >> Yao, Jiewen
> >>
> >>
> >>> 在 2017年10月17日，下午10:20，Duran, Leo
> >>> <leo.duran@amd.com<mailto:leo.duran@amd.com>> 写道：
> >>>
> >>> Yao, Lazlo, et al,
> >>>
> >>> For the SRAM_SAVE_STATE_MAP_OFFSET:
> >>> I propose returning the value by a function in SmmCpuFeaturesLib...
> Here's the rationale:
> >>> - The value is fixed per CPU architecture, so this qualifies as a CPU
> feature.
> >>> - The logic for CPU architecture detection would be in one place
> >>> (e.g., PiSmmCpuDxeSmm would call the library function)
> >>> - The OVMF and Quark instances of the library could just return the
> current (default) value, so no compatibility issues.
> >>>
> >>> if you agree with this is an acceptable solution, I will submit a revised
> patch-set to address just the SRAM_SAVE_STATE_MAP_OFFSET.
> >>> (BTW, I'm re-evaluating the changes submitted for the PSD offset,
> >>> with the goal of just using the default value and dropping those
> >>> changes)
> >>>
> >>> Thanks,
> >>> Leo.
> >>>
> >>>> -----Original Message-----
> >>>> From: Duran, Leo
> >>>> Sent: Wednesday, October 11, 2017 2:46 PM
> >>>> To: edk2-devel@lists.01.org<mailto:edk2-devel@lists.01.org>
> >>>> Cc: Duran, Leo <leo.duran@amd.com<mailto:leo.duran@amd.com>>;
> >>>> Jiewen Yao <jiewen.yao@intel.com<mailto:jiewen.yao@intel.com>>;
> >>>> Ruiyu Ni <ruiyu.ni@intel.com<mailto:ruiyu.ni@intel.com>>; Michael D
> >>>> Kinney
> >>>> <michael.d.kinney@intel.com<mailto:michael.d.kinney@intel.com>>;
> >>>> Jordan Justen
> >>>> <jordan.l.justen@intel.com<mailto:jordan.l.justen@intel.com>>;
> >>>> Liming Gao <liming.gao@intel.com<mailto:liming.gao@intel.com>>
> >>>> Subject: [PATCH v5 1/2] UefiCpuPkg/SmmCpuFeaturesLib: Use global
> >>>> variables to replace macros
> >>>>
> >>>> Set global variables on Constructor function based on CPUID checks.
> >>>> The variables replace Intel macros to allow support on AMD x86
> systems.
> >>>>
> >>>> Specifically, the replaced macros are:
> >>>> 1) SRAM_SAVE_STATE_MAP_OFFSET
> >>>> 2) TXT_SMM_PSD_OFFSET
> >>>>
> >>>> Cc: Jiewen Yao
> <jiewen.yao@intel.com<mailto:jiewen.yao@intel.com>>
> >>>> Cc: Ruiyu Ni <ruiyu.ni@intel.com<mailto:ruiyu.ni@intel.com>>
> >>>> Cc: Michael D Kinney
> >>>> <michael.d.kinney@intel.com<mailto:michael.d.kinney@intel.com>>
> >>>> Cc: Jordan Justen
> >>>> <jordan.l.justen@intel.com<mailto:jordan.l.justen@intel.com>>
> >>>> Cc: Liming Gao <liming.gao@intel.com<mailto:liming.gao@intel.com>>
> >>>> Contributed-under: TianoCore Contribution Agreement 1.1
> >>>> Signed-off-by: Leo Duran
> >>>> <leo.duran@amd.com<mailto:leo.duran@amd.com>>
> >>>> ---
> >>>> .../Library/SmmCpuFeaturesLib/Ia32/SmiEntry.S | 28 ++++++----
> >>>> .../Library/SmmCpuFeaturesLib/Ia32/SmiEntry.asm | 29 +++++++----
> >>>> .../Library/SmmCpuFeaturesLib/Ia32/SmiEntry.nasm | 43
> ++++++++++++---
> >>>> -
> >>>> UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCommon.h | 48
> >>>> ++++++++++++++++++
> >>>> .../Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c | 59
> >>>> ++++++++++++++++++----
> >>>> .../SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf | 3 ++
> >>>> .../SmmCpuFeaturesLib/SmmCpuFeaturesLibStm.inf | 3 ++
> >>>> UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c | 39
> >>>> ++++++++++++--
> >>>> .../Library/SmmCpuFeaturesLib/X64/SmiEntry.S | 28 ++++++----
> >>>> .../Library/SmmCpuFeaturesLib/X64/SmiEntry.asm | 30 +++++++----
> >>>> .../Library/SmmCpuFeaturesLib/X64/SmiEntry.nasm | 47
> ++++++++++++---
> >>>> --
> >>>> 11 files changed, 282 insertions(+), 75 deletions(-) create mode
> >>>> 100644 UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCommon.h
> >>>>
> >>>> diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.S
> >>>> b/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.S
> >>>> index 4c0f8c8..c7b49d7 100644
> >>>> --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.S
> >>>> +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.S
> >>>> @@ -1,6 +1,8 @@
> >>>> #------------------------------------------------------------------
> >>>> ------------
> >>>> #
> >>>> # Copyright (c) 2009 - 2016, Intel Corporation. All rights
> >>>> reserved.<BR>
> >>>> +# Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR> #
> >>>> # This program and the accompanying materials # are licensed and
> >>>> made available under the terms and conditions of the BSD License #
> >>>> which accompanies this distribution. The full text of the license
> >>>> may be found at @@ -28,6 +30,9 @@ ASM_GLOBAL
> ASM_PFX(gStmSmbase)
> >>>> ASM_GLOBAL
> >>>> ASM_PFX(gStmXdSupported) ASM_GLOBAL
> ASM_PFX(FeaturePcdGet
> >>>> (PcdCpuSmmStackGuard)) ASM_GLOBAL
> ASM_PFX(gStmSmiHandlerIdtr)
> >>>> +ASM_GLOBAL ASM_PFX(gStmPsdOffset) ASM_GLOBAL
> >>>> +ASM_PFX(gStmGdtSize) ASM_GLOBAL ASM_PFX(gStmGdtPtr)
> >>>>
> >>>> .equ MSR_IA32_MISC_ENABLE, 0x1A0
> >>>> .equ MSR_EFER, 0xc0000080
> >>>> @@ -36,12 +41,13 @@ ASM_GLOBAL ASM_PFX(gStmSmiHandlerIdtr)
> # #
> >>>> Constants relating to TXT_PROCESSOR_SMM_DESCRIPTOR #
> >>>> -.equ DSC_OFFSET, 0xfb00
> >>>> -.equ DSC_GDTPTR, 0x48
> >>>> -.equ DSC_GDTSIZ, 0x50
> >>>> -.equ DSC_CS, 0x14
> >>>> -.equ DSC_DS, 0x16
> >>>> -.equ DSC_SS, 0x18
> >>>> +# .equ DSC_OFFSET, 0xfb00
> >>>> +# .equ DSC_GDTPTR, 0x48
> >>>> +# .equ DSC_GDTSIZ, 0x50
> >>>> +#
> >>>> +.equ DSC_CS, 0x14
> >>>> +.equ DSC_DS, 0x16
> >>>> +.equ DSC_SS, 0x18
> >>>> .equ DSC_OTHERSEG, 0x1A
> >>>>
> >>>> .equ PROTECT_MODE_CS, 0x08
> >>>> @@ -55,11 +61,11 @@ _StmSmiEntryPoint:
> >>>> .byte 0xbb # mov bx, imm16
> >>>> .word _StmGdtDesc - _StmSmiEntryPoint + 0x8000
> >>>> .byte 0x2e,0xa1 # mov ax, cs:[offset16]
> >>>> - .word DSC_OFFSET + DSC_GDTSIZ
> >>>> +ASM_PFX(gStmGdtSize): .space 2 # .word DSC_OFFSET +
> DSC_GDTSIZ
> >>>> decl %eax
> >>>> movl %eax, %cs:(%edi) # mov cs:[bx], ax
> >>>> .byte 0x66,0x2e,0xa1 # mov eax, cs:[offset16]
> >>>> - .word DSC_OFFSET + DSC_GDTPTR
> >>>> +ASM_PFX(gStmGdtPtr): .space 2 # .word DSC_OFFSET +
> DSC_GDTPTR
> >>>> movw %ax, %cs:2(%edi)
> >>>> movw %ax, %bp # ebp = GDT base
> >>>> .byte 0x66
> >>>> @@ -167,7 +173,11 @@ XdDone:
> >>>> movl %cr0, %ebx
> >>>> orl $0x080010023, %ebx # enable paging + WP + NE + MP + PE
> >>>> movl %ebx, %cr0
> >>>> - leal DSC_OFFSET(%edi),%ebx
> >>>> +
> >>>> + movl $ASM_PFX(gStmPsdOffset), %ebx # leal
> DSC_OFFSET(%edi),
> >>>> %ebx
> >>>> + movzxw (%ebx), %esi
> >>>> + leal (%edi, %esi), %ebx
> >>>> +
> >>>> movw DSC_DS(%ebx),%ax
> >>>> movl %eax, %ds
> >>>> movw DSC_OTHERSEG(%ebx),%ax
> >>>> diff --git
> a/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.asm
> >>>> b/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.asm
> >>>> index 91dc1eb..4dbe276 100644
> >>>> --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.asm
> >>>> +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.asm
> >>>> @@ -1,5 +1,7 @@
> >>>> ;------------------------------------------------------------------
> >>>> ------------ ; ; Copyright (c) 2009 - 2017, Intel Corporation. All
> >>>> rights reserved.<BR>
> >>>> +; Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR> ;
> >>>> ; This program and the accompanying materials ; are licensed and
> >>>> made available under the terms and conditions of the BSD License ;
> >>>> which accompanies this distribution. The full text of the license may be
> found at
> >>>> @@ -29,13 +31,14 @@ MSR_EFER_XD EQU 0800h
> >>>> ;
> >>>> ; Constants relating to TXT_PROCESSOR_SMM_DESCRIPTOR ;
> >>>> -DSC_OFFSET EQU 0fb00h
> >>>> -DSC_GDTPTR EQU 48h
> >>>> -DSC_GDTSIZ EQU 50h
> >>>> -DSC_CS EQU 14h
> >>>> -DSC_DS EQU 16h
> >>>> -DSC_SS EQU 18h
> >>>> -DSC_OTHERSEG EQU 1Ah
> >>>> +; DSC_OFFSET EQU 0fb00h
> >>>> +; DSC_GDTPTR EQU 48h
> >>>> +; DSC_GDTSIZ EQU 50h
> >>>> +;
> >>>> +DSC_CS EQU 14h
> >>>> +DSC_DS EQU 16h
> >>>> +DSC_SS EQU 18h
> >>>> +DSC_OTHERSEG EQU 1Ah
> >>>>
> >>>> PROTECT_MODE_CS EQU 08h
> >>>> PROTECT_MODE_DS EQU 20h
> >>>> @@ -54,6 +57,9 @@ EXTERNDEF gStmSmbase:DWORD
> >>>> EXTERNDEF gStmXdSupported:BYTE
> >>>> EXTERNDEF FeaturePcdGet (PcdCpuSmmStackGuard):BYTE
> >>>> EXTERNDEF gStmSmiHandlerIdtr:FWORD
> >>>> +EXTERNDEF gStmPsdOffset:WORD
> >>>> +EXTERNDEF gStmGdtSize:WORD
> >>>> +EXTERNDEF gStmGdtPtr:WORD
> >>>>
> >>>> .code
> >>>>
> >>>> @@ -63,11 +69,11 @@ _StmSmiEntryPoint:
> >>>> DB 0bbh ; mov bx, imm16
> >>>> DW offset _StmGdtDesc - _StmSmiEntryPoint + 8000h
> >>>> DB 2eh, 0a1h ; mov ax, cs:[offset16]
> >>>> - DW DSC_OFFSET + DSC_GDTSIZ
> >>>> +gStmGdtSize DW ? ; DSC_OFFSET + DSC_GDTSIZ
> >>>> dec eax
> >>>> mov cs:[edi], eax ; mov cs:[bx], ax
> >>>> DB 66h, 2eh, 0a1h ; mov eax, cs:[offset16]
> >>>> - DW DSC_OFFSET + DSC_GDTPTR
> >>>> +gStmGdtPtr DW ? ; DSC_OFFSET + DSC_GDTPTR
> >>>> mov cs:[edi + 2], ax ; mov cs:[bx + 2], eax
> >>>> mov bp, ax ; ebp = GDT base
> >>>> DB 66h
> >>>> @@ -174,7 +180,10 @@ gStmXdSupported DB 1
> >>>> mov ebx, cr0
> >>>> or ebx, 080010023h ; enable paging + WP + NE + MP + PE
> >>>> mov cr0, ebx
> >>>> - lea ebx, [edi + DSC_OFFSET]
> >>>> +
> >>>> + movzx esi, word ptr [gStmPsdOffset] ; lea ebx, [edi +
> DSC_OFFSET]
> >>>> + lea ebx, [edi + esi] ;
> >>>> +
> >>>> mov ax, [ebx + DSC_DS]
> >>>> mov ds, eax
> >>>> mov ax, [ebx + DSC_OTHERSEG]
> >>>> diff --git
> >>>> a/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.nasm
> >>>> b/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.nasm
> >>>> index 00c0f067..023923a 100644
> >>>> --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.nasm
> >>>> +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.nasm
> >>>> @@ -1,5 +1,7 @@
> >>>> ;------------------------------------------------------------------
> >>>> ------------ ; ; Copyright (c) 2016 - 2017, Intel Corporation. All
> >>>> rights reserved.<BR>
> >>>> +; Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR> ;
> >>>> ; This program and the accompanying materials ; are licensed and
> >>>> made available under the terms and conditions of the BSD License ;
> >>>> which accompanies this distribution. The full text of the license
> >>>> may be found at @@ -25,17 +27,18 @@ ; ; Constants relating to
> >>>> TXT_PROCESSOR_SMM_DESCRIPTOR ; -%define DSC_OFFSET 0xfb00 -
> >>>> %define DSC_GDTPTR 0x48 -%define DSC_GDTSIZ 0x50 -%define
> DSC_CS
> >>>> 0x14 -%define DSC_DS 0x16 -%define DSC_SS 0x18 -%define
> >>>> DSC_OTHERSEG 0x1a
> >>>> +; %define DSC_OFFSET 0xfb00
> >>>> +; %define DSC_GDTPTR 0x48
> >>>> +; %define DSC_GDTSIZ 0x50
> >>>> +;
> >>>> +%define DSC_CS 0x14
> >>>> +%define DSC_DS 0x16
> >>>> +%define DSC_SS 0x18
> >>>> +%define DSC_OTHERSEG 0x1a
> >>>>
> >>>> %define PROTECT_MODE_CS 0x8
> >>>> %define PROTECT_MODE_DS 0x20
> >>>> -%define TSS_SEGMENT 0x40
> >>>> +%define TSS_SEGMENT 0x40
> >>>>
> >>>> extern ASM_PFX(SmiRendezvous)
> >>>> extern ASM_PFX(FeaturePcdGet (PcdCpuSmmStackGuard)) @@ -51,6
> >>>> +54,10 @@ global ASM_PFX(gStmSmbase) global
> >>>> ASM_PFX(gStmXdSupported) extern ASM_PFX(gStmSmiHandlerIdtr)
> >>>>
> >>>> +extern ASM_PFX(gStmPsdOffset)
> >>>> +global ASM_PFX(gStmGdtSize)
> >>>> +global ASM_PFX(gStmGdtPtr)
> >>>> +
> >>>> ASM_PFX(gStmSmiCr3) EQU StmSmiCr3Patch - 4
> >>>> ASM_PFX(gStmSmiStack) EQU StmSmiStackPatch - 4
> >>>> ASM_PFX(gStmSmbase) EQU StmSmbasePatch - 4
> >>>> @@ -62,10 +69,18 @@ BITS 16
> >>>> ASM_PFX(gcStmSmiHandlerTemplate):
> >>>> _StmSmiEntryPoint:
> >>>> mov bx, _StmGdtDesc - _StmSmiEntryPoint + 0x8000
> >>>> - mov ax,[cs:DSC_OFFSET + DSC_GDTSIZ]
> >>>> +
> >>>> + mov eax, ASM_PFX(gStmGdtSize) ; mov ax, [cs:DSC_OFFSET +
> >>>> DSC_GDTSIZ]
> >>>> + mov si, [cs:eax] ;
> >>>> + mov ax, [cs:si] ;
> >>>> +
> >>>> dec ax
> >>>> mov [cs:bx], ax
> >>>> - mov eax, [cs:DSC_OFFSET + DSC_GDTPTR]
> >>>> +
> >>>> + mov eax, ASM_PFX(gStmGdtPtr) ; mov eax, [cs:DSC_OFFSET
> +
> >>>> DSC_GDTPTR]
> >>>> + mov si, [cs:eax] ;
> >>>> + mov eax, [cs:si] ;
> >>>> +
> >>>> mov [cs:bx + 2], eax
> >>>> mov ebp, eax ; ebp = GDT base
> >>>> o32 lgdt [cs:bx] ; lgdt fword ptr cs:[bx]
> >>>> @@ -166,7 +181,10 @@ StmXdSupportedPatch:
> >>>> mov ebx, cr0
> >>>> or ebx, 0x80010023 ; enable paging + WP + NE + MP + PE
> >>>> mov cr0, ebx
> >>>> - lea ebx, [edi + DSC_OFFSET]
> >>>> +
> >>>> + movzx esi, word [ASM_PFX(gStmPsdOffset)] ; lea ebx, [edi +
> >>>> DSC_OFFSET]
> >>>> + lea ebx, [edi + esi] ;
> >>>> +
> >>>> mov ax, [ebx + DSC_DS]
> >>>> mov ds, eax
> >>>> mov ax, [ebx + DSC_OTHERSEG]
> >>>> @@ -271,5 +289,8 @@ _StmSmiHandler:
> >>>> ; STM init finish
> >>>> jmp CommonHandler
> >>>>
> >>>> +ASM_PFX(gStmGdtSize) : RESW 1
> >>>> +ASM_PFX(gStmGdtPtr) : RESW 1
> >>>> +
> >>>> ASM_PFX(gcStmSmiHandlerSize) : DW $ - _StmSmiEntryPoint
> >>>> ASM_PFX(gcStmSmiHandlerOffset) : DW _StmSmiHandler -
> >>>> _StmSmiEntryPoint
> >>>> diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCommon.h
> >>>> b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCommon.h
> >>>> new file mode 100644
> >>>> index 0000000..78b3a5b
> >>>> --- /dev/null
> >>>> +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCommon.h
> >>>> @@ -0,0 +1,48 @@
> >>>> +/** @file
> >>>> + Common declarations
> >>>> +
> >>>> + Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>
> >>>> +
> >>>> + This program and the accompanying materials are licensed and
> >>>> + made available under the terms and conditions of the BSD License
> >>>> + which accompanies this distribution. The full text of the
> >>>> + license may be found at http://opensource.org/licenses/bsd-
> license.php.
> >>>> +
> >>>> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS
> IS"
> >>>> BASIS,
> >>>> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
> >>>> EXPRESS OR IMPLIED.
> >>>> +
> >>>> +**/
> >>>> +
> >>>> +#ifndef _SMM_COMMON_H_
> >>>> +#define _SMM_COMMON_H_
> >>>> +
> >>>> +#include <Register/Amd/Cpuid.h>
> >>>> +
> >>>> +//
> >>>> +// Definitions for AMD systems are based on contents of the //
> >>>> +AMD64 Architecture Programmer's Manual // Volume 2: System
> >>>> +Programming, Section 10 System-Management Mode // #define
> >>>> +AMD_SMRAM_SAVE_STATE_MAP_OFFSET 0xfe00
> >>>> +#define AMD_SMM_PSD_OFFSET 0xfc00
> >>>> +
> >>>> +//
> >>>> +// External global variables for SMRAM offsets // extern UINT16
> >>>> +gSmramStateMapOffset; extern UINT16 gSmmPsdOffset;
> >>>> +
> >>>> +
> >>>> +/**
> >>>> + Determine if the standard CPU signature is "AuthenticAMD".
> >>>> +
> >>>> + @retval TRUE The CPU signature matches.
> >>>> + @retval FALSE The CPU signature does not match.
> >>>> +
> >>>> +**/
> >>>> +BOOLEAN
> >>>> +SmmStandardSignatureIsAuthenticAMD (
> >>>> + VOID
> >>>> + );
> >>>> +
> >>>> +#endif
> >>>> diff --git
> >>>> a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c
> >>>> b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c
> >>>> index 2d2bc6d..1c12095 100644
> >>>> --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c
> >>>> +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c
> >>>> @@ -1,14 +1,16 @@
> >>>> /** @file
> >>>> -The CPU specific programming for PiSmmCpuDxeSmm module.
> >>>> + The CPU specific programming for PiSmmCpuDxeSmm module.
> >>>>
> >>>> -Copyright (c) 2010 - 2016, Intel Corporation. All rights
> >>>> reserved.<BR> -This program and the accompanying materials -are
> >>>> licensed and made available under the terms and conditions of the
> >>>> BSD License -which accompanies this distribution. The full text of
> >>>> the license may be found at -
> >>>> http://opensource.org/licenses/bsd-license.php
> >>>> + Copyright (c) 2010 - 2016, Intel Corporation. All rights
> >>>> + reserved.<BR> Copyright (c) 2017, AMD Incorporated. All rights
> >>>> + reserved.<BR>
> >>>>
> >>>> -THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS
> IS"
> >>>> BASIS, -WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND,
> EITHER
> >>>> EXPRESS OR IMPLIED.
> >>>> + This program and the accompanying materials are licensed and
> >>>> + made available under the terms and conditions of the BSD License
> >>>> + which accompanies this distribution. The full text of the
> >>>> + license may be found at
> >>>> + http://opensource.org/licenses/bsd-license.php
> >>>> +
> >>>> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS
> IS"
> >>>> BASIS,
> >>>> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
> >>>> EXPRESS OR IMPLIED.
> >>>>
> >>>> **/
> >>>>
> >>>> @@ -22,6 +24,8 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF
> ANY
> >>>> KIND, EITHER EXPRESS OR IMPLIED.
> >>>> #include <Register/Cpuid.h>
> >>>> #include <Register/SmramSaveStateMap.h>
> >>>>
> >>>> +#include "SmmCommon.h"
> >>>> +
> >>>> //
> >>>> // Machine Specific Registers (MSRs) // @@ -41,6 +45,7 @@ WITHOUT
> >>>> WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR
> >>>> IMPLIED.
> >>>> #define SMM_FEATURES_LIB_IA32_MCA_CAP 0x17D
> >>>> #define SMM_CODE_ACCESS_CHK_BIT BIT58
> >>>>
> >>>> +
> >>>> /**
> >>>> Internal worker function that is called to complete CPU initialization at
> the
> >>>> end of SmmCpuFeaturesInitializeProcessor().
> >>>> @@ -77,6 +82,13 @@ BOOLEAN mNeedConfigureMtrrs = TRUE; //
> BOOLEAN
> >>>> *mSmrrEnabled;
> >>>>
> >>>> +//
> >>>> +// Set default value for SMRAM offset // from
> >>>> +<Register/SmramSaveStateMap.h> //
> >>>> +UINT16 gSmramStateMapOffset =
> SMRAM_SAVE_STATE_MAP_OFFSET;
> >>>> +
> >>>> +
> >>>> /**
> >>>> The constructor function
> >>>>
> >>>> @@ -99,6 +111,13 @@ SmmCpuFeaturesLibConstructor (
> >>>> UINTN ModelId;
> >>>>
> >>>> //
> >>>> + // Override SMRAM offset for AMD // if
> >>>> + (SmmStandardSignatureIsAuthenticAMD ()) {
> >>>> + gSmramStateMapOffset =
> AMD_SMRAM_SAVE_STATE_MAP_OFFSET; }
> >>>> +
> >>>> + //
> >>>> // Retrieve CPU Family and Model
> >>>> //
> >>>> AsmCpuid (CPUID_VERSION_INFO, &RegEax, NULL, NULL, &RegEdx);
> @@ -
> >>>> 224,7 +243,7 @@ SmmCpuFeaturesInitializeProcessor (
> >>>> //
> >>>> // Configure SMBASE.
> >>>> //
> >>>> - CpuState = (SMRAM_SAVE_STATE_MAP
> *)(UINTN)(SMM_DEFAULT_SMBASE +
> >>>> SMRAM_SAVE_STATE_MAP_OFFSET);
> >>>> + CpuState = (SMRAM_SAVE_STATE_MAP
> >>>> *)(UINTN)(SMM_DEFAULT_SMBASE +
> >>>> + gSmramStateMapOffset);
> >>>> CpuState->x86.SMBASE = (UINT32)CpuHotPlugData-
> >SmBase[CpuIndex];
> >>>>
> >>>> //
> >>>> @@ -630,3 +649,25 @@ SmmCpuFeaturesAllocatePageTableMemory (
> >>>> return NULL;
> >>>> }
> >>>>
> >>>> +
> >>>> +/**
> >>>> + Determine if the standard CPU signature is "AuthenticAMD".
> >>>> +
> >>>> + @retval TRUE The CPU signature matches.
> >>>> + @retval FALSE The CPU signature does not match.
> >>>> +
> >>>> +**/
> >>>> +BOOLEAN
> >>>> +SmmStandardSignatureIsAuthenticAMD (
> >>>> + VOID
> >>>> + )
> >>>> +{
> >>>> + UINT32 RegEbx;
> >>>> + UINT32 RegEcx;
> >>>> + UINT32 RegEdx;
> >>>> +
> >>>> + AsmCpuid (CPUID_SIGNATURE, NULL, &RegEbx, &RegEcx, &RegEdx);
> >>>> + return (RegEbx == CPUID_SIGNATURE_AUTHENTIC_AMD_EBX &&
> >>>> + RegEcx == CPUID_SIGNATURE_AUTHENTIC_AMD_ECX &&
> >>>> + RegEdx == CPUID_SIGNATURE_AUTHENTIC_AMD_EDX);
> >>>> +}
> >>>> diff --git
> >>>> a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf
> >>>> b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf
> >>>> index 77908b0..6a39d4b 100644
> >>>> --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf
> >>>> +++
> b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf
> >>>> @@ -2,6 +2,8 @@
> >>>> # The CPU specific programming for PiSmmCpuDxeSmm module.
> >>>> #
> >>>> # Copyright (c) 2009 - 2016, Intel Corporation. All rights
> >>>> reserved.<BR>
> >>>> +# Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>
> >>>> +#
> >>>> # This program and the accompanying materials # are licensed and
> >>>> made available under the terms and conditions of the BSD License #
> >>>> which accompanies this distribution. The full text of the license
> >>>> may be found at @@ -24,6 +26,7 @@
> >>>>
> >>>> [Sources]
> >>>> SmmCpuFeaturesLib.c
> >>>> + SmmCommon.h
> >>>> SmmCpuFeaturesLibNoStm.c
> >>>>
> >>>> [Packages]
> >>>> diff --git
> >>>>
> a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibStm.inf
> >>>>
> b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibStm.inf
> >>>> index db8dcdc..a76bed6 100644
> >>>> ---
> a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibStm.inf
> >>>> +++
> b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibStm.inf
> >>>> @@ -3,6 +3,8 @@
> >>>> # is included.
> >>>> #
> >>>> # Copyright (c) 2009 - 2016, Intel Corporation. All rights
> >>>> reserved.<BR>
> >>>> +# Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>
> >>>> +#
> >>>> # This program and the accompanying materials # are licensed and
> >>>> made available under the terms and conditions of the BSD License #
> >>>> which accompanies this distribution. The full text of the license
> >>>> may be found at @@ -25,6 +27,7 @@
> >>>>
> >>>> [Sources]
> >>>> SmmCpuFeaturesLib.c
> >>>> + SmmCommon.h
> >>>> SmmStm.c
> >>>> SmmStm.h
> >>>>
> >>>> diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c
> >>>> b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c
> >>>> index 45015b8..5f7c3db 100644
> >>>> --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c
> >>>> +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c
> >>>> @@ -2,6 +2,8 @@
> >>>> SMM STM support functions
> >>>>
> >>>> Copyright (c) 2015 - 2017, Intel Corporation. All rights
> >>>> reserved.<BR>
> >>>> + Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>
> >>>> +
> >>>> This program and the accompanying materials
> >>>> are licensed and made available under the terms and conditions of
> >>>> the BSD License
> >>>> which accompanies this distribution. The full text of the
> >>>> license may be found at @@ -28,6 +30,8 @@ #include
> >>>> <Protocol/MpService.h>
> >>>>
> >>>> #include "SmmStm.h"
> >>>> +#include "SmmCommon.h"
> >>>> +
> >>>>
> >>>> #define TXT_EVTYPE_BASE 0x400
> >>>> #define TXT_EVTYPE_STM_HASH (TXT_EVTYPE_BASE + 14)
> >>>> @@ -97,6 +101,20 @@ extern volatile UINT8
> >>>> gcStmSmiHandlerTemplate[];
> >>>> extern CONST UINT16 gcStmSmiHandlerSize;
> >>>> extern UINT16 gcStmSmiHandlerOffset;
> >>>> extern BOOLEAN gStmXdSupported;
> >>>> +extern UINT16 gStmGdtSize;
> >>>> +extern UINT16 gStmGdtPtr;
> >>>> +
> >>>> +//
> >>>> +// Constants relating to TXT_PROCESSOR_SMM_DESCRIPTOR //
> >>>> +#define TXT_PSD_GDTPTR 0x48
> >>>> +#define TXT_PSD_GDTSIZE 0x50
> >>>> +
> >>>> +//
> >>>> +// Set default value for PSD offset in SMRAM // from
> >>>> +<Register/StmApi.h> //
> >>>> +UINT16 gStmPsdOffset = TXT_SMM_PSD_OFFSET;
> >>>>
> >>>> //
> >>>> // Variables used by SMI Handler
> >>>> @@ -145,6 +163,19 @@ SmmCpuFeaturesLibStmConstructor (
> >>>> ASSERT_EFI_ERROR (Status);
> >>>>
> >>>> //
> >>>> + // Override PSD offset for AMD
> >>>> + //
> >>>> + if (SmmStandardSignatureIsAuthenticAMD ()) {
> >>>> + gStmPsdOffset = AMD_SMM_PSD_OFFSET; }
> >>>> +
> >>>> + //
> >>>> + // Initialize STM global variables associated with SMI Handler
> >>>> + // gStmGdtSize = gStmPsdOffset + TXT_PSD_GDTSIZE; gStmGdtPtr =
> >>>> + gStmPsdOffset + TXT_PSD_GDTPTR;
> >>>> +
> >>>> + //
> >>>> // Lookup the MP Services Protocol
> >>>> //
> >>>> Status = gBS->LocateProtocol (
> >>>> @@ -276,8 +307,8 @@ SmmCpuFeaturesInstallSmiHandler (
> >>>> UINT32 RegEdx;
> >>>> EFI_PROCESSOR_INFORMATION ProcessorInfo;
> >>>>
> >>>> - CopyMem ((VOID *)((UINTN)SmBase + TXT_SMM_PSD_OFFSET),
> >>>> &gcStmPsd, sizeof (gcStmPsd));
> >>>> - Psd = (TXT_PROCESSOR_SMM_DESCRIPTOR *)(VOID
> *)((UINTN)SmBase +
> >>>> TXT_SMM_PSD_OFFSET);
> >>>> + CopyMem ((VOID *)((UINTN)SmBase + gStmPsdOffset), &gcStmPsd,
> >>>> sizeof
> >>>> + (gcStmPsd)); Psd = (TXT_PROCESSOR_SMM_DESCRIPTOR *)(VOID
> >>>> + *)((UINTN)SmBase + gStmPsdOffset);
> >>>> Psd->SmmGdtPtr = GdtBase;
> >>>> Psd->SmmGdtSize = (UINT32)GdtSize;
> >>>>
> >>>> @@ -416,7 +447,7 @@ SmmEndOfDxeEventNotify (
> >>>> }
> >>>>
> >>>> for (Index = 0; Index < gSmst->NumberOfCpus; Index++) {
> >>>> - Psd = (TXT_PROCESSOR_SMM_DESCRIPTOR *)((UINTN)gSmst-
> >>>>> CpuSaveState[Index] - SMRAM_SAVE_STATE_MAP_OFFSET +
> >>>> TXT_SMM_PSD_OFFSET);
> >>>> + Psd = (TXT_PROCESSOR_SMM_DESCRIPTOR
> >>>> + *)((UINTN)gSmst->CpuSaveState[Index] - gSmramStateMapOffset +
> >>>> + gStmPsdOffset);
> >>>> DEBUG ((DEBUG_INFO, "Index=%d Psd=%p Rsdp=%p\n", Index,
> Psd,
> >>>> Rsdp));
> >>>> Psd->AcpiRsdp = (UINT64)(UINTN)Rsdp;
> >>>> }
> >>>> @@ -1266,7 +1297,7 @@ NotifyStmResourceChange (
> >>>> TXT_PROCESSOR_SMM_DESCRIPTOR *Psd;
> >>>>
> >>>> for (Index = 0; Index < gSmst->NumberOfCpus; Index++) {
> >>>> - Psd = (TXT_PROCESSOR_SMM_DESCRIPTOR *)((UINTN)gSmst-
> >>>>> CpuSaveState[Index] - SMRAM_SAVE_STATE_MAP_OFFSET +
> >>>> TXT_SMM_PSD_OFFSET);
> >>>> + Psd = (TXT_PROCESSOR_SMM_DESCRIPTOR
> >>>> + *)((UINTN)gSmst->CpuSaveState[Index] - gSmramStateMapOffset +
> >>>> + gStmPsdOffset);
> >>>> Psd->BiosHwResourceRequirementsPtr =
> (UINT64)(UINTN)StmResource;
> >>>> }
> >>>> return ;
> >>>> diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.S
> >>>> b/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.S
> >>>> index 1f9f91c..5f3386a 100644
> >>>> --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.S
> >>>> +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.S
> >>>> @@ -1,6 +1,8 @@
> >>>> #------------------------------------------------------------------
> >>>> ------------
> >>>> #
> >>>> # Copyright (c) 2009 - 2016, Intel Corporation. All rights
> >>>> reserved.<BR>
> >>>> +# Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR> #
> >>>> # This program and the accompanying materials # are licensed and
> >>>> made available under the terms and conditions of the BSD License #
> >>>> which accompanies this distribution. The full text of the license
> >>>> may be found at @@ -27,6 +29,9 @@ ASM_GLOBAL
> ASM_PFX(gStmSmiStack)
> >>>> ASM_GLOBAL
> >>>> ASM_PFX(gStmSmbase) ASM_GLOBAL ASM_PFX(gStmXdSupported)
> >>>> ASM_GLOBAL ASM_PFX(gStmSmiHandlerIdtr)
> >>>> +ASM_GLOBAL ASM_PFX(gStmPsdOffset) ASM_GLOBAL
> >>>> +ASM_PFX(gStmGdtSize) ASM_GLOBAL ASM_PFX(gStmGdtPtr)
> >>>>
> >>>> .equ MSR_IA32_MISC_ENABLE, 0x1A0
> >>>> .equ MSR_EFER, 0xc0000080
> >>>> @@ -35,12 +40,13 @@ ASM_GLOBAL ASM_PFX(gStmSmiHandlerIdtr)
> # #
> >>>> Constants relating to TXT_PROCESSOR_SMM_DESCRIPTOR #
> >>>> -.equ DSC_OFFSET, 0xfb00
> >>>> -.equ DSC_GDTPTR, 0x48
> >>>> -.equ DSC_GDTSIZ, 0x50
> >>>> -.equ DSC_CS, 0x14
> >>>> -.equ DSC_DS, 0x16
> >>>> -.equ DSC_SS, 0x18
> >>>> +# .equ DSC_OFFSET, 0xfb00
> >>>> +# .equ DSC_GDTPTR, 0x48
> >>>> +# .equ DSC_GDTSIZ, 0x50
> >>>> +#
> >>>> +.equ DSC_CS, 0x14
> >>>> +.equ DSC_DS, 0x16
> >>>> +.equ DSC_SS, 0x18
> >>>> .equ DSC_OTHERSEG, 0x1a
> >>>> #
> >>>> # Constants relating to CPU State Save Area @@ -71,12 +77,12 @@
> >>>> _StmSmiEntryPoint:
> >>>> # fix GDT descriptor
> >>>> #
> >>>> .byte 0x2e,0xa1 # mov ax, cs:[offset16]
> >>>> - .word DSC_OFFSET + DSC_GDTSIZ
> >>>> +ASM_PFX(gStmGdtSize): .space 2 # .word DSC_OFFSET +
> DSC_GDTSIZ
> >>>> .byte 0x48 # dec ax
> >>>> .byte 0x2e
> >>>> movl %eax, (%rdi) # mov cs:[bx], ax
> >>>> .byte 0x66,0x2e,0xa1 # mov eax, cs:[offset16]
> >>>> - .word DSC_OFFSET + DSC_GDTPTR
> >>>> +ASM_PFX(gStmGdtPtr): .space 2 # .word DSC_OFFSET +
> DSC_GDTPTR
> >>>> .byte 0x2e
> >>>> movw %ax, 2(%rdi)
> >>>> .byte 0x66,0x2e
> >>>> @@ -183,7 +189,11 @@ Base:
> >>>> LongMode: # long mode (64-bit code) starts here
> >>>> movabsq $ASM_PFX(gStmSmiHandlerIdtr), %rax
> >>>> lidt (%rax)
> >>>> - lea (DSC_OFFSET)(%rdi), %ebx
> >>>> +
> >>>> + movl $ASM_PFX(gStmPsdOffset), %ebx # lea
> (DSC_OFFSET)(%rdi),
> >>>> %ebx
> >>>> + movzxw (%ebx), %rsi
> >>>> + leal (%rdi, %rsi), %ebx
> >>>> +
> >>>> movw DSC_DS(%rbx), %ax
> >>>> movl %eax,%ds
> >>>> movw DSC_OTHERSEG(%rbx), %ax
> >>>> diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.asm
> >>>> b/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.asm
> >>>> index ad51e07..10913df 100644
> >>>> --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.asm
> >>>> +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.asm
> >>>> @@ -1,5 +1,7 @@
> >>>> ;------------------------------------------------------------------
> >>>> ------------ ; ; Copyright (c) 2009 - 2016, Intel Corporation. All
> >>>> rights reserved.<BR>
> >>>> +; Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR> ;
> >>>> ; This program and the accompanying materials ; are licensed and
> >>>> made available under the terms and conditions of the BSD License ;
> >>>> which accompanies this distribution. The full text of the license may be
> found at
> >>>> @@ -32,6 +34,10 @@ EXTERNDEF gStmSmiStack:DWORD
> >>>> EXTERNDEF gStmSmbase:DWORD
> >>>> EXTERNDEF gStmXdSupported:BYTE
> >>>> EXTERNDEF gStmSmiHandlerIdtr:FWORD
> >>>> +EXTERNDEF gStmPsdOffset:WORD
> >>>> +EXTERNDEF gStmGdtSize:WORD
> >>>> +EXTERNDEF gStmGdtPtr:WORD
> >>>> +
> >>>>
> >>>> MSR_IA32_MISC_ENABLE EQU 1A0h
> >>>> MSR_EFER EQU 0c0000080h
> >>>> @@ -40,13 +46,14 @@ MSR_EFER_XD EQU 0800h
> >>>> ;
> >>>> ; Constants relating to TXT_PROCESSOR_SMM_DESCRIPTOR ;
> >>>> -DSC_OFFSET EQU 0fb00h
> >>>> -DSC_GDTPTR EQU 48h
> >>>> -DSC_GDTSIZ EQU 50h
> >>>> -DSC_CS EQU 14h
> >>>> -DSC_DS EQU 16h
> >>>> -DSC_SS EQU 18h
> >>>> -DSC_OTHERSEG EQU 1ah
> >>>> +; DSC_OFFSET EQU 0fb00h
> >>>> +; DSC_GDTPTR EQU 48h
> >>>> +; DSC_GDTSIZ EQU 50h
> >>>> +;
> >>>> +DSC_CS EQU 14h
> >>>> +DSC_DS EQU 16h
> >>>> +DSC_SS EQU 18h
> >>>> +DSC_OTHERSEG EQU 1ah
> >>>> ;
> >>>> ; Constants relating to CPU State Save Area ; @@ -74,12 +81,12 @@
> >>>> _StmSmiEntryPoint:
> >>>> DW offset _StmGdtDesc - _StmSmiEntryPoint + 8000h ; bx =
> GdtDesc
> >>>> offset
> >>>> ; fix GDT descriptor
> >>>> DB 2eh, 0a1h ; mov ax, cs:[offset16]
> >>>> - DW DSC_OFFSET + DSC_GDTSIZ
> >>>> +gStmGdtSize DW ? ; DSC_OFFSET + DSC_GDTSIZ
> >>>> DB 48h ; dec ax
> >>>> DB 2eh
> >>>> mov [rdi], eax ; mov cs:[bx], ax
> >>>> DB 66h, 2eh, 0a1h ; mov eax, cs:[offset16]
> >>>> - DW DSC_OFFSET + DSC_GDTPTR
> >>>> +gStmGdtPtr DW ? ; DSC_OFFSET + DSC_GDTPTR
> >>>> DB 2eh
> >>>> mov [rdi + 2], ax ; mov cs:[bx + 2], eax
> >>>> DB 66h, 2eh
> >>>> @@ -178,7 +185,10 @@ Base:
> >>>> @LongMode: ; long mode (64-bit code) starts here
> >>>> mov rax, offset gStmSmiHandlerIdtr
> >>>> lidt fword ptr [rax]
> >>>> - lea ebx, [rdi + DSC_OFFSET]
> >>>> +
> >>>> + movzx rsi, word ptr [gStmPsdOffset] ; lea ebx, [rdi +
> DSC_OFFSET]
> >>>> + lea ebx, [rdi + rsi] ;
> >>>> +
> >>>> mov ax, [rbx + DSC_DS]
> >>>> mov ds, eax
> >>>> mov ax, [rbx + DSC_OTHERSEG]
> >>>> diff --git
> a/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.nasm
> >>>> b/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.nasm
> >>>> index bcac643..df4c5a2 100644
> >>>> --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.nasm
> >>>> +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.nasm
> >>>> @@ -1,5 +1,7 @@
> >>>> ;------------------------------------------------------------------
> >>>> ------------ ; ; Copyright (c) 2016 - 2017, Intel Corporation. All
> >>>> rights reserved.<BR>
> >>>> +; Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR> ;
> >>>> ; This program and the accompanying materials ; are licensed and
> >>>> made available under the terms and conditions of the BSD License ;
> >>>> which accompanies this distribution. The full text of the license
> >>>> may be found at @@ -29,13 +31,14 @@ ; ; Constants relating to
> >>>> TXT_PROCESSOR_SMM_DESCRIPTOR ; -%define DSC_OFFSET 0xfb00 -
> >>>> %define DSC_GDTPTR 0x48 -%define DSC_GDTSIZ 0x50 -%define
> DSC_CS
> >>>> 0x14 -%define DSC_DS 0x16 -%define DSC_SS 0x18 -%define
> >>>> DSC_OTHERSEG 0x1a
> >>>> +; %define DSC_OFFSET 0xfb00
> >>>> +; %define DSC_GDTPTR 0x48
> >>>> +; %define DSC_GDTSIZ 0x50
> >>>> +;
> >>>> +%define DSC_CS 0x14
> >>>> +%define DSC_DS 0x16
> >>>> +%define DSC_SS 0x18
> >>>> +%define DSC_OTHERSEG 0x1a
> >>>> ;
> >>>> ; Constants relating to CPU State Save Area ; @@ -44,9 +47,9 @@
> >>>>
> >>>> %define PROTECT_MODE_CS 0x8
> >>>> %define PROTECT_MODE_DS 0x20
> >>>> -%define LONG_MODE_CS 0x38
> >>>> -%define TSS_SEGMENT 0x40
> >>>> -%define GDT_SIZE 0x50
> >>>> +%define LONG_MODE_CS 0x38
> >>>> +%define TSS_SEGMENT 0x40
> >>>> +%define GDT_SIZE 0x50
> >>>>
> >>>> extern ASM_PFX(SmiRendezvous)
> >>>> extern ASM_PFX(gStmSmiHandlerIdtr)
> >>>> @@ -61,6 +64,10 @@ global ASM_PFX(gcStmSmiHandlerTemplate)
> global
> >>>> ASM_PFX(gcStmSmiHandlerSize) global
> ASM_PFX(gcStmSmiHandlerOffset)
> >>>>
> >>>> +extern ASM_PFX(gStmPsdOffset)
> >>>> +global ASM_PFX(gStmGdtSize)
> >>>> +global ASM_PFX(gStmGdtPtr)
> >>>> +
> >>>> ASM_PFX(gStmSmbase) EQU StmSmbasePatch - 4
> >>>> ASM_PFX(gStmSmiStack) EQU StmSmiStackPatch - 4
> >>>> ASM_PFX(gStmSmiCr3) EQU StmSmiCr3Patch - 4
> >>>> @@ -73,10 +80,18 @@ BITS 16
> >>>> ASM_PFX(gcStmSmiHandlerTemplate):
> >>>> _StmSmiEntryPoint:
> >>>> mov bx, _StmGdtDesc - _StmSmiEntryPoint + 0x8000
> >>>> - mov ax,[cs:DSC_OFFSET + DSC_GDTSIZ]
> >>>> +
> >>>> + mov eax, ASM_PFX(gStmGdtSize) ; mov ax, [cs:DSC_OFFSET +
> >>>> DSC_GDTSIZ]
> >>>> + mov si, [cs:eax] ;
> >>>> + mov ax, [cs:si] ;
> >>>> +
> >>>> dec ax
> >>>> mov [cs:bx], ax
> >>>> - mov eax, [cs:DSC_OFFSET + DSC_GDTPTR]
> >>>> +
> >>>> + mov eax, ASM_PFX(gStmGdtPtr) ; mov eax, [cs:DSC_OFFSET
> +
> >>>> DSC_GDTPTR]
> >>>> + mov si, [cs:eax] ;
> >>>> + mov eax, [cs:si] ;
> >>>> +
> >>>> mov [cs:bx + 2], eax
> >>>> o32 lgdt [cs:bx] ; lgdt fword ptr cs:[bx]
> >>>> mov ax, PROTECT_MODE_CS
> >>>> @@ -166,7 +181,10 @@ Base:
> >>>> @LongMode: ; long mode (64-bit code) starts here
> >>>> mov rax, ASM_PFX(gStmSmiHandlerIdtr)
> >>>> lidt [rax]
> >>>> - lea ebx, [rdi + DSC_OFFSET]
> >>>> +
> >>>> + movzx rsi, word [ASM_PFX(gStmPsdOffset)] ; lea ebx, [rdi +
> >>>> DSC_OFFSET]
> >>>> + lea ebx, [rdi + rsi] ;
> >>>> +
> >>>> mov ax, [rbx + DSC_DS]
> >>>> mov ds, eax
> >>>> mov ax, [rbx + DSC_OTHERSEG]
> >>>> @@ -262,5 +280,8 @@ _StmSmiHandler:
> >>>> ; STM init finish
> >>>> jmp CommonHandler
> >>>>
> >>>> +ASM_PFX(gStmGdtSize) : RESW 1
> >>>> +ASM_PFX(gStmGdtPtr) : RESW 1
> >>>> +
> >>>> ASM_PFX(gcStmSmiHandlerSize) : DW $ - _StmSmiEntryPoint
> >>>> ASM_PFX(gcStmSmiHandlerOffset) : DW _StmSmiHandler -
> >>>> _StmSmiEntryPoint
> >>>> --
> >>>> 2.7.4
> >>>
> >
> > _______________________________________________
> > edk2-devel mailing list
> > edk2-devel@lists.01.org<mailto:edk2-devel@lists.01.org>
> > https://lists.01.org/mailman/listinfo/edk2-devel
> >
^ permalink raw reply [flat|nested] 30+ messages in thread
end of thread, other threads:[~2017-10-19 16:58 UTC | newest]
Thread overview: 30+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2017-10-11 19:45 [PATCH v5 0/2] Enhanced SMM support for AMD-based x86 systems Leo Duran
2017-10-11 19:45 ` [PATCH v5 1/2] UefiCpuPkg/SmmCpuFeaturesLib: Use global variables to replace macros Leo Duran
2017-10-12 21:40 ` Paolo Bonzini
2017-10-14 15:51 ` Duran, Leo
2017-10-15 15:26 ` Paolo Bonzini
2017-10-17 14:19 ` Duran, Leo
2017-10-17 14:23 ` Laszlo Ersek
2017-10-17 14:37 ` Paolo Bonzini
2017-10-17 14:50 ` Duran, Leo
2017-10-17 15:16 ` Paolo Bonzini
2017-10-17 14:50 ` Yao, Jiewen
2017-10-17 15:14 ` Laszlo Ersek
2017-10-17 16:40 ` Duran, Leo
2017-10-18 1:50 ` Yao, Jiewen
2017-10-18 14:36 ` Duran, Leo
2017-10-19 7:00 ` Laszlo Ersek
2017-10-19 17:02 ` Duran, Leo
2017-10-17 16:30 ` Duran, Leo
2017-10-11 19:45 ` [PATCH v5 2/2] UefiCpuPkg/PiSmmCpuDxeSmm: " Leo Duran
2017-10-13 1:52 ` [PATCH v5 0/2] Enhanced SMM support for AMD-based x86 systems Yao, Jiewen
2017-10-13 2:36 ` Yao, Jiewen
2017-10-14 16:04 ` Duran, Leo
2017-10-15 0:58 ` Yao, Jiewen
2017-10-16 17:06 ` Laszlo Ersek
2017-10-16 17:08 ` Paolo Bonzini
2017-10-16 17:31 ` Duran, Leo
2017-10-16 18:44 ` Laszlo Ersek
2017-10-16 18:56 ` Duran, Leo
2017-10-14 16:08 ` Duran, Leo
2017-10-16 17:13 ` Paolo Bonzini
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