From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:4864:20::542; helo=mail-pg1-x542.google.com; envelope-from=ming.huang@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-pg1-x542.google.com (mail-pg1-x542.google.com [IPv6:2607:f8b0:4864:20::542]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 46B9521109FE3 for ; Thu, 30 Aug 2018 19:12:20 -0700 (PDT) Received: by mail-pg1-x542.google.com with SMTP id 2-v6so4210063pgo.4 for ; Thu, 30 Aug 2018 19:12:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=1qN9wpTI0OGqLd+Jhu3sk+55jO/Hnpr6ZNWLDNR1ZNo=; b=AtrUWKO0CTAh4t3woSmw5EQ/h6Au1JGfYpi9WvaEW/xLHUrQvY80/43vgyT5FMa16/ BzsWCZrIWVnKfqOlz4czo0Dl/XfitIh7VgsICpN0wBgL0OM595o6VQGV/0yUoSVQU7Td //4dIrDfHG8xupR5YrQJOJc1/8bdLeAFueTaQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=1qN9wpTI0OGqLd+Jhu3sk+55jO/Hnpr6ZNWLDNR1ZNo=; b=OcaQR3bCx/PCJ+KKF/NfbQUuwMKvZnveMH2Lq8o/8F4OCV568nsMW5A/VlhfReDHz2 kLOkgHGfBy6zfB7t3xesu8CMiM8M2y3xjdGxWa6mKCvwrcsClhivrquXlG+jBXgbl3n3 LDXXOLedJMli72fMnAwUfoV/AuoJNGRRauuczyyt2Go5rxnggV7Pkf8p0tDrYBAwrce+ C4JmTVbRosIwEOVhMGJBrktaLJpbf/z2jAiZbcDBiXCH242GHZVRkn9w9dfeZgYsV9lX W4Rn0gy13XOeERsU0kn6/QH15XmIefC5nDnkRij4OXPqEhxQ+X+kxWzTq0EEHuASBjaL yDwQ== X-Gm-Message-State: APzg51CZuFRQ++W9ZX1roMqNB0P/G3TPF6zOc1y3ePH57rbiHV7oCUdm E/Qq3uIb4g5x/0vQz1QQMOyt1g== X-Google-Smtp-Source: ANB0VdaDSmikhbRYO8Ezs2PQUA5dKDUS/SbzgVJeN3blIkyP9Vm6CXYMLlY6/L8kGDSTS6wjyge8bg== X-Received: by 2002:a62:4704:: with SMTP id u4-v6mr13616284pfa.76.1535681540524; Thu, 30 Aug 2018 19:12:20 -0700 (PDT) Received: from [10.198.0.186] ([64.64.108.241]) by smtp.gmail.com with ESMTPSA id m27-v6sm6349882pff.152.2018.08.30.19.12.10 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 30 Aug 2018 19:12:19 -0700 (PDT) To: Leif Lindholm Cc: linaro-uefi@lists.linaro.org, edk2-devel@lists.01.org, graeme.gregory@linaro.org, ard.biesheuvel@linaro.org, michael.d.kinney@intel.com, lersek@redhat.com, guoheyi@huawei.com, wanghuiqiang@huawei.com, huangming23@huawei.com, zhangjinsong2@huawei.com, huangdaode@hisilicon.com, john.garry@huawei.com, xinliang.liu@linaro.org References: <20180823160743.45638-1-ming.huang@linaro.org> <20180823160743.45638-12-ming.huang@linaro.org> <20180830183940.4uynhkgd4h5qudvw@bivouac.eciton.net> From: Ming Message-ID: Date: Fri, 31 Aug 2018 10:12:03 +0800 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:60.0) Gecko/20100101 Thunderbird/60.0 MIME-Version: 1.0 In-Reply-To: <20180830183940.4uynhkgd4h5qudvw@bivouac.eciton.net> Subject: Re: [PATCH edk2-platforms v4 11/31] Silicon/Hisilicon/Acpi: Unify HisiAcpiPlatformDxe X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 31 Aug 2018 02:12:21 -0000 Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit On 8/31/2018 2:39 AM, Leif Lindholm wrote: > On Fri, Aug 24, 2018 at 12:07:23AM +0800, Ming Huang wrote: >> The EFI_ACPI_STATIC_RESOURCE_AFFINITY_TABLE struct is used by >> UpdateAcpiTable.c and Srat aslc. The struct may be different >> according to chips, so move some macro to PlatformArch.h. >> >> Contributed-under: TianoCore Contribution Agreement 1.1 >> Signed-off-by: Ming Huang >> Reviewed-by: Leif Lindholm > > Right, so I missed one bit on this last time around. > Could you leave changes to > Silicon/Hisilicon/Hi1620/Include/PlatformArch.h out here and just add > that in the initial d06 patch? > > Then, could you move this patch immediately after "Move RAS macro to > PlatformArch"? OK, do it in v5. > > / > Leif > >> --- >> Silicon/Hisilicon/Hi1610/Include/PlatformArch.h | 6 ++++ >> Silicon/Hisilicon/Hi1620/Include/PlatformArch.h | 6 ++++ >> Silicon/Hisilicon/Include/Library/AcpiNextLib.h | 31 ++++++++++++++------ >> Silicon/Hisilicon/Drivers/HisiAcpiPlatformDxe/UpdateAcpiTable.c | 2 -- >> 4 files changed, 34 insertions(+), 11 deletions(-) >> >> diff --git a/Silicon/Hisilicon/Hi1610/Include/PlatformArch.h b/Silicon/Hisilicon/Hi1610/Include/PlatformArch.h >> index f39ae0748c..1ebddca4e5 100644 >> --- a/Silicon/Hisilicon/Hi1610/Include/PlatformArch.h >> +++ b/Silicon/Hisilicon/Hi1610/Include/PlatformArch.h >> @@ -30,6 +30,12 @@ >> // Max NUMA node number for each node type >> #define MAX_NUM_PER_TYPE 8 >> >> +// for acpi >> +#define NODE_IN_SOCKET 2 >> +#define CORE_NUM_PER_SOCKET 32 >> +#define EFI_ACPI_MEMORY_AFFINITY_STRUCTURE_COUNT 10 >> +#define EFI_ACPI_6_2_ITS_AFFINITY_STRUCTURE_COUNT 8 >> + >> #define S1_BASE 0x40000000000 >> >> #define RASC_BASE (0x5000) >> diff --git a/Silicon/Hisilicon/Hi1620/Include/PlatformArch.h b/Silicon/Hisilicon/Hi1620/Include/PlatformArch.h >> index 9539cfdada..f3ad45f6c6 100644 >> --- a/Silicon/Hisilicon/Hi1620/Include/PlatformArch.h >> +++ b/Silicon/Hisilicon/Hi1620/Include/PlatformArch.h >> @@ -57,5 +57,11 @@ >> EFI_ACPI_ARM_CREATOR_REVISION /* UINT32 CreatorRevision */ \ >> } >> >> +// for acpi >> +#define NODE_IN_SOCKET 2 >> +#define CORE_NUM_PER_SOCKET 48 >> +#define EFI_ACPI_MEMORY_AFFINITY_STRUCTURE_COUNT 16 >> +#define EFI_ACPI_6_2_ITS_AFFINITY_STRUCTURE_COUNT 1 >> + >> #endif >> >> diff --git a/Silicon/Hisilicon/Include/Library/AcpiNextLib.h b/Silicon/Hisilicon/Include/Library/AcpiNextLib.h >> index fd05a3b960..2abffb65fc 100644 >> --- a/Silicon/Hisilicon/Include/Library/AcpiNextLib.h >> +++ b/Silicon/Hisilicon/Include/Library/AcpiNextLib.h >> @@ -19,6 +19,21 @@ >> #ifndef __ACPI_NEXT_LIB_H__ >> #define __ACPI_NEXT_LIB_H__ >> >> +#include >> + >> +/// >> +/// ITS Affinity Structure Definition >> +/// >> +#pragma pack(1) >> +typedef struct { >> + UINT8 Type; >> + UINT8 Length; >> + UINT32 ProximityDomain; >> + UINT16 Reserved; >> + UINT32 ItsHwId; >> +} EFI_ACPI_6_2_ITS_AFFINITY_STRUCTURE; >> +#pragma pack() >> + >> #define EFI_ACPI_6_1_GIC_ITS_INIT(GicITSHwId, GicITSBase) \ >> { \ >> EFI_ACPI_6_1_GIC_ITS, sizeof (EFI_ACPI_6_1_GIC_ITS_STRUCTURE), EFI_ACPI_RESERVED_WORD, \ >> @@ -42,8 +57,8 @@ >> #define EFI_ACPI_6_2_ITS_AFFINITY_STRUCTURE_INIT( \ >> ProximityDomain, ItsId) \ >> { \ >> - 4, sizeof (EFI_ACPI_6_2_GIC_ITS_AFFINITY_STRUCTURE), ProximityDomain, \ >> - {EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE}, ItsId \ >> + 4, sizeof (EFI_ACPI_6_2_ITS_AFFINITY_STRUCTURE), ProximityDomain, \ >> + EFI_ACPI_RESERVED_WORD, ItsId \ >> } >> >> #define EFI_ACPI_6_1_MEMORY_AFFINITY_STRUCTURE_INIT( \ >> @@ -75,15 +90,13 @@ >> // Define the number of each table type. >> // This is where the table layout is modified. >> // >> -#define EFI_ACPI_PROCESSOR_LOCAL_GICC_AFFINITY_STRUCTURE_COUNT 64 >> -#define EFI_ACPI_MEMORY_AFFINITY_STRUCTURE_COUNT 10 >> -#define EFI_ACPI_6_2_ITS_AFFINITY_STRUCTURE_COUNT 8 >> +#define EFI_ACPI_PROCESSOR_LOCAL_GICC_AFFINITY_STRUCTURE_COUNT (MAX_SOCKET*CORE_NUM_PER_SOCKET) >> >> typedef struct { >> - EFI_ACPI_6_0_SYSTEM_RESOURCE_AFFINITY_TABLE_HEADER Header; >> - EFI_ACPI_6_0_MEMORY_AFFINITY_STRUCTURE Memory[EFI_ACPI_MEMORY_AFFINITY_STRUCTURE_COUNT]; >> - EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE Gicc[EFI_ACPI_PROCESSOR_LOCAL_GICC_AFFINITY_STRUCTURE_COUNT]; >> - EFI_ACPI_6_2_GIC_ITS_AFFINITY_STRUCTURE Its[EFI_ACPI_6_2_ITS_AFFINITY_STRUCTURE_COUNT]; >> + EFI_ACPI_6_2_SYSTEM_RESOURCE_AFFINITY_TABLE_HEADER Header; >> + EFI_ACPI_6_2_MEMORY_AFFINITY_STRUCTURE Memory[EFI_ACPI_MEMORY_AFFINITY_STRUCTURE_COUNT]; >> + EFI_ACPI_6_2_GICC_AFFINITY_STRUCTURE Gicc[EFI_ACPI_PROCESSOR_LOCAL_GICC_AFFINITY_STRUCTURE_COUNT]; >> + EFI_ACPI_6_2_ITS_AFFINITY_STRUCTURE Its[EFI_ACPI_6_2_ITS_AFFINITY_STRUCTURE_COUNT]; >> } EFI_ACPI_STATIC_RESOURCE_AFFINITY_TABLE; >> >> #pragma pack() >> diff --git a/Silicon/Hisilicon/Drivers/HisiAcpiPlatformDxe/UpdateAcpiTable.c b/Silicon/Hisilicon/Drivers/HisiAcpiPlatformDxe/UpdateAcpiTable.c >> index f5869841dc..54f49977c3 100644 >> --- a/Silicon/Hisilicon/Drivers/HisiAcpiPlatformDxe/UpdateAcpiTable.c >> +++ b/Silicon/Hisilicon/Drivers/HisiAcpiPlatformDxe/UpdateAcpiTable.c >> @@ -20,8 +20,6 @@ >> #include >> #include >> >> -#define CORE_NUM_PER_SOCKET 32 >> -#define NODE_IN_SOCKET 2 >> #define CORECOUNT(X) ((X) * CORE_NUM_PER_SOCKET) >> >> STATIC >> -- >> 2.18.0 >>