From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mx.groups.io with SMTP id smtpd.web11.9925.1590140395577171962 for ; Fri, 22 May 2020 02:39:55 -0700 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: arm.com, ip: 217.140.110.172, mailfrom: ard.biesheuvel@arm.com) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 16FFD30E; Fri, 22 May 2020 02:39:55 -0700 (PDT) Received: from [192.168.1.81] (unknown [10.37.8.250]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id E6D0F3F305; Fri, 22 May 2020 02:39:51 -0700 (PDT) Subject: Re: [PATCH edk2-platforms 12/16] Silicon/NXP: PciSegmentLib: LsGen4Ctrl: Add Workaround for A-011264 To: Wasim Khan , devel@edk2.groups.io, meenakshi.aggarwal@nxp.com, vabhav.sharma@nxp.com, V.Sethi@nxp.com, leif@nuviainc.com, jon@solid-run.com Cc: Wasim Khan References: <1590102139-16588-1-git-send-email-wasim.khan@oss.nxp.com> <1590102139-16588-13-git-send-email-wasim.khan@oss.nxp.com> From: "Ard Biesheuvel" Message-ID: Date: Fri, 22 May 2020 11:39:48 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.7.0 MIME-Version: 1.0 In-Reply-To: <1590102139-16588-13-git-send-email-wasim.khan@oss.nxp.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: quoted-printable On 5/22/20 1:02 AM, Wasim Khan wrote: > From: Wasim Khan >=20 > With PCIe LsGen4 controller, clearing the Bus Master Enable bit in > Command register blocks all outbound transactions to be sent out > in RC mode. >=20 > According to PCI Express base specification, the Command register=E2=80= =99s > Bus Master Enable bit of a PCI Express RC controller can only > control the forwarding of memory requests received at its root port > in the upstream direction. In other words, clearing the Bus Master > Enable bit must not block all outbound transactions to be sent out > toward RC=E2=80=99s downstream devices. Due to this erratum, when the > Command register=E2=80=99s Bus Master Enable bit is cleared, all the ou= tbound > transactions from the device=E2=80=99s internal bus masters, including = but > not limited to configuration read and write transactions, are > terminated with the slave error (SLVERR) response status on the PCI > Express RC controller=E2=80=99s internal AXI bus interface. >=20 > Signed-off-by: Wasim Khan > --- > Silicon/NXP/Library/PciSegmentLib/PciSegmentLib.c | 17 ++++++++++++++= +++ > 1 file changed, 17 insertions(+) >=20 > diff --git a/Silicon/NXP/Library/PciSegmentLib/PciSegmentLib.c b/Silico= n/NXP/Library/PciSegmentLib/PciSegmentLib.c > index 02a1525ef308..c3bc14820ea5 100755 > --- a/Silicon/NXP/Library/PciSegmentLib/PciSegmentLib.c > +++ b/Silicon/NXP/Library/PciSegmentLib/PciSegmentLib.c > @@ -39,6 +39,21 @@ static BOOLEAN PciLsGen4Ctrl; > =20 > STATIC > VOID > +PciLsGen4SetBusMaster ( > + IN EFI_PHYSICAL_ADDRESS Dbi > + ) > +{ > + UINT32 Val; > + > + /* Make sure the Master Enable bit not cleared */ Please use // style comments > + Val =3D PciLsGen4Read32 ((UINTN)Dbi, PCI_COMMAND_OFFSET); > + if (!(Val & EFI_PCI_COMMAND_BUS_MASTER)) { > + PciLsGen4Write32 ((UINTN)Dbi, PCI_COMMAND_OFFSET, Val | EFI_PCI_CO= MMAND_BUS_MASTER); > + } > +} > + > +STATIC > +VOID > PcieCfgSetTarget ( > IN EFI_PHYSICAL_ADDRESS Dbi, > IN UINT32 Target) > @@ -71,6 +86,8 @@ PciLsGen4GetConfigBase ( > UINT32 Target; > =20 > if (Bus) { > + PciLsGen4SetBusMaster (PCI_SEG0_DBI_BASE + PCI_DBI_SIZE_DIFF* Segm= ent); > + Can't we just set this once and never touch it? Or is that tricky? > Target =3D ((((Address >> 20) & 0xFF) << 24) | > (((Address >> 15) & 0x1F) << 19) | > (((Address >> 12) & 0x7) << 16)); >=20