From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from us-smtp-delivery-1.mimecast.com (us-smtp-delivery-1.mimecast.com [207.211.31.81]) by mx.groups.io with SMTP id smtpd.web10.1959.1589231514242026287 for ; Mon, 11 May 2020 14:11:54 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@redhat.com header.s=mimecast20190719 header.b=D+8SnYnr; spf=pass (domain: redhat.com, ip: 207.211.31.81, mailfrom: philmd@redhat.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1589231513; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Vs1S/ub4zhJZV4e+MvPbkSRY2Hq8h7kp1a78mm6HM30=; b=D+8SnYnrjha2Gc/m2o101wvzaSBB28pXjw5Q8LpdfYMf8DFdwjr44epN6MXxkiRJXvh/1N ksDGj+NBkSw5kLDblAxEFtjSaQHrJxF4a3jxUg5UdzkVU2p8196Wrgnb0UMHgvi8EtUQf4 zdtLbZ9xDJbYj8lda9cj1yQGJapPJxA= Received: from mail-wr1-f72.google.com (mail-wr1-f72.google.com [209.85.221.72]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-465-q8-luYz8NoKAvYYZVNSskQ-1; Mon, 11 May 2020 17:11:51 -0400 X-MC-Unique: q8-luYz8NoKAvYYZVNSskQ-1 Received: by mail-wr1-f72.google.com with SMTP id f2so5842563wrm.9 for ; Mon, 11 May 2020 14:11:51 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=Vs1S/ub4zhJZV4e+MvPbkSRY2Hq8h7kp1a78mm6HM30=; b=kQO+MXv6hpsGkiGK9bTpHXVFZhC/c3ChG9m3HVgSBaRO3ZygQ5hoHwbu4fC2/5wF0+ j4giVyFMYZBl/mJ5FWISWVFt8dAsHDC2QIknFC24QLybFYvY5XsDozly8V158lu+qGXC A0y6FtpulM45zlFteoscURxmoVm/fQ9eMMM/9xLmhWKs63gXSqg6CQ1M7BAlz0za4ad0 foaQGaAR7mkytsUWaRSAg80vowNpXuU+2onMSRc2F/TkftNA25ihb/20ZhT8IGuOCPEh zA5wclBr6zr+a3ContBXSqAoPG+NN1Vzo8E9ND9IOtRn6e0Uf1Wyt8et9r4Pu2WgZB5N jw/g== X-Gm-Message-State: AGi0PuYC/3FFeUC67MaYQv/LerF5DmgRXkjGh79e2mL1ckW+mqvGpiRb i4dQQWpV3zGO21XQzEUu3T7rRo6rcq09ALkzWeNHn0WC4qPRFHNbTWkhtjmpHxr5b0ThOCQ22hx BkkyzS285HqJ6cw== X-Received: by 2002:a5d:4102:: with SMTP id l2mr20533144wrp.51.1589231510733; Mon, 11 May 2020 14:11:50 -0700 (PDT) X-Google-Smtp-Source: APiQypLeo0EH4sTeb6oNQPLtYuiXQaeh5FQem9RNxEehGJNCFIHl3o1YOuZfOJd7H/RBgrEgO1oRLw== X-Received: by 2002:a5d:4102:: with SMTP id l2mr20533117wrp.51.1589231510507; Mon, 11 May 2020 14:11:50 -0700 (PDT) Return-Path: Received: from [192.168.1.37] (17.red-88-21-202.staticip.rima-tde.net. [88.21.202.17]) by smtp.gmail.com with ESMTPSA id 2sm19205913wre.25.2020.05.11.14.11.49 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 11 May 2020 14:11:49 -0700 (PDT) Subject: Re: [edk2-devel] [PATCH edk2-platforms v4 7/9] Silicon/Broadcom/BcmGenetDxe: use MemoryFence() for MMIO write ordering To: devel@edk2.groups.io, ard.biesheuvel@arm.com Cc: Pete Batard , Jared McNeill , Andrei Warkentin , Samer El-Haj-Mahmoud , Jeremy Linton References: <20200511145527.23453-1-ard.biesheuvel@arm.com> <20200511145527.23453-8-ard.biesheuvel@arm.com> From: =?UTF-8?B?UGhpbGlwcGUgTWF0aGlldS1EYXVkw6k=?= Message-ID: Date: Mon, 11 May 2020 23:11:48 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.5.0 MIME-Version: 1.0 In-Reply-To: <20200511145527.23453-8-ard.biesheuvel@arm.com> X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Language: en-US Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit On 5/11/20 4:55 PM, Ard Biesheuvel wrote: > ARM synchronization barriers can be used to stall execution and wait > for cache or TLB maintenance to complete. TLB maintenance is irrelevant > in the context of the GENET driver, but cache maintenance is important > for non-cache coherent DMA, and synchronization barriers are needed to > ensure that outgoing data is cleaned before starting DMA for TX frames. > > However, this cache maintenance is already taken care of by the cache > maintenance routines, and so all we need to do in our I/O routines is > ensure that MMIO writes are issued in the right order, and for this, > an ordinary MemoryFence () is sufficient. > > This means we don't need to depend on ArmLib either. > > Signed-off-by: Ard Biesheuvel Reviewed-by: Philippe Mathieu-Daude > --- > Silicon/Broadcom/Drivers/Net/BcmGenetDxe/BcmGenetDxe.inf | 2 -- > Silicon/Broadcom/Drivers/Net/BcmGenetDxe/DriverBinding.c | 1 - > Silicon/Broadcom/Drivers/Net/BcmGenetDxe/GenetUtil.c | 3 +-- > 3 files changed, 1 insertion(+), 5 deletions(-) > > diff --git a/Silicon/Broadcom/Drivers/Net/BcmGenetDxe/BcmGenetDxe.inf b/Silicon/Broadcom/Drivers/Net/BcmGenetDxe/BcmGenetDxe.inf > index 9b3dc5e62ecf..e3e4ebbddb93 100644 > --- a/Silicon/Broadcom/Drivers/Net/BcmGenetDxe/BcmGenetDxe.inf > +++ b/Silicon/Broadcom/Drivers/Net/BcmGenetDxe/BcmGenetDxe.inf > @@ -27,7 +27,6 @@ [Sources] > SimpleNetwork.c > > [Packages] > - ArmPkg/ArmPkg.dec > EmbeddedPkg/EmbeddedPkg.dec > MdeModulePkg/MdeModulePkg.dec > MdePkg/MdePkg.dec > @@ -35,7 +34,6 @@ [Packages] > Silicon/Broadcom/Drivers/Net/BcmNet.dec > > [LibraryClasses] > - ArmLib > BaseLib > BaseMemoryLib > DebugLib > diff --git a/Silicon/Broadcom/Drivers/Net/BcmGenetDxe/DriverBinding.c b/Silicon/Broadcom/Drivers/Net/BcmGenetDxe/DriverBinding.c > index 00fbfbc109bb..630a92ef210b 100644 > --- a/Silicon/Broadcom/Drivers/Net/BcmGenetDxe/DriverBinding.c > +++ b/Silicon/Broadcom/Drivers/Net/BcmGenetDxe/DriverBinding.c > @@ -9,7 +9,6 @@ > > **/ > > -#include > #include > #include > #include > diff --git a/Silicon/Broadcom/Drivers/Net/BcmGenetDxe/GenetUtil.c b/Silicon/Broadcom/Drivers/Net/BcmGenetDxe/GenetUtil.c > index 35a3c7abdf1e..e3ce8614aeb2 100644 > --- a/Silicon/Broadcom/Drivers/Net/BcmGenetDxe/GenetUtil.c > +++ b/Silicon/Broadcom/Drivers/Net/BcmGenetDxe/GenetUtil.c > @@ -8,7 +8,6 @@ > > #include "GenetUtil.h" > > -#include > #include > #include > #include > @@ -64,7 +63,7 @@ GenetMmioWrite ( > { > ASSERT ((Offset & 3) == 0); > > - ArmDataSynchronizationBarrier (); > + MemoryFence (); > MmioWrite32 (Genet->RegBase + Offset, Data); > } > >