From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by mx.groups.io with SMTP id smtpd.web11.17591.1646032955417624285 for ; Sun, 27 Feb 2022 23:23:05 -0800 Authentication-Results: mx.groups.io; dkim=fail reason="unable to parse pub key" header.i=@intel.com header.s=intel header.b=MukZWO4J; spf=pass (domain: intel.com, ip: 134.134.136.24, mailfrom: min.m.xu@intel.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1646032985; x=1677568985; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=b4sUMTfGW/e/w0ToDj478D/qg9at0oQsNJFi1kJGQXQ=; b=MukZWO4JXoiOFDaH9+LvvVTkjgyXydWTip1by1t/RWGKQrnj98JyFh+C FDVt2WMj89TB/X7V3bMpqxmfMx9RHBk/m+u7iifq3PEt1E+uz4thWgqfP 9HxKDY3TmJjZ9GbCGB3bamJiqhMM03VV8yJFV7D9UIgHN3+4oH9hyl2CO +oxZqvuTUuiESRr6coDkYkpE8Tz0yFEt+Cbto0AoD8l0z0qlE6eGUt8TM 4iz4WdatEO0mBA92mEIQZT0Roi8Of02AYrdxyZAgarNmyqbWvRYpt4xko +0nHuf3csZ7jq15XQkawRiQFWgsHbFO6j+XVGzRrYCg/HmUZMXPe/Kl1d A==; X-IronPort-AV: E=McAfee;i="6200,9189,10271"; a="252553202" X-IronPort-AV: E=Sophos;i="5.90,142,1643702400"; d="scan'208";a="252553202" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Feb 2022 23:23:05 -0800 X-IronPort-AV: E=Sophos;i="5.90,142,1643702400"; d="scan'208";a="534341423" Received: from mxu9-mobl1.ccr.corp.intel.com ([10.238.2.184]) by orsmga007-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Feb 2022 23:23:03 -0800 From: "Min Xu" To: devel@edk2.groups.io Cc: Min Xu , Jiewen Yao , Gerd Hoffmann , Anthony Perard , Julien Grall , Eric Dong , Ray Ni Subject: [PATCH V7 36/37] UefiCpuPkg: Setting initial-count register as the last step Date: Mon, 28 Feb 2022 15:21:08 +0800 Message-Id: X-Mailer: git-send-email 2.29.2.windows.2 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3711 Per SDM, changing the mode of APIC timer (from one-shot to periodic or vice versa) by writing to the timer LVT entry does not start the timer. To start the timer, it is necessary to write to the initial-count register. If initial-count is wrote before mode change, it's possible that timer expired before the mode change. Thus failing the periodic mode. Cc: Jiewen Yao Cc: Gerd Hoffmann Cc: Anthony Perard Cc: Julien Grall Cc: Eric Dong Cc: Ray Ni Acked-by: Gerd Hoffmann Signed-off-by: Min Xu --- .../Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c b/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c index 2d17177df12b..f26d9c93894f 100644 --- a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c +++ b/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c @@ -967,11 +967,6 @@ InitializeApicTimer ( // InitializeLocalApicSoftwareEnable (TRUE); - // - // Program init-count register. - // - WriteLocalApicReg (XAPIC_TIMER_INIT_COUNT_OFFSET, InitCount); - if (DivideValue != 0) { ASSERT (DivideValue <= 128); ASSERT (DivideValue == GetPowerOfTwo32 ((UINT32)DivideValue)); @@ -996,6 +991,11 @@ InitializeApicTimer ( LvtTimer.Bits.Mask = 0; LvtTimer.Bits.Vector = Vector; WriteLocalApicReg (XAPIC_LVT_TIMER_OFFSET, LvtTimer.Uint32); + + // + // Program init-count register. + // + WriteLocalApicReg (XAPIC_TIMER_INIT_COUNT_OFFSET, InitCount); } /** -- 2.29.2.windows.2