* [PATCH 2/2] add support bh720+emmc chip
[not found] <89a247208056d3f458a20e9f335d03d9f54c1c9a.1548669154.git.mike.li@bayhubtech.com>
@ 2019-01-29 1:47 ` Mike Li (WH)
0 siblings, 0 replies; only message in thread
From: Mike Li (WH) @ 2019-01-29 1:47 UTC (permalink / raw)
To: edk2-devel@lists.01.org
---
MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c | 147 ++++++++++++++----
.../Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c | 130 +++++++---------
2 files changed, 174 insertions(+), 103 deletions(-)
diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c
index 83e6bf0c90..4f38eca199 100644
--- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c
+++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c
@@ -319,9 +319,116 @@ SdCardSetRca (
return Status;
}
+/**
+ Send command SEND_CSD to the SD device to get the data of the CSD register.
+
+ Refer to SD Physical Layer Simplified Spec 4.1 Section 4.7 for details.
+
+ @param[in] PassThru A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL instance.
+ @param[in] Slot The slot number of the SD card to send the command to.
+ @param[in] Rca The relative device address of selected device.
+ @param[out] Csd The buffer to store the content of the CSD register.
+ Note the caller should ignore the lowest byte of this
+ buffer as the content of this byte is meaningless even
+ if the operation succeeds.
+
+ @retval EFI_SUCCESS The operation is done correctly.
+ @retval Others The operation fails.
+
+**/
+EFI_STATUS
+SdCardGetCsd (
+ IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru,
+ IN UINT8 Slot,
+ IN UINT16 Rca,
+ OUT SD_CSD *Csd
+ )
+{
+ EFI_SD_MMC_COMMAND_BLOCK SdMmcCmdBlk;
+ EFI_SD_MMC_STATUS_BLOCK SdMmcStatusBlk;
+ EFI_SD_MMC_PASS_THRU_COMMAND_PACKET Packet;
+ EFI_STATUS Status;
+
+ ZeroMem (&SdMmcCmdBlk, sizeof (SdMmcCmdBlk));
+ ZeroMem (&SdMmcStatusBlk, sizeof (SdMmcStatusBlk));
+ ZeroMem (&Packet, sizeof (Packet));
+ Packet.SdMmcCmdBlk = &SdMmcCmdBlk;
+ Packet.SdMmcStatusBlk = &SdMmcStatusBlk;
+ Packet.Timeout = SD_MMC_HC_GENERIC_TIMEOUT;
+ SdMmcCmdBlk.CommandIndex = SD_SEND_CSD;
+ SdMmcCmdBlk.CommandType = SdMmcCommandTypeAc;
+ SdMmcCmdBlk.ResponseType = SdMmcResponseTypeR2;
+ SdMmcCmdBlk.CommandArgument = (UINT32)Rca << 16;
+ Status = SdMmcPassThruPassThru (PassThru, Slot, &Packet, NULL);
+ if (!EFI_ERROR (Status)) {
+ //
+ // For details, refer to SD Host Controller Simplified Spec 3.0 Table 2-12.
+ //
+ CopyMem (((UINT8*)Csd) + 1, &SdMmcStatusBlk.Resp0, sizeof (SD_CSD) - 1);
+ }
+
+ return Status;
+}
+
+/**
+ Send command SEND_CSD to the SD device to get the data of the CSD register.
+
+ Refer to SD Physical Layer Simplified Spec 4.1 Section 4.7 for details.
+
+ @param[in] PassThru A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL instance.
+ @param[in] Slot The slot number of the SD card to send the command to.
+ @param[in] Rca The relative device address of selected device.
+ @param[out] Scr The buffer to store the content of the SCR register.
+
+ @retval EFI_SUCCESS The operation is done correctly.
+ @retval Others The operation fails.
+
+**/
+EFI_STATUS
+SdCardGetScr (
+ IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru,
+ IN UINT8 Slot,
+ IN UINT16 Rca,
+ OUT SD_SCR *Scr
+ )
+{
+ EFI_SD_MMC_COMMAND_BLOCK SdMmcCmdBlk;
+ EFI_SD_MMC_STATUS_BLOCK SdMmcStatusBlk;
+ EFI_SD_MMC_PASS_THRU_COMMAND_PACKET Packet;
+ EFI_STATUS Status;
+
+ ZeroMem (&SdMmcCmdBlk, sizeof (SdMmcCmdBlk));
+ ZeroMem (&SdMmcStatusBlk, sizeof (SdMmcStatusBlk));
+ ZeroMem (&Packet, sizeof (Packet));
+
+ Packet.SdMmcCmdBlk = &SdMmcCmdBlk;
+ Packet.SdMmcStatusBlk = &SdMmcStatusBlk;
+ Packet.Timeout = SD_MMC_HC_GENERIC_TIMEOUT;
+
+ SdMmcCmdBlk.CommandIndex = SD_APP_CMD;
+ SdMmcCmdBlk.CommandType = SdMmcCommandTypeAc;
+ SdMmcCmdBlk.ResponseType = SdMmcResponseTypeR1;
+ SdMmcCmdBlk.CommandArgument = (UINT32)Rca << 16;
+
+ Status = SdMmcPassThruPassThru (PassThru, Slot, &Packet, NULL);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ SdMmcCmdBlk.CommandIndex = SD_SEND_SCR;
+ SdMmcCmdBlk.CommandType = SdMmcCommandTypeAdtc;
+ SdMmcCmdBlk.ResponseType = SdMmcResponseTypeR1;
+
+ Packet.InDataBuffer = Scr;
+ Packet.InTransferLength = sizeof (SD_SCR);
+
+ Status = SdMmcPassThruPassThru (PassThru, Slot, &Packet, NULL);
+
+ return Status;
+}
/**
Send command SELECT_DESELECT_CARD to the SD device to select/deselect it.
@@ -785,8 +892,8 @@ SdCardSetBusMode (
UINT8 BusWidth;
UINT8 AccessMode;
UINT8 HostCtrl1;
+ UINT8 HostCtrl2;
UINT8 SwitchResp[64];
- SD_MMC_BUS_MODE Timing;
SD_MMC_HC_PRIVATE_DATA *Private;
Private = SD_MMC_HC_PRIVATE_FROM_THIS (PassThru);
@@ -818,23 +925,18 @@ SdCardSetBusMode (
if (S18A && (Capability->Sdr104 != 0) && ((SwitchResp[13] & BIT3) != 0)) {
ClockFreq = 208;
AccessMode = 3;
- Timing = SdMmcUhsSdr104;
} else if (S18A && (Capability->Sdr50 != 0) && ((SwitchResp[13] & BIT2) != 0)) {
ClockFreq = 100;
AccessMode = 2;
- Timing = SdMmcUhsSdr50;
} else if (S18A && (Capability->Ddr50 != 0) && ((SwitchResp[13] & BIT4) != 0)) {
ClockFreq = 50;
AccessMode = 4;
- Timing = SdMmcUhsDdr50;
} else if ((SwitchResp[13] & BIT1) != 0) {
ClockFreq = 50;
AccessMode = 1;
- Timing = SdMmcUhsSdr25;
} else {
ClockFreq = 25;
AccessMode = 0;
- Timing = SdMmcUhsSdr12;
}
Status = SdCardSwitch (PassThru, Slot, AccessMode, 0xF, 0xF, 0xF, TRUE, SwitchResp);
@@ -860,32 +962,20 @@ SdCardSetBusMode (
}
}
- Status = SdMmcHcUhsSignaling (Private->ControllerHandle, PciIo, Slot, Timing);
+ HostCtrl2 = (UINT8)~0x7;
+ Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
if (EFI_ERROR (Status)) {
return Status;
}
-
- Status = SdMmcHcClockSupply (PciIo, Slot, ClockFreq * 1000, Private->BaseClkFreq[Slot], Private->ControllerVersion[Slot]);
+ HostCtrl2 = AccessMode;
+ Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
if (EFI_ERROR (Status)) {
return Status;
}
- if (mOverride != NULL && mOverride->NotifyPhase != NULL) {
- Status = mOverride->NotifyPhase (
- Private->ControllerHandle,
- Slot,
- EdkiiSdMmcSwitchClockFreqPost,
- &Timing
- );
- if (EFI_ERROR (Status)) {
- DEBUG ((
- DEBUG_ERROR,
- "%a: SD/MMC switch clock freq post notifier callback failed - %r\n",
- __FUNCTION__,
- Status
- ));
- return Status;
- }
+ Status = SdMmcHcClockSupply (PciIo, Slot, ClockFreq * 1000, *Capability);
+ if (EFI_ERROR (Status)) {
+ return Status;
}
if ((AccessMode == 3) || ((AccessMode == 2) && (Capability->TuningSDR50 != 0))) {
@@ -996,10 +1086,9 @@ SdCardIdentification (
return Status;
}
- if (((ControllerVer & 0xFF) >= SD_MMC_HC_CTRL_VER_300) &&
- ((ControllerVer & 0xFF) <= SD_MMC_HC_CTRL_VER_420)) {
+ if (((ControllerVer & 0xFF) == 2) || ((ControllerVer & 0xFF) == 3)) {
S18r = TRUE;
- } else if (((ControllerVer & 0xFF) == SD_MMC_HC_CTRL_VER_100) || ((ControllerVer & 0xFF) == SD_MMC_HC_CTRL_VER_200)) {
+ } else if (((ControllerVer & 0xFF) == 0) || ((ControllerVer & 0xFF) == 1)) {
S18r = FALSE;
} else {
ASSERT (FALSE);
@@ -1065,7 +1154,7 @@ SdCardIdentification (
goto Error;
}
- SdMmcHcInitClockFreq (PciIo, Slot, Private->BaseClkFreq[Slot], Private->ControllerVersion[Slot]);
+ SdMmcHcInitClockFreq (PciIo, Slot, Private->Capability[Slot]);
gBS->Stall (1000);
diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c
index 76c32a4dcd..9f635cba78 100644
--- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c
+++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c
@@ -4,7 +4,6 @@
It would expose EFI_SD_MMC_PASS_THRU_PROTOCOL for upper layer use.
- Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
@@ -18,8 +17,6 @@
#include "SdMmcPciHcDxe.h"
-EDKII_SD_MMC_OVERRIDE *mOverride;
-
//
// Driver Global Variables
//
@@ -63,9 +60,7 @@ SD_MMC_HC_PRIVATE_DATA gSdMmcPciHcTemplate = {
{ // MaxCurrent
0,
},
- {
- 0 // ControllerVersion
- }
+ 0 // ControllerVersion
};
SD_DEVICE_PATH mSdDpTemplate = {
@@ -286,14 +281,14 @@ SdMmcPciHcEnumerateDevice (
//
// Reset the specified slot of the SD/MMC Pci Host Controller
//
- Status = SdMmcHcReset (Private, Slot);
+ Status = SdMmcHcReset (Private->PciIo, Slot);
if (EFI_ERROR (Status)) {
continue;
}
//
// Reinitialize slot and restart identification process for the new attached device
//
- Status = SdMmcHcInitHost (Private, Slot);
+ Status = SdMmcHcInitHost (Private->PciIo, Slot, Private->Capability[Slot]);
if (EFI_ERROR (Status)) {
continue;
}
@@ -314,6 +309,8 @@ SdMmcPciHcEnumerateDevice (
// This card doesn't get initialized correctly.
//
if (Index == RoutineNum) {
+
+
Private->Slot[Slot].Initialized = FALSE;
}
@@ -533,6 +530,8 @@ SdMmcPciHcDriverBindingStart (
UINT32 RoutineNum;
BOOLEAN MediaPresent;
BOOLEAN Support64BitDma;
+ UINT16 IntStatus;
+ UINT32 value;
DEBUG ((DEBUG_INFO, "SdMmcPciHcDriverBindingStart: Start\n"));
@@ -606,68 +605,17 @@ SdMmcPciHcDriverBindingStart (
goto Done;
}
- //
- // Attempt to locate the singleton instance of the SD/MMC override protocol,
- // which implements platform specific workarounds for non-standard SDHCI
- // implementations.
- //
- if (mOverride == NULL) {
- Status = gBS->LocateProtocol (&gEdkiiSdMmcOverrideProtocolGuid, NULL,
- (VOID **)&mOverride);
- if (!EFI_ERROR (Status)) {
- DEBUG ((DEBUG_INFO, "%a: found SD/MMC override protocol\n",
- __FUNCTION__));
- }
- }
-
Support64BitDma = TRUE;
for (Slot = FirstBar; Slot < (FirstBar + SlotNum); Slot++) {
Private->Slot[Slot].Enable = TRUE;
- //
- // Get SD/MMC Pci Host Controller Version
- //
- Status = SdMmcHcGetControllerVersion (PciIo, Slot, &Private->ControllerVersion[Slot]);
- if (EFI_ERROR (Status)) {
- continue;
- }
-
Status = SdMmcHcGetCapability (PciIo, Slot, &Private->Capability[Slot]);
if (EFI_ERROR (Status)) {
continue;
}
-
- Private->BaseClkFreq[Slot] = Private->Capability[Slot].BaseClkFreq;
-
- if (mOverride != NULL && mOverride->Capability != NULL) {
- Status = mOverride->Capability (
- Controller,
- Slot,
- &Private->Capability[Slot],
- &Private->BaseClkFreq[Slot]
- );
- if (EFI_ERROR (Status)) {
- DEBUG ((DEBUG_WARN, "%a: Failed to override capability - %r\n",
- __FUNCTION__, Status));
- continue;
- }
- }
DumpCapabilityReg (Slot, &Private->Capability[Slot]);
- DEBUG ((
- DEBUG_INFO,
- "Slot[%d] Base Clock Frequency: %dMHz\n",
- Slot,
- Private->BaseClkFreq[Slot]
- ));
- //
- // If any of the slots does not support 64b system bus
- // do not enable 64b DMA in the PCI layer.
- //
- if (Private->Capability[Slot].SysBus64V3 == 0 &&
- Private->Capability[Slot].SysBus64V4 == 0) {
- Support64BitDma = FALSE;
- }
+ Support64BitDma &= Private->Capability[Slot].SysBus64;
Status = SdMmcHcGetMaxCurrent (PciIo, Slot, &Private->MaxCurrent[Slot]);
if (EFI_ERROR (Status)) {
@@ -683,28 +631,22 @@ SdMmcPciHcDriverBindingStart (
//
// Reset the specified slot of the SD/MMC Pci Host Controller
//
- Status = SdMmcHcReset (Private, Slot);
+ Status = SdMmcHcReset (PciIo, Slot);
if (EFI_ERROR (Status)) {
continue;
}
//
// Check whether there is a SD/MMC card attached
//
- if (Private->Slot[Slot].SlotType == RemovableSlot) {
- Status = SdMmcHcCardDetect (PciIo, Slot, &MediaPresent);
- if (EFI_ERROR (Status) && (Status != EFI_MEDIA_CHANGED)) {
- continue;
- } else if (!MediaPresent) {
- DEBUG ((
- DEBUG_INFO,
- "SdMmcHcCardDetect: No device attached in Slot[%d]!!!\n",
- Slot
- ));
- continue;
- }
+ Status = SdMmcHcCardDetect (PciIo, Slot, &MediaPresent);
+ if (EFI_ERROR (Status) && (Status != EFI_MEDIA_CHANGED)) {
+ continue;
+ } else if (!MediaPresent) {
+ DEBUG ((DEBUG_INFO, "SdMmcHcCardDetect: No device attached in Slot[%d]!!!\n", Slot));
+ continue;
}
- Status = SdMmcHcInitHost (Private, Slot);
+ Status = SdMmcHcInitHost (PciIo, Slot, Private->Capability[Slot]);
if (EFI_ERROR (Status)) {
continue;
}
@@ -725,9 +667,49 @@ SdMmcPciHcDriverBindingStart (
// This card doesn't get initialized correctly.
//
if (Index == RoutineNum) {
+
+
+
Private->Slot[Slot].Initialized = FALSE;
}
+
}
+
+ if(BhtHostPciSupport(Private->PciIo)){
+
+ SdMmcHcRwMmio (Private->PciIo,0,0x110,TRUE,sizeof (value),&value);
+ DbgMsg(L"0x110: 0x%x\n",value);
+
+ SdMmcHcRwMmio (Private->PciIo,0,0x114,TRUE,sizeof (value),&value);
+ DbgMsg(L"0x114: 0x%x\n",value);
+
+ SdMmcHcRwMmio (Private->PciIo,0,0x1a8,TRUE,sizeof (value),&value);
+ DbgMsg(L"MEM 1A8: 0x%x\n",value);
+ SdMmcHcRwMmio (Private->PciIo,0,0x1ac,TRUE,sizeof (value),&value);
+ DbgMsg(L"MEM 1AC: 0x%x\n",value);
+ SdMmcHcRwMmio (Private->PciIo,0,0x1B0,TRUE,sizeof (value),&value);
+ DbgMsg(L"MEM 1B0: 0x%x\n",value);
+
+ DbgMsg(L" - pcr 0x304 = 0x%08x\n", PciBhtRead32(Private->PciIo, 0x304));
+ DbgMsg(L" - pcr 0x328 = 0x%08x\n", PciBhtRead32(Private->PciIo, 0x328));
+ DbgMsg(L" - pcr 0x3e4 = 0x%08x\n", PciBhtRead32(Private->PciIo, 0x3e4));
+
+ SdMmcHcRwMmio (Private->PciIo,0,0x040,TRUE,sizeof (value),&value);
+ DbgMsg(L"0x40: 0x%x\n",value);
+
+ SdMmcHcRwMmio (Private->PciIo,0,SD_MMC_HC_PRESENT_STATE,TRUE,sizeof (value),&value);
+ DbgMsg(L"Present State: 0x%x\n",value);
+ SdMmcHcRwMmio (Private->PciIo,0,SD_MMC_HC_HOST_CTRL1,TRUE,sizeof (IntStatus),&IntStatus);
+ DbgMsg(L"Power&Host1: 0x%x\n",IntStatus);
+ SdMmcHcRwMmio (Private->PciIo,0,SD_MMC_HC_CLOCK_CTRL,TRUE,sizeof (IntStatus),&IntStatus);
+ DbgMsg(L"CLK: 0x%x\n",IntStatus);
+ SdMmcHcRwMmio (Private->PciIo,0,SD_MMC_HC_TIMEOUT_CTRL,TRUE,sizeof (IntStatus),&IntStatus);
+ DbgMsg(L"SWR&Timeout: 0x%x\n",IntStatus);
+ SdMmcHcRwMmio (Private->PciIo,0,SD_MMC_HC_NOR_INT_STS,TRUE,sizeof (value),&value);
+ DbgMsg(L"INR&IER: 0x%x\n",value);
+ SdMmcHcRwMmio (Private->PciIo,0,SD_MMC_HC_HOST_CTRL2,TRUE,sizeof (IntStatus),&IntStatus);
+ DbgMsg(L"Host2: 0x%x\n",IntStatus);
+ }
//
// Enable 64-bit DMA support in the PCI layer if this controller
--
2.19.1.windows.1
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2019-01-29 1:47 ` [PATCH 2/2] add support bh720+emmc chip Mike Li (WH)
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