From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.133.124]) by mx.groups.io with SMTP id smtpd.web10.34586.1683643613431598668 for ; Tue, 09 May 2023 07:46:53 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@redhat.com header.s=mimecast20190719 header.b=ifQssbDE; spf=pass (domain: redhat.com, ip: 170.10.133.124, mailfrom: kraxel@redhat.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1683643612; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=4rQCB7m3SIW14XNSickvj8wuxxR6I2yDnatWTqa3BKI=; b=ifQssbDEyVIHwYkW7iNuJMYrqBTeGmx7hocDyUb8DzkbQXxj/nhMlHlNGDayfd6Lj4oM9p 7ymIVAjzPSz4ltHvbvYQFSoVTsmwC2tRmlzH1e2Yg9O7wcCBOlJgH44vpBlzHfRJgO52nf 8s06lWjxnUWVGeize8obKc9zZgG65C8= Received: from mimecast-mx02.redhat.com (mx3-rdu2.redhat.com [66.187.233.73]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id us-mta-508-fgZwLlI3PK6XJ8qLH7fX7g-1; Tue, 09 May 2023 10:46:50 -0400 X-MC-Unique: fgZwLlI3PK6XJ8qLH7fX7g-1 Received: from smtp.corp.redhat.com (int-mx09.intmail.prod.int.rdu2.redhat.com [10.11.54.9]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id 3571E2A5954D; Tue, 9 May 2023 14:46:50 +0000 (UTC) Received: from sirius.home.kraxel.org (unknown [10.39.192.221]) by smtp.corp.redhat.com (Postfix) with ESMTPS id E1133492B00; Tue, 9 May 2023 14:46:49 +0000 (UTC) Received: by sirius.home.kraxel.org (Postfix, from userid 1000) id B78AA18000A6; Tue, 9 May 2023 16:46:48 +0200 (CEST) Date: Tue, 9 May 2023 16:46:48 +0200 From: "Gerd Hoffmann" To: devel@edk2.groups.io, jiaxin.wu@intel.com Subject: Re: [edk2-devel] [PATCH v1 0/3] Target to enable paging from temporary RAM Done Message-ID: References: <20230509102253.16632-1-jiaxin.wu@intel.com> MIME-Version: 1.0 In-Reply-To: <20230509102253.16632-1-jiaxin.wu@intel.com> X-Scanned-By: MIMEDefang 3.1 on 10.11.54.9 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Tue, May 09, 2023 at 06:22:50PM +0800, Wu, Jiaxin wrote: > For arch X64, system will enable the page table in SPI to cover 0-512G > range via CR4.PAE & MSR.LME & CR0.PG & CR3 setting. Existing code doesn't > cover the higher address access above 512G before memory-discovered > callback. This series patches provide the solution to enable paging from > temporary RAM Done. > > Jiaxin Wu (3): > UefiCpuPkg/SecCore: Migrate page table to permanent memory > UefiCpuPkg/CpuMpPei: Enable PAE page table if CR0.PG is not set > MdeModulePkg/DxeIpl: Align Page table Level setting with previous > level. Fails to build OvmfPkg/OvmfPkgX64.dsc Please run this through CI before sending out the patches. thanks, Gerd