From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.133.124]) by mx.groups.io with SMTP id smtpd.web11.5655.1681466701582770736 for ; Fri, 14 Apr 2023 03:05:01 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@redhat.com header.s=mimecast20190719 header.b=Pm4WpWhF; spf=pass (domain: redhat.com, ip: 170.10.133.124, mailfrom: kraxel@redhat.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1681466700; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=hB9qR8Hbam3TASU0qIhLEM70KeJgJQnMDaaIfQLnEIA=; b=Pm4WpWhFalCFCB08SDXQG4imTG1qGE5fYT5gbF8tmWNLmZZ+ztZrwZDiNGa4/bsjKCI6ig LnmyTXpTFOkmBSDwPLN0YjkHEnNG/aUw694ogl759wEU/jAJqdeuAz3YcUV8l5SwXpjelA 0XoGHW8ZJOLFKT+vP8U18/B61lDCglI= Received: from mimecast-mx02.redhat.com (mimecast-mx02.redhat.com [66.187.233.88]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id us-mta-534-yz6ikwOUMaSIgpQ0rJrPzA-1; Fri, 14 Apr 2023 06:04:55 -0400 X-MC-Unique: yz6ikwOUMaSIgpQ0rJrPzA-1 Received: from smtp.corp.redhat.com (int-mx05.intmail.prod.int.rdu2.redhat.com [10.11.54.5]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id 9588B855304; Fri, 14 Apr 2023 10:04:54 +0000 (UTC) Received: from sirius.home.kraxel.org (unknown [10.39.192.81]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 6D2A0BC88; Fri, 14 Apr 2023 10:04:54 +0000 (UTC) Received: by sirius.home.kraxel.org (Postfix, from userid 1000) id 4B98F1800081; Fri, 14 Apr 2023 12:04:53 +0200 (CEST) Date: Fri, 14 Apr 2023 12:04:53 +0200 From: "Gerd Hoffmann" To: devel@edk2.groups.io, zhiguang.liu@intel.com Cc: "Dong, Eric" , "Ni, Ray" , "Kumar, Rahul R" , "De, Debkumar" , "West, Catharine" Subject: Re: [edk2-devel] [PATCH 2/2] UefiCpuPkg: Support 5 level page table in ResetVector Message-ID: References: <20230403092814.1709-1-zhiguang.liu@intel.com> <2oe66me7kd474drxptj6rcjxh7bf25cnq7sunvrvtizgkfetyo@vmiqncl6r32b> MIME-Version: 1.0 In-Reply-To: X-Scanned-By: MIMEDefang 3.1 on 10.11.54.5 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=us-ascii Content-Disposition: inline > Using 5level paging when the below two conditions are both true: > 1. CPU support 5level paging > 2. Platform choose to use 5level paging. (by specifing macro USE_5_LEVEL_PAGE_TABLE) > > There is an assumption that if platform choose to use 5level paging, > then 5level paging should be supported by CPU. (Platform should know > its CPU capability) That assumption does not hold for virtual machines. OVMF builds with 5-level paging support enabled should continue to work on CPUs without 5-level paging support. > If Platform choose to use 4level paging at build time, we can save 4K space by not creating the 5 level page. I'm fine with that. But with 5-level paging enabled the reset vector should be able to fallback to 4-level paging in case the CPU does not support 5-level paging. take care, Gerd